diff --git a/bsp/boards/i2c.h b/bsp/boards/i2c.h index 24d2c0c516..0f5873aea9 100644 --- a/bsp/boards/i2c.h +++ b/bsp/boards/i2c.h @@ -24,6 +24,7 @@ //=========================== prototypes ====================================== void i2c_init(void); +void i2c_set_addr(uint8_t address); void i2c_read_registers(uint8_t bus_num,uint8_t slave_addr, uint8_t reg_addr, uint8_t numBytes, diff --git a/bsp/boards/nrf52840/adc_sensor.c b/bsp/boards/nrf52840/adc_sensor.c deleted file mode 100644 index 238addcc78..0000000000 --- a/bsp/boards/nrf52840/adc_sensor.c +++ /dev/null @@ -1,101 +0,0 @@ -/** - \brief Definition of the nrf52480 ADC driver. - \author Frank Senf , July 2018. -*/ - - -#include "sdk/components/boards/boards.h" -#include "nrf_drv_saadc.h" -#include "nrf_temp.h" - -#include "adc_sensor.h" - - -//=========================== defines ========================================= - -//=========================== typedef ========================================= - -//=========================== variables ======================================= - -//=========================== prototype ======================================= - -static void saadc_callback(nrf_drv_saadc_evt_t const* p_event); - - -//=========================== public ========================================== - -bool adc_sens_init(void) { - ret_code_t retVal; - - nrfx_saadc_config_t saadc_config = NRFX_SAADC_DEFAULT_CONFIG; - nrf_saadc_channel_config_t channel_config = NRF_DRV_SAADC_DEFAULT_CHANNEL_CONFIG_SE(SAADC_CH_PSELP_PSELP_VDD); - - retVal = nrf_drv_saadc_init(&saadc_config, saadc_callback); - if (NRFX_SUCCESS != retVal) { - return false; - } - - retVal = nrf_drv_saadc_channel_init(0, &channel_config); - if (NRFX_SUCCESS != retVal) { - nrf_drv_saadc_uninit(); - return false; - } - - retVal = nrfx_saadc_calibrate_offset(); - if (NRFX_SUCCESS != retVal) { - while (nrfx_saadc_is_busy()) {} - } - - nrf_temp_init(); - - return true; -} - -uint16_t adc_sens_read_battery(void) { - - nrf_saadc_value_t value = 0; - - nrf_drv_saadc_sample_convert(0, &value); - - return (uint16_t) value; -} - -float adc_sens_convert_battery(uint16_t raw) { - - float converted = raw; - - converted *= 600; // 0.6V internal reference - converted /= 1024; // 10 bit resolution - converted *= 6; // 1/6 prescaling - // in volts - converted /= 1000; - - return converted; -} - -uint16_t adc_sens_read_temperature(void) { - - int32_t cpu_temp_raw; - - NRF_TEMP->TASKS_START = 1; - while (NRF_TEMP->EVENTS_DATARDY==0) {} - NRF_TEMP->EVENTS_DATARDY = 0; - cpu_temp_raw = nrf_temp_read(); - NRF_TEMP->TASKS_STOP = 1; - - return cpu_temp_raw; -} - -float adc_sens_convert_temperature(uint16_t cpu_temp_raw) { - - float cpu_temp = cpu_temp_raw; - cpu_temp /= 4; - - return cpu_temp; -} - - -//=========================== private ========================================= - -static void saadc_callback(nrf_drv_saadc_evt_t const* p_event) { -} diff --git a/bsp/boards/nrf52840/app_config.h b/bsp/boards/nrf52840/app_config.h deleted file mode 100644 index 8301c7ad98..0000000000 --- a/bsp/boards/nrf52840/app_config.h +++ /dev/null @@ -1,63 +0,0 @@ -/** - * Author: Tamas Harczos (tamas.harczos@imms.de) - * Date: Apr 2018 - * Description: nRF52840-specific nRF52 SDK configuration definitions. - */ - -#ifndef BSP_NRF52480_SDK_CONFIG_H -#define BSP_NRF52480_SDK_CONFIG_H - -// clock -#define CLOCK_ENABLED 1 -// FIFO -#define APP_FIFO_ENABLED 1 - - -// UART -#define UART_ENABLED 1 -#define UART_EASY_DMA_SUPPORT 0 -#define UART0_ENABLED 1 -#define UART0_CONFIG_USE_EASY_DMA 0 -#define APP_UART_ENABLED 1 -#define APP_UART_DRIVER_INSTANCE 0 - -// SPI -#define SPI_ENABLED 1 // solely for legacy driver calls (if any) -#define SPI0_ENABLED 1 // solely for legacy driver calls (if any) -#define SPI0_USE_EASY_DMA 0 // solely for legacy driver calls (if any) -#define NRFX_SPI_ENABLED -#define NRFX_SPI0_ENABLED -#define NRFX_SPIM0_ENABLED - -// TWI (caution: uses same resources as SPI, so different instance is required) -#define TWI_ENABLED 1 // solely for legacy driver calls (if any) -#define TWI1_ENABLED 1 // solely for legacy driver calls (if any) -#define TWI1_USE_EASY_DMA 0 // solely for legacy driver calls (if any) -#define NRFX_TWI_ENABLED -#define NRFX_TWI1_ENABLED - -// SYSTICK -#define NRFX_SYSTICK_ENABLED 1 - -// sctimer -#define RTC_ENABLED 1 // solely for legacy driver calls (if any) -#define RTC0_ENABLED 1 // solely for legacy driver calls (if any) -#define NRFX_RTC_ENABLED 1 -#define NRFX_RTC0_ENABLED 1 - -// power management -#define NRF_PWR_MGMT_ENABLED 1 - -// ADC -#define SAADC_ENABLED 1 -#define NRFX_SAADC_ENABLED 1 - -// priorities -#define NRFX_RADIO_CONFIG_IRQ_PRIORITY 2 -#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY 2 -#define NRFX_SAADC_CONFIG_IRQ_PRIORITY 7 -#define NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#define NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#define NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY 7 - -#endif // BSP_NRF52480_SDK_CONFIG_H diff --git a/bsp/boards/nrf52840/board.c b/bsp/boards/nrf52840/board.c deleted file mode 100644 index eaa8f1f3a3..0000000000 --- a/bsp/boards/nrf52840/board.c +++ /dev/null @@ -1,137 +0,0 @@ -/** - * Author: Tamas Harczos (tamas.harczos@imms.de) - * Date: Apr 2018 - * Description: nRF52840-specific definition of the "board" bsp module. - */ - -#include "sdk/modules/nrfx/hal/nrf_power.h" -#include "sdk/components/libraries/pwr_mgmt/nrf_pwr_mgmt.h" -#include "sdk/integration/nrfx/legacy/nrf_drv_clock.h" -#include "sdk/components/libraries/delay/nrf_delay.h" - -#include "sdk/modules/nrfx/mdk/nrf52840.h" -#include "sdk/modules/nrfx/drivers/nrfx_common.h" -#include "sdk/modules/nrfx/drivers/include/nrfx_systick.h" -#include "sdk/components/libraries/util/nrf_assert.h" -#include "sdk/components/toolchain/cmsis/include/core_cm4.h" -#include "sdk/integration/nrfx/nrfx_glue.h" - -#include "sdk/components/boards/boards.h" - -#include "config.h" -#include "board.h" -#include "leds.h" -// #include "bsp_timer.h" ///< OBSOLETE, use sctimer instead -// #include "radiotimer.h" ///< OBSOLETE, use sctimer instead -#include "sctimer.h" -#include "debugpins.h" -#include "uart.h" -#include "radio.h" -#include "spi.h" -#include "radio.h" -#include "sensors.h" -#include "i2c.h" - - -//=========================== variables ======================================= - -//=========================== prototypes ====================================== - -static void button_init(void); - - -//=========================== main ============================================ - -extern int mote_main(void); - -int main(void) { - return mote_main(); -} - - -//=========================== public ========================================== - -void board_init(void) { - - // start low-frequency clock (LFCLK) - nrf_drv_clock_init(); - NRF_CLOCK->EVENTS_LFCLKSTARTED= 0; ///< part of workaround for 3.1 [20] RTC: Register values are invalid from http://infocenter.nordicsemi.com/pdf/nRF52840_Rev_1_Errata_v1.1.pdf - nrf_drv_clock_lfclk_request(NULL); - while (!nrf_drv_clock_lfclk_is_running()); - NRF_RTC0->TASKS_STOP= 0; ///< part of workaround for 3.1 [20] RTC: Register values are invalid from http://infocenter.nordicsemi.com/pdf/nRF52840_Rev_1_Errata_v1.1.pdf - - nrfx_systick_init(); - - leds_init(); - - // enable on-board DC-DC converter to reduce overall consumption (this also disables the LDO [low-dropout] regulator) - // This only works if the required coil and condenser are properly connected to the pins DCC and DEC4, which is the - // case with the development kit, but not with some other nRF52840-based boards. (If enabled without the proper - // circuitry, the CPU will hang.) - nrf_power_dcdcen_set(true); - nrf_power_dcdcen_vddh_set(true); - - // initialize power management library - nrf_pwr_mgmt_init(); - - // initialize board with LEDs and buttons - bsp_board_init(BSP_INIT_LEDS | BSP_INIT_BUTTONS); - button_init(); - - uart_init(); - - debugpins_init(); - - sctimer_init(); ///< bsp_timer_init() and radiotimer_init() were OBSOLETE, we use sctimer instead - - radio_init(); - - spi_init(); - - i2c_init(); - -#if BOARD_SENSORS_ENABLED - sensors_init(); -#endif -} - -/** - * Puts the board to sleep - */ -void board_sleep(void) { - nrf_pwr_mgmt_run(); - -/* - // @note: Below code could be an alternative without using the power management library - #ifdef __GNUC__ - static void __INLINE cpu_wfe(void) - #else - static void __forceinline cpu_wfe(void) - #endif - { - __WFE(); - __SEV(); - __WFE(); - } -*/ -} - -/** - * Resets the board - */ -void board_reset(void) { - NVIC_SystemReset(); -} - - -//=========================== private ========================================= - - -/** - * Configures the user button as input source - */ -static void button_init(void) -{ -} - -//=========================== interrupt handlers ============================== diff --git a/bsp/boards/nrf52840/debugpins.c b/bsp/boards/nrf52840/debugpins.c deleted file mode 100644 index 38f0c6d8ba..0000000000 --- a/bsp/boards/nrf52840/debugpins.c +++ /dev/null @@ -1,139 +0,0 @@ - /** - * Author: Tamas Harczos (tamas.harczos@imms.de) - * Date: Apr 2018 - * Description: nRF52840-specific definition of the "debugpins" bsp module. - */ - -#include "sdk/modules/nrfx/hal/nrf_gpio.h" - -#include "debugpins.h" -#include "stdint.h" -#include "board.h" -#include "board_info.h" - - -#ifndef DEBUG_PINS_DISABLED - - -//=========================== defines ========================================= - -// board debug PINS defines - -#if BOARD_PCA10056 // nrf52840-DK -#define GPIO_DEBUGPIN_FRAME 26 -#define GPIO_DEBUGPIN_SLOT 27 -#define GPIO_DEBUGPIN_FSM 29 -#define GPIO_DEBUGPIN_TASK 28 -#define GPIO_DEBUGPIN_ISR 30 -#define GPIO_DEBUGPIN_RADIO 31 -#endif -#if BOARD_PCA10059 // nrf52840-DONGLE -#define GPIO_DEBUGPIN_FRAME 9 -#define GPIO_DEBUGPIN_SLOT 10 -#define GPIO_DEBUGPIN_FSM 42 -#define GPIO_DEBUGPIN_TASK 31 -#define GPIO_DEBUGPIN_ISR 22 -#define GPIO_DEBUGPIN_RADIO 29 -#endif - -// the below defines are used to cycle through all pins -#define GPIO_NUM_DEBUGPINS 6 -#define GPIO_PINS_LIST { GPIO_DEBUGPIN_SLOT, GPIO_DEBUGPIN_FRAME, GPIO_DEBUGPIN_ISR, GPIO_DEBUGPIN_TASK, GPIO_DEBUGPIN_FSM, GPIO_DEBUGPIN_RADIO } - -//=========================== variables ======================================= - -//=========================== prototypes ====================================== - -//=========================== public ========================================== - -void debugpins_init(void) { - // set the corresponding GPIO pins to be used as output - const uint8_t m_board_gpio_debugpin_list[GPIO_NUM_DEBUGPINS] = GPIO_PINS_LIST; - - for (uint8_t p=0; p < GPIO_NUM_DEBUGPINS; ++p) { - nrf_gpio_cfg_output(m_board_gpio_debugpin_list[p]); - } -} - - -void debugpins_frame_set(void) { - nrf_gpio_pin_set(GPIO_DEBUGPIN_FRAME); -} - -void debugpins_frame_clr(void) { - nrf_gpio_pin_clear(GPIO_DEBUGPIN_FRAME); -} - -void debugpins_frame_toggle(void) { - nrf_gpio_pin_toggle(GPIO_DEBUGPIN_FRAME); -} - - -void debugpins_slot_set(void) { - nrf_gpio_pin_set(GPIO_DEBUGPIN_SLOT); -} - -void debugpins_slot_clr(void) { - nrf_gpio_pin_clear(GPIO_DEBUGPIN_SLOT); -} - -void debugpins_slot_toggle(void) { - nrf_gpio_pin_toggle(GPIO_DEBUGPIN_SLOT); -} - - -void debugpins_fsm_set(void) { - nrf_gpio_pin_set(GPIO_DEBUGPIN_FSM); -} - -void debugpins_fsm_clr(void) { - nrf_gpio_pin_clear(GPIO_DEBUGPIN_FSM); -} - -void debugpins_fsm_toggle(void) { - nrf_gpio_pin_toggle(GPIO_DEBUGPIN_FSM); -} - - -void debugpins_task_set(void) { - nrf_gpio_pin_set(GPIO_DEBUGPIN_TASK); -} - -void debugpins_task_clr(void) { - nrf_gpio_pin_clear(GPIO_DEBUGPIN_TASK); -} - -void debugpins_task_toggle(void) { - nrf_gpio_pin_toggle(GPIO_DEBUGPIN_TASK); -} - - -void debugpins_isr_set(void) { - nrf_gpio_pin_set(GPIO_DEBUGPIN_ISR); -} - -void debugpins_isr_clr(void) { - nrf_gpio_pin_clear(GPIO_DEBUGPIN_ISR); -} - -void debugpins_isr_toggle(void) { - nrf_gpio_pin_toggle(GPIO_DEBUGPIN_ISR); -} - - -void debugpins_radio_set(void) { - nrf_gpio_pin_set(GPIO_DEBUGPIN_RADIO); -} - -void debugpins_radio_clr(void) { - nrf_gpio_pin_clear(GPIO_DEBUGPIN_RADIO); -} - -void debugpins_radio_toggle(void) { - nrf_gpio_pin_toggle(GPIO_DEBUGPIN_RADIO); -} - - -//------------ private ------------// - -#endif // DEBUG_PINS_DISABLED \ No newline at end of file diff --git a/bsp/boards/nrf52840/documents/GPIO_usage_DK.txt b/bsp/boards/nrf52840/documents/GPIO_usage_DK.txt deleted file mode 100644 index e2bdad66e1..0000000000 Binary files a/bsp/boards/nrf52840/documents/GPIO_usage_DK.txt and /dev/null differ diff --git a/bsp/boards/nrf52840/documents/GPIO_usage_dongle.txt b/bsp/boards/nrf52840/documents/GPIO_usage_dongle.txt deleted file mode 100644 index 5da373147e..0000000000 Binary files a/bsp/boards/nrf52840/documents/GPIO_usage_dongle.txt and /dev/null differ diff --git a/bsp/boards/nrf52840/i2c.c b/bsp/boards/nrf52840/i2c.c deleted file mode 100644 index caa3758228..0000000000 --- a/bsp/boards/nrf52840/i2c.c +++ /dev/null @@ -1,97 +0,0 @@ -/** - * brief nrf52840-specific definition of the "i2c" bsp module. - * - * Authors: Tamas Harczos (tamas.harczos@imms.de) - * Company: Institut fuer Mikroelektronik- und Mechatronik-Systeme gemeinnuetzige GmbH (IMMS GmbH) - * Date: August 2018 -*/ - - -#include "nrfx_twi.h" - -#include "i2c.h" -#include "app_config.h" -#include "leds.h" -#include "board.h" -#include "board_info.h" -#include "nrf_gpio.h" - - -//=========================== defines ========================================= - - -//=========================== variables ======================================= - -#if BOARD_PCA10056 // nrf52840-DK -#define I2C_SCL_PIN NRF_GPIO_PIN_MAP(1, 5) -#define I2C_SDA_PIN NRF_GPIO_PIN_MAP(1, 6) -#endif - -#if BOARD_PCA10059 // nrf52840-DONGLE -#define I2C_SCL_PIN NRF_GPIO_PIN_MAP(1, 0) -#define I2C_SDA_PIN NRF_GPIO_PIN_MAP(0, 24) -#endif - -nrf_twi_frequency_t const I2C_BAUDRATE= NRF_TWI_FREQ_400K; ///< actual rate is 410256 bps -nrfx_twi_t m_twi= NRFX_TWI_INSTANCE(1); ///< instance 0 is used by the SPI - - -//=========================== prototypes ====================================== - -//=========================== public ========================================== - -void i2c_init(void) { - nrfx_twi_config_t const i2c_config= - { - .scl= I2C_SCL_PIN, ///< SCL pin number - .sda= I2C_SDA_PIN, ///< SDA pin number - .frequency= I2C_BAUDRATE, ///< TWI frequency - .interrupt_priority= NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY, ///< interrupt priority - .hold_bus_uninit= false ///< hold pull up state on GPIO pins after uninit - }; - - if (NRFX_SUCCESS != nrfx_twi_init(&m_twi, &i2c_config, NULL, NULL)) { - leds_error_blink(); - } - - // After enabling the TWI, it will draw some current. @todo: Maybe we could enable/disable TWI only during - // transfers. Or maybe we should disable it every time the board goes to sleep and reinitialize it upon usage. - nrfx_twi_enable(&m_twi); -} - - -void i2c_read_byte(uint8_t address, uint8_t* byte) { - i2c_read_bytes(address, byte, 1); -} - - -uint32_t i2c_read_bytes(uint8_t address, uint8_t* buffer, uint32_t length) { - nrfx_err_t retVal= nrfx_twi_rx(&m_twi, address, buffer, (size_t) length); - - if (retVal != NRFX_SUCCESS) { - // handle error - } - - return length; -} - - -void i2c_write_byte(uint8_t address, uint8_t byte) { - - i2c_write_bytes(address, &byte, 1); -} - - -uint32_t i2c_write_bytes(uint8_t address, uint8_t* buffer, uint32_t length) { - - nrfx_err_t retVal= nrfx_twi_tx(&m_twi, address, (uint8_t const *) buffer, (size_t) length, false); - - if (retVal != NRFX_SUCCESS) { - // handle error - } - - return length; -} - -//=========================== private ========================================= - diff --git a/bsp/boards/nrf52840/leds.c b/bsp/boards/nrf52840/leds.c deleted file mode 100644 index e3d397e21e..0000000000 --- a/bsp/boards/nrf52840/leds.c +++ /dev/null @@ -1,235 +0,0 @@ -/** - * Author: Tamas Harczos (tamas.harczos@imms.de) - * Date: Apr 2018 - * Description: nRF52840-specific definition of the "leds" bsp module. - */ - -#include "sdk/components/boards/boards.h" -#include "sdk/components/libraries/delay/nrf_delay.h" - -#include "stdint.h" -#include "leds.h" -#include "board.h" -#include "board_info.h" - - -//=========================== defines ========================================= -#if BOARD_PCA10056 -// nrf52840-DK -#define LED_IDX_ERROR 0 -#define LED_IDX_DEBUG 1 -#define LED_IDX_SYNC 2 -#define LED_IDX_RADIO 3 -#endif -#if BOARD_PCA10059 -// nrf52840-DONGLE -#define LED_IDX_ERROR 0 // LED1 -#define LED_IDX_DEBUG 2 // LED2_G -#define LED_IDX_RADIO 3 // LED2_B -#endif - - -//=========================== variables ======================================= - -//=========================== prototypes ====================================== - -void bspLedSet(uint8_t ui8Led); -void bspLedClear(uint8_t ui8Led); -void bspLedToggle(uint8_t ui8Led); -bool bspLedGet(uint8_t ui8Led); - - -//=========================== public ========================================== - -void leds_init() { -#ifndef NO_LEDS - // LEDs have probably been already initialized in board.c:board_init(), but we can do that again without problems - - const uint8_t m_board_led_list[LEDS_NUMBER] = LEDS_LIST; - - for (uint8_t l=0; l < LEDS_NUMBER; ++l) { - nrf_gpio_cfg_output(m_board_led_list[l]); - } - - bsp_board_leds_off(); -#endif // NO_LEDS -} - - -void leds_error_on(void) { - bspLedSet(LED_IDX_ERROR); -} - -void leds_error_off(void) { - bspLedClear(LED_IDX_ERROR); -} - -void leds_error_toggle(void) { - bspLedToggle(LED_IDX_ERROR); -} - -uint8_t leds_error_isOn(void) { - return((uint8_t) bspLedGet(LED_IDX_ERROR)); -} - - -void leds_sync_on(void) { -#if BOARD_PCA10056 - bspLedSet(LED_IDX_SYNC); -#endif -} - -void leds_sync_off(void) { -#if BOARD_PCA10056 - bspLedClear(LED_IDX_SYNC); -#endif -} - -void leds_sync_toggle(void) { -#if BOARD_PCA10056 - bspLedToggle(LED_IDX_SYNC); -#endif -} - -uint8_t leds_sync_isOn(void) { -#if BOARD_PCA10056 - return((uint8_t) bspLedGet(LED_IDX_SYNC)); -#else - return FALSE; -#endif -} - - -void leds_radio_on(void) { - bspLedSet(LED_IDX_RADIO); -} - -void leds_radio_off(void) { - bspLedClear(LED_IDX_RADIO); -} - -void leds_radio_toggle(void) { - bspLedToggle(LED_IDX_RADIO); -} - -uint8_t leds_radio_isOn(void) { - return((uint8_t) bspLedGet(LED_IDX_RADIO)); -} - - -void leds_debug_on(void) { - bspLedSet(LED_IDX_DEBUG); -} - -void leds_debug_off(void) { - bspLedClear(LED_IDX_DEBUG); -} - -void leds_debug_toggle(void) { - bspLedToggle(LED_IDX_DEBUG); -} - -uint8_t leds_debug_isOn(void) { - return((uint8_t) bspLedGet(LED_IDX_DEBUG)); -} - - -void leds_all_on(void) { - leds_radio_on(); - leds_sync_on(); - leds_debug_on(); - leds_error_on(); -} - -void leds_all_off(void) { - leds_radio_off(); - leds_sync_off(); - leds_debug_off(); - leds_error_off(); -} - -void leds_all_toggle(void) { - leds_radio_toggle(); - leds_sync_toggle(); - leds_debug_toggle(); - leds_error_toggle(); -} - -void leds_error_blink(void) { - uint8_t i; - - // turn all LEDs off - leds_all_off(); - - // blink error LED for ~10s - for (i = 0; i < 100; i++) { - leds_error_toggle(); - nrf_delay_ms(100); - } -} - -void leds_circular_shift(void) { - bool led3_state= bspLedGet(3); - (bspLedGet(2))?(bspLedSet(3)):(bspLedClear(3)); - (bspLedGet(1))?(bspLedSet(2)):(bspLedClear(2)); - (bspLedGet(0))?(bspLedSet(1)):(bspLedClear(1)); - (led3_state)?(bspLedSet(0)):(bspLedClear(0)); -} - -void leds_increment(void) { - if (bspLedGet(3)) { - leds_all_off(); - } else { - if (bspLedGet(2)) { - bspLedSet(3); - return; - } - - if (bspLedGet(1)) { - bspLedSet(2); - return; - } - - if (bspLedGet(0)) { - bspLedSet(1); - return; - } - - bspLedSet(0); - } -} - -//=========================== private ========================================= - -void bspLedSet(uint8_t ui8Led) { -#ifndef NO_LEDS - bsp_board_led_on(ui8Led); -#else - (void)ui8Led; -#endif -} - -void bspLedClear(uint8_t ui8Led) { -#ifndef NO_LEDS - bsp_board_led_off(ui8Led); -#else - (void)ui8Led; -#endif -} - -void bspLedToggle(uint8_t ui8Led) { -#ifndef NO_LEDS - bsp_board_led_invert(ui8Led); -#else - (void)ui8Led; -#endif -} - -bool bspLedGet(uint8_t ui8Led) { -#ifndef NO_LEDS - return bsp_board_led_state_get(ui8Led); -#else - (void)ui8Led; - return false; -#endif -} \ No newline at end of file diff --git a/bsp/boards/nrf52840/nrf52840_xxaa.ld b/bsp/boards/nrf52840/nrf52840_xxaa.ld deleted file mode 100644 index 13ca57be17..0000000000 --- a/bsp/boards/nrf52840/nrf52840_xxaa.ld +++ /dev/null @@ -1,24 +0,0 @@ -/* Linker script to configure memory regions. */ - -SEARCH_DIR(.) -GROUP(-lgcc -lc -lnosys) - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x100000 - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000 -} - -INCLUDE "nrf_common.ld" - -SECTIONS -{ - .pwr_mgmt_data : - { - PROVIDE(__start_pwr_mgmt_data = .); - KEEP(*(SORT(.pwr_mgmt_data*))) - PROVIDE(__stop_pwr_mgmt_data = .); - } > FLASH -} - - diff --git a/bsp/boards/nrf52840/nrf52840_xxaa_dongle.ld b/bsp/boards/nrf52840/nrf52840_xxaa_dongle.ld deleted file mode 100644 index f2048ce199..0000000000 --- a/bsp/boards/nrf52840/nrf52840_xxaa_dongle.ld +++ /dev/null @@ -1,25 +0,0 @@ -/* Linker script to configure memory regions. */ - -SEARCH_DIR(.) -GROUP(-lgcc -lc -lnosys) - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x1000, LENGTH = 0xff000 - RAM (rwx) : ORIGIN = 0x20000008, LENGTH = 0x3fff8 -} - - -INCLUDE "nrf_common.ld" - -SECTIONS -{ - .pwr_mgmt_data : - { - PROVIDE(__start_pwr_mgmt_data = .); - KEEP(*(SORT(.pwr_mgmt_data*))) - PROVIDE(__stop_pwr_mgmt_data = .); - } > FLASH -} - - diff --git a/bsp/boards/nrf52840/nrfx_rtc_hack.c b/bsp/boards/nrf52840/nrfx_rtc_hack.c deleted file mode 100644 index e215a8dc04..0000000000 --- a/bsp/boards/nrf52840/nrfx_rtc_hack.c +++ /dev/null @@ -1,378 +0,0 @@ -/** - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include -#include "sdk/components/libraries/delay/nrf_delay.h" - -#if NRFX_CHECK(NRFX_RTC_ENABLED) - -#if !(NRFX_CHECK(NRFX_RTC0_ENABLED) || NRFX_CHECK(NRFX_RTC1_ENABLED) || \ - NRFX_CHECK(NRFX_RTC2_ENABLED)) -#error "No enabled RTC instances. Check ." -#endif - -#include - -#define NRFX_LOG_MODULE RTC -#include - - -#define EVT_TO_STR(event) \ - (event == NRF_RTC_EVENT_TICK ? "NRF_RTC_EVENT_TICK" : \ - (event == NRF_RTC_EVENT_OVERFLOW ? "NRF_RTC_EVENT_OVERFLOW" : \ - (event == NRF_RTC_EVENT_COMPARE_0 ? "NRF_RTC_EVENT_COMPARE_0" : \ - (event == NRF_RTC_EVENT_COMPARE_1 ? "NRF_RTC_EVENT_COMPARE_1" : \ - (event == NRF_RTC_EVENT_COMPARE_2 ? "NRF_RTC_EVENT_COMPARE_2" : \ - (event == NRF_RTC_EVENT_COMPARE_3 ? "NRF_RTC_EVENT_COMPARE_3" : \ - "UNKNOWN EVENT")))))) - - -/**@brief RTC driver instance control block structure. */ -typedef struct -{ - nrfx_drv_state_t state; /**< Instance state. */ - bool reliable; /**< Reliable mode flag. */ - uint8_t tick_latency; /**< Maximum length of interrupt handler in ticks (max 7.7 ms). */ -} nrfx_rtc_cb_t; - -// User callbacks local storage. -static nrfx_rtc_handler_t m_handlers[NRFX_RTC_ENABLED_COUNT]; -static nrfx_rtc_cb_t m_cb[NRFX_RTC_ENABLED_COUNT]; - - -///< >>>>>> HACK to be able to schedule an ISR from opentimers >>>>>> - -static volatile bool RTC0_CC1_Pending= false; - - -///< <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< - - -nrfx_err_t nrfx_rtc_init(nrfx_rtc_t const * const p_instance, - nrfx_rtc_config_t const * p_config, - nrfx_rtc_handler_t handler) -{ - NRFX_ASSERT(p_config); - NRFX_ASSERT(handler); - nrfx_err_t err_code; - - m_handlers[p_instance->instance_id] = handler; - - if (m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED) - { - err_code = NRFX_ERROR_INVALID_STATE; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - NRFX_IRQ_PRIORITY_SET(p_instance->irq, p_config->interrupt_priority); - NRFX_IRQ_ENABLE(p_instance->irq); - nrf_rtc_prescaler_set(p_instance->p_reg, p_config->prescaler); - m_cb[p_instance->instance_id].reliable = p_config->reliable; - m_cb[p_instance->instance_id].tick_latency = p_config->tick_latency; - m_cb[p_instance->instance_id].state = NRFX_DRV_STATE_INITIALIZED; - - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -void nrfx_rtc_uninit(nrfx_rtc_t const * const p_instance) -{ - uint32_t mask = NRF_RTC_INT_TICK_MASK | - NRF_RTC_INT_OVERFLOW_MASK | - NRF_RTC_INT_COMPARE0_MASK | - NRF_RTC_INT_COMPARE1_MASK | - NRF_RTC_INT_COMPARE2_MASK | - NRF_RTC_INT_COMPARE3_MASK; - NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); - - NRFX_IRQ_DISABLE(p_instance->irq); - - nrf_rtc_task_trigger(p_instance->p_reg, NRF_RTC_TASK_STOP); - nrf_rtc_event_disable(p_instance->p_reg, mask); - nrf_rtc_int_disable(p_instance->p_reg, mask); - - m_cb[p_instance->instance_id].state = NRFX_DRV_STATE_UNINITIALIZED; - NRFX_LOG_INFO("Uninitialized."); -} - -void nrfx_rtc_enable(nrfx_rtc_t const * const p_instance) -{ - NRFX_ASSERT(m_cb[p_instance->instance_id].state == NRFX_DRV_STATE_INITIALIZED); - - nrf_rtc_task_trigger(p_instance->p_reg, NRF_RTC_TASK_START); - m_cb[p_instance->instance_id].state = NRFX_DRV_STATE_POWERED_ON; - NRFX_LOG_INFO("Enabled."); -} - -void nrfx_rtc_disable(nrfx_rtc_t const * const p_instance) -{ - NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); - - nrf_rtc_task_trigger(p_instance->p_reg, NRF_RTC_TASK_STOP); - m_cb[p_instance->instance_id].state = NRFX_DRV_STATE_INITIALIZED; - NRFX_LOG_INFO("Disabled."); -} - -nrfx_err_t nrfx_rtc_cc_disable(nrfx_rtc_t const * const p_instance, uint32_t channel) -{ - NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); - NRFX_ASSERT(channelcc_channel_count); - - nrfx_err_t err_code; - uint32_t int_mask = RTC_CHANNEL_INT_MASK(channel); - nrf_rtc_event_t event = RTC_CHANNEL_EVENT_ADDR(channel); - - nrf_rtc_event_disable(p_instance->p_reg,int_mask); - if (nrf_rtc_int_is_enabled(p_instance->p_reg,int_mask)) - { - nrf_rtc_int_disable(p_instance->p_reg,int_mask); - if (nrf_rtc_event_pending(p_instance->p_reg,event)) - { - nrf_rtc_event_clear(p_instance->p_reg,event); - err_code = NRFX_ERROR_TIMEOUT; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - } - NRFX_LOG_INFO("RTC id: %d, channel disabled: %lu.", p_instance->instance_id, channel); - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -nrfx_err_t nrfx_rtc_cc_set(nrfx_rtc_t const * const p_instance, - uint32_t channel, - uint32_t val, - bool enable_irq) -{ - NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); - NRFX_ASSERT(channelcc_channel_count); - - nrfx_err_t err_code; - uint32_t int_mask = RTC_CHANNEL_INT_MASK(channel); - nrf_rtc_event_t event = RTC_CHANNEL_EVENT_ADDR(channel); - - nrf_rtc_event_disable(p_instance->p_reg, int_mask); - nrf_rtc_int_disable(p_instance->p_reg, int_mask); - - val = RTC_WRAP(val); - if (m_cb[p_instance->instance_id].reliable) - { - nrf_rtc_cc_set(p_instance->p_reg,channel,val); - uint32_t cnt = nrf_rtc_counter_get(p_instance->p_reg); - int32_t diff = cnt - val; - if (cnt < val) - { - diff += RTC_COUNTER_COUNTER_Msk; - } - if (diff < m_cb[p_instance->instance_id].tick_latency) - { - err_code = NRFX_ERROR_TIMEOUT; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - } - else - { - nrf_rtc_cc_set(p_instance->p_reg,channel,val); - } - - if (enable_irq) - { - nrf_rtc_event_clear(p_instance->p_reg,event); - nrf_rtc_int_enable(p_instance->p_reg, int_mask); - } - nrf_rtc_event_enable(p_instance->p_reg,int_mask); - - NRFX_LOG_INFO("RTC id: %d, channel enabled: %lu, compare value: %lu.", - p_instance->instance_id, - channel, - val); - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -void nrfx_rtc_tick_enable(nrfx_rtc_t const * const p_instance, bool enable_irq) -{ - nrf_rtc_event_t event = NRF_RTC_EVENT_TICK; - uint32_t mask = NRF_RTC_INT_TICK_MASK; - - nrf_rtc_event_clear(p_instance->p_reg, event); - nrf_rtc_event_enable(p_instance->p_reg, mask); - if (enable_irq) - { - nrf_rtc_int_enable(p_instance->p_reg, mask); - } - NRFX_LOG_INFO("Tick events enabled."); -} - -void nrfx_rtc_tick_disable(nrfx_rtc_t const * const p_instance) -{ - uint32_t mask = NRF_RTC_INT_TICK_MASK; - - nrf_rtc_event_disable(p_instance->p_reg, mask); - nrf_rtc_int_disable(p_instance->p_reg, mask); - NRFX_LOG_INFO("Tick events disabled."); -} - -void nrfx_rtc_overflow_enable(nrfx_rtc_t const * const p_instance, bool enable_irq) -{ - nrf_rtc_event_t event = NRF_RTC_EVENT_OVERFLOW; - uint32_t mask = NRF_RTC_INT_OVERFLOW_MASK; - - nrf_rtc_event_clear(p_instance->p_reg, event); - nrf_rtc_event_enable(p_instance->p_reg, mask); - if (enable_irq) - { - nrf_rtc_int_enable(p_instance->p_reg, mask); - } -} - -void nrfx_rtc_overflow_disable(nrfx_rtc_t const * const p_instance) -{ - uint32_t mask = NRF_RTC_INT_OVERFLOW_MASK; - nrf_rtc_event_disable(p_instance->p_reg, mask); - nrf_rtc_int_disable(p_instance->p_reg, mask); -} - -uint32_t nrfx_rtc_max_ticks_get(nrfx_rtc_t const * const p_instance) -{ - uint32_t ticks; - if (m_cb[p_instance->instance_id].reliable) - { - ticks = RTC_COUNTER_COUNTER_Msk - m_cb[p_instance->instance_id].tick_latency; - } - else - { - ticks = RTC_COUNTER_COUNTER_Msk; - } - return ticks; -} - -static void irq_handler(NRF_RTC_Type * p_reg, - uint32_t instance_id, - uint32_t channel_count) -{ - uint32_t i; - uint32_t int_mask = (uint32_t)NRF_RTC_INT_COMPARE0_MASK; - nrf_rtc_event_t event = NRF_RTC_EVENT_COMPARE_0; - - for (i = 0; i < channel_count; i++) - { - if (nrf_rtc_int_is_enabled(p_reg,int_mask) && nrf_rtc_event_pending(p_reg,event)) - { - nrf_rtc_event_disable(p_reg,int_mask); - nrf_rtc_int_disable(p_reg,int_mask); - nrf_rtc_event_clear(p_reg,event); - NRFX_LOG_DEBUG("Event: %s, instance id: %lu.", EVT_TO_STR(event), instance_id); - m_handlers[instance_id]((nrfx_rtc_int_type_t)i); - } - int_mask <<= 1; - event = (nrf_rtc_event_t)((uint32_t)event + sizeof(uint32_t)); - } - event = NRF_RTC_EVENT_TICK; - if (nrf_rtc_int_is_enabled(p_reg,NRF_RTC_INT_TICK_MASK) && - nrf_rtc_event_pending(p_reg, event)) - { - nrf_rtc_event_clear(p_reg, event); - NRFX_LOG_DEBUG("Event: %s, instance id: %lu.", EVT_TO_STR(event), instance_id); - m_handlers[instance_id](NRFX_RTC_INT_TICK); - } - - event = NRF_RTC_EVENT_OVERFLOW; - if (nrf_rtc_int_is_enabled(p_reg,NRF_RTC_INT_OVERFLOW_MASK) && - nrf_rtc_event_pending(p_reg, event)) - { - nrf_rtc_event_clear(p_reg,event); - NRFX_LOG_DEBUG("Event: %s, instance id: %lu.", EVT_TO_STR(event), instance_id); - m_handlers[instance_id](NRFX_RTC_INT_OVERFLOW); - } -} - - -///< >>>>>> HACK to be able to schedule an ISR from opentimers >>>>>> -void setIntPending_RTC0_CC1() -{ - RTC0_CC1_Pending= true; - __DSB(); - NVIC_SetPendingIRQ(RTC0_IRQn); -} -///< <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< - - -#if NRFX_CHECK(NRFX_RTC0_ENABLED) -void nrfx_rtc_0_irq_handler(void) -{ - irq_handler(NRF_RTC0, NRFX_RTC0_INST_IDX, NRF_RTC_CC_CHANNEL_COUNT(0)); - - ///< >>>>>> HACK to be able to schedule an ISR from opentimers >>>>>> - if (RTC0_CC1_Pending) - { - RTC0_CC1_Pending= false; - m_handlers[NRFX_RTC0_INST_IDX](NRFX_RTC_INT_COMPARE1); - } - ///< <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< -} -#endif - -#if NRFX_CHECK(NRFX_RTC1_ENABLED) -void nrfx_rtc_1_irq_handler(void) -{ - irq_handler(NRF_RTC1, NRFX_RTC1_INST_IDX, NRF_RTC_CC_CHANNEL_COUNT(1)); -} -#endif - -#if NRFX_CHECK(NRFX_RTC2_ENABLED) -void nrfx_rtc_2_irq_handler(void) -{ - irq_handler(NRF_RTC2, NRFX_RTC2_INST_IDX, NRF_RTC_CC_CHANNEL_COUNT(2)); -} -#endif - -#endif // NRFX_CHECK(NRFX_RTC_ENABLED) diff --git a/bsp/boards/nrf52840/nrfx_rtc_hack.h b/bsp/boards/nrf52840/nrfx_rtc_hack.h deleted file mode 100644 index 0077bd674f..0000000000 --- a/bsp/boards/nrf52840/nrfx_rtc_hack.h +++ /dev/null @@ -1,375 +0,0 @@ -/** - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_RTC_HACK_H__ -#define NRFX_RTC_HACK_H__ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_rtc RTC driver - * @{ - * @ingroup nrf_rtc - * @brief Real Timer Counter (RTC) peripheral driver. - */ - -/**@brief Macro to convert microseconds into ticks. */ -#define NRFX_RTC_US_TO_TICKS(us,freq) (((us) * (freq)) / 1000000U) - -/**@brief RTC driver interrupt types. */ -typedef enum -{ - NRFX_RTC_INT_COMPARE0 = 0, /**< Interrupt from COMPARE0 event. */ - NRFX_RTC_INT_COMPARE1 = 1, /**< Interrupt from COMPARE1 event. */ - NRFX_RTC_INT_COMPARE2 = 2, /**< Interrupt from COMPARE2 event. */ - NRFX_RTC_INT_COMPARE3 = 3, /**< Interrupt from COMPARE3 event. */ - NRFX_RTC_INT_TICK = 4, /**< Interrupt from TICK event. */ - NRFX_RTC_INT_OVERFLOW = 5 /**< Interrupt from OVERFLOW event. */ -} nrfx_rtc_int_type_t; - -/**@brief RTC driver instance structure. */ -typedef struct -{ - NRF_RTC_Type * p_reg; /**< Pointer to instance register set. */ - IRQn_Type irq; /**< Instance IRQ ID. */ - uint8_t instance_id; /**< Instance index. */ - uint8_t cc_channel_count; /**< Number of capture/compare channels. */ -} nrfx_rtc_t; - -/**@brief Macro for creating RTC driver instance.*/ -#define NRFX_RTC_INSTANCE(id) \ -{ \ - .p_reg = NRFX_CONCAT_2(NRF_RTC, id), \ - .irq = NRFX_CONCAT_3(RTC, id, _IRQn), \ - .instance_id = NRFX_CONCAT_3(NRFX_RTC, id, _INST_IDX), \ - .cc_channel_count = NRF_RTC_CC_CHANNEL_COUNT(id), \ -} - -enum { -#if NRFX_CHECK(NRFX_RTC0_ENABLED) - NRFX_RTC0_INST_IDX, -#endif -#if NRFX_CHECK(NRFX_RTC1_ENABLED) - NRFX_RTC1_INST_IDX, -#endif -#if NRFX_CHECK(NRFX_RTC2_ENABLED) - NRFX_RTC2_INST_IDX, -#endif - NRFX_RTC_ENABLED_COUNT -}; - -/**@brief RTC driver instance configuration structure. */ -typedef struct -{ - uint16_t prescaler; /**< Prescaler. */ - uint8_t interrupt_priority; /**< Interrupt priority. */ - uint8_t tick_latency; /**< Maximum length of interrupt handler in ticks (max 7.7 ms). */ - bool reliable; /**< Reliable mode flag. */ -} nrfx_rtc_config_t; - -/**@brief RTC instance default configuration. */ -#define NRFX_RTC_DEFAULT_CONFIG \ -{ \ - .prescaler = RTC_FREQ_TO_PRESCALER(NRFX_RTC_DEFAULT_CONFIG_FREQUENCY), \ - .interrupt_priority = NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY, \ - .reliable = NRFX_RTC_DEFAULT_CONFIG_RELIABLE, \ - .tick_latency = NRFX_RTC_US_TO_TICKS(NRFX_RTC_MAXIMUM_LATENCY_US, \ - NRFX_RTC_DEFAULT_CONFIG_FREQUENCY), \ -} - -/**@brief RTC driver instance handler type. */ -typedef void (*nrfx_rtc_handler_t)(nrfx_rtc_int_type_t int_type); - -/**@brief Function for initializing the RTC driver instance. - * - * After initialization, the instance is in power off state. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_config Pointer to the structure with initial configuration. - * @param[in] handler Event handler provided by the user. - * Must not be NULL. - * - * @retval NRFX_SUCCESS If successfully initialized. - * @retval NRFX_ERROR_INVALID_STATE If the instance is already initialized. - */ -nrfx_err_t nrfx_rtc_init(nrfx_rtc_t const * const p_instance, - nrfx_rtc_config_t const * p_config, - nrfx_rtc_handler_t handler); - -/**@brief Function for uninitializing the RTC driver instance. - * - * After uninitialization, the instance is in idle state. The hardware should return to the state - * before initialization. The function asserts if the instance is in idle state. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_rtc_uninit(nrfx_rtc_t const * const p_instance); - -/**@brief Function for enabling the RTC driver instance. - * - * @note Function asserts if instance is enabled. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_rtc_enable(nrfx_rtc_t const * const p_instance); - -/**@brief Function for disabling the RTC driver instance. - * - * @note Function asserts if instance is disabled. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_rtc_disable(nrfx_rtc_t const * const p_instance); - -/**@brief Function for setting a compare channel. - * - * The function asserts if the instance is not initialized or if the channel parameter is - * wrong. The function powers on the instance if the instance was in power off state. - * - * The driver is not entering a critical section when configuring RTC, which means that it can be - * preempted for a certain amount of time. When the driver was preempted and the value to be set - * is short in time, there is a risk that the driver sets a compare value that is - * behind. If RTCn_CONFIG_RELIABLE is 1 for the given instance, the Reliable mode handles that case. - * However, to detect if the requested value is behind, this mode makes the following assumptions: - * - The maximum preemption time in ticks (8 - bit value) is known and is less than 7.7 ms - * (for prescaler = 0, RTC frequency 32 kHz). - * - The requested absolute compare value is not bigger than (0x00FFFFFF) - tick_latency. It is - * the user's responsibility to ensure that. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] channel One of the instance's channels. - * @param[in] val Absolute value to be set in the compare register. - * @param[in] enable_irq True to enable the interrupt. False to disable the interrupt. - * - * @retval NRFX_SUCCESS If the procedure was successful. - * @retval NRFX_ERROR_TIMEOUT If the compare was not set because the request value is behind the current counter - * value. This error can only be reported if RTCn_CONFIG_RELIABLE = 1. - */ -nrfx_err_t nrfx_rtc_cc_set(nrfx_rtc_t const * const p_instance, - uint32_t channel, - uint32_t val, - bool enable_irq); - -/**@brief Function for disabling a channel. - * - * This function disables channel events and channel interrupts. The function asserts if the instance is not - * initialized or if the channel parameter is wrong. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] channel One of the instance's channels. - * - * @retval NRFX_SUCCESS If the procedure was successful. - * @retval NRFX_ERROR_TIMEOUT If an interrupt was pending on the requested channel. - */ -nrfx_err_t nrfx_rtc_cc_disable(nrfx_rtc_t const * const p_instance, uint32_t channel); - -/**@brief Function for enabling tick. - * - * This function enables the tick event and optionally the interrupt. The function asserts if the instance is not - * powered on. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] enable_irq True to enable the interrupt. False to disable the interrupt. - */ -void nrfx_rtc_tick_enable(nrfx_rtc_t const * const p_instance, bool enable_irq); - -/**@brief Function for disabling tick. - * - * This function disables the tick event and interrupt. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_rtc_tick_disable(nrfx_rtc_t const * const p_instance); - -/**@brief Function for enabling overflow. - * - * This function enables the overflow event and optionally the interrupt. The function asserts if the instance is - * not powered on. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] enable_irq True to enable the interrupt. False to disable the interrupt. - */ -void nrfx_rtc_overflow_enable(nrfx_rtc_t const * const p_instance, bool enable_irq); - -/**@brief Function for disabling overflow. - * - * This function disables the overflow event and interrupt. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_rtc_overflow_disable(nrfx_rtc_t const * const p_instance); - -/**@brief Function for getting the maximum relative ticks value that can be set in the compare channel. - * - * When a stack (for example SoftDevice) is used and it occupies high priority interrupts, - * the application code can be interrupted at any moment for a certain period of time. - * If Reliable mode is enabled, the provided maximum latency is taken into account - * and the return value is smaller than the RTC counter resolution. - * If Reliable mode is disabled, the return value equals the counter resolution. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @retval ticks Maximum ticks value. - */ -uint32_t nrfx_rtc_max_ticks_get(nrfx_rtc_t const * const p_instance); - - -///< >>>>>> HACK to be able to schedule an ISR from opentimers >>>>>> -void setIntPending_RTC0_CC1(void); -///< <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< - - -/**@brief Function for disabling all instance interrupts. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_mask Pointer to the location where the mask is filled. - */ -__STATIC_INLINE void nrfx_rtc_int_disable(nrfx_rtc_t const * const p_instance, - uint32_t * p_mask); - -/**@brief Function for enabling instance interrupts. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] mask Mask of interrupts to enable. - */ -__STATIC_INLINE void nrfx_rtc_int_enable(nrfx_rtc_t const * const p_instance, uint32_t mask); - -/**@brief Function for retrieving the current counter value. - * - * This function asserts if the instance is not powered on or if p_val is NULL. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @retval value Counter value. - */ -__STATIC_INLINE uint32_t nrfx_rtc_counter_get(nrfx_rtc_t const * const p_instance); - -/**@brief Function for clearing the counter value. - * - * This function asserts if the instance is not powered on. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -__STATIC_INLINE void nrfx_rtc_counter_clear(nrfx_rtc_t const * const p_instance); - -/**@brief Function for returning a requested task address for the RTC driver instance. - * - * This function asserts if the output pointer is NULL. The task address can be used by the PPI module. - * - * @param[in] p_instance Pointer to the instance. - * @param[in] task One of the peripheral tasks. - * - * @retval Address of task register. - */ -__STATIC_INLINE uint32_t nrfx_rtc_task_address_get(nrfx_rtc_t const * const p_instance, - nrf_rtc_task_t task); - -/**@brief Function for returning a requested event address for the RTC driver instance. - * - * This function asserts if the output pointer is NULL. The event address can be used by the PPI module. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] event One of the peripheral events. - * - * @retval Address of event register. - */ -__STATIC_INLINE uint32_t nrfx_rtc_event_address_get(nrfx_rtc_t const * const p_instance, - nrf_rtc_event_t event); - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -__STATIC_INLINE void nrfx_rtc_int_disable(nrfx_rtc_t const * const p_instance, - uint32_t * p_mask) -{ - *p_mask = nrf_rtc_int_get(p_instance->p_reg); - nrf_rtc_int_disable(p_instance->p_reg, NRF_RTC_INT_TICK_MASK | - NRF_RTC_INT_OVERFLOW_MASK | - NRF_RTC_INT_COMPARE0_MASK | - NRF_RTC_INT_COMPARE1_MASK | - NRF_RTC_INT_COMPARE2_MASK | - NRF_RTC_INT_COMPARE3_MASK); -} - -__STATIC_INLINE void nrfx_rtc_int_enable(nrfx_rtc_t const * const p_instance, uint32_t mask) -{ - nrf_rtc_int_enable(p_instance->p_reg, mask); -} - -__STATIC_INLINE uint32_t nrfx_rtc_counter_get(nrfx_rtc_t const * const p_instance) -{ - return nrf_rtc_counter_get(p_instance->p_reg); -} - -__STATIC_INLINE void nrfx_rtc_counter_clear(nrfx_rtc_t const * const p_instance) -{ - nrf_rtc_task_trigger(p_instance->p_reg, NRF_RTC_TASK_CLEAR); -} - -__STATIC_INLINE uint32_t nrfx_rtc_task_address_get(nrfx_rtc_t const * const p_instance, - nrf_rtc_task_t task) -{ - return nrf_rtc_task_address_get(p_instance->p_reg, task); -} - -__STATIC_INLINE uint32_t nrfx_rtc_event_address_get(nrfx_rtc_t const * const p_instance, - nrf_rtc_event_t event) -{ - return nrf_rtc_event_address_get(p_instance->p_reg, event); -} -#endif // SUPPRESS_INLINE_IMPLEMENTATION - - -void nrfx_rtc_0_irq_handler(void); -void nrfx_rtc_1_irq_handler(void); -void nrfx_rtc_2_irq_handler(void); - - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_RTC_HACK_H__ diff --git a/bsp/boards/nrf52840/radio_ble.h b/bsp/boards/nrf52840/radio_ble.h deleted file mode 100644 index db14729d57..0000000000 --- a/bsp/boards/nrf52840/radio_ble.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef __RADIO_BLE_H -#define __RADIO_BLE_H - -/** - -\brief declaration "radio_ble" bsp module. - -\author Tengfei Chang , August 2020. -*/ - -//=========================== define ========================================== - -//=========================== typedef ========================================= - -//=========================== variables ======================================= - -//=========================== prototypes ====================================== - -// admin -void radio_ble_init(void); -void radio_ble_setFrequency(uint8_t channel); -void radio_ble_loadPacket(uint8_t* packet, uint16_t len); -void radio_ble_getReceivedFrame(uint8_t* pBufRead, - uint8_t* pLenRead, - uint8_t maxBufLen, - int8_t* pRssi, - uint8_t* pLqi, - bool* pCrc); - -/** -\} -\} -*/ - -#endif diff --git a/bsp/boards/nrf52840/sctimer.c b/bsp/boards/nrf52840/sctimer.c deleted file mode 100644 index 175acea9ea..0000000000 --- a/bsp/boards/nrf52840/sctimer.c +++ /dev/null @@ -1,181 +0,0 @@ -/** - * brief A timer module with only a single compare value. - * - * Authors: Tamas Harczos (1, tamas.harczos@imms.de) and Adam Sedmak (2, adam.sedmak@gmail.com) - * Company: (1) Institut fuer Mikroelektronik- und Mechatronik-Systeme gemeinnuetzige GmbH (IMMS GmbH) - * (2) Faculty of Electronics and Computing, Zagreb, Croatia - * Date: May 2018 - * - * Note: We use RTC0 peripheral with its CC0 register. -*/ - - -#if defined(UNIT_TESTING) -#include "nrf52840.h" -#include "nrf52840_bitfields.h" -#include "nrf52840_peripherals.h" -#endif -#include "sdk/components/boards/boards.h" - -#include "nrfx_rtc_hack.h" ///< the implementation is based on the hacked version of Nordic's Real-Time Counter (RTC) driver, which allows us to schedule an RTC0 interrupt with CC1 event, triggered "by hand" -#include "sdk/components/libraries/delay/nrf_delay.h" - -#include "sctimer.h" -#include "board.h" -#include "leds.h" -#include "debugpins.h" - - -// ========================== define ========================================== - -#define MINIMUM_ISR_ADVANCE 16 ///< number of ticks to set CC ahead to make sure the RTC will fire (should this be equal to TIMERTHRESHOLD of opentimers?) -#define TIMERLOOP_THRESHOLD 0x20000 ///< 3s, if sctimer_setCompare() is late by max that many ticks, we still issue the ISR -#define MAX_RTC_TASKS_DELAY 47 ///< maximum delay in us until an RTC config task is executed - - -// ========================== variable ======================================== - -typedef struct -{ - sctimer_cbt cb; - uint32_t last_counter; - uint32_t counter_MSB; ///< the first 8 bits of the 32 bit counter (which do not exist in the physical timer) - uint32_t cc32bit_MSB; ///< the first 8 bits of the 32 bit CC (capture and compare) value, set - bool RTC_enabled; -} sctimer_vars_t; - -sctimer_vars_t sctimer_vars= {0}; - -nrfx_rtc_t m_timer= NRFX_RTC_INSTANCE(0); - - - -// ========================== prototypes======================================== - -extern bool ieee154e_isSynch(void); - -void timer_event_handler(nrfx_rtc_int_type_t int_type); - - -// ========================== protocol ========================================= - -/** -\brief Initialization sctimer. -*/ -void sctimer_init(void) { - nrfx_err_t retVal= NRFX_SUCCESS; - memset(&sctimer_vars, 0, sizeof(sctimer_vars_t)); - - nrfx_rtc_config_t const rtc_cfg= - { - .prescaler= RTC_FREQ_TO_PRESCALER(NRFX_RTC_DEFAULT_CONFIG_FREQUENCY), - .interrupt_priority= NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY, - .tick_latency= NRFX_RTC_US_TO_TICKS(NRFX_RTC_MAXIMUM_LATENCY_US, NRFX_RTC_DEFAULT_CONFIG_FREQUENCY), - .reliable= 0 - }; - - // initialize RTC, we use the 32768 Hz clock without prescaler - retVal= nrfx_rtc_init(&m_timer, &rtc_cfg, timer_event_handler); - if (NRFX_SUCCESS != retVal) { - leds_error_blink(); - board_reset(); - } - nrf_delay_us(MAX_RTC_TASKS_DELAY); - - // disable interrupt and event for overflow - nrfx_rtc_overflow_disable(&m_timer); - - // reset counter - nrfx_rtc_counter_clear(&m_timer); - nrf_delay_us(MAX_RTC_TASKS_DELAY); - - // from this on, the RTC will run, but also draw electrical current - sctimer_enable(); -} - -void sctimer_set_callback(sctimer_cbt cb) { - sctimer_vars.cb= cb; -} - -/** -\brief set compare interrupt -*/ -void sctimer_setCompare(PORT_TIMER_WIDTH val) { - - uint32_t counter_current= sctimer_readCounter(); - - if (counter_current - val < TIMERLOOP_THRESHOLD) { - // the timer is already late, schedule the ISR right now manually - setIntPending_RTC0_CC1(); - } else { - if (val - counter_current < MINIMUM_ISR_ADVANCE) { - // there is hardware limitation to schedule the timer within TIMERTHRESHOLD ticks - // schedule ISR right now manually - setIntPending_RTC0_CC1(); - } else { - // schedule the timer at val - nrfx_rtc_cc_set(&m_timer, 0, val & 0x00FFFFFF, true); ///< set 3 LSBs of CC - } - } -} - -/** -\brief Return the current value of the timer's counter. - - \returns The current value of the timer's counter. -*/ -PORT_TIMER_WIDTH sctimer_readCounter(void) { - uint32_t current_counter= nrfx_rtc_counter_get(&m_timer); - - NRFX_CRITICAL_SECTION_ENTER(); - - if (current_counter < sctimer_vars.last_counter) { - // 24-bit overflow happened - sctimer_vars.counter_MSB += 0x01000000; - } - - sctimer_vars.last_counter= current_counter; - current_counter |= sctimer_vars.counter_MSB; - - NRFX_CRITICAL_SECTION_EXIT(); - - return current_counter; -} - -void sctimer_enable(void) { - - if (!sctimer_vars.RTC_enabled) { - // power on RTC instance - sctimer_vars.RTC_enabled= true; - nrfx_rtc_enable(&m_timer); - nrf_delay_us(MAX_RTC_TASKS_DELAY); - } -} - -void sctimer_disable(void) { - if (sctimer_vars.RTC_enabled) { - // power down RTC instance - sctimer_vars.RTC_enabled= false; - nrfx_rtc_disable(&m_timer); - nrf_delay_us(MAX_RTC_TASKS_DELAY); - } -} - - -//=========================== interrupt handler =============================== - -void timer_event_handler(nrfx_rtc_int_type_t int_type) { - debugpins_isr_set(); - - if ( - (sctimer_vars.cb != 0) && - ( - (int_type == NRFX_RTC_INT_COMPARE1) || - (int_type == NRFX_RTC_INT_COMPARE0) - ) - ) { - sctimer_vars.cb(); - } - - debugpins_isr_clr(); -} diff --git a/bsp/boards/nrf52840/sdk/components/boards/boards.c b/bsp/boards/nrf52840/sdk/components/boards/boards.c deleted file mode 100644 index 92903f1cad..0000000000 --- a/bsp/boards/nrf52840/sdk/components/boards/boards.c +++ /dev/null @@ -1,228 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include "boards.h" -#if defined(BOARDS_WITH_USB_DFU_TRIGGER) && defined(BOARD_PCA10059) -#include "nrf_dfu_trigger_usb.h" -#endif -#include -#include - -#if LEDS_NUMBER > 0 -static const uint8_t m_board_led_list[LEDS_NUMBER] = LEDS_LIST; -#endif - -#if BUTTONS_NUMBER > 0 -static const uint8_t m_board_btn_list[BUTTONS_NUMBER] = BUTTONS_LIST; -#endif - -#if LEDS_NUMBER > 0 -bool bsp_board_led_state_get(uint32_t led_idx) -{ - ASSERT(led_idx < LEDS_NUMBER); - bool pin_set = nrf_gpio_pin_out_read(m_board_led_list[led_idx]) ? true : false; - return (pin_set == (LEDS_ACTIVE_STATE ? true : false)); -} - -void bsp_board_led_on(uint32_t led_idx) -{ - ASSERT(led_idx < LEDS_NUMBER); - nrf_gpio_pin_write(m_board_led_list[led_idx], LEDS_ACTIVE_STATE ? 1 : 0); -} - -void bsp_board_led_off(uint32_t led_idx) -{ - ASSERT(led_idx < LEDS_NUMBER); - nrf_gpio_pin_write(m_board_led_list[led_idx], LEDS_ACTIVE_STATE ? 0 : 1); -} - -void bsp_board_leds_off(void) -{ - uint32_t i; - for (i = 0; i < LEDS_NUMBER; ++i) - { - bsp_board_led_off(i); - } -} - -void bsp_board_leds_on(void) -{ - uint32_t i; - for (i = 0; i < LEDS_NUMBER; ++i) - { - bsp_board_led_on(i); - } -} - -void bsp_board_led_invert(uint32_t led_idx) -{ - ASSERT(led_idx < LEDS_NUMBER); - nrf_gpio_pin_toggle(m_board_led_list[led_idx]); -} - -#if defined(BOARD_PCA10059) -/** - * Function for configuring UICR_REGOUT0 register - * to set GPIO output voltage to 3.0V. - */ -static void gpio_output_voltage_setup(void) -{ - // Configure UICR_REGOUT0 register only if it is set to default value. - if ((NRF_UICR->REGOUT0 & UICR_REGOUT0_VOUT_Msk) == - (UICR_REGOUT0_VOUT_DEFAULT << UICR_REGOUT0_VOUT_Pos)) - { - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - - NRF_UICR->REGOUT0 = (NRF_UICR->REGOUT0 & ~((uint32_t)UICR_REGOUT0_VOUT_Msk)) | - (UICR_REGOUT0_VOUT_3V0 << UICR_REGOUT0_VOUT_Pos); - - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - - // System reset is needed to update UICR registers. - NVIC_SystemReset(); - } -} -#endif - -static void bsp_board_leds_init(void) -{ - #if defined(BOARD_PCA10059) - // If nRF52 USB Dongle is powered from USB (high voltage mode), - // GPIO output voltage is set to 1.8 V by default, which is not - // enough to turn on green and blue LEDs. Therefore, GPIO voltage - // needs to be increased to 3.0 V by configuring the UICR register. - if (NRF_POWER->MAINREGSTATUS & - (POWER_MAINREGSTATUS_MAINREGSTATUS_High << POWER_MAINREGSTATUS_MAINREGSTATUS_Pos)) - { - gpio_output_voltage_setup(); - } - #endif - - uint32_t i; - for (i = 0; i < LEDS_NUMBER; ++i) - { - nrf_gpio_cfg_output(m_board_led_list[i]); - } - bsp_board_leds_off(); -} - -uint32_t bsp_board_led_idx_to_pin(uint32_t led_idx) -{ - ASSERT(led_idx < LEDS_NUMBER); - return m_board_led_list[led_idx]; -} - -uint32_t bsp_board_pin_to_led_idx(uint32_t pin_number) -{ - uint32_t ret = 0xFFFFFFFF; - uint32_t i; - for (i = 0; i < LEDS_NUMBER; ++i) - { - if (m_board_led_list[i] == pin_number) - { - ret = i; - break; - } - } - return ret; -} -#endif //LEDS_NUMBER > 0 - -#if BUTTONS_NUMBER > 0 -bool bsp_board_button_state_get(uint32_t button_idx) -{ - ASSERT(button_idx < BUTTONS_NUMBER); - bool pin_set = nrf_gpio_pin_read(m_board_btn_list[button_idx]) ? true : false; - return (pin_set == (BUTTONS_ACTIVE_STATE ? true : false)); -} - -static void bsp_board_buttons_init(void) -{ - uint32_t i; - for (i = 0; i < BUTTONS_NUMBER; ++i) - { - nrf_gpio_cfg_input(m_board_btn_list[i], BUTTON_PULL); - } -} - -uint32_t bsp_board_pin_to_button_idx(uint32_t pin_number) -{ - uint32_t i; - uint32_t ret = 0xFFFFFFFF; - for (i = 0; i < BUTTONS_NUMBER; ++i) - { - if (m_board_btn_list[i] == pin_number) - { - ret = i; - break; - } - } - return ret; -} - -uint32_t bsp_board_button_idx_to_pin(uint32_t button_idx) -{ - ASSERT(button_idx < BUTTONS_NUMBER); - return m_board_btn_list[button_idx]; -} -#endif //BUTTONS_NUMBER > 0 - - -void bsp_board_init(uint32_t init_flags) -{ - #if defined(BOARDS_WITH_USB_DFU_TRIGGER) && defined(BOARD_PCA10059) - (void) nrf_dfu_trigger_usb_init(); - #endif - - #if LEDS_NUMBER > 0 - if (init_flags & BSP_INIT_LEDS) - { - bsp_board_leds_init(); - } - #endif //LEDS_NUMBER > 0 - - #if BUTTONS_NUMBER > 0 - if (init_flags & BSP_INIT_BUTTONS) - { - bsp_board_buttons_init(); - } - #endif //BUTTONS_NUMBER > 0 -} diff --git a/bsp/boards/nrf52840/sdk/components/boards/boards.h b/bsp/boards/nrf52840/sdk/components/boards/boards.h deleted file mode 100644 index b7cecdf643..0000000000 --- a/bsp/boards/nrf52840/sdk/components/boards/boards.h +++ /dev/null @@ -1,355 +0,0 @@ -/** - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef BOARDS_H -#define BOARDS_H - -#include "nrf_gpio.h" -#include "nordic_common.h" - -#if defined(BOARD_NRF6310) - #include "nrf6310.h" -#elif defined(BOARD_PCA10000) - #include "pca10000.h" -#elif defined(BOARD_PCA10001) - #include "pca10001.h" -#elif defined(BOARD_PCA10002) - #include "pca10000.h" -#elif defined(BOARD_PCA10003) - #include "pca10003.h" -#elif defined(BOARD_PCA20006) - #include "pca20006.h" -#elif defined(BOARD_PCA10028) - #include "pca10028.h" -#elif defined(BOARD_PCA10031) - #include "pca10031.h" -#elif defined(BOARD_PCA10036) - #include "pca10036.h" -#elif defined(BOARD_PCA10040) - #include "pca10040.h" -#elif defined(BOARD_PCA10056) - #include "pca10056.h" -#elif defined(BOARD_PCA20020) - #include "pca20020.h" -#elif defined(BOARD_PCA10059) - #include "pca10059.h" -#elif defined(BOARD_WT51822) - #include "wt51822.h" -#elif defined(BOARD_N5DK1) - #include "n5_starterkit.h" -#elif defined (BOARD_D52DK1) - #include "d52_starterkit.h" -#elif defined (BOARD_ARDUINO_PRIMO) - #include "arduino_primo.h" -#elif defined (CUSTOM_BOARD_INC) - #include STRINGIFY(CUSTOM_BOARD_INC.h) -#elif defined(BOARD_CUSTOM) - #include "custom_board.h" -#else -#error "Board is not defined" - -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/**@defgroup BSP_BOARD_INIT_FLAGS Board initialization flags. - * @{ */ -#define BSP_INIT_NONE 0 /**< No initialization of LEDs or buttons (@ref bsp_board_init).*/ -#define BSP_INIT_LEDS (1 << 0) /**< Enable LEDs during initialization (@ref bsp_board_init).*/ -#define BSP_INIT_BUTTONS (1 << 1) /**< Enable buttons during initialization (@ref bsp_board_init).*/ -/**@} */ - -/** - * Function for returning the state of an LED. - * - * @param led_idx LED index (starting from 0), as defined in the board-specific header. - * - * @return True if the LED is turned on. - */ -bool bsp_board_led_state_get(uint32_t led_idx); - -/** - * Function for turning on an LED. - * - * @param led_idx LED index (starting from 0), as defined in the board-specific header. - */ -void bsp_board_led_on(uint32_t led_idx); - -/** - * Function for turning off an LED. - * - * @param led_idx LED index (starting from 0), as defined in the board-specific header. - */ -void bsp_board_led_off(uint32_t led_idx); - -/** - * Function for inverting the state of an LED. - * - * @param led_idx LED index (starting from 0), as defined in the board-specific header. - */ -void bsp_board_led_invert(uint32_t led_idx); -/** - * Function for turning off all LEDs. - */ -void bsp_board_leds_off(void); - -/** - * Function for turning on all LEDs. - */ -void bsp_board_leds_on(void); - -/** - * Function for initializing the BSP handling for the board. - * - * @note This also initializes the USB DFU trigger library if @ref BOARDS_WITH_USB_DFU_TRIGGER is 1. - * - * @param[in] init_flags Flags specifying what to initialize (LEDs/buttons). - * See @ref BSP_BOARD_INIT_FLAGS. - */ -void bsp_board_init(uint32_t init_flags); - -/** - * Function for converting pin number to LED index. - * - * @param pin_number Pin number. - * - * @return LED index of the given pin or 0xFFFFFFFF if invalid pin provided. - */ -uint32_t bsp_board_pin_to_led_idx(uint32_t pin_number); - -/** - * Function for converting LED index to pin number. - * - * @param led_idx LED index. - * - * @return Pin number. - */ -uint32_t bsp_board_led_idx_to_pin(uint32_t led_idx); - -/** - * Function for returning the state of a button. - * - * @param button_idx Button index (starting from 0), as defined in the board-specific header. - * - * @return True if the button is pressed. - */ -bool bsp_board_button_state_get(uint32_t button_idx); - -/** - * Function for converting pin number to button index. - * - * @param pin_number Pin number. - * - * @return Button index of the given pin or 0xFFFFFFFF if invalid pin provided. - */ -uint32_t bsp_board_pin_to_button_idx(uint32_t pin_number); - - -/** - * Function for converting button index to pin number. - * - * @param button_idx Button index. - * - * @return Pin number. - */ -uint32_t bsp_board_button_idx_to_pin(uint32_t button_idx); - -#define BSP_BOARD_LED_0 0 -#define BSP_BOARD_LED_1 1 -#define BSP_BOARD_LED_2 2 -#define BSP_BOARD_LED_3 3 -#define BSP_BOARD_LED_4 4 -#define BSP_BOARD_LED_5 5 -#define BSP_BOARD_LED_6 6 -#define BSP_BOARD_LED_7 7 - -#define PIN_MASK(_pin) /*lint -save -e504 */ \ - (1u << (uint32_t)((_pin) & (~P0_PIN_NUM))) \ - /*lint -restore */ - -#define PIN_PORT(_pin) (((_pin) >= P0_PIN_NUM) ? NRF_P1 : NRF_GPIO) - -#ifdef BSP_LED_0 -#define BSP_LED_0_MASK PIN_MASK(BSP_LED_0) -#define BSP_LED_0_PORT PIN_PORT(BSP_LED_0) -#else -#define BSP_LED_0_MASK 0 -#define BSP_LED_0_PORT 0 -#endif -#ifdef BSP_LED_1 -#define BSP_LED_1_MASK PIN_MASK(BSP_LED_1) -#define BSP_LED_1_PORT PIN_PORT(BSP_LED_1) -#else -#define BSP_LED_1_MASK 0 -#define BSP_LED_1_PORT 0 -#endif -#ifdef BSP_LED_2 -#define BSP_LED_2_MASK PIN_MASK(BSP_LED_2) -#define BSP_LED_2_PORT PIN_PORT(BSP_LED_2) -#else -#define BSP_LED_2_MASK 0 -#define BSP_LED_2_PORT 0 -#endif -#ifdef BSP_LED_3 -#define BSP_LED_3_MASK PIN_MASK(BSP_LED_3) -#define BSP_LED_3_PORT PIN_PORT(BSP_LED_3) -#else -#define BSP_LED_3_MASK 0 -#define BSP_LED_3_PORT 0 -#endif -#ifdef BSP_LED_4 -#define BSP_LED_4_MASK PIN_MASK(BSP_LED_4) -#define BSP_LED_4_PORT PIN_PORT(BSP_LED_4) -#else -#define BSP_LED_4_MASK 0 -#define BSP_LED_4_PORT 0 -#endif -#ifdef BSP_LED_5 -#define BSP_LED_5_MASK PIN_MASK(BSP_LED_5) -#define BSP_LED_5_PORT PIN_PORT(BSP_LED_5) -#else -#define BSP_LED_5_MASK 0 -#define BSP_LED_5_PORT 0 -#endif -#ifdef BSP_LED_6 -#define BSP_LED_6_MASK PIN_MASK(BSP_LED_6) -#define BSP_LED_6_PORT PIN_PORT(BSP_LED_6) -#else -#define BSP_LED_6_MASK 0 -#define BSP_LED_6_PORT 0 -#endif -#ifdef BSP_LED_7 -#define BSP_LED_7_MASK PIN_MASK(BSP_LED_7) -#define BSP_LED_7_PORT PIN_PORT(BSP_LED_7) -#else -#define BSP_LED_7_MASK 0 -#define BSP_LED_7_PORT 0 -#endif - - -#define LEDS_MASK (BSP_LED_0_MASK | BSP_LED_1_MASK | \ - BSP_LED_2_MASK | BSP_LED_3_MASK | \ - BSP_LED_4_MASK | BSP_LED_5_MASK | \ - BSP_LED_6_MASK | BSP_LED_7_MASK) - -#define BSP_BOARD_BUTTON_0 0 -#define BSP_BOARD_BUTTON_1 1 -#define BSP_BOARD_BUTTON_2 2 -#define BSP_BOARD_BUTTON_3 3 -#define BSP_BOARD_BUTTON_4 4 -#define BSP_BOARD_BUTTON_5 5 -#define BSP_BOARD_BUTTON_6 6 -#define BSP_BOARD_BUTTON_7 7 - - -#ifdef BSP_BUTTON_0 -#define BSP_BUTTON_0_MASK (1<OUTSET = (leds_mask) & (LEDS_MASK & LEDS_INV_MASK); \ - NRF_GPIO->OUTCLR = (leds_mask) & (LEDS_MASK & ~LEDS_INV_MASK); } while (0) - -#define LEDS_ON(leds_mask) do { ASSERT(sizeof(leds_mask) == 4); \ - NRF_GPIO->OUTCLR = (leds_mask) & (LEDS_MASK & LEDS_INV_MASK); \ - NRF_GPIO->OUTSET = (leds_mask) & (LEDS_MASK & ~LEDS_INV_MASK); } while (0) - -#define LED_IS_ON(leds_mask) ((leds_mask) & (NRF_GPIO->OUT ^ LEDS_INV_MASK) ) - -#define LEDS_INVERT(leds_mask) do { uint32_t gpio_state = NRF_GPIO->OUT; \ - ASSERT(sizeof(leds_mask) == 4); \ - NRF_GPIO->OUTSET = ((leds_mask) & ~gpio_state); \ - NRF_GPIO->OUTCLR = ((leds_mask) & gpio_state); } while (0) - -#define LEDS_CONFIGURE(leds_mask) do { uint32_t pin; \ - ASSERT(sizeof(leds_mask) == 4); \ - for (pin = 0; pin < 32; pin++) \ - if ( (leds_mask) & (1 << pin) ) \ - nrf_gpio_cfg_output(pin); } while (0) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsp/boards/nrf52840/sdk/components/boards/pca10056.h b/bsp/boards/nrf52840/sdk/components/boards/pca10056.h deleted file mode 100644 index df102abf7e..0000000000 --- a/bsp/boards/nrf52840/sdk/components/boards/pca10056.h +++ /dev/null @@ -1,163 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef PCA10056_H -#define PCA10056_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "nrf_gpio.h" - -// LEDs definitions for PCA10056 -#define LEDS_NUMBER 4 - -#define LED_1 NRF_GPIO_PIN_MAP(0,13) -#define LED_2 NRF_GPIO_PIN_MAP(0,14) -#define LED_3 NRF_GPIO_PIN_MAP(0,15) -#define LED_4 NRF_GPIO_PIN_MAP(0,16) -#define LED_START LED_1 -#define LED_STOP LED_4 - -#define LEDS_ACTIVE_STATE 0 - -#define LEDS_LIST { LED_1, LED_2, LED_3, LED_4 } - -#define LEDS_INV_MASK LEDS_MASK - -#define BSP_LED_0 13 -#define BSP_LED_1 14 -#define BSP_LED_2 15 -#define BSP_LED_3 16 - -#define BUTTONS_NUMBER 4 - -#define BUTTON_1 11 -#define BUTTON_2 12 -#define BUTTON_3 24 -#define BUTTON_4 25 -#define BUTTON_PULL NRF_GPIO_PIN_PULLUP - -#define BUTTONS_ACTIVE_STATE 0 - -#define BUTTONS_LIST { BUTTON_1, BUTTON_2, BUTTON_3, BUTTON_4 } - -#define BSP_BUTTON_0 BUTTON_1 -#define BSP_BUTTON_1 BUTTON_2 -#define BSP_BUTTON_2 BUTTON_3 -#define BSP_BUTTON_3 BUTTON_4 - -#define RX_PIN_NUMBER 8 -#define TX_PIN_NUMBER 6 -#define CTS_PIN_NUMBER 7 -#define RTS_PIN_NUMBER 5 -#define HWFC true - -#define BSP_QSPI_SCK_PIN 19 -#define BSP_QSPI_CSN_PIN 17 -#define BSP_QSPI_IO0_PIN 20 -#define BSP_QSPI_IO1_PIN 21 -#define BSP_QSPI_IO2_PIN 22 -#define BSP_QSPI_IO3_PIN 23 - - -// serialization APPLICATION board - temp. setup for running serialized MEMU tests -#define SER_APP_RX_PIN NRF_GPIO_PIN_MAP(1,13) // UART RX pin number. -#define SER_APP_TX_PIN NRF_GPIO_PIN_MAP(1,14) // UART TX pin number. -#define SER_APP_CTS_PIN NRF_GPIO_PIN_MAP(0,2) // UART Clear To Send pin number. -#define SER_APP_RTS_PIN NRF_GPIO_PIN_MAP(1,15) // UART Request To Send pin number. - -#define SER_APP_SPIM0_SCK_PIN NRF_GPIO_PIN_MAP(0,27) // SPI clock GPIO pin number. -#define SER_APP_SPIM0_MOSI_PIN NRF_GPIO_PIN_MAP(0,2) // SPI Master Out Slave In GPIO pin number -#define SER_APP_SPIM0_MISO_PIN NRF_GPIO_PIN_MAP(0,26) // SPI Master In Slave Out GPIO pin number -#define SER_APP_SPIM0_SS_PIN NRF_GPIO_PIN_MAP(1,13) // SPI Slave Select GPIO pin number -#define SER_APP_SPIM0_RDY_PIN NRF_GPIO_PIN_MAP(1,15) // SPI READY GPIO pin number -#define SER_APP_SPIM0_REQ_PIN NRF_GPIO_PIN_MAP(1,14) // SPI REQUEST GPIO pin number - -// serialization CONNECTIVITY board -#define SER_CON_RX_PIN NRF_GPIO_PIN_MAP(1,14) // UART RX pin number. -#define SER_CON_TX_PIN NRF_GPIO_PIN_MAP(1,13) // UART TX pin number. -#define SER_CON_CTS_PIN NRF_GPIO_PIN_MAP(1,15) // UART Clear To Send pin number. Not used if HWFC is set to false. -#define SER_CON_RTS_PIN NRF_GPIO_PIN_MAP(0,2) // UART Request To Send pin number. Not used if HWFC is set to false. - - -#define SER_CON_SPIS_SCK_PIN NRF_GPIO_PIN_MAP(0,27) // SPI SCK signal. -#define SER_CON_SPIS_MOSI_PIN NRF_GPIO_PIN_MAP(0,2) // SPI MOSI signal. -#define SER_CON_SPIS_MISO_PIN NRF_GPIO_PIN_MAP(0,26) // SPI MISO signal. -#define SER_CON_SPIS_CSN_PIN NRF_GPIO_PIN_MAP(1,13) // SPI CSN signal. -#define SER_CON_SPIS_RDY_PIN NRF_GPIO_PIN_MAP(1,15) // SPI READY GPIO pin number. -#define SER_CON_SPIS_REQ_PIN NRF_GPIO_PIN_MAP(1,14) // SPI REQUEST GPIO pin number. - -#define SER_CONN_CHIP_RESET_PIN NRF_GPIO_PIN_MAP(1,1) // Pin used to reset connectivity chip - -// Arduino board mappings -#define ARDUINO_SCL_PIN 27 // SCL signal pin -#define ARDUINO_SDA_PIN 26 // SDA signal pin -#define ARDUINO_AREF_PIN 2 // Aref pin - -#define ARDUINO_13_PIN NRF_GPIO_PIN_MAP(1, 15) // Digital pin 13 -#define ARDUINO_12_PIN NRF_GPIO_PIN_MAP(1, 14) // Digital pin 12 -#define ARDUINO_11_PIN NRF_GPIO_PIN_MAP(1, 13) // Digital pin 11 -#define ARDUINO_10_PIN NRF_GPIO_PIN_MAP(1, 12) // Digital pin 10 -#define ARDUINO_9_PIN NRF_GPIO_PIN_MAP(1, 11) // Digital pin 9 -#define ARDUINO_8_PIN NRF_GPIO_PIN_MAP(1, 10) // Digital pin 8 - -#define ARDUINO_7_PIN NRF_GPIO_PIN_MAP(1, 8) // Digital pin 7 -#define ARDUINO_6_PIN NRF_GPIO_PIN_MAP(1, 7) // Digital pin 6 -#define ARDUINO_5_PIN NRF_GPIO_PIN_MAP(1, 6) // Digital pin 5 -#define ARDUINO_4_PIN NRF_GPIO_PIN_MAP(1, 5) // Digital pin 4 -#define ARDUINO_3_PIN NRF_GPIO_PIN_MAP(1, 4) // Digital pin 3 -#define ARDUINO_2_PIN NRF_GPIO_PIN_MAP(1, 3) // Digital pin 2 -#define ARDUINO_1_PIN NRF_GPIO_PIN_MAP(1, 2) // Digital pin 1 -#define ARDUINO_0_PIN NRF_GPIO_PIN_MAP(1, 1) // Digital pin 0 - -#define ARDUINO_A0_PIN 3 // Analog channel 0 -#define ARDUINO_A1_PIN 4 // Analog channel 1 -#define ARDUINO_A2_PIN 28 // Analog channel 2 -#define ARDUINO_A3_PIN 29 // Analog channel 3 -#define ARDUINO_A4_PIN 30 // Analog channel 4 -#define ARDUINO_A5_PIN 31 // Analog channel 5 - - -#ifdef __cplusplus -} -#endif - -#endif // PCA10056_H diff --git a/bsp/boards/nrf52840/sdk/components/boards/pca10059.h b/bsp/boards/nrf52840/sdk/components/boards/pca10059.h deleted file mode 100644 index f4976ba1be..0000000000 --- a/bsp/boards/nrf52840/sdk/components/boards/pca10059.h +++ /dev/null @@ -1,95 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef PCA10059_H -#define PCA10059_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "nrf_gpio.h" - -// LED definitions for PCA10059 -// Each LED color is considered a separate LED -#define LEDS_NUMBER 4 - -#define LED1_G NRF_GPIO_PIN_MAP(0,6) -#define LED2_R NRF_GPIO_PIN_MAP(0,8) -#define LED2_G NRF_GPIO_PIN_MAP(1,9) -#define LED2_B NRF_GPIO_PIN_MAP(0,12) - -#define LED_1 LED1_G -#define LED_2 LED2_R -#define LED_3 LED2_G -#define LED_4 LED2_B - -#define LEDS_ACTIVE_STATE 0 - -#define LEDS_LIST { LED_1, LED_2, LED_3, LED_4 } - -#define LEDS_INV_MASK LEDS_MASK - -#define BSP_LED_0 LED_1 -#define BSP_LED_1 LED_2 -#define BSP_LED_2 LED_3 -#define BSP_LED_3 LED_4 - -// There is only one button for the application -// as the second button is used for a RESET. -#define BUTTONS_NUMBER 1 - -#define BUTTON_1 NRF_GPIO_PIN_MAP(1,6) -#define BUTTON_PULL NRF_GPIO_PIN_PULLUP - -#define BUTTONS_ACTIVE_STATE 0 - -#define BUTTONS_LIST { BUTTON_1 } - -#define BSP_BUTTON_0 BUTTON_1 - -#define BSP_SELF_PINRESET_PIN NRF_GPIO_PIN_MAP(0,19) - -#define HWFC true - -#ifdef __cplusplus -} -#endif - -#endif // PCA10059_H diff --git a/bsp/boards/nrf52840/sdk/components/drivers_nrf/nrf_soc_nosd/nrf_error.h b/bsp/boards/nrf52840/sdk/components/drivers_nrf/nrf_soc_nosd/nrf_error.h deleted file mode 100644 index e97fa069de..0000000000 --- a/bsp/boards/nrf52840/sdk/components/drivers_nrf/nrf_soc_nosd/nrf_error.h +++ /dev/null @@ -1,95 +0,0 @@ -/** - * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -/* Header guard */ - -#ifndef SOFTDEVICE_PRESENT - -/** - @defgroup nrf_error Global Error Codes - @{ - - @brief Global Error definitions -*/ - -#ifndef NRF_ERROR_H__ -#define NRF_ERROR_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup NRF_ERRORS_BASE Error Codes Base number definitions - * @{ */ -#define NRF_ERROR_BASE_NUM (0x0) ///< Global error base -#define NRF_ERROR_SDM_BASE_NUM (0x1000) ///< SDM error base -#define NRF_ERROR_SOC_BASE_NUM (0x2000) ///< SoC error base -#define NRF_ERROR_STK_BASE_NUM (0x3000) ///< STK error base -/** @} */ - -#define NRF_SUCCESS (NRF_ERROR_BASE_NUM + 0) ///< Successful command -#define NRF_ERROR_SVC_HANDLER_MISSING (NRF_ERROR_BASE_NUM + 1) ///< SVC handler is missing -#define NRF_ERROR_SOFTDEVICE_NOT_ENABLED (NRF_ERROR_BASE_NUM + 2) ///< SoftDevice has not been enabled -#define NRF_ERROR_INTERNAL (NRF_ERROR_BASE_NUM + 3) ///< Internal Error -#define NRF_ERROR_NO_MEM (NRF_ERROR_BASE_NUM + 4) ///< No Memory for operation -#define NRF_ERROR_NOT_FOUND (NRF_ERROR_BASE_NUM + 5) ///< Not found -#define NRF_ERROR_NOT_SUPPORTED (NRF_ERROR_BASE_NUM + 6) ///< Not supported -#define NRF_ERROR_INVALID_PARAM (NRF_ERROR_BASE_NUM + 7) ///< Invalid Parameter -#define NRF_ERROR_INVALID_STATE (NRF_ERROR_BASE_NUM + 8) ///< Invalid state, operation disallowed in this state -#define NRF_ERROR_INVALID_LENGTH (NRF_ERROR_BASE_NUM + 9) ///< Invalid Length -#define NRF_ERROR_INVALID_FLAGS (NRF_ERROR_BASE_NUM + 10) ///< Invalid Flags -#define NRF_ERROR_INVALID_DATA (NRF_ERROR_BASE_NUM + 11) ///< Invalid Data -#define NRF_ERROR_DATA_SIZE (NRF_ERROR_BASE_NUM + 12) ///< Data size exceeds limit -#define NRF_ERROR_TIMEOUT (NRF_ERROR_BASE_NUM + 13) ///< Operation timed out -#define NRF_ERROR_NULL (NRF_ERROR_BASE_NUM + 14) ///< Null Pointer -#define NRF_ERROR_FORBIDDEN (NRF_ERROR_BASE_NUM + 15) ///< Forbidden Operation -#define NRF_ERROR_INVALID_ADDR (NRF_ERROR_BASE_NUM + 16) ///< Bad Memory Address -#define NRF_ERROR_BUSY (NRF_ERROR_BASE_NUM + 17) ///< Busy - -#ifdef __cplusplus -} -#endif - -#endif // NRF_ERROR_H__ - -/** - @} -*/ - -#endif // SOFTDEVICE_PRESENT diff --git a/bsp/boards/nrf52840/sdk/components/drivers_nrf/nrf_soc_nosd/nrf_nvic.c b/bsp/boards/nrf52840/sdk/components/drivers_nrf/nrf_soc_nosd/nrf_nvic.c deleted file mode 100644 index a90d90873d..0000000000 --- a/bsp/boards/nrf52840/sdk/components/drivers_nrf/nrf_soc_nosd/nrf_nvic.c +++ /dev/null @@ -1,123 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include -#include "nrf_soc.h" -#include "nrf_error.h" - -static uint8_t m_in_critical_region = 0; - -uint32_t sd_nvic_EnableIRQ(IRQn_Type IRQn) -{ - NVIC_EnableIRQ(IRQn); - return NRF_SUCCESS; -} - -uint32_t sd_nvic_DisableIRQ(IRQn_Type IRQn) -{ - NVIC_DisableIRQ(IRQn); - return NRF_SUCCESS; -} - -uint32_t sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t * p_pending_irq) -{ - if (p_pending_irq != NULL) - { - *p_pending_irq = NVIC_GetPendingIRQ(IRQn); - return NRF_SUCCESS; - } - return NRF_ERROR_NULL; -} - -uint32_t sd_nvic_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC_SetPendingIRQ(IRQn); - return NRF_SUCCESS; -} - -uint32_t sd_nvic_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC_ClearPendingIRQ(IRQn); - return NRF_SUCCESS; -} - -uint32_t sd_nvic_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - NVIC_SetPriority(IRQn, priority); - return NRF_SUCCESS; -} - -uint32_t sd_nvic_GetPriority(IRQn_Type IRQn, uint32_t * p_priority) -{ - if (p_priority != NULL) - { - *p_priority = NVIC_GetPriority(IRQn); - return NRF_SUCCESS; - } - - return NRF_ERROR_NULL; -} - -uint32_t sd_nvic_SystemReset(void) -{ - NVIC_SystemReset(); - return NRF_SUCCESS; -} - -uint32_t sd_nvic_critical_region_enter(uint8_t * p_is_nested_critical_region) -{ - __disable_irq(); - - *p_is_nested_critical_region = (m_in_critical_region != 0); - m_in_critical_region++; - - return NRF_SUCCESS; -} - -uint32_t sd_nvic_critical_region_exit(uint8_t is_nested_critical_region) -{ - m_in_critical_region--; - - if (is_nested_critical_region == 0) - { - m_in_critical_region = 0; - __enable_irq(); - } - return NRF_SUCCESS; -} diff --git a/bsp/boards/nrf52840/sdk/components/drivers_nrf/nrf_soc_nosd/nrf_nvic.h b/bsp/boards/nrf52840/sdk/components/drivers_nrf/nrf_soc_nosd/nrf_nvic.h deleted file mode 100644 index d7daa3df8d..0000000000 --- a/bsp/boards/nrf52840/sdk/components/drivers_nrf/nrf_soc_nosd/nrf_nvic.h +++ /dev/null @@ -1,166 +0,0 @@ -/** - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef NRF_NVIC_H__ -#define NRF_NVIC_H__ - -#include -#include "nrf.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/**@brief Enable External Interrupt. - * @note Corresponds to NVIC_EnableIRQ in CMSIS. - * - * @pre{IRQn is valid and not reserved by the stack} - * - * @param[in] IRQn See the NVIC_EnableIRQ documentation in CMSIS. - * - * @retval ::NRF_SUCCESS The interrupt was enabled. - */ -uint32_t sd_nvic_EnableIRQ(IRQn_Type IRQn); - -/**@brief Disable External Interrupt. - * @note Corresponds to NVIC_DisableIRQ in CMSIS. - * - * @pre{IRQn is valid and not reserved by the stack} - * - * @param[in] IRQn See the NVIC_DisableIRQ documentation in CMSIS - * - * @retval ::NRF_SUCCESS The interrupt was disabled. - */ -uint32_t sd_nvic_DisableIRQ(IRQn_Type IRQn); - -/**@brief Get Pending Interrupt. - * @note Corresponds to NVIC_GetPendingIRQ in CMSIS. - * - * @pre{IRQn is valid and not reserved by the stack} - * - * @param[in] IRQn See the NVIC_GetPendingIRQ documentation in CMSIS. - * @param[out] p_pending_irq Return value from NVIC_GetPendingIRQ. - * - * @retval ::NRF_SUCCESS The interrupt is available for the application. - */ -uint32_t sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t * p_pending_irq); - -/**@brief Set Pending Interrupt. - * @note Corresponds to NVIC_SetPendingIRQ in CMSIS. - * - * @pre{IRQn is valid and not reserved by the stack} - * - * @param[in] IRQn See the NVIC_SetPendingIRQ documentation in CMSIS. - * - * @retval ::NRF_SUCCESS The interrupt is set pending. - */ -uint32_t sd_nvic_SetPendingIRQ(IRQn_Type IRQn); - -/**@brief Clear Pending Interrupt. - * @note Corresponds to NVIC_ClearPendingIRQ in CMSIS. - * - * @pre{IRQn is valid and not reserved by the stack} - * - * @param[in] IRQn See the NVIC_ClearPendingIRQ documentation in CMSIS. - * - * @retval ::NRF_SUCCESS The interrupt pending flag is cleared. - */ -uint32_t sd_nvic_ClearPendingIRQ(IRQn_Type IRQn); - -/**@brief Set Interrupt Priority. - * @note Corresponds to NVIC_SetPriority in CMSIS. - * - * @pre{IRQn is valid and not reserved by the stack} - * @pre{priority is valid and not reserved by the stack} - * - * @param[in] IRQn See the NVIC_SetPriority documentation in CMSIS. - * @param[in] priority A valid IRQ priority for use by the application. - * - * @retval ::NRF_SUCCESS The interrupt and priority level is available for the application. - */ -uint32_t sd_nvic_SetPriority(IRQn_Type IRQn, uint32_t priority); - -/**@brief Get Interrupt Priority. - * @note Corresponds to NVIC_GetPriority in CMSIS. - * - * @pre{IRQn is valid and not reserved by the stack} - * - * @param[in] IRQn See the NVIC_GetPriority documentation in CMSIS. - * @param[out] p_priority Return value from NVIC_GetPriority. - * - * @retval ::NRF_SUCCESS The interrupt priority is returned in p_priority. - */ -uint32_t sd_nvic_GetPriority(IRQn_Type IRQn, uint32_t * p_priority); - -/**@brief System Reset. - * @note Corresponds to NVIC_SystemReset in CMSIS. - * - * @retval ::NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN - */ -uint32_t sd_nvic_SystemReset(void); - -/**@brief Enters critical region. - * - * @post Application interrupts will be disabled. - * @sa sd_nvic_critical_region_exit - * - * @param[out] p_is_nested_critical_region 1: If in a nested critical region. - * 0: Otherwise. - * - * @retval ::NRF_SUCCESS - */ -uint32_t sd_nvic_critical_region_enter(uint8_t * p_is_nested_critical_region); - -/**@brief Exit critical region. - * - * @pre Application has entered a critical region using ::sd_nvic_critical_region_enter. - * @post If not in a nested critical region, the application interrupts will restored to the state before ::sd_nvic_critical_region_enter was called. - * - * @param[in] is_nested_critical_region If this is set to 1, the critical region won't be exited. @sa sd_nvic_critical_region_enter. - * - * @retval ::NRF_SUCCESS - */ -uint32_t sd_nvic_critical_region_exit(uint8_t is_nested_critical_region); - - -#ifdef __cplusplus -} -#endif - -#endif /* NRF_NVIC_H__ */ diff --git a/bsp/boards/nrf52840/sdk/components/drivers_nrf/nrf_soc_nosd/nrf_sdm.h b/bsp/boards/nrf52840/sdk/components/drivers_nrf/nrf_soc_nosd/nrf_sdm.h deleted file mode 100644 index 46e558b2ee..0000000000 --- a/bsp/boards/nrf52840/sdk/components/drivers_nrf/nrf_soc_nosd/nrf_sdm.h +++ /dev/null @@ -1,56 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef NRF_SDM_H__ -#define NRF_SDM_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -#define NRF_FAULT_ID_SD_RANGE_START 0x00000000 /**< SoftDevice ID range start. */ -#define NRF_FAULT_ID_APP_RANGE_START 0x00001000 /**< Application ID range start. */ - -#ifdef __cplusplus -} -#endif -#endif // NRF_SDM_H__ - - diff --git a/bsp/boards/nrf52840/sdk/components/drivers_nrf/nrf_soc_nosd/nrf_soc.c b/bsp/boards/nrf52840/sdk/components/drivers_nrf/nrf_soc_nosd/nrf_soc.c deleted file mode 100644 index b3b712f0f0..0000000000 --- a/bsp/boards/nrf52840/sdk/components/drivers_nrf/nrf_soc_nosd/nrf_soc.c +++ /dev/null @@ -1,48 +0,0 @@ -/** - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include -#include "nrf_soc.h" -#include "nrf_error.h" - -uint32_t sd_app_evt_wait(void) -{ - __WFE(); - return NRF_SUCCESS; -} diff --git a/bsp/boards/nrf52840/sdk/components/drivers_nrf/nrf_soc_nosd/nrf_soc.h b/bsp/boards/nrf52840/sdk/components/drivers_nrf/nrf_soc_nosd/nrf_soc.h deleted file mode 100644 index efe5b8b7a6..0000000000 --- a/bsp/boards/nrf52840/sdk/components/drivers_nrf/nrf_soc_nosd/nrf_soc.h +++ /dev/null @@ -1,80 +0,0 @@ -/** - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef NRF_SOC_H__ -#define NRF_SOC_H__ - -#include -#include "nrf.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/**@brief Waits for an application event. - * - * An application event is either an application interrupt or a pended interrupt when the - * interrupt is disabled. When the interrupt is enabled it will be taken immediately since - * this function will wait in thread mode, then the execution will return in the application's - * main thread. When an interrupt is disabled and gets pended it will return to the application's - * thread main. The application must ensure that the pended flag is cleared using - * ::sd_nvic_ClearPendingIRQ in order to sleep using this function. This is only necessary for - * disabled interrupts, as the interrupt handler will clear the pending flag automatically for - * enabled interrupts. - * - * In order to wake up from disabled interrupts, the SEVONPEND flag has to be set in the Cortex-M0 - * System Control Register (SCR). @sa CMSIS_SCB - * - * @note If an application interrupt has happened since the last time sd_app_evt_wait was - * called this function will return immediately and not go to sleep. This is to avoid race - * conditions that can occur when a flag is updated in the interrupt handler and processed - * in the main loop. - * - * @post An application interrupt has happened or a interrupt pending flag is set. - * - * @retval ::NRF_SUCCESS - */ -uint32_t sd_app_evt_wait(void); - - -#ifdef __cplusplus -} -#endif - -#endif /* NRF_SOC_H__ */ diff --git a/bsp/boards/nrf52840/sdk/components/drivers_nrf/radio_config/radio_config.c b/bsp/boards/nrf52840/sdk/components/drivers_nrf/radio_config/radio_config.c deleted file mode 100644 index a8bbb9c93e..0000000000 --- a/bsp/boards/nrf52840/sdk/components/drivers_nrf/radio_config/radio_config.c +++ /dev/null @@ -1,188 +0,0 @@ -/** - * Copyright (c) 2009 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -/** @file -* @addtogroup nrf_dev_radio_rx_example_main nrf_dev_radio_tx_example_main -* @{ -*/ - -#include "radio_config.h" -#include "nrf_delay.h" - -/* These are set to zero as ShockBurst packets don't have corresponding fields. */ -#define PACKET_S1_FIELD_SIZE (0UL) /**< Packet S1 field size in bits. */ -#define PACKET_S0_FIELD_SIZE (0UL) /**< Packet S0 field size in bits. */ -#define PACKET_LENGTH_FIELD_SIZE (0UL) /**< Packet length field size in bits. */ - -/** - * @brief Function for swapping/mirroring bits in a byte. - * - *@verbatim - * output_bit_7 = input_bit_0 - * output_bit_6 = input_bit_1 - * : - * output_bit_0 = input_bit_7 - *@endverbatim - * - * @param[in] inp is the input byte to be swapped. - * - * @return - * Returns the swapped/mirrored input byte. - */ -static uint32_t swap_bits(uint32_t inp); - -/** - * @brief Function for swapping bits in a 32 bit word for each byte individually. - * - * The bits are swapped as follows: - * @verbatim - * output[31:24] = input[24:31] - * output[23:16] = input[16:23] - * output[15:8] = input[8:15] - * output[7:0] = input[0:7] - * @endverbatim - * @param[in] input is the input word to be swapped. - * - * @return - * Returns the swapped input byte. - */ -static uint32_t bytewise_bitswap(uint32_t inp); - -static uint32_t swap_bits(uint32_t inp) -{ - uint32_t i; - uint32_t retval = 0; - - inp = (inp & 0x000000FFUL); - - for (i = 0; i < 8; i++) - { - retval |= ((inp >> i) & 0x01) << (7 - i); - } - - return retval; -} - - -static uint32_t bytewise_bitswap(uint32_t inp) -{ - return (swap_bits(inp >> 24) << 24) - | (swap_bits(inp >> 16) << 16) - | (swap_bits(inp >> 8) << 8) - | (swap_bits(inp)); -} - - -/** - * @brief Function for configuring the radio to operate in ShockBurst compatible mode. - * - * To configure the application running on nRF24L series devices: - * - * @verbatim - * uint8_t tx_address[5] = { 0xC0, 0x01, 0x23, 0x45, 0x67 }; - * hal_nrf_set_rf_channel(7); - * hal_nrf_set_address_width(HAL_NRF_AW_5BYTES); - * hal_nrf_set_address(HAL_NRF_TX, tx_address); - * hal_nrf_set_address(HAL_NRF_PIPE0, tx_address); - * hal_nrf_open_pipe(0, false); - * hal_nrf_set_datarate(HAL_NRF_1MBPS); - * hal_nrf_set_crc_mode(HAL_NRF_CRC_16BIT); - * hal_nrf_setup_dynamic_payload(0xFF); - * hal_nrf_enable_dynamic_payload(false); - * @endverbatim - * - * When transmitting packets with hal_nrf_write_tx_payload(const uint8_t *tx_pload, uint8_t length), - * match the length with PACKET_STATIC_LENGTH. - * hal_nrf_write_tx_payload(payload, PACKET_STATIC_LENGTH); - * -*/ -void radio_configure() -{ - // Radio config - NRF_RADIO->TXPOWER = (RADIO_TXPOWER_TXPOWER_0dBm << RADIO_TXPOWER_TXPOWER_Pos); - NRF_RADIO->FREQUENCY = 7UL; // Frequency bin 7, 2407MHz - NRF_RADIO->MODE = (RADIO_MODE_MODE_Nrf_1Mbit << RADIO_MODE_MODE_Pos); - - // Radio address config - NRF_RADIO->PREFIX0 = - ((uint32_t)swap_bits(0xC3) << 24) // Prefix byte of address 3 converted to nRF24L series format - | ((uint32_t)swap_bits(0xC2) << 16) // Prefix byte of address 2 converted to nRF24L series format - | ((uint32_t)swap_bits(0xC1) << 8) // Prefix byte of address 1 converted to nRF24L series format - | ((uint32_t)swap_bits(0xC0) << 0); // Prefix byte of address 0 converted to nRF24L series format - - NRF_RADIO->PREFIX1 = - ((uint32_t)swap_bits(0xC7) << 24) // Prefix byte of address 7 converted to nRF24L series format - | ((uint32_t)swap_bits(0xC6) << 16) // Prefix byte of address 6 converted to nRF24L series format - | ((uint32_t)swap_bits(0xC4) << 0); // Prefix byte of address 4 converted to nRF24L series format - - NRF_RADIO->BASE0 = bytewise_bitswap(0x01234567UL); // Base address for prefix 0 converted to nRF24L series format - NRF_RADIO->BASE1 = bytewise_bitswap(0x89ABCDEFUL); // Base address for prefix 1-7 converted to nRF24L series format - - NRF_RADIO->TXADDRESS = 0x00UL; // Set device address 0 to use when transmitting - NRF_RADIO->RXADDRESSES = 0x01UL; // Enable device address 0 to use to select which addresses to receive - - // Packet configuration - NRF_RADIO->PCNF0 = (PACKET_S1_FIELD_SIZE << RADIO_PCNF0_S1LEN_Pos) | - (PACKET_S0_FIELD_SIZE << RADIO_PCNF0_S0LEN_Pos) | - (PACKET_LENGTH_FIELD_SIZE << RADIO_PCNF0_LFLEN_Pos); //lint !e845 "The right argument to operator '|' is certain to be 0" - - // Packet configuration - NRF_RADIO->PCNF1 = (RADIO_PCNF1_WHITEEN_Disabled << RADIO_PCNF1_WHITEEN_Pos) | - (RADIO_PCNF1_ENDIAN_Big << RADIO_PCNF1_ENDIAN_Pos) | - (PACKET_BASE_ADDRESS_LENGTH << RADIO_PCNF1_BALEN_Pos) | - (PACKET_STATIC_LENGTH << RADIO_PCNF1_STATLEN_Pos) | - (PACKET_PAYLOAD_MAXSIZE << RADIO_PCNF1_MAXLEN_Pos); //lint !e845 "The right argument to operator '|' is certain to be 0" - - // CRC Config - NRF_RADIO->CRCCNF = (RADIO_CRCCNF_LEN_Two << RADIO_CRCCNF_LEN_Pos); // Number of checksum bits - if ((NRF_RADIO->CRCCNF & RADIO_CRCCNF_LEN_Msk) == (RADIO_CRCCNF_LEN_Two << RADIO_CRCCNF_LEN_Pos)) - { - NRF_RADIO->CRCINIT = 0xFFFFUL; // Initial value - NRF_RADIO->CRCPOLY = 0x11021UL; // CRC poly: x^16 + x^12^x^5 + 1 - } - else if ((NRF_RADIO->CRCCNF & RADIO_CRCCNF_LEN_Msk) == (RADIO_CRCCNF_LEN_One << RADIO_CRCCNF_LEN_Pos)) - { - NRF_RADIO->CRCINIT = 0xFFUL; // Initial value - NRF_RADIO->CRCPOLY = 0x107UL; // CRC poly: x^8 + x^2^x^1 + 1 - } -} - -/** - * @} - */ diff --git a/bsp/boards/nrf52840/sdk/components/drivers_nrf/radio_config/radio_config.h b/bsp/boards/nrf52840/sdk/components/drivers_nrf/radio_config/radio_config.h deleted file mode 100644 index 75226dd01b..0000000000 --- a/bsp/boards/nrf52840/sdk/components/drivers_nrf/radio_config/radio_config.h +++ /dev/null @@ -1,58 +0,0 @@ -/** - * Copyright (c) 2009 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef RADIO_CONFIG_H -#define RADIO_CONFIG_H - -#ifdef __cplusplus -extern "C" { -#endif - -#define PACKET_BASE_ADDRESS_LENGTH (4UL) //!< Packet base address length field size in bytes -#define PACKET_STATIC_LENGTH (1UL) //!< Packet static length in bytes -#define PACKET_PAYLOAD_MAXSIZE (PACKET_STATIC_LENGTH) //!< Packet payload maximum size in bytes - -void radio_configure(void); - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsp/boards/nrf52840/sdk/components/libraries/atomic/nrf_atomic.c b/bsp/boards/nrf52840/sdk/components/libraries/atomic/nrf_atomic.c deleted file mode 100644 index 7ee52ad4a7..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/atomic/nrf_atomic.c +++ /dev/null @@ -1,447 +0,0 @@ -/** - * Copyright (c) 2018 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include "nrf_atomic.h" - -#ifndef NRF_ATOMIC_USE_BUILD_IN -#if (defined(__GNUC__) && defined(WIN32)) - #define NRF_ATOMIC_USE_BUILD_IN 1 -#else - #define NRF_ATOMIC_USE_BUILD_IN 0 -#endif -#endif // NRF_ATOMIC_USE_BUILD_IN - -#if ((__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)) -#define STREX_LDREX_PRESENT -#else -#include "app_util_platform.h" -#endif - - -#if (NRF_ATOMIC_USE_BUILD_IN == 0) && defined(STREX_LDREX_PRESENT) -#include "nrf_atomic_internal.h" -#endif - -uint32_t nrf_atomic_u32_fetch_store(nrf_atomic_u32_t * p_data, uint32_t value) -{ -#if NRF_ATOMIC_USE_BUILD_IN - return __atomic_exchange_n(p_data, value, __ATOMIC_SEQ_CST); - -#elif defined(STREX_LDREX_PRESENT) - uint32_t old_val; - uint32_t new_val; - NRF_ATOMIC_OP(mov, old_val, new_val, p_data, value); - - UNUSED_PARAMETER(old_val); - UNUSED_PARAMETER(new_val); - return old_val; -#else - CRITICAL_REGION_ENTER(); - uint32_t old_val = *p_data; - *p_data = value; - CRITICAL_REGION_EXIT(); - return old_val; -#endif //NRF_ATOMIC_USE_BUILD_IN -} - -uint32_t nrf_atomic_u32_store(nrf_atomic_u32_t * p_data, uint32_t value) -{ -#if NRF_ATOMIC_USE_BUILD_IN - __atomic_store_n(p_data, value, __ATOMIC_SEQ_CST); - return value; -#elif defined(STREX_LDREX_PRESENT) - uint32_t old_val; - uint32_t new_val; - - NRF_ATOMIC_OP(mov, old_val, new_val, p_data, value); - - UNUSED_PARAMETER(old_val); - UNUSED_PARAMETER(new_val); - return new_val; -#else - CRITICAL_REGION_ENTER(); - *p_data = value; - CRITICAL_REGION_EXIT(); - return value; -#endif //NRF_ATOMIC_USE_BUILD_IN -} - -uint32_t nrf_atomic_u32_fetch_or(nrf_atomic_u32_t * p_data, uint32_t value) -{ -#if NRF_ATOMIC_USE_BUILD_IN - return __atomic_fetch_or(p_data, value, __ATOMIC_SEQ_CST); -#elif defined(STREX_LDREX_PRESENT) - uint32_t old_val; - uint32_t new_val; - - NRF_ATOMIC_OP(orr, old_val, new_val, p_data, value); - UNUSED_PARAMETER(old_val); - UNUSED_PARAMETER(new_val); - return old_val; -#else - CRITICAL_REGION_ENTER(); - uint32_t old_val = *p_data; - *p_data |= value; - CRITICAL_REGION_EXIT(); - return old_val; -#endif //NRF_ATOMIC_USE_BUILD_IN -} - -uint32_t nrf_atomic_u32_or(nrf_atomic_u32_t * p_data, uint32_t value) -{ -#if NRF_ATOMIC_USE_BUILD_IN - return __atomic_or_fetch(p_data, value, __ATOMIC_SEQ_CST); -#elif defined(STREX_LDREX_PRESENT) - uint32_t old_val; - uint32_t new_val; - - NRF_ATOMIC_OP(orr, old_val, new_val, p_data, value); - UNUSED_PARAMETER(old_val); - UNUSED_PARAMETER(new_val); - return new_val; -#else - CRITICAL_REGION_ENTER(); - *p_data |= value; - uint32_t new_value = *p_data; - CRITICAL_REGION_EXIT(); - return new_value; -#endif //NRF_ATOMIC_USE_BUILD_IN -} - -uint32_t nrf_atomic_u32_fetch_and(nrf_atomic_u32_t * p_data, uint32_t value) -{ -#if NRF_ATOMIC_USE_BUILD_IN - return __atomic_fetch_and(p_data, value, __ATOMIC_SEQ_CST); -#elif defined(STREX_LDREX_PRESENT) - uint32_t old_val; - uint32_t new_val; - - NRF_ATOMIC_OP(and, old_val, new_val, p_data, value); - UNUSED_PARAMETER(old_val); - UNUSED_PARAMETER(new_val); - return old_val; -#else - CRITICAL_REGION_ENTER(); - uint32_t old_val = *p_data; - *p_data &= value; - CRITICAL_REGION_EXIT(); - return old_val; -#endif //NRF_ATOMIC_USE_BUILD_IN -} - -uint32_t nrf_atomic_u32_and(nrf_atomic_u32_t * p_data, uint32_t value) -{ -#if NRF_ATOMIC_USE_BUILD_IN - return __atomic_and_fetch(p_data, value, __ATOMIC_SEQ_CST); -#elif defined(STREX_LDREX_PRESENT) - uint32_t old_val; - uint32_t new_val; - - NRF_ATOMIC_OP(and, old_val, new_val, p_data, value); - UNUSED_PARAMETER(old_val); - UNUSED_PARAMETER(new_val); - return new_val; -#else - CRITICAL_REGION_ENTER(); - *p_data &= value; - uint32_t new_value = *p_data; - CRITICAL_REGION_EXIT(); - return new_value; -#endif //NRF_ATOMIC_USE_BUILD_IN -} - -uint32_t nrf_atomic_u32_fetch_xor(nrf_atomic_u32_t * p_data, uint32_t value) -{ -#if NRF_ATOMIC_USE_BUILD_IN - return __atomic_fetch_xor(p_data, value, __ATOMIC_SEQ_CST); -#elif defined(STREX_LDREX_PRESENT) - uint32_t old_val; - uint32_t new_val; - - NRF_ATOMIC_OP(eor, old_val, new_val, p_data, value); - UNUSED_PARAMETER(old_val); - UNUSED_PARAMETER(new_val); - return old_val; -#else - CRITICAL_REGION_ENTER(); - uint32_t old_val = *p_data; - *p_data ^= value; - CRITICAL_REGION_EXIT(); - return old_val; -#endif //NRF_ATOMIC_USE_BUILD_IN -} - -uint32_t nrf_atomic_u32_xor(nrf_atomic_u32_t * p_data, uint32_t value) -{ -#if NRF_ATOMIC_USE_BUILD_IN - return __atomic_xor_fetch(p_data, value, __ATOMIC_SEQ_CST); -#elif defined(STREX_LDREX_PRESENT) - uint32_t old_val; - uint32_t new_val; - - NRF_ATOMIC_OP(eor, old_val, new_val, p_data, value); - UNUSED_PARAMETER(old_val); - UNUSED_PARAMETER(new_val); - return new_val; -#else - CRITICAL_REGION_ENTER(); - *p_data ^= value; - uint32_t new_value = *p_data; - CRITICAL_REGION_EXIT(); - return new_value; -#endif //NRF_ATOMIC_USE_BUILD_IN -} - -uint32_t nrf_atomic_u32_fetch_add(nrf_atomic_u32_t * p_data, uint32_t value) -{ -#if NRF_ATOMIC_USE_BUILD_IN - return __atomic_fetch_add(p_data, value, __ATOMIC_SEQ_CST); -#elif defined(STREX_LDREX_PRESENT) - uint32_t old_val; - uint32_t new_val; - - NRF_ATOMIC_OP(add, old_val, new_val, p_data, value); - UNUSED_PARAMETER(old_val); - UNUSED_PARAMETER(new_val); - return old_val; -#else - CRITICAL_REGION_ENTER(); - uint32_t old_val = *p_data; - *p_data += value; - CRITICAL_REGION_EXIT(); - return old_val; -#endif //NRF_ATOMIC_USE_BUILD_IN -} - -uint32_t nrf_atomic_u32_add(nrf_atomic_u32_t * p_data, uint32_t value) -{ -#if NRF_ATOMIC_USE_BUILD_IN - return __atomic_add_fetch(p_data, value, __ATOMIC_SEQ_CST); -#elif defined(STREX_LDREX_PRESENT) - uint32_t old_val; - uint32_t new_val; - - NRF_ATOMIC_OP(add, old_val, new_val, p_data, value); - UNUSED_PARAMETER(old_val); - UNUSED_PARAMETER(new_val); - return new_val; -#else - CRITICAL_REGION_ENTER(); - *p_data += value; - uint32_t new_value = *p_data; - CRITICAL_REGION_EXIT(); - return new_value; -#endif //NRF_ATOMIC_USE_BUILD_IN -} - -uint32_t nrf_atomic_u32_fetch_sub(nrf_atomic_u32_t * p_data, uint32_t value) -{ -#if NRF_ATOMIC_USE_BUILD_IN - return __atomic_fetch_sub(p_data, value, __ATOMIC_SEQ_CST); -#elif defined(STREX_LDREX_PRESENT) - uint32_t old_val; - uint32_t new_val; - - NRF_ATOMIC_OP(sub, old_val, new_val, p_data, value); - UNUSED_PARAMETER(old_val); - UNUSED_PARAMETER(new_val); - return old_val; -#else - CRITICAL_REGION_ENTER(); - uint32_t old_val = *p_data; - *p_data -= value; - CRITICAL_REGION_EXIT(); - return old_val; -#endif //NRF_ATOMIC_USE_BUILD_IN -} - -uint32_t nrf_atomic_u32_sub(nrf_atomic_u32_t * p_data, uint32_t value) -{ -#if NRF_ATOMIC_USE_BUILD_IN - return __atomic_sub_fetch(p_data, value, __ATOMIC_SEQ_CST); -#elif defined(STREX_LDREX_PRESENT) - uint32_t old_val; - uint32_t new_val; - - NRF_ATOMIC_OP(sub, old_val, new_val, p_data, value); - UNUSED_PARAMETER(old_val); - UNUSED_PARAMETER(new_val); - return new_val; -#else - CRITICAL_REGION_ENTER(); - *p_data -= value; - uint32_t new_value = *p_data; - CRITICAL_REGION_EXIT(); - return new_value; -#endif //NRF_ATOMIC_USE_BUILD_IN -} - -bool nrf_atomic_u32_cmp_exch(nrf_atomic_u32_t * p_data, - uint32_t * p_expected, - uint32_t desired) -{ -#if NRF_ATOMIC_USE_BUILD_IN - return __atomic_compare_exchange(p_data, - p_expected, - &desired, - 1, - __ATOMIC_SEQ_CST, - __ATOMIC_SEQ_CST); -#elif defined(STREX_LDREX_PRESENT) - return nrf_atomic_internal_cmp_exch(p_data, p_expected, desired); -#else - CRITICAL_REGION_ENTER(); - if(*p_data == *p_expected) - { - *p_data = desired; - return true; - } - else - { - *p_expected = *p_data; - return false; - } - CRITICAL_REGION_EXIT(); -#endif -} - -uint32_t nrf_atomic_u32_fetch_sub_hs(nrf_atomic_u32_t * p_data, uint32_t value) -{ -#if NRF_ATOMIC_USE_BUILD_IN - uint32_t expected = *p_data; - uint32_t new_val; - bool success; - - do - { - if (expected >= value) - { - new_val = expected - value; - } - else - { - new_val = expected; - } - success = __atomic_compare_exchange(p_data, - &expected, - &new_val, - 1, - __ATOMIC_SEQ_CST, - __ATOMIC_SEQ_CST); - } while(!success); - return expected; -#elif defined(STREX_LDREX_PRESENT) - uint32_t old_val; - uint32_t new_val; - - NRF_ATOMIC_OP(sub_hs, old_val, new_val, p_data, value); - UNUSED_PARAMETER(old_val); - UNUSED_PARAMETER(new_val); - return old_val; -#else - CRITICAL_REGION_ENTER(); - uint32_t old_val = *p_data; - *p_data -= value; - CRITICAL_REGION_EXIT(); - return old_val; -#endif //NRF_ATOMIC_USE_BUILD_IN -} - -uint32_t nrf_atomic_u32_sub_hs(nrf_atomic_u32_t * p_data, uint32_t value) -{ -#if NRF_ATOMIC_USE_BUILD_IN - uint32_t expected = *p_data; - uint32_t new_val; - bool success; - - do - { - if (expected >= value) - { - new_val = expected - value; - } - else - { - new_val = expected; - } - success = __atomic_compare_exchange(p_data, - &expected, - &new_val, - 1, - __ATOMIC_SEQ_CST, - __ATOMIC_SEQ_CST); - } while(!success); - return new_val; -#elif defined(STREX_LDREX_PRESENT) - uint32_t old_val; - uint32_t new_val; - - NRF_ATOMIC_OP(sub_hs, old_val, new_val, p_data, value); - UNUSED_PARAMETER(old_val); - UNUSED_PARAMETER(new_val); - return new_val; -#else - CRITICAL_REGION_ENTER(); - *p_data -= value; - uint32_t new_value = *p_data; - CRITICAL_REGION_EXIT(); - return new_value; -#endif //NRF_ATOMIC_USE_BUILD_IN -} - -uint32_t nrf_atomic_flag_set_fetch(nrf_atomic_flag_t * p_data) -{ - return nrf_atomic_u32_fetch_or(p_data, 1); -} - -uint32_t nrf_atomic_flag_set(nrf_atomic_flag_t * p_data) -{ - return nrf_atomic_u32_or(p_data, 1); -} - -uint32_t nrf_atomic_flag_clear_fetch(nrf_atomic_flag_t * p_data) -{ - return nrf_atomic_u32_fetch_and(p_data, 0); -} - -uint32_t nrf_atomic_flag_clear(nrf_atomic_flag_t * p_data) -{ - return nrf_atomic_u32_and(p_data, 0); -} - diff --git a/bsp/boards/nrf52840/sdk/components/libraries/atomic/nrf_atomic.h b/bsp/boards/nrf52840/sdk/components/libraries/atomic/nrf_atomic.h deleted file mode 100644 index b7560a463e..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/atomic/nrf_atomic.h +++ /dev/null @@ -1,274 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -/**@file - * - * @defgroup nrf_atomic Atomic operations API - * @ingroup app_common - * @{ - * - * @brief @tagAPI52 This module implements C11 stdatomic.h simplified API. - At this point only Cortex-M3/M4 cores are supported (LDREX/STREX instructions). - * Atomic types are limited to @ref nrf_atomic_u32_t and @ref nrf_atomic_flag_t. - */ - -#ifndef NRF_ATOMIC_H__ -#define NRF_ATOMIC_H__ - -#include "sdk_common.h" - -/** - * @brief Atomic 32 bit unsigned type - * */ -typedef volatile uint32_t nrf_atomic_u32_t; - -/** - * @brief Atomic 1 bit flag type (technically 32 bit) - * */ -typedef volatile uint32_t nrf_atomic_flag_t; - - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Stores value to an atomic object - * - * @param[in] p_data Atomic memory pointer - * @param[in] value Value to store - * - * @return Old value stored into atomic object - * */ -uint32_t nrf_atomic_u32_fetch_store(nrf_atomic_u32_t * p_data, uint32_t value); - -/** - * @brief Stores value to an atomic object - * - * @param[in] p_data Atomic memory pointer - * @param[in] value Value to store - * - * @return New value stored into atomic object - * */ -uint32_t nrf_atomic_u32_store(nrf_atomic_u32_t * p_data, uint32_t value); - -/** - * @brief Logical OR operation on an atomic object - * - * @param[in] p_data Atomic memory pointer - * @param[in] value Value of second operand OR operation - * - * @return Old value stored into atomic object - * */ -uint32_t nrf_atomic_u32_fetch_or(nrf_atomic_u32_t * p_data, uint32_t value); - -/** - * @brief Logical OR operation on an atomic object - * - * @param[in] p_data Atomic memory pointer - * @param[in] value Value of second operand OR operation - * - * @return New value stored into atomic object - * */ -uint32_t nrf_atomic_u32_or(nrf_atomic_u32_t * p_data, uint32_t value); - -/** - * @brief Logical AND operation on an atomic object - * - * @param[in] p_data Atomic memory pointer - * @param[in] value Value of second operand AND operation - * - * @return Old value stored into atomic object - * */ -uint32_t nrf_atomic_u32_fetch_and(nrf_atomic_u32_t * p_data, uint32_t value); - -/** - * @brief Logical AND operation on an atomic object - * - * @param[in] p_data Atomic memory pointer - * @param[in] value Value of second operand AND operation - * - * @return New value stored into atomic object - * */ -uint32_t nrf_atomic_u32_and(nrf_atomic_u32_t * p_data, uint32_t value); - -/** - * @brief Logical XOR operation on an atomic object - * - * @param[in] p_data Atomic memory pointer - * @param[in] value Value of second operand XOR operation - * - * @return Old value stored into atomic object - * */ -uint32_t nrf_atomic_u32_fetch_xor(nrf_atomic_u32_t * p_data, uint32_t value); - -/** - * @brief Logical XOR operation on an atomic object - * - * @param[in] p_data Atomic memory pointer - * @param[in] value Value of second operand XOR operation - * - * @return New value stored into atomic object - * */ -uint32_t nrf_atomic_u32_xor(nrf_atomic_u32_t * p_data, uint32_t value); - -/** - * @brief Arithmetic ADD operation on an atomic object - * - * @param[in] p_data Atomic memory pointer - * @param[in] value Value of second operand ADD operation - * - * @return Old value stored into atomic object - * */ -uint32_t nrf_atomic_u32_fetch_add(nrf_atomic_u32_t * p_data, uint32_t value); - -/** - * @brief Arithmetic ADD operation on an atomic object - * - * @param[in] p_data Atomic memory pointer - * @param[in] value Value of second operand ADD operation - * - * @return New value stored into atomic object - * */ -uint32_t nrf_atomic_u32_add(nrf_atomic_u32_t * p_data, uint32_t value); - -/** - * @brief Arithmetic SUB operation on an atomic object - * - * @param[in] p_data Atomic memory pointer - * @param[in] value Value of second operand SUB operation - * - * @return Old value stored into atomic object - * */ -uint32_t nrf_atomic_u32_fetch_sub(nrf_atomic_u32_t * p_data, uint32_t value); - -/** - * @brief Arithmetic SUB operation on an atomic object - * - * @param[in] p_data Atomic memory pointer - * @param[in] value Value of second operand SUB operation - * - * @return New value stored into atomic object - * */ -uint32_t nrf_atomic_u32_sub(nrf_atomic_u32_t * p_data, uint32_t value); - -/** - * @brief If value at pointer is equal to expected value, changes value at pointer to desired - * - * Atomically compares the value pointed to by p_data with the value pointed to by p_expected, - * and if those are equal, replaces the former with desired. Otherwise, loads the actual value - * pointed to by p_data into *p_expected. - * - * @param p_data Atomic memory pointer to test and modify. - * @param p_expected Pointer to test value. - * @param desired Value to be stored to atomic memory. - * - * @retval true *p_data was equal to *p_expected - * @retval false *p_data was not equal to *p_expected - */ -bool nrf_atomic_u32_cmp_exch(nrf_atomic_u32_t * p_data, - uint32_t * p_expected, - uint32_t desired); - -/** - * @brief Arithmetic SUB operation on an atomic object performed if object >= value. - * - * @param[in] p_data Atomic memory pointer - * @param[in] value Value of second operand SUB operation - * - * @return Old value stored into atomic object - * */ -uint32_t nrf_atomic_u32_fetch_sub_hs(nrf_atomic_u32_t * p_data, uint32_t value); - -/** - * @brief Arithmetic SUB operation on an atomic object performed if object >= value. - * - * @param[in] p_data Atomic memory pointer - * @param[in] value Value of second operand SUB operation - * - * @return New value stored into atomic object - * */ -uint32_t nrf_atomic_u32_sub_hs(nrf_atomic_u32_t * p_data, uint32_t value); - -/**************************************************************************************************/ - -/** - * @brief Logic one bit flag set operation on an atomic object - * - * @param[in] p_data Atomic flag memory pointer - * - * @return Old flag value - * */ -uint32_t nrf_atomic_flag_set_fetch(nrf_atomic_flag_t * p_data); - -/** - * @brief Logic one bit flag set operation on an atomic object - * - * @param[in] p_data Atomic flag memory pointer - * - * @return New flag value - * */ -uint32_t nrf_atomic_flag_set(nrf_atomic_flag_t * p_data); - -/** - * @brief Logic one bit flag clear operation on an atomic object - * - * @param[in] p_data Atomic flag memory pointer - * - * @return Old flag value - * */ -uint32_t nrf_atomic_flag_clear_fetch(nrf_atomic_flag_t * p_data); - -/** - * @brief Logic one bit flag clear operation on an atomic object - * - * @param[in] p_data Atomic flag memory pointer - * - * @return New flag value - * */ -uint32_t nrf_atomic_flag_clear(nrf_atomic_flag_t * p_data); - -#ifdef __cplusplus -} -#endif - -#endif /* NRF_ATOMIC_H__ */ - -/** @} */ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/atomic/nrf_atomic_internal.h b/bsp/boards/nrf52840/sdk/components/libraries/atomic/nrf_atomic_internal.h deleted file mode 100644 index 54cb897656..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/atomic/nrf_atomic_internal.h +++ /dev/null @@ -1,343 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef NRF_ATOMIC_INTERNAL_H__ -#define NRF_ATOMIC_INTERNAL_H__ - -#include "sdk_common.h" -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * - * @defgroup nrf_atomic_internal Atomic operations internals - * @ingroup nrf_atomic - * @{ - * - */ - -/* Only Cortex M cores > 3 support LDREX/STREX instructions*/ -#if ((__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)) == 0 -#error "Unsupported core version" -#endif - -#if defined ( __CC_ARM ) -static __asm uint32_t nrf_atomic_internal_mov(nrf_atomic_u32_t * p_ptr, - uint32_t value, - uint32_t * p_new) -{ - /* The base standard provides for passing arguments in core registers (r0-r3) and on the stack. - * Registers r4 and r5 have to be saved on stack. Note that only even number of register push are - * allowed. This is a requirement of the Procedure Call Standard for the ARM Architecture [AAPCS]. - * */ - push {r4, r5} - mov r4, r0 - -loop_mov - ldrex r0, [r4] - mov r5, r1 - strex r3, r5, [r4] - cmp r3, #0 - bne loop_mov - - str r5, [r2] - pop {r4, r5} - bx lr -} - - -static __asm uint32_t nrf_atomic_internal_orr(nrf_atomic_u32_t * p_ptr, - uint32_t value, - uint32_t * p_new) -{ - push {r4, r5} - mov r4, r0 - -loop_orr - ldrex r0, [r4] - orr r5, r0, r1 - strex r3, r5, [r4] - cmp r3, #0 - bne loop_orr - - str r5, [r2] - pop {r4, r5} - bx lr -} - -static __asm uint32_t nrf_atomic_internal_and(nrf_atomic_u32_t * p_ptr, - uint32_t value, - uint32_t * p_new) -{ - push {r4, r5} - mov r4, r0 - -loop_and - ldrex r0, [r4] - and r5, r0, r1 - strex r3, r5, [r4] - cmp r3, #0 - bne loop_and - - str r5, [r2] - pop {r4, r5} - bx lr -} - -static __asm uint32_t nrf_atomic_internal_eor(nrf_atomic_u32_t * p_ptr, - uint32_t value, - uint32_t * p_new) -{ - push {r4, r5} - mov r4, r0 - -loop_eor - ldrex r0, [r4] - eor r5, r0, r1 - strex r3, r5, [r4] - cmp r3, #0 - bne loop_eor - - str r5, [r2] - pop {r4, r5} - bx lr -} - -static __asm uint32_t nrf_atomic_internal_add(nrf_atomic_u32_t * p_ptr, - uint32_t value, - uint32_t * p_new) -{ - push {r4, r5} - mov r4, r0 - -loop_add - ldrex r0, [r4] - add r5, r0, r1 - strex r3, r5, [r4] - cmp r3, #0 - bne loop_add - - str r5, [r2] - pop {r4, r5} - bx lr -} - -static __asm uint32_t nrf_atomic_internal_sub(nrf_atomic_u32_t * p_ptr, - uint32_t value, - uint32_t * p_new) -{ - push {r4, r5} - mov r4, r0 - -loop_sub - ldrex r0, [r4] - sub r5, r0, r1 - strex r3, r5, [r4] - cmp r3, #0 - bne loop_sub - - str r5, [r2] - pop {r4, r5} - bx lr -} - -static __asm bool nrf_atomic_internal_cmp_exch(nrf_atomic_u32_t * p_data, - uint32_t * p_expected, - uint32_t value) -{ -#define RET_REG r0 -#define P_EXPC r1 -#define VALUE r2 -#define STR_RES r3 -#define P_DATA r4 -#define EXPC_VAL r5 -#define ACT_VAL r6 - - push {r4-r6} - mov P_DATA, r0 - mov RET_REG, #0 - -loop_cmp_exch - ldrex ACT_VAL, [P_DATA] - ldr EXPC_VAL, [P_EXPC] - cmp ACT_VAL, EXPC_VAL - ittee eq - strexeq STR_RES, VALUE, [P_DATA] - moveq RET_REG, #1 - strexne STR_RES, ACT_VAL, [P_DATA] - strne ACT_VAL, [P_EXPC] - cmp STR_RES, #0 - itt ne - movne RET_REG, #0 - bne loop_cmp_exch - - pop {r4-r6} - bx lr - -#undef RET_REG -#undef P_EXPC -#undef VALUE -#undef STR_RES -#undef P_DATA -#undef EXPC_VAL -#undef ACT_VAL -} - -static __asm uint32_t nrf_atomic_internal_sub_hs(nrf_atomic_u32_t * p_ptr, - uint32_t value, - uint32_t * p_new) -{ - push {r4, r5} - mov r4, r0 - -loop_sub_ge - ldrex r0, [r4] - cmp r0, r1 - ite hs - subhs r5, r0, r1 - movlo r5, r0 - strex r3, r5, [r4] - cmp r3, #0 - bne loop_sub_ge - - str r5, [r2] - pop {r4, r5} - bx lr -} - - -#define NRF_ATOMIC_OP(asm_op, old_val, new_val, ptr, value) \ - old_val = nrf_atomic_internal_##asm_op(ptr, value, &new_val) - -#elif defined ( __ICCARM__ ) || defined ( __GNUC__ ) - -/** - * @brief Atomic operation generic macro - * @param[in] asm_op operation: mov, orr, and, eor, add, sub - * @param[out] old_val atomic object output (uint32_t), value before operation - * @param[out] new_val atomic object output (uint32_t), value after operation - * @param[in] value atomic operation operand - * */ -#define NRF_ATOMIC_OP(asm_op, old_val, new_val, ptr, value) \ -{ \ - uint32_t str_res; \ - __ASM volatile( \ - "1: ldrex %["#old_val"], [%["#ptr"]]\n" \ - NRF_ATOMIC_OP_##asm_op(new_val, old_val, value) \ - " strex %[str_res], %["#new_val"], [%["#ptr"]]\n" \ - " teq %[str_res], #0\n" \ - " bne.n 1b" \ - : \ - [old_val]"=&r" (old_val), \ - [new_val]"=&r" (new_val), \ - [str_res]"=&r" (str_res) \ - : \ - [ptr]"r" (ptr), \ - [value]"r" (value) \ - : "cc"); \ - UNUSED_PARAMETER(str_res); \ -} - -#define NRF_ATOMIC_OP_mov(new_val, old_val, value) "mov %["#new_val"], %["#value"]\n" -#define NRF_ATOMIC_OP_orr(new_val, old_val, value) "orr %["#new_val"], %["#old_val"], %["#value"]\n" -#define NRF_ATOMIC_OP_and(new_val, old_val, value) "and %["#new_val"], %["#old_val"], %["#value"]\n" -#define NRF_ATOMIC_OP_eor(new_val, old_val, value) "eor %["#new_val"], %["#old_val"], %["#value"]\n" -#define NRF_ATOMIC_OP_add(new_val, old_val, value) "add %["#new_val"], %["#old_val"], %["#value"]\n" -#define NRF_ATOMIC_OP_sub(new_val, old_val, value) "sub %["#new_val"], %["#old_val"], %["#value"]\n" -#define NRF_ATOMIC_OP_sub_hs(new_val, old_val, value) \ - "cmp %["#old_val"], %["#value"]\n " \ - "ite hs\n" \ - "subhs %["#new_val"], %["#old_val"], %["#value"]\n" \ - "movlo %["#new_val"], %["#old_val"]\n" - -static inline bool nrf_atomic_internal_cmp_exch(nrf_atomic_u32_t * p_data, - uint32_t * p_expected, - uint32_t value) -{ - bool res = false; - uint32_t str_res = 0; - uint32_t act_val = 0; - uint32_t exp_val = 0; - UNUSED_VARIABLE(str_res); - UNUSED_VARIABLE(act_val); - UNUSED_VARIABLE(exp_val); - __ASM volatile( - "1: ldrex %[act_val], [%[ptr]]\n" - " ldr %[exp_val], [%[expc]]\n" - " cmp %[act_val], %[exp_val]\n" - " ittee eq\n" - " strexeq %[str_res], %[value], [%[ptr]]\n" - " moveq %[res], #1\n" - " strexne %[str_res], %[act_val], [%[ptr]]\n" - " strne %[act_val], [%[expc]]\n" - " cmp %[str_res], #0\n" - " itt ne\n" - " movne %[res], #0\n" - " bne.n 1b" - : - [res] "=&r" (res), - [exp_val] "=&r" (exp_val), - [act_val] "=&r" (act_val), - [str_res] "=&r" (str_res) - : - "0" (res), - "1" (exp_val), - "2" (act_val), - [expc] "r" (p_expected), - [ptr] "r" (p_data), - [value] "r" (value) - : "cc"); - return res; -} - -#else -#error "Unsupported compiler" -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* NRF_ATOMIC_INTERNAL_H__ */ - -/** @} */ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/atomic/nrf_atomic_sanity_check.h b/bsp/boards/nrf52840/sdk/components/libraries/atomic/nrf_atomic_sanity_check.h deleted file mode 100644 index db17470510..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/atomic/nrf_atomic_sanity_check.h +++ /dev/null @@ -1,153 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef NRF_ATOMIC_SANITY_CHECK_H__ -#define NRF_ATOMIC_SANITY_CHECK_H__ - -#include "nrf_atomic.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Quick sanity check of nrf_atomic API - * */ -static inline void nrf_atomic_sanity_check(void) -{ -#if defined(DEBUG_NRF) || defined(DEBUG_NRF_USER) - nrf_atomic_u32_t val; - nrf_atomic_u32_t flag; - - /*Fetch version tests*/ - val = 0; - ASSERT(nrf_atomic_u32_store_fetch(&val, 10) == 0); - ASSERT(nrf_atomic_u32_store_fetch(&val, 0) == 10); - - val = 0; - ASSERT(nrf_atomic_u32_or_fetch(&val, 1 << 16) == 0); - ASSERT(nrf_atomic_u32_or_fetch(&val, 1 << 5) == ((1 << 16))); - ASSERT(nrf_atomic_u32_or_fetch(&val, 1 << 5) == ((1 << 16) | (1 << 5))); - ASSERT(nrf_atomic_u32_or_fetch(&val, 0) == ((1 << 16) | (1 << 5))); - ASSERT(nrf_atomic_u32_or_fetch(&val, 0xFFFFFFFF) == ((1 << 16) | (1 << 5))); - ASSERT(nrf_atomic_u32_or_fetch(&val, 0xFFFFFFFF) == (0xFFFFFFFF)); - - val = 0xFFFFFFFF; - ASSERT(nrf_atomic_u32_and_fetch(&val, ~(1 << 16)) == 0xFFFFFFFF); - ASSERT(nrf_atomic_u32_and_fetch(&val, ~(1 << 5)) == (0xFFFFFFFF & ~((1 << 16)))); - ASSERT(nrf_atomic_u32_and_fetch(&val, 0) == (0xFFFFFFFF & ~(((1 << 16) | (1 << 5))))); - ASSERT(nrf_atomic_u32_and_fetch(&val, 0xFFFFFFFF) == (0)); - - val = 0; - ASSERT(nrf_atomic_u32_xor_fetch(&val, (1 << 16)) == 0); - ASSERT(nrf_atomic_u32_xor_fetch(&val, (1 << 5)) == ((1 << 16))); - ASSERT(nrf_atomic_u32_xor_fetch(&val, 0) == ((1 << 16) | (1 << 5))); - ASSERT(nrf_atomic_u32_xor_fetch(&val, (1 << 16) | (1 << 5)) == ((1 << 16) | (1 << 5))); - ASSERT(nrf_atomic_u32_xor_fetch(&val, 0) == (0)); - - val = 0; - ASSERT(nrf_atomic_u32_add_fetch(&val, 100) == 0); - ASSERT(nrf_atomic_u32_add_fetch(&val, 100) == 100); - ASSERT(nrf_atomic_u32_add_fetch(&val, 1 << 24) == 200); - ASSERT(nrf_atomic_u32_add_fetch(&val, 0) == (200 + (1 << 24))); - ASSERT(nrf_atomic_u32_add_fetch(&val, 0xFFFFFFFF) == (200 + (1 << 24))); - ASSERT(nrf_atomic_u32_add_fetch(&val, 0) == (200 - 1 + (1 << 24))); - - val = 1000; - ASSERT(nrf_atomic_u32_sub_fetch(&val, 100) == 1000); - ASSERT(nrf_atomic_u32_sub_fetch(&val, 100) == 900); - ASSERT(nrf_atomic_u32_sub_fetch(&val, 0) == 800); - ASSERT(nrf_atomic_u32_sub_fetch(&val, 0xFFFFFFFF) == 800); - ASSERT(nrf_atomic_u32_sub_fetch(&val, 0) == 801); - - flag = 0; - ASSERT(nrf_atomic_flag_set_fetch(&flag) == 0); - ASSERT(nrf_atomic_flag_set_fetch(&flag) == 1); - ASSERT(nrf_atomic_flag_clear_fetch(&flag) == 1); - ASSERT(nrf_atomic_flag_clear_fetch(&flag) == 0); - - /*No fetch version tests*/ - val = 0; - ASSERT(nrf_atomic_u32_store(&val, 10) == 10); - ASSERT(nrf_atomic_u32_store(&val, 0) == 0); - - val = 0; - ASSERT(nrf_atomic_u32_or(&val, 1 << 16) == 1 << 16); - ASSERT(nrf_atomic_u32_or(&val, 1 << 5) == ((1 << 16) | (1 << 5))); - ASSERT(nrf_atomic_u32_or(&val, 1 << 5) == ((1 << 16) | (1 << 5))); - ASSERT(nrf_atomic_u32_or(&val, 0) == ((1 << 16) | (1 << 5))); - ASSERT(nrf_atomic_u32_or(&val, 0xFFFFFFFF) == 0xFFFFFFFF); - - val = 0xFFFFFFFF; - ASSERT(nrf_atomic_u32_and(&val, ~(1 << 16)) == (0xFFFFFFFF & ~((1 << 16)))); - ASSERT(nrf_atomic_u32_and(&val, ~(1 << 5)) == (0xFFFFFFFF & ~(((1 << 16) | (1 << 5))))); - ASSERT(nrf_atomic_u32_and(&val, 0) == 0); - - val = 0; - ASSERT(nrf_atomic_u32_xor(&val, (1 << 16)) == ((1 << 16))); - ASSERT(nrf_atomic_u32_xor(&val, (1 << 5)) == ((1 << 16) | (1 << 5))); - ASSERT(nrf_atomic_u32_xor(&val, 0) == ((1 << 16) | (1 << 5))); - ASSERT(nrf_atomic_u32_xor(&val, (1 << 16) | (1 << 5)) == 0); - - val = 0; - ASSERT(nrf_atomic_u32_add(&val, 100) == 100); - ASSERT(nrf_atomic_u32_add(&val, 100) == 200); - ASSERT(nrf_atomic_u32_add(&val, 1 << 24) == (200 + (1 << 24))); - ASSERT(nrf_atomic_u32_add(&val, 0) == (200 + (1 << 24))); - ASSERT(nrf_atomic_u32_add(&val, 0xFFFFFFFF) == (200 - 1 + (1 << 24))); - - val = 1000; - ASSERT(nrf_atomic_u32_sub(&val, 100) == 900); - ASSERT(nrf_atomic_u32_sub(&val, 100) == 800); - ASSERT(nrf_atomic_u32_sub(&val, 0) == 800); - ASSERT(nrf_atomic_u32_sub(&val, 0xFFFFFFFF) == 801); - - flag = 0; - ASSERT(nrf_atomic_flag_set(&flag) == 1); - ASSERT(nrf_atomic_flag_set(&flag) == 1); - ASSERT(nrf_atomic_flag_clear(&flag) == 0); - ASSERT(nrf_atomic_flag_clear(&flag) == 0); -#endif -} - -#ifdef __cplusplus -} -#endif - -#endif /* NRF_ATOMIC_SANITY_CHECK_H__ */ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/balloc/nrf_balloc.c b/bsp/boards/nrf52840/sdk/components/libraries/balloc/nrf_balloc.c deleted file mode 100644 index da60b9a56f..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/balloc/nrf_balloc.c +++ /dev/null @@ -1,399 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include "sdk_common.h" - #if NRF_MODULE_ENABLED(NRF_BALLOC) - -#include "nrf_section.h" -#include "nrf_balloc.h" -#include "app_util_platform.h" - - -#if NRF_BALLOC_CONFIG_LOG_ENABLED - #define NRF_LOG_LEVEL NRF_BALLOC_CONFIG_LOG_LEVEL - #define NRF_LOG_INITIAL_LEVEL NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL - #define NRF_LOG_INFO_COLOR NRF_BALLOC_CONFIG_INFO_COLOR - #define NRF_LOG_DEBUG_COLOR NRF_BALLOC_CONFIG_DEBUG_COLOR -#else - #define NRF_LOG_LEVEL 0 -#endif // NRF_BALLOC_CONFIG_LOG_ENABLED -#include "nrf_log.h" - -#define HEAD_GUARD_FILL 0xBAADF00D /**< Magic number used to mark head guard.*/ -#define TAIL_GUARD_FILL 0xBAADCAFE /**< Magic number used to mark tail guard.*/ -#define FREE_MEM_FILL 0xBAADBAAD /**< Magic number used to mark free memory.*/ - -#if NRF_BALLOC_CONFIG_DEBUG_ENABLED -#define POOL_ID(_p_pool) _p_pool->p_name -#define POOL_MARKER "%s" -#else -#define POOL_ID(_p_pool) _p_pool -#define POOL_MARKER "0x%08X" -#endif - -NRF_SECTION_DEF(nrf_balloc, nrf_balloc_t); - -#if NRF_BALLOC_CLI_CMDS -#include "nrf_cli.h" - -static void nrf_balloc_status(nrf_cli_t const * p_cli, size_t argc, char **argv) -{ - UNUSED_PARAMETER(argv); - - if (nrf_cli_help_requested(p_cli)) - { - nrf_cli_help_print(p_cli, NULL, 0); - return; - } - - if (argc > 1) - { - nrf_cli_fprintf(p_cli, NRF_CLI_ERROR, "Bad argument count"); - return; - } - - uint32_t num_of_instances = NRF_SECTION_ITEM_COUNT(nrf_balloc, nrf_balloc_t); - uint32_t i; - - for (i = 0; i < num_of_instances; i++) - { - const nrf_balloc_t * p_instance = NRF_SECTION_ITEM_GET(nrf_balloc, nrf_balloc_t, i); - - uint32_t element_size = NRF_BALLOC_ELEMENT_SIZE(p_instance); - uint32_t dbg_addon = p_instance->block_size - element_size; - uint32_t pool_size = p_instance->p_stack_limit - p_instance->p_stack_base; - uint32_t max_util = nrf_balloc_max_utilization_get(p_instance); - uint32_t util = nrf_balloc_utilization_get(p_instance); - const char * p_name = p_instance->p_name; - nrf_cli_fprintf(p_cli, NRF_CLI_NORMAL, - "%s\r\n\t- Element size:\t%d + %d bytes of debug information\r\n" - "\t- Usage:\t%u%% (%u out of %u elements)\r\n" - "\t- Maximum:\t%u%% (%u out of %u elements)\r\n\r\n", - p_name, element_size, dbg_addon, - 100ul * util/pool_size, util,pool_size, - 100ul * max_util/pool_size, max_util,pool_size); - - } -} -// Register "balloc" command and its subcommands in CLI. -NRF_CLI_CREATE_STATIC_SUBCMD_SET(nrf_balloc_commands) -{ - NRF_CLI_CMD(status, NULL, "Print status of balloc instances.", nrf_balloc_status), - NRF_CLI_SUBCMD_SET_END -}; - -NRF_CLI_CMD_REGISTER(balloc, &nrf_balloc_commands, "Commands for BALLOC management", nrf_balloc_status); -#endif //NRF_BALLOC_CLI_CMDS - -#if NRF_BALLOC_CONFIG_DEBUG_ENABLED -/**@brief Validate block memory, prepare block guards, and calculate pointer to the element. - * - * @param[in] p_pool Pointer to the memory pool. - * @param[in] p_head Pointer to the beginning of the block. - * - * @return Pointer to the element. - */ -__STATIC_INLINE void * nrf_balloc_block_unwrap(nrf_balloc_t const * p_pool, void * p_head) -{ - ASSERT((p_pool != NULL) && ((p_pool->block_size % sizeof(uint32_t)) == 0)); - ASSERT((p_head != NULL) && (((uint32_t)(p_head) % sizeof(uint32_t)) == 0)); - - uint32_t head_words = NRF_BALLOC_DEBUG_HEAD_GUARD_WORDS_GET(p_pool->debug_flags); - uint32_t tail_words = NRF_BALLOC_DEBUG_TAIL_GUARD_WORDS_GET(p_pool->debug_flags); - - uint32_t * p_tail = (uint32_t *)((size_t)(p_head) + p_pool->block_size); - uint32_t * p_element = (uint32_t *)p_head + head_words; - - if (NRF_BALLOC_DEBUG_DATA_TRASHING_CHECK_GET(p_pool->debug_flags)) - { - for (uint32_t * ptr = p_head; ptr < p_tail; ptr++) - { - if (*ptr != FREE_MEM_FILL) - { - NRF_LOG_INST_ERROR(p_pool->p_log, - "Detected free memory corruption at 0x%08X (0x%08X != 0x%08X)", - ptr, *ptr, FREE_MEM_FILL); - APP_ERROR_CHECK_BOOL(false); - } - } - } - - for (uint32_t * ptr = p_head; ptr < p_element; ptr++) - { - *ptr = HEAD_GUARD_FILL; - } - - for (uint32_t * ptr = ( p_tail - tail_words); ptr < p_tail; ptr++) - { - *ptr = TAIL_GUARD_FILL; - } - - return p_element; -} - -/**@brief Calculate pointer to the block, validate block guards, and mark block memory as free. - * - * @param[in] p_pool Pointer to the memory pool. - * @param[in] p_element Pointer to the element. - * - * @return Pointer to the beginning of the block. - */ -__STATIC_INLINE void * nrf_balloc_element_wrap(nrf_balloc_t const * p_pool, void * p_element) -{ - ASSERT((p_pool != NULL) && ((p_pool->block_size % sizeof(uint32_t)) == 0)); - ASSERT((p_element != NULL) && (((uint32_t)(p_element) % sizeof(uint32_t)) == 0)); - - uint32_t head_words = NRF_BALLOC_DEBUG_HEAD_GUARD_WORDS_GET(p_pool->debug_flags); - uint32_t tail_words = NRF_BALLOC_DEBUG_TAIL_GUARD_WORDS_GET(p_pool->debug_flags); - - uint32_t * p_head = (uint32_t *)p_element - head_words; - uint32_t * p_tail = (uint32_t *)((size_t)(p_head) + p_pool->block_size); - - for (uint32_t * ptr = p_head; ptr < (uint32_t *)p_element; ptr++) - { - if (*ptr != HEAD_GUARD_FILL) - { - NRF_LOG_INST_ERROR(p_pool->p_log, - "Detected Head Guard corruption at 0x%08X (0x%08X != 0x%08X)", - ptr, *ptr, HEAD_GUARD_FILL); - APP_ERROR_CHECK_BOOL(false); - } - } - - for (uint32_t * ptr = ( p_tail - tail_words); ptr < p_tail; ptr++) - { - if (*ptr != TAIL_GUARD_FILL) - { - NRF_LOG_INST_ERROR(p_pool->p_log, - "Detected Tail Guard corruption at 0x%08X (0x%08X != 0x%08X)", - ptr, *ptr, TAIL_GUARD_FILL); - APP_ERROR_CHECK_BOOL(false); - } - } - - if (NRF_BALLOC_DEBUG_DATA_TRASHING_CHECK_GET(p_pool->debug_flags)) - { - for (uint32_t * ptr = p_head; ptr < p_tail; ptr++) - { - *ptr = FREE_MEM_FILL; - } - } - - return p_head; -} - -#endif // NRF_BALLOC_CONFIG_DEBUG_ENABLED - -/**@brief Convert block index to a pointer. - * - * @param[in] p_pool Pointer to the memory pool. - * @param[in] idx Index of the block. - * - * @return Pointer to the beginning of the block. - */ -static void * nrf_balloc_idx2block(nrf_balloc_t const * p_pool, uint8_t idx) -{ - ASSERT(p_pool != NULL); - return (uint8_t *)(p_pool->p_memory_begin) + ((size_t)(idx) * p_pool->block_size); -} - -/**@brief Convert block pointer to index. - * - * @param[in] p_pool Pointer to the memory pool. - * @param[in] p_block Pointer to the beginning of the block. - * - * @return Index of the block. - */ -static uint8_t nrf_balloc_block2idx(nrf_balloc_t const * p_pool, void const * p_block) -{ - ASSERT(p_pool != NULL); - return ((size_t)(p_block) - (size_t)(p_pool->p_memory_begin)) / p_pool->block_size; -} - -ret_code_t nrf_balloc_init(nrf_balloc_t const * p_pool) -{ - uint8_t pool_size; - - VERIFY_PARAM_NOT_NULL(p_pool); - - ASSERT(p_pool->p_cb); - ASSERT(p_pool->p_stack_base); - ASSERT(p_pool->p_stack_limit); - ASSERT(p_pool->p_memory_begin); - ASSERT(p_pool->block_size); - - pool_size = p_pool->p_stack_limit - p_pool->p_stack_base; - -#if NRF_BALLOC_CONFIG_DEBUG_ENABLED - void *p_memory_end = (uint8_t *)(p_pool->p_memory_begin) + (pool_size * p_pool->block_size); - if (NRF_BALLOC_DEBUG_DATA_TRASHING_CHECK_GET(p_pool->debug_flags)) - { - for (uint32_t * ptr = p_pool->p_memory_begin; ptr < (uint32_t *)(p_memory_end); ptr++) - { - *ptr = FREE_MEM_FILL; - } - } -#endif - - NRF_LOG_INST_INFO(p_pool->p_log, "Initialized (size: %u x %u = %u bytes)", - pool_size, - p_pool->block_size, - pool_size * p_pool->block_size); - - p_pool->p_cb->p_stack_pointer = p_pool->p_stack_base; - while (pool_size--) - { - *(p_pool->p_cb->p_stack_pointer)++ = pool_size; - } - - p_pool->p_cb->max_utilization = 0; - - return NRF_SUCCESS; -} - -void * nrf_balloc_alloc(nrf_balloc_t const * p_pool) -{ - ASSERT(p_pool != NULL); - - void * p_block = NULL; - - CRITICAL_REGION_ENTER(); - - if (p_pool->p_cb->p_stack_pointer > p_pool->p_stack_base) - { - // Allocate block. - p_block = nrf_balloc_idx2block(p_pool, *--(p_pool->p_cb->p_stack_pointer)); - - // Update utilization statistics. - uint8_t utilization = p_pool->p_stack_limit - p_pool->p_cb->p_stack_pointer; - if (p_pool->p_cb->max_utilization < utilization) - { - p_pool->p_cb->max_utilization = utilization; - } - } - - CRITICAL_REGION_EXIT(); - -#if NRF_BALLOC_CONFIG_DEBUG_ENABLED - if (p_block != NULL) - { - p_block = nrf_balloc_block_unwrap(p_pool, p_block); - } -#endif - - NRF_LOG_INST_DEBUG(p_pool->p_log, "Allocating element: 0x%08X", p_block); - - return p_block; -} - -void nrf_balloc_free(nrf_balloc_t const * p_pool, void * p_element) -{ - ASSERT(p_pool != NULL); - ASSERT(p_element != NULL) - - NRF_LOG_INST_DEBUG(p_pool->p_log, "Freeing element: 0x%08X", p_element); - -#if NRF_BALLOC_CONFIG_DEBUG_ENABLED - void * p_block = nrf_balloc_element_wrap(p_pool, p_element); - - // These checks could be done outside critical region as they use only pool configuration data. - if (NRF_BALLOC_DEBUG_BASIC_CHECKS_GET(p_pool->debug_flags)) - { - uint8_t pool_size = p_pool->p_stack_limit - p_pool->p_stack_base; - void *p_memory_end = (uint8_t *)(p_pool->p_memory_begin) + (pool_size * p_pool->block_size); - - // Check if the element belongs to this pool. - if ((p_block < p_pool->p_memory_begin) || (p_block >= p_memory_end)) - { - NRF_LOG_INST_ERROR(p_pool->p_log, - "Attempted to free element (0x%08X) that does not belong to the pool.", - p_element); - APP_ERROR_CHECK_BOOL(false); - } - - // Check if the pointer is valid. - if ((((size_t)(p_block) - (size_t)(p_pool->p_memory_begin)) % p_pool->block_size) != 0) - { - NRF_LOG_INST_ERROR(p_pool->p_log, - "Attempted to free corrupted element address (0x%08X).", p_element); - APP_ERROR_CHECK_BOOL(false); - } - } -#else - void * p_block = p_element; -#endif // NRF_BALLOC_CONFIG_DEBUG_ENABLED - - CRITICAL_REGION_ENTER(); - -#if NRF_BALLOC_CONFIG_DEBUG_ENABLED - // These checks have to be done in critical region as they use p_pool->p_stack_pointer. - if (NRF_BALLOC_DEBUG_BASIC_CHECKS_GET(p_pool->debug_flags)) - { - // Check for allocated/free ballance. - if (p_pool->p_cb->p_stack_pointer >= p_pool->p_stack_limit) - { - NRF_LOG_INST_ERROR(p_pool->p_log, - "Attempted to free an element (0x%08X) while the pool is full.", - p_element); - APP_ERROR_CHECK_BOOL(false); - } - } - - if (NRF_BALLOC_DEBUG_DOUBLE_FREE_CHECK_GET(p_pool->debug_flags)) - { - // Check for double free. - for (uint8_t * p_idx = p_pool->p_stack_base; p_idx < p_pool->p_cb->p_stack_pointer; p_idx++) - { - if (nrf_balloc_idx2block(p_pool, *p_idx) == p_block) - { - NRF_LOG_INST_ERROR(p_pool->p_log, "Attempted to double-free an element (0x%08X).", - p_element); - APP_ERROR_CHECK_BOOL(false); - } - } - } -#endif // NRF_BALLOC_CONFIG_DEBUG_ENABLED - - // Free the element. - *(p_pool->p_cb->p_stack_pointer)++ = nrf_balloc_block2idx(p_pool, p_block); - - CRITICAL_REGION_EXIT(); -} - -#endif // NRF_MODULE_ENABLED(NRF_BALLOC) diff --git a/bsp/boards/nrf52840/sdk/components/libraries/balloc/nrf_balloc.h b/bsp/boards/nrf52840/sdk/components/libraries/balloc/nrf_balloc.h deleted file mode 100644 index d62c1f74a1..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/balloc/nrf_balloc.h +++ /dev/null @@ -1,351 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -/** - * @defgroup nrf_balloc Block memory allocator - * @{ - * @ingroup app_common - * @brief This module handles block memory allocator features. - */ - - -#ifndef NRF_BALLOC_H__ -#define NRF_BALLOC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "sdk_errors.h" -#include "sdk_config.h" -#include "app_util_platform.h" -#include "app_util.h" -#include "nrf_log_instance.h" -#include "nrf_section.h" - -/** @brief Name of the module used for logger messaging. - */ -#define NRF_BALLOC_LOG_NAME balloc - -#if NRF_BALLOC_CONFIG_DEBUG_ENABLED || NRF_BALLOC_CLI_CMDS -#define NRF_BALLOC_HAS_NAME 1 -#else -#define NRF_BALLOC_HAS_NAME 0 -#endif - -/**@defgroup NRF_BALLOC_DEBUG Macros for preparing debug flags for block allocator module. - * @{ */ -#define NRF_BALLOC_DEBUG_HEAD_GUARD_WORDS_SET(words) (((words) & 0xFF) << 0) -#define NRF_BALLOC_DEBUG_HEAD_GUARD_WORDS_GET(flags) (((flags) >> 0) & 0xFF) -#define NRF_BALLOC_DEBUG_TAIL_GUARD_WORDS_SET(words) (((words) & 0xFF) << 8) -#define NRF_BALLOC_DEBUG_TAIL_GUARD_WORDS_GET(flags) (((flags) >> 8) & 0xFF) - -#define NRF_BALLOC_DEBUG_BASIC_CHECKS_SET(enable) (!!(enable) << 16) -#define NRF_BALLOC_DEBUG_BASIC_CHECKS_GET(flags) (flags & (1 << 16)) -#define NRF_BALLOC_DEBUG_DOUBLE_FREE_CHECK_SET(enable) (!!(enable) << 17) -#define NRF_BALLOC_DEBUG_DOUBLE_FREE_CHECK_GET(flags) (flags & (1 << 17)) -#define NRF_BALLOC_DEBUG_DATA_TRASHING_CHECK_SET(enable) (!!(enable) << 18) -#define NRF_BALLOC_DEBUG_DATA_TRASHING_CHECK_GET(flags) (flags & (1 << 18)) -/**@} */ - -/**@brief Default debug flags for @ref nrf_balloc. This is used by the @ref NRF_BALLOC_DEF macro. - * Flags can be changed in @ref sdk_config. - */ -#if NRF_BALLOC_CONFIG_DEBUG_ENABLED - #define NRF_BALLOC_DEFAULT_DEBUG_FLAGS \ - ( \ - NRF_BALLOC_DEBUG_HEAD_GUARD_WORDS_SET(NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS) | \ - NRF_BALLOC_DEBUG_TAIL_GUARD_WORDS_SET(NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS) | \ - NRF_BALLOC_DEBUG_BASIC_CHECKS_SET(NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED) | \ - NRF_BALLOC_DEBUG_DOUBLE_FREE_CHECK_SET(NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED) | \ - NRF_BALLOC_DEBUG_DATA_TRASHING_CHECK_SET(NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED) \ - ) -#else - #define NRF_BALLOC_DEFAULT_DEBUG_FLAGS 0 -#endif // NRF_BALLOC_CONFIG_DEBUG_ENABLED - -/**@brief Block memory allocator control block.*/ -typedef struct -{ - uint8_t * p_stack_pointer; //!< Current allocation stack pointer. - uint8_t max_utilization; //!< Maximum utilization of the memory pool. -} nrf_balloc_cb_t; - -/**@brief Block memory allocator pool instance. The pool is made of elements of the same size. */ -typedef struct -{ - nrf_balloc_cb_t * p_cb; //!< Pointer to the instance control block. - uint8_t * p_stack_base; //!< Base of the allocation stack. - /**< - * Stack is used to store handlers to not allocated elements. - */ - uint8_t * p_stack_limit; //!< Maximum possible value of the allocation stack pointer. - void * p_memory_begin; //!< Pointer to the start of the memory pool. - /**< - * Memory is used as a heap for blocks. - */ - NRF_LOG_INSTANCE_PTR_DECLARE(p_log) //!< Pointer to instance of the logger object (Conditionally compiled). -#if NRF_BALLOC_HAS_NAME - const char * p_name; //!< Pointer to string with pool name. -#endif -#if NRF_BALLOC_CONFIG_DEBUG_ENABLED - uint32_t debug_flags; //!< Debugging settings. - /**< - * Debug flag should be created by @ref NRF_BALLOC_DEBUG. - */ -#endif // NRF_BALLOC_CONFIG_DEBUG_ENABLED - uint16_t block_size; //!< Size of the allocated block (including debug overhead). - /**< - * Single block contains user element with header and tail - * words. - */ -} nrf_balloc_t; - -/**@brief Get total memory consumed by single block (element size with overhead caused by debug - * flags). - * - * @param[in] _element_size Size of an element. - * @param[in] _debug_flags Debug flags. - */ -#if NRF_BALLOC_CONFIG_DEBUG_ENABLED - #define NRF_BALLOC_BLOCK_SIZE(_element_size, _debug_flags) \ - ( \ - (sizeof(uint32_t) * NRF_BALLOC_DEBUG_HEAD_GUARD_WORDS_GET(_debug_flags)) + \ - ALIGN_NUM(sizeof(uint32_t), (_element_size)) + \ - (sizeof(uint32_t) * NRF_BALLOC_DEBUG_TAIL_GUARD_WORDS_GET(_debug_flags)) \ - ) -#else - #define NRF_BALLOC_BLOCK_SIZE(_element_size, _debug_flags) \ - ALIGN_NUM(sizeof(uint32_t), (_element_size)) -#endif // NRF_BALLOC_CONFIG_DEBUG_ENABLED - - -/**@brief Get element size ( excluding debugging overhead is present) - * flags). - * - * @param[in] _p_balloc Pointer to balloc instance. - */ -#if NRF_BALLOC_CONFIG_DEBUG_ENABLED -#define NRF_BALLOC_ELEMENT_SIZE(_p_balloc) \ - (ALIGN_NUM(sizeof(uint32_t), (_p_balloc)->block_size) - \ - ((sizeof(uint32_t) * NRF_BALLOC_DEBUG_HEAD_GUARD_WORDS_GET((_p_balloc)->debug_flags)) + \ - (sizeof(uint32_t) * NRF_BALLOC_DEBUG_TAIL_GUARD_WORDS_GET((_p_balloc)->debug_flags)))) -#else -#define NRF_BALLOC_ELEMENT_SIZE(_p_balloc) \ - (_p_balloc)->block_size -#endif // NRF_BALLOC_CONFIG_DEBUG_ENABLED - -#if NRF_BALLOC_CONFIG_DEBUG_ENABLED -#define __NRF_BALLOC_ASSIGN_DEBUG_FLAGS(_debug_flags) .debug_flags = (_debug_flags), -#else -#define __NRF_BALLOC_ASSIGN_DEBUG_FLAGS(_debug_flags) -#endif - -#if NRF_BALLOC_HAS_NAME -#define __NRF_BALLOC_ASSIGN_POOL_NAME(_name) .p_name = STRINGIFY(_name), -#else -#define __NRF_BALLOC_ASSIGN_POOL_NAME(_name) -#endif - - -/**@brief Create a block allocator instance with custom debug flags. - * - * @note This macro reserves memory for the given block allocator instance. - * - * @param[in] _name Name of the allocator. - * @param[in] _element_size Size of one element. - * @param[in] _pool_size Size of the pool. - * @param[in] _debug_flags Debug flags (@ref NRF_BALLOC_DEBUG). - */ -#define NRF_BALLOC_DBG_DEF(_name, _element_size, _pool_size, _debug_flags) \ - STATIC_ASSERT((_pool_size) <= UINT8_MAX); \ - static uint8_t CONCAT_2(_name, _nrf_balloc_pool_stack)[(_pool_size)]; \ - static uint32_t CONCAT_2(_name,_nrf_balloc_pool_mem) \ - [NRF_BALLOC_BLOCK_SIZE(_element_size, _debug_flags) * (_pool_size) / sizeof(uint32_t)]; \ - static nrf_balloc_cb_t CONCAT_2(_name,_nrf_balloc_cb); \ - NRF_LOG_INSTANCE_REGISTER(NRF_BALLOC_LOG_NAME, _name, \ - NRF_BALLOC_CONFIG_INFO_COLOR, \ - NRF_BALLOC_CONFIG_DEBUG_COLOR, \ - NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL, \ - NRF_BALLOC_CONFIG_LOG_ENABLED ? \ - NRF_BALLOC_CONFIG_LOG_LEVEL : NRF_LOG_SEVERITY_NONE); \ - NRF_SECTION_ITEM_REGISTER(nrf_balloc, const nrf_balloc_t _name) = \ - { \ - .p_cb = &CONCAT_2(_name,_nrf_balloc_cb), \ - .p_stack_base = CONCAT_2(_name,_nrf_balloc_pool_stack), \ - .p_stack_limit = CONCAT_2(_name,_nrf_balloc_pool_stack) + (_pool_size), \ - .p_memory_begin = CONCAT_2(_name,_nrf_balloc_pool_mem), \ - .block_size = NRF_BALLOC_BLOCK_SIZE(_element_size, _debug_flags), \ - \ - NRF_LOG_INSTANCE_PTR_INIT(p_log, NRF_BALLOC_LOG_NAME, _name) \ - __NRF_BALLOC_ASSIGN_POOL_NAME(_name) \ - __NRF_BALLOC_ASSIGN_DEBUG_FLAGS(_debug_flags) \ - } - -/**@brief Create a block allocator instance. - * - * @note This macro reserves memory for the given block allocator instance. - * - * @param[in] _name Name of the allocator. - * @param[in] _element_size Size of one element. - * @param[in] _pool_size Size of the pool. - */ -#define NRF_BALLOC_DEF(_name, _element_size, _pool_size) \ - NRF_BALLOC_DBG_DEF(_name, _element_size, _pool_size, NRF_BALLOC_DEFAULT_DEBUG_FLAGS) - -/**@brief Create a block allocator interface. - * - * @param[in] _type Type which is allocated. - * @param[in] _name Name of the allocator. - */ -#define NRF_BALLOC_INTERFACE_DEC(_type, _name) \ - _type * CONCAT_2(_name,_alloc)(void); \ - void CONCAT_2(_name,_free)(_type * p_element) - -/**@brief Define a custom block allocator interface. - * - * @param[in] _attr Function attribute that will be added to allocator function definition. - * @param[in] _type Type which is allocated. - * @param[in] _name Name of the allocator. - * @param[in] _p_pool Pool from which data will be allocated. - */ -#define NRF_BALLOC_INTERFACE_CUSTOM_DEF(_attr, _type, _name, _p_pool) \ - _attr _type * CONCAT_2(_name,_alloc)(void) \ - { \ - GCC_PRAGMA("GCC diagnostic push") \ - GCC_PRAGMA("GCC diagnostic ignored \"-Waddress\"") \ - ASSERT((_p_pool) != NULL); \ - ASSERT((_p_pool)->block_size >= \ - NRF_BALLOC_BLOCK_SIZE(sizeof(_type), (_p_pool)->debug_flags)); \ - GCC_PRAGMA("GCC diagnostic pop") \ - return (_type *)(nrf_balloc_alloc(_p_pool)); \ - } \ - \ - _attr void CONCAT_2(_name,_free)(_type * p_element) \ - { \ - GCC_PRAGMA("GCC diagnostic push") \ - GCC_PRAGMA("GCC diagnostic ignored \"-Waddress\"") \ - ASSERT((_p_pool) != NULL); \ - ASSERT((_p_pool)->block_size >= \ - NRF_BALLOC_BLOCK_SIZE(sizeof(_type), (_p_pool)->debug_flags)); \ - GCC_PRAGMA("GCC diagnostic pop") \ - nrf_balloc_free((_p_pool), p_element); \ - } - -/**@brief Define block allocator interface. - * - * @param[in] _type Type which is allocated. - * @param[in] _name Name of the allocator. - * @param[in] _p_pool Pool from which data will be allocated. - */ -#define NRF_BALLOC_INTERFACE_DEF(_type, _name, _p_pool) \ - NRF_BALLOC_INTERFACE_CUSTOM_DEF(/* empty */, _type, _name, _p_pool) - -/**@brief Define a local block allocator interface. - * - * @param[in] _type Type which is allocated. - * @param[in] _name Name of the allocator. - * @param[in] _p_pool Pool from which data will be allocated. - */ -#define NRF_BALLOC_INTERFACE_LOCAL_DEF(_type, _name, _p_pool) \ - NRF_BALLOC_INTERFACE_CUSTOM_DEF(static, _type, _name, _p_pool) - -/**@brief Function for initializing a block memory allocator pool. - * - * @param[out] p_pool Pointer to the pool that is to be initialized. - * - * @return NRF_SUCCESS on success, otherwise error code. - */ -ret_code_t nrf_balloc_init(nrf_balloc_t const * p_pool); - -/**@brief Function for allocating an element from the pool. - * - * @note This module guarantees that the returned memory is aligned to 4. - * - * @param[in] p_pool Pointer to the memory pool from which the element will be allocated. - * - * @return Allocated element or NULL if the specified pool is empty. - */ -void * nrf_balloc_alloc(nrf_balloc_t const * p_pool); - -/**@brief Function for freeing an element back to the pool. - * - * @param[in] p_pool Pointer to the memory pool. - * @param[in] p_element Element to be freed. - */ -void nrf_balloc_free(nrf_balloc_t const * p_pool, void * p_element); - -/**@brief Function for getting maximum memory pool utilization. - * - * @param[in] p_pool Pointer to the memory pool instance. - * - * @return Maximum number of elements allocated from the pool. - */ -__STATIC_INLINE uint8_t nrf_balloc_max_utilization_get(nrf_balloc_t const * p_pool); - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION -__STATIC_INLINE uint8_t nrf_balloc_max_utilization_get(nrf_balloc_t const * p_pool) -{ - ASSERT(p_pool != NULL); - return p_pool->p_cb->max_utilization; -} -#endif //SUPPRESS_INLINE_IMPLEMENTATION - -/**@brief Function for getting current memory pool utilization. - * - * @param[in] p_pool Pointer to the memory pool instance. - * - * @return Maximum number of elements allocated from the pool. - */ -__STATIC_INLINE uint8_t nrf_balloc_utilization_get(nrf_balloc_t const * p_pool); - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION -__STATIC_INLINE uint8_t nrf_balloc_utilization_get(nrf_balloc_t const * p_pool) -{ - ASSERT(p_pool != NULL); - return (p_pool->p_stack_limit - p_pool->p_cb->p_stack_pointer); -} -#endif //SUPPRESS_INLINE_IMPLEMENTATION - -#ifdef __cplusplus -} -#endif - -#endif // NRF_BALLOC_H__ -/** @} */ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/delay/nrf_delay.h b/bsp/boards/nrf52840/sdk/components/libraries/delay/nrf_delay.h deleted file mode 100644 index 641276d2ca..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/delay/nrf_delay.h +++ /dev/null @@ -1,80 +0,0 @@ -/** - * Copyright (c) 2011 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _NRF_DELAY_H -#define _NRF_DELAY_H - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Function for delaying execution for a number of microseconds. - * - * @param us_time Number of microseconds to wait. - */ -#define nrf_delay_us(us_time) NRFX_DELAY_US(us_time) - - -/** - * @brief Function for delaying execution for a number of milliseconds. - * - * @param ms_time Number of milliseconds to wait. - */ - -__STATIC_INLINE void nrf_delay_ms(uint32_t ms_time) -{ - if (ms_time == 0) - { - return; - } - - do { - nrf_delay_us(1000); - } while (--ms_time); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log.h b/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log.h deleted file mode 100644 index 870f6ec7e2..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log.h +++ /dev/null @@ -1,291 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -/**@file - * - * @defgroup nrf_log Logger module - * @{ - * @ingroup app_common - * - * @brief The nrf_log module interface. - */ - -#ifndef NRF_LOG_H_ -#define NRF_LOG_H_ - -#include "sdk_common.h" -#include "nrf_section.h" -#if NRF_MODULE_ENABLED(NRF_LOG) -#include "nrf_strerror.h" -#define NRF_LOG_ERROR_STRING_GET(code) nrf_strerror_get(code) -#else -#define NRF_LOG_ERROR_STRING_GET(code) "" -#endif - - -#ifdef __cplusplus -extern "C" { -#endif - -/** @brief Severity level for the module. - * - * The severity level can be defined in a module to override the default. - */ -#ifndef NRF_LOG_LEVEL - #define NRF_LOG_LEVEL NRF_LOG_DEFAULT_LEVEL -#endif - -/** @brief Initial severity if filtering is enabled. - */ -#ifndef NRF_LOG_INITIAL_LEVEL - #define NRF_LOG_INITIAL_LEVEL NRF_LOG_LEVEL -#endif - - -#include "nrf_log_internal.h" - -/** @def NRF_LOG_ERROR - * @brief Macro for logging error messages. It takes a printf-like, formatted - * string with up to seven arguments. - * - * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes error logs. - */ - -/** @def NRF_LOG_WARNING - * @brief Macro for logging error messages. It takes a printf-like, formatted - * string with up to seven arguments. - * - * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes warning logs. - */ - -/** @def NRF_LOG_INFO - * @brief Macro for logging error messages. It takes a printf-like, formatted - * string with up to seven arguments. - * - * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes info logs. - */ - -/** @def NRF_LOG_DEBUG - * @brief Macro for logging error messages. It takes a printf-like, formatted - * string with up to seven arguments. - * - * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes debug logs. - */ - -#define NRF_LOG_ERROR(...) NRF_LOG_INTERNAL_ERROR(__VA_ARGS__) -#define NRF_LOG_WARNING(...) NRF_LOG_INTERNAL_WARNING( __VA_ARGS__) -#define NRF_LOG_INFO(...) NRF_LOG_INTERNAL_INFO( __VA_ARGS__) -#define NRF_LOG_DEBUG(...) NRF_LOG_INTERNAL_DEBUG( __VA_ARGS__) - -/** @def NRF_LOG_INST_ERROR - * @brief Macro for logging error messages for a given module instance. It takes a printf-like, formatted - * string with up to seven arguments. - * - * @param p_inst Pointer to the instance with logging support. - * - * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes error logs. - */ - -/** @def NRF_LOG_INST_WARNING - * @brief Macro for logging error messages for a given module instance. It takes a printf-like, formatted - * string with up to seven arguments. - * - * @param p_inst Pointer to the instance with logging support. - * - * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes error logs. - */ - -/** @def NRF_LOG_INST_INFO - * @brief Macro for logging error messages for a given module instance. It takes a printf-like, formatted - * string with up to seven arguments. - * - * @param p_inst Pointer to the instance with logging support. - * - * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes error logs. - */ - -/** @def NRF_LOG_INST_DEBUG - * @brief Macro for logging error messages for given module instance. It takes a printf-like, formatted - * string with up to seven arguments. - * - * @param p_inst Pointer to the instance with logging support. - * - * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes error logs. - */ -#define NRF_LOG_INST_ERROR(p_inst,...) NRF_LOG_INTERNAL_INST_ERROR(p_inst,__VA_ARGS__) -#define NRF_LOG_INST_WARNING(p_inst,...) NRF_LOG_INTERNAL_INST_WARNING(p_inst,__VA_ARGS__) -#define NRF_LOG_INST_INFO(p_inst,...) NRF_LOG_INTERNAL_INST_INFO(p_inst, __VA_ARGS__) -#define NRF_LOG_INST_DEBUG(p_inst,...) NRF_LOG_INTERNAL_INST_DEBUG(p_inst, __VA_ARGS__) - -/** - * @brief Macro for logging a formatted string without any prefix or timestamp. - */ -#define NRF_LOG_RAW_INFO(...) NRF_LOG_INTERNAL_RAW_INFO( __VA_ARGS__) - -/** @def NRF_LOG_HEXDUMP_ERROR - * @brief Macro for logging raw bytes. - * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes error logs. - * - * @param p_data Pointer to data. - * @param len Data length in bytes. - */ -/** @def NRF_LOG_HEXDUMP_WARNING - * @brief Macro for logging raw bytes. - * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes warning logs. - * - * @param p_data Pointer to data. - * @param len Data length in bytes. - */ -/** @def NRF_LOG_HEXDUMP_INFO - * @brief Macro for logging raw bytes. - * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes info logs. - * - * @param p_data Pointer to data. - * @param len Data length in bytes. - */ -/** @def NRF_LOG_HEXDUMP_DEBUG - * @brief Macro for logging raw bytes. - * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes debug logs. - * - * @param p_data Pointer to data. - * @param len Data length in bytes. - */ -#define NRF_LOG_HEXDUMP_ERROR(p_data, len) NRF_LOG_INTERNAL_HEXDUMP_ERROR(p_data, len) -#define NRF_LOG_HEXDUMP_WARNING(p_data, len) NRF_LOG_INTERNAL_HEXDUMP_WARNING(p_data, len) -#define NRF_LOG_HEXDUMP_INFO(p_data, len) NRF_LOG_INTERNAL_HEXDUMP_INFO(p_data, len) -#define NRF_LOG_HEXDUMP_DEBUG(p_data, len) NRF_LOG_INTERNAL_HEXDUMP_DEBUG(p_data, len) - -/** @def NRF_LOG_HEXDUMP_INST_ERROR - * @brief Macro for logging raw bytes for a specific module instance. - * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes error logs. - * - * @param p_inst Pointer to the instance with logging support. - * @param p_data Pointer to data. - * @param len Data length in bytes. - */ -/** @def NRF_LOG_HEXDUMP_INST_WARNING - * @brief Macro for logging raw bytes for a specific module instance. - * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes error logs. - * - * @param p_inst Pointer to the instance with logging support. - * @param p_data Pointer to data. - * @param len Data length in bytes. - */ -/** @def NRF_LOG_HEXDUMP_INST_INFO - * @brief Macro for logging raw bytes for a specific module instance. - * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes error logs. - * - * @param p_inst Pointer to the instance with logging support. - * @param p_data Pointer to data. - * @param len Data length in bytes. - */ -/** @def NRF_LOG_HEXDUMP_INST_DEBUG - * @brief Macro for logging raw bytes for a specific module instance. - * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes error logs. - * - * @param p_inst Pointer to the instance with logging support. - * @param p_data Pointer to data. - * @param len Data length in bytes. - */ -#define NRF_LOG_HEXDUMP_INST_ERROR(p_inst, p_data, len) NRF_LOG_INTERNAL_HEXDUMP_INST_ERROR(p_inst, p_data, len) -#define NRF_LOG_HEXDUMP_INST_WARNING(p_inst, p_data, len) NRF_LOG_INTERNAL_HEXDUMP_INST_WARNING(p_inst, p_data, len) -#define NRF_LOG_HEXDUMP_INST_INFO(p_inst, p_data, len) NRF_LOG_INTERNAL_HEXDUMP_INST_INFO(p_inst, p_data, len) -#define NRF_LOG_HEXDUMP_INST_DEBUG(p_inst, p_data, len) NRF_LOG_INTERNAL_HEXDUMP_INST_DEBUG(p_inst, p_data, len) - -/** - * @brief Macro for logging hexdump without any prefix or timestamp. - */ -#define NRF_LOG_RAW_HEXDUMP_INFO(p_data, len) NRF_LOG_INTERNAL_RAW_HEXDUMP_INFO(p_data, len) - - -/** - * @brief Macro for copying a string to internal logger buffer if logs are deferred. - * - * @param _str String. - */ -#define NRF_LOG_PUSH(_str) NRF_LOG_INTERNAL_LOG_PUSH(_str) - -/** - * @brief Function for copying a string to the internal logger buffer if logs are deferred. - * - * Use this function to store a string that is volatile (for example allocated - * on stack) or that may change before the deferred logs are processed. Such string is copied - * into the internal logger buffer and is persistent until the log is processed. - * - * @note If the logs are not deferred, then this function returns the input parameter. - * - * @param p_str Pointer to the user string. - * - * @return Address to the location where the string is stored in the internal logger buffer. - */ -uint32_t nrf_log_push(char * const p_str); - -/** - * @brief Macro to be used in a formatted string to a pass float number to the log. - * - * Use this macro in a formatted string instead of the %f specifier together with - * @ref NRF_LOG_FLOAT macro. - * Example: NRF_LOG_INFO("My float number" NRF_LOG_FLOAT_MARKER "\r\n", NRF_LOG_FLOAT(f))) - */ -#define NRF_LOG_FLOAT_MARKER "%s%d.%02d" - -/** - * @brief Macro for dissecting a float number into two numbers (integer and residuum). - */ -#define NRF_LOG_FLOAT(val) (uint32_t)(((val) < 0 && (val) > -1.0) ? "-" : ""), \ - (int32_t)(val), \ - (int32_t)((((val) > 0) ? (val) - (int32_t)(val) \ - : (int32_t)(val) - (val))*100) - - -/** - * @brief Macro for registering an independent module. - * - * Registration creates set of dynamic (RAM) and constant variables associated with the module. - */ -#define NRF_LOG_MODULE_REGISTER() NRF_LOG_INTERNAL_MODULE_REGISTER() - - -#ifdef __cplusplus -} -#endif - -#endif // NRF_LOG_H_ - -/** @} */ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log_backend_flash.h b/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log_backend_flash.h deleted file mode 100644 index 87e538b80a..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log_backend_flash.h +++ /dev/null @@ -1,129 +0,0 @@ -/** - * Copyright (c) 2018 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - /**@file - * - * @defgroup nrf_log_backend_flash Flash logger backend - * @{ - * @ingroup nrf_log - * @brief Flash logger backend. - */ - -#ifndef NRF_LOG_BACKEND_FLASH_H -#define NRF_LOG_BACKEND_FLASH_H - -#include "nrf_log_backend_interface.h" -#include "nrf_fstorage.h" -#include "nrf_log_internal.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @brief Flashlog logger backend API. */ -extern const nrf_log_backend_api_t nrf_log_backend_flashlog_api; - -/** @brief Crashlog logger backend API. */ -extern const nrf_log_backend_api_t nrf_log_backend_crashlog_api; - -/** @brief Flashlog logger backend structure. */ -typedef struct { - nrf_log_backend_t backend; -} nrf_log_backend_flashlog_t; - -/** @brief Crashlog logger backend structure. */ -typedef struct { - nrf_log_backend_t backend; -} nrf_log_backend_crashlog_t; - -/** @brief Macro for creating an instance of the flashlog logger backend. */ -#define NRF_LOG_BACKEND_FLASHLOG_DEF(name) \ - static nrf_log_backend_flashlog_t name = { \ - .backend = {.p_api = &nrf_log_backend_flashlog_api}, \ - } - -/** @brief Macro for creating an instance of the crashlog logger backend. */ -#define NRF_LOG_BACKEND_CRASHLOG_DEF(name) \ - static nrf_log_backend_crashlog_t name = { \ - .backend = {.p_api = &nrf_log_backend_crashlog_api}, \ - } - -/** - * @brief Function for initializing the flash logger backend. - * - * Flash logger backend consists of two logical backends: flashlog and crashlog. Since both - * backends write to the same flash area, the initialization is common. - * - * @param p_fs_api fstorage API to be used. - * - * @return NRF_SUCCESS or error code returned by @ref nrf_fstorage_init. - */ -ret_code_t nrf_log_backend_flash_init(nrf_fstorage_api_t const * p_fs_api); - -/** - * @brief Function for getting a log entry stored in flash. - * - * Log messages stored in flash can be read one by one starting from the oldest one. - * - * @param[in, out] p_token Token reused between consecutive readings of log entries. - * Token must be set to 0 to read the first entry. - * @param[out] pp_header Pointer to the entry header. - * @param[out] pp_data Pointer to the data part of the entry (arguments or data in case of hexdump). - * - * @retval NRF_SUCCESS Entry was successfully read. - * @retval NRF_ERROR_NOT_SUPPORTED fstorage API does not support direct reading. - * @retval NRF_ERROR_NOT_FOUND Entry not found. Last entry was already reached or area is empty. - */ -ret_code_t nrf_log_backend_flash_next_entry_get(uint32_t * p_token, - nrf_log_header_t * * pp_header, - uint8_t * * pp_data); - -/** - * @brief Function for erasing flash area dedicated for the flash logger backend. - */ -ret_code_t nrf_log_backend_flash_erase(void); - -#ifdef __cplusplus -} -#endif - -#endif //NRF_LOG_BACKEND_UART_H - -/** @} */ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log_backend_interface.h b/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log_backend_interface.h deleted file mode 100644 index 4ed31a2a4f..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log_backend_interface.h +++ /dev/null @@ -1,220 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef NRF_LOG_BACKEND_INTERFACE_H -#define NRF_LOG_BACKEND_INTERFACE_H - -/**@file - * @addtogroup nrf_log Logger module - * @ingroup app_common - * - * @defgroup nrf_log_backend_interface Logger backend interface - * @{ - * @ingroup nrf_log - * @brief The nrf_log backend interface. - */ - -#include "nrf_memobj.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - - -/** - * @brief nrf_log entry. - */ -typedef nrf_memobj_t nrf_log_entry_t; - -/* Forward declaration of the nrf_log_backend_t type. */ -typedef struct nrf_log_backend_s nrf_log_backend_t; - -/** - * @brief Logger backend API. - */ -typedef struct -{ - /** - * @brief @ref nrf_log_backend_put - */ - void (*put)(nrf_log_backend_t const * p_backend, nrf_log_entry_t * p_entry); - - /** - * @brief @ref nrf_log_backend_panic_set - */ - void (*panic_set)(nrf_log_backend_t const * p_backend); - - /** - * @brief @ref nrf_log_backend_flush - */ - void (*flush)(nrf_log_backend_t const * p_backend); -} nrf_log_backend_api_t; - -/** - * @brief Logger backend structure. - */ -struct nrf_log_backend_s -{ - nrf_log_backend_api_t const * p_api; //!< Pointer to interface. - nrf_log_backend_t * p_next; //!< Pointer to next backend added to the logger. - uint8_t id; //!< Backend id. - bool enabled;//!< Flag indicating backend status. -}; - -/** - * @brief Function for putting message with log entry to the backend. - * - * @param[in] p_backend Pointer to the backend instance. - * @param[in] p_msg Pointer to message with log entry. - */ -__STATIC_INLINE void nrf_log_backend_put(nrf_log_backend_t const * p_backend, - nrf_log_entry_t * p_msg); - -/** - * @brief Function for reconfiguring backend to panic mode. - * - * @param[in] p_backend Pointer to the backend instance. - */ -__STATIC_INLINE void nrf_log_backend_panic_set(nrf_log_backend_t const * p_backend); - -/** - * @brief Function for flushing backend. - * - * On flushing request backend should release log message(s). - * - * @param[in] p_backend Pointer to the backend instance. - */ -__STATIC_INLINE void nrf_log_backend_flush(nrf_log_backend_t const * p_backend); - - -/** - * @brief Function for setting backend id. - * - * @note It is used internally by the logger. - * - * @param[in] p_backend Pointer to the backend instance. - * @param[in] id Id. - */ -__STATIC_INLINE void nrf_log_backend_id_set(nrf_log_backend_t * p_backend, uint8_t id); - -/** - * @brief Function for getting backend id. - * - * @note It is used internally by the logger. - * - * @param[in] p_backend Pointer to the backend instance. - * @return Id. - */ -__STATIC_INLINE uint8_t nrf_log_backend_id_get(nrf_log_backend_t const * p_backend); - -/** - * @brief Function for enabling backend. - * - * @param[in] p_backend Pointer to the backend instance. - */ -__STATIC_INLINE void nrf_log_backend_enable(nrf_log_backend_t * p_backend); - -/** - * @brief Function for disabling backend. - * - * @param[in] p_backend Pointer to the backend instance. - */ -__STATIC_INLINE void nrf_log_backend_disable(nrf_log_backend_t * p_backend); - -/** - * @brief Function for checking state of the backend. - * - * @param[in] p_backend Pointer to the backend instance. - * - * @return True if backend is enabled, false otherwise. - */ -__STATIC_INLINE bool nrf_log_backend_is_enabled(nrf_log_backend_t const * p_backend); - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION -__STATIC_INLINE void nrf_log_backend_put(nrf_log_backend_t const * p_backend, - nrf_log_entry_t * p_msg) -{ - p_backend->p_api->put(p_backend, p_msg); -} - -__STATIC_INLINE void nrf_log_backend_panic_set(nrf_log_backend_t const * p_backend) -{ - p_backend->p_api->panic_set(p_backend); -} - -__STATIC_INLINE void nrf_log_backend_flush(nrf_log_backend_t const * p_backend) -{ - p_backend->p_api->flush(p_backend); -} - -__STATIC_INLINE void nrf_log_backend_id_set(nrf_log_backend_t * p_backend, uint8_t id) -{ - p_backend->id = id; -} - -__STATIC_INLINE uint8_t nrf_log_backend_id_get(nrf_log_backend_t const * p_backend) -{ - return p_backend->id; -} - -__STATIC_INLINE void nrf_log_backend_enable(nrf_log_backend_t * p_backend) -{ - p_backend->enabled = true; -} - -__STATIC_INLINE void nrf_log_backend_disable(nrf_log_backend_t * p_backend) -{ - p_backend->enabled = false; -} - -__STATIC_INLINE bool nrf_log_backend_is_enabled(nrf_log_backend_t const * p_backend) -{ - return p_backend->enabled; -} - -#endif // SUPPRESS_INLINE_IMPLEMENTATION - -#ifdef __cplusplus -} -#endif - -#endif //NRF_LOG_BACKEND_INTERFACE_H - -/** @} */ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log_backend_rtt.h b/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log_backend_rtt.h deleted file mode 100644 index f764a14817..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log_backend_rtt.h +++ /dev/null @@ -1,82 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - /**@file - * - * @defgroup nrf_log_backend_rtt Log RTT backend - * @{ - * @ingroup nrf_log - * @brief Log RTT backend. - */ - -#ifndef NRF_LOG_BACKEND_RTT_H -#define NRF_LOG_BACKEND_RTT_H - -#include "nrf_log_backend_interface.h" - -#ifdef __cplusplus -extern "C" { -#endif - -extern const nrf_log_backend_api_t nrf_log_backend_rtt_api; - -typedef struct { - nrf_log_backend_t backend; -} nrf_log_backend_rtt_t; - -/** - * @brief RTT backend definition - * - * @param _name Name of the instance. - */ -#define NRF_LOG_BACKEND_RTT_DEF(_name) \ - static nrf_log_backend_rtt_t _name = { \ - .backend = {.p_api = &nrf_log_backend_rtt_api}, \ - } - -void nrf_log_backend_rtt_init(void); - -#ifdef __cplusplus -} -#endif - -#endif //NRF_LOG_BACKEND_RTT_H - -/** @} */ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log_backend_uart.h b/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log_backend_uart.h deleted file mode 100644 index f606c5d8fc..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log_backend_uart.h +++ /dev/null @@ -1,77 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - /**@file - * - * @defgroup nrf_log_backend_uart Log UART backend - * @{ - * @ingroup nrf_log - * @brief Log UART backend. - */ - -#ifndef NRF_LOG_BACKEND_UART_H -#define NRF_LOG_BACKEND_UART_H - -#include "nrf_log_backend_interface.h" - -#ifdef __cplusplus -extern "C" { -#endif - -extern const nrf_log_backend_api_t nrf_log_backend_uart_api; - -typedef struct { - nrf_log_backend_t backend; -} nrf_log_backend_uart_t; - -#define NRF_LOG_BACKEND_UART_DEF(name) \ - static nrf_log_backend_uart_t name = { \ - .backend = {.p_api = &nrf_log_backend_uart_api}, \ - } - -void nrf_log_backend_uart_init(void); - -#ifdef __cplusplus -} -#endif - -#endif //NRF_LOG_BACKEND_UART_H - -/** @} */ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log_ctrl.h b/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log_ctrl.h deleted file mode 100644 index 864f10f9fc..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log_ctrl.h +++ /dev/null @@ -1,226 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef NRF_LOG_CTRL_H -#define NRF_LOG_CTRL_H - -/**@file - * @addtogroup nrf_log Logger module - * @ingroup app_common - * - * @defgroup nrf_log_ctrl Functions for controlling nrf_log - * @{ - * @ingroup nrf_log - * @brief The nrf_log control interface. - */ - -#include "sdk_config.h" -#include "sdk_errors.h" -#include -#include -#include "nrf_log_types.h" -#include "nrf_log_ctrl_internal.h" -#include "nrf_log_backend_interface.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Timestamp function prototype. - * - * @return Timestamp value. - */ -typedef uint32_t (*nrf_log_timestamp_func_t)(void); - -/**@brief Macro for initializing the logs. - * - * Macro has one or two parameters. First parameter (obligatory) is the timestamp function (@ref nrf_log_timestamp_func_t). - * Additionally, as the second parameter timestamp frequency in Hz can be provided. If not provided then default - * frequency is used (@ref NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY). Frequency is used to format timestamp prefix if - * @ref NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED is set. - * - * @return NRF_SUCCESS after successful initialization, otherwise an error code. - */ -#define NRF_LOG_INIT(...) NRF_LOG_INTERNAL_INIT(__VA_ARGS__) - - -/**@brief Macro for processing a single log entry from a queue of deferred logs. - * - * You can call this macro from the main context or from the error handler to process - * log entries one by one. - * - * @note If logs are not deferred, this call has no use and is defined as 'false'. - * - * @retval true There are more logs to process in the buffer. - * @retval false No more logs in the buffer. - */ -#define NRF_LOG_PROCESS() NRF_LOG_INTERNAL_PROCESS() - -/** @brief Macro for processing all log entries from the buffer. - * It blocks until all buffered entries are processed by the backend. - * - * @note If logs are not deferred, this call has no use and is empty. - */ -#define NRF_LOG_FLUSH() NRF_LOG_INTERNAL_FLUSH() - -/** @brief Macro for flushing log data before reset. - * - * @note If logs are not deferred, this call has no use and is empty. - * - * @note If RTT is used, then a breakpoint is hit once flushed. - */ -#define NRF_LOG_FINAL_FLUSH() NRF_LOG_INTERNAL_FINAL_FLUSH() - -/** - * @brief Function for initializing the frontend and the default backend. - * - * @ref NRF_LOG_INIT calls this function to initialize the frontend and the backend. - * If custom backend is used, then @ref NRF_LOG_INIT should not be called. - * Instead, frontend and user backend should be verbosely initialized. - * - * @param timestamp_func Function for getting a 32-bit timestamp. - * @param timestamp_freq Frequency of the timestamp. - * - * @return Error status. - * - */ -ret_code_t nrf_log_init(nrf_log_timestamp_func_t timestamp_func, uint32_t timestamp_freq); - -/** - * @brief Function for adding new backend interface to the logger. - * - * @param p_backend Pointer to the backend interface. - * @param severity Initial value of severity level for each module forwarded to the backend. This - * option is only applicable if @ref NRF_LOG_FILTERS_ENABLED is set. - * @return -1 if backend cannot be added or positive number (backend ID). - */ -int32_t nrf_log_backend_add(nrf_log_backend_t * p_backend, nrf_log_severity_t severity); - -/** - * @brief Function for removing backend from the logger. - * - * @param p_backend Pointer to the backend interface. - * - */ -void nrf_log_backend_remove(nrf_log_backend_t * p_backend); - -/** - * @brief Function for setting logger backends into panic mode. - * - * When this function is called all attached backends are informed about panic state of the system. - * It is up to the backend to react properly (hold or process logs in blocking mode, etc.) - */ -void nrf_log_panic(void); - -/** - * @brief Function for handling a single log entry. - * - * Use this function only if the logs are buffered. It takes a single entry from the - * buffer and attempts to process it. - * - * @retval true If there are more entries to process. - * @retval false If there are no more entries to process. - */ -bool nrf_log_frontend_dequeue(void); - -/** - * @brief Function for getting number of independent log modules registered into the logger. - * - * @return Number of registered modules. - */ -uint32_t nrf_log_module_cnt_get(void); - -/** - * @brief Function for getting module name. - * - * @param module_id Module ID. - * @param is_ordered_idx Module ID is given is index in alphabetically sorted list of modules. - * @return Pointer to string with module name. - */ -const char * nrf_log_module_name_get(uint32_t module_id, bool is_ordered_idx); - -/** - * @brief Function for getting coloring of specific logs. - * - * @param module_id Module ID. - * @param severity Log severity. - * - * @return ID of the color. - */ -uint8_t nrf_log_color_id_get(uint32_t module_id, nrf_log_severity_t severity); - -/** - * @brief Function for configuring filtering ofs logs in the module. - * - * Filtering of logs in modules is independent for each backend. - * - * @param backend_id Backend ID which want to chenge its configuration. - * @param module_id Module ID which logs will be reconfigured. - * @param severity New severity filter. - */ -void nrf_log_module_filter_set(uint32_t backend_id, - uint32_t module_id, - nrf_log_severity_t severity); - -/** - * @brief Function for getting module severity level. - * - * @param backend_id Backend ID. - * @param module_id Module ID. - * @param is_ordered_idx Module ID is given is index in alphabetically sorted list of modules. - * @param dynamic It true current filter for given backend is returned. If false then - * compiled-in level is returned (maximum available). If this parameter is - * false then backend_id parameter is not used. - * - * @return Severity. - */ -nrf_log_severity_t nrf_log_module_filter_get(uint32_t backend_id, - uint32_t module_id, - bool is_ordered_idx, - bool dynamic); - -#ifdef __cplusplus -} -#endif - -#endif // NRF_LOG_CTRL_H - -/** - *@} - **/ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log_default_backends.h b/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log_default_backends.h deleted file mode 100644 index 6f5bd5ca9a..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log_default_backends.h +++ /dev/null @@ -1,81 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef NRF_LOG_DEFAULT_BACKENDS_H__ -#define NRF_LOG_DEFAULT_BACKENDS_H__ - -/**@file - * @addtogroup nrf_log Logger module - * @ingroup app_common - * - * @defgroup nrf_log_default_backends Functions for initializing and adding default backends - * @{ - * @ingroup nrf_log - * @brief The nrf_log default backends. - */ - -#include "sdk_config.h" -#include "sdk_errors.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @def NRF_LOG_DEFAULT_BACKENDS_INIT - * @brief Macro for initializing default backends. - * - * Each backend enabled in configuration is initialized and added as a backend to the logger. - */ -#if NRF_LOG_ENABLED -#define NRF_LOG_DEFAULT_BACKENDS_INIT() nrf_log_default_backends_init() -#else -#define NRF_LOG_DEFAULT_BACKENDS_INIT() -#endif - -void nrf_log_default_backends_init(void); - -#ifdef __cplusplus -} -#endif - -/** @} */ - -#endif // NRF_LOG_DEFAULT_BACKENDS_H__ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log_instance.h b/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log_instance.h deleted file mode 100644 index 6b3200941a..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log_instance.h +++ /dev/null @@ -1,135 +0,0 @@ -/** - * Copyright (c) 2018 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef NRF_LOG_INSTANCE_H -#define NRF_LOG_INSTANCE_H - -#include "sdk_config.h" -#include "nrf_section.h" -#include "nrf_log_types.h" -#include -/* - * For GCC, sections are sorted in the group by the linker. For IAR and KEIL, it is assumed that linker will sort - * dynamic and const section in the same order (but in different locations). Proper message formatting - * is based on that assumption. - */ -#if defined(__GNUC__) -#define NRF_LOG_DYNAMIC_SECTION_NAME(_module_name) CONCAT_2(log_dynamic_data_,_module_name) -#define NRF_LOG_CONST_SECTION_NAME(_module_name) CONCAT_2(log_const_data_,_module_name) -#else -#define NRF_LOG_DYNAMIC_SECTION_NAME(_module_name) log_dynamic_data -#define NRF_LOG_CONST_SECTION_NAME(_module_name) log_const_data -#endif - -#define NRF_LOG_ITEM_DATA(_name) CONCAT_3(m_nrf_log_,_name,_logs_data) -#define NRF_LOG_ITEM_DATA_DYNAMIC(_name) CONCAT_2(NRF_LOG_ITEM_DATA(_name),_dynamic) -#define NRF_LOG_ITEM_DATA_CONST(_name) CONCAT_2(NRF_LOG_ITEM_DATA(_name),_const) - -#ifdef UNIT_TEST -#define _CONST -#else -#define _CONST const -#endif - -#if NRF_LOG_FILTERS_ENABLED -#define NRF_LOG_DYNAMIC_STRUCT_NAME nrf_log_module_dynamic_data_t -#else -#define NRF_LOG_DYNAMIC_STRUCT_NAME nrf_log_module_reduced_dynamic_data_t -#endif - -#define NRF_LOG_INTERNAL_ITEM_REGISTER( \ - _name, _str_name, _info_color, _debug_color, _initial_lvl, _compiled_lvl) \ - NRF_SECTION_ITEM_REGISTER(NRF_LOG_CONST_SECTION_NAME(_name), \ - _CONST nrf_log_module_const_data_t NRF_LOG_ITEM_DATA_CONST(_name)) = { \ - .p_module_name = _str_name, \ - .info_color_id = (_info_color), \ - .debug_color_id = (_debug_color), \ - .compiled_lvl = (nrf_log_severity_t)(_compiled_lvl), \ - .initial_lvl = (nrf_log_severity_t)(_initial_lvl), \ - }; \ - NRF_SECTION_ITEM_REGISTER(NRF_LOG_DYNAMIC_SECTION_NAME(_name), \ - NRF_LOG_DYNAMIC_STRUCT_NAME NRF_LOG_ITEM_DATA_DYNAMIC(_name)) - -/**@file - * - * @defgroup nrf_log_instance Macros for logging on instance level - * @{ - * @ingroup nrf_log - * - * @brief Macros for logging on instance level - */ - -/** @def NRF_LOG_INSTANCE_PTR_DECLARE - * @brief Macro for declaring a logger instance pointer in the module stucture. - */ - -/** @def NRF_LOG_INSTANCE_REGISTER - * @brief Macro for creating an independent module instance. - * - * Module instance provides filtering of logs on instance level instead of module level. - */ - -/** @def NRF_LOG_INSTANCE_PTR_INIT - * @brief Macro for initializing a pointer to the logger instance. - */ - - - /** @} */ -#if NRF_LOG_ENABLED -#define NRF_LOG_INSTANCE_PTR_DECLARE(_p_name) NRF_LOG_DYNAMIC_STRUCT_NAME * _p_name; - -#define NRF_LOG_INSTANCE_REGISTER( \ - _module_name, _inst_name, _info_color, _debug_color, _initial_lvl, _compiled_lvl) \ - NRF_LOG_INTERNAL_ITEM_REGISTER(CONCAT_3(_module_name,_,_inst_name), \ - STRINGIFY(_module_name._inst_name), \ - _info_color, \ - _debug_color, \ - _initial_lvl, \ - _compiled_lvl) - -#define NRF_LOG_INSTANCE_PTR_INIT(_p_name, _module_name, _inst_name) \ - ._p_name = &NRF_LOG_ITEM_DATA_DYNAMIC(CONCAT_3(_module_name,_,_inst_name)), - -#else -#define NRF_LOG_INSTANCE_PTR_DECLARE(_p_name) -#define NRF_LOG_INSTANCE_REGISTER(_module_name, _inst_name, info_color, debug_color, _initial_lvl, compiled_lvl) -#define NRF_LOG_INSTANCE_PTR_INIT(_p_name, _module_name, _inst_name) -#endif - -#endif //NRF_LOG_INSTANCE_H diff --git a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log_str_formatter.h b/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log_str_formatter.h deleted file mode 100644 index 103fa94264..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log_str_formatter.h +++ /dev/null @@ -1,86 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/**@file - * - * @defgroup nrf_log_str_formatter String formatter for the logger messages - * @{ - * @ingroup nrf_log - */ - -#ifndef NRF_LOG_STR_FORMATTER_H -#define NRF_LOG_STR_FORMATTER_H - -#include -#include "nrf_fprintf.h" -#include "nrf_log_ctrl.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct -{ - uint32_t timestamp; - uint16_t module_id; - uint16_t dropped; - nrf_log_severity_t severity; - uint8_t use_colors; -} nrf_log_str_formatter_entry_params_t; - - -void nrf_log_std_entry_process(char const * p_str, - uint32_t const * p_args, - uint32_t nargs, - nrf_log_str_formatter_entry_params_t * p_params, - nrf_fprintf_ctx_t * p_ctx); - -void nrf_log_hexdump_entry_process(uint8_t * p_data, - uint32_t data_len, - nrf_log_str_formatter_entry_params_t * p_params, - nrf_fprintf_ctx_t * p_ctx); - -void nrf_log_str_formatter_timestamp_freq_set(uint32_t freq); -#ifdef __cplusplus -} -#endif - -#endif //NRF_LOG_STR_FORMATTER_H -/** @} */ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log_types.h b/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log_types.h deleted file mode 100644 index 4b678ca88f..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/nrf_log_types.h +++ /dev/null @@ -1,97 +0,0 @@ -/** - * Copyright (c) 2018 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef NRF_LOG_TYPES_H -#define NRF_LOG_TYPES_H - -#include - -/** - * @brief Logger severity levels. - */ -typedef enum -{ - NRF_LOG_SEVERITY_NONE, - NRF_LOG_SEVERITY_ERROR, - NRF_LOG_SEVERITY_WARNING, - NRF_LOG_SEVERITY_INFO, - NRF_LOG_SEVERITY_DEBUG, - NRF_LOG_SEVERITY_INFO_RAW, /* Artificial level to pass information about skipping string postprocessing.*/ -} nrf_log_severity_t; - -/** - * @brief Structure holding dynamic data associated with a module or instance if filtering is enabled (@ref NRF_LOG_FILTERS_ENABLED). - * - * See @ref NRF_LOG_MODULE_REGISTER and @ref NRF_LOG_INSTANCE_REGISTER. - */ -typedef struct -{ - uint16_t module_id; ///< Module ID assigned during initialization. - uint16_t order_idx; ///< Ordered index of the module (used for auto-completion). - uint32_t filter; ///< Current highest severity level accepted (redundant to @ref nrf_log_module_dynamic_data_t::filter_lvls, used for optimization) - uint32_t filter_lvls; ///< Current severity levels for each backend (3 bits per backend). -} nrf_log_module_dynamic_data_t; - -/** - * @brief Structure holding dynamic data associated with a module or instance if filtering is disabled (@ref NRF_LOG_FILTERS_ENABLED). - * - * See @ref NRF_LOG_MODULE_REGISTER and @ref NRF_LOG_INSTANCE_REGISTER. - */ -typedef struct -{ - uint16_t module_id; ///< Module ID assigned during initialization. - uint16_t padding; ///< Padding to fit in word. -} nrf_log_module_reduced_dynamic_data_t; - - -/** - * @brief Structure holding constant data associated with a module or instance. - * - * See @ref NRF_LOG_MODULE_REGISTER and @ref NRF_LOG_INSTANCE_REGISTER. - */ -typedef struct -{ - const char * p_module_name; ///< Module or instance name. - uint8_t info_color_id; ///< Color code of info messages. - uint8_t debug_color_id; ///< Color code of debug messages. - nrf_log_severity_t compiled_lvl; ///< Compiled highest severity level. - nrf_log_severity_t initial_lvl; ///< Severity level for given module or instance set on backend initialization. -} nrf_log_module_const_data_t; - -#endif //NRF_LOG_TYPES_H diff --git a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_backend_flash.c b/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_backend_flash.c deleted file mode 100644 index 7a826e7541..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_backend_flash.c +++ /dev/null @@ -1,739 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include "sdk_common.h" -#if NRF_MODULE_ENABLED(NRF_LOG) && NRF_MODULE_ENABLED(NRF_LOG_BACKEND_FLASH) -#include "nrf_log_backend_flash.h" -#include "nrf_log_str_formatter.h" -#include "nrf_fstorage_nvmc.h" -#include "nrf_log.h" -#include "nrf_atomic.h" -#include "nrf_queue.h" -#include "app_error.h" -#include - -#if (NRF_LOG_BACKEND_FLASHLOG_ENABLED == 0) && (NRF_LOG_BACKEND_CRASHLOG_ENABLED == 0) -#error "No flash backend enabled." -#endif - -/** @brief Maximum logger message payload (arguments or data in hexdump) which can be stored. */ -#define FLASH_LOG_MAX_PAYLOAD_SIZE (NRF_LOG_BACKEND_FLASH_SER_BUFFER_SIZE - sizeof(nrf_log_header_t)) - -/** @brief Size of serialization buffer in words. */ -#define FLASH_LOG_SER_BUFFER_WORDS (NRF_LOG_BACKEND_FLASH_SER_BUFFER_SIZE/sizeof(uint32_t)) - -/** @brief Length of logger header. */ -#define LOG_HEADER_LEN (sizeof(nrf_log_header_t)) - -/** @brief Length of logger header given in 32 bit words. */ -#define LOG_HEADER_LEN_WORDS (LOG_HEADER_LEN/sizeof(uint32_t)) - -/** @brief Maximum possible length of standard log message. */ -#define STD_LOG_MSG_MAX_LEN (LOG_HEADER_LEN + NRF_LOG_MAX_NUM_OF_ARGS*sizeof(uint32_t)) - -/* Buffer must be multiple of 4. */ -STATIC_ASSERT((NRF_LOG_BACKEND_FLASH_SER_BUFFER_SIZE % sizeof(uint32_t)) == 0); - -/* Buffer must fit standard log message. */ -STATIC_ASSERT(NRF_LOG_BACKEND_FLASH_SER_BUFFER_SIZE >= STD_LOG_MSG_MAX_LEN); - -/** @brief Flash page size in bytes. */ -#define CODE_PAGE_SIZE 4096 - -/** @brief Start address of the area dedicated for flash log. */ -#define FLASH_LOG_START_ADDR (NRF_LOG_BACKEND_FLASH_START_PAGE * CODE_PAGE_SIZE) - -/** @brief End address of the area dedicated for flash log. */ -#define FLASH_LOG_END_ADDR (FLASH_LOG_START_ADDR + (NRF_LOG_BACKEND_PAGES * CODE_PAGE_SIZE) - 1) - -/** @brief Size of the area dedicated for flash log. */ -#define FLASH_LOG_SIZE (NRF_LOG_BACKEND_PAGES * CODE_PAGE_SIZE) - -/** @brief Start address determined in runtime. - * - * If configuration indicates that flash log should be placed after application. - * */ -#if defined ( __CC_ARM ) -#define RUNTIME_START_ADDR \ - _Pragma("diag_suppress 170") \ - ((NRF_LOG_BACKEND_FLASH_START_PAGE == 0) ? \ - (CODE_PAGE_SIZE*CEIL_DIV((uint32_t)CODE_END, CODE_PAGE_SIZE)) : FLASH_LOG_START_ADDR) \ - _Pragma("diag_default 170") -#else -#define RUNTIME_START_ADDR ((NRF_LOG_BACKEND_FLASH_START_PAGE == 0) ? \ - (CODE_PAGE_SIZE*CEIL_DIV((uint32_t)CODE_END, CODE_PAGE_SIZE)) : FLASH_LOG_START_ADDR) -#endif -static void fstorage_evt_handler(nrf_fstorage_evt_t * p_evt); - -/** @brief Message queue for run time flash log. */ -#if NRF_LOG_BACKEND_FLASHLOG_ENABLED -NRF_QUEUE_DEF(nrf_log_entry_t *, - m_flashlog_queue, - NRF_LOG_BACKEND_FLASHLOG_QUEUE_SIZE, - NRF_QUEUE_MODE_NO_OVERFLOW); -static const nrf_queue_t * mp_flashlog_queue = &m_flashlog_queue; -#else -static const nrf_queue_t * mp_flashlog_queue = NULL; -#endif - - -/** @brief Message FIFO for crash log. */ -#if NRF_LOG_BACKEND_CRASHLOG_ENABLED -NRF_QUEUE_DEF(nrf_log_entry_t *, - m_crashlog_queue, - NRF_LOG_BACKEND_CRASHLOG_FIFO_SIZE, - NRF_QUEUE_MODE_NO_OVERFLOW); -static const nrf_queue_t * mp_crashlog_queue = &m_crashlog_queue; -#else -static const nrf_queue_t * mp_crashlog_queue = NULL; -#endif - - -/** @brief Fstorage instance used for flash log. */ -NRF_FSTORAGE_DEF(nrf_fstorage_t m_log_flash_fstorage) = -{ - /* Set a handler for fstorage events. */ - .evt_handler = fstorage_evt_handler, - .start_addr = FLASH_LOG_START_ADDR, - .end_addr = FLASH_LOG_END_ADDR, -}; - -/** @brief Flash log state. */ -typedef enum -{ - LOG_BACKEND_FLASH_ACTIVE, /**< Flash backend is active. */ - LOG_BACKEND_FLASH_INACTIVE, /**< Flash backend is inactive. All incoming requests are skipped. */ - LOG_BACKEND_FLASH_IN_PANIC, /**< Flash backend is in panic mode. Incoming messages are written to flash in synchronous mode. */ -} log_backend_flash_state_t; - -static log_backend_flash_state_t m_state; /**< Flash logger backend state. */ -static nrf_atomic_flag_t m_busy_flag; /**< Flag indicating if module performs flash writing. */ -static uint32_t m_flash_buf[FLASH_LOG_SER_BUFFER_WORDS]; /**< Buffer used for serializing messages. */ -static uint32_t m_curr_addr; /**< Address of free spot in the storage area. */ -static size_t m_curr_len; /**< Length of current message being written. */ -static uint32_t m_dropped; /**< Number of dropped messages. */ - -/** @brief Log message string injected when entering panic mode. */ -static const char crashlog_str[] = "-----------CRASHLOG------------\r\n"; - -/** @brief Function saturates input to maximum possible length and rounds up value to be multiple - * of word size. - * - * @param length Length value. - * - * @return Modified input length. - */ -static uint32_t saturate_align_length(uint32_t length) -{ - length = (length > FLASH_LOG_MAX_PAYLOAD_SIZE) ? FLASH_LOG_MAX_PAYLOAD_SIZE : length; //saturate - length = CEIL_DIV(length, sizeof(uint32_t))*sizeof(uint32_t); - return length; -} - - -/** - * @brief Function for copying logger message to the buffer. - * - * @param[in] p_msg Logger message. - * @param[out] p_buf Output buffer where serialized message is placed. - * @param[in,out] p_len Buffer size as input, length of prepared data as output. - * - * @return True if message fits into the buffer, false otherwise - */ -static bool msg_to_buf(nrf_log_entry_t * p_msg, uint8_t * p_buf, size_t * p_len) -{ - uint32_t data_len; - nrf_log_header_t header = {0}; - uint32_t memobj_offset = HEADER_SIZE*sizeof(uint32_t); - - nrf_memobj_read(p_msg, &header, HEADER_SIZE*sizeof(uint32_t), 0); - - memcpy(p_buf, &header, sizeof(nrf_log_header_t)); - p_buf += sizeof(nrf_log_header_t); - - switch (header.base.generic.type) - { - case HEADER_TYPE_STD: - { - data_len = header.base.std.nargs * sizeof(uint32_t); - break; - } - case HEADER_TYPE_HEXDUMP: - { - data_len = saturate_align_length(header.base.hexdump.len); - break; - } - default: - *p_len = 0; - return false; - } - nrf_memobj_read(p_msg, p_buf, data_len, memobj_offset); - - if (*p_len >= sizeof(nrf_log_header_t) + data_len) - { - *p_len = sizeof(nrf_log_header_t) + data_len; - return true; - } - else - { - return false; - } -} - -/** - * @brief Function for getting logger message stored in flash. - * - * @param[in] p_buf Pointer to the location where message is stored. - * @param[out] pp_header Pointer to the log message header. - * @param[out] pp_data Pointer to the log message data (arguments or data in case of hexdump). - * - * @return True if message was successfully fetched, false otherwise. - */ -static bool msg_from_buf(uint32_t * p_buf, - nrf_log_header_t * * pp_header, - uint8_t * * pp_data, - uint32_t * p_len) -{ - *pp_header = (nrf_log_header_t *)p_buf; - *pp_data = (uint8_t *)&p_buf[LOG_HEADER_LEN_WORDS]; - - uint32_t data_len; - - switch ((*pp_header)->base.generic.type) - { - case HEADER_TYPE_STD: - { - data_len = ((*pp_header)->base.std.nargs)*sizeof(uint32_t); - break; - } - case HEADER_TYPE_HEXDUMP: - { - - data_len = saturate_align_length((*pp_header)->base.hexdump.len); - break; - } - default: - return false; - } - - *p_len = LOG_HEADER_LEN + data_len; - return true; -} - -/** - * @brief Function for processing log message queue. - * - * If writing to flash is synchronous then function drains the queue and writes all messages to flash. - * If writing to flash is asynchronous then function starts single write operation. In asynchronous mode - * function is called when new message is put into the queue from from flash operation callback. - * - * Function detects the situation that flash module reports attempt to write outside dedicated area. - * In that case flash backend stops writing any new messages. - * - * @param p_queue Queue will log messages - * @param fstorage_blocking If true it indicates that flash operations are blocking, event handler is not used. - */ -static void log_msg_queue_process(nrf_queue_t const * p_queue, bool fstorage_blocking) -{ - nrf_log_entry_t * p_msg; - bool busy = false; - while (nrf_queue_pop(p_queue, &p_msg) == NRF_SUCCESS) - { - ret_code_t err_code; - - m_curr_len = sizeof(m_flash_buf); - if (!msg_to_buf(p_msg, (uint8_t *)m_flash_buf, &m_curr_len)) - { - continue; - } - - err_code = nrf_fstorage_write(&m_log_flash_fstorage, m_curr_addr, m_flash_buf, m_curr_len, p_msg); - - if (err_code == NRF_SUCCESS) - { - if (fstorage_blocking) - { - m_curr_addr += m_curr_len; - - nrf_memobj_put(p_msg); - } - else - { - busy = true; - break; - } - } - else if (!fstorage_blocking && (err_code == NRF_ERROR_NO_MEM)) - { - // fstorage queue got full. Drop entry. - nrf_memobj_put(p_msg); - m_dropped++; - break; - } - else if (err_code == NRF_ERROR_INVALID_ADDR) - { - // Trying to write outside the area, flash log is full. Skip any new writes. - nrf_memobj_put(p_msg); - m_state = LOG_BACKEND_FLASH_INACTIVE; - } - else - { - ASSERT(false); - } - } - - if (!busy) - { - UNUSED_RETURN_VALUE(nrf_atomic_flag_clear(&m_busy_flag)); - } -} - -static void queue_element_drop(nrf_queue_t const * p_queue) -{ - nrf_log_entry_t * p_msg; - if (nrf_queue_pop(p_queue, &p_msg) == NRF_SUCCESS) - { - m_dropped++; - nrf_memobj_put(p_msg); - } -} - -static void fstorage_evt_handler(nrf_fstorage_evt_t * p_evt) -{ - if (m_state == LOG_BACKEND_FLASH_ACTIVE) - { - switch (p_evt->id) - { - case NRF_FSTORAGE_EVT_WRITE_RESULT: - { - if (p_evt->result == NRF_SUCCESS) - { - m_curr_addr += m_curr_len; - m_curr_len = 0; - log_msg_queue_process(mp_flashlog_queue, false); - } - else - { - m_dropped++; - } - - if (p_evt->p_param) - { - nrf_memobj_put((nrf_log_entry_t *)p_evt->p_param); - } - break; - } - default: - break; - } - } - else if ((m_state == LOG_BACKEND_FLASH_INACTIVE) && - (p_evt->id == NRF_FSTORAGE_EVT_ERASE_RESULT) && - (p_evt->addr == RUNTIME_START_ADDR)) - { - m_state = LOG_BACKEND_FLASH_ACTIVE; - } -} - -/** - * @brief Function for enqueueing new message. - * - * If queue is full then the oldest message is freed. - * - * @param p_queue Queue. - * @param p_msg Message. - * - * @return Number of dropped messages - */ -static uint32_t message_enqueue(nrf_queue_t const * p_queue, nrf_log_entry_t * p_msg) -{ - uint32_t dropped = 0; - - //flag was set, busy so enqueue message - while (nrf_queue_push(p_queue, &p_msg) != NRF_SUCCESS) - { - - nrf_log_entry_t * p_old_msg; - if (nrf_queue_pop(p_queue, &p_old_msg) == NRF_SUCCESS) - { - nrf_memobj_put(p_old_msg); - dropped++; - } - } - - return dropped; -} - - -void nrf_log_backend_flashlog_put(nrf_log_backend_t const * p_backend, - nrf_log_entry_t * p_msg) -{ - if (m_state == LOG_BACKEND_FLASH_ACTIVE) - { - nrf_memobj_get(p_msg); - - m_dropped += message_enqueue(mp_flashlog_queue, p_msg); - - if (nrf_atomic_flag_set_fetch(&m_busy_flag) == 0) - { - log_msg_queue_process(mp_flashlog_queue, false); - } - } -} - - -void nrf_log_backend_crashlog_put(nrf_log_backend_t const * p_backend, - nrf_log_entry_t * p_msg) -{ - if (m_state != LOG_BACKEND_FLASH_INACTIVE) - { - nrf_memobj_get(p_msg); - - UNUSED_RETURN_VALUE(message_enqueue(mp_crashlog_queue, p_msg)); - } - - if (m_state == LOG_BACKEND_FLASH_IN_PANIC) - { - log_msg_queue_process(mp_crashlog_queue, true); - } -} - -void nrf_log_backend_flashlog_flush(nrf_log_backend_t const * p_backend) -{ - queue_element_drop(mp_flashlog_queue); -} - -void nrf_log_backend_crashlog_flush(nrf_log_backend_t const * p_backend) -{ - queue_element_drop(mp_crashlog_queue); -} - -void nrf_log_backend_flashlog_panic_set(nrf_log_backend_t const * p_backend) -{ - /* Empty */ -} - -/** - * @brief Function for injecting log message which will indicate start of crash log. - */ -static void crashlog_marker_inject(void) -{ - nrf_log_header_t crashlog_marker_hdr = { - .base = { - .std = { - .type = HEADER_TYPE_STD, - .severity = NRF_LOG_SEVERITY_INFO_RAW, - .nargs = 0, - .addr = (uint32_t)crashlog_str & STD_ADDR_MASK - } - }, - .module_id = 0, - .timestamp = 0, - }; - m_flash_buf[0] = crashlog_marker_hdr.base.raw; - m_flash_buf[1] = crashlog_marker_hdr.module_id; - m_flash_buf[2] = crashlog_marker_hdr.timestamp; - (void)nrf_fstorage_write(&m_log_flash_fstorage, m_curr_addr, m_flash_buf, LOG_HEADER_LEN, NULL); - m_curr_addr += LOG_HEADER_LEN; -} - - -void nrf_log_backend_crashlog_panic_set(nrf_log_backend_t const * p_backend) -{ - if (nrf_fstorage_init(&m_log_flash_fstorage, &nrf_fstorage_nvmc, NULL) == NRF_SUCCESS) - { - m_state = LOG_BACKEND_FLASH_IN_PANIC; - - /* In case of Softdevice MWU may protect access to NVMC. */ - NVIC_DisableIRQ(MWU_IRQn); - - log_msg_queue_process(mp_flashlog_queue, true); - - crashlog_marker_inject(); - - log_msg_queue_process(mp_crashlog_queue, true); - } - else - { - m_state = LOG_BACKEND_FLASH_INACTIVE; - } -} - -/** - * @brief Function for determining first empty location in area dedicated for flash logger backend. - */ -static uint32_t empty_addr_get(void) -{ - uint32_t token = 0; - nrf_log_header_t * p_dummy_header; - uint8_t * p_dummy_data; - - while(nrf_log_backend_flash_next_entry_get(&token, &p_dummy_header, &p_dummy_data) == NRF_SUCCESS) - { - - } - - return token; -} - - -ret_code_t nrf_log_backend_flash_init(nrf_fstorage_api_t const * p_fs_api) -{ - ret_code_t err_code; - - - uint32_t start_addr = RUNTIME_START_ADDR; - uint32_t end_addr = start_addr + FLASH_LOG_SIZE - 1; - - m_log_flash_fstorage.start_addr = start_addr; - m_log_flash_fstorage.end_addr = end_addr; - - err_code = nrf_fstorage_init(&m_log_flash_fstorage, p_fs_api, NULL); - if (err_code != NRF_SUCCESS) - { - return err_code; - } - - m_curr_addr = empty_addr_get(); - m_state = LOG_BACKEND_FLASH_ACTIVE; - - return err_code; -} - - -ret_code_t nrf_log_backend_flash_next_entry_get(uint32_t * p_token, - nrf_log_header_t * * pp_header, - uint8_t * * pp_data) -{ - uint32_t * p_addr = p_token; - uint32_t len; - - *p_addr = (*p_addr == 0) ? RUNTIME_START_ADDR : *p_addr; - - if (nrf_fstorage_rmap(&m_log_flash_fstorage, *p_addr) == NULL) - { - //Supports only memories which can be mapped for reading. - return NRF_ERROR_NOT_SUPPORTED; - } - - if (msg_from_buf((uint32_t *)*p_addr, pp_header, pp_data, &len)) - { - *p_addr += len; - return NRF_SUCCESS; - } - else - { - return NRF_ERROR_NOT_FOUND; - } -} - - -ret_code_t nrf_log_backend_flash_erase(void) -{ - ret_code_t err_code; - - m_state = LOG_BACKEND_FLASH_INACTIVE; - err_code = nrf_fstorage_erase(&m_log_flash_fstorage, RUNTIME_START_ADDR, NRF_LOG_BACKEND_PAGES, NULL); - - m_curr_addr = RUNTIME_START_ADDR; - - return err_code; -} - -#if NRF_LOG_BACKEND_FLASHLOG_ENABLED -const nrf_log_backend_api_t nrf_log_backend_flashlog_api = { - .put = nrf_log_backend_flashlog_put, - .flush = nrf_log_backend_flashlog_flush, - .panic_set = nrf_log_backend_flashlog_panic_set, -}; -#endif - -#if NRF_LOG_BACKEND_CRASHLOG_ENABLED -const nrf_log_backend_api_t nrf_log_backend_crashlog_api = { - .put = nrf_log_backend_crashlog_put, - .flush = nrf_log_backend_crashlog_flush, - .panic_set = nrf_log_backend_crashlog_panic_set, -}; -#endif - -#if NRF_LOG_BACKEND_FLASH_CLI_CMDS -#include "nrf_cli.h" - -static uint8_t m_buffer[64]; -static nrf_cli_t const * mp_cli; - -static void cli_tx(void const * p_context, char const * p_buffer, size_t len); - -static nrf_fprintf_ctx_t m_fprintf_ctx = -{ - .p_io_buffer = (char *)m_buffer, - .io_buffer_size = sizeof(m_buffer)-1, - .io_buffer_cnt = 0, - .auto_flush = true, - .p_user_ctx = &mp_cli, - .fwrite = cli_tx -}; - - -static void flashlog_clear_cmd(nrf_cli_t const * p_cli, size_t argc, char ** argv) -{ - if (nrf_cli_help_requested(p_cli)) - { - nrf_cli_help_print(p_cli, NULL, 0); - } - - UNUSED_RETURN_VALUE(nrf_log_backend_flash_erase()); -} - -#include "nrf_delay.h" -static void cli_tx(void const * p_context, char const * p_buffer, size_t len) -{ - nrf_cli_t * * pp_cli = (nrf_cli_t * *)p_context; - char * p_strbuf = (char *)&p_buffer[len]; - *p_strbuf = '\0'; - nrf_cli_fprintf((nrf_cli_t const *)*pp_cli, NRF_CLI_DEFAULT, p_buffer); - // nrf_delay_ms(10); -} - - -static void entry_process(nrf_cli_t const * p_cli, nrf_log_header_t * p_header, uint8_t * p_data) -{ - mp_cli = p_cli; - - nrf_log_str_formatter_entry_params_t params = - { - .timestamp = p_header->timestamp, - .module_id = p_header->module_id, - .use_colors = 0, - }; - - switch (p_header->base.generic.type) - { - case HEADER_TYPE_STD: - { - params.severity = (nrf_log_severity_t)p_header->base.std.severity; - nrf_log_std_entry_process((const char *)((uint32_t)p_header->base.std.addr), - (uint32_t *)p_data, - p_header->base.std.nargs, - ¶ms, - &m_fprintf_ctx); - break; - } - case HEADER_TYPE_HEXDUMP: - { - params.severity = (nrf_log_severity_t)p_header->base.hexdump.severity; - - nrf_log_hexdump_entry_process(p_data, - p_header->base.hexdump.len, - ¶ms, - &m_fprintf_ctx); - break; - } - default: - ASSERT(0); - } - -} - - -static void flashlog_read_cmd(nrf_cli_t const * p_cli, size_t argc, char ** argv) -{ - if (nrf_cli_help_requested(p_cli)) - { - nrf_cli_help_print(p_cli, NULL, 0); - } - - uint32_t token = 0; - uint8_t * p_data = NULL; - bool empty = true; - nrf_log_header_t * p_header; - - while (1) - { - if (nrf_log_backend_flash_next_entry_get(&token, &p_header, &p_data) == NRF_SUCCESS) - { - entry_process(p_cli, p_header, p_data); - empty = false; - } - else - { - break; - } - } - - if (empty) - { - nrf_cli_fprintf(p_cli, NRF_CLI_ERROR, "Flash log empty\r\n"); - } -} - - -static void flashlog_status_cmd(nrf_cli_t const * p_cli, size_t argc, char ** argv) -{ - if (nrf_cli_help_requested(p_cli)) - { - nrf_cli_help_print(p_cli, NULL, 0); - } - - nrf_cli_fprintf(p_cli, NRF_CLI_NORMAL, "Flash log status:\r\n"); - nrf_cli_fprintf(p_cli, NRF_CLI_NORMAL, "\t\t- Location (address: 0x%08X, length: %d)\r\n", - RUNTIME_START_ADDR, FLASH_LOG_SIZE); - nrf_cli_fprintf(p_cli, NRF_CLI_NORMAL, "\t\t- Current usage:%d%% (%d of %d bytes used)\r\n", - 100ul * (m_curr_addr - RUNTIME_START_ADDR)/FLASH_LOG_SIZE, - m_curr_addr - RUNTIME_START_ADDR, - FLASH_LOG_SIZE); - nrf_cli_fprintf(p_cli, NRF_CLI_NORMAL, "\t\t- Dropped logs: %d\r\n", m_dropped); - - -} - - -NRF_CLI_CREATE_STATIC_SUBCMD_SET(m_flashlog_cmd) -{ - NRF_CLI_CMD(clear, NULL, "Remove logs", flashlog_clear_cmd), - NRF_CLI_CMD(read, NULL, "Read stored logs", flashlog_read_cmd), - NRF_CLI_CMD(status, NULL, "Flash log status", flashlog_status_cmd), - NRF_CLI_SUBCMD_SET_END -}; - -NRF_CLI_CMD_REGISTER(flashlog, &m_flashlog_cmd, "Commands for reading logs stored in non-volatile memory", NULL); - -#endif //NRF_LOG_BACKEND_FLASH_CLI_CMDS - -#endif //NRF_MODULE_ENABLED(NRF_LOG) && NRF_MODULE_ENABLED(NRF_LOG_BACKEND_FLASH) diff --git a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_backend_rtt.c b/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_backend_rtt.c deleted file mode 100644 index 56bba5cf54..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_backend_rtt.c +++ /dev/null @@ -1,123 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include "sdk_common.h" -#if NRF_MODULE_ENABLED(NRF_LOG) && NRF_MODULE_ENABLED(NRF_LOG_BACKEND_RTT) -#include "nrf_log_backend_rtt.h" -#include "nrf_log_backend_serial.h" -#include "nrf_log_str_formatter.h" -#include "nrf_log_internal.h" -#include "nrf_delay.h" -#include -#include - -static bool m_host_present; - -static uint8_t m_string_buff[NRF_LOG_BACKEND_RTT_TEMP_BUFFER_SIZE]; - -void nrf_log_backend_rtt_init(void) -{ - SEGGER_RTT_Init(); -} - -static void serial_tx(void const * p_context, char const * buffer, size_t len) -{ - if (len) - { - uint32_t idx = 0; - uint32_t processed; - uint32_t watchdog_counter = NRF_LOG_BACKEND_RTT_TX_RETRY_CNT; - do - { - processed = SEGGER_RTT_WriteNoLock(0, &buffer[idx], len); - idx += processed; - len -= processed; - if (processed == 0) - { - /* There are two possible reasons for not writing any data to RTT: - * - The host is not connected and not reading the data. - * - The buffer got full and will be read by the host. - * These two situations are distinguished using the following algorithm. - * At the begining, the module assumes that the host is active, - * so when no data is read, it busy waits and retries. - * If, after retrying, the host reads the data, the module assumes that the host is active. - * If it fails, the module assumes that the host is inactive and stores that information. On next - * call, only one attempt takes place. The host is marked as active if the attempt is successful. - */ - if (!m_host_present) - { - break; - } - else - { - nrf_delay_ms(NRF_LOG_BACKEND_RTT_TX_RETRY_DELAY_MS); - watchdog_counter--; - if (watchdog_counter == 0) - { - m_host_present = false; - break; - } - } - } - m_host_present = true; - } while (len); - } -} -static void nrf_log_backend_rtt_put(nrf_log_backend_t const * p_backend, - nrf_log_entry_t * p_msg) -{ - nrf_log_backend_serial_put(p_backend, p_msg, m_string_buff, NRF_LOG_BACKEND_RTT_TEMP_BUFFER_SIZE, serial_tx); -} - -static void nrf_log_backend_rtt_flush(nrf_log_backend_t const * p_backend) -{ - -} - -static void nrf_log_backend_rtt_panic_set(nrf_log_backend_t const * p_backend) -{ - -} - -const nrf_log_backend_api_t nrf_log_backend_rtt_api = { - .put = nrf_log_backend_rtt_put, - .flush = nrf_log_backend_rtt_flush, - .panic_set = nrf_log_backend_rtt_panic_set, -}; -#endif //NRF_MODULE_ENABLED(NRF_LOG) && NRF_MODULE_ENABLED(NRF_LOG_BACKEND_RTT) diff --git a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_backend_serial.c b/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_backend_serial.c deleted file mode 100644 index e604d37359..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_backend_serial.c +++ /dev/null @@ -1,115 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include "sdk_common.h" -#if NRF_MODULE_ENABLED(NRF_LOG) -#include "nrf_log_backend_serial.h" -#include "nrf_log_str_formatter.h" -#include "nrf_log_internal.h" - -void nrf_log_backend_serial_put(nrf_log_backend_t const * p_backend, - nrf_log_entry_t * p_msg, - uint8_t * p_buffer, - uint32_t length, - nrf_fprintf_fwrite tx_func) -{ - nrf_memobj_get(p_msg); - - nrf_fprintf_ctx_t fprintf_ctx = { - .p_io_buffer = (char *)p_buffer, - .io_buffer_size = length, - .io_buffer_cnt = 0, - .auto_flush = false, - .p_user_ctx = NULL, - .fwrite = tx_func - }; - - nrf_log_str_formatter_entry_params_t params; - - nrf_log_header_t header; - uint32_t memobj_offset = 0; - nrf_memobj_read(p_msg, &header, HEADER_SIZE*sizeof(uint32_t), memobj_offset); - memobj_offset = HEADER_SIZE*sizeof(uint32_t); - - params.timestamp = header.timestamp; - params.module_id = header.module_id; - params.dropped = header.dropped; - params.use_colors = NRF_LOG_USES_COLORS; - - /*lint -save -e438*/ - if (header.base.generic.type == HEADER_TYPE_STD) - { - char const * p_log_str = (char const *)((uint32_t)header.base.std.addr); - params.severity = (nrf_log_severity_t)header.base.std.severity; - uint32_t nargs = header.base.std.nargs; - uint32_t args[NRF_LOG_MAX_NUM_OF_ARGS]; - - nrf_memobj_read(p_msg, args, nargs*sizeof(uint32_t), memobj_offset); - memobj_offset += (nargs*sizeof(uint32_t)); - - nrf_log_std_entry_process(p_log_str, - args, - nargs, - ¶ms, - &fprintf_ctx); - - } - else if (header.base.generic.type == HEADER_TYPE_HEXDUMP) - { - uint32_t data_len = header.base.hexdump.len; - params.severity = (nrf_log_severity_t)header.base.hexdump.severity; - uint8_t data_buf[8]; - uint32_t chunk_len; - do - { - chunk_len = sizeof(data_buf) > data_len ? data_len : sizeof(data_buf); - nrf_memobj_read(p_msg, data_buf, chunk_len, memobj_offset); - memobj_offset += chunk_len; - data_len -= chunk_len; - - nrf_log_hexdump_entry_process(data_buf, - chunk_len, - ¶ms, - &fprintf_ctx); - } while (data_len > 0); - } - nrf_memobj_put(p_msg); - /*lint -restore*/ -} -#endif //NRF_LOG_ENABLED diff --git a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_backend_serial.h b/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_backend_serial.h deleted file mode 100644 index 26459ca862..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_backend_serial.h +++ /dev/null @@ -1,77 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef NRF_LOG_BACKEND_SERIAL_H -#define NRF_LOG_BACKEND_SERIAL_H -/**@file - * @addtogroup nrf_log Logger module - * @ingroup app_common - * - * @defgroup nrf_log_backend_serial Common part of serial backends - * @{ - * @ingroup nrf_log - * @brief The nrf_log serial backend common put function. - */ - - -#include "nrf_log_backend_interface.h" -#include "nrf_fprintf.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief A function for processing logger entry with simple serial interface as output. - * - * - */ -void nrf_log_backend_serial_put(nrf_log_backend_t const * p_backend, - nrf_log_entry_t * p_msg, - uint8_t * p_buffer, - uint32_t length, - nrf_fprintf_fwrite tx_func); - -#endif //NRF_LOG_BACKEND_SERIAL_H - -#ifdef __cplusplus -} -#endif - -/** @} */ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_backend_uart.c b/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_backend_uart.c deleted file mode 100644 index ae6f8eaeb4..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_backend_uart.c +++ /dev/null @@ -1,116 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include "sdk_common.h" -#if NRF_MODULE_ENABLED(NRF_LOG) && NRF_MODULE_ENABLED(NRF_LOG_BACKEND_UART) -#include "nrf_log_backend_uart.h" -#include "nrf_log_backend_serial.h" -#include "nrf_log_internal.h" -#include "nrf_drv_uart.h" -#include "app_error.h" - -nrf_drv_uart_t m_uart = NRF_DRV_UART_INSTANCE(0); - -static uint8_t m_string_buff[NRF_LOG_BACKEND_UART_TEMP_BUFFER_SIZE]; -static volatile bool m_xfer_done; -static bool m_async_mode; -static void uart_evt_handler(nrf_drv_uart_event_t * p_event, void * p_context) -{ - m_xfer_done = true; -} - -static void uart_init(bool async_mode) -{ - nrf_drv_uart_config_t config = NRF_DRV_UART_DEFAULT_CONFIG; - config.pseltxd = NRF_LOG_BACKEND_UART_TX_PIN; - config.pselrxd = NRF_UART_PSEL_DISCONNECTED; - config.pselcts = NRF_UART_PSEL_DISCONNECTED; - config.pselrts = NRF_UART_PSEL_DISCONNECTED; - config.baudrate = (nrf_uart_baudrate_t)NRF_LOG_BACKEND_UART_BAUDRATE; - ret_code_t err_code = nrf_drv_uart_init(&m_uart, &config, async_mode ? uart_evt_handler : NULL); - APP_ERROR_CHECK(err_code); - - m_async_mode = async_mode; -} - -void nrf_log_backend_uart_init(void) -{ - bool async_mode = NRF_LOG_DEFERRED ? true : false; - uart_init(async_mode); -} - -static void serial_tx(void const * p_context, char const * p_buffer, size_t len) -{ - uint8_t len8 = (uint8_t)(len & 0x000000FF); - m_xfer_done = false; - ret_code_t err_code = nrf_drv_uart_tx(&m_uart, (uint8_t *)p_buffer, len8); - APP_ERROR_CHECK(err_code); - /* wait for completion since buffer is reused*/ - while (m_async_mode && (m_xfer_done == false)) - { - - } - -} - -static void nrf_log_backend_uart_put(nrf_log_backend_t const * p_backend, - nrf_log_entry_t * p_msg) -{ - nrf_log_backend_serial_put(p_backend, p_msg, m_string_buff, - NRF_LOG_BACKEND_UART_TEMP_BUFFER_SIZE, serial_tx); -} - -static void nrf_log_backend_uart_flush(nrf_log_backend_t const * p_backend) -{ - -} - -static void nrf_log_backend_uart_panic_set(nrf_log_backend_t const * p_backend) -{ - nrf_drv_uart_uninit(&m_uart); - - uart_init(false); -} - -const nrf_log_backend_api_t nrf_log_backend_uart_api = { - .put = nrf_log_backend_uart_put, - .flush = nrf_log_backend_uart_flush, - .panic_set = nrf_log_backend_uart_panic_set, -}; -#endif //NRF_MODULE_ENABLED(NRF_LOG) && NRF_MODULE_ENABLED(NRF_LOG_BACKEND_UART) diff --git a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_ctrl_internal.h b/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_ctrl_internal.h deleted file mode 100644 index 7b29889136..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_ctrl_internal.h +++ /dev/null @@ -1,80 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef NRF_LOG_CTRL_INTERNAL_H -#define NRF_LOG_CTRL_INTERNAL_H -/** - * @cond (NODOX) - * @defgroup nrf_log_ctrl_internal Auxiliary internal types declarations - * @{ - * @internal - */ - -#include "sdk_common.h" -#if NRF_MODULE_ENABLED(NRF_LOG) -#define NRF_LOG_INTERNAL_INIT(...) \ - nrf_log_init(GET_VA_ARG_1(__VA_ARGS__), \ - GET_VA_ARG_1(GET_ARGS_AFTER_1(__VA_ARGS__, NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY))) - -#define NRF_LOG_INTERNAL_PROCESS() nrf_log_frontend_dequeue() -#define NRF_LOG_INTERNAL_FLUSH() \ - do { \ - while (NRF_LOG_INTERNAL_PROCESS()); \ - } while (0) - -#define NRF_LOG_INTERNAL_FINAL_FLUSH() \ - do { \ - nrf_log_panic(); \ - NRF_LOG_INTERNAL_FLUSH(); \ - } while (0) - - -#else // NRF_MODULE_ENABLED(NRF_LOG) -#define NRF_LOG_INTERNAL_PROCESS() false -#define NRF_LOG_INTERNAL_FLUSH() -#define NRF_LOG_INTERNAL_INIT(timestamp_func) NRF_SUCCESS -#define NRF_LOG_INTERNAL_HANDLERS_SET(default_handler, bytes_handler) \ - UNUSED_PARAMETER(default_handler); UNUSED_PARAMETER(bytes_handler) -#define NRF_LOG_INTERNAL_FINAL_FLUSH() -#endif // NRF_MODULE_ENABLED(NRF_LOG) - -/** @} - * @endcond - */ -#endif // NRF_LOG_CTRL_INTERNAL_H diff --git a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_default_backends.c b/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_default_backends.c deleted file mode 100644 index 351aaa3ff4..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_default_backends.c +++ /dev/null @@ -1,76 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include "sdk_common.h" -#if NRF_MODULE_ENABLED(NRF_LOG) -#include "nrf_log_default_backends.h" -#include "nrf_log_ctrl.h" -#include "nrf_log_internal.h" -#include "nrf_assert.h" - -#if defined(NRF_LOG_BACKEND_RTT_ENABLED) && NRF_LOG_BACKEND_RTT_ENABLED -#include "nrf_log_backend_rtt.h" -NRF_LOG_BACKEND_RTT_DEF(rtt_log_backend); -#endif - -#if defined(NRF_LOG_BACKEND_UART_ENABLED) && NRF_LOG_BACKEND_UART_ENABLED -#include "nrf_log_backend_uart.h" -NRF_LOG_BACKEND_UART_DEF(uart_log_backend); -#endif - -void nrf_log_default_backends_init(void) -{ - int32_t backend_id = -1; - (void)backend_id; -#if defined(NRF_LOG_BACKEND_RTT_ENABLED) && NRF_LOG_BACKEND_RTT_ENABLED - nrf_log_backend_rtt_init(); - backend_id = nrf_log_backend_add(&rtt_log_backend.backend, NRF_LOG_SEVERITY_DEBUG); - ASSERT(backend_id >= 0); - nrf_log_backend_enable(&rtt_log_backend.backend); -#endif - -#if defined(NRF_LOG_BACKEND_UART_ENABLED) && NRF_LOG_BACKEND_UART_ENABLED - nrf_log_backend_uart_init(); - backend_id = nrf_log_backend_add(&uart_log_backend.backend, NRF_LOG_SEVERITY_DEBUG); - ASSERT(backend_id >= 0); - nrf_log_backend_enable(&uart_log_backend.backend); -#endif -} -#endif diff --git a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_frontend.c b/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_frontend.c deleted file mode 100644 index 343b6de220..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_frontend.c +++ /dev/null @@ -1,1245 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include "sdk_common.h" -#if NRF_MODULE_ENABLED(NRF_LOG) -#include "app_util.h" -#include "app_util_platform.h" -#include "nrf_log.h" -#include "nrf_log_internal.h" -#include "nrf_log_ctrl.h" -#include "nrf_log_str_formatter.h" -#include "nrf_section.h" -#include "nrf_memobj.h" -#include "nrf_atomic.h" -#include - -STATIC_ASSERT((NRF_LOG_BUFSIZE % 4) == 0); -STATIC_ASSERT(IS_POWER_OF_TWO(NRF_LOG_BUFSIZE)); - -#define NRF_LOG_BUF_WORDS (NRF_LOG_BUFSIZE/4) - -#if NRF_LOG_BUF_WORDS < 32 -#warning "NRF_LOG_BUFSIZE too small, significant number of logs may be lost." -#endif - -NRF_MEMOBJ_POOL_DEF(log_mempool, NRF_LOG_MSGPOOL_ELEMENT_SIZE, NRF_LOG_MSGPOOL_ELEMENT_COUNT); - -#define NRF_LOG_BACKENDS_FULL 0xFF -#define NRF_LOG_FILTER_BITS_PER_BACKEND 3 -#define NRF_LOG_MAX_BACKENDS (32/NRF_LOG_FILTER_BITS_PER_BACKEND) -#define NRF_LOG_MAX_HEXDUMP (NRF_LOG_MSGPOOL_ELEMENT_SIZE*NRF_LOG_MSGPOOL_ELEMENT_COUNT/2) - -/** - * brief An internal control block of the logger - * - * @note Circular buffer is using never cleared indexes and a mask. It means - * that logger may break when indexes overflows. However, it is quite unlikely. - * With rate of 1000 log entries with 2 parameters per second such situation - * would happen after 12 days. - */ -typedef struct -{ - uint32_t wr_idx; // Current write index (never reset) - uint32_t rd_idx; // Current read index (never_reset) - uint32_t mask; // Size of buffer (must be power of 2) presented as mask - uint32_t buffer[NRF_LOG_BUF_WORDS]; - nrf_log_timestamp_func_t timestamp_func; // A pointer to function that returns timestamp - nrf_log_backend_t * p_backend_head; - nrf_atomic_flag_t log_skipping; - nrf_atomic_flag_t log_skipped; - nrf_atomic_u32_t log_dropped_cnt; - bool autoflush; -} log_data_t; - -static log_data_t m_log_data; - -/*lint -save -esym(526,log_const_data*) -esym(526,log_dynamic_data*)*/ -NRF_SECTION_DEF(log_dynamic_data, NRF_LOG_DYNAMIC_STRUCT_NAME); -NRF_SECTION_DEF(log_const_data, nrf_log_module_const_data_t); -/*lint -restore*/ -NRF_LOG_MODULE_REGISTER(); -// Helper macros for section variables. -#define NRF_LOG_DYNAMIC_SECTION_VARS_GET(i) NRF_SECTION_ITEM_GET(log_dynamic_data, NRF_LOG_DYNAMIC_STRUCT_NAME, (i)) - -#define NRF_LOG_CONST_SECTION_VARS_GET(i) NRF_SECTION_ITEM_GET(log_const_data, nrf_log_module_const_data_t, (i)) -#define NRF_LOG_CONST_SECTION_VARS_COUNT NRF_SECTION_ITEM_COUNT(log_const_data, nrf_log_module_const_data_t) - -#define PUSHED_HEADER_FILL(P_HDR, OFFSET, LENGTH) \ - (P_HDR)->base.raw = 0; \ - (P_HDR)->base.pushed.type = HEADER_TYPE_PUSHED; \ - (P_HDR)->base.pushed.offset = OFFSET; \ - (P_HDR)->base.pushed.len = LENGTH - - -ret_code_t nrf_log_init(nrf_log_timestamp_func_t timestamp_func, uint32_t timestamp_freq) -{ - if (NRF_LOG_USES_TIMESTAMP && (timestamp_func == NULL)) - { - return NRF_ERROR_INVALID_PARAM; - } - - m_log_data.mask = NRF_LOG_BUF_WORDS - 1; - m_log_data.wr_idx = 0; - m_log_data.rd_idx = 0; - m_log_data.log_skipped = 0; - m_log_data.log_skipping = 0; - m_log_data.autoflush = NRF_LOG_DEFERRED ? false : true; - if (NRF_LOG_USES_TIMESTAMP) - { - nrf_log_str_formatter_timestamp_freq_set(timestamp_freq); - m_log_data.timestamp_func = timestamp_func; - } - - ret_code_t err_code = nrf_memobj_pool_init(&log_mempool); - if (err_code != NRF_SUCCESS) - { - return err_code; - } - - uint32_t modules_cnt = NRF_LOG_CONST_SECTION_VARS_COUNT; - uint32_t i; - if (NRF_LOG_FILTERS_ENABLED) - { - uint32_t j; - //sort modules by name - for (i = 0; i < modules_cnt; i++) - { - uint32_t idx = 0; - - for (j = 0; j < modules_cnt; j++) - { - if (i != j) - { - char const * p_name0 = NRF_LOG_CONST_SECTION_VARS_GET(i)->p_module_name; - char const * p_name1 = NRF_LOG_CONST_SECTION_VARS_GET(j)->p_module_name; - if (strncmp(p_name0, p_name1, 20) > 0) - { - idx++; - } - } - - } - nrf_log_module_dynamic_data_t * p_module_ddata = - (nrf_log_module_dynamic_data_t *)NRF_LOG_DYNAMIC_SECTION_VARS_GET(i); - p_module_ddata->filter = 0; - p_module_ddata->module_id = i; - p_module_ddata->order_idx = idx; - } - } - else - { - for(i = 0; i < modules_cnt; i++) - { - nrf_log_module_reduced_dynamic_data_t * p_module_ddata = - (nrf_log_module_reduced_dynamic_data_t *)NRF_LOG_DYNAMIC_SECTION_VARS_GET(i); - p_module_ddata->module_id = i; - } - } - - return NRF_SUCCESS; -} - -uint32_t nrf_log_module_cnt_get(void) -{ - return NRF_LOG_CONST_SECTION_VARS_COUNT; -} - -static ret_code_t module_idx_get(uint32_t * p_idx, bool ordered_idx) -{ - if (ordered_idx) - { - uint32_t module_cnt = nrf_log_module_cnt_get(); - uint32_t i; - for (i = 0; i < module_cnt; i++) - { - nrf_log_module_dynamic_data_t * p_module_data = - (nrf_log_module_dynamic_data_t *)NRF_LOG_DYNAMIC_SECTION_VARS_GET(i); - if (p_module_data->order_idx == *p_idx) - { - *p_idx = i; - return NRF_SUCCESS; - } - } - return NRF_ERROR_NOT_FOUND; - } - else - { - return NRF_SUCCESS; - } -} -const char * nrf_log_module_name_get(uint32_t module_id, bool ordered_idx) -{ - if (module_idx_get(&module_id, ordered_idx) == NRF_SUCCESS) - { - nrf_log_module_const_data_t * p_module_data = NRF_LOG_CONST_SECTION_VARS_GET(module_id); - return p_module_data->p_module_name; - } - else - { - return NULL; - } -} - -uint8_t nrf_log_color_id_get(uint32_t module_id, nrf_log_severity_t severity) -{ - nrf_log_module_const_data_t * p_module_data = NRF_LOG_CONST_SECTION_VARS_GET(module_id); - uint8_t color_id; - switch (severity) - { - case NRF_LOG_SEVERITY_ERROR: - color_id = NRF_LOG_ERROR_COLOR; - break; - case NRF_LOG_SEVERITY_WARNING: - color_id = NRF_LOG_WARNING_COLOR; - break; - case NRF_LOG_SEVERITY_INFO: - color_id = p_module_data->info_color_id; - break; - case NRF_LOG_SEVERITY_DEBUG: - color_id = p_module_data->debug_color_id; - break; - default: - color_id = 0; - break; - } - return color_id; -} - -static uint32_t higher_lvl_get(uint32_t lvls) -{ - uint32_t top_lvl = 0; - uint32_t tmp_lvl; - uint32_t i; - - //Find highest level enabled by backends - for (i = 0; i < (32/NRF_LOG_LEVEL_BITS); i+=NRF_LOG_LEVEL_BITS) - { - tmp_lvl = BF_GET(lvls,NRF_LOG_LEVEL_BITS, i); - if (tmp_lvl > top_lvl) - { - top_lvl = tmp_lvl; - } - } - return top_lvl; -} - -void nrf_log_module_filter_set(uint32_t backend_id, uint32_t module_id, nrf_log_severity_t severity) -{ - if (NRF_LOG_FILTERS_ENABLED) - { - nrf_log_module_dynamic_data_t * p_module_filter = - (nrf_log_module_dynamic_data_t *)NRF_LOG_DYNAMIC_SECTION_VARS_GET(module_id); - p_module_filter->filter_lvls &= ~(NRF_LOG_LEVEL_MASK << (NRF_LOG_LEVEL_BITS * backend_id)); - p_module_filter->filter_lvls |= (severity & NRF_LOG_LEVEL_MASK) << (NRF_LOG_LEVEL_BITS * backend_id); - p_module_filter->filter = higher_lvl_get(p_module_filter->filter_lvls); - } -} - -static nrf_log_severity_t nrf_log_module_init_filter_get(uint32_t module_id) -{ - nrf_log_module_const_data_t * p_module_data = - NRF_LOG_CONST_SECTION_VARS_GET(module_id); - return NRF_LOG_FILTERS_ENABLED ? p_module_data->initial_lvl : p_module_data->compiled_lvl; -} - -nrf_log_severity_t nrf_log_module_filter_get(uint32_t backend_id, - uint32_t module_id, - bool ordered_idx, - bool dynamic) -{ - nrf_log_severity_t severity = NRF_LOG_SEVERITY_NONE; - if (NRF_LOG_FILTERS_ENABLED && dynamic) - { - if (module_idx_get(&module_id, ordered_idx) == NRF_SUCCESS) - { - nrf_log_module_dynamic_data_t * p_module_filter = - (nrf_log_module_dynamic_data_t *)NRF_LOG_DYNAMIC_SECTION_VARS_GET(module_id); - severity = (nrf_log_severity_t)((p_module_filter->filter_lvls >> (NRF_LOG_LEVEL_BITS * backend_id)) & - NRF_LOG_LEVEL_MASK); - } - } - else if (!dynamic) - { - if (module_idx_get(&module_id, ordered_idx) == NRF_SUCCESS) - { - nrf_log_module_const_data_t * p_module_data = - NRF_LOG_CONST_SECTION_VARS_GET(module_id); - severity = (nrf_log_severity_t)p_module_data->compiled_lvl; - } - } - return severity; -} -/** - * Function examines current header and omits pushed strings and packets which are in progress. - */ -static bool invalid_packets_pushed_str_omit(nrf_log_header_t const * p_header, uint32_t * p_rd_idx) -{ - bool ret = false; - if ((p_header->base.generic.type == HEADER_TYPE_PUSHED) || (p_header->base.generic.in_progress == 1)) - { - if (p_header->base.generic.in_progress == 1) - { - switch (p_header->base.generic.type) - { - case HEADER_TYPE_STD: - *p_rd_idx += (HEADER_SIZE + p_header->base.std.nargs); - break; - case HEADER_TYPE_HEXDUMP: - *p_rd_idx += (HEADER_SIZE + p_header->base.hexdump.len); - break; - default: - ASSERT(0); - break; - } - } - else - { - *p_rd_idx += - (PUSHED_HEADER_SIZE + p_header->base.pushed.len + p_header->base.pushed.offset); - } - ret = true; - } - return ret; -} -/** - * @brief Skips the oldest, not pushed logs to make space for new logs. - * @details This function moves forward read index to prepare space for new logs. - */ - -static uint32_t log_skip(void) -{ - uint16_t dropped = 0; - - (void)nrf_atomic_flag_set(&m_log_data.log_skipped); - (void)nrf_atomic_flag_set(&m_log_data.log_skipping); - - uint32_t rd_idx = m_log_data.rd_idx; - uint32_t mask = m_log_data.mask; - nrf_log_header_t * p_header = (nrf_log_header_t *)&m_log_data.buffer[rd_idx & mask]; - nrf_log_header_t header; - - // Skip any string that is pushed to the circular buffer. - do { - if (invalid_packets_pushed_str_omit(p_header, &rd_idx)) - { - //something was omitted. Point to new header and try again. - p_header = (nrf_log_header_t *)&m_log_data.buffer[rd_idx & mask]; - } - else - { - break; - } - } while (true); - - uint32_t i; - for (i = 0; i < HEADER_SIZE; i++) - { - ((uint32_t*)&header)[i] = m_log_data.buffer[rd_idx++ & mask]; - } - - switch (header.base.generic.type) - { - case HEADER_TYPE_HEXDUMP: - dropped = header.dropped; - rd_idx += CEIL_DIV(header.base.hexdump.len, sizeof(uint32_t)); - break; - case HEADER_TYPE_STD: - dropped = header.dropped; - rd_idx += header.base.std.nargs; - break; - default: - ASSERT(false); - break; - } - - uint32_t log_skipping_tmp = nrf_atomic_flag_clear_fetch(&m_log_data.log_skipping); - //update read index only if log_skip was not interrupted by another log skip - if (log_skipping_tmp) - { - m_log_data.rd_idx = rd_idx; - } - - return (uint32_t)dropped; -} - -/** - * @brief Function for getting number of dropped logs. Dropped counter is reset after reading. - * - * @return Number of dropped logs saturated to 16 bits. - */ -static inline uint32_t dropped_sat16_get(void) -{ - uint32_t dropped = nrf_atomic_u32_fetch_store(&m_log_data.log_dropped_cnt, 0); - return __USAT(dropped, 16); //Saturate to 16 bits -} - - -static inline void std_header_set(uint32_t severity_mid, - char const * const p_str, - uint32_t nargs, - uint32_t wr_idx, - uint32_t mask) -{ - - - //Prepare header - in reverse order to ensure that packet type is validated (set to STD as last action) - uint32_t module_id = severity_mid >> NRF_LOG_MODULE_ID_POS; - uint32_t dropped = dropped_sat16_get(); - ASSERT(module_id < nrf_log_module_cnt_get()); - m_log_data.buffer[(wr_idx + 1) & mask] = module_id | (dropped << 16); - - if (NRF_LOG_USES_TIMESTAMP) - { - m_log_data.buffer[(wr_idx + 2) & mask] = m_log_data.timestamp_func(); - } - - nrf_log_header_t * p_header = (nrf_log_header_t *)&m_log_data.buffer[wr_idx & mask]; - p_header->base.std.severity = severity_mid & NRF_LOG_LEVEL_MASK; - p_header->base.std.nargs = nargs; - p_header->base.std.addr = ((uint32_t)(p_str) & STD_ADDR_MASK); - p_header->base.std.type = HEADER_TYPE_STD; - p_header->base.std.in_progress = 0; -} - -/** - * @brief Allocates chunk in a buffer for one entry and injects overflow if - * there is no room for requested entry. - * - * @param content_len Number of 32bit arguments. In case of allocating for hex dump it - * is the size of the buffer in 32bit words (ceiled). - * @param p_wr_idx Pointer to write index. - * - * @return True if successful allocation, false otherwise. - * - */ -static inline bool buf_prealloc(uint32_t content_len, uint32_t * p_wr_idx, bool std) -{ - uint32_t req_len = content_len + HEADER_SIZE; - bool ret = true; - CRITICAL_REGION_ENTER(); - *p_wr_idx = m_log_data.wr_idx; - uint32_t available_words = (m_log_data.mask + 1) - (m_log_data.wr_idx - m_log_data.rd_idx); - while (req_len > available_words) - { - UNUSED_RETURN_VALUE(nrf_atomic_u32_add(&m_log_data.log_dropped_cnt, 1)); - if (NRF_LOG_ALLOW_OVERFLOW) - { - uint32_t dropped_in_skip = log_skip(); - UNUSED_RETURN_VALUE(nrf_atomic_u32_add(&m_log_data.log_dropped_cnt, dropped_in_skip)); - available_words = (m_log_data.mask + 1) - (m_log_data.wr_idx - m_log_data.rd_idx); - } - else - { - ret = false; - break; - } - } - - if (ret) - { - nrf_log_main_header_t invalid_header; - invalid_header.raw = 0; - - if (std) - { - invalid_header.std.type = HEADER_TYPE_STD; - invalid_header.std.in_progress = 1; - invalid_header.std.nargs = content_len; - } - else - { - invalid_header.hexdump.type = HEADER_TYPE_HEXDUMP; - invalid_header.hexdump.in_progress = 1; - invalid_header.hexdump.len = content_len; - } - - nrf_log_main_header_t * p_header = (nrf_log_main_header_t *)&m_log_data.buffer[m_log_data.wr_idx & m_log_data.mask]; - - p_header->raw = invalid_header.raw; - - m_log_data.wr_idx += req_len; - } - - CRITICAL_REGION_EXIT(); - return ret; -} - - -/** - * @brief Function for preallocating a continuous chunk of memory from circular buffer. - * - * If buffer does not fit starting from current position it will be allocated at - * the beginning of the circular buffer and offset will be returned indicating - * how much memory has been ommited at the end of the buffer. Function is - * using critical section. - * - * @param len32 Length of buffer to allocate. Given in words. - * @param p_offset Offset of the buffer. - * @param p_wr_idx Pointer to write index. - * - * @return A pointer to the allocated buffer. NULL if allocation failed. - */ -static inline uint32_t * cont_buf_prealloc(uint32_t len32, - uint32_t * p_offset, - uint32_t * p_wr_idx) -{ - //allocation algorithm relies on that assumption - STATIC_ASSERT(PUSHED_HEADER_SIZE == 1); - uint32_t * p_buf = NULL; - - len32 += PUSHED_HEADER_SIZE; // Increment because 32bit header is needed to be stored. - - CRITICAL_REGION_ENTER(); - *p_wr_idx = m_log_data.wr_idx; - uint32_t available_words = (m_log_data.mask + 1) - - (m_log_data.wr_idx - m_log_data.rd_idx); - uint32_t tail_words = (m_log_data.mask + 1) - (m_log_data.wr_idx & m_log_data.mask); - - //available space is continuous - uint32_t curr_pos_available = (available_words <= tail_words) ? available_words : tail_words; - uint32_t start_pos_available = (available_words <= tail_words) ? 0 : (available_words - tail_words); - - if ((len32 <= curr_pos_available) || - ((len32 - PUSHED_HEADER_SIZE) <= start_pos_available)) - { - // buffer will fit in the tail or in the begining - // non zero offset is set if string is put at the beginning of the buffer - *p_offset = (len32 <= curr_pos_available) ? 0 : (tail_words - PUSHED_HEADER_SIZE); - uint32_t str_start_idx = - (m_log_data.wr_idx + PUSHED_HEADER_SIZE + *p_offset) & m_log_data.mask; - p_buf = &m_log_data.buffer[str_start_idx]; - // index is incremented by payload and offset - m_log_data.wr_idx += (len32 + *p_offset); - } - - CRITICAL_REGION_EXIT(); - - return p_buf; -} - - -uint32_t nrf_log_push(char * const p_str) -{ - if ((m_log_data.autoflush) || (p_str == NULL)) - { - return (uint32_t)p_str; - } - - uint32_t mask = m_log_data.mask; - uint32_t slen = strlen(p_str) + 1; - uint32_t buflen = CEIL_DIV(slen, sizeof(uint32_t)); - uint32_t offset = 0; - uint32_t wr_idx; - char * p_dst_str = (char *)cont_buf_prealloc(buflen, &offset, &wr_idx); - if (p_dst_str) - { - nrf_log_header_t * p_header = (nrf_log_header_t *)&m_log_data.buffer[wr_idx & mask]; - PUSHED_HEADER_FILL(p_header, offset, buflen); - memcpy(p_dst_str, p_str, slen); - } - return (uint32_t)p_dst_str; -} - -static inline void std_n(uint32_t severity_mid, char const * const p_str, uint32_t const * args, uint32_t nargs) -{ - uint32_t mask = m_log_data.mask; - uint32_t wr_idx; - - if (buf_prealloc(nargs, &wr_idx, true)) - { - // Proceed only if buffer was successfully preallocated. - - uint32_t data_idx = wr_idx + HEADER_SIZE; - uint32_t i; - for (i = 0; i < nargs; i++) - { - m_log_data.buffer[data_idx++ & mask] =args[i]; - } - std_header_set(severity_mid, p_str, nargs, wr_idx, mask); - } - if (m_log_data.autoflush) - { - NRF_LOG_FLUSH(); - } - -} - -void nrf_log_frontend_std_0(uint32_t severity_mid, char const * const p_str) -{ - std_n(severity_mid, p_str, NULL, 0); -} - - -void nrf_log_frontend_std_1(uint32_t severity_mid, - char const * const p_str, - uint32_t val0) -{ - uint32_t args[] = {val0}; - std_n(severity_mid, p_str, args, ARRAY_SIZE(args)); -} - - -void nrf_log_frontend_std_2(uint32_t severity_mid, - char const * const p_str, - uint32_t val0, - uint32_t val1) -{ - uint32_t args[] = {val0, val1}; - std_n(severity_mid, p_str, args, ARRAY_SIZE(args)); -} - - -void nrf_log_frontend_std_3(uint32_t severity_mid, - char const * const p_str, - uint32_t val0, - uint32_t val1, - uint32_t val2) -{ - uint32_t args[] = {val0, val1, val2}; - std_n(severity_mid, p_str, args, ARRAY_SIZE(args)); -} - - -void nrf_log_frontend_std_4(uint32_t severity_mid, - char const * const p_str, - uint32_t val0, - uint32_t val1, - uint32_t val2, - uint32_t val3) -{ - uint32_t args[] = {val0, val1, val2, val3}; - std_n(severity_mid, p_str, args, ARRAY_SIZE(args)); -} - - -void nrf_log_frontend_std_5(uint32_t severity_mid, - char const * const p_str, - uint32_t val0, - uint32_t val1, - uint32_t val2, - uint32_t val3, - uint32_t val4) -{ - uint32_t args[] = {val0, val1, val2, val3, val4}; - std_n(severity_mid, p_str, args, ARRAY_SIZE(args)); -} - - -void nrf_log_frontend_std_6(uint32_t severity_mid, - char const * const p_str, - uint32_t val0, - uint32_t val1, - uint32_t val2, - uint32_t val3, - uint32_t val4, - uint32_t val5) -{ - uint32_t args[] = {val0, val1, val2, val3, val4, val5}; - std_n(severity_mid, p_str, args, ARRAY_SIZE(args)); -} - - -void nrf_log_frontend_hexdump(uint32_t severity_mid, - const void * const p_data, - uint16_t length) -{ - uint32_t mask = m_log_data.mask; - - uint32_t wr_idx; - if (buf_prealloc(CEIL_DIV(length, sizeof(uint32_t)), &wr_idx, false)) - { - uint32_t header_wr_idx = wr_idx; - wr_idx += HEADER_SIZE; - - uint32_t space0 = sizeof(uint32_t) * (m_log_data.mask + 1 - (wr_idx & mask)); - if (length <= space0) - { - memcpy(&m_log_data.buffer[wr_idx & mask], p_data, length); - } - else - { - memcpy(&m_log_data.buffer[wr_idx & mask], p_data, space0); - memcpy(&m_log_data.buffer[0], &((uint8_t *)p_data)[space0], length - space0); - } - - //Prepare header - in reverse order to ensure that packet type is validated (set to HEXDUMP as last action) - if (NRF_LOG_USES_TIMESTAMP) - { - m_log_data.buffer[(header_wr_idx + 2) & mask] = m_log_data.timestamp_func(); - } - - uint32_t module_id = severity_mid >> NRF_LOG_MODULE_ID_POS; - uint32_t dropped = dropped_sat16_get(); - m_log_data.buffer[(header_wr_idx + 1) & mask] = module_id | (dropped << 16); - //Header prepare - nrf_log_header_t * p_header = (nrf_log_header_t *)&m_log_data.buffer[header_wr_idx & mask]; - p_header->base.hexdump.severity = severity_mid & NRF_LOG_LEVEL_MASK; - p_header->base.hexdump.offset = 0; - p_header->base.hexdump.len = length; - p_header->base.hexdump.type = HEADER_TYPE_HEXDUMP; - p_header->base.hexdump.in_progress = 0; - - - - } - - if (m_log_data.autoflush) - { - NRF_LOG_FLUSH(); - } -} - - -bool buffer_is_empty(void) -{ - return (m_log_data.rd_idx == m_log_data.wr_idx); -} - -bool nrf_log_frontend_dequeue(void) -{ - - if (buffer_is_empty()) - { - return false; - } - m_log_data.log_skipped = 0; - //It has to be ensured that reading rd_idx occurs after skipped flag is cleared. - __DSB(); - uint32_t rd_idx = m_log_data.rd_idx; - uint32_t mask = m_log_data.mask; - nrf_log_header_t * p_header = (nrf_log_header_t *)&m_log_data.buffer[rd_idx & mask]; - nrf_log_header_t header; - nrf_memobj_t * p_msg_buf = NULL; - uint32_t memobj_offset = 0; - uint32_t severity = 0; - - // Skip any string that is pushed to the circular buffer. - do { - if (invalid_packets_pushed_str_omit(p_header, &rd_idx)) - { - //Check if end of data is not reached. - if (rd_idx >= m_log_data.wr_idx) - { - m_log_data.rd_idx = m_log_data.wr_idx; - return false; - } - //something was omitted. Point to new header and try again. - p_header = (nrf_log_header_t *)&m_log_data.buffer[rd_idx & mask]; - } - else - { - break; - } - } while (true); - - uint32_t i; - for (i = 0; i < HEADER_SIZE; i++) - { - ((uint32_t*)&header)[i] = m_log_data.buffer[rd_idx++ & mask]; - } - - if (header.base.generic.type == HEADER_TYPE_HEXDUMP) - { - uint32_t orig_data_len = header.base.hexdump.len; - uint32_t data_len = MIN(header.base.hexdump.len, NRF_LOG_MAX_HEXDUMP); //limit the data - header.base.hexdump.len = data_len; - uint32_t msg_buf_size8 = sizeof(uint32_t)*HEADER_SIZE + data_len; - severity = header.base.hexdump.severity; - p_msg_buf = nrf_memobj_alloc(&log_mempool, msg_buf_size8); - - if (p_msg_buf) - { - nrf_memobj_get(p_msg_buf); - nrf_memobj_write(p_msg_buf, &header, HEADER_SIZE*sizeof(uint32_t), memobj_offset); - memobj_offset += HEADER_SIZE*sizeof(uint32_t); - - uint32_t space0 = sizeof(uint32_t) * (mask + 1 - (rd_idx & mask)); - if (data_len > space0) - { - uint8_t * ptr0 = space0 ? - (uint8_t *)&m_log_data.buffer[rd_idx & mask] : - (uint8_t *)&m_log_data.buffer[0]; - uint8_t len0 = space0 ? space0 : data_len; - uint8_t * ptr1 = space0 ? - (uint8_t *)&m_log_data.buffer[0] : NULL; - uint8_t len1 = space0 ? data_len - space0 : 0; - - nrf_memobj_write(p_msg_buf, ptr0, len0, memobj_offset); - memobj_offset += len0; - if (ptr1) - { - nrf_memobj_write(p_msg_buf, ptr1, len1, memobj_offset); - } - } - else - { - uint8_t * p_data = (uint8_t *)&m_log_data.buffer[rd_idx & mask]; - nrf_memobj_write(p_msg_buf, p_data, data_len, memobj_offset); - } - rd_idx += CEIL_DIV(orig_data_len, 4); - } - } - else if (header.base.generic.type == HEADER_TYPE_STD) // standard entry - { - header.base.std.nargs = MIN(header.base.std.nargs, NRF_LOG_MAX_NUM_OF_ARGS); - uint32_t msg_buf_size32 = HEADER_SIZE + header.base.std.nargs; - severity = header.base.std.severity; - - p_msg_buf = nrf_memobj_alloc(&log_mempool, msg_buf_size32*sizeof(uint32_t)); - - if (p_msg_buf) - { - nrf_memobj_get(p_msg_buf); - nrf_memobj_write(p_msg_buf, &header, HEADER_SIZE*sizeof(uint32_t), memobj_offset); - memobj_offset += HEADER_SIZE*sizeof(uint32_t); - - for (i = 0; i < header.base.std.nargs; i++) - { - nrf_memobj_write(p_msg_buf, &m_log_data.buffer[rd_idx++ & mask], - sizeof(uint32_t), memobj_offset); - memobj_offset += sizeof(uint32_t); - } - } - } - else - { - //Do nothing. In case of log overflow buffer can contain corrupted data. - } - - if (p_msg_buf) - { - nrf_log_backend_t * p_backend = m_log_data.p_backend_head; - if (NRF_LOG_ALLOW_OVERFLOW && m_log_data.log_skipped) - { - // Check if any log was skipped during log processing. Do not forward log if skipping - // occured because data may be invalid. - nrf_memobj_put(p_msg_buf); - } - else - { - while (p_backend) - { - bool entry_accepted = false; - if (nrf_log_backend_is_enabled(p_backend) == true) - { - if (NRF_LOG_FILTERS_ENABLED) - { - uint8_t backend_id = nrf_log_backend_id_get(p_backend); - nrf_log_module_dynamic_data_t * p_module_filter = - (nrf_log_module_dynamic_data_t *)NRF_LOG_DYNAMIC_SECTION_VARS_GET(header.module_id); - uint32_t filter_lvls = p_module_filter->filter_lvls; - uint32_t backend_lvl = (filter_lvls >> (backend_id*NRF_LOG_LEVEL_BITS)) - & NRF_LOG_LEVEL_MASK; - //Degrade INFO_RAW level to INFO. - severity = (severity == NRF_LOG_SEVERITY_INFO_RAW) ? NRF_LOG_SEVERITY_INFO : severity; - if (backend_lvl >= severity) - { - entry_accepted = true; - } - } - else - { - (void)severity; - entry_accepted = true; - } - } - if (entry_accepted) - { - nrf_log_backend_put(p_backend, p_msg_buf); - } - p_backend = p_backend->p_next; - } - - nrf_memobj_put(p_msg_buf); - - if (NRF_LOG_ALLOW_OVERFLOW) - { - // Read index can be moved forward only if dequeueing process was not interrupt by - // skipping procedure. If NRF_LOG_ALLOW_OVERFLOW is set then in case of buffer gets full - // and new logger entry occurs, oldest entry is removed. In that case read index is - // changed and updating it here would corrupt the internal circular buffer. - CRITICAL_REGION_ENTER(); - if (m_log_data.log_skipped == 0) - { - m_log_data.rd_idx = rd_idx; - } - CRITICAL_REGION_EXIT(); - } - else - { - m_log_data.rd_idx = rd_idx; - } - } - } - else - { - //Could not allocate memobj - backends are not freeing them on time. - nrf_log_backend_t * p_backend = m_log_data.p_backend_head; - //Flush all backends - while (p_backend) - { - nrf_log_backend_flush(p_backend); - p_backend = p_backend->p_next; - } - NRF_LOG_WARNING("Backends flushed"); - } - - return buffer_is_empty() ? false : true; -} - -static int32_t backend_id_assign(void) -{ - int32_t candidate_id; - nrf_log_backend_t * p_backend; - bool id_available; - for (candidate_id = 0; candidate_id < NRF_LOG_MAX_BACKENDS; candidate_id++) - { - p_backend = m_log_data.p_backend_head; - id_available = true; - while (p_backend) - { - if (nrf_log_backend_id_get(p_backend) == candidate_id) - { - id_available = false; - break; - } - p_backend = p_backend->p_next; - } - if (id_available) - { - return candidate_id; - } - } - return -1; -} - -int32_t nrf_log_backend_add(nrf_log_backend_t * p_backend, nrf_log_severity_t severity) -{ - int32_t id = backend_id_assign(); - if (id == -1) - { - return id; - } - - nrf_log_backend_id_set(p_backend, id); - //add to list - if (m_log_data.p_backend_head == NULL) - { - m_log_data.p_backend_head = p_backend; - p_backend->p_next = NULL; - } - else - { - p_backend->p_next = m_log_data.p_backend_head->p_next; - m_log_data.p_backend_head->p_next = p_backend; - } - - if (NRF_LOG_FILTERS_ENABLED) - { - uint32_t i; - for (i = 0; i < nrf_log_module_cnt_get(); i++) - { - nrf_log_severity_t buildin_lvl = nrf_log_module_init_filter_get(i); - nrf_log_severity_t actual_severity = MIN(buildin_lvl, severity); - nrf_log_module_filter_set(nrf_log_backend_id_get(p_backend), i, actual_severity); - } - } - - return id; -} - -void nrf_log_backend_remove(nrf_log_backend_t * p_backend) -{ - nrf_log_backend_t * p_curr = m_log_data.p_backend_head; - nrf_log_backend_t * p_prev = NULL; - while (p_curr != p_backend) - { - p_prev = p_curr; - p_curr = p_curr->p_next; - } - - if (p_prev) - { - p_prev->p_next = p_backend->p_next; - } - else - { - m_log_data.p_backend_head = NULL; - } -} - -void nrf_log_panic(void) -{ - nrf_log_backend_t * p_backend = m_log_data.p_backend_head; - m_log_data.autoflush = true; - while (p_backend) - { - nrf_log_backend_enable(p_backend); - nrf_log_backend_panic_set(p_backend); - p_backend = p_backend->p_next; - } -} - -#if NRF_LOG_CLI_CMDS -#include "nrf_cli.h" - -static const char * m_severity_lvls[] = { - "none", - "error", - "warning", - "info", - "debug", -}; - -static const char * m_severity_lvls_sorted[] = { - "debug", - "error", - "info", - "none", - "warning", -}; - -static void log_status(nrf_cli_t const * p_cli, size_t argc, char **argv) -{ - uint32_t modules_cnt = nrf_log_module_cnt_get(); - uint32_t backend_id = p_cli->p_log_backend->backend.id; - uint32_t i; - - if (!nrf_log_backend_is_enabled(&p_cli->p_log_backend->backend)) - { - nrf_cli_fprintf(p_cli, NRF_CLI_ERROR, "Logs are halted!\r\n"); - } - nrf_cli_fprintf(p_cli, NRF_CLI_NORMAL, "%-40s | current | built-in \r\n", "module_name"); - nrf_cli_fprintf(p_cli, NRF_CLI_NORMAL, "----------------------------------------------------------\r\n"); - for (i = 0; i < modules_cnt; i++) - { - nrf_log_severity_t module_dynamic_lvl = nrf_log_module_filter_get(backend_id, i, true, true); - nrf_log_severity_t module_compiled_lvl = nrf_log_module_filter_get(backend_id, i, true, false); - nrf_log_severity_t actual_compiled_lvl = MIN(module_compiled_lvl, (nrf_log_severity_t)NRF_LOG_DEFAULT_LEVEL); - nrf_cli_fprintf(p_cli, NRF_CLI_NORMAL, "%-40s | %-7s | %s%s\r\n", - nrf_log_module_name_get(i, true), - m_severity_lvls[module_dynamic_lvl], - m_severity_lvls[actual_compiled_lvl], - actual_compiled_lvl < module_compiled_lvl ? "*" : ""); - } -} - -static bool module_id_get(const char * p_name, uint32_t * p_id) -{ - uint32_t modules_cnt = nrf_log_module_cnt_get(); - const char * p_tmp_name; - uint32_t j; - for (j = 0; j < modules_cnt; j++) - { - p_tmp_name = nrf_log_module_name_get(j, false); - if (strncmp(p_tmp_name, p_name, 32) == 0) - { - *p_id = j; - break; - } - } - return (j != modules_cnt); -} - -static bool module_id_filter_set(uint32_t backend_id, - uint32_t module_id, - nrf_log_severity_t lvl) -{ - nrf_log_severity_t buildin_lvl = nrf_log_module_filter_get(backend_id, module_id, false, false); - if (lvl > buildin_lvl) - { - return false; - } - else - { - nrf_log_module_filter_set(backend_id, module_id, lvl); - return true; - } -} - -static void log_ctrl(nrf_cli_t const * p_cli, size_t argc, char **argv) -{ - uint32_t backend_id = p_cli->p_log_backend->backend.id; - nrf_log_severity_t lvl; - uint32_t first_m_name_idx; - uint32_t i; - bool all_modules = false; - - if (argc > 0) - { - if (strncmp(argv[0], "enable", 7) == 0) - { - if (argc == 1) - { - nrf_cli_fprintf(p_cli, NRF_CLI_ERROR, "Bad parameter count.\r\n"); - return; - } - - if (argc == 2) - { - all_modules = true; - } - - for (i = 0; i < ARRAY_SIZE(m_severity_lvls); i++) - { - if (strncmp(argv[1], m_severity_lvls[i], 10) == 0) - { - break; - } - } - - if (i == ARRAY_SIZE(m_severity_lvls)) - { - nrf_cli_fprintf(p_cli, NRF_CLI_ERROR, "Unknown severity level: %s\r\n", argv[1]); - return; - } - - lvl = (nrf_log_severity_t)i; - first_m_name_idx = 2; - - } - else if (strncmp(argv[0], "disable", 8) == 0) - { - if (argc == 1) - { - all_modules = true; - } - lvl = NRF_LOG_SEVERITY_NONE; - first_m_name_idx = 1; - } - else - { - nrf_cli_fprintf(p_cli, NRF_CLI_ERROR, "Unknown option: %s\r\n", argv[0]); - return; - } - - if (all_modules) - { - for (i = 0; i < nrf_log_module_cnt_get(); i++) - { - if (module_id_filter_set(backend_id, i, lvl) == false) - { - nrf_cli_fprintf(p_cli, NRF_CLI_ERROR, "Level unavailable for module: %s\r\n", nrf_log_module_name_get(i, false)); - } - } - } - else - { - for (i = first_m_name_idx; i < argc; i++) - { - uint32_t module_id = 0; - if (module_id_get(argv[i], &module_id) == false) - { - nrf_cli_fprintf(p_cli, NRF_CLI_ERROR, "Unknown module:%s\r\n", argv[i]); - } - - if (module_id_filter_set(backend_id, module_id, lvl) == false) - { - nrf_cli_fprintf(p_cli, NRF_CLI_ERROR, "Level unavailable for module: %s\r\n", nrf_log_module_name_get(module_id, false)); - } - } - } - } -} -static void module_name_get(size_t idx, nrf_cli_static_entry_t * p_static); - -NRF_CLI_CREATE_DYNAMIC_CMD(m_module_name, module_name_get); - -static void module_name_get(size_t idx, nrf_cli_static_entry_t * p_static) -{ - p_static->handler = NULL; - p_static->p_help = NULL; - p_static->p_subcmd = &m_module_name; - p_static->p_syntax = nrf_log_module_name_get(idx, true); -} - -static void severity_lvl_get(size_t idx, nrf_cli_static_entry_t * p_static) -{ - p_static->handler = NULL; - p_static->p_help = NULL; - p_static->p_subcmd = &m_module_name; - p_static->p_syntax = (idx < ARRAY_SIZE(m_severity_lvls_sorted)) ? - m_severity_lvls_sorted[idx] : NULL; -} - -NRF_CLI_CREATE_DYNAMIC_CMD(m_severity_lvl, severity_lvl_get); - -static void log_halt(nrf_cli_t const * p_cli, size_t argc, char **argv) -{ - nrf_log_backend_disable(&p_cli->p_log_backend->backend); -} - -static void log_go(nrf_cli_t const * p_cli, size_t argc, char **argv) -{ - nrf_log_backend_enable(&p_cli->p_log_backend->backend); -} - -NRF_CLI_CREATE_STATIC_SUBCMD_SET(m_sub_log_stat) -{ - NRF_CLI_CMD(disable, &m_module_name, - "'log disable .. ' disables logs in specified " - "modules (all if no modules specified).", - log_ctrl), - NRF_CLI_CMD(enable, &m_severity_lvl, - "'log enable ... ' enables logs up to given level in " - "specified modules (all if no modules specified).", - log_ctrl), - NRF_CLI_CMD(go, NULL, "Resume logging", log_go), - NRF_CLI_CMD(halt, NULL, "Halt logging", log_halt), - NRF_CLI_CMD(status, NULL, "Logger status", log_status), - NRF_CLI_SUBCMD_SET_END -}; - -static void log_cmd(nrf_cli_t const * p_cli, size_t argc, char **argv) -{ - if ((argc == 1) || nrf_cli_help_requested(p_cli)) - { - nrf_cli_help_print(p_cli, NULL, 0); - return; - } - - nrf_cli_fprintf(p_cli, NRF_CLI_ERROR, "%s:%s%s\r\n", argv[0], " unknown parameter: ", argv[1]); -} - -NRF_CLI_CMD_REGISTER(log, &m_sub_log_stat, "Commands for controlling logger", log_cmd); - -#endif //NRF_LOG_CLI_CMDS - -#endif // NRF_MODULE_ENABLED(NRF_LOG) diff --git a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_internal.h b/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_internal.h deleted file mode 100644 index babc14c3d1..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_internal.h +++ /dev/null @@ -1,529 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef NRF_LOG_INTERNAL_H__ -#define NRF_LOG_INTERNAL_H__ -#include "sdk_common.h" -#include "nrf.h" -#include "nrf_error.h" -#include "app_util.h" -#include -#include -#include "nrf_log_instance.h" -#include "nrf_log_types.h" - -#ifndef NRF_LOG_ERROR_COLOR - #define NRF_LOG_ERROR_COLOR NRF_LOG_COLOR_DEFAULT -#endif - -#ifndef NRF_LOG_WARNING_COLOR - #define NRF_LOG_WARNING_COLOR NRF_LOG_COLOR_DEFAULT -#endif - -#ifndef NRF_LOG_INFO_COLOR - #define NRF_LOG_INFO_COLOR NRF_LOG_COLOR_DEFAULT -#endif - -#ifndef NRF_LOG_DEBUG_COLOR - #define NRF_LOG_DEBUG_COLOR NRF_LOG_COLOR_DEFAULT -#endif - - -#ifndef NRF_LOG_COLOR_DEFAULT -#define NRF_LOG_COLOR_DEFAULT 0 -#endif - -#ifndef NRF_LOG_DEFAULT_LEVEL -#define NRF_LOG_DEFAULT_LEVEL 0 -#endif - -#ifndef NRF_LOG_USES_COLORS -#define NRF_LOG_USES_COLORS 0 -#endif - -#ifndef NRF_LOG_USES_TIMESTAMP -#define NRF_LOG_USES_TIMESTAMP 0 -#endif - -#ifndef NRF_LOG_FILTERS_ENABLED -#define NRF_LOG_FILTERS_ENABLED 0 -#endif - -#ifndef NRF_LOG_MODULE_NAME - #define NRF_LOG_MODULE_NAME app -#endif - -#define NRF_LOG_LEVEL_BITS 3 -#define NRF_LOG_LEVEL_MASK ((1UL << NRF_LOG_LEVEL_BITS) - 1) -#define NRF_LOG_MODULE_ID_BITS 16 -#define NRF_LOG_MODULE_ID_POS 16 - - -#define NRF_LOG_MAX_NUM_OF_ARGS 6 - - -#if NRF_LOG_FILTERS_ENABLED && NRF_LOG_ENABLED - #define NRF_LOG_FILTER NRF_LOG_ITEM_DATA_DYNAMIC(NRF_LOG_MODULE_NAME).filter - #define NRF_LOG_INST_FILTER(p_inst) (p_inst)->filter -#else - #undef NRF_LOG_FILTER - #define NRF_LOG_FILTER NRF_LOG_SEVERITY_DEBUG - #define NRF_LOG_INST_FILTER(p_inst) NRF_LOG_SEVERITY_DEBUG -#endif - -#if NRF_LOG_ENABLED -#define NRF_LOG_MODULE_ID NRF_LOG_ITEM_DATA_DYNAMIC(NRF_LOG_MODULE_NAME).module_id -#define NRF_LOG_INST_ID(p_inst) (p_inst)->module_id -#else -#define NRF_LOG_MODULE_ID 0 -#define NRF_LOG_INST_ID(p_inst) 0 -#endif - - -#define LOG_INTERNAL_X(N, ...) CONCAT_2(LOG_INTERNAL_, N) (__VA_ARGS__) -#define LOG_INTERNAL(type, ...) LOG_INTERNAL_X(NUM_VA_ARGS_LESS_1( \ - __VA_ARGS__), type, __VA_ARGS__) -#if NRF_LOG_ENABLED -#define NRF_LOG_INTERNAL_LOG_PUSH(_str) nrf_log_push(_str) -#define LOG_INTERNAL_0(type, str) \ - nrf_log_frontend_std_0(type, str) -#define LOG_INTERNAL_1(type, str, arg0) \ - /*lint -save -e571*/nrf_log_frontend_std_1(type, str, (uint32_t)(arg0))/*lint -restore*/ -#define LOG_INTERNAL_2(type, str, arg0, arg1) \ - /*lint -save -e571*/nrf_log_frontend_std_2(type, str, (uint32_t)(arg0), \ - (uint32_t)(arg1))/*lint -restore*/ -#define LOG_INTERNAL_3(type, str, arg0, arg1, arg2) \ - /*lint -save -e571*/nrf_log_frontend_std_3(type, str, (uint32_t)(arg0), \ - (uint32_t)(arg1), (uint32_t)(arg2))/*lint -restore*/ -#define LOG_INTERNAL_4(type, str, arg0, arg1, arg2, arg3) \ - /*lint -save -e571*/nrf_log_frontend_std_4(type, str, (uint32_t)(arg0), \ - (uint32_t)(arg1), (uint32_t)(arg2), (uint32_t)(arg3))/*lint -restore*/ -#define LOG_INTERNAL_5(type, str, arg0, arg1, arg2, arg3, arg4) \ - /*lint -save -e571*/nrf_log_frontend_std_5(type, str, (uint32_t)(arg0), \ - (uint32_t)(arg1), (uint32_t)(arg2), (uint32_t)(arg3), (uint32_t)(arg4))/*lint -restore*/ -#define LOG_INTERNAL_6(type, str, arg0, arg1, arg2, arg3, arg4, arg5) \ - /*lint -save -e571*/nrf_log_frontend_std_6(type, str, (uint32_t)(arg0), \ - (uint32_t)(arg1), (uint32_t)(arg2), (uint32_t)(arg3), (uint32_t)(arg4), (uint32_t)(arg5))/*lint -restore*/ - - -#else //NRF_LOG_ENABLED -#define NRF_LOG_INTERNAL_LOG_PUSH(_str) (void)(_str) -#define LOG_INTERNAL_0(_type, _str) \ - (void)(_type); (void)(_str) -#define LOG_INTERNAL_1(_type, _str, _arg0) \ - (void)(_type); (void)(_str); (void)(_arg0) -#define LOG_INTERNAL_2(_type, _str, _arg0, _arg1) \ - (void)(_type); (void)(_str); (void)(_arg0); (void)(_arg1) -#define LOG_INTERNAL_3(_type, _str, _arg0, _arg1, _arg2) \ - (void)(_type); (void)(_str); (void)(_arg0); (void)(_arg1); (void)(_arg2) -#define LOG_INTERNAL_4(_type, _str, _arg0, _arg1, _arg2, _arg3) \ - (void)(_type); (void)(_str); (void)(_arg0); (void)(_arg1); (void)(_arg2); (void)(_arg3) -#define LOG_INTERNAL_5(_type, _str, _arg0, _arg1, _arg2, _arg3, _arg4) \ - (void)(_type); (void)(_str); (void)(_arg0); (void)(_arg1); (void)(_arg2); (void)(_arg3); (void)(_arg4) -#define LOG_INTERNAL_6(_type, _str, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5) \ - (void)(_type); (void)(_str); (void)(_arg0); (void)(_arg1); (void)(_arg2); (void)(_arg3); (void)(_arg4); (void)(_arg5) -#endif //NRF_LOG_ENABLED - -#define LOG_SEVERITY_MOD_ID(severity) ((severity) | NRF_LOG_MODULE_ID << NRF_LOG_MODULE_ID_POS) -#define LOG_SEVERITY_INST_ID(severity,p_inst) ((severity) | NRF_LOG_INST_ID(p_inst) << NRF_LOG_MODULE_ID_POS) - -#if NRF_LOG_ENABLED -#define LOG_HEXDUMP(_severity, _p_data, _length) \ - nrf_log_frontend_hexdump((_severity), (_p_data), (_length)) -#else -#define LOG_HEXDUMP(_severity, _p_data, _length) \ - (void)(_severity); (void)(_p_data); (void)_length -#endif - -#define NRF_LOG_INTERNAL_INST(level, level_id, p_inst, ...) \ - if (NRF_LOG_ENABLED && (NRF_LOG_LEVEL >= level) && \ - (level <= NRF_LOG_DEFAULT_LEVEL)) \ - { \ - if (NRF_LOG_INST_FILTER(p_inst) >= level) \ - { \ - LOG_INTERNAL(LOG_SEVERITY_INST_ID(level_id, p_inst), __VA_ARGS__); \ - } \ - } - -#define NRF_LOG_INTERNAL_MODULE(level, level_id, ...) \ - if (NRF_LOG_ENABLED && (NRF_LOG_LEVEL >= level) && \ - (level <= NRF_LOG_DEFAULT_LEVEL)) \ - { \ - if (NRF_LOG_FILTER >= level) \ - { \ - LOG_INTERNAL(LOG_SEVERITY_MOD_ID(level_id), __VA_ARGS__); \ - } \ - } - -#define NRF_LOG_INTERNAL_HEXDUMP_INST(level, level_id, p_inst, p_data, len) \ - if (NRF_LOG_ENABLED && (NRF_LOG_LEVEL >= level) && \ - (level <= NRF_LOG_DEFAULT_LEVEL)) \ - { \ - if (NRF_LOG_INST_FILTER(p_inst) >= level) \ - { \ - LOG_HEXDUMP(LOG_SEVERITY_INST_ID(level_id, p_inst), \ - (p_data), (len)); \ - } \ - } - -#define NRF_LOG_INTERNAL_HEXDUMP_MODULE(level, level_id, p_data, len) \ - if (NRF_LOG_ENABLED && (NRF_LOG_LEVEL >= level) && \ - (level <= NRF_LOG_DEFAULT_LEVEL)) \ - { \ - if (NRF_LOG_FILTER >= level) \ - { \ - LOG_HEXDUMP(LOG_SEVERITY_MOD_ID(level_id), \ - (p_data), (len)); \ - } \ - } - -#define NRF_LOG_INTERNAL_INST_ERROR(p_inst, ...) \ - NRF_LOG_INTERNAL_INST(NRF_LOG_SEVERITY_ERROR, NRF_LOG_SEVERITY_ERROR, p_inst, __VA_ARGS__) - -#define NRF_LOG_INTERNAL_ERROR(...) \ - NRF_LOG_INTERNAL_MODULE(NRF_LOG_SEVERITY_ERROR, NRF_LOG_SEVERITY_ERROR,__VA_ARGS__) - -#define NRF_LOG_INTERNAL_HEXDUMP_INST_ERROR(p_inst, p_data, len) \ - NRF_LOG_INTERNAL_HEXDUMP_INST(NRF_LOG_SEVERITY_ERROR, NRF_LOG_SEVERITY_ERROR, p_inst, p_data, len) - -#define NRF_LOG_INTERNAL_HEXDUMP_ERROR(p_data, len) \ - NRF_LOG_INTERNAL_HEXDUMP_MODULE(NRF_LOG_SEVERITY_ERROR, NRF_LOG_SEVERITY_ERROR, p_data, len) - -#define NRF_LOG_INTERNAL_INST_WARNING(p_inst, ...) \ - NRF_LOG_INTERNAL_INST(NRF_LOG_SEVERITY_WARNING, NRF_LOG_SEVERITY_WARNING, p_inst, __VA_ARGS__) - -#define NRF_LOG_INTERNAL_WARNING(...) \ - NRF_LOG_INTERNAL_MODULE(NRF_LOG_SEVERITY_WARNING, NRF_LOG_SEVERITY_WARNING,__VA_ARGS__) - -#define NRF_LOG_INTERNAL_HEXDUMP_INST_WARNING(p_inst, p_data, len) \ - NRF_LOG_INTERNAL_HEXDUMP_INST(NRF_LOG_SEVERITY_WARNING, NRF_LOG_SEVERITY_WARNING, p_inst, p_data, len) - -#define NRF_LOG_INTERNAL_HEXDUMP_WARNING(p_data, len) \ - NRF_LOG_INTERNAL_HEXDUMP_(NRF_LOG_SEVERITY_WARNING, NRF_LOG_SEVERITY_WARNING, p_data, len) - -#define NRF_LOG_INTERNAL_INST_INFO(p_inst, ...) \ - NRF_LOG_INTERNAL_INST(NRF_LOG_SEVERITY_INFO, NRF_LOG_SEVERITY_INFO, p_inst, __VA_ARGS__) - -#define NRF_LOG_INTERNAL_INFO(...) \ - NRF_LOG_INTERNAL_MODULE(NRF_LOG_SEVERITY_INFO, NRF_LOG_SEVERITY_INFO, __VA_ARGS__) - -#define NRF_LOG_INTERNAL_HEXDUMP_INST_INFO(p_inst, p_data, len) \ - NRF_LOG_INTERNAL_HEXDUMP_INST(NRF_LOG_SEVERITY_INFO, NRF_LOG_SEVERITY_INFO, p_inst, p_data, len) - -#define NRF_LOG_INTERNAL_HEXDUMP_INFO(p_data, len) \ - NRF_LOG_INTERNAL_HEXDUMP_MODULE(NRF_LOG_SEVERITY_INFO, NRF_LOG_SEVERITY_INFO, p_data, len) - -#define NRF_LOG_INTERNAL_RAW_INFO(...) \ - NRF_LOG_INTERNAL_MODULE(NRF_LOG_SEVERITY_INFO, NRF_LOG_SEVERITY_INFO_RAW, __VA_ARGS__) - -#define NRF_LOG_INTERNAL_RAW_HEXDUMP_INFO(p_data, len) \ - NRF_LOG_INTERNAL_HEXDUMP_MODULE(NRF_LOG_SEVERITY_INFO, NRF_LOG_SEVERITY_INFO_RAW, p_data, len) - -#define NRF_LOG_INTERNAL_INST_DEBUG(p_inst, ...) \ - NRF_LOG_INTERNAL_INST(NRF_LOG_SEVERITY_DEBUG, NRF_LOG_SEVERITY_DEBUG, p_inst, __VA_ARGS__) - -#define NRF_LOG_INTERNAL_DEBUG(...) \ - NRF_LOG_INTERNAL_MODULE(NRF_LOG_SEVERITY_DEBUG, NRF_LOG_SEVERITY_DEBUG, __VA_ARGS__) - -#define NRF_LOG_INTERNAL_HEXDUMP_INST_DEBUG(p_inst, p_data, len) \ - NRF_LOG_INTERNAL_HEXDUMP_INST(NRF_LOG_SEVERITY_DEBUG, NRF_LOG_SEVERITY_DEBUG, p_inst, p_data, len) - -#define NRF_LOG_INTERNAL_HEXDUMP_DEBUG(p_data, len) \ - NRF_LOG_INTERNAL_HEXDUMP_MODULE(NRF_LOG_SEVERITY_DEBUG, NRF_LOG_SEVERITY_DEBUG, p_data, len) - - -#if NRF_LOG_ENABLED - -#ifdef UNIT_TEST -#define COMPILED_LOG_LEVEL 4 -#else -#define COMPILED_LOG_LEVEL NRF_LOG_LEVEL -#endif - - -#define NRF_LOG_INTERNAL_MODULE_REGISTER() \ - NRF_LOG_INTERNAL_ITEM_REGISTER(NRF_LOG_MODULE_NAME, \ - STRINGIFY(NRF_LOG_MODULE_NAME), \ - NRF_LOG_INFO_COLOR, \ - NRF_LOG_DEBUG_COLOR, \ - NRF_LOG_INITIAL_LEVEL, \ - COMPILED_LOG_LEVEL) - -#else -#define NRF_LOG_INTERNAL_MODULE_REGISTER() /*lint -save -e19*/ /*lint -restore*/ -#endif - -extern NRF_LOG_DYNAMIC_STRUCT_NAME NRF_LOG_ITEM_DATA_DYNAMIC(NRF_LOG_MODULE_NAME); - -/** - * Set of macros for encoding and decoding header for log entries. - * There are 3 types of entries: - * 1. Standard entry (STD) - * An entry consists of header, pointer to string and values. Header contains - * severity leveland determines number of arguments and thus size of the entry. - * Since flash address space starts from 0x00000000 and is limited to kB rather - * than MB 22 bits are used to store the address (4MB). It is used that way to - * save one RAM memory. - * - * -------------------------------- - * |TYPE|SEVERITY|NARGS| P_STR | - * |------------------------------| - * | Module_ID (optional) | - * |------------------------------| - * | TIMESTAMP (optional) | - * |------------------------------| - * | ARG0 | - * |------------------------------| - * | .... | - * |------------------------------| - * | ARG(nargs-1) | - * -------------------------------- - * - * 2. Hexdump entry (HEXDUMP) is used for dumping raw data. An entry consists of - * header, optional timestamp, pointer to string and data. A header contains - * length (10bit) and offset which is updated after backend processes part of - * data. - * - * -------------------------------- - * |TYPE|SEVERITY|NARGS|OFFSET|LEN| - * |------------------------------| - * | Module_ID (optional) | - * |------------------------------| - * | TIMESTAMP (optional) | - * |------------------------------| - * | P_STR | - * |------------------------------| - * | data | - * |------------------------------| - * | data | dummy | - * -------------------------------- - * - * 3. Pushed string. If string is pushed into the logger internal buffer it is - * stored as PUSHED entry. It consists of header, unused data (optional) and - * string. Unused data is present if string does not not fit into a buffer - * without wrapping (and string cannot be wrapped). In that case header - * contains information about offset. - * - * -------------------------------- - * |TYPE| OFFSET | LEN | - * |------------------------------| - * | OFFSET | - * |------------------------------| - * end| OFFSET | - * 0|------------------------------| - * | STRING | - * |------------------------------| - * | STRING | dummy | - * -------------------------------- - */ - -#define STD_ADDR_MASK ((uint32_t)(1U << 22) - 1U) -#define HEADER_TYPE_STD 1U -#define HEADER_TYPE_HEXDUMP 2U -#define HEADER_TYPE_PUSHED 0U -#define HEADER_TYPE_INVALID 3U - -typedef struct -{ - uint32_t type : 2; - uint32_t in_progress: 1; - uint32_t data : 29; -} nrf_log_generic_header_t; - -typedef struct -{ - uint32_t type : 2; - uint32_t in_progress: 1; - uint32_t severity : 3; - uint32_t nargs : 4; - uint32_t addr : 22; -} nrf_log_std_header_t; - -typedef struct -{ - uint32_t type : 2; - uint32_t in_progress: 1; - uint32_t severity : 3; - uint32_t offset : 10; - uint32_t reserved : 6; - uint32_t len : 10; -} nrf_log_hexdump_header_t; - -typedef struct -{ - uint32_t type : 2; - uint32_t reserved0 : 4; - uint32_t offset : 10; - uint32_t reserved1 : 6; - uint32_t len : 10; -} nrf_log_pushed_header_t; - -typedef union -{ - nrf_log_generic_header_t generic; - nrf_log_std_header_t std; - nrf_log_hexdump_header_t hexdump; - nrf_log_pushed_header_t pushed; - uint32_t raw; -} nrf_log_main_header_t; - -typedef struct -{ - nrf_log_main_header_t base; - uint16_t module_id; - uint16_t dropped; - uint32_t timestamp; -} nrf_log_header_t; - -#define HEADER_SIZE (sizeof(nrf_log_header_t)/sizeof(uint32_t) - \ - (NRF_LOG_USES_TIMESTAMP ? 0 : 1)) - -#define PUSHED_HEADER_SIZE (sizeof(nrf_log_pushed_header_t)/sizeof(uint32_t)) - -//Implementation assumes that pushed header has one word. -STATIC_ASSERT(PUSHED_HEADER_SIZE == 1); -/** - * @brief A function for logging raw string. - * - * @param severity_mid Severity. - * @param p_str A pointer to a string. - */ -void nrf_log_frontend_std_0(uint32_t severity_mid, char const * const p_str); - -/** - * @brief A function for logging a formatted string with one argument. - * - * @param severity_mid Severity. - * @param p_str A pointer to a formatted string. - * @param val0 An argument. - */ -void nrf_log_frontend_std_1(uint32_t severity_mid, - char const * const p_str, - uint32_t val0); - -/** - * @brief A function for logging a formatted string with 2 arguments. - * - * @param severity_mid Severity. - * @param p_str A pointer to a formatted string. - * @param val0, val1 Arguments for formatting string. - */ -void nrf_log_frontend_std_2(uint32_t severity_mid, - char const * const p_str, - uint32_t val0, - uint32_t val1); - -/** - * @brief A function for logging a formatted string with 3 arguments. - * - * @param severity_mid Severity. - * @param p_str A pointer to a formatted string. - * @param val0, val1, val2 Arguments for formatting string. - */ -void nrf_log_frontend_std_3(uint32_t severity_mid, - char const * const p_str, - uint32_t val0, - uint32_t val1, - uint32_t val2); - -/** - * @brief A function for logging a formatted string with 4 arguments. - * - * @param severity_mid Severity. - * @param p_str A pointer to a formatted string. - * @param val0, val1, val2, val3 Arguments for formatting string. - */ -void nrf_log_frontend_std_4(uint32_t severity_mid, - char const * const p_str, - uint32_t val0, - uint32_t val1, - uint32_t val2, - uint32_t val3); - -/** - * @brief A function for logging a formatted string with 5 arguments. - * - * @param severity_mid Severity. - * @param p_str A pointer to a formatted string. - * @param val0, val1, val2, val3, val4 Arguments for formatting string. - */ -void nrf_log_frontend_std_5(uint32_t severity_mid, - char const * const p_str, - uint32_t val0, - uint32_t val1, - uint32_t val2, - uint32_t val3, - uint32_t val4); - -/** - * @brief A function for logging a formatted string with 6 arguments. - * - * @param severity_mid Severity. - * @param p_str A pointer to a formatted string. - * @param val0, val1, val2, val3, val4, val5 Arguments for formatting string. - */ -void nrf_log_frontend_std_6(uint32_t severity_mid, - char const * const p_str, - uint32_t val0, - uint32_t val1, - uint32_t val2, - uint32_t val3, - uint32_t val4, - uint32_t val5); - -/** - * @brief A function for logging raw data. - * - * @param severity_mid Severity. - * @param p_str A pointer to a string which is prefixing the data. - * @param p_data A pointer to data to be dumped. - * @param length Length of data (in bytes). - * - */ -void nrf_log_frontend_hexdump(uint32_t severity_mid, - const void * const p_data, - uint16_t length); - -/** - * @brief A function for reading a byte from log backend. - * - * @return Byte. - */ -uint8_t nrf_log_getchar(void); -#endif // NRF_LOG_INTERNAL_H__ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_str_formatter.c b/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_str_formatter.c deleted file mode 100644 index 36f8039e54..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/experimental_log/src/nrf_log_str_formatter.c +++ /dev/null @@ -1,256 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include "sdk_common.h" -#if NRF_MODULE_ENABLED(NRF_LOG) -#include "nrf_log_str_formatter.h" -#include "nrf_log_internal.h" -#include "nrf_log_ctrl.h" -#include "nrf_fprintf.h" -#include - -#define NRF_LOG_COLOR_CODE_DEFAULT "\x1B[0m" -#define NRF_LOG_COLOR_CODE_BLACK "\x1B[1;30m" -#define NRF_LOG_COLOR_CODE_RED "\x1B[1;31m" -#define NRF_LOG_COLOR_CODE_GREEN "\x1B[1;32m" -#define NRF_LOG_COLOR_CODE_YELLOW "\x1B[1;33m" -#define NRF_LOG_COLOR_CODE_BLUE "\x1B[1;34m" -#define NRF_LOG_COLOR_CODE_MAGENTA "\x1B[1;35m" -#define NRF_LOG_COLOR_CODE_CYAN "\x1B[1;36m" -#define NRF_LOG_COLOR_CODE_WHITE "\x1B[1;37m" - -static const char * severity_names[] = { - NULL, - "error", - "warning", - "info", - "debug" -}; - -static const char * m_colors[] = { - NRF_LOG_COLOR_CODE_DEFAULT, - NRF_LOG_COLOR_CODE_BLACK, - NRF_LOG_COLOR_CODE_RED, - NRF_LOG_COLOR_CODE_GREEN, - NRF_LOG_COLOR_CODE_YELLOW, - NRF_LOG_COLOR_CODE_BLUE, - NRF_LOG_COLOR_CODE_MAGENTA, - NRF_LOG_COLOR_CODE_CYAN, - NRF_LOG_COLOR_CODE_WHITE, -}; - -static uint32_t m_freq; -static uint32_t m_timestamp_div; - -static void timestamp_print(nrf_fprintf_ctx_t * p_ctx, uint32_t timestamp) -{ - if (NRF_LOG_USES_TIMESTAMP) - { - if (NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED) - { - timestamp /= m_timestamp_div; - uint32_t seconds = timestamp/m_freq; - uint32_t hours = seconds/3600; - seconds -= hours * 3600; - uint32_t mins = seconds/60; - seconds -= mins * 60; - - uint32_t reminder = timestamp % m_freq; - uint32_t ms = (reminder * 1000)/m_freq; - uint32_t us = (1000*(1000*reminder - (ms * m_freq)))/m_freq; - - nrf_fprintf(p_ctx, "[%02d:%02d:%02d.%03d,%03d] ", hours, mins, seconds, ms, us); - } - else - { - nrf_fprintf(p_ctx, "[%08lu] ", timestamp); - } - } -} -static void prefix_process(nrf_log_str_formatter_entry_params_t * p_params, - nrf_fprintf_ctx_t * p_ctx) -{ - if (p_params->dropped) - { - nrf_fprintf(p_ctx, - "%sLogs dropped (%d)%s\r\n", - NRF_LOG_COLOR_CODE_RED, - p_params->dropped, - NRF_LOG_COLOR_CODE_DEFAULT); - } - - if (!(p_params->severity == NRF_LOG_SEVERITY_INFO_RAW)) - { - if (p_params->use_colors) - { - nrf_fprintf(p_ctx, "%s", - m_colors[nrf_log_color_id_get( p_params->module_id, p_params->severity)]); - } - timestamp_print(p_ctx, p_params->timestamp); - - nrf_fprintf(p_ctx, "<%s> %s: ", - severity_names[p_params->severity], nrf_log_module_name_get(p_params->module_id, false)); - } -} - -static void postfix_process(nrf_log_str_formatter_entry_params_t * p_params, - nrf_fprintf_ctx_t * p_ctx, - bool newline) -{ - if (!(p_params->severity == NRF_LOG_SEVERITY_INFO_RAW)) - { - if (p_params->use_colors) - { - nrf_fprintf(p_ctx, "%s", m_colors[0]); - } - nrf_fprintf(p_ctx, "\r\n"); - } - else if (newline) - { - nrf_fprintf(p_ctx, "\r\n"); - } - nrf_fprintf_buffer_flush(p_ctx); -} - -void nrf_log_std_entry_process(char const * p_str, - uint32_t const * p_args, - uint32_t nargs, - nrf_log_str_formatter_entry_params_t * p_params, - nrf_fprintf_ctx_t * p_ctx) -{ - bool auto_flush = p_ctx->auto_flush; - p_ctx->auto_flush = false; - - prefix_process(p_params, p_ctx); - - switch (nargs) - { - case 0: - nrf_fprintf(p_ctx, p_str); - break; - case 1: - nrf_fprintf(p_ctx, p_str, p_args[0]); - break; - case 2: - nrf_fprintf(p_ctx, p_str, p_args[0], p_args[1]); - break; - case 3: - nrf_fprintf(p_ctx, p_str, p_args[0], p_args[1], p_args[2]); - break; - case 4: - nrf_fprintf(p_ctx, p_str, p_args[0], p_args[1], p_args[2], p_args[3]); - break; - case 5: - nrf_fprintf(p_ctx, p_str, p_args[0], p_args[1], p_args[2], p_args[3], p_args[4]); - break; - case 6: - nrf_fprintf(p_ctx, p_str, p_args[0], p_args[1], p_args[2], p_args[3], p_args[4], p_args[5]); - break; - - default: - break; - } - - postfix_process(p_params, p_ctx, false); - p_ctx->auto_flush = auto_flush; -} - -#define HEXDUMP_BYTES_IN_LINE 8 - -void nrf_log_hexdump_entry_process(uint8_t * p_data, - uint32_t data_len, - nrf_log_str_formatter_entry_params_t * p_params, - nrf_fprintf_ctx_t * p_ctx) -{ - if (data_len > HEXDUMP_BYTES_IN_LINE) - { - return; - } - bool auto_flush = p_ctx->auto_flush; - p_ctx->auto_flush = false; - - prefix_process(p_params, p_ctx); - - uint32_t i; - - for (i = 0; i < HEXDUMP_BYTES_IN_LINE; i++) - { - if (i < data_len) - { - nrf_fprintf(p_ctx, " %02x", p_data[i]); - } - else - { - nrf_fprintf(p_ctx, " "); - } - } - nrf_fprintf(p_ctx, "|"); - - for (i = 0; i < HEXDUMP_BYTES_IN_LINE; i++) - { - if (i < data_len) - { - char c = (char)p_data[i]; - nrf_fprintf(p_ctx, "%c", isprint((int)c) ? c :'.'); - } - else - { - nrf_fprintf(p_ctx, " "); - } - } - - postfix_process(p_params, p_ctx, true); - - p_ctx->auto_flush = auto_flush; -} - -void nrf_log_str_formatter_timestamp_freq_set(uint32_t freq) -{ - m_timestamp_div = 1; - /* There is no point to have frequency higher than 1MHz (ns are not printed) and too high - * frequency leads to overflows in calculations. - */ - while (freq > 1000000) - { - freq /= 2; - m_timestamp_div *= 2; - } - m_freq = freq; -} -#endif //NRF_LOG_ENABLED diff --git a/bsp/boards/nrf52840/sdk/components/libraries/experimental_memobj/nrf_memobj.c b/bsp/boards/nrf52840/sdk/components/libraries/experimental_memobj/nrf_memobj.c deleted file mode 100644 index 7350437f3a..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/experimental_memobj/nrf_memobj.c +++ /dev/null @@ -1,231 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include "nrf_memobj.h" -#include "nrf_atomic.h" -#include "nrf_assert.h" - -typedef struct memobj_elem_s memobj_elem_t; - -typedef struct -{ - memobj_elem_t * p_next; -} memobj_header_t; - -typedef struct -{ - uint8_t user_cnt; - uint8_t chunk_cnt; - uint16_t chunk_size; -} memobj_head_header_fields_t; - -typedef struct -{ - union - { - nrf_atomic_u32_t atomic_user_cnt; - memobj_head_header_fields_t fields; - } data; -} memobj_head_header_t; - -typedef struct -{ - memobj_header_t header; - memobj_head_header_t head_header; - uint8_t data[1]; -} memobj_head_t; - -STATIC_ASSERT(sizeof(memobj_header_t) == NRF_MEMOBJ_STD_HEADER_SIZE); - -struct memobj_elem_s -{ - memobj_header_t header; - uint8_t data[1]; -}; - -ret_code_t nrf_memobj_pool_init(nrf_memobj_pool_t const * p_pool) -{ - return nrf_balloc_init((nrf_balloc_t const *)p_pool); -} - -nrf_memobj_t * nrf_memobj_alloc(nrf_memobj_pool_t const * p_pool, - size_t size) -{ - uint32_t bsize = (uint32_t)NRF_BALLOC_ELEMENT_SIZE((nrf_balloc_t const *)p_pool) - sizeof(memobj_header_t); - uint8_t num_of_chunks = (uint8_t)CEIL_DIV(size + sizeof(memobj_head_header_t), bsize); - - memobj_head_t * p_head = nrf_balloc_alloc((nrf_balloc_t const *)p_pool); - if (p_head == NULL) - { - return NULL; - } - p_head->head_header.data.fields.user_cnt = 0; - p_head->head_header.data.fields.chunk_cnt = 1; - p_head->head_header.data.fields.chunk_size = bsize; - - memobj_header_t * p_prev = (memobj_header_t *)p_head; - memobj_header_t * p_curr; - uint32_t i; - uint32_t chunk_less1 = (uint32_t)num_of_chunks - 1; - - p_prev->p_next = (memobj_elem_t *)p_pool; - for (i = 0; i < chunk_less1; i++) - { - p_curr = (memobj_header_t *)nrf_balloc_alloc((nrf_balloc_t const *)p_pool); - if (p_curr) - { - (p_head->head_header.data.fields.chunk_cnt)++; - p_prev->p_next = (memobj_elem_t *)p_curr; - p_curr->p_next = (memobj_elem_t *)p_pool; - p_prev = p_curr; - } - else - { - //Couldn't allocate all requested buffers - nrf_memobj_free((nrf_memobj_t *)p_head); - return NULL; - } - } - return (nrf_memobj_t *)p_head; -} - -void nrf_memobj_free(nrf_memobj_t * p_obj) -{ - memobj_head_t * p_head = (memobj_head_t *)p_obj; - uint8_t chunk_cnt = p_head->head_header.data.fields.chunk_cnt; - uint32_t i; - memobj_header_t * p_curr = (memobj_header_t *)p_obj; - memobj_header_t * p_next; - uint32_t chunk_less1 = (uint32_t)chunk_cnt - 1; - - for (i = 0; i < chunk_less1; i++) - { - p_curr = (memobj_header_t *)p_curr->p_next; - } - nrf_balloc_t const * p_pool2 = (nrf_balloc_t const *)p_curr->p_next; - - p_curr = (memobj_header_t *)p_obj; - for (i = 0; i < chunk_cnt; i++) - { - p_next = (memobj_header_t *)p_curr->p_next; - nrf_balloc_free(p_pool2, p_curr); - p_curr = p_next; - } -} - -void nrf_memobj_get(nrf_memobj_t const * p_obj) -{ - memobj_head_t * p_head = (memobj_head_t *)p_obj; - (void)nrf_atomic_u32_add(&p_head->head_header.data.atomic_user_cnt, 1); -} - -void nrf_memobj_put(nrf_memobj_t * p_obj) -{ - memobj_head_t * p_head = (memobj_head_t *)p_obj; - uint32_t user_cnt = nrf_atomic_u32_sub(&p_head->head_header.data.atomic_user_cnt, 1); - memobj_head_header_fields_t * p_fields = (memobj_head_header_fields_t *)&user_cnt; - if (p_fields->user_cnt == 0) - { - nrf_memobj_free(p_obj); - } -} - -static void memobj_op(nrf_memobj_t * p_obj, - void * p_data, - uint32_t len, - uint32_t offset, - bool read) -{ - - memobj_head_t * p_head = (memobj_head_t *)p_obj; - uint32_t space_in_chunk = p_head->head_header.data.fields.chunk_size; - memobj_elem_t * p_curr_chunk = (memobj_elem_t *)p_obj; - uint32_t chunk_idx = (offset + sizeof(memobj_head_header_fields_t))/space_in_chunk; - uint32_t chunk_offset = (offset + sizeof(memobj_head_header_fields_t)) % space_in_chunk; - - uint8_t chunks_expected = CEIL_DIV((offset + sizeof(memobj_head_header_fields_t) + len), - space_in_chunk); - UNUSED_VARIABLE(chunks_expected); - ASSERT(p_head->head_header.data.fields.chunk_cnt >= chunks_expected); - - while (chunk_idx > 0) - { - p_curr_chunk = p_curr_chunk->header.p_next; - chunk_idx--; - } - - uint32_t src_offset = 0; - uint32_t curr_cpy_size = space_in_chunk-chunk_offset; - curr_cpy_size = curr_cpy_size > len ? len : curr_cpy_size; - - while (len) - { - if (read) - { - memcpy(&((uint8_t *)p_data)[src_offset], &p_curr_chunk->data[chunk_offset], curr_cpy_size); - } - else - { - memcpy(&p_curr_chunk->data[chunk_offset], &((uint8_t *)p_data)[src_offset], curr_cpy_size); - } - chunk_offset = 0; - p_curr_chunk = p_curr_chunk->header.p_next; - len -= curr_cpy_size; - src_offset += curr_cpy_size; - curr_cpy_size = (space_in_chunk > len) ? len : space_in_chunk; - } -} - -void nrf_memobj_write(nrf_memobj_t * p_obj, - void * p_data, - uint32_t len, - uint32_t offset) -{ - - memobj_op(p_obj, p_data, len, offset, false); -} - -void nrf_memobj_read(nrf_memobj_t * p_obj, - void * p_data, - uint32_t len, - uint32_t offset) -{ - memobj_op(p_obj, p_data, len, offset, true); -} diff --git a/bsp/boards/nrf52840/sdk/components/libraries/experimental_memobj/nrf_memobj.h b/bsp/boards/nrf52840/sdk/components/libraries/experimental_memobj/nrf_memobj.h deleted file mode 100644 index 91bbaf95d4..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/experimental_memobj/nrf_memobj.h +++ /dev/null @@ -1,198 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_MEMOBJ_H -#define NRF_MEMOBJ_H - -/** -* @defgroup nrf_memobj Memory Object module -* @{ -* @ingroup app_common -* @brief Functions for controlling memory object -*/ -#include -#include -#include "sdk_errors.h" -#include "nrf_balloc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Memory object can consist of multiple object with the same size. Each object has header and data - * part. First element in memory object is memory object head which has special header, remaining objects - * has the same header. Model of memory object is presented below. - * - * |---------------------| |---------------------| |---------------------| - * | head header (u32): | --->| std header - p_next |------->| p_memobj_pool | - * | num_of_chunks, | | |---------------------| |---------------------| - * | ref counter | | | | | | - * |---------------------| | | | | | - * | std header - p_next |-| | | .... | | - * |---------------------| | data | | data | - * | | | | | | - * | data | | | | | - * | | | | | | - * |---------------------| |---------------------| |---------------------| - * head mid_element last_element - * - * - */ -#define NRF_MEMOBJ_STD_HEADER_SIZE sizeof(uint32_t) - -/** - * @brief Macro for creating a nrf_memobj pool. - * - * Macro declares nrf_balloc object. Element in the pool contains user defined data part and - * memobj header. - */ -#define NRF_MEMOBJ_POOL_DEF(_name, _element_size, _pool_size) \ - NRF_BALLOC_DEF(_name, ((_element_size)+NRF_MEMOBJ_STD_HEADER_SIZE), (_pool_size)) - -/** - * @brief Pool of memobj. - */ -typedef nrf_balloc_t nrf_memobj_pool_t; - -/** - * @brief Memobj handle. - */ -typedef void * nrf_memobj_t; - -/** - * @brief Function for initializing the memobj pool instance. - * - * This function initializes the pool. - * - * @param[in] p_pool Pointer to the memobj pool instance structure. - * - * @return NRF_SUCCESS on success, otherwise error code. - */ -ret_code_t nrf_memobj_pool_init(nrf_memobj_pool_t const * p_pool); - -/** - * @brief Function for allocating memobj with requested size. - * - * Fixed length elements in the pool are linked together to provide amount of memory requested by - * the user. If memory object is successfully allocated then user can use memory however it is - * fragmented into multiple object so it has to be access through the API: @ref nrf_memobj_write, - * @ref nrf_memobj_read. - * - * This function initializes the pool. - * - * @param[in] p_pool Pointer to the memobj pool instance structure. - * @param[in] size Data size of requested object. - * - * @return Pointer to memory object or NULL if requested size cannot be allocated. - */ -nrf_memobj_t * nrf_memobj_alloc(nrf_memobj_pool_t const * p_pool, - size_t size); - -/** - * @brief Function for indicating that memory object is used and cannot be freed. - * - * Memory object can be shared and reused between multiple modules and this mechanism ensures that - * object is freed when no longer used by any module. Memory object has a counter which is incremented - * whenever this function is called. @ref nrf_memobj_put function decrements the counter. - * - * @param[in] p_obj Pointer to memory object. - */ -void nrf_memobj_get(nrf_memobj_t const * p_obj); - - -/** - * @brief Function for indicated that memory object is no longer used by the module and can be freed - * if no other module is using it. - * - * Memory object is returned to the pool if internal counter reaches 0 after decrementing. It means - * that no other module is needing it anymore. - * - * @note Memory object holds pointer to the pool which was used to allocate it so it does not have - * to be provided explicitly to this function. - * - * @param[in] p_obj Pointer to memory object. - */ -void nrf_memobj_put(nrf_memobj_t * p_obj); - - -/** - * @brief Function for forcing freeing of the memory object. - * - * @note This function should be use with caution because it can lead to undefined behavior of the - * modules since modules using the memory object are not aware that it has been freed. - * - * @param[in] p_obj Pointer to memory object. - */ -void nrf_memobj_free(nrf_memobj_t * p_obj); - -/** - * @brief Function for writing data to the memory object. - * - * @param[in] p_obj Pointer to memory object. - * @param[in] p_data Pointer to data to be written to the memory object. - * @param[in] len Amount of data to be written to the memory object. - * @param[in] offset Offset. - */ -void nrf_memobj_write(nrf_memobj_t * p_obj, - void * p_data, - uint32_t len, - uint32_t offset); - -/** - * @brief Function for reading data from the memory object. - * - * @param[in] p_obj Pointer to memory object. - * @param[in] p_data Pointer to the destination buffer. - * @param[in] len Amount of data to be read from the memory object. - * @param[in] offset Offset. - */ -void nrf_memobj_read(nrf_memobj_t * p_obj, - void * p_data, - uint32_t len, - uint32_t offset); - -#ifdef __cplusplus -} -#endif - -#endif //NRF_MEMOBJ_H - -/** @} */ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/experimental_section_vars/nrf_section.h b/bsp/boards/nrf52840/sdk/components/libraries/experimental_section_vars/nrf_section.h deleted file mode 100644 index d63d0d51cc..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/experimental_section_vars/nrf_section.h +++ /dev/null @@ -1,191 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef NRF_SECTION_H__ -#define NRF_SECTION_H__ - -#include "nordic_common.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup section_vars Section variables - * @ingroup app_common - * @{ - * - * @brief Section variables. - */ - -//lint -save -e27 -esym(526,*) - -#if defined(__ICCARM__) -// Enable IAR language extensions -#pragma language=extended -#endif - -/**@brief Macro for obtaining the address of the beginning of a section. - * - * param[in] section_name Name of the section. - * @hideinitializer - */ -#if defined(__CC_ARM) -#define NRF_SECTION_START_ADDR(section_name) &CONCAT_2(section_name, $$Base) - -#elif defined(__GNUC__) -#define NRF_SECTION_START_ADDR(section_name) &CONCAT_2(__start_, section_name) - -#elif defined(__ICCARM__) -#define NRF_SECTION_START_ADDR(section_name) __section_begin(STRINGIFY(section_name)) -#endif - - -/**@brief Macro for obtaining the address of the end of a section. - * - * @param[in] section_name Name of the section. - * @hideinitializer - */ -#if defined(__CC_ARM) -#define NRF_SECTION_END_ADDR(section_name) &CONCAT_2(section_name, $$Limit) - -#elif defined(__GNUC__) -#define NRF_SECTION_END_ADDR(section_name) &CONCAT_2(__stop_, section_name) - -#elif defined(__ICCARM__) -#define NRF_SECTION_END_ADDR(section_name) __section_end(STRINGIFY(section_name)) -#endif - - -/**@brief Macro for retrieving the length of a given section, in bytes. - * - * @param[in] section_name Name of the section. - * @hideinitializer - */ -#define NRF_SECTION_LENGTH(section_name) \ - ((size_t)NRF_SECTION_END_ADDR(section_name) - \ - (size_t)NRF_SECTION_START_ADDR(section_name)) - - -/**@brief Macro for creating a section. - * - * @param[in] section_name Name of the section. - * @param[in] data_type Data type of the variables to be registered in the section. - * - * @warning Data type must be word aligned to prevent padding. - * @hideinitializer - */ -#if defined(__CC_ARM) -#define NRF_SECTION_DEF(section_name, data_type) \ - extern data_type * CONCAT_2(section_name, $$Base); \ - extern void * CONCAT_2(section_name, $$Limit) - -#elif defined(__GNUC__) -#define NRF_SECTION_DEF(section_name, data_type) \ - extern data_type * CONCAT_2(__start_, section_name); \ - extern void * CONCAT_2(__stop_, section_name) - -#elif defined(__ICCARM__) -#define NRF_SECTION_DEF(section_name, data_type) \ - _Pragma(STRINGIFY(section = STRINGIFY(section_name))); - -#endif - - -/**@brief Macro for declaring a variable and registering it in a section. - * - * @details Declares a variable and registers it in a named section. This macro ensures that the - * variable is not stripped away when using optimizations. - * - * @note The order in which variables are placed in a section is dependent on the order in - * which the linker script encounters the variables during linking. - * - * @param[in] section_name Name of the section. - * @param[in] section_var Variable to register in the given section. - * @hideinitializer - */ -#if defined(__CC_ARM) -#define NRF_SECTION_ITEM_REGISTER(section_name, section_var) \ - section_var __attribute__ ((section(STRINGIFY(section_name)))) __attribute__((used)) - -#elif defined(__GNUC__) -#define NRF_SECTION_ITEM_REGISTER(section_name, section_var) \ - section_var __attribute__ ((section("." STRINGIFY(section_name)))) __attribute__((used)) - -#elif defined(__ICCARM__) -#define NRF_SECTION_ITEM_REGISTER(section_name, section_var) \ - __root section_var @ STRINGIFY(section_name) -#endif - - -/**@brief Macro for retrieving a variable from a section. - * - * @warning The stored symbol can only be resolved using this macro if the - * type of the data is word aligned. The operation of acquiring - * the stored symbol relies on the size of the stored type. No - * padding can exist in the named section in between individual - * stored items or this macro will fail. - * - * @param[in] section_name Name of the section. - * @param[in] data_type Data type of the variable. - * @param[in] i Index of the variable in section. - * @hideinitializer - */ -#define NRF_SECTION_ITEM_GET(section_name, data_type, i) \ - ((data_type*)NRF_SECTION_START_ADDR(section_name) + (i)) - - -/**@brief Macro for getting the number of variables in a section. - * - * @param[in] section_name Name of the section. - * @param[in] data_type Data type of the variables in the section. - * @hideinitializer - */ -#define NRF_SECTION_ITEM_COUNT(section_name, data_type) \ - NRF_SECTION_LENGTH(section_name) / sizeof(data_type) - -/** @} */ - -//lint -restore - -#ifdef __cplusplus -} -#endif - -#endif // NRF_SECTION_H__ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/experimental_section_vars/nrf_section_iter.c b/bsp/boards/nrf52840/sdk/components/libraries/experimental_section_vars/nrf_section_iter.c deleted file mode 100644 index a55a0021a9..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/experimental_section_vars/nrf_section_iter.c +++ /dev/null @@ -1,125 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include "sdk_common.h" - -#if NRF_MODULE_ENABLED(NRF_SECTION_ITER) - -#include "nrf_section_iter.h" - - -#if !defined(__GNUC__) -static void nrf_section_iter_item_set(nrf_section_iter_t * p_iter) -{ - ASSERT(p_iter != NULL); - ASSERT(p_iter->p_set != NULL); - ASSERT(p_iter->p_section != NULL); - - while (true) - { - if (p_iter->p_section == p_iter->p_set->p_last) - { - // End of the section set. - p_iter->p_item = NULL; - return; - } - - if (p_iter->p_section->p_start != p_iter->p_section->p_end) - { - // Not empty section. - p_iter->p_item = p_iter->p_section->p_start; - return; - } - - // Next section. - p_iter->p_section++; - } -} -#endif - - -void nrf_section_iter_init(nrf_section_iter_t * p_iter, nrf_section_set_t const * p_set) -{ - ASSERT(p_iter != NULL); - ASSERT(p_set != NULL); - - p_iter->p_set = p_set; - -#if defined(__GNUC__) - p_iter->p_item = p_iter->p_set->section.p_start; - if (p_iter->p_item == p_iter->p_set->section.p_end) - { - p_iter->p_item = NULL; - } -#else - p_iter->p_section = p_set->p_first; - nrf_section_iter_item_set(p_iter); -#endif -} - -void nrf_section_iter_next(nrf_section_iter_t * p_iter) -{ - ASSERT(p_iter != NULL); - ASSERT(p_iter->p_set != NULL); - - if (p_iter->p_item == NULL) - { - return; - } - - p_iter->p_item = (void *)((size_t)(p_iter->p_item) + p_iter->p_set->item_size); - -#if defined(__GNUC__) - if (p_iter->p_item == p_iter->p_set->section.p_end) - { - p_iter->p_item = NULL; - } -#else - ASSERT(p_iter->p_section != NULL); - // End of current section reached? - if (p_iter->p_item == p_iter->p_section->p_end) - { - p_iter->p_section++; - nrf_section_iter_item_set(p_iter); - } -#endif -} - -#endif // NRF_MODULE_ENABLED(NRF_SECTION_ITER) diff --git a/bsp/boards/nrf52840/sdk/components/libraries/experimental_section_vars/nrf_section_iter.h b/bsp/boards/nrf52840/sdk/components/libraries/experimental_section_vars/nrf_section_iter.h deleted file mode 100644 index e4e8f35c0f..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/experimental_section_vars/nrf_section_iter.h +++ /dev/null @@ -1,206 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_SECTION_ITER_H__ -#define NRF_SECTION_ITER_H__ - -#include -#include "nrf_section.h" -#include "nrf_assert.h" -#include "app_util.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -/** - * @defgroup nrf_section_iter Section variables iterator - * @ingroup app_common - * @{ - */ - -/**@brief Single section description structure. */ -typedef struct -{ - void * p_start; //!< Pointer to the start of section. - void * p_end; //!< Pointer to the end of section. -} nrf_section_t; - - -/**@brief Set of the sections description structure. */ -typedef struct -{ -#if defined(__GNUC__) - nrf_section_t section; //!< Description of the set of sections. - /**< - * In case of GCC all sections in the set are sorted and - * placed in contiguous area, because they are treated as - * one section. - */ -#else - nrf_section_t const * p_first; //!< Pointer to the first section in the set. - nrf_section_t const * p_last; //!< Pointer to the last section in the set. -#endif - size_t item_size; //!< Size of the single item in the section. -} nrf_section_set_t; - - -/**@brief Section iterator structure. */ -typedef struct -{ - nrf_section_set_t const * p_set; //!< Pointer to the appropriate section set. -#if !defined(__GNUC__) - nrf_section_t const * p_section; //!< Pointer to the selected section. - /**< - * In case of GCC all sections in the set are sorted and - * placed in contiguous area, because they are treated - * as one section. - */ -#endif - void * p_item; //!< Pointer to the selected item in the section. -} nrf_section_iter_t; - - -/**@brief Create a set of sections. - * - * @note This macro reserves memory for the given set of sections. - * - * @details A set of sections, is an ordered collections of sections. - * - * @param[in] _name Name of the set. - * @param[in] _type Type of the elements stored in the sections. - * @param[in] _count Number of the sections in the set. This parameter is ignored in case of GCC. - * @hideinitializer - */ -#if defined(__GNUC__) - -#define NRF_SECTION_SET_DEF(_name, _type, _count) \ - \ - NRF_SECTION_DEF(_name, _type); \ - static nrf_section_set_t const _name = \ - { \ - .section = \ - { \ - .p_start = NRF_SECTION_START_ADDR(_name), \ - .p_end = NRF_SECTION_END_ADDR(_name), \ - }, \ - .item_size = sizeof(_type), \ - } - -#else - -#define NRF_SECTION_SET_DEF(_name, _type, _count) \ -/*lint -save -emacro(14, MACRO_REPEAT_FOR*) */ \ -MACRO_REPEAT_FOR(_count, NRF_SECTION_DEF_, _name, _type) \ -static nrf_section_t const CONCAT_2(_name, _array)[] = \ -{ \ - MACRO_REPEAT_FOR(_count, NRF_SECTION_SET_DEF_, _name) \ -}; \ -/*lint -restore */ \ -static nrf_section_set_t const _name = \ -{ \ - .p_first = CONCAT_2(_name, _array), \ - .p_last = CONCAT_2(_name, _array) + ARRAY_SIZE(CONCAT_2(_name, _array)), \ - .item_size = sizeof(_type), \ -} - -#ifndef DOXYGEN -#define NRF_SECTION_DEF_(_priority, _name, _type) \ -NRF_SECTION_DEF(CONCAT_2(_name, _priority), _type); - -#define NRF_SECTION_SET_DEF_(_priority, _name) \ -{ \ - .p_start = NRF_SECTION_START_ADDR(CONCAT_2(_name, _priority)), \ - .p_end = NRF_SECTION_END_ADDR(CONCAT_2(_name, _priority)), \ -}, -#endif // DOXYGEN -#endif // __GNUC__ - - -/**@brief Macro to declare a variable and register it in the section set. - * - * @note The order of the section in the set is based on the priority. The order with which - * variables are placed in a section is dependant on the order with which the linker - * encouters the variables during linking. - * - * @param[in] _name Name of the section set. - * @param[in] _priority Priority of the desired section. - * @param[in] _var The variable to register in the given section. - * @hideinitializer - */ -#define NRF_SECTION_SET_ITEM_REGISTER(_name, _priority, _var) \ - NRF_SECTION_ITEM_REGISTER(CONCAT_2(_name, _priority), _var) - - -/**@brief Function for initializing the section set iterator. - * - * @param[in] p_iter Pointer to the iterator. - * @param[in] p_set Pointer to the sections set. - */ -void nrf_section_iter_init(nrf_section_iter_t * p_iter, nrf_section_set_t const * p_set); - - -/**@brief Function for incrementing iterator. - * - * @param[in] p_iter Pointer to the iterator. - */ -void nrf_section_iter_next(nrf_section_iter_t * p_iter); - - -/**@brief Function for getting the element pointed to by the iterator. - * - * @param[in] p_iter Pointer to the iterator. - * - * @retval Pointer to the element or NULL if iterator points end of the set. - */ -static inline void * nrf_section_iter_get(nrf_section_iter_t const * p_iter) -{ - ASSERT(p_iter); - return p_iter->p_item; -} - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_SECTION_ITER_H__ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/fifo/app_fifo.c b/bsp/boards/nrf52840/sdk/components/libraries/fifo/app_fifo.c deleted file mode 100644 index 80202677f6..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/fifo/app_fifo.c +++ /dev/null @@ -1,214 +0,0 @@ -/** - * Copyright (c) 2013 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include "sdk_common.h" -#if NRF_MODULE_ENABLED(APP_FIFO) -#include "app_fifo.h" - -static __INLINE uint32_t fifo_length(app_fifo_t * p_fifo) -{ - uint32_t tmp = p_fifo->read_pos; - return p_fifo->write_pos - tmp; -} - - -#define FIFO_LENGTH() fifo_length(p_fifo) /**< Macro for calculating the FIFO length. */ - - -/**@brief Put one byte to the FIFO. */ -static __INLINE void fifo_put(app_fifo_t * p_fifo, uint8_t byte) -{ - p_fifo->p_buf[p_fifo->write_pos & p_fifo->buf_size_mask] = byte; - p_fifo->write_pos++; -} - - -/**@brief Look at one byte in the FIFO. */ -static __INLINE void fifo_peek(app_fifo_t * p_fifo, uint16_t index, uint8_t * p_byte) -{ - *p_byte = p_fifo->p_buf[(p_fifo->read_pos + index) & p_fifo->buf_size_mask]; -} - - -/**@brief Get one byte from the FIFO. */ -static __INLINE void fifo_get(app_fifo_t * p_fifo, uint8_t * p_byte) -{ - fifo_peek(p_fifo, 0, p_byte); - p_fifo->read_pos++; -} - - -uint32_t app_fifo_init(app_fifo_t * p_fifo, uint8_t * p_buf, uint16_t buf_size) -{ - // Check buffer for null pointer. - if (p_buf == NULL) - { - return NRF_ERROR_NULL; - } - - // Check that the buffer size is a power of two. - if (!IS_POWER_OF_TWO(buf_size)) - { - return NRF_ERROR_INVALID_LENGTH; - } - - p_fifo->p_buf = p_buf; - p_fifo->buf_size_mask = buf_size - 1; - p_fifo->read_pos = 0; - p_fifo->write_pos = 0; - - return NRF_SUCCESS; -} - - -uint32_t app_fifo_put(app_fifo_t * p_fifo, uint8_t byte) -{ - if (FIFO_LENGTH() <= p_fifo->buf_size_mask) - { - fifo_put(p_fifo, byte); - return NRF_SUCCESS; - } - - return NRF_ERROR_NO_MEM; -} - - -uint32_t app_fifo_get(app_fifo_t * p_fifo, uint8_t * p_byte) -{ - if (FIFO_LENGTH() != 0) - { - fifo_get(p_fifo, p_byte); - return NRF_SUCCESS; - } - - return NRF_ERROR_NOT_FOUND; - -} - - -uint32_t app_fifo_peek(app_fifo_t * p_fifo, uint16_t index, uint8_t * p_byte) -{ - if (FIFO_LENGTH() > index) - { - fifo_peek(p_fifo, index, p_byte); - return NRF_SUCCESS; - } - - return NRF_ERROR_NOT_FOUND; -} - - -uint32_t app_fifo_flush(app_fifo_t * p_fifo) -{ - p_fifo->read_pos = p_fifo->write_pos; - return NRF_SUCCESS; -} - - -uint32_t app_fifo_read(app_fifo_t * p_fifo, uint8_t * p_byte_array, uint32_t * p_size) -{ - VERIFY_PARAM_NOT_NULL(p_fifo); - VERIFY_PARAM_NOT_NULL(p_size); - - const uint32_t byte_count = fifo_length(p_fifo); - const uint32_t requested_len = (*p_size); - uint32_t index = 0; - uint32_t read_size = MIN(requested_len, byte_count); - - (*p_size) = byte_count; - - // Check if the FIFO is empty. - if (byte_count == 0) - { - return NRF_ERROR_NOT_FOUND; - } - - // Check if application has requested only the size. - if (p_byte_array == NULL) - { - return NRF_SUCCESS; - } - - // Fetch bytes from the FIFO. - while (index < read_size) - { - fifo_get(p_fifo, &p_byte_array[index++]); - } - - (*p_size) = read_size; - - return NRF_SUCCESS; -} - - -uint32_t app_fifo_write(app_fifo_t * p_fifo, uint8_t const * p_byte_array, uint32_t * p_size) -{ - VERIFY_PARAM_NOT_NULL(p_fifo); - VERIFY_PARAM_NOT_NULL(p_size); - - const uint32_t available_count = p_fifo->buf_size_mask - fifo_length(p_fifo) + 1; - const uint32_t requested_len = (*p_size); - uint32_t index = 0; - uint32_t write_size = MIN(requested_len, available_count); - - (*p_size) = available_count; - - // Check if the FIFO is FULL. - if (available_count == 0) - { - return NRF_ERROR_NO_MEM; - } - - // Check if application has requested only the size. - if (p_byte_array == NULL) - { - return NRF_SUCCESS; - } - - //Fetch bytes from the FIFO. - while (index < write_size) - { - fifo_put(p_fifo, p_byte_array[index++]); - } - - (*p_size) = write_size; - - return NRF_SUCCESS; -} -#endif //NRF_MODULE_ENABLED(APP_FIFO) diff --git a/bsp/boards/nrf52840/sdk/components/libraries/fifo/app_fifo.h b/bsp/boards/nrf52840/sdk/components/libraries/fifo/app_fifo.h deleted file mode 100644 index bc7b9d3956..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/fifo/app_fifo.h +++ /dev/null @@ -1,181 +0,0 @@ -/** - * Copyright (c) 2013 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -/**@file - * - * @defgroup app_fifo FIFO implementation - * @{ - * @ingroup app_common - * - * @brief FIFO implementation. - */ - -#ifndef APP_FIFO_H__ -#define APP_FIFO_H__ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/**@brief A FIFO instance structure. - * @details Keeps track of which bytes to read and write next. - * Also, it keeps the information about which memory is allocated for the buffer - * and its size. This structure must be initialized by app_fifo_init() before use. - */ -typedef struct -{ - uint8_t * p_buf; /**< Pointer to FIFO buffer memory. */ - uint16_t buf_size_mask; /**< Read/write index mask. Also used for size checking. */ - volatile uint32_t read_pos; /**< Next read position in the FIFO buffer. */ - volatile uint32_t write_pos; /**< Next write position in the FIFO buffer. */ -} app_fifo_t; - -/**@brief Function for initializing the FIFO. - * - * @param[out] p_fifo FIFO object. - * @param[in] p_buf FIFO buffer for storing data. The buffer size must be a power of two. - * @param[in] buf_size Size of the FIFO buffer provided. This size must be a power of two. - * - * @retval NRF_SUCCESS If initialization was successful. - * @retval NRF_ERROR_NULL If a NULL pointer is provided as buffer. - * @retval NRF_ERROR_INVALID_LENGTH If size of buffer provided is not a power of two. - */ -uint32_t app_fifo_init(app_fifo_t * p_fifo, uint8_t * p_buf, uint16_t buf_size); - -/**@brief Function for adding an element to the FIFO. - * - * @param[in] p_fifo Pointer to the FIFO. - * @param[in] byte Data byte to add to the FIFO. - * - * @retval NRF_SUCCESS If an element has been successfully added to the FIFO. - * @retval NRF_ERROR_NO_MEM If the FIFO is full. - */ -uint32_t app_fifo_put(app_fifo_t * p_fifo, uint8_t byte); - -/**@brief Function for getting the next element from the FIFO. - * - * @param[in] p_fifo Pointer to the FIFO. - * @param[out] p_byte Byte fetched from the FIFO. - * - * @retval NRF_SUCCESS If an element was returned. - * @retval NRF_ERROR_NOT_FOUND If there are no more elements in the queue. - */ -uint32_t app_fifo_get(app_fifo_t * p_fifo, uint8_t * p_byte); - -/**@brief Function for looking at an element in the FIFO, without consuming it. - * - * @param[in] p_fifo Pointer to the FIFO. - * @param[in] index Which element to look at. The lower the index, the earlier it was put. - * @param[out] p_byte Byte fetched from the FIFO. - * - * @retval NRF_SUCCESS If an element was returned. - * @retval NRF_ERROR_NOT_FOUND If there are no more elements in the queue, or the index was - * too large. - */ -uint32_t app_fifo_peek(app_fifo_t * p_fifo, uint16_t index, uint8_t * p_byte); - -/**@brief Function for flushing the FIFO. - * - * @param[in] p_fifo Pointer to the FIFO. - * - * @retval NRF_SUCCESS If the FIFO was flushed successfully. - */ -uint32_t app_fifo_flush(app_fifo_t * p_fifo); - -/**@brief Function for reading bytes from the FIFO. - * - * This function can also be used to get the number of bytes in the FIFO. - * - * @param[in] p_fifo Pointer to the FIFO. Must not be NULL. - * @param[out] p_byte_array Memory pointer where the read bytes are fetched from the FIFO. - * Can be NULL. If NULL, the number of bytes that can be read in the FIFO - * are returned in the p_size parameter. - * @param[inout] p_size Address to memory indicating the maximum number of bytes to be read. - * The provided memory is overwritten with the actual number of bytes - * read if the procedure was successful. This field must not be NULL. - * If p_byte_array is set to NULL by the application, this parameter - * returns the number of bytes in the FIFO. - * - * @retval NRF_SUCCESS If the procedure is successful. The actual number of bytes read might - * be less than the requested maximum, depending on how many elements exist - * in the FIFO. Even if less bytes are returned, the procedure is considered - * successful. - * @retval NRF_ERROR_NULL If a NULL parameter was passed for a parameter that must not - * be NULL. - * @retval NRF_ERROR_NOT_FOUND If the FIFO is empty. - */ -uint32_t app_fifo_read(app_fifo_t * p_fifo, uint8_t * p_byte_array, uint32_t * p_size); - -/**@brief Function for writing bytes to the FIFO. - * - * This function can also be used to get the available size on the FIFO. - * - * @param[in] p_fifo Pointer to the FIFO. Must not be NULL. - * @param[in] p_byte_array Memory pointer containing the bytes to be written to the FIFO. - * Can be NULL. If NULL, this function returns the number of bytes - * that can be written to the FIFO. - * @param[inout] p_size Address to memory indicating the maximum number of bytes to be written. - * The provided memory is overwritten with the number of bytes that were actually - * written if the procedure is successful. This field must not be NULL. - * If p_byte_array is set to NULL by the application, this parameter - * returns the number of bytes available in the FIFO. - * - * @retval NRF_SUCCESS If the procedure is successful. The actual number of bytes written might - * be less than the requested maximum, depending on how much room there is in - * the FIFO. Even if less bytes are written, the procedure is considered - * successful. If the write was partial, the application should use - * subsequent calls to attempt writing the data again. - * @retval NRF_ERROR_NULL If a NULL parameter was passed for a parameter that must not - * be NULL. - * @retval NRF_ERROR_NO_MEM If the FIFO is full. - * - */ -uint32_t app_fifo_write(app_fifo_t * p_fifo, uint8_t const * p_byte_array, uint32_t * p_size); - - -#ifdef __cplusplus -} -#endif - -#endif // APP_FIFO_H__ - -/** @} */ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/mutex/nrf_mtx.h b/bsp/boards/nrf52840/sdk/components/libraries/mutex/nrf_mtx.h deleted file mode 100644 index 14ae771b9b..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/mutex/nrf_mtx.h +++ /dev/null @@ -1,159 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -/** @file - * @defgroup nrf_mtx nRF Mutex - * @{ - * @ingroup app_common - * @brief Mutex used for protecting resources. - * - * This module provides a mutex that can be used to ensure only one context may enter a critical - * section holding the lock. - */ -#ifndef NRF_MTX_H__ -#define NRF_MTX_H__ - -#include -#include -#include "nrf.h" -#include "nrf_atomic.h" -#include "nrf_assert.h" - -#define NRF_MTX_LOCKED 1 -#define NRF_MTX_UNLOCKED 0 - -/** - * @brief Mutex data type. - * - * All fields in this struct are internal, and should never be modified outside of the nrf_mtx_* - * functions. - */ -typedef nrf_atomic_u32_t nrf_mtx_t; - -/** - * @brief Initialize mutex. - * - * This function _must_ be called before nrf_mtx_trylock() and nrf_mtx_unlock() functions. - * - * @param[in, out] p_mtx The mutex to be initialized. - */ -__STATIC_INLINE void nrf_mtx_init(nrf_mtx_t * p_mtx); - - -/** - * @brief Destroy mutex. - * - * This function can be used in abort scenarios or when the mutex is no longer to be used. - * - * @param[in] p_mtx The mutex to be destroy. - */ -__STATIC_INLINE void nrf_mtx_destroy(nrf_mtx_t * p_mtx); - -/** - * @brief Try to lock a mutex. - * - * If the mutex is already held by another context, this function will return immediately. - * - * @param[in, out] p_mtx The mutex to be locked. - * @return true if lock was acquired, false if not - */ -__STATIC_INLINE bool nrf_mtx_trylock(nrf_mtx_t * p_mtx); - -/** - * @brief Unlock a mutex. - * - * This function _must_ only be called when holding the lock. Unlocking a mutex which you do not - * hold will give undefined behavior. - * - * @note Unlock must happen from the same context as the one used to lock the mutex. - * - * @param[in, out] p_mtx The mutex to be unlocked. - */ -__STATIC_INLINE void nrf_mtx_unlock(nrf_mtx_t * p_mtx); - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -__STATIC_INLINE void nrf_mtx_init(nrf_mtx_t * p_mtx) -{ - ASSERT(p_mtx != NULL); - - *p_mtx = NRF_MTX_UNLOCKED; - __DMB(); -} - -__STATIC_INLINE void nrf_mtx_destroy(nrf_mtx_t * p_mtx) -{ - ASSERT(p_mtx != NULL); - - // Add memory barrier to ensure that any memory operations protected by the mutex complete - // before the mutex is destroyed. - __DMB(); - - *p_mtx = NRF_MTX_UNLOCKED; -} - -__STATIC_INLINE bool nrf_mtx_trylock(nrf_mtx_t * p_mtx) -{ - ASSERT(p_mtx != NULL); - - uint32_t old_val = nrf_atomic_u32_fetch_store(p_mtx, NRF_MTX_LOCKED); - - // Add memory barrier to ensure that the mutex is locked before any memory operations protected - // by the mutex are started. - __DMB(); - - return (old_val == NRF_MTX_UNLOCKED); -} - -__STATIC_INLINE void nrf_mtx_unlock(nrf_mtx_t * p_mtx) -{ - ASSERT(p_mtx != NULL); - ASSERT(*p_mtx == NRF_MTX_LOCKED); - - // Add memory barrier to ensure that any memory operations protected by the mutex complete - // before the mutex is unlocked. - __DMB(); - - *p_mtx = NRF_MTX_UNLOCKED; -} - -#endif //SUPPRESS_INLINE_IMPLEMENTATION - -#endif // NRF_MTX_H__ -/** @} */ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/pwr_mgmt/nrf_pwr_mgmt.c b/bsp/boards/nrf52840/sdk/components/libraries/pwr_mgmt/nrf_pwr_mgmt.c deleted file mode 100644 index caf4909521..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/pwr_mgmt/nrf_pwr_mgmt.c +++ /dev/null @@ -1,465 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include "sdk_common.h" -#if NRF_MODULE_ENABLED(NRF_PWR_MGMT) - -#include "nrf_pwr_mgmt.h" -#include "nrf.h" -#include "nrf_mtx.h" -#include "nrf_power.h" -#include "app_error.h" -#include "nrf_assert.h" -#include "nrf_log_ctrl.h" -#include "app_util_platform.h" - -#define NRF_LOG_MODULE_NAME pwr_mgmt -#if NRF_PWR_MGMT_CONFIG_LOG_ENABLED - #define NRF_LOG_LEVEL NRF_PWR_MGMT_CONFIG_LOG_LEVEL - #define NRF_LOG_INFO_COLOR NRF_PWR_MGMT_CONFIG_INFO_COLOR - #define NRF_LOG_DEBUG_COLOR NRF_PWR_MGMT_CONFIG_DEBUG_COLOR -#else - #define NRF_LOG_LEVEL 0 -#endif // NRF_PWR_MGMT_CONFIG_LOG_ENABLED -#include "nrf_log.h" -NRF_LOG_MODULE_REGISTER(); - -#ifdef SOFTDEVICE_PRESENT - #include "nrf_soc.h" - #include "nrf_sdh.h" -#endif // SOFTDEVICE_PRESENT - - -#if NRF_PWR_MGMT_CONFIG_USE_SCHEDULER - #if (APP_SCHEDULER_ENABLED != 1) - #error "APP_SCHEDULER is required." - #endif - #include "app_scheduler.h" -#endif // NRF_PWR_MGMT_CONFIG_USE_SCHEDULER - - -// Create section "pwr_mgmt_data". -NRF_SECTION_SET_DEF(pwr_mgmt_data, - nrf_pwr_mgmt_shutdown_handler_t, - NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT); - -static nrf_pwr_mgmt_evt_t m_pwr_mgmt_evt; /**< Event type which will be passed to the shutdown - handlers.*/ -static nrf_mtx_t m_sysoff_mtx; /**< Module API lock.*/ -static bool m_shutdown_started; /**< True if application started the shutdown preparation. */ -static nrf_section_iter_t m_handlers_iter; /**< Shutdown handlers iterator. */ - -#if (NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED && __FPU_PRESENT) - #define PWR_MGMT_FPU_SLEEP_PREPARE() pwr_mgmt_fpu_sleep_prepare() - - __STATIC_INLINE void pwr_mgmt_fpu_sleep_prepare(void) - { - uint32_t fpscr; - CRITICAL_REGION_ENTER(); - fpscr = __get_FPSCR(); - /* - * Clear FPU exceptions. - * Without this step, the FPU interrupt is marked as pending, - * preventing system from sleeping. Exceptions cleared: - * - IOC - Invalid Operation cumulative exception bit. - * - DZC - Division by Zero cumulative exception bit. - * - OFC - Overflow cumulative exception bit. - * - UFC - Underflow cumulative exception bit. - * - IXC - Inexact cumulative exception bit. - * - IDC - Input Denormal cumulative exception bit. - */ - __set_FPSCR(fpscr & ~0x9Fu); - __DMB(); - NVIC_ClearPendingIRQ(FPU_IRQn); - CRITICAL_REGION_EXIT(); - - /* - * Assert no critical FPU exception is signaled: - * - IOC - Invalid Operation cumulative exception bit. - * - DZC - Division by Zero cumulative exception bit. - * - OFC - Overflow cumulative exception bit. - */ - ASSERT((fpscr & 0x07) == 0); - } -#else - #define PWR_MGMT_FPU_SLEEP_PREPARE() -#endif // NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED - - -#if NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED - #undef PWR_MGMT_SLEEP_IN_CRITICAL_SECTION_REQUIRED - #define PWR_MGMT_SLEEP_IN_CRITICAL_SECTION_REQUIRED - - #include "nrf_gpio.h" - #define PWR_MGMT_DEBUG_PINS_INIT() pwr_mgmt_debug_pins_init() - #define PWR_MGMT_DEBUG_PIN_CLEAR() nrf_gpio_pin_clear(NRF_PWR_MGMT_SLEEP_DEBUG_PIN) - #define PWR_MGMT_DEBUG_PIN_SET() nrf_gpio_pin_set(NRF_PWR_MGMT_SLEEP_DEBUG_PIN) - - __STATIC_INLINE void pwr_mgmt_debug_pins_init(void) - { - nrf_gpio_pin_clear(NRF_PWR_MGMT_SLEEP_DEBUG_PIN); - nrf_gpio_cfg_output(NRF_PWR_MGMT_SLEEP_DEBUG_PIN); - } - -#else - #define PWR_MGMT_DEBUG_PIN_CLEAR() - #define PWR_MGMT_DEBUG_PIN_SET() - #define PWR_MGMT_DEBUG_PINS_INIT() -#endif - - -#if NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED - #undef PWR_MGMT_SLEEP_IN_CRITICAL_SECTION_REQUIRED - #define PWR_MGMT_SLEEP_IN_CRITICAL_SECTION_REQUIRED - - #undef PWR_MGMT_TIMER_REQUIRED - #define PWR_MGMT_TIMER_REQUIRED - #include "app_timer.h" - - #define PWR_MGMT_CPU_USAGE_MONITOR_INIT() pwr_mgmt_cpu_usage_monitor_init() - #define PWR_MGMT_CPU_USAGE_MONITOR_UPDATE() pwr_mgmt_cpu_usage_monitor_update() - #define PWR_MGMT_CPU_USAGE_MONITOR_SUMMARY() NRF_LOG_INFO("Maximum CPU usage: %u%%", \ - m_max_cpu_usage) - #define PWR_MGMT_CPU_USAGE_MONITOR_SECTION_ENTER() \ - { \ - uint32_t sleep_start = app_timer_cnt_get() - - #define PWR_MGMT_CPU_USAGE_MONITOR_SECTION_EXIT() \ - uint32_t sleep_end = app_timer_cnt_get(); \ - uint32_t sleep_duration; \ - sleep_duration = app_timer_cnt_diff_compute(sleep_end, \ - sleep_start); \ - m_ticks_sleeping += sleep_duration; \ - } - - static uint32_t m_ticks_sleeping; /**< Number of ticks spent in sleep mode (__WFE()). */ - static uint32_t m_ticks_last; /**< Number of ticks from the last CPU usage computation. */ - static uint8_t m_max_cpu_usage; /**< Maximum observed CPU usage (0 - 100%). */ - - __STATIC_INLINE void pwr_mgmt_cpu_usage_monitor_init(void) - { - m_ticks_sleeping = 0; - m_ticks_last = 0; - m_max_cpu_usage = 0; - } - - __STATIC_INLINE void pwr_mgmt_cpu_usage_monitor_update(void) - { - uint32_t delta; - uint32_t ticks; - uint8_t cpu_usage; - - ticks = app_timer_cnt_get(); - delta = app_timer_cnt_diff_compute(ticks, m_ticks_last); - cpu_usage = 100 * (delta - m_ticks_sleeping) / delta; - - NRF_LOG_INFO("CPU Usage: %u%%", cpu_usage); - if (m_max_cpu_usage < cpu_usage) - { - m_max_cpu_usage = cpu_usage; - } - - m_ticks_last = ticks; - m_ticks_sleeping = 0; - } - -#else - #define PWR_MGMT_CPU_USAGE_MONITOR_INIT() - #define PWR_MGMT_CPU_USAGE_MONITOR_UPDATE() - #define PWR_MGMT_CPU_USAGE_MONITOR_SUMMARY() - #define PWR_MGMT_CPU_USAGE_MONITOR_SECTION_ENTER() - #define PWR_MGMT_CPU_USAGE_MONITOR_SECTION_EXIT() -#endif // NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED - - -#if NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED - #undef PWR_MGMT_TIMER_REQUIRED - #define PWR_MGMT_TIMER_REQUIRED - - #define PWR_MGMT_STANDBY_TIMEOUT_INIT() pwr_mgmt_standby_timeout_clear() - #define PWR_MGMT_STANDBY_TIMEOUT_CLEAR() pwr_mgmt_standby_timeout_clear() - #define PWR_MGMT_STANDBY_TIMEOUT_CHECK() pwr_mgmt_standby_timeout_check() - - static uint16_t m_standby_counter; /**< Number of seconds from the last activity - (@ref pwr_mgmt_feed). */ - - __STATIC_INLINE void pwr_mgmt_standby_timeout_clear(void) - { - m_standby_counter = 0; - } - - __STATIC_INLINE void pwr_mgmt_standby_timeout_check(void) - { - if (m_standby_counter < NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S) - { - m_standby_counter++; - } - else if (m_shutdown_started == false) - { - nrf_pwr_mgmt_shutdown(NRF_PWR_MGMT_SHUTDOWN_GOTO_SYSOFF); - } - } - -#else - #define PWR_MGMT_STANDBY_TIMEOUT_INIT() - #define PWR_MGMT_STANDBY_TIMEOUT_CLEAR() - #define PWR_MGMT_STANDBY_TIMEOUT_CHECK() -#endif // NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED - - -#if NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY - #undef PWR_MGMT_TIMER_REQUIRED - #define PWR_MGMT_TIMER_REQUIRED - - #define PWR_MGMT_AUTO_SHUTDOWN_RETRY() pwr_mgmt_auto_shutdown_retry() - - __STATIC_INLINE void pwr_mgmt_auto_shutdown_retry(void) - { - if (m_shutdown_started) - { - // Try to continue the shutdown procedure. - nrf_pwr_mgmt_shutdown(NRF_PWR_MGMT_SHUTDOWN_CONTINUE); - } - } - -#else - #define PWR_MGMT_AUTO_SHUTDOWN_RETRY() -#endif // NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY - - -#ifdef PWR_MGMT_SLEEP_IN_CRITICAL_SECTION_REQUIRED - #define PWR_MGMT_SLEEP_INIT() pwr_mgmt_sleep_init() - #define PWR_MGMT_SLEEP_LOCK_ACQUIRE() CRITICAL_REGION_ENTER() - #define PWR_MGMT_SLEEP_LOCK_RELEASE() CRITICAL_REGION_EXIT() - - __STATIC_INLINE void pwr_mgmt_sleep_init(void) - { - #ifdef SOFTDEVICE_PRESENT - ASSERT(current_int_priority_get() >= APP_IRQ_PRIORITY_LOW); - #endif - SCB->SCR |= SCB_SCR_SEVONPEND_Msk; - } - -#else - #define PWR_MGMT_SLEEP_INIT() - #define PWR_MGMT_SLEEP_LOCK_ACQUIRE() - #define PWR_MGMT_SLEEP_LOCK_RELEASE() -#endif // PWR_MGMT_SLEEP_IN_CRITICAL_SECTION_REQUIRED - - -#ifdef PWR_MGMT_TIMER_REQUIRED - #include "app_timer.h" - #define PWR_MGMT_TIMER_CREATE() pwr_mgmt_timer_create() - - APP_TIMER_DEF(m_pwr_mgmt_timer); /**< Timer used by this module. */ - - /**@brief Handle events from m_pwr_mgmt_timer. - */ - static void nrf_pwr_mgmt_timeout_handler(void * p_context) - { - PWR_MGMT_CPU_USAGE_MONITOR_UPDATE(); - PWR_MGMT_AUTO_SHUTDOWN_RETRY(); - PWR_MGMT_STANDBY_TIMEOUT_CHECK(); - } - - __STATIC_INLINE ret_code_t pwr_mgmt_timer_create(void) - { - ret_code_t ret_code = app_timer_create(&m_pwr_mgmt_timer, - APP_TIMER_MODE_REPEATED, - nrf_pwr_mgmt_timeout_handler); - if (ret_code != NRF_SUCCESS) - { - return ret_code; - } - - return app_timer_start(m_pwr_mgmt_timer, APP_TIMER_TICKS(1000), NULL); - } -#else - #define PWR_MGMT_TIMER_CREATE() NRF_SUCCESS -#endif // PWR_MGMT_TIMER_REQUIRED - -ret_code_t nrf_pwr_mgmt_init(void) -{ - NRF_LOG_INFO("Init"); - - m_shutdown_started = false; - nrf_mtx_init(&m_sysoff_mtx); - nrf_section_iter_init(&m_handlers_iter, &pwr_mgmt_data); - - PWR_MGMT_SLEEP_INIT(); - PWR_MGMT_DEBUG_PINS_INIT(); - PWR_MGMT_STANDBY_TIMEOUT_INIT(); - PWR_MGMT_CPU_USAGE_MONITOR_INIT(); - - return PWR_MGMT_TIMER_CREATE(); -} - -void nrf_pwr_mgmt_run(void) -{ - PWR_MGMT_FPU_SLEEP_PREPARE(); - PWR_MGMT_SLEEP_LOCK_ACQUIRE(); - PWR_MGMT_CPU_USAGE_MONITOR_SECTION_ENTER(); - PWR_MGMT_DEBUG_PIN_SET(); - - // Wait for an event. -#ifdef SOFTDEVICE_PRESENT - if (nrf_sdh_is_enabled()) - { - ret_code_t ret_code = sd_app_evt_wait(); - ASSERT((ret_code == NRF_SUCCESS) || (ret_code == NRF_ERROR_SOFTDEVICE_NOT_ENABLED)); - UNUSED_VARIABLE(ret_code); - } - else -#endif // SOFTDEVICE_PRESENT - { - // Wait for an event. - __WFE(); - // Clear the internal event register. - __SEV(); - __WFE(); - } - - PWR_MGMT_DEBUG_PIN_CLEAR(); - PWR_MGMT_CPU_USAGE_MONITOR_SECTION_EXIT(); - PWR_MGMT_SLEEP_LOCK_RELEASE(); -} - -void nrf_pwr_mgmt_feed(void) -{ - NRF_LOG_DEBUG("Feed"); - // It does not stop started shutdown process. - PWR_MGMT_STANDBY_TIMEOUT_CLEAR(); -} - -/**@brief Function runs the shutdown procedure. - */ -static void shutdown_process(void) -{ - NRF_LOG_INFO("Shutdown started. Type %d", m_pwr_mgmt_evt); - // Executing all callbacks. - for (/* m_handlers_iter is initialized in nrf_pwr_mgmt_init(). Thanks to that each handler is - called only once.*/; - nrf_section_iter_get(&m_handlers_iter) != NULL; - nrf_section_iter_next(&m_handlers_iter)) - { - nrf_pwr_mgmt_shutdown_handler_t * p_handler = - (nrf_pwr_mgmt_shutdown_handler_t *) nrf_section_iter_get(&m_handlers_iter); - if ((*p_handler)(m_pwr_mgmt_evt)) - { - NRF_LOG_INFO("SysOff handler 0x%08X => ready", (unsigned int)*p_handler); - } - else - { - // One of the modules is not ready. - NRF_LOG_INFO("SysOff handler 0x%08X => blocking", (unsigned int)*p_handler); - return; - } - } - - PWR_MGMT_CPU_USAGE_MONITOR_SUMMARY(); - NRF_LOG_INFO("Shutdown complete."); - NRF_LOG_FINAL_FLUSH(); - - if ((m_pwr_mgmt_evt == NRF_PWR_MGMT_EVT_PREPARE_RESET) - || (m_pwr_mgmt_evt == NRF_PWR_MGMT_EVT_PREPARE_DFU)) - { - NVIC_SystemReset(); - } - else - { - // Enter System OFF. -#ifdef SOFTDEVICE_PRESENT - if (nrf_sdh_is_enabled()) - { - ret_code_t ret_code = sd_power_system_off(); - ASSERT((ret_code == NRF_SUCCESS) || (ret_code == NRF_ERROR_SOFTDEVICE_NOT_ENABLED)); - UNUSED_VARIABLE(ret_code); - } -#endif // SOFTDEVICE_PRESENT - nrf_power_system_off(); - } -} - -#if NRF_PWR_MGMT_CONFIG_USE_SCHEDULER -/**@brief Handle events from app_scheduler. - */ -static void scheduler_shutdown_handler(void * p_event_data, uint16_t event_size) -{ - UNUSED_PARAMETER(p_event_data); - UNUSED_PARAMETER(event_size); - shutdown_process(); -} -#endif // NRF_PWR_MGMT_CONFIG_USE_SCHEDULER - -void nrf_pwr_mgmt_shutdown(nrf_pwr_mgmt_shutdown_t shutdown_type) -{ - // Check if shutdown procedure is not started. - if (!nrf_mtx_trylock(&m_sysoff_mtx)) - { - return; - } - - if (shutdown_type != NRF_PWR_MGMT_SHUTDOWN_CONTINUE) - { - if (m_shutdown_started) - { - nrf_mtx_unlock(&m_sysoff_mtx); - return; - } - else - { - m_pwr_mgmt_evt = (nrf_pwr_mgmt_evt_t)shutdown_type; - m_shutdown_started = true; - } - } - - ASSERT(m_shutdown_started); - NRF_LOG_INFO("Shutdown request %d", shutdown_type); - -#if NRF_PWR_MGMT_CONFIG_USE_SCHEDULER - ret_code_t ret_code = app_sched_event_put(NULL, 0, scheduler_shutdown_handler); - APP_ERROR_CHECK(ret_code); -#else - shutdown_process(); -#endif // NRF_PWR_MGMT_CONFIG_USE_SCHEDULER - - nrf_mtx_unlock(&m_sysoff_mtx); -} - -#endif // NRF_MODULE_ENABLED(NRF_PWR_MGMT) diff --git a/bsp/boards/nrf52840/sdk/components/libraries/pwr_mgmt/nrf_pwr_mgmt.h b/bsp/boards/nrf52840/sdk/components/libraries/pwr_mgmt/nrf_pwr_mgmt.h deleted file mode 100644 index 5b24f13974..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/pwr_mgmt/nrf_pwr_mgmt.h +++ /dev/null @@ -1,150 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -/** - * @defgroup nrf_pwr_mgmt Power management - * @ingroup app_common - * @{ - * @brief This module handles power management features. - * - */ -#ifndef NRF_PWR_MGMT_H__ -#define NRF_PWR_MGMT_H__ - -#include -#include -#include -#include "nrf_section_iter.h" - -/**@brief Power management shutdown types. */ -typedef enum -{ - NRF_PWR_MGMT_SHUTDOWN_GOTO_SYSOFF, - //!< Go to System OFF. - - NRF_PWR_MGMT_SHUTDOWN_STAY_IN_SYSOFF, - //!< Go to System OFF and stay there. - /**< - * Useful when battery level is dangerously low, for example. - */ - - NRF_PWR_MGMT_SHUTDOWN_GOTO_DFU, - //!< Go to DFU mode. - - NRF_PWR_MGMT_SHUTDOWN_RESET, - //!< Reset chip. - - NRF_PWR_MGMT_SHUTDOWN_CONTINUE - //!< Continue shutdown. - /**< - * This should be used by modules that block the shutdown process, when they become ready for - * shutdown. - */ -} nrf_pwr_mgmt_shutdown_t; - -/**@brief Shutdown event types. */ -typedef enum -{ - NRF_PWR_MGMT_EVT_PREPARE_WAKEUP = NRF_PWR_MGMT_SHUTDOWN_GOTO_SYSOFF, - //!< Application will prepare the wakeup mechanism. - - NRF_PWR_MGMT_EVT_PREPARE_SYSOFF = NRF_PWR_MGMT_SHUTDOWN_STAY_IN_SYSOFF, - //!< Application will prepare to stay in System OFF state. - - NRF_PWR_MGMT_EVT_PREPARE_DFU = NRF_PWR_MGMT_SHUTDOWN_GOTO_DFU, - //!< Application will prepare to enter DFU mode. - - NRF_PWR_MGMT_EVT_PREPARE_RESET = NRF_PWR_MGMT_SHUTDOWN_RESET, - //!< Application will prepare to chip reset. -} nrf_pwr_mgmt_evt_t; - -/**@brief Shutdown callback. - * @param[in] event Type of shutdown process. - * - * @retval true System OFF / Enter DFU preparation successful. Process will be continued. - * @retval false System OFF / Enter DFU preparation failed. @ref NRF_PWR_MGMT_SHUTDOWN_CONTINUE - * should be used to continue the shutdown process. - */ -typedef bool (*nrf_pwr_mgmt_shutdown_handler_t)(nrf_pwr_mgmt_evt_t event); - -/**@brief Macro for registering a shutdown handler. Modules that want to get events - * from this module must register the handler using this macro. - * - * @details This macro places the handler in a section named "pwr_mgmt_data". - * - * @param[in] _handler Event handler (@ref nrf_pwr_mgmt_shutdown_handler_t). - * @param[in] _priority Priority of the given handler. - */ -#define NRF_PWR_MGMT_HANDLER_REGISTER(_handler, _priority) \ - STATIC_ASSERT(_priority < NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT); \ - /*lint -esym(528,*_handler_function) -esym(529,*_handler_function) : Symbol not referenced. */ \ - NRF_SECTION_SET_ITEM_REGISTER(pwr_mgmt_data, _priority, \ - static nrf_pwr_mgmt_shutdown_handler_t const CONCAT_2(_handler, _handler_function)) = (_handler) - -/**@brief Function for initializing power management. - * - * @warning Depending on configuration, this function sets SEVONPEND in System Control Block (SCB). - * This operation is unsafe with the SoftDevice from interrupt priority higher than SVC. - * - * @retval NRF_SUCCESS - */ -ret_code_t nrf_pwr_mgmt_init(void); - -/**@brief Function for running power management. Should run in the main loop. - */ -void nrf_pwr_mgmt_run(void); - -/**@brief Function for indicating activity. - * - * @details Call this function whenever doing something that constitutes "activity". - * For example, whenever sending data, call this function to indicate that the application - * is active and should not disconnect any ongoing communication links. - */ -void nrf_pwr_mgmt_feed(void); - -/**@brief Function for shutting down the system. - * - * @param[in] shutdown_type Type of operation. - * - * @details All callbacks will be executed prior to shutdown. - */ -void nrf_pwr_mgmt_shutdown(nrf_pwr_mgmt_shutdown_t shutdown_type); - -#endif // NRF_PWR_MGMT_H__ -/** @} */ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/strerror/nrf_strerror.c b/bsp/boards/nrf52840/sdk/components/libraries/strerror/nrf_strerror.c deleted file mode 100644 index f20f55bcaa..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/strerror/nrf_strerror.c +++ /dev/null @@ -1,161 +0,0 @@ -/** - * Copyright (c) 2011 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include "sdk_common.h" -#if NRF_MODULE_ENABLED(NRF_STRERROR) -#include "nrf_strerror.h" - -/** - * @brief Macro for adding an entity to the description array. - * - * Macro that helps to create a single entity in the description array. - */ -#define NRF_STRERROR_ENTITY(mnemonic) {.code = mnemonic, .name = #mnemonic} - -/** - * @brief Array entity element that describes an error. - */ -typedef struct -{ - ret_code_t code; /**< Error code. */ - char const * name; /**< Descriptive name (the same as the internal error mnemonic). */ -}nrf_strerror_desc_t; - -/** - * @brief Unknown error code. - * - * The constant string used by @ref nrf_strerror_get when the error description was not found. - */ -static char const m_unknown_str[] = "Unknown error code"; - -/** - * @brief Array with error codes. - * - * Array that describes error codes. - * - * @note It is required for this array to have error codes placed in ascending order. - * This condition is checked in automatic unit test before the release. - */ -static nrf_strerror_desc_t const nrf_strerror_array[] = -{ - NRF_STRERROR_ENTITY(NRF_SUCCESS), - NRF_STRERROR_ENTITY(NRF_ERROR_SVC_HANDLER_MISSING), - NRF_STRERROR_ENTITY(NRF_ERROR_SOFTDEVICE_NOT_ENABLED), - NRF_STRERROR_ENTITY(NRF_ERROR_INTERNAL), - NRF_STRERROR_ENTITY(NRF_ERROR_NO_MEM), - NRF_STRERROR_ENTITY(NRF_ERROR_NOT_FOUND), - NRF_STRERROR_ENTITY(NRF_ERROR_NOT_SUPPORTED), - NRF_STRERROR_ENTITY(NRF_ERROR_INVALID_PARAM), - NRF_STRERROR_ENTITY(NRF_ERROR_INVALID_STATE), - NRF_STRERROR_ENTITY(NRF_ERROR_INVALID_LENGTH), - NRF_STRERROR_ENTITY(NRF_ERROR_INVALID_FLAGS), - NRF_STRERROR_ENTITY(NRF_ERROR_INVALID_DATA), - NRF_STRERROR_ENTITY(NRF_ERROR_DATA_SIZE), - NRF_STRERROR_ENTITY(NRF_ERROR_TIMEOUT), - NRF_STRERROR_ENTITY(NRF_ERROR_NULL), - NRF_STRERROR_ENTITY(NRF_ERROR_FORBIDDEN), - NRF_STRERROR_ENTITY(NRF_ERROR_INVALID_ADDR), - NRF_STRERROR_ENTITY(NRF_ERROR_BUSY), -#ifdef NRF_ERROR_CONN_COUNT - NRF_STRERROR_ENTITY(NRF_ERROR_CONN_COUNT), -#endif -#ifdef NRF_ERROR_RESOURCES - NRF_STRERROR_ENTITY(NRF_ERROR_RESOURCES), -#endif - - /* SDK Common errors */ - NRF_STRERROR_ENTITY(NRF_ERROR_MODULE_NOT_INITIALIZED), - NRF_STRERROR_ENTITY(NRF_ERROR_MUTEX_INIT_FAILED), - NRF_STRERROR_ENTITY(NRF_ERROR_MUTEX_LOCK_FAILED), - NRF_STRERROR_ENTITY(NRF_ERROR_MUTEX_UNLOCK_FAILED), - NRF_STRERROR_ENTITY(NRF_ERROR_MUTEX_COND_INIT_FAILED), - NRF_STRERROR_ENTITY(NRF_ERROR_MODULE_ALREADY_INITIALIZED), - NRF_STRERROR_ENTITY(NRF_ERROR_STORAGE_FULL), - NRF_STRERROR_ENTITY(NRF_ERROR_API_NOT_IMPLEMENTED), - NRF_STRERROR_ENTITY(NRF_ERROR_FEATURE_NOT_ENABLED), - NRF_STRERROR_ENTITY(NRF_ERROR_IO_PENDING), - - /* TWI error codes */ - NRF_STRERROR_ENTITY(NRF_ERROR_DRV_TWI_ERR_OVERRUN), - NRF_STRERROR_ENTITY(NRF_ERROR_DRV_TWI_ERR_ANACK), - NRF_STRERROR_ENTITY(NRF_ERROR_DRV_TWI_ERR_DNACK), - - /* IPSP error codes */ - NRF_STRERROR_ENTITY(NRF_ERROR_BLE_IPSP_RX_PKT_TRUNCATED), - NRF_STRERROR_ENTITY(NRF_ERROR_BLE_IPSP_CHANNEL_ALREADY_EXISTS), - NRF_STRERROR_ENTITY(NRF_ERROR_BLE_IPSP_LINK_DISCONNECTED), - NRF_STRERROR_ENTITY(NRF_ERROR_BLE_IPSP_PEER_REJECTED) -}; - - -char const * nrf_strerror_get(ret_code_t code) -{ - char const * p_ret = nrf_strerror_find(code); - return (p_ret == NULL) ? m_unknown_str : p_ret; -} - -char const * nrf_strerror_find(ret_code_t code) -{ - nrf_strerror_desc_t const * p_start; - nrf_strerror_desc_t const * p_end; - p_start = nrf_strerror_array; - p_end = nrf_strerror_array + ARRAY_SIZE(nrf_strerror_array); - - while (p_start < p_end) - { - nrf_strerror_desc_t const * p_mid = p_start + ((p_end - p_start) / 2); - ret_code_t mid_c = p_mid->code; - if (mid_c > code) - { - p_end = p_mid; - } - else if (mid_c < code) - { - p_start = p_mid + 1; - } - else - { - return p_mid->name; - } - } - return NULL; -} - -#endif /* NRF_STRERROR enabled */ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/strerror/nrf_strerror.h b/bsp/boards/nrf52840/sdk/components/libraries/strerror/nrf_strerror.h deleted file mode 100644 index 44419f58e1..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/strerror/nrf_strerror.h +++ /dev/null @@ -1,89 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/** - * @defgroup nrf_strerror Error code to string converter - * @ingroup app_common - * - * @brief Module for converting error code into a printable string. - * @{ - */ -#ifndef NRF_STRERROR_H__ -#define NRF_STRERROR_H__ - -#include "sdk_errors.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Function for getting a printable error string. - * - * @param code Error code to convert. - * - * @note This function cannot fail. - * For the function that may fail with error translation, see @ref nrf_strerror_find. - * - * @return Pointer to the printable string. - * If the string is not found, - * it returns a simple string that says that the error is unknown. - */ -char const * nrf_strerror_get(ret_code_t code); - -/** - * @brief Function for finding a printable error string. - * - * This function gets the error string in the same way as @ref nrf_strerror_get, - * but if the string is not found, it returns NULL. - * - * @param code Error code to convert. - * @return Pointer to the printable string. - * If the string is not found, NULL is returned. - */ -char const * nrf_strerror_find(ret_code_t code); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* NRF_STRERROR_H__ */ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/uart/app_uart.c b/bsp/boards/nrf52840/sdk/components/libraries/uart/app_uart.c deleted file mode 100644 index c777ae2285..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/uart/app_uart.c +++ /dev/null @@ -1,160 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include "sdk_common.h" -#if NRF_MODULE_ENABLED(APP_UART) -#include "app_uart.h" -#include "nrf_drv_uart.h" -#include "nrf_assert.h" - -static uint8_t tx_buffer[1]; -static uint8_t rx_buffer[1]; -static volatile bool rx_done; -static app_uart_event_handler_t m_event_handler; /**< Event handler function. */ -static nrf_drv_uart_t app_uart_inst = NRF_DRV_UART_INSTANCE(APP_UART_DRIVER_INSTANCE); - -static void uart_event_handler(nrf_drv_uart_event_t * p_event, void* p_context) -{ - if (p_event->type == NRF_DRV_UART_EVT_RX_DONE) - { - app_uart_evt_t app_uart_event; - app_uart_event.evt_type = APP_UART_DATA; - app_uart_event.data.value = p_event->data.rxtx.p_data[0]; - (void)nrf_drv_uart_rx(&app_uart_inst, rx_buffer, 1); - rx_done = true; - m_event_handler(&app_uart_event); - } - else if (p_event->type == NRF_DRV_UART_EVT_ERROR) - { - app_uart_evt_t app_uart_event; - app_uart_event.evt_type = APP_UART_COMMUNICATION_ERROR; - app_uart_event.data.error_communication = p_event->data.error.error_mask; - (void)nrf_drv_uart_rx(&app_uart_inst, rx_buffer, 1); - m_event_handler(&app_uart_event); - } - else if (p_event->type == NRF_DRV_UART_EVT_TX_DONE) - { - // Last byte from FIFO transmitted, notify the application. - // Notify that new data is available if this was first byte put in the buffer. - app_uart_evt_t app_uart_event; - app_uart_event.evt_type = APP_UART_TX_EMPTY; - m_event_handler(&app_uart_event); - } -} - -uint32_t app_uart_init(const app_uart_comm_params_t * p_comm_params, - app_uart_buffers_t * p_buffers, - app_uart_event_handler_t event_handler, - app_irq_priority_t irq_priority) -{ - nrf_drv_uart_config_t config = NRF_DRV_UART_DEFAULT_CONFIG; - config.baudrate = (nrf_uart_baudrate_t)p_comm_params->baud_rate; - config.hwfc = (p_comm_params->flow_control == APP_UART_FLOW_CONTROL_DISABLED) ? - NRF_UART_HWFC_DISABLED : NRF_UART_HWFC_ENABLED; - config.interrupt_priority = irq_priority; - config.parity = p_comm_params->use_parity ? NRF_UART_PARITY_INCLUDED : NRF_UART_PARITY_EXCLUDED; - config.pselcts = p_comm_params->cts_pin_no; - config.pselrts = p_comm_params->rts_pin_no; - config.pselrxd = p_comm_params->rx_pin_no; - config.pseltxd = p_comm_params->tx_pin_no; - - m_event_handler = event_handler; - - rx_done = false; - - uint32_t err_code = nrf_drv_uart_init(&app_uart_inst, &config, uart_event_handler); - VERIFY_SUCCESS(err_code); - - // Turn on receiver if RX pin is connected - if (p_comm_params->rx_pin_no != UART_PIN_DISCONNECTED) - { - return nrf_drv_uart_rx(&app_uart_inst, rx_buffer,1); - } - else - { - return NRF_SUCCESS; - } -} - - -uint32_t app_uart_get(uint8_t * p_byte) -{ - ASSERT(p_byte); - uint32_t err_code = NRF_SUCCESS; - if (rx_done) - { - *p_byte = rx_buffer[0]; - rx_done = false; - } - else - { - err_code = NRF_ERROR_NOT_FOUND; - } - return err_code; -} - -uint32_t app_uart_put(uint8_t byte) -{ - tx_buffer[0] = byte; - ret_code_t ret = nrf_drv_uart_tx(&app_uart_inst, tx_buffer, 1); - if (NRF_ERROR_BUSY == ret) - { - return NRF_ERROR_NO_MEM; - } - else if (ret != NRF_SUCCESS) - { - return NRF_ERROR_INTERNAL; - } - else - { - return NRF_SUCCESS; - } -} - -uint32_t app_uart_flush(void) -{ - return NRF_SUCCESS; -} - -uint32_t app_uart_close(void) -{ - nrf_drv_uart_uninit(&app_uart_inst); - return NRF_SUCCESS; -} -#endif //NRF_MODULE_ENABLED(APP_UART) diff --git a/bsp/boards/nrf52840/sdk/components/libraries/uart/app_uart.h b/bsp/boards/nrf52840/sdk/components/libraries/uart/app_uart.h deleted file mode 100644 index 7935cf2bb2..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/uart/app_uart.h +++ /dev/null @@ -1,262 +0,0 @@ -/** - * Copyright (c) 2013 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -/**@file - * - * @defgroup app_uart UART module - * @{ - * @ingroup app_common - * - * @brief UART module interface. - */ - -#ifndef APP_UART_H__ -#define APP_UART_H__ - -#include -#include -#include "app_util_platform.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define UART_PIN_DISCONNECTED 0xFFFFFFFF /**< Value indicating that no pin is connected to this UART register. */ - -/**@brief UART Flow Control modes for the peripheral. - */ -typedef enum -{ - APP_UART_FLOW_CONTROL_DISABLED, /**< UART Hw Flow Control is disabled. */ - APP_UART_FLOW_CONTROL_ENABLED, /**< Standard UART Hw Flow Control is enabled. */ -} app_uart_flow_control_t; - -/**@brief UART communication structure holding configuration settings for the peripheral. - */ -typedef struct -{ - uint32_t rx_pin_no; /**< RX pin number. */ - uint32_t tx_pin_no; /**< TX pin number. */ - uint32_t rts_pin_no; /**< RTS pin number, only used if flow control is enabled. */ - uint32_t cts_pin_no; /**< CTS pin number, only used if flow control is enabled. */ - app_uart_flow_control_t flow_control; /**< Flow control setting, if flow control is used, the system will use low power UART mode, based on CTS signal. */ - bool use_parity; /**< Even parity if TRUE, no parity if FALSE. */ - uint32_t baud_rate; /**< Baud rate configuration. */ -} app_uart_comm_params_t; - -/**@brief UART buffer for transmitting/receiving data. - */ -typedef struct -{ - uint8_t * rx_buf; /**< Pointer to the RX buffer. */ - uint32_t rx_buf_size; /**< Size of the RX buffer. */ - uint8_t * tx_buf; /**< Pointer to the TX buffer. */ - uint32_t tx_buf_size; /**< Size of the TX buffer. */ -} app_uart_buffers_t; - -/**@brief Enumeration which defines events used by the UART module upon data reception or error. - * - * @details The event type is used to indicate the type of additional information in the event - * @ref app_uart_evt_t. - */ -typedef enum -{ - APP_UART_DATA_READY, /**< An event indicating that UART data has been received. The data is available in the FIFO and can be fetched using @ref app_uart_get. */ - APP_UART_FIFO_ERROR, /**< An error in the FIFO module used by the app_uart module has occured. The FIFO error code is stored in app_uart_evt_t.data.error_code field. */ - APP_UART_COMMUNICATION_ERROR, /**< An communication error has occured during reception. The error is stored in app_uart_evt_t.data.error_communication field. */ - APP_UART_TX_EMPTY, /**< An event indicating that UART has completed transmission of all available data in the TX FIFO. */ - APP_UART_DATA, /**< An event indicating that UART data has been received, and data is present in data field. This event is only used when no FIFO is configured. */ -} app_uart_evt_type_t; - -/**@brief Struct containing events from the UART module. - * - * @details The app_uart_evt_t is used to notify the application of asynchronous events when data - * are received on the UART peripheral or in case an error occured during data reception. - */ -typedef struct -{ - app_uart_evt_type_t evt_type; /**< Type of event. */ - union - { - uint32_t error_communication; /**< Field used if evt_type is: APP_UART_COMMUNICATION_ERROR. This field contains the value in the ERRORSRC register for the UART peripheral. The UART_ERRORSRC_x defines from nrf5x_bitfields.h can be used to parse the error code. See also the \nRFXX Series Reference Manual for specification. */ - uint32_t error_code; /**< Field used if evt_type is: NRF_ERROR_x. Additional status/error code if the error event type is APP_UART_FIFO_ERROR. This error code refer to errors defined in nrf_error.h. */ - uint8_t value; /**< Field used if evt_type is: NRF_ERROR_x. Additional status/error code if the error event type is APP_UART_FIFO_ERROR. This error code refer to errors defined in nrf_error.h. */ - } data; -} app_uart_evt_t; - -/**@brief Function for handling app_uart event callback. - * - * @details Upon an event in the app_uart module this callback function will be called to notify - * the application about the event. - * - * @param[in] p_app_uart_event Pointer to UART event. - */ -typedef void (* app_uart_event_handler_t) (app_uart_evt_t * p_app_uart_event); - -/**@brief Macro for safe initialization of the UART module in a single user instance when using - * a FIFO together with UART. - * - * @param[in] P_COMM_PARAMS Pointer to a UART communication structure: app_uart_comm_params_t - * @param[in] RX_BUF_SIZE Size of desired RX buffer, must be a power of 2 or ZERO (No FIFO). - * @param[in] TX_BUF_SIZE Size of desired TX buffer, must be a power of 2 or ZERO (No FIFO). - * @param[in] EVT_HANDLER Event handler function to be called when an event occurs in the - * UART module. - * @param[in] IRQ_PRIO IRQ priority, app_irq_priority_t, for the UART module irq handler. - * @param[out] ERR_CODE The return value of the UART initialization function will be - * written to this parameter. - * - * @note Since this macro allocates a buffer and registers the module as a GPIOTE user when flow - * control is enabled, it must only be called once. - */ -#define APP_UART_FIFO_INIT(P_COMM_PARAMS, RX_BUF_SIZE, TX_BUF_SIZE, EVT_HANDLER, IRQ_PRIO, ERR_CODE) \ - do \ - { \ - app_uart_buffers_t buffers; \ - static uint8_t rx_buf[RX_BUF_SIZE]; \ - static uint8_t tx_buf[TX_BUF_SIZE]; \ - \ - buffers.rx_buf = rx_buf; \ - buffers.rx_buf_size = sizeof (rx_buf); \ - buffers.tx_buf = tx_buf; \ - buffers.tx_buf_size = sizeof (tx_buf); \ - ERR_CODE = app_uart_init(P_COMM_PARAMS, &buffers, EVT_HANDLER, IRQ_PRIO); \ - } while (0) - -/**@brief Macro for safe initialization of the UART module in a single user instance. - * - * @param[in] P_COMM_PARAMS Pointer to a UART communication structure: app_uart_comm_params_t - * @param[in] EVT_HANDLER Event handler function to be called when an event occurs in the - * UART module. - * @param[in] IRQ_PRIO IRQ priority, app_irq_priority_t, for the UART module irq handler. - * @param[out] ERR_CODE The return value of the UART initialization function will be - * written to this parameter. - * - * @note Since this macro allocates registers the module as a GPIOTE user when flow control is - * enabled, it must only be called once. - */ -#define APP_UART_INIT(P_COMM_PARAMS, EVT_HANDLER, IRQ_PRIO, ERR_CODE) \ - do \ - { \ - ERR_CODE = app_uart_init(P_COMM_PARAMS, NULL, EVT_HANDLER, IRQ_PRIO); \ - } while (0) - -/**@brief Function for initializing the UART module. Use this initialization when several instances of the UART - * module are needed. - * - * - * @note Normally single initialization should be done using the APP_UART_INIT() or - * APP_UART_INIT_FIFO() macro depending on whether the FIFO should be used by the UART, as - * that will allocate the buffers needed by the UART module (including aligning the buffer - * correctly). - - * @param[in] p_comm_params Pin and communication parameters. - * @param[in] p_buffers RX and TX buffers, NULL is FIFO is not used. - * @param[in] error_handler Function to be called in case of an error. - * @param[in] irq_priority Interrupt priority level. - * - * @retval NRF_SUCCESS If successful initialization. - * @retval NRF_ERROR_INVALID_LENGTH If a provided buffer is not a power of two. - * @retval NRF_ERROR_NULL If one of the provided buffers is a NULL pointer. - * - * The below errors are propagated by the UART module to the caller upon registration when Hardware - * Flow Control is enabled. When Hardware Flow Control is not used, these errors cannot occur. - * @retval NRF_ERROR_INVALID_STATE The GPIOTE module is not in a valid state when registering - * the UART module as a user. - * @retval NRF_ERROR_INVALID_PARAM The UART module provides an invalid callback function when - * registering the UART module as a user. - * Or the value pointed to by *p_uart_uid is not a valid - * GPIOTE number. - * @retval NRF_ERROR_NO_MEM GPIOTE module has reached the maximum number of users. - */ -uint32_t app_uart_init(const app_uart_comm_params_t * p_comm_params, - app_uart_buffers_t * p_buffers, - app_uart_event_handler_t error_handler, - app_irq_priority_t irq_priority); - -/**@brief Function for getting a byte from the UART. - * - * @details This function will get the next byte from the RX buffer. If the RX buffer is empty - * an error code will be returned and the app_uart module will generate an event upon - * reception of the first byte which is added to the RX buffer. - * - * @param[out] p_byte Pointer to an address where next byte received on the UART will be copied. - * - * @retval NRF_SUCCESS If a byte has been received and pushed to the pointer provided. - * @retval NRF_ERROR_NOT_FOUND If no byte is available in the RX buffer of the app_uart module. - */ -uint32_t app_uart_get(uint8_t * p_byte); - -/**@brief Function for putting a byte on the UART. - * - * @details This call is non-blocking. - * - * @param[in] byte Byte to be transmitted on the UART. - * - * @retval NRF_SUCCESS If the byte was successfully put on the TX buffer for transmission. - * @retval NRF_ERROR_NO_MEM If no more space is available in the TX buffer. - * NRF_ERROR_NO_MEM may occur if flow control is enabled and CTS signal - * is high for a long period and the buffer fills up. - * @retval NRF_ERROR_INTERNAL If UART driver reported error. - */ -uint32_t app_uart_put(uint8_t byte); - -/**@brief Function for flushing the RX and TX buffers (Only valid if FIFO is used). - * This function does nothing if FIFO is not used. - * - * @retval NRF_SUCCESS Flushing completed (Current implementation will always succeed). - */ -uint32_t app_uart_flush(void); - -/**@brief Function for closing the UART module. - * - * @retval NRF_SUCCESS If successfully closed. - * @retval NRF_ERROR_INVALID_PARAM If an invalid user id is provided or the user id differs from - * the current active user. - */ -uint32_t app_uart_close(void); - - - -#ifdef __cplusplus -} -#endif - -#endif //APP_UART_H__ - -/** @} */ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/uart/app_uart_fifo.c b/bsp/boards/nrf52840/sdk/components/libraries/uart/app_uart_fifo.c deleted file mode 100644 index 4fb80b6123..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/uart/app_uart_fifo.c +++ /dev/null @@ -1,244 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include "sdk_common.h" -#if NRF_MODULE_ENABLED(APP_UART) -#include "app_uart.h" -#include "app_fifo.h" -#include "nrf_drv_uart.h" -#include "nrf_assert.h" - -static nrf_drv_uart_t app_uart_inst = NRF_DRV_UART_INSTANCE(APP_UART_DRIVER_INSTANCE); - -static __INLINE uint32_t fifo_length(app_fifo_t * const fifo) -{ - uint32_t tmp = fifo->read_pos; - return fifo->write_pos - tmp; -} - -#define FIFO_LENGTH(F) fifo_length(&F) /**< Macro to calculate length of a FIFO. */ - - -static app_uart_event_handler_t m_event_handler; /**< Event handler function. */ -static uint8_t tx_buffer[1]; -static uint8_t rx_buffer[1]; -static bool m_rx_ovf; - -static app_fifo_t m_rx_fifo; /**< RX FIFO buffer for storing data received on the UART until the application fetches them using app_uart_get(). */ -static app_fifo_t m_tx_fifo; /**< TX FIFO buffer for storing data to be transmitted on the UART when TXD is ready. Data is put to the buffer on using app_uart_put(). */ - -static void uart_event_handler(nrf_drv_uart_event_t * p_event, void* p_context) -{ - app_uart_evt_t app_uart_event; - uint32_t err_code; - - switch (p_event->type) - { - case NRF_DRV_UART_EVT_RX_DONE: - // Write received byte to FIFO. - err_code = app_fifo_put(&m_rx_fifo, p_event->data.rxtx.p_data[0]); - if (err_code != NRF_SUCCESS) - { - app_uart_event.evt_type = APP_UART_FIFO_ERROR; - app_uart_event.data.error_code = err_code; - m_event_handler(&app_uart_event); - } - // Notify that there are data available. - else if (FIFO_LENGTH(m_rx_fifo) != 0) - { - app_uart_event.evt_type = APP_UART_DATA_READY; - m_event_handler(&app_uart_event); - } - - // Start new RX if size in buffer. - if (FIFO_LENGTH(m_rx_fifo) <= m_rx_fifo.buf_size_mask) - { - (void)nrf_drv_uart_rx(&app_uart_inst, rx_buffer, 1); - } - else - { - // Overflow in RX FIFO. - m_rx_ovf = true; - } - - break; - - case NRF_DRV_UART_EVT_ERROR: - app_uart_event.evt_type = APP_UART_COMMUNICATION_ERROR; - app_uart_event.data.error_communication = p_event->data.error.error_mask; - (void)nrf_drv_uart_rx(&app_uart_inst, rx_buffer, 1); - m_event_handler(&app_uart_event); - break; - - case NRF_DRV_UART_EVT_TX_DONE: - // Get next byte from FIFO. - if (app_fifo_get(&m_tx_fifo, tx_buffer) == NRF_SUCCESS) - { - (void)nrf_drv_uart_tx(&app_uart_inst, tx_buffer, 1); - } - else - { - // Last byte from FIFO transmitted, notify the application. - app_uart_event.evt_type = APP_UART_TX_EMPTY; - m_event_handler(&app_uart_event); - } - break; - - default: - break; - } -} - - -uint32_t app_uart_init(const app_uart_comm_params_t * p_comm_params, - app_uart_buffers_t * p_buffers, - app_uart_event_handler_t event_handler, - app_irq_priority_t irq_priority) -{ - uint32_t err_code; - - m_event_handler = event_handler; - - if (p_buffers == NULL) - { - return NRF_ERROR_INVALID_PARAM; - } - - // Configure buffer RX buffer. - err_code = app_fifo_init(&m_rx_fifo, p_buffers->rx_buf, p_buffers->rx_buf_size); - VERIFY_SUCCESS(err_code); - - // Configure buffer TX buffer. - err_code = app_fifo_init(&m_tx_fifo, p_buffers->tx_buf, p_buffers->tx_buf_size); - VERIFY_SUCCESS(err_code); - - nrf_drv_uart_config_t config = NRF_DRV_UART_DEFAULT_CONFIG; - config.baudrate = (nrf_uart_baudrate_t)p_comm_params->baud_rate; - config.hwfc = (p_comm_params->flow_control == APP_UART_FLOW_CONTROL_DISABLED) ? - NRF_UART_HWFC_DISABLED : NRF_UART_HWFC_ENABLED; - config.interrupt_priority = irq_priority; - config.parity = p_comm_params->use_parity ? NRF_UART_PARITY_INCLUDED : NRF_UART_PARITY_EXCLUDED; - config.pselcts = p_comm_params->cts_pin_no; - config.pselrts = p_comm_params->rts_pin_no; - config.pselrxd = p_comm_params->rx_pin_no; - config.pseltxd = p_comm_params->tx_pin_no; - - err_code = nrf_drv_uart_init(&app_uart_inst, &config, uart_event_handler); - VERIFY_SUCCESS(err_code); - m_rx_ovf = false; - - // Turn on receiver if RX pin is connected - if (p_comm_params->rx_pin_no != UART_PIN_DISCONNECTED) - { - return nrf_drv_uart_rx(&app_uart_inst, rx_buffer,1); - } - else - { - return NRF_SUCCESS; - } -} - - -uint32_t app_uart_flush(void) -{ - uint32_t err_code; - - err_code = app_fifo_flush(&m_rx_fifo); - VERIFY_SUCCESS(err_code); - - err_code = app_fifo_flush(&m_tx_fifo); - VERIFY_SUCCESS(err_code); - - return NRF_SUCCESS; -} - - -uint32_t app_uart_get(uint8_t * p_byte) -{ - ASSERT(p_byte); - bool rx_ovf = m_rx_ovf; - - ret_code_t err_code = app_fifo_get(&m_rx_fifo, p_byte); - - // If FIFO was full new request to receive one byte was not scheduled. Must be done here. - if (rx_ovf) - { - m_rx_ovf = false; - uint32_t uart_err_code = nrf_drv_uart_rx(&app_uart_inst, rx_buffer, 1); - - // RX resume should never fail. - APP_ERROR_CHECK(uart_err_code); - } - - return err_code; -} - - -uint32_t app_uart_put(uint8_t byte) -{ - uint32_t err_code; - err_code = app_fifo_put(&m_tx_fifo, byte); - if (err_code == NRF_SUCCESS) - { - // The new byte has been added to FIFO. It will be picked up from there - // (in 'uart_event_handler') when all preceding bytes are transmitted. - // But if UART is not transmitting anything at the moment, we must start - // a new transmission here. - if (!nrf_drv_uart_tx_in_progress(&app_uart_inst)) - { - // This operation should be almost always successful, since we've - // just added a byte to FIFO, but if some bigger delay occurred - // (some heavy interrupt handler routine has been executed) since - // that time, FIFO might be empty already. - if (app_fifo_get(&m_tx_fifo, tx_buffer) == NRF_SUCCESS) - { - err_code = nrf_drv_uart_tx(&app_uart_inst, tx_buffer, 1); - } - } - } - return err_code; -} - - -uint32_t app_uart_close(void) -{ - nrf_drv_uart_uninit(&app_uart_inst); - return NRF_SUCCESS; -} -#endif //NRF_MODULE_ENABLED(APP_UART) diff --git a/bsp/boards/nrf52840/sdk/components/libraries/uart/retarget.c b/bsp/boards/nrf52840/sdk/components/libraries/uart/retarget.c deleted file mode 100644 index dc2882f7bf..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/uart/retarget.c +++ /dev/null @@ -1,176 +0,0 @@ -/** - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include "sdk_common.h" -/** @file - * - * @defgroup retarget Retarget layer for stdio functions - * @{ - * @ingroup app_common - * @} */ -#if NRF_MODULE_ENABLED(RETARGET) -#if !defined(NRF_LOG_USES_RTT) || NRF_LOG_USES_RTT != 1 -#if !defined(HAS_SIMPLE_UART_RETARGET) - - -#include -#include -#include "app_uart.h" -#include "nrf_error.h" - - -#if defined(__CC_ARM) - -// This part is taken from MDK-ARM template file and is required here to prevent -// linker from selecting libraries functions that use semihosting and failing -// because of multiple definitions of fgetc() and fputc(). -// Refer to: http://www.keil.com/support/man/docs/gsac/gsac_retargetcortex.htm -// -- BEGIN -- -struct __FILE { int handle; /* Add whatever you need here */ }; -FILE __stdout; -FILE __stdin; -// --- END --- - -int fgetc(FILE * p_file) -{ - uint8_t input; - while (app_uart_get(&input) == NRF_ERROR_NOT_FOUND) - { - // No implementation needed. - } - return input; -} - -int fputc(int ch, FILE * p_file) -{ - UNUSED_PARAMETER(p_file); - - UNUSED_VARIABLE(app_uart_put((uint8_t)ch)); - return ch; -} - -#elif defined(__GNUC__) && defined(__SES_ARM) - -int __getchar(FILE * p_file) -{ - uint8_t input; - while (app_uart_get(&input) == NRF_ERROR_NOT_FOUND) - { - // No implementation needed. - } - return input; -} - -int __putchar(int ch, FILE * p_file) -{ - UNUSED_PARAMETER(p_file); - - UNUSED_VARIABLE(app_uart_put((uint8_t)ch)); - return ch; -} - -#elif defined(__GNUC__) && !defined(__SES_ARM) - -int _write(int file, const char * p_char, int len) -{ - int i; - - UNUSED_PARAMETER(file); - - for (i = 0; i < len; i++) - { - UNUSED_VARIABLE(app_uart_put(*p_char++)); - } - - return len; -} - -int _read(int file, char * p_char, int len) -{ - UNUSED_PARAMETER(file); - while (app_uart_get((uint8_t *)p_char) == NRF_ERROR_NOT_FOUND) - { - // No implementation needed. - } - - return 1; -} -#elif defined(__ICCARM__) - -size_t __write(int handle, const unsigned char * buffer, size_t size) -{ - int i; - UNUSED_PARAMETER(handle); - for (i = 0; i < size; i++) - { - UNUSED_VARIABLE(app_uart_put(*buffer++)); - } - return size; -} - -size_t __read(int handle, unsigned char * buffer, size_t size) -{ - UNUSED_PARAMETER(handle); - UNUSED_PARAMETER(size); - while (app_uart_get((uint8_t *)buffer) == NRF_ERROR_NOT_FOUND) - { - // No implementation needed. - } - - return 1; -} - -long __lseek(int handle, long offset, int whence) -{ - return -1; -} -int __close(int handle) -{ - return 0; -} -int remove(const char * filename) -{ - return 0; -} - -#endif - -#endif // !defined(HAS_SIMPLE_UART_RETARGET) -#endif // NRF_LOG_USES_RTT != 1 -#endif //NRF_MODULE_ENABLED(RETARGET) diff --git a/bsp/boards/nrf52840/sdk/components/libraries/util/app_error.c b/bsp/boards/nrf52840/sdk/components/libraries/util/app_error.c deleted file mode 100644 index 3e814ab04d..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/util/app_error.c +++ /dev/null @@ -1,125 +0,0 @@ -/** - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -/** @file - * - * @defgroup app_error Common application error handler - * @{ - * @ingroup app_common - * - * @brief Common application error handler. - */ - -#include "nrf.h" -#include -#include "app_error.h" -#include "nordic_common.h" -#include "sdk_errors.h" - -/**@brief Function for error handling, which is called when an error has occurred. - * - * @warning This handler is an example only and does not fit a final product. You need to analyze - * how your product is supposed to react in case of error. - * - * @param[in] error_code Error code supplied to the handler. - * @param[in] line_num Line number where the handler is called. - * @param[in] p_file_name Pointer to the file name. - */ -void app_error_handler_bare(ret_code_t error_code) -{ - error_info_t error_info = - { - .line_num = 0, - .p_file_name = NULL, - .err_code = error_code, - }; - - app_error_fault_handler(NRF_FAULT_ID_SDK_ERROR, 0, (uint32_t)(&error_info)); - - UNUSED_VARIABLE(error_info); -} - -void app_error_save_and_stop(uint32_t id, uint32_t pc, uint32_t info) -{ - /* static error variables - in order to prevent removal by optimizers */ - static volatile struct - { - uint32_t fault_id; - uint32_t pc; - uint32_t error_info; - assert_info_t * p_assert_info; - error_info_t * p_error_info; - ret_code_t err_code; - uint32_t line_num; - const uint8_t * p_file_name; - } m_error_data = {0}; - - // The following variable helps Keil keep the call stack visible, in addition, it can be set to - // 0 in the debugger to continue executing code after the error check. - volatile bool loop = true; - UNUSED_VARIABLE(loop); - - m_error_data.fault_id = id; - m_error_data.pc = pc; - m_error_data.error_info = info; - - switch (id) - { - case NRF_FAULT_ID_SDK_ASSERT: - m_error_data.p_assert_info = (assert_info_t *)info; - m_error_data.line_num = m_error_data.p_assert_info->line_num; - m_error_data.p_file_name = m_error_data.p_assert_info->p_file_name; - break; - - case NRF_FAULT_ID_SDK_ERROR: - m_error_data.p_error_info = (error_info_t *)info; - m_error_data.err_code = m_error_data.p_error_info->err_code; - m_error_data.line_num = m_error_data.p_error_info->line_num; - m_error_data.p_file_name = m_error_data.p_error_info->p_file_name; - break; - } - - UNUSED_VARIABLE(m_error_data); - - // If printing is disrupted, remove the irq calls, or set the loop variable to 0 in the debugger. - __disable_irq(); - while (loop); - - __enable_irq(); -} diff --git a/bsp/boards/nrf52840/sdk/components/libraries/util/app_error.h b/bsp/boards/nrf52840/sdk/components/libraries/util/app_error.h deleted file mode 100644 index c5e8244f50..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/util/app_error.h +++ /dev/null @@ -1,192 +0,0 @@ -/** - * Copyright (c) 2013 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -/** @file - * - * @defgroup app_error Common application error handler - * @{ - * @ingroup app_common - * - * @brief Common application error handler and macros for utilizing a common error handler. - */ - -#ifndef APP_ERROR_H__ -#define APP_ERROR_H__ - - -#include -#include -#include -#include "nrf.h" -#include "sdk_errors.h" -#include "nordic_common.h" -#include "app_error_weak.h" -#ifdef ANT_STACK_SUPPORT_REQD -#include "ant_error.h" -#endif // ANT_STACK_SUPPORT_REQD - - - -#ifdef __cplusplus -extern "C" { -#endif - -#define NRF_FAULT_ID_SDK_RANGE_START (0x00004000) /**< The start of the range of error IDs defined in the SDK. */ - -/**@defgroup APP_ERROR_FAULT_IDS Fault ID types - * @{ */ -#define NRF_FAULT_ID_SDK_ERROR (NRF_FAULT_ID_SDK_RANGE_START + 1) /**< An error stemming from a call to @ref APP_ERROR_CHECK or @ref APP_ERROR_CHECK_BOOL. The info parameter is a pointer to an @ref error_info_t variable. */ -#define NRF_FAULT_ID_SDK_ASSERT (NRF_FAULT_ID_SDK_RANGE_START + 2) /**< An error stemming from a call to ASSERT (nrf_assert.h). The info parameter is a pointer to an @ref assert_info_t variable. */ -/**@} */ - -/**@brief Structure containing info about an error of the type @ref NRF_FAULT_ID_SDK_ERROR. - */ -typedef struct -{ - uint32_t line_num; /**< The line number where the error occurred. */ - uint8_t const * p_file_name; /**< The file in which the error occurred. */ - uint32_t err_code; /**< The error code representing the error that occurred. */ -} error_info_t; - -/**@brief Structure containing info about an error of the type @ref NRF_FAULT_ID_SDK_ASSERT. - */ -typedef struct -{ - uint16_t line_num; /**< The line number where the error occurred. */ - uint8_t const * p_file_name; /**< The file in which the error occurred. */ -} assert_info_t; - -/**@brief Defines required by app_error_handler assembler intructions. - */ -#define APP_ERROR_ERROR_INFO_OFFSET_LINE_NUM (offsetof(error_info_t, line_num)) -#define APP_ERROR_ERROR_INFO_OFFSET_P_FILE_NAME (offsetof(error_info_t, p_file_name)) -#define APP_ERROR_ERROR_INFO_OFFSET_ERR_CODE (offsetof(error_info_t, err_code)) -#define APP_ERROR_ERROR_INFO_SIZE (sizeof(error_info_t)) -#define APP_ERROR_ERROR_INFO_SIZE_ALIGNED_8BYTE \ - ALIGN_NUM(APP_ERROR_ERROR_INFO_SIZE, sizeof(uint64_t)) - - -/**@brief Function for error handling, which is called when an error has occurred. - * - * @param[in] error_code Error code supplied to the handler. - * @param[in] line_num Line number where the handler is called. - * @param[in] p_file_name Pointer to the file name. - */ -void app_error_handler(uint32_t error_code, uint32_t line_num, const uint8_t * p_file_name); - -/**@brief Function for error handling, which is called when an error has occurred. - * - * @param[in] error_code Error code supplied to the handler. - */ -void app_error_handler_bare(ret_code_t error_code); - -/**@brief Function for saving the parameters and entering an eternal loop, for debug purposes. - * - * @param[in] id Fault identifier. See @ref NRF_FAULT_IDS. - * @param[in] pc The program counter of the instruction that triggered the fault, or 0 if - * unavailable. - * @param[in] info Optional additional information regarding the fault. Refer to each fault - * identifier for details. - */ -void app_error_save_and_stop(uint32_t id, uint32_t pc, uint32_t info); - -/**@brief Function for logging details of error and flushing logs. - * - * @param[in] id Fault identifier. See @ref NRF_FAULT_IDS. - * @param[in] pc The program counter of the instruction that triggered the fault, or 0 if - * unavailable. - * @param[in] info Optional additional information regarding the fault. Refer to each fault - * identifier for details. - */ -void app_error_log_handle(uint32_t id, uint32_t pc, uint32_t info); - - -/**@brief Macro for calling error handler function. - * - * @param[in] ERR_CODE Error code supplied to the error handler. - */ -#ifdef DEBUG -#define APP_ERROR_HANDLER(ERR_CODE) \ - do \ - { \ - app_error_handler((ERR_CODE), __LINE__, (uint8_t*) __FILE__); \ - } while (0) -#else -#define APP_ERROR_HANDLER(ERR_CODE) \ - do \ - { \ - app_error_handler_bare((ERR_CODE)); \ - } while (0) -#endif -/**@brief Macro for calling error handler function if supplied error code any other than NRF_SUCCESS. - * - * @param[in] ERR_CODE Error code supplied to the error handler. - */ -#define APP_ERROR_CHECK(ERR_CODE) \ - do \ - { \ - const uint32_t LOCAL_ERR_CODE = (ERR_CODE); \ - if (LOCAL_ERR_CODE != NRF_SUCCESS) \ - { \ - APP_ERROR_HANDLER(LOCAL_ERR_CODE); \ - } \ - } while (0) - -/**@brief Macro for calling error handler function if supplied boolean value is false. - * - * @param[in] BOOLEAN_VALUE Boolean value to be evaluated. - */ -#define APP_ERROR_CHECK_BOOL(BOOLEAN_VALUE) \ - do \ - { \ - const uint32_t LOCAL_BOOLEAN_VALUE = (BOOLEAN_VALUE); \ - if (!LOCAL_BOOLEAN_VALUE) \ - { \ - APP_ERROR_HANDLER(0); \ - } \ - } while (0) - - -#ifdef __cplusplus -} -#endif - -#endif // APP_ERROR_H__ - -/** @} */ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/util/app_error_handler_gcc.c b/bsp/boards/nrf52840/sdk/components/libraries/util/app_error_handler_gcc.c deleted file mode 100644 index 912ece0abc..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/util/app_error_handler_gcc.c +++ /dev/null @@ -1,101 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include "sdk_common.h" -#include "compiler_abstraction.h" -#include "app_error.h" - -#if defined (__CORTEX_M) && (__CORTEX_M == 0x04) -void app_error_handler(ret_code_t error_code, uint32_t line_num, const uint8_t * p_file_name) __attribute__(( naked )); - -void app_error_handler(ret_code_t error_code, uint32_t line_num, const uint8_t * p_file_name) -{ - __ASM volatile( - - "push {lr} \n" - - /* reserve space on stack for error_info_t struct - preserve 8byte stack aligment */ - "sub sp, sp, %0 \n" - - /* prepare error_info_t struct */ - "str r0, [sp, %1] \n" - "str r1, [sp, %3] \n" - "str r2, [sp, %2] \n" - - /* prepare arguments and call function: app_error_fault_handler */ - "ldr r0, =%4 \n" - "mov r1, lr \n" - "mov r2, sp \n" - "bl %5 \n" - - /* release stack */ - "add sp, sp, %0 \n" - - "pop {pc} \n" - ".ltorg \n" - - : /* Outputs */ - : /* Inputs */ - "I" (APP_ERROR_ERROR_INFO_SIZE_ALIGNED_8BYTE), - "I" (APP_ERROR_ERROR_INFO_OFFSET_ERR_CODE), - "I" (APP_ERROR_ERROR_INFO_OFFSET_P_FILE_NAME), - "I" (APP_ERROR_ERROR_INFO_OFFSET_LINE_NUM), - "X" (NRF_FAULT_ID_SDK_ERROR), - "X" (app_error_fault_handler) - : /* Clobbers */ - "r0", "r1", "r2" - ); -} -#elif defined(__CORTEX_M) && (__CORTEX_M == 0x00) -/* NRF51 implementation is currently not supporting PC readout */ -void app_error_handler(ret_code_t error_code, uint32_t line_num, const uint8_t * p_file_name) -{ - error_info_t error_info = { - .line_num = line_num, - .p_file_name = p_file_name, - .err_code = error_code, - }; - app_error_fault_handler(NRF_FAULT_ID_SDK_ERROR, 0, (uint32_t)(&error_info)); - - UNUSED_VARIABLE(error_info); -} -#else -#error Architecture not supported -#endif - diff --git a/bsp/boards/nrf52840/sdk/components/libraries/util/app_error_handler_iar.c b/bsp/boards/nrf52840/sdk/components/libraries/util/app_error_handler_iar.c deleted file mode 100644 index 97d7631221..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/util/app_error_handler_iar.c +++ /dev/null @@ -1,101 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include "sdk_common.h" -#include "compiler_abstraction.h" -#include "app_error.h" - -#if defined (__CORTEX_M) && (__CORTEX_M == 0x04) -void app_error_handler(ret_code_t error_code, uint32_t line_num, const uint8_t * p_file_name) -{ - __ASM volatile( - "push {lr} \n" - /* reserve space on stack for error_info_t struct */ - "sub sp, sp, %0 \n" - - /* prepare error_info_t struct */ - "str r0, [sp, %1] \n" - "str r1, [sp, %3] \n" - "str r2, [sp, %2] \n" - - /* prepare arguments and call function: app_error_fault_handler */ - "ldr.n r0, 1f \n" - "mov r1, LR \n" - "mov r2, sp \n" - - /* call app_error_fault_handler */ - "bl %c5 \n" - - /* release stack */ - "add sp, sp, %0 \n" - "pop {pc} \n" - - "DATA \n" - "1: \n" - " DC32 %c4 \n" - - : /* Outputs */ - : /* Inputs */ - "i" (APP_ERROR_ERROR_INFO_SIZE_ALIGNED_8BYTE), - "i" (APP_ERROR_ERROR_INFO_OFFSET_ERR_CODE), - "i" (APP_ERROR_ERROR_INFO_OFFSET_P_FILE_NAME), - "i" (APP_ERROR_ERROR_INFO_OFFSET_LINE_NUM), - "i" (NRF_FAULT_ID_SDK_ERROR), - "i" (app_error_fault_handler) - : /* CLobbers */ - "r0", "r1", "r2" - ); -} -#elif defined(__CORTEX_M) && (__CORTEX_M == 0x00) -/* NRF51 implementation is currently not supporting PC readout */ -void app_error_handler(ret_code_t error_code, uint32_t line_num, const uint8_t * p_file_name) -{ - error_info_t error_info = { - .line_num = line_num, - .p_file_name = p_file_name, - .err_code = error_code, - }; - app_error_fault_handler(NRF_FAULT_ID_SDK_ERROR, 0, (uint32_t)(&error_info)); - - UNUSED_VARIABLE(error_info); -} -#else -#error Architecture not supported -#endif - diff --git a/bsp/boards/nrf52840/sdk/components/libraries/util/app_error_handler_keil.c b/bsp/boards/nrf52840/sdk/components/libraries/util/app_error_handler_keil.c deleted file mode 100644 index 53b7e49e62..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/util/app_error_handler_keil.c +++ /dev/null @@ -1,89 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include "sdk_common.h" -#include "compiler_abstraction.h" -#include "app_error.h" - -#if defined (__CORTEX_M) && (__CORTEX_M == 0x04) -__ASM void app_error_handler(ret_code_t error_code, uint32_t line_num, const uint8_t * p_file_name) -{ - PRESERVE8 {TRUE} - THUMB - - push {lr} - - /* reserve space on stack for error_info_t struct - preserve 8byte stack aligment */ - sub sp, sp, #__cpp(APP_ERROR_ERROR_INFO_SIZE_ALIGNED_8BYTE) - - /* prepare error_info_t struct */ - str r0, [sp, #__cpp(APP_ERROR_ERROR_INFO_OFFSET_ERR_CODE)] - str r1, [sp, #__cpp(APP_ERROR_ERROR_INFO_OFFSET_LINE_NUM)] - str r2, [sp, #__cpp(APP_ERROR_ERROR_INFO_OFFSET_P_FILE_NAME)] - - /* prepare arguments and call function: app_error_fault_handler */ - mov r0, #__cpp(NRF_FAULT_ID_SDK_ERROR) - mov r1, lr - mov r2, sp - - /* call function */ - bl __cpp(app_error_fault_handler) - - /* release stack */ - add sp, sp, #__cpp(APP_ERROR_ERROR_INFO_SIZE_ALIGNED_8BYTE) - - pop {pc} -} -#elif defined(__CORTEX_M) && (__CORTEX_M == 0x00) -/* NRF51 implementation is currently not supporting PC readout */ -void app_error_handler(ret_code_t error_code, uint32_t line_num, const uint8_t * p_file_name) -{ - error_info_t error_info = { - .line_num = line_num, - .p_file_name = p_file_name, - .err_code = error_code, - }; - app_error_fault_handler(NRF_FAULT_ID_SDK_ERROR, 0, (uint32_t)(&error_info)); - - UNUSED_VARIABLE(error_info); -} -#else -#error Architecture not supported -#endif - diff --git a/bsp/boards/nrf52840/sdk/components/libraries/util/app_error_weak.c b/bsp/boards/nrf52840/sdk/components/libraries/util/app_error_weak.c deleted file mode 100644 index 4551e7d68f..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/util/app_error_weak.c +++ /dev/null @@ -1,109 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include "app_error.h" - -#include "nrf_log.h" -#include "nrf_log_ctrl.h" -#include "nrf_strerror.h" - -#if defined(SOFTDEVICE_PRESENT) && SOFTDEVICE_PRESENT -#include "nrf_sdm.h" -#endif - -/*lint -save -e14 */ -/** - * Function is implemented as weak so that it can be overwritten by custom application error handler - * when needed. - */ -__WEAK void app_error_fault_handler(uint32_t id, uint32_t pc, uint32_t info) -{ - __disable_irq(); - NRF_LOG_FINAL_FLUSH(); - -#ifndef DEBUG - NRF_LOG_ERROR("Fatal error"); -#else - switch (id) - { -#if defined(SOFTDEVICE_PRESENT) && SOFTDEVICE_PRESENT - case NRF_FAULT_ID_SD_ASSERT: - NRF_LOG_ERROR("SOFTDEVICE: ASSERTION FAILED"); - break; - case NRF_FAULT_ID_APP_MEMACC: - NRF_LOG_ERROR("SOFTDEVICE: INVALID MEMORY ACCESS"); - break; -#endif - case NRF_FAULT_ID_SDK_ASSERT: - { - assert_info_t * p_info = (assert_info_t *)info; - NRF_LOG_ERROR("ASSERTION FAILED at %s:%u", - p_info->p_file_name, - p_info->line_num); - break; - } - case NRF_FAULT_ID_SDK_ERROR: - { - error_info_t * p_info = (error_info_t *)info; - NRF_LOG_ERROR("ERROR %u [%s] at %s:%u\r\nPC at: 0x%08x", - p_info->err_code, - nrf_strerror_get(p_info->err_code), - p_info->p_file_name, - p_info->line_num, - pc); - NRF_LOG_ERROR("End of error report"); - break; - } - default: - NRF_LOG_ERROR("UNKNOWN FAULT at 0x%08X", pc); - break; - } -#endif - - NRF_BREAKPOINT_COND; - // On assert, the system can only recover with a reset. - -#ifndef DEBUG - NRF_LOG_WARNING("System reset"); - NVIC_SystemReset(); -#else - app_error_save_and_stop(id, pc, info); -#endif // DEBUG -} -/*lint -restore */ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/util/app_error_weak.h b/bsp/boards/nrf52840/sdk/components/libraries/util/app_error_weak.h deleted file mode 100644 index 880c518d3b..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/util/app_error_weak.h +++ /dev/null @@ -1,87 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef APP_ERROR_WEAK_H__ -#define APP_ERROR_WEAK_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** @file - * - * @defgroup app_error Common application error handler - * @{ - * @ingroup app_common - * - * @brief Common application error handler. - */ - -/**@brief Callback function for errors, asserts, and faults. - * - * @details This function is called every time an error is raised in app_error, nrf_assert, or - * in the SoftDevice. Information about the error can be found in the @p info - * parameter. - * - * See also @ref nrf_fault_handler_t for more details. - * - * @note The function is implemented as weak so that it can be redefined by a custom error - * handler when needed. - * - * @param[in] id Fault identifier. See @ref NRF_FAULT_IDS. - * @param[in] pc The program counter of the instruction that triggered the fault, or 0 if - * unavailable. - * @param[in] info Optional additional information regarding the fault. The value of the @p id - * parameter dictates how to interpret this parameter. Refer to the documentation - * for each fault identifier (@ref NRF_FAULT_IDS and @ref APP_ERROR_FAULT_IDS) for - * details about interpreting @p info. - */ -void app_error_fault_handler(uint32_t id, uint32_t pc, uint32_t info); - - -/** @} */ - - -#ifdef __cplusplus -} -#endif - -#endif // APP_ERROR_WEAK_H__ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/util/app_util.h b/bsp/boards/nrf52840/sdk/components/libraries/util/app_util.h deleted file mode 100644 index 9d65af9533..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/util/app_util.h +++ /dev/null @@ -1,1204 +0,0 @@ -/** - * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -/** @file - * - * @defgroup app_util Utility Functions and Definitions - * @{ - * @ingroup app_common - * - * @brief Various types and definitions available to all applications. - */ - -#ifndef APP_UTIL_H__ -#define APP_UTIL_H__ - -#include -#include -#include -#include "compiler_abstraction.h" -#include "nordic_common.h" -#include "nrf.h" - -#ifdef __cplusplus -extern "C" { -#endif -/** - * @cond (NODOX) - */ -/*lint -save -e27 -e10 -e19 */ -#if defined (__LINT__) -#define STACK_BASE 0x1F000 // Arbitrary value. -#define STACK_TOP 0x20000 // Arbitrary value. - -#elif defined ( __CC_ARM ) -extern char STACK$$Base; -extern char STACK$$Length; -#define STACK_BASE &STACK$$Base -#define STACK_TOP ((void*)((uint32_t)STACK_BASE + (uint32_t)&STACK$$Length)) - -#elif defined ( __ICCARM__ ) -extern char CSTACK$$Base; -extern char CSTACK$$Length; -#define STACK_BASE &CSTACK$$Base -#define STACK_TOP ((void*)((uint32_t)STACK_BASE + (uint32_t)&CSTACK$$Length)) - -#elif defined ( __GNUC__ ) -extern uint32_t __StackTop; -extern uint32_t __StackLimit; -#define STACK_BASE &__StackLimit -#define STACK_TOP &__StackTop -#endif - -/* These macros are valid only when absolute placement is used for the application - * image. The macros are not compile time symbols. They cannot be used as a - * constant expression, for example, inside a static assert or linker script - * at-placement. */ -#if defined (__LINT__) -#define CODE_START (0) // Arbitrary value. -#define CODE_END (0x1000) // Arbitrary value. -#define CODE_SIZE (0x1000) // Arbitrary value. - -#elif defined ( __CC_ARM ) -extern char Load$$LR$$LR_IROM1$$Base; -extern char Load$$LR$$LR_IROM1$$Length; -extern char Load$$LR$$LR_IROM1$$Limit; -#define CODE_START ((uint32_t)&Load$$LR$$LR_IROM1$$Base) -#define CODE_END ((uint32_t)&Load$$LR$$LR_IROM1$$Limit) -#define CODE_SIZE ((uint32_t)&Load$$LR$$LR_IROM1$$Length) - -#elif defined ( __ICCARM__ ) -extern void * __vector_table; -extern char RO_END$$Base; -#define CODE_START ((uint32_t)&__vector_table) -#define CODE_END ((uint32_t)&RO_END$$Base) -#define CODE_SIZE (CODE_END - CODE_START) - -#elif defined(__SES_ARM) -extern uint32_t * _vectors; -extern uint32_t __FLASH_segment_used_end__; -#define CODE_START ((uint32_t)&_vectors) -#define CODE_END ((uint32_t)&__FLASH_segment_used_end__) -#define CODE_SIZE (CODE_END - CODE_START) - -#elif defined ( __GNUC__ ) -extern uint32_t __isr_vector; -extern uint32_t __etext; -#define CODE_START ((uint32_t)&__isr_vector) -#define CODE_END ((uint32_t)&__etext) -#define CODE_SIZE (CODE_END - CODE_START) -#endif -/** @} - * @endcond - */ -/* lint -restore */ - -enum -{ - UNIT_0_625_MS = 625, /**< Number of microseconds in 0.625 milliseconds. */ - UNIT_1_25_MS = 1250, /**< Number of microseconds in 1.25 milliseconds. */ - UNIT_10_MS = 10000 /**< Number of microseconds in 10 milliseconds. */ -}; - -/** - * @brief Counts number of bits required for the given value - * - * The macro technically searches for the highest bit set. - * For value 0 it returns 0. - * - * @param val Value to be processed - * - * @return Number of bits required for the given value - */ -//lint -emacro(572,VBITS) -#define VBITS(val) VBITS_32(val) - -/** - * @def VBITS_1 - * @brief Internal macro used by @ref VBITS */ -/** - * @def VBITS_2 - * @brief Internal macro used by @ref VBITS */ -/** - * @def VBITS_4 - * @brief Internal macro used by @ref VBITS */ -/** - * @def VBITS_8 - * @brief Internal macro used by @ref VBITS */ -/** - * @def VBITS_16 - * @brief Internal macro used by @ref VBITS */ -/** - * @def VBITS_32 - * @brief Internal macro used by @ref VBITS */ -#define VBITS_1( v) ((((v) & (0x0001U << 0)) != 0) ? 1U : 0U) -#define VBITS_2( v) ((((v) & (0x0001U << 1)) != 0) ? VBITS_1 ((v) >> 1) + 1 : VBITS_1 (v)) -#define VBITS_4( v) ((((v) & (0x0003U << 2)) != 0) ? VBITS_2 ((v) >> 2) + 2 : VBITS_2 (v)) -#define VBITS_8( v) ((((v) & (0x000fU << 4)) != 0) ? VBITS_4 ((v) >> 4) + 4 : VBITS_4 (v)) -#define VBITS_16(v) ((((v) & (0x00ffU << 8)) != 0) ? VBITS_8 ((v) >> 8) + 8 : VBITS_8 (v)) -#define VBITS_32(v) ((((v) & (0xffffU << 16)) != 0) ? VBITS_16((v) >> 16) + 16 : VBITS_16(v)) - - -/*Segger embedded studio originally has offsetof macro which cannot be used in macros (like STATIC_ASSERT). - This redefinition is to allow using that. */ -#if defined(__SES_ARM) && defined(__GNUC__) -#undef offsetof -#define offsetof(TYPE, MEMBER) __builtin_offsetof (TYPE, MEMBER) -#endif - -/**@brief Implementation specific macro for delayed macro expansion used in string concatenation -* -* @param[in] lhs Left hand side in concatenation -* @param[in] rhs Right hand side in concatenation -*/ -#define STRING_CONCATENATE_IMPL(lhs, rhs) lhs ## rhs - - -/**@brief Macro used to concatenate string using delayed macro expansion -* -* @note This macro will delay concatenation until the expressions have been resolved -* -* @param[in] lhs Left hand side in concatenation -* @param[in] rhs Right hand side in concatenation -*/ -#define STRING_CONCATENATE(lhs, rhs) STRING_CONCATENATE_IMPL(lhs, rhs) - - -#ifndef __LINT__ - -#ifdef __GNUC__ -#define STATIC_ASSERT_SIMPLE(EXPR) _Static_assert(EXPR, "unspecified message") -#define STATIC_ASSERT_MSG(EXPR, MSG) _Static_assert(EXPR, MSG) -#endif - -#ifdef __CC_ARM -#define STATIC_ASSERT_SIMPLE(EXPR) extern char (*_do_assert(void)) [sizeof(char[1 - 2*!(EXPR)])] -#define STATIC_ASSERT_MSG(EXPR, MSG) extern char (*_do_assert(void)) [sizeof(char[1 - 2*!(EXPR)])] -#endif - -#ifdef __ICCARM__ -#define STATIC_ASSERT_SIMPLE(EXPR) static_assert(EXPR, "unspecified message") -#define STATIC_ASSERT_MSG(EXPR, MSG) static_assert(EXPR, MSG) -#endif - -#else // __LINT__ - -#define STATIC_ASSERT_SIMPLE(EXPR) extern char (*_ignore(void)) -#define STATIC_ASSERT_MSG(EXPR, MSG) extern char (*_ignore(void)) - -#endif - - -#define _SELECT_ASSERT_FUNC(x, EXPR, MSG, ASSERT_MACRO, ...) ASSERT_MACRO - -/** - * @brief Static (i.e. compile time) assert macro. - * - * @note The output of STATIC_ASSERT can be different across compilers. - * - * Usage: - * STATIC_ASSERT(expression); - * STATIC_ASSERT(expression, message); - * - * @hideinitializer - */ -//lint -save -esym(???, STATIC_ASSERT) -#define STATIC_ASSERT(...) \ - _SELECT_ASSERT_FUNC(x, ##__VA_ARGS__, \ - STATIC_ASSERT_MSG(__VA_ARGS__), \ - STATIC_ASSERT_SIMPLE(__VA_ARGS__)) -//lint -restore - - -/**@brief Implementation details for NUM_VAR_ARGS */ -#define NUM_VA_ARGS_IMPL( \ - _0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \ - _11, _12, _13, _14, _15, _16, _17, _18, _19, _20, \ - _21, _22, _23, _24, _25, _26, _27, _28, _29, _30, \ - _31, _32, _33, _34, _35, _36, _37, _38, _39, _40, \ - _41, _42, _43, _44, _45, _46, _47, _48, _49, _50, \ - _51, _52, _53, _54, _55, _56, _57, _58, _59, _60, \ - _61, _62, N, ...) N - - -/**@brief Macro to get the number of arguments in a call variadic macro call - * - * param[in] ... List of arguments - * - * @retval Number of variadic arguments in the argument list - */ -#define NUM_VA_ARGS(...) NUM_VA_ARGS_IMPL(__VA_ARGS__, 63, 62, 61, \ - 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ - 50, 49, 48, 47, 46, 45, 44, 43, 42, 41, \ - 40, 39, 38, 37, 36, 35, 34, 33, 32, 31, \ - 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, \ - 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, \ - 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) - -/**@brief Implementation details for NUM_VAR_ARGS */ -#define NUM_VA_ARGS_LESS_1_IMPL( \ - _ignored, \ - _0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \ - _11, _12, _13, _14, _15, _16, _17, _18, _19, _20, \ - _21, _22, _23, _24, _25, _26, _27, _28, _29, _30, \ - _31, _32, _33, _34, _35, _36, _37, _38, _39, _40, \ - _41, _42, _43, _44, _45, _46, _47, _48, _49, _50, \ - _51, _52, _53, _54, _55, _56, _57, _58, _59, _60, \ - _61, _62, N, ...) N - -/**@brief Macro to get the number of arguments in a call variadic macro call. - * First argument is not counted. - * - * param[in] ... List of arguments - * - * @retval Number of variadic arguments in the argument list - */ -#define NUM_VA_ARGS_LESS_1(...) NUM_VA_ARGS_LESS_1_IMPL(__VA_ARGS__, 63, 62, 61, \ - 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ - 50, 49, 48, 47, 46, 45, 44, 43, 42, 41, \ - 40, 39, 38, 37, 36, 35, 34, 33, 32, 31, \ - 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, \ - 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, \ - 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, ~) - - -/**@brief type for holding an encoded (i.e. little endian) 16 bit unsigned integer. */ -typedef uint8_t uint16_le_t[2]; - -/**@brief Type for holding an encoded (i.e. little endian) 32 bit unsigned integer. */ -typedef uint8_t uint32_le_t[4]; - -/**@brief Byte array type. */ -typedef struct -{ - uint16_t size; /**< Number of array entries. */ - uint8_t * p_data; /**< Pointer to array entries. */ -} uint8_array_t; - - -/**@brief Macro for performing rounded integer division (as opposed to truncating the result). - * - * @param[in] A Numerator. - * @param[in] B Denominator. - * - * @return Rounded (integer) result of dividing A by B. - */ -#define ROUNDED_DIV(A, B) (((A) + ((B) / 2)) / (B)) - - -/**@brief Macro for checking if an integer is a power of two. - * - * @param[in] A Number to be tested. - * - * @return true if value is power of two. - * @return false if value not power of two. - */ -#define IS_POWER_OF_TWO(A) ( ((A) != 0) && ((((A) - 1) & (A)) == 0) ) - - -/**@brief Macro for converting milliseconds to ticks. - * - * @param[in] TIME Number of milliseconds to convert. - * @param[in] RESOLUTION Unit to be converted to in [us/ticks]. - */ -#define MSEC_TO_UNITS(TIME, RESOLUTION) (((TIME) * 1000) / (RESOLUTION)) - - -/**@brief Macro for performing integer division, making sure the result is rounded up. - * - * @details One typical use for this is to compute the number of objects with size B is needed to - * hold A number of bytes. - * - * @param[in] A Numerator. - * @param[in] B Denominator. - * - * @return Integer result of dividing A by B, rounded up. - */ -#define CEIL_DIV(A, B) \ - (((A) + (B) - 1) / (B)) - - -/**@brief Macro for creating a buffer aligned to 4 bytes. - * - * @param[in] NAME Name of the buffor. - * @param[in] MIN_SIZE Size of this buffor (it will be rounded up to multiples of 4 bytes). - */ -#define WORD_ALIGNED_MEM_BUFF(NAME, MIN_SIZE) static uint32_t NAME[CEIL_DIV(MIN_SIZE, sizeof(uint32_t))] - - -/**@brief Macro for calculating the number of words that are needed to hold a number of bytes. - * - * @details Adds 3 and divides by 4. - * - * @param[in] n_bytes The number of bytes. - * - * @return The number of words that @p n_bytes take up (rounded up). - */ -#define BYTES_TO_WORDS(n_bytes) (((n_bytes) + 3) >> 2) - - -/**@brief The number of bytes in a word. - */ -#define BYTES_PER_WORD (4) - - -/**@brief Macro for increasing a number to the nearest (larger) multiple of another number. - * - * @param[in] alignment The number to align to. - * @param[in] number The number to align (increase). - * - * @return The aligned (increased) @p number. - */ -#define ALIGN_NUM(alignment, number) (((number) - 1) + (alignment) - (((number) - 1) % (alignment))) - -/**@brief Macro for getting first of 2 parameters. - * - * @param[in] a1 First parameter. - * @param[in] a2 Second parameter. - */ -#define GET_ARG_1(a1, a2) a1 - -/**@brief Macro for getting second of 2 parameters. - * - * @param[in] a1 First parameter. - * @param[in] a2 Second parameter. - */ -#define GET_ARG_2(a1, a2) a2 - - -/**@brief Container of macro (borrowed from Linux kernel). - * - * This macro returns parent structure address basing on child member address. - * - * @param ptr Address of child type. - * @param type Type of parent structure. - * @param member Name of child field in parent structure. - * - * @return Parent structure address. - * */ -#define CONTAINER_OF(ptr, type, member) \ - (type *)((char *)ptr - offsetof(type, member)) - - -/** - * @brief Define Bit-field mask - * - * Macro that defined the mask with selected number of bits set, starting from - * provided bit number. - * - * @param[in] bcnt Number of bits in the bit-field - * @param[in] boff Lowest bit number - */ -#define BF_MASK(bcnt, boff) ( ((1U << (bcnt)) - 1U) << (boff) ) - -/** - * @brief Get bit-field - * - * Macro that extracts selected bit-field from provided value - * - * @param[in] val Value from witch selected bit-field would be extracted - * @param[in] bcnt Number of bits in the bit-field - * @param[in] boff Lowest bit number - * - * @return Value of the selected bits - */ -#define BF_GET(val, bcnt, boff) ( ( (val) & BF_MASK((bcnt), (boff)) ) >> (boff) ) - -/** - * @brief Create bit-field value - * - * Value is masked and shifted to match given bit-field - * - * @param[in] val Value to set on bit-field - * @param[in] bcnt Number of bits for bit-field - * @param[in] boff Offset of bit-field - * - * @return Value positioned of given bit-field. - */ -#define BF_VAL(val, bcnt, boff) ( (((uint32_t)(val)) << (boff)) & BF_MASK(bcnt, boff) ) - -/** - * @name Configuration of complex bit-field - * - * @sa BF_CX - * @{ - */ -/** @brief Position of bit count in complex bit-field value */ -#define BF_CX_BCNT_POS 0U -/** @brief Mask of bit count in complex bit-field value */ -#define BF_CX_BCNT_MASK (0xffU << BF_CX_BCNT_POS) -/** @brief Position of bit position in complex bit-field value */ -#define BF_CX_BOFF_POS 8U -/** @brief Mask of bit position in complex bit-field value */ -#define BF_CX_BOFF_MASK (0xffU << BF_CX_BOFF_POS) -/** @} */ - -/** - * @brief Define complex bit-field - * - * Complex bit-field would contain its position and size in one number. - * @sa BF_CX_MASK - * @sa BF_CX_POS - * @sa BF_CX_GET - * - * @param[in] bcnt Number of bits in the bit-field - * @param[in] boff Lowest bit number - * - * @return The single number that describes the bit-field completely. - */ -#define BF_CX(bcnt, boff) ( ((((uint32_t)(bcnt)) << BF_CX_BCNT_POS) & BF_CX_BCNT_MASK) | ((((uint32_t)(boff)) << BF_CX_BOFF_POS) & BF_CX_BOFF_MASK) ) - -/** - * @brief Get number of bits in bit-field - * - * @sa BF_CX - * - * @param bf_cx Complex bit-field - * - * @return Number of bits in given bit-field - */ -#define BF_CX_BCNT(bf_cx) ( ((bf_cx) & BF_CX_BCNT_MASK) >> BF_CX_BCNT_POS ) - -/** - * @brief Get lowest bit number in the field - * - * @sa BF_CX - * - * @param[in] bf_cx Complex bit-field - * - * @return Lowest bit number in given bit-field - */ -#define BF_CX_BOFF(bf_cx) ( ((bf_cx) & BF_CX_BOFF_MASK) >> BF_CX_BOFF_POS ) - -/** - * @brief Get bit mask of the selected field - * - * @sa BF_CX - * - * @param[in] bf_cx Complex bit-field - * - * @return Mask of given bit-field - */ -#define BF_CX_MASK(bf_cx) BF_MASK(BF_CX_BCNT(bf_cx), BF_CX_BOFF(bf_cx)) - -/** - * @brief Get bit-field - * - * Macro that extracts selected bit-field from provided value. - * Bit-field is given as a complex value. - * - * @sa BF_CX - * @sa BF_GET - * - * @param[in] val Value from witch selected bit-field would be extracted - * @param[in] bf_cx Complex bit-field - * - * @return Value of the selected bits. - */ -#define BF_CX_GET(val, bf_cx) BF_GET(val, BF_CX_BCNT(bf_cx), BF_CX_BOFF(bf_cx)) - -/** - * @brief Create bit-field value - * - * Value is masked and shifted to match given bit-field. - * - * @param[in] val Value to set on bit-field - * @param[in] bf_cx Complex bit-field - * - * @return Value positioned of given bit-field. - */ -#define BF_CX_VAL(val, bf_cx) BF_VAL(val, BF_CX_BCNT(bf_cx), BF_CX_BOFF(bf_cx)) - -/** - * @brief Extracting data from the brackets - * - * This macro get rid of brackets around the argument. - * It can be used to pass multiple arguments in logical one argument to a macro. - * Call it with arguments inside brackets: - * @code - * #define ARGUMENTS (a, b, c) - * BRACKET_EXTRACT(ARGUMENTS) - * @endcode - * It would produce: - * @code - * a, b, c - * @endcode - * - * @param a Argument with anything inside brackets - * @return Anything that appears inside the brackets of the argument - * - * @note - * The argument of the macro have to be inside brackets. - * In other case the compilation would fail. - */ -#define BRACKET_EXTRACT(a) BRACKET_EXTRACT_(a) -#define BRACKET_EXTRACT_(a) BRACKET_EXTRACT__ a -#define BRACKET_EXTRACT__(...) __VA_ARGS__ - - -/** - * @brief Check if number of parameters is more than 1 - * - * @param ... Arguments to count - * - * @return 0 If argument count is <= 1 - * @return 1 If argument count is > 1 - * - * @sa NUM_VA_ARGS - * @sa NUM_IS_MORE_THAN_1 - */ -#define NUM_VA_ARGS_IS_MORE_THAN_1(...) NUM_IS_MORE_THAN_1(NUM_VA_ARGS(__VA_ARGS__)) - -/** - * @brief Check if given numeric value is bigger than 1 - * - * This macro accepts numeric value, that may be the result of argument expansion. - * This numeric value is then converted to 0 if it is lover than 1 or to 1 if - * its value is higher than 1. - * The generated result can be used to glue it into other macro mnemonic name. - * - * @param N Numeric value to check - * - * @return 0 If argument is <= 1 - * @return 1 If argument is > 1 - * - * @note Any existing definition of a form NUM_IS_MORE_THAN_1_PROBE_[N] can - * broke the result of this macro - */ -#define NUM_IS_MORE_THAN_1(N) NUM_IS_MORE_THAN_1_(N) -#define NUM_IS_MORE_THAN_1_(N) NUM_IS_MORE_THAN_1_PROBE_(NUM_IS_MORE_THAN_1_PROBE_ ## N, 1) -#define NUM_IS_MORE_THAN_1_PROBE_(...) GET_VA_ARG_1(GET_ARGS_AFTER_1(__VA_ARGS__)) -#define NUM_IS_MORE_THAN_1_PROBE_0 ~, 0 -#define NUM_IS_MORE_THAN_1_PROBE_1 ~, 0 - -/** - * @brief Get the first argument - * - * @param ... Arguments to select - * - * @return First argument or empty if no arguments are provided - */ -#define GET_VA_ARG_1(...) GET_VA_ARG_1_(__VA_ARGS__, ) // Make sure that also for 1 argument it works -#define GET_VA_ARG_1_(a1, ...) a1 - -/** - * @brief Get all the arguments but the first one - * - * @param ... Arguments to select - * - * @return All arguments after the first one or empty if less than 2 arguments are provided - */ -#define GET_ARGS_AFTER_1(...) GET_ARGS_AFTER_1_(__VA_ARGS__, ) // Make sure that also for 1 argument it works -#define GET_ARGS_AFTER_1_(a1, ...) __VA_ARGS__ - -/** - * @brief Size of a field in declared structure - * - * Macro that returns the size of the structure field. - * @param struct_type Variable type to get the field size from - * @param field Field name to analyze. It can be even field inside field (field.somethingelse.and_another). - * - * @return Size of the field - */ -#define FIELD_SIZE(struct_type, field) sizeof(((struct struct_type*)NULL)->field) - -/** - * @brief Number of elements in field array in declared structure - * - * Macro that returns number of elementy in structure field. - * @param struct_type Variable type to get the field size from - * @param field Field name to analyze. - * - * @return Number of elements in field array - * - * @sa FIELD_SIZE - */ -#define FIELD_ARRAY_SIZE(struct_type, field) (FIELD_SIZE(struct_type, field) / FIELD_SIZE(struct_type, field[0])) - -/** - * @brief Mapping macro - * - * Macro that process all arguments using given macro - * - * @param ... Macro name to be used for argument processing followed by arguments to process. - * Macro should have following form: MACRO(argument) - * - * @return All arguments processed by given macro - */ -#define MACRO_MAP(...) MACRO_MAP_(__VA_ARGS__) -#define MACRO_MAP_(...) MACRO_MAP_N(NUM_VA_ARGS_LESS_1(__VA_ARGS__), __VA_ARGS__) // To make sure it works also for 2 arguments in total - -/** - * @brief Mapping macro, recursive version - * - * Can be used in @ref MACRO_MAP macro - */ -#define MACRO_MAP_REC(...) MACRO_MAP_REC_(__VA_ARGS__) -#define MACRO_MAP_REC_(...) MACRO_MAP_REC_N(NUM_VA_ARGS_LESS_1(__VA_ARGS__), __VA_ARGS__) // To make sure it works also for 2 arguments in total -/** - * @brief Mapping N arguments macro - * - * Macro similar to @ref MACRO_MAP but maps exact number of arguments. - * If there is more arguments given, the rest would be ignored. - * - * @param N Number of arguments to map - * @param ... Macro name to be used for argument processing followed by arguments to process. - * Macro should have following form: MACRO(argument) - * - * @return Selected number of arguments processed by given macro - */ -#define MACRO_MAP_N(N, ...) MACRO_MAP_N_(N, __VA_ARGS__) -#define MACRO_MAP_N_(N, ...) CONCAT_2(MACRO_MAP_, N)(__VA_ARGS__, ) - -/** - * @brief Mapping N arguments macro, recursive version - * - * Can be used in @ref MACRO_MAP_N macro - */ -#define MACRO_MAP_REC_N(N, ...) MACRO_MAP_REC_N_(N, __VA_ARGS__) -#define MACRO_MAP_REC_N_(N, ...) CONCAT_2(MACRO_MAP_REC_, N)(__VA_ARGS__, ) - -#define MACRO_MAP_0( ...) -#define MACRO_MAP_1( macro, a, ...) macro(a) -#define MACRO_MAP_2( macro, a, ...) macro(a) MACRO_MAP_1 (macro, __VA_ARGS__, ) -#define MACRO_MAP_3( macro, a, ...) macro(a) MACRO_MAP_2 (macro, __VA_ARGS__, ) -#define MACRO_MAP_4( macro, a, ...) macro(a) MACRO_MAP_3 (macro, __VA_ARGS__, ) -#define MACRO_MAP_5( macro, a, ...) macro(a) MACRO_MAP_4 (macro, __VA_ARGS__, ) -#define MACRO_MAP_6( macro, a, ...) macro(a) MACRO_MAP_5 (macro, __VA_ARGS__, ) -#define MACRO_MAP_7( macro, a, ...) macro(a) MACRO_MAP_6 (macro, __VA_ARGS__, ) -#define MACRO_MAP_8( macro, a, ...) macro(a) MACRO_MAP_7 (macro, __VA_ARGS__, ) -#define MACRO_MAP_9( macro, a, ...) macro(a) MACRO_MAP_8 (macro, __VA_ARGS__, ) -#define MACRO_MAP_10(macro, a, ...) macro(a) MACRO_MAP_9 (macro, __VA_ARGS__, ) -#define MACRO_MAP_11(macro, a, ...) macro(a) MACRO_MAP_10(macro, __VA_ARGS__, ) -#define MACRO_MAP_12(macro, a, ...) macro(a) MACRO_MAP_11(macro, __VA_ARGS__, ) -#define MACRO_MAP_13(macro, a, ...) macro(a) MACRO_MAP_12(macro, __VA_ARGS__, ) -#define MACRO_MAP_14(macro, a, ...) macro(a) MACRO_MAP_13(macro, __VA_ARGS__, ) -#define MACRO_MAP_15(macro, a, ...) macro(a) MACRO_MAP_14(macro, __VA_ARGS__, ) - -#define MACRO_MAP_REC_0( ...) -#define MACRO_MAP_REC_1( macro, a, ...) macro(a) -#define MACRO_MAP_REC_2( macro, a, ...) macro(a) MACRO_MAP_REC_1 (macro, __VA_ARGS__, ) -#define MACRO_MAP_REC_3( macro, a, ...) macro(a) MACRO_MAP_REC_2 (macro, __VA_ARGS__, ) -#define MACRO_MAP_REC_4( macro, a, ...) macro(a) MACRO_MAP_REC_3 (macro, __VA_ARGS__, ) -#define MACRO_MAP_REC_5( macro, a, ...) macro(a) MACRO_MAP_REC_4 (macro, __VA_ARGS__, ) -#define MACRO_MAP_REC_6( macro, a, ...) macro(a) MACRO_MAP_REC_5 (macro, __VA_ARGS__, ) -#define MACRO_MAP_REC_7( macro, a, ...) macro(a) MACRO_MAP_REC_6 (macro, __VA_ARGS__, ) -#define MACRO_MAP_REC_8( macro, a, ...) macro(a) MACRO_MAP_REC_7 (macro, __VA_ARGS__, ) -#define MACRO_MAP_REC_9( macro, a, ...) macro(a) MACRO_MAP_REC_8 (macro, __VA_ARGS__, ) -#define MACRO_MAP_REC_10(macro, a, ...) macro(a) MACRO_MAP_REC_9 (macro, __VA_ARGS__, ) -#define MACRO_MAP_REC_11(macro, a, ...) macro(a) MACRO_MAP_REC_10(macro, __VA_ARGS__, ) -#define MACRO_MAP_REC_12(macro, a, ...) macro(a) MACRO_MAP_REC_11(macro, __VA_ARGS__, ) -#define MACRO_MAP_REC_13(macro, a, ...) macro(a) MACRO_MAP_REC_12(macro, __VA_ARGS__, ) -#define MACRO_MAP_REC_14(macro, a, ...) macro(a) MACRO_MAP_REC_13(macro, __VA_ARGS__, ) -#define MACRO_MAP_REC_15(macro, a, ...) macro(a) MACRO_MAP_REC_14(macro, __VA_ARGS__, ) - -/** - * @brief Mapping macro with current index - * - * Basically macro similar to @ref MACRO_MAP, but the processing function would get an argument - * and current argument index (beginning from 0). - * - * @param ... Macro name to be used for argument processing followed by arguments to process. - * Macro should have following form: MACRO(argument, index) - * @return All arguments processed by given macro - */ -#define MACRO_MAP_FOR(...) MACRO_MAP_FOR_(__VA_ARGS__) -#define MACRO_MAP_FOR_N_LIST 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -#define MACRO_MAP_FOR_(...) MACRO_MAP_FOR_N(NUM_VA_ARGS_LESS_1(__VA_ARGS__), __VA_ARGS__) - -/** - * @brief Mapping N arguments macro with current index - * - * Macro is similar to @ref MACRO_MAP_FOR but maps exact number of arguments. - * If there is more arguments given, the rest would be ignored. - * - * @param N Number of arguments to map - * @param ... Macro name to be used for argument processing followed by arguments to process. - * Macro should have following form: MACRO(argument, index) - * - * @return Selected number of arguments processed by given macro - */ -#define MACRO_MAP_FOR_N(N, ...) MACRO_MAP_FOR_N_(N, __VA_ARGS__) -#define MACRO_MAP_FOR_N_(N, ...) CONCAT_2(MACRO_MAP_FOR_, N)((MACRO_MAP_FOR_N_LIST), __VA_ARGS__, ) - -#define MACRO_MAP_FOR_0( n_list, ...) -#define MACRO_MAP_FOR_1( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) -#define MACRO_MAP_FOR_2( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_1 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) -#define MACRO_MAP_FOR_3( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_2 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) -#define MACRO_MAP_FOR_4( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_3 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) -#define MACRO_MAP_FOR_5( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_4 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) -#define MACRO_MAP_FOR_6( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_5 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) -#define MACRO_MAP_FOR_7( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_6 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) -#define MACRO_MAP_FOR_8( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_7 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) -#define MACRO_MAP_FOR_9( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_8 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) -#define MACRO_MAP_FOR_10(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_9 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) -#define MACRO_MAP_FOR_11(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_10((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) -#define MACRO_MAP_FOR_12(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_11((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) -#define MACRO_MAP_FOR_13(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_12((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) -#define MACRO_MAP_FOR_14(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_13((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) -#define MACRO_MAP_FOR_15(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_14((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) - - -/** - * @brief Mapping macro with current index and parameter - * - * Version of @ref MACRO_MAP_FOR that passes also the same parameter to all macros. - * - * @param param Parameter that would be passed to each macro call during mapping. - * @param ... Macro name to be used for argument processing followed by arguments to process. - * Macro should have following form: MACRO(argument, index, param) - * - * @return All arguments processed by given macro - */ -#define MACRO_MAP_FOR_PARAM(param, ...) MACRO_MAP_FOR_PARAM_(param, __VA_ARGS__) -#define MACRO_MAP_FOR_PARAM_(param, ...) MACRO_MAP_FOR_PARAM_N(NUM_VA_ARGS_LESS_1(__VA_ARGS__), param, __VA_ARGS__) - -/** - * @brief Mapping N arguments macro with with current index and parameter - * - * @param N Number of arguments to map - * @param param Parameter that would be passed to each macro call during mapping. - * @param ... Macro name to be used for argument processing followed by arguments to process. - * Macro should have following form: MACRO(argument, index, param) - * - * @return All arguments processed by given macro - */ -#define MACRO_MAP_FOR_PARAM_N(N, param, ...) MACRO_MAP_FOR_PARAM_N_(N, param, __VA_ARGS__) -#define MACRO_MAP_FOR_PARAM_N_(N, param, ...) CONCAT_2(MACRO_MAP_FOR_PARAM_, N)((MACRO_MAP_FOR_N_LIST), param, __VA_ARGS__, ) - - -#define MACRO_MAP_FOR_PARAM_0( n_list, param, ...) -#define MACRO_MAP_FOR_PARAM_1( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) -#define MACRO_MAP_FOR_PARAM_2( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_1 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) -#define MACRO_MAP_FOR_PARAM_3( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_2 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) -#define MACRO_MAP_FOR_PARAM_4( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_3 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) -#define MACRO_MAP_FOR_PARAM_5( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_4 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) -#define MACRO_MAP_FOR_PARAM_6( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_5 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) -#define MACRO_MAP_FOR_PARAM_7( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_6 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) -#define MACRO_MAP_FOR_PARAM_8( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_7 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) -#define MACRO_MAP_FOR_PARAM_9( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_8 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) -#define MACRO_MAP_FOR_PARAM_10(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_9 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) -#define MACRO_MAP_FOR_PARAM_11(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_10((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) -#define MACRO_MAP_FOR_PARAM_12(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_11((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) -#define MACRO_MAP_FOR_PARAM_13(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_12((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) -#define MACRO_MAP_FOR_PARAM_14(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_13((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) -#define MACRO_MAP_FOR_PARAM_15(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_14((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) - - -/** - * @brief Repeating macro. - * - * @param count Count of repeats. - * @param macro Macro must have the following form: MACRO(arguments). - * @param ... Arguments passed to the macro. - * - * @return All arguments processed by the given macro. - */ -#define MACRO_REPEAT(count, macro, ...) MACRO_REPEAT_(count, macro, __VA_ARGS__) -#define MACRO_REPEAT_(count, macro, ...) CONCAT_2(MACRO_REPEAT_, count)(macro, __VA_ARGS__) - -#define MACRO_REPEAT_0(macro, ...) -#define MACRO_REPEAT_1(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_0(macro, __VA_ARGS__) -#define MACRO_REPEAT_2(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_1(macro, __VA_ARGS__) -#define MACRO_REPEAT_3(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_2(macro, __VA_ARGS__) -#define MACRO_REPEAT_4(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_3(macro, __VA_ARGS__) -#define MACRO_REPEAT_5(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_4(macro, __VA_ARGS__) -#define MACRO_REPEAT_6(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_5(macro, __VA_ARGS__) -#define MACRO_REPEAT_7(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_6(macro, __VA_ARGS__) -#define MACRO_REPEAT_8(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_7(macro, __VA_ARGS__) -#define MACRO_REPEAT_9(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_8(macro, __VA_ARGS__) -#define MACRO_REPEAT_10(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_9(macro, __VA_ARGS__) -#define MACRO_REPEAT_11(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_10(macro, __VA_ARGS__) -#define MACRO_REPEAT_12(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_11(macro, __VA_ARGS__) -#define MACRO_REPEAT_13(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_12(macro, __VA_ARGS__) -#define MACRO_REPEAT_14(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_13(macro, __VA_ARGS__) -#define MACRO_REPEAT_15(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_14(macro, __VA_ARGS__) - - -/** - * @brief Repeating macro with current index. - * - * Macro similar to @ref MACRO_REPEAT but the processing function gets the arguments - * and the current argument index (beginning from 0). - - * @param count Count of repeats. - * @param macro Macro must have the following form: MACRO(index, arguments). - * @param ... Arguments passed to the macro. - * - * @return All arguments processed by the given macro. - */ -#define MACRO_REPEAT_FOR(count, macro, ...) MACRO_REPEAT_FOR_(count, macro, __VA_ARGS__) -#define MACRO_REPEAT_FOR_(count, macro, ...) CONCAT_2(MACRO_REPEAT_FOR_, count)((MACRO_MAP_FOR_N_LIST), macro, __VA_ARGS__) - -#define MACRO_REPEAT_FOR_0(n_list, macro, ...) -#define MACRO_REPEAT_FOR_1(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_0((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) -#define MACRO_REPEAT_FOR_2(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_1((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) -#define MACRO_REPEAT_FOR_3(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_2((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) -#define MACRO_REPEAT_FOR_4(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_3((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) -#define MACRO_REPEAT_FOR_5(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_4((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) -#define MACRO_REPEAT_FOR_6(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_5((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) -#define MACRO_REPEAT_FOR_7(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_6((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) -#define MACRO_REPEAT_FOR_8(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_7((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) -#define MACRO_REPEAT_FOR_9(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_8((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) -#define MACRO_REPEAT_FOR_10(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_9((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) -#define MACRO_REPEAT_FOR_11(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_10((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) -#define MACRO_REPEAT_FOR_12(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_11((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) -#define MACRO_REPEAT_FOR_13(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_12((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) -#define MACRO_REPEAT_FOR_14(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_13((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) -#define MACRO_REPEAT_FOR_15(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_14((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) - -/**@brief Adding curly brace to the macro parameter. - * - * Useful in array of structures initialization. - * - * @param p Parameter to put into the curly brace. */ -#define PARAM_CBRACE(p) { p }, - - -/**@brief Function for changing the value unit. - * - * @param[in] value Value to be rescaled. - * @param[in] old_unit_reversal Reversal of the incoming unit. - * @param[in] new_unit_reversal Reversal of the desired unit. - * - * @return Number of bytes written. - */ -static __INLINE uint64_t value_rescale(uint32_t value, uint32_t old_unit_reversal, uint16_t new_unit_reversal) -{ - return (uint64_t)ROUNDED_DIV((uint64_t)value * new_unit_reversal, old_unit_reversal); -} - -/**@brief Function for encoding a uint16 value. - * - * @param[in] value Value to be encoded. - * @param[out] p_encoded_data Buffer where the encoded data is to be written. - * - * @return Number of bytes written. - */ -static __INLINE uint8_t uint16_encode(uint16_t value, uint8_t * p_encoded_data) -{ - p_encoded_data[0] = (uint8_t) ((value & 0x00FF) >> 0); - p_encoded_data[1] = (uint8_t) ((value & 0xFF00) >> 8); - return sizeof(uint16_t); -} - -/**@brief Function for encoding a three-byte value. - * - * @param[in] value Value to be encoded. - * @param[out] p_encoded_data Buffer where the encoded data is to be written. - * - * @return Number of bytes written. - */ -static __INLINE uint8_t uint24_encode(uint32_t value, uint8_t * p_encoded_data) -{ - p_encoded_data[0] = (uint8_t) ((value & 0x000000FF) >> 0); - p_encoded_data[1] = (uint8_t) ((value & 0x0000FF00) >> 8); - p_encoded_data[2] = (uint8_t) ((value & 0x00FF0000) >> 16); - return 3; -} - -/**@brief Function for encoding a uint32 value. - * - * @param[in] value Value to be encoded. - * @param[out] p_encoded_data Buffer where the encoded data is to be written. - * - * @return Number of bytes written. - */ -static __INLINE uint8_t uint32_encode(uint32_t value, uint8_t * p_encoded_data) -{ - p_encoded_data[0] = (uint8_t) ((value & 0x000000FF) >> 0); - p_encoded_data[1] = (uint8_t) ((value & 0x0000FF00) >> 8); - p_encoded_data[2] = (uint8_t) ((value & 0x00FF0000) >> 16); - p_encoded_data[3] = (uint8_t) ((value & 0xFF000000) >> 24); - return sizeof(uint32_t); -} - -/**@brief Function for encoding a uint40 value. - * - * @param[in] value Value to be encoded. - * @param[out] p_encoded_data Buffer where the encoded data is to be written. - * - * @return Number of bytes written. - */ -static __INLINE uint8_t uint40_encode(uint64_t value, uint8_t * p_encoded_data) -{ - p_encoded_data[0] = (uint8_t) ((value & 0x00000000FF) >> 0); - p_encoded_data[1] = (uint8_t) ((value & 0x000000FF00) >> 8); - p_encoded_data[2] = (uint8_t) ((value & 0x0000FF0000) >> 16); - p_encoded_data[3] = (uint8_t) ((value & 0x00FF000000) >> 24); - p_encoded_data[4] = (uint8_t) ((value & 0xFF00000000) >> 32); - return 5; -} - -/**@brief Function for encoding a uint48 value. - * - * @param[in] value Value to be encoded. - * @param[out] p_encoded_data Buffer where the encoded data is to be written. - * - * @return Number of bytes written. - */ -static __INLINE uint8_t uint48_encode(uint64_t value, uint8_t * p_encoded_data) -{ - p_encoded_data[0] = (uint8_t) ((value & 0x0000000000FF) >> 0); - p_encoded_data[1] = (uint8_t) ((value & 0x00000000FF00) >> 8); - p_encoded_data[2] = (uint8_t) ((value & 0x000000FF0000) >> 16); - p_encoded_data[3] = (uint8_t) ((value & 0x0000FF000000) >> 24); - p_encoded_data[4] = (uint8_t) ((value & 0x00FF00000000) >> 32); - p_encoded_data[5] = (uint8_t) ((value & 0xFF0000000000) >> 40); - return 6; -} - -/**@brief Function for decoding a uint16 value. - * - * @param[in] p_encoded_data Buffer where the encoded data is stored. - * - * @return Decoded value. - */ -static __INLINE uint16_t uint16_decode(const uint8_t * p_encoded_data) -{ - return ( (((uint16_t)((uint8_t *)p_encoded_data)[0])) | - (((uint16_t)((uint8_t *)p_encoded_data)[1]) << 8 )); -} - -/**@brief Function for decoding a uint16 value in big-endian format. - * - * @param[in] p_encoded_data Buffer where the encoded data is stored. - * - * @return Decoded value. - */ -static __INLINE uint16_t uint16_big_decode(const uint8_t * p_encoded_data) -{ - return ( (((uint16_t)((uint8_t *)p_encoded_data)[0]) << 8 ) | - (((uint16_t)((uint8_t *)p_encoded_data)[1])) ); -} - -/**@brief Function for decoding a three-byte value. - * - * @param[in] p_encoded_data Buffer where the encoded data is stored. - * - * @return Decoded value (uint32_t). - */ -static __INLINE uint32_t uint24_decode(const uint8_t * p_encoded_data) -{ - return ( (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0) | - (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8) | - (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16)); -} - -/**@brief Function for decoding a uint32 value. - * - * @param[in] p_encoded_data Buffer where the encoded data is stored. - * - * @return Decoded value. - */ -static __INLINE uint32_t uint32_decode(const uint8_t * p_encoded_data) -{ - return ( (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0) | - (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8) | - (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16) | - (((uint32_t)((uint8_t *)p_encoded_data)[3]) << 24 )); -} - -/**@brief Function for decoding a uint32 value in big-endian format. - * - * @param[in] p_encoded_data Buffer where the encoded data is stored. - * - * @return Decoded value. - */ -static __INLINE uint32_t uint32_big_decode(const uint8_t * p_encoded_data) -{ - return ( (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 24) | - (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 16) | - (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 8) | - (((uint32_t)((uint8_t *)p_encoded_data)[3]) << 0) ); -} - -/** - * @brief Function for encoding an uint16 value in big-endian format. - * - * @param[in] value Value to be encoded. - * @param[out] p_encoded_data Buffer where the encoded data will be written. - * - * @return Number of bytes written. - */ -static __INLINE uint8_t uint16_big_encode(uint16_t value, uint8_t * p_encoded_data) -{ - p_encoded_data[0] = (uint8_t) (value >> 8); - p_encoded_data[1] = (uint8_t) (value & 0xFF); - - return sizeof(uint16_t); -} - -/*lint -esym(526, __rev) */ -/*lint -esym(628, __rev) */ -/**@brief Function for encoding a uint32 value in big-endian format. - * - * @param[in] value Value to be encoded. - * @param[out] p_encoded_data Buffer where the encoded data will be written. - * - * @return Number of bytes written. - */ -static __INLINE uint8_t uint32_big_encode(uint32_t value, uint8_t * p_encoded_data) -{ - *(uint32_t *)p_encoded_data = __REV(value); - return sizeof(uint32_t); -} - -/**@brief Function for decoding a uint40 value. - * - * @param[in] p_encoded_data Buffer where the encoded data is stored. - * - * @return Decoded value. (uint64_t) - */ -static __INLINE uint64_t uint40_decode(const uint8_t * p_encoded_data) -{ - return ( (((uint64_t)((uint8_t *)p_encoded_data)[0]) << 0) | - (((uint64_t)((uint8_t *)p_encoded_data)[1]) << 8) | - (((uint64_t)((uint8_t *)p_encoded_data)[2]) << 16) | - (((uint64_t)((uint8_t *)p_encoded_data)[3]) << 24) | - (((uint64_t)((uint8_t *)p_encoded_data)[4]) << 32 )); -} - -/**@brief Function for decoding a uint48 value. - * - * @param[in] p_encoded_data Buffer where the encoded data is stored. - * - * @return Decoded value. (uint64_t) - */ -static __INLINE uint64_t uint48_decode(const uint8_t * p_encoded_data) -{ - return ( (((uint64_t)((uint8_t *)p_encoded_data)[0]) << 0) | - (((uint64_t)((uint8_t *)p_encoded_data)[1]) << 8) | - (((uint64_t)((uint8_t *)p_encoded_data)[2]) << 16) | - (((uint64_t)((uint8_t *)p_encoded_data)[3]) << 24) | - (((uint64_t)((uint8_t *)p_encoded_data)[4]) << 32) | - (((uint64_t)((uint8_t *)p_encoded_data)[5]) << 40 )); -} - -/** @brief Function for converting the input voltage (in milli volts) into percentage of 3.0 Volts. - * - * @details The calculation is based on a linearized version of the battery's discharge - * curve. 3.0V returns 100% battery level. The limit for power failure is 2.1V and - * is considered to be the lower boundary. - * - * The discharge curve for CR2032 is non-linear. In this model it is split into - * 4 linear sections: - * - Section 1: 3.0V - 2.9V = 100% - 42% (58% drop on 100 mV) - * - Section 2: 2.9V - 2.74V = 42% - 18% (24% drop on 160 mV) - * - Section 3: 2.74V - 2.44V = 18% - 6% (12% drop on 300 mV) - * - Section 4: 2.44V - 2.1V = 6% - 0% (6% drop on 340 mV) - * - * These numbers are by no means accurate. Temperature and - * load in the actual application is not accounted for! - * - * @param[in] mvolts The voltage in mV - * - * @return Battery level in percent. -*/ -static __INLINE uint8_t battery_level_in_percent(const uint16_t mvolts) -{ - uint8_t battery_level; - - if (mvolts >= 3000) - { - battery_level = 100; - } - else if (mvolts > 2900) - { - battery_level = 100 - ((3000 - mvolts) * 58) / 100; - } - else if (mvolts > 2740) - { - battery_level = 42 - ((2900 - mvolts) * 24) / 160; - } - else if (mvolts > 2440) - { - battery_level = 18 - ((2740 - mvolts) * 12) / 300; - } - else if (mvolts > 2100) - { - battery_level = 6 - ((2440 - mvolts) * 6) / 340; - } - else - { - battery_level = 0; - } - - return battery_level; -} - -/**@brief Function for checking if a pointer value is aligned to a 4 byte boundary. - * - * @param[in] p Pointer value to be checked. - * - * @return TRUE if pointer is aligned to a 4 byte boundary, FALSE otherwise. - */ -static __INLINE bool is_word_aligned(void const* p) -{ - return (((uintptr_t)p & 0x03) == 0); -} - -/*lint -e{568, 685} */ -/** - * @brief Function for checking if provided address is located in stack space. - * - * @param[in] ptr Pointer to be checked. - * - * @return true if address is in stack space, false otherwise. - */ -static __INLINE bool is_address_from_stack(void * ptr) -{ - if (((uint32_t)ptr >= (uint32_t)STACK_BASE) && - ((uint32_t)ptr < (uint32_t)STACK_TOP) ) - { - return true; - } - else - { - return false; - } -} - -#ifdef __cplusplus -} -#endif - -#endif // APP_UTIL_H__ - -/** @} */ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/util/app_util_bds.h b/bsp/boards/nrf52840/sdk/components/libraries/util/app_util_bds.h deleted file mode 100644 index 5118a7c487..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/util/app_util_bds.h +++ /dev/null @@ -1,449 +0,0 @@ -/** - * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -/** @file - * - * @defgroup app_util Utility Functions and Definitions - * @{ - * @ingroup app_common - * - * @brief Various types and definitions available to all applications. - */ - -#ifndef APP_UTIL_BDS_H__ -#define APP_UTIL_BDS_H__ - -#include -#include -#include -#include "compiler_abstraction.h" -#include "app_util.h" -#include "ble_srv_common.h" -#include "nordic_common.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef uint8_t nibble_t; -typedef uint32_t uint24_t; -typedef uint64_t uint40_t; - -/**@brief IEEE 11073-20601 Regulatory Certification Data List Structure */ -typedef struct -{ - uint8_t * p_list; /**< Pointer the byte array containing the encoded opaque structure based on IEEE 11073-20601 specification. */ - uint8_t list_len; /**< Length of the byte array. */ -} regcertdatalist_t; - -/**@brief SFLOAT format (IEEE-11073 16-bit FLOAT, meaning 4 bits for exponent (base 10) and 12 bits mantissa) */ -typedef struct -{ - int8_t exponent; /**< Base 10 exponent, should be using only 4 bits */ - int16_t mantissa; /**< Mantissa, should be using only 12 bits */ -} sfloat_t; - -/**@brief Date and Time structure. */ -typedef struct -{ - uint16_t year; - uint8_t month; - uint8_t day; - uint8_t hours; - uint8_t minutes; - uint8_t seconds; -} ble_date_time_t; - - -/**@brief Function for encoding a uint16 value. - * - * @param[in] p_value Value to be encoded. - * @param[out] p_encoded_data Buffer where the encoded data is to be written. - * - * @return Number of bytes written. - */ -static __INLINE uint8_t bds_uint16_encode(const uint16_t * p_value, uint8_t * p_encoded_data) -{ - p_encoded_data[0] = (uint8_t) ((*p_value & 0x00FF) >> 0); - p_encoded_data[1] = (uint8_t) ((*p_value & 0xFF00) >> 8); - return sizeof(uint16_t); -} - -static __INLINE uint8_t bds_int16_encode(const int16_t * p_value, uint8_t * p_encoded_data) -{ - uint16_t tmp = *p_value; - return bds_uint16_encode(&tmp, p_encoded_data); -} - -/**@brief Function for encoding a uint24 value. - * - * @param[in] p_value Value to be encoded. - * @param[out] p_encoded_data Buffer where the encoded data is to be written. - * - * @return Number of bytes written. - */ -static __INLINE uint8_t bds_uint24_encode(const uint32_t * p_value, uint8_t * p_encoded_data) -{ - p_encoded_data[0] = (uint8_t) ((*p_value & 0x000000FF) >> 0); - p_encoded_data[1] = (uint8_t) ((*p_value & 0x0000FF00) >> 8); - p_encoded_data[2] = (uint8_t) ((*p_value & 0x00FF0000) >> 16); - return (3); -} - - -/**@brief Function for encoding a uint32 value. - * - * @param[in] p_value Value to be encoded. - * @param[out] p_encoded_data Buffer where the encoded data is to be written. - * - * @return Number of bytes written. - */ -static __INLINE uint8_t bds_uint32_encode(const uint32_t * p_value, uint8_t * p_encoded_data) -{ - p_encoded_data[0] = (uint8_t) ((*p_value & 0x000000FF) >> 0); - p_encoded_data[1] = (uint8_t) ((*p_value & 0x0000FF00) >> 8); - p_encoded_data[2] = (uint8_t) ((*p_value & 0x00FF0000) >> 16); - p_encoded_data[3] = (uint8_t) ((*p_value & 0xFF000000) >> 24); - return sizeof(uint32_t); -} - - -/**@brief Function for encoding a uint40 value. - * - * @param[in] p_value Value to be encoded. - * @param[out] p_encoded_data Buffer where the encoded data is to be written. - * - * @return Number of bytes written. - */ -static __INLINE uint8_t bds_uint40_encode(const uint64_t * p_value, uint8_t * p_encoded_data) -{ - p_encoded_data[0] = (uint8_t) ((*p_value & 0x00000000000000FF) >> 0); - p_encoded_data[1] = (uint8_t) ((*p_value & 0x000000000000FF00) >> 8); - p_encoded_data[2] = (uint8_t) ((*p_value & 0x0000000000FF0000) >> 16); - p_encoded_data[3] = (uint8_t) ((*p_value & 0x00000000FF000000) >> 24); - p_encoded_data[4] = (uint8_t) ((*p_value & 0x000000FF00000000) >> 32); - return 5; -} - -/**@brief Function for encoding a sfloat value. - * - * @param[in] p_value Value to be encoded. - * @param[out] p_encoded_data Buffer where the encoded data is to be written. - * - * @return Number of bytes written. - */ -static __INLINE uint8_t bds_sfloat_encode(const sfloat_t * p_value, uint8_t * p_encoded_data) -{ - uint16_t encoded_val; - - encoded_val = ((p_value->exponent << 12) & 0xF000) | - ((p_value->mantissa << 0) & 0x0FFF); - - return(bds_uint16_encode(&encoded_val, p_encoded_data)); -} - - -/**@brief Function for encoding a uint8_array value. - * - * @param[in] p_value Value to be encoded. - * @param[out] p_encoded_data Buffer where the encoded data is to be written. - */ -static __INLINE uint8_t bds_uint8_array_encode(const uint8_array_t * p_value, - uint8_t * p_encoded_data) -{ - memcpy(p_encoded_data, p_value->p_data, p_value->size); - return p_value->size; -} - - -/**@brief Function for encoding a utf8_str value. - * - * @param[in] p_value Value to be encoded. - * @param[out] p_encoded_data Buffer where the encoded data is to be written. - - */ -static __INLINE uint8_t bds_ble_srv_utf8_str_encode(const ble_srv_utf8_str_t * p_value, - uint8_t * p_encoded_data) -{ - memcpy(p_encoded_data, p_value->p_str, p_value->length); - return p_value->length; -} - -/**@brief Function for encoding a regcertdatalist value. - * - * @param[in] p_value Value to be encoded. - * @param[out] p_encoded_data Buffer where the encoded data is to be written. - - */ -static __INLINE uint8_t bds_regcertdatalist_encode(const regcertdatalist_t * p_value, - uint8_t * p_encoded_data) -{ - memcpy(p_encoded_data, p_value->p_list, p_value->list_len); - return p_value->list_len; -} - - -/**@brief Function for decoding a date_time value. - * - * @param[in] p_date_time pointer to the date_time structure to encode. - * @param[in] p_encoded_data pointer to the encoded data - * @return length of the encoded field. - */ -static __INLINE uint8_t bds_ble_date_time_encode(const ble_date_time_t * p_date_time, - uint8_t * p_encoded_data) -{ - uint8_t len = bds_uint16_encode(&p_date_time->year, &p_encoded_data[0]); - - p_encoded_data[len++] = p_date_time->month; - p_encoded_data[len++] = p_date_time->day; - p_encoded_data[len++] = p_date_time->hours; - p_encoded_data[len++] = p_date_time->minutes; - p_encoded_data[len++] = p_date_time->seconds; - - return len; -} - - -/**@brief Function for decoding a uint16 value. - * - * @param[in] len length of the field to be decoded. - * @param[in] p_encoded_data Buffer where the encoded data is stored. - * @param[in] p_decoded_val pointer to the decoded value - * @return length of the decoded field. - */ -static __INLINE uint8_t bds_uint16_decode(const uint8_t len, - const uint8_t * p_encoded_data, - uint16_t * p_decoded_val) -{ - UNUSED_VARIABLE(len); - *p_decoded_val = (((uint16_t)((uint8_t *)p_encoded_data)[0])) | - (((uint16_t)((uint8_t *)p_encoded_data)[1]) << 8 ); - return (sizeof(uint16_t)); -} - - -/**@brief Function for decoding a int16 value. - * - * @param[in] len length of the field to be decoded. - * @param[in] p_encoded_data Buffer where the encoded data is stored. - * @param[in] p_decoded_val pointer to the decoded value - * @return length of the decoded field. - */ -static __INLINE uint8_t bds_int16_decode(const uint8_t len, - const uint8_t * p_encoded_data, - int16_t * p_decoded_val) -{ - UNUSED_VARIABLE(len); - uint16_t tmp = 0; - uint8_t retval = bds_uint16_decode(len, p_encoded_data, &tmp); - *p_decoded_val = (int16_t)tmp; - return retval; -} - - -/**@brief Function for decoding a uint24 value. - * - * @param[in] len length of the field to be decoded. - * @param[in] p_encoded_data Buffer where the encoded data is stored. - * @param[in] p_decoded_val pointer to the decoded value - * - * @return length of the decoded field. - */ -static __INLINE uint8_t bds_uint24_decode(const uint8_t len, - const uint8_t * p_encoded_data, - uint32_t * p_decoded_val) -{ - UNUSED_VARIABLE(len); - *p_decoded_val = (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0) | - (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8) | - (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16); - return (3); -} - - -/**@brief Function for decoding a uint32 value. - * - * @param[in] len length of the field to be decoded. - * @param[in] p_encoded_data Buffer where the encoded data is stored. - * @param[in] p_decoded_val pointer to the decoded value - * - * @return length of the decoded field. - */ -static __INLINE uint8_t bds_uint32_decode(const uint8_t len, - const uint8_t * p_encoded_data, - uint32_t * p_decoded_val) -{ - UNUSED_VARIABLE(len); - *p_decoded_val = (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0) | - (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8) | - (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16) | - (((uint32_t)((uint8_t *)p_encoded_data)[3]) << 24 ); - return (sizeof(uint32_t)); -} - - -/**@brief Function for decoding a uint40 value. - * - * @param[in] len length of the field to be decoded. - * @param[in] p_encoded_data Buffer where the encoded data is stored. - * @param[in] p_decoded_val pointer to the decoded value - * - * @return length of the decoded field. - */ -static __INLINE uint8_t bds_uint40_decode(const uint8_t len, - const uint8_t * p_encoded_data, - uint64_t * p_decoded_val) -{ - UNUSED_VARIABLE(len); - *p_decoded_val = (((uint64_t)((uint8_t *)p_encoded_data)[0]) << 0) | - (((uint64_t)((uint8_t *)p_encoded_data)[1]) << 8) | - (((uint64_t)((uint8_t *)p_encoded_data)[2]) << 16) | - (((uint64_t)((uint8_t *)p_encoded_data)[3]) << 24 )| - (((uint64_t)((uint8_t *)p_encoded_data)[4]) << 32 ); - return (40); -} - - -/**@brief Function for decoding a sfloat value. - * - * @param[in] len length of the field to be decoded. - * @param[in] p_encoded_data Buffer where the encoded data is stored. - * @param[in] p_decoded_val pointer to the decoded value - * - * @return length of the decoded field. - - */ -static __INLINE uint8_t bds_sfloat_decode(const uint8_t len, - const uint8_t * p_encoded_data, - sfloat_t * p_decoded_val) -{ - - p_decoded_val->exponent = 0; - bds_uint16_decode(len, p_encoded_data, (uint16_t*)&p_decoded_val->mantissa); - p_decoded_val->exponent = (uint8_t)((p_decoded_val->mantissa & 0xF000) >> 12); - p_decoded_val->mantissa &= 0x0FFF; - return len; -} - - -/**@brief Function for decoding a uint8_array value. - * - * @param[in] len length of the field to be decoded. - * @param[in] p_encoded_data Buffer where the encoded data is stored. - * @param[in] p_decoded_val pointer to the decoded value - * - * @return length of the decoded field. - */ -static __INLINE uint8_t bds_uint8_array_decode(const uint8_t len, - const uint8_t * p_encoded_data, - uint8_array_t * p_decoded_val) -{ - memcpy(p_decoded_val->p_data, p_encoded_data, len); - p_decoded_val->size = len; - return p_decoded_val->size; -} - - -/**@brief Function for decoding a utf8_str value. - * - * @param[in] len length of the field to be decoded. - * @param[in] p_encoded_data Buffer where the encoded data is stored. - * @param[in] p_decoded_val pointer to the decoded value - * - * @return length of the decoded field. - */ -static __INLINE uint8_t bds_ble_srv_utf8_str_decode(const uint8_t len, - const uint8_t * p_encoded_data, - ble_srv_utf8_str_t * p_decoded_val) -{ - p_decoded_val->p_str = (uint8_t*)p_encoded_data; - p_decoded_val->length = len; - return p_decoded_val->length; -} - - -/**@brief Function for decoding a regcertdatalist value. - * - * @param[in] len length of the field to be decoded. - * @param[in] p_encoded_data Buffer where the encoded data is stored. - * @param[in] p_decoded_val pointer to the decoded value - * - * @return length of the decoded field. - */ -static __INLINE uint8_t bds_regcertdatalist_decode(const uint8_t len, - const uint8_t * p_encoded_data, - regcertdatalist_t * p_decoded_val) -{ - memcpy(p_decoded_val->p_list, p_encoded_data, len); - p_decoded_val->list_len = len; - return p_decoded_val->list_len; -} - - -/**@brief Function for decoding a date_time value. - * - * @param[in] len length of the field to be decoded. - * @param[in] p_encoded_data Buffer where the encoded data is stored. - * @param[in] p_date_time pointer to the decoded value - * - * @return length of the decoded field. - */ -static __INLINE uint8_t bds_ble_date_time_decode(const uint8_t len, - const uint8_t * p_encoded_data, - ble_date_time_t * p_date_time) -{ - UNUSED_VARIABLE(len); - uint8_t pos = bds_uint16_decode(len, &p_encoded_data[0], &p_date_time->year); - p_date_time->month = p_encoded_data[pos++]; - p_date_time->day = p_encoded_data[pos++]; - p_date_time->hours = p_encoded_data[pos++]; - p_date_time->minutes = p_encoded_data[pos++]; - p_date_time->seconds = p_encoded_data[pos++]; - - return pos; -} - - -#ifdef __cplusplus -} -#endif - -#endif // APP_UTIL_BDS_H__ - -/** @} */ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/util/app_util_platform.c b/bsp/boards/nrf52840/sdk/components/libraries/util/app_util_platform.c deleted file mode 100644 index 963991759b..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/util/app_util_platform.c +++ /dev/null @@ -1,127 +0,0 @@ -/** - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include "app_util_platform.h" - -#ifdef SOFTDEVICE_PRESENT -/* Global nvic state instance, required by nrf_nvic.h */ -nrf_nvic_state_t nrf_nvic_state; -#endif - -static uint32_t m_in_critical_region = 0; - -void app_util_disable_irq(void) -{ - __disable_irq(); - m_in_critical_region++; -} - -void app_util_enable_irq(void) -{ - m_in_critical_region--; - if (m_in_critical_region == 0) - { - __enable_irq(); - } -} - -void app_util_critical_region_enter(uint8_t *p_nested) -{ -#if __CORTEX_M == (0x04U) - ASSERT(APP_LEVEL_PRIVILEGED == privilege_level_get()) -#endif - -#if defined(SOFTDEVICE_PRESENT) - /* return value can be safely ignored */ - (void) sd_nvic_critical_region_enter(p_nested); -#else - app_util_disable_irq(); -#endif -} - -void app_util_critical_region_exit(uint8_t nested) -{ -#if __CORTEX_M == (0x04U) - ASSERT(APP_LEVEL_PRIVILEGED == privilege_level_get()) -#endif - -#if defined(SOFTDEVICE_PRESENT) - /* return value can be safely ignored */ - (void) sd_nvic_critical_region_exit(nested); -#else - app_util_enable_irq(); -#endif -} - - -uint8_t privilege_level_get(void) -{ -#if __CORTEX_M == (0x00U) || defined(_WIN32) || defined(__unix) || defined(__APPLE__) - /* the Cortex-M0 has no concept of privilege */ - return APP_LEVEL_PRIVILEGED; -#elif __CORTEX_M == (0x04U) - uint32_t isr_vector_num = __get_IPSR() & IPSR_ISR_Msk ; - if (0 == isr_vector_num) - { - /* Thread Mode, check nPRIV */ - int32_t control = __get_CONTROL(); - return control & CONTROL_nPRIV_Msk ? APP_LEVEL_UNPRIVILEGED : APP_LEVEL_PRIVILEGED; - } - else - { - /* Handler Mode, always privileged */ - return APP_LEVEL_PRIVILEGED; - } -#endif -} - - -uint8_t current_int_priority_get(void) -{ - uint32_t isr_vector_num = __get_IPSR() & IPSR_ISR_Msk ; - if (isr_vector_num > 0) - { - int32_t irq_type = ((int32_t)isr_vector_num - EXTERNAL_INT_VECTOR_OFFSET); - return (NVIC_GetPriority((IRQn_Type)irq_type) & 0xFF); - } - else - { - return APP_IRQ_PRIORITY_THREAD; - } -} diff --git a/bsp/boards/nrf52840/sdk/components/libraries/util/app_util_platform.h b/bsp/boards/nrf52840/sdk/components/libraries/util/app_util_platform.h deleted file mode 100644 index 63ef368963..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/util/app_util_platform.h +++ /dev/null @@ -1,279 +0,0 @@ -/** - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -/**@file - * - * @defgroup app_util_platform Utility Functions and Definitions (Platform) - * @{ - * @ingroup app_common - * - * @brief Various types and definitions available to all applications when using SoftDevice. - */ - -#ifndef APP_UTIL_PLATFORM_H__ -#define APP_UTIL_PLATFORM_H__ - -#include -#include "compiler_abstraction.h" -#include "nrf.h" -#ifdef SOFTDEVICE_PRESENT -#include "nrf_soc.h" -#include "nrf_nvic.h" -#endif -#include "nrf_assert.h" -#include "app_error.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if __CORTEX_M == (0x00U) -#define _PRIO_SD_HIGH 0 -#define _PRIO_APP_HIGH 1 -#define _PRIO_APP_MID 1 -#define _PRIO_SD_LOW 2 -#define _PRIO_APP_LOW 3 -#define _PRIO_APP_LOWEST 3 -#define _PRIO_THREAD 4 -#elif __CORTEX_M == (0x04U) -#define _PRIO_SD_HIGH 0 -#define _PRIO_SD_MID 1 -#define _PRIO_APP_HIGH 2 -#define _PRIO_APP_MID 3 -#define _PRIO_SD_LOW 4 -#define _PRIO_SD_LOWEST 5 -#define _PRIO_APP_LOW 6 -#define _PRIO_APP_LOWEST 7 -#define _PRIO_THREAD 15 -#else - #error "No platform defined" -#endif - - -//lint -save -e113 -e452 -/**@brief The interrupt priorities available to the application while the SoftDevice is active. */ -typedef enum -{ -#ifndef SOFTDEVICE_PRESENT - APP_IRQ_PRIORITY_HIGHEST = _PRIO_SD_HIGH, -#else - APP_IRQ_PRIORITY_HIGHEST = _PRIO_APP_HIGH, -#endif - APP_IRQ_PRIORITY_HIGH = _PRIO_APP_HIGH, -#ifndef SOFTDEVICE_PRESENT - APP_IRQ_PRIORITY_MID = _PRIO_SD_LOW, -#else - APP_IRQ_PRIORITY_MID = _PRIO_APP_MID, -#endif - APP_IRQ_PRIORITY_LOW = _PRIO_APP_LOW, - APP_IRQ_PRIORITY_LOWEST = _PRIO_APP_LOWEST, - APP_IRQ_PRIORITY_THREAD = _PRIO_THREAD /**< "Interrupt level" when running in Thread Mode. */ -} app_irq_priority_t; -//lint -restore - - -/*@brief The privilege levels available to applications in Thread Mode */ -typedef enum -{ - APP_LEVEL_UNPRIVILEGED, - APP_LEVEL_PRIVILEGED -} app_level_t; - -/**@cond NO_DOXYGEN */ -#define EXTERNAL_INT_VECTOR_OFFSET 16 -/**@endcond */ - -/**@brief Macro for setting a breakpoint. - */ -#if defined(__GNUC__) -#define NRF_BREAKPOINT __asm__("BKPT 0"); -#else -#define NRF_BREAKPOINT __BKPT(0) -#endif - -/** @brief Macro for setting a breakpoint. - * - * If it is possible to detect debugger presence then it is set only in that case. - * - */ -#if __CORTEX_M == 0x04 -#define NRF_BREAKPOINT_COND do { \ - /* C_DEBUGEN == 1 -> Debugger Connected */ \ - if (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) \ - { \ - /* Generate breakpoint if debugger is connected */ \ - NRF_BREAKPOINT; \ - } \ - }while (0) -#else -#define NRF_BREAKPOINT_COND NRF_BREAKPOINT -#endif // __CORTEX_M == 0x04 - -#if defined ( __CC_ARM ) -#define PACKED(TYPE) __packed TYPE -#define PACKED_STRUCT PACKED(struct) -#elif defined ( __GNUC__ ) -#define PACKED __attribute__((packed)) -#define PACKED_STRUCT struct PACKED -#elif defined (__ICCARM__) -#define PACKED_STRUCT __packed struct -#endif - -#if defined ( __CC_ARM ) -#define PRAGMA_OPTIMIZATION_FORCE_START _Pragma ("push") \ - _Pragma ("O3") -#define PRAGMA_OPTIMIZATION_FORCE_END _Pragma ("pop") -#elif defined ( __GNUC__ ) -#define PRAGMA_OPTIMIZATION_FORCE_START _Pragma("GCC push_options") \ - _Pragma ("GCC optimize (\"Os\")") -#define PRAGMA_OPTIMIZATION_FORCE_END _Pragma ("GCC pop_options") -#elif defined (__ICCARM__) -#define PRAGMA_OPTIMIZATION_FORCE_START _Pragma ("optimize=high z") -#define PRAGMA_OPTIMIZATION_FORCE_END -#endif - - -void app_util_critical_region_enter (uint8_t *p_nested); -void app_util_critical_region_exit (uint8_t nested); - -/**@brief Macro for entering a critical region. - * - * @note Due to implementation details, there must exist one and only one call to - * CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located - * in the same scope. - */ -#ifdef SOFTDEVICE_PRESENT -#define CRITICAL_REGION_ENTER() \ - { \ - uint8_t __CR_NESTED = 0; \ - app_util_critical_region_enter(&__CR_NESTED); -#else -#define CRITICAL_REGION_ENTER() app_util_critical_region_enter(NULL) -#endif - -/**@brief Macro for leaving a critical region. - * - * @note Due to implementation details, there must exist one and only one call to - * CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located - * in the same scope. - */ -#ifdef SOFTDEVICE_PRESENT -#define CRITICAL_REGION_EXIT() \ - app_util_critical_region_exit(__CR_NESTED); \ - } -#else -#define CRITICAL_REGION_EXIT() app_util_critical_region_exit(0) -#endif - -/* Workaround for Keil 4 */ -#ifndef IPSR_ISR_Msk -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ -#endif - - - -/**@brief Macro to enable anonymous unions from a certain point in the code. - */ -#if defined(__CC_ARM) - #define ANON_UNIONS_ENABLE _Pragma("push") \ - _Pragma("anon_unions") \ - struct semicolon_swallower -#elif defined(__ICCARM__) - #define ANON_UNIONS_ENABLE _Pragma("language=extended") \ - struct semicolon_swallower -#else - #define ANON_UNIONS_ENABLE struct semicolon_swallower - // No action will be taken. - // For GCC anonymous unions are enabled by default. -#endif - -/**@brief Macro to disable anonymous unions from a certain point in the code. - * @note Call only after first calling @ref ANON_UNIONS_ENABLE. - */ -#if defined(__CC_ARM) - #define ANON_UNIONS_DISABLE _Pragma("pop") \ - struct semicolon_swallower -#elif defined(__ICCARM__) - #define ANON_UNIONS_DISABLE struct semicolon_swallower - // for IAR leave anonymous unions enabled -#else - #define ANON_UNIONS_DISABLE struct semicolon_swallower - // No action will be taken. - // For GCC anonymous unions are enabled by default. -#endif - -/**@brief Macro for adding pragma directive only for GCC. - */ -#ifdef __GNUC__ -#define GCC_PRAGMA(v) _Pragma(v) -#else -#define GCC_PRAGMA(v) -#endif - -/* Workaround for Keil 4 */ -#ifndef CONTROL_nPRIV_Msk -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ -#endif - -/**@brief Function for finding the current interrupt level. - * - * @return Current interrupt level. - * @retval APP_IRQ_PRIORITY_HIGH We are running in Application High interrupt level. - * @retval APP_IRQ_PRIORITY_LOW We are running in Application Low interrupt level. - * @retval APP_IRQ_PRIORITY_THREAD We are running in Thread Mode. - */ -uint8_t current_int_priority_get(void); - - -/**@brief Function for finding out the current privilege level. - * - * @return Current privilege level. - * @retval APP_LEVEL_UNPRIVILEGED We are running in unprivileged level. - * @retval APP_LEVEL_PRIVILEGED We are running in privileged level. - */ -uint8_t privilege_level_get(void); - - -#ifdef __cplusplus -} -#endif - -#endif // APP_UTIL_PLATFORM_H__ - -/** @} */ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/util/nordic_common.h b/bsp/boards/nrf52840/sdk/components/libraries/util/nordic_common.h deleted file mode 100644 index 80b81752ae..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/util/nordic_common.h +++ /dev/null @@ -1,215 +0,0 @@ -/** - * Copyright (c) 2008 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -/** @file - * @brief Common defines and macros for firmware developed by Nordic Semiconductor. - */ - -#ifndef NORDIC_COMMON_H__ -#define NORDIC_COMMON_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Check if selected module is enabled - * - * This is save function for driver enable checking. - * Correct from Lint point of view (not using default of undefined value). - * - * Usage: - * @code - #if NRF_MODULE_ENABLED(UART) - ... - #endif - * @endcode - * - * @param module The module name. - * - * @retval 1 The macro _ENABLE is defined and is non-zero. - * @retval 0 The macro _ENABLE is not defined or it equals zero. - * - * @note - * This macro intentionally does not implement second expansion level. - * The name of the module to be checked has to be given directly as a parameter. - * And given parameter would be connected with @c _ENABLED postfix directly - * without evaluating its value. - */ -//lint -emacro(491,NRF_MODULE_ENABLED) // Suppers warning 491 "non-standard use of 'defined' preprocessor operator" -#ifdef NRF_MODULE_ENABLE_ALL -#warning "Do not use NRF_MODULE_ENABLE_ALL for real builds." -#define NRF_MODULE_ENABLED(module) 1 -#else -#define NRF_MODULE_ENABLED(module) \ - ((defined(module ## _ENABLED) && (module ## _ENABLED)) ? 1 : 0) -#endif -/** The upper 8 bits of a 32 bit value */ -//lint -emacro(572,MSB_32) // Suppress warning 572 "Excessive shift value" -#define MSB_32(a) (((a) & 0xFF000000) >> 24) -/** The lower 8 bits (of a 32 bit value) */ -#define LSB_32(a) ((a) & 0x000000FF) - -/** The upper 8 bits of a 16 bit value */ -//lint -emacro(572,MSB_16) // Suppress warning 572 "Excessive shift value" -#define MSB_16(a) (((a) & 0xFF00) >> 8) -/** The lower 8 bits (of a 16 bit value) */ -#define LSB_16(a) ((a) & 0x00FF) - -/** Leaves the minimum of the two 32-bit arguments */ -/*lint -emacro(506, MIN) */ /* Suppress "Constant value Boolean */ -#define MIN(a, b) ((a) < (b) ? (a) : (b)) -/** Leaves the maximum of the two 32-bit arguments */ -/*lint -emacro(506, MAX) */ /* Suppress "Constant value Boolean */ -#define MAX(a, b) ((a) < (b) ? (b) : (a)) - -/**@brief Concatenates two parameters. - * - * It realizes two level expansion to make it sure that all the parameters - * are actually expanded before gluing them together. - * - * @param p1 First parameter to concatenating - * @param p2 Second parameter to concatenating - * - * @return Two parameters glued together. - * They have to create correct C mnemonic in other case - * preprocessor error would be generated. - * - * @sa CONCAT_3 - */ -#define CONCAT_2(p1, p2) CONCAT_2_(p1, p2) -/** Auxiliary macro used by @ref CONCAT_2 */ -#define CONCAT_2_(p1, p2) p1##p2 - -/**@brief Concatenates three parameters. - * - * It realizes two level expansion to make it sure that all the parameters - * are actually expanded before gluing them together. - * - * @param p1 First parameter to concatenating - * @param p2 Second parameter to concatenating - * @param p3 Third parameter to concatenating - * - * @return Three parameters glued together. - * They have to create correct C mnemonic in other case - * preprocessor error would be generated. - * - * @sa CONCAT_2 - */ -#define CONCAT_3(p1, p2, p3) CONCAT_3_(p1, p2, p3) -/** Auxiliary macro used by @ref CONCAT_3 */ -#define CONCAT_3_(p1, p2, p3) p1##p2##p3 - -#define STRINGIFY_(val) #val -/** Converts a macro argument into a character constant. - */ -#define STRINGIFY(val) STRINGIFY_(val) - -/** Counts number of elements inside the array - */ -#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) - -/**@brief Set a bit in the uint32 word. - * - * @param[in] W Word whose bit is being set. - * @param[in] B Bit number in the word to be set. - */ -#define SET_BIT(W, B) ((W) |= (uint32_t)(1U << (B))) - - -/**@brief Clears a bit in the uint32 word. - * - * @param[in] W Word whose bit is to be cleared. - * @param[in] B Bit number in the word to be cleared. - */ -#define CLR_BIT(W, B) ((W) &= (~(uint32_t)(1U << (B)))) - - -/**@brief Checks if a bit is set. - * - * @param[in] W Word whose bit is to be checked. - * @param[in] B Bit number in the word to be checked. - * - * @retval 1 if bit is set. - * @retval 0 if bit is not set. - */ -#define IS_SET(W, B) (((W) >> (B)) & 1) - -#define BIT_0 0x01 /**< The value of bit 0 */ -#define BIT_1 0x02 /**< The value of bit 1 */ -#define BIT_2 0x04 /**< The value of bit 2 */ -#define BIT_3 0x08 /**< The value of bit 3 */ -#define BIT_4 0x10 /**< The value of bit 4 */ -#define BIT_5 0x20 /**< The value of bit 5 */ -#define BIT_6 0x40 /**< The value of bit 6 */ -#define BIT_7 0x80 /**< The value of bit 7 */ -#define BIT_8 0x0100 /**< The value of bit 8 */ -#define BIT_9 0x0200 /**< The value of bit 9 */ -#define BIT_10 0x0400 /**< The value of bit 10 */ -#define BIT_11 0x0800 /**< The value of bit 11 */ -#define BIT_12 0x1000 /**< The value of bit 12 */ -#define BIT_13 0x2000 /**< The value of bit 13 */ -#define BIT_14 0x4000 /**< The value of bit 14 */ -#define BIT_15 0x8000 /**< The value of bit 15 */ -#define BIT_16 0x00010000 /**< The value of bit 16 */ -#define BIT_17 0x00020000 /**< The value of bit 17 */ -#define BIT_18 0x00040000 /**< The value of bit 18 */ -#define BIT_19 0x00080000 /**< The value of bit 19 */ -#define BIT_20 0x00100000 /**< The value of bit 20 */ -#define BIT_21 0x00200000 /**< The value of bit 21 */ -#define BIT_22 0x00400000 /**< The value of bit 22 */ -#define BIT_23 0x00800000 /**< The value of bit 23 */ -#define BIT_24 0x01000000 /**< The value of bit 24 */ -#define BIT_25 0x02000000 /**< The value of bit 25 */ -#define BIT_26 0x04000000 /**< The value of bit 26 */ -#define BIT_27 0x08000000 /**< The value of bit 27 */ -#define BIT_28 0x10000000 /**< The value of bit 28 */ -#define BIT_29 0x20000000 /**< The value of bit 29 */ -#define BIT_30 0x40000000 /**< The value of bit 30 */ -#define BIT_31 0x80000000 /**< The value of bit 31 */ - -#define UNUSED_VARIABLE(X) ((void)(X)) -#define UNUSED_PARAMETER(X) UNUSED_VARIABLE(X) -#define UNUSED_RETURN_VALUE(X) UNUSED_VARIABLE(X) - -#ifdef __cplusplus -} -#endif - -#endif // NORDIC_COMMON_H__ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/util/nrf_assert.c b/bsp/boards/nrf52840/sdk/components/libraries/util/nrf_assert.c deleted file mode 100644 index 99498b33aa..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/util/nrf_assert.c +++ /dev/null @@ -1,54 +0,0 @@ -/** - * Copyright (c) 2006 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include "nrf_assert.h" -#include "app_error.h" -#include "nordic_common.h" - -__WEAK void assert_nrf_callback(uint16_t line_num, const uint8_t * file_name) -{ - assert_info_t assert_info = - { - .line_num = line_num, - .p_file_name = file_name, - }; - app_error_fault_handler(NRF_FAULT_ID_SDK_ASSERT, 0, (uint32_t)(&assert_info)); - - UNUSED_VARIABLE(assert_info); -} diff --git a/bsp/boards/nrf52840/sdk/components/libraries/util/nrf_assert.h b/bsp/boards/nrf52840/sdk/components/libraries/util/nrf_assert.h deleted file mode 100644 index 538387c7ce..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/util/nrf_assert.h +++ /dev/null @@ -1,122 +0,0 @@ -/** - * Copyright (c) 2006 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -/** @file - * @brief Utilities for verifying program logic - */ - -#ifndef NRF_ASSERT_H_ -#define NRF_ASSERT_H_ - -#include -#include "nrf.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @brief Function for handling assertions. - * - * - * @note - * This function is called when an assertion has triggered. - * - * @note - * This function is deprecated and will be removed in future releases. - * Use app_error_fault_handler instead. - * - * - * @post - * All hardware is put into an idle non-emitting state (in particular the radio is highly - * important to switch off since the radio might be in a state that makes it send - * packets continiously while a typical final infinit ASSERT loop is executing). - * - * - * @param line_num The line number where the assertion is called - * @param file_name Pointer to the file name - */ -//lint -save -esym(14, assert_nrf_callback) -void assert_nrf_callback(uint16_t line_num, const uint8_t *file_name); -//lint -restore - -#if (defined(DEBUG_NRF) || defined(DEBUG_NRF_USER)) -#define NRF_ASSERT_PRESENT 1 -#else -#define NRF_ASSERT_PRESENT 0 -#endif - -//#if defined(DEBUG_NRF) || defined(DEBUG_NRF_USER) - -/*lint -emacro(506, ASSERT) */ /* Suppress "Constant value Boolean */ -/*lint -emacro(774, ASSERT) */ /* Suppress "Boolean within 'if' always evaluates to True" */ \ - -/** @brief Function for checking intended for production code. - * - * Check passes if "expr" evaluates to true. */ - -#ifdef _lint -#define ASSERT(expr) \ -if (expr) \ -{ \ -} \ -else \ -{ \ - while (1); \ -} -#else //_lint -#define ASSERT(expr) \ -if (NRF_ASSERT_PRESENT) \ -{ \ - if (expr) \ - { \ - } \ - else \ - { \ - assert_nrf_callback((uint16_t)__LINE__, (uint8_t *)__FILE__); \ - } \ -} - -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* NRF_ASSERT_H_ */ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/util/nrf_bitmask.h b/bsp/boards/nrf52840/sdk/components/libraries/util/nrf_bitmask.h deleted file mode 100644 index 63dae2e667..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/util/nrf_bitmask.h +++ /dev/null @@ -1,147 +0,0 @@ -/** - * Copyright (c) 2006 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef NRF_BITMASK_H -#define NRF_BITMASK_H - -#include "compiler_abstraction.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#define BITMASK_BYTE_GET(abs_bit) ((abs_bit)/8) -#define BITMASK_RELBIT_GET(abs_bit) ((abs_bit) & 0x00000007) - -/** - * Function for checking if bit in the multi-byte bit mask is set. - * - * @param bit Bit index. - * @param p_mask A pointer to mask with bit fields. - * - * @return 0 if bit is not set, positive value otherwise. - */ -__STATIC_INLINE uint32_t nrf_bitmask_bit_is_set(uint32_t bit, void const * p_mask) -{ - uint8_t const * p_mask8 = (uint8_t const *)p_mask; - uint32_t byte_idx = BITMASK_BYTE_GET(bit); - bit = BITMASK_RELBIT_GET(bit); - return (1 << bit) & p_mask8[byte_idx]; -} - -/** - * Function for setting a bit in the multi-byte bit mask. - * - * @param bit Bit index. - * @param p_mask A pointer to mask with bit fields. - */ -__STATIC_INLINE void nrf_bitmask_bit_set(uint32_t bit, void * p_mask) -{ - uint8_t * p_mask8 = (uint8_t *)p_mask; - uint32_t byte_idx = BITMASK_BYTE_GET(bit); - bit = BITMASK_RELBIT_GET(bit); - p_mask8[byte_idx] |= (1 << bit); -} - -/** - * Function for clearing a bit in the multi-byte bit mask. - * - * @param bit Bit index. - * @param p_mask A pointer to mask with bit fields. - */ -__STATIC_INLINE void nrf_bitmask_bit_clear(uint32_t bit, void * p_mask) -{ - uint8_t * p_mask8 = (uint8_t *)p_mask; - uint32_t byte_idx = BITMASK_BYTE_GET(bit); - bit = BITMASK_RELBIT_GET(bit); - p_mask8[byte_idx] &= ~(1 << bit); -} - -/** - * Function for performing bitwise OR operation on two multi-byte bit masks. - * - * @param p_mask1 A pointer to the first bit mask. - * @param p_mask2 A pointer to the second bit mask. - * @param p_mask_out A pointer to the output bit mask. - * @param length Length of output mask in bytes. - */ -__STATIC_INLINE void nrf_bitmask_masks_or(void const * p_mask1, - void const * p_mask2, - void * p_out_mask, - uint32_t length) -{ - uint8_t const * p_mask8_1 = (uint8_t const *)p_mask1; - uint8_t const * p_mask8_2 = (uint8_t const *)p_mask2; - uint8_t * p_mask8_out = (uint8_t *)p_out_mask; - uint32_t i; - for (i = 0; i < length; i++) - { - p_mask8_out[i] = p_mask8_1[i] | p_mask8_2[i]; - } -} - -/** - * Function for performing bitwise AND operation on two multi-byte bit masks. - * - * @param p_mask1 A pointer to the first bit mask. - * @param p_mask2 A pointer to the second bit mask. - * @param p_mask_out A pointer to the output bit mask. - * @param length Length of output mask in bytes. - */ -__STATIC_INLINE void nrf_bitmask_masks_and(void const * p_mask1, - void const * p_mask2, - void * p_out_mask, - uint32_t length) -{ - uint8_t const * p_mask8_1 = (uint8_t const *)p_mask1; - uint8_t const * p_mask8_2 = (uint8_t const *)p_mask2; - uint8_t * p_mask8_out = (uint8_t *)p_out_mask; - uint32_t i; - for (i = 0; i < length; i++) - { - p_mask8_out[i] = p_mask8_1[i] & p_mask8_2[i]; - } -} - -#ifdef __cplusplus -} -#endif - -#endif //NRF_BITMASK_H diff --git a/bsp/boards/nrf52840/sdk/components/libraries/util/sdk_alloca.h b/bsp/boards/nrf52840/sdk/components/libraries/util/sdk_alloca.h deleted file mode 100644 index b00809708a..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/util/sdk_alloca.h +++ /dev/null @@ -1,85 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -/** @file sdk_alloca.h - * - * @brief Defines alloca() function. - * - * @details This file defines alloca() function. This can be done directly or by including system - * header files. Not all platforms support alloca(). In this case no error will be shown, but - * SDK_ALLOCA_DEFINED will be set to 0. - */ - -#ifndef SDK_ALLOCA_H__ -#define SDK_ALLOCA_H__ - - -#if defined(__SDK_DOXYGEN__) - /** @brief Set to one it alloca() function is available on this platform and it is correctly defined - * by this header file. - */ - #define SDK_ALLOCA_DEFINED 1 -#elif defined(__GNUC__) - #if defined(__SES_ARM) - // SES does not have definition of alloca(), but it have working GCC's __builtin_alloca(). - #if !defined(alloca) - #define alloca(size) __builtin_alloca((size)) - #endif - #else - // alloca() can be defined in on some platforms, but if not then try standard header file. - #include - #if !defined(alloca) - #include - #endif - #endif - #define SDK_ALLOCA_DEFINED 1 -#elif defined(__IAR_SYSTEMS_ICC__) - // IAR does not support alloca() function. - #define SDK_ALLOCA_DEFINED 0 -#else - // All other supported compilers have alloca() definition in header file. - #include - #define SDK_ALLOCA_DEFINED 1 -#endif - - -/*lint -"d__builtin_alloca=(void*)" */ - - -#endif // NRF_ALLOCA_H__ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/util/sdk_common.h b/bsp/boards/nrf52840/sdk/components/libraries/util/sdk_common.h deleted file mode 100644 index e4df925793..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/util/sdk_common.h +++ /dev/null @@ -1,77 +0,0 @@ -/** - * Copyright (c) 2013 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -/** @cond */ -/**@file - * - * @ingroup experimental_api - * @defgroup sdk_common SDK Common Header - * @brief All common headers needed for SDK examples will be included here so that application - * developer does not have to include headers on him/herself. - * @{ - */ - -#ifndef SDK_COMMON_H__ -#define SDK_COMMON_H__ - -#include -#include -#include -#include "sdk_config.h" -#include "nordic_common.h" -#include "compiler_abstraction.h" -#include "sdk_os.h" -#include "sdk_errors.h" -#include "app_util.h" -#include "sdk_macros.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -/** @} */ -/** @endcond */ - -#ifdef __cplusplus -} -#endif - -#endif // SDK_COMMON_H__ - diff --git a/bsp/boards/nrf52840/sdk/components/libraries/util/sdk_errors.h b/bsp/boards/nrf52840/sdk/components/libraries/util/sdk_errors.h deleted file mode 100644 index b6d2dd4ee2..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/util/sdk_errors.h +++ /dev/null @@ -1,167 +0,0 @@ -/** - * Copyright (c) 2013 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -/**@file - * - * @defgroup sdk_error SDK Error codes - * @{ - * @ingroup app_common - * @{ - * @details Error codes are 32-bit unsigned integers with the most significant 16-bit reserved for - * identifying the module where the error occurred while the least least significant LSB - * are used to provide the cause or nature of error. Each module is assigned a 16-bit - * unsigned integer. Which it will use to identify all errors that occurred in it. 16-bit - * LSB range is with module id as the MSB in the 32-bit error code is reserved for the - * module. As an example, if 0x8800 identifies a certain SDK module, all values from - * 0x88000000 - 0x8800FFFF are reserved for this module. - * It should be noted that common error reasons have been assigned values to make it - * possible to decode error reason easily. As an example, lets module uninitialized has - * been assigned an error code 0x000A0. Then, if application encounters an error code - * 0xZZZZ00A0, it knows that it accessing a certain module without initializing it. - * Apart from this, each module is allowed to define error codes that are not covered by - * the common ones, however, these values are defined in a range that does not conflict - * with common error values. For module, specific error however, it is possible that the - * same error value is used by two different modules to indicated errors of very different - * nature. If error is already defined by the NRF common error codes, these are reused. - * A range is reserved for application as well, it can use this range for defining - * application specific errors. - * - * @note Success code, NRF_SUCCESS, does not include any module identifier. - - */ - -#ifndef SDK_ERRORS_H__ -#define SDK_ERRORS_H__ - -#include -#include "nrf_error.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup sdk_err_base Base defined for SDK Modules - * @{ - */ -#define NRF_ERROR_SDK_ERROR_BASE (NRF_ERROR_BASE_NUM + 0x8000) /**< Base value defined for SDK module identifiers. */ -#define NRF_ERROR_SDK_COMMON_ERROR_BASE (NRF_ERROR_BASE_NUM + 0x0080) /**< Base error value to be used for SDK error values. */ -/** @} */ - -/** - * @defgroup sdk_module_codes Codes reserved as identification for module where the error occurred. - * @{ - */ -#define NRF_ERROR_MEMORY_MANAGER_ERR_BASE (0x8100) /**< Base address for Memory Manager related errors. */ -#define NRF_ERROR_PERIPH_DRIVERS_ERR_BASE (0x8200) /**< Base address for Peripheral drivers related errors. */ -#define NRF_ERROR_GAZELLE_ERR_BASE (0x8300) /**< Base address for Gazelle related errors. */ -#define NRF_ERROR_BLE_IPSP_ERR_BASE (0x8400) /**< Base address for BLE IPSP related errors. */ -#define NRF_ERROR_CRYPTO_ERR_BASE (0x8500) /**< Base address for crypto related errors. */ -/** @} */ - - -/** - * @defgroup sdk_iot_errors Codes reserved as identification for IoT errors. - * @{ - */ -#define NRF_ERROR_IOT_ERR_BASE_START (0xA000) -#define NRF_ERROR_IOT_ERR_BASE_STOP (0xAFFF) -/** @} */ - - -/** - * @defgroup sdk_common_errors Codes reserved as identification for common errors. - * @{ - */ -#define NRF_ERROR_MODULE_NOT_INITIALIZED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0000) ///< Module not initialized -#define NRF_ERROR_MUTEX_INIT_FAILED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0001) ///< Mutex initialization failed -#define NRF_ERROR_MUTEX_LOCK_FAILED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0002) ///< Mutex lock failed -#define NRF_ERROR_MUTEX_UNLOCK_FAILED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0003) ///< Mutex unlock failed -#define NRF_ERROR_MUTEX_COND_INIT_FAILED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0004) ///< Mutex conditional initialization failed -#define NRF_ERROR_MODULE_ALREADY_INITIALIZED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0005) ///< Module already initialized -#define NRF_ERROR_STORAGE_FULL (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0006) ///< Storage full -#define NRF_ERROR_API_NOT_IMPLEMENTED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0010) ///< API not implemented -#define NRF_ERROR_FEATURE_NOT_ENABLED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0011) ///< Feature not enabled -#define NRF_ERROR_IO_PENDING (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0012) ///< Input/Output pending -/** @} */ - - -/** - * @defgroup drv_specific_errors Error / status codes specific to drivers. - * @{ - */ -#define NRF_ERROR_DRV_TWI_ERR_OVERRUN (NRF_ERROR_PERIPH_DRIVERS_ERR_BASE + 0x0000) -#define NRF_ERROR_DRV_TWI_ERR_ANACK (NRF_ERROR_PERIPH_DRIVERS_ERR_BASE + 0x0001) -#define NRF_ERROR_DRV_TWI_ERR_DNACK (NRF_ERROR_PERIPH_DRIVERS_ERR_BASE + 0x0002) -/** @} */ - - -/** - * @defgroup ble_ipsp_errors IPSP codes - * @brief Error and status codes specific to IPSP. - * @{ - */ -#define NRF_ERROR_BLE_IPSP_RX_PKT_TRUNCATED (NRF_ERROR_BLE_IPSP_ERR_BASE + 0x0000) -#define NRF_ERROR_BLE_IPSP_CHANNEL_ALREADY_EXISTS (NRF_ERROR_BLE_IPSP_ERR_BASE + 0x0001) -#define NRF_ERROR_BLE_IPSP_LINK_DISCONNECTED (NRF_ERROR_BLE_IPSP_ERR_BASE + 0x0002) -#define NRF_ERROR_BLE_IPSP_PEER_REJECTED (NRF_ERROR_BLE_IPSP_ERR_BASE + 0x0003) -/* @} */ - - -/** - * @brief API Result. - * - * @details Indicates success or failure of an API procedure. In case of failure, a comprehensive - * error code indicating cause or reason for failure is provided. - * - * Though called an API result, it could used in Asynchronous notifications callback along - * with asynchronous callback as event result. This mechanism is employed when an event - * marks the end of procedure initiated using API. API result, in this case, will only be - * an indicative of whether the procedure has been requested successfully. - */ -typedef uint32_t ret_code_t; - -/** @} */ -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // SDK_ERRORS_H__ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/util/sdk_macros.h b/bsp/boards/nrf52840/sdk/components/libraries/util/sdk_macros.h deleted file mode 100644 index 4f02da62dd..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/util/sdk_macros.h +++ /dev/null @@ -1,215 +0,0 @@ -/** - * Copyright (c) 2013 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -/**@file - * - - * @defgroup sdk_common_macros SDK Common Header - * @ingroup app_common - * @brief Macros for parameter checking and similar tasks - * @{ - */ - -#ifndef SDK_MACROS_H__ -#define SDK_MACROS_H__ - -#include "nrf_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -/**@brief Macro for parameter checking. - * - * If @p _cond evaluates to true, does nothing. Otherwise, - * if @p _module ## _PARAM_CHECK_DISABLED is @e not set (default), prints an error message - * if @p _printfn is provided, and returns from the calling function context with code @p _err. - * If @p _module ## _PARAM_CHECK_DISABLED is set, behaves like the ASSERT macro. - * - * Parameter checking implemented using this macro can be optionally turned off for release code. - * Only disable runtime parameter checks if size if a major concern. - * - * @param _module The module name. - * @param _cond The condition to be evaluated. - * @param _err The error to be returned. - * @param _printfn A printf-compatible function used to log the error. - * Leave empty if no logging is needed. - * - * @hideinitializer - */ -/*lint -esym(666, NRF_PARAM_CHECK*) : Expression with side effects passed to macro */ -#define NRF_PARAM_CHECK(_module, _cond, _err, _printfn) \ - do \ - { \ - if ((_cond)) \ - { \ - /* Do nothing. */ \ - } \ - else if (!(_module ## _PARAM_CHECK_DISABLED)) \ - { \ - _printfn("%s check failed in %s() with value 0x%x.", #_cond, __func__, _err); \ - return (_err); \ - } \ - else \ - { \ - ASSERT((_cond)); \ - } \ - } while (0); - - -/**@brief Macro for verifying statement to be true. It will cause the exterior function to return - * err_code if the statement is not true. - * - * @param[in] statement Statement to test. - * @param[in] err_code Error value to return if test was invalid. - * - * @retval nothing, but will cause the exterior function to return @p err_code if @p statement - * is false. - */ -#define VERIFY_TRUE(statement, err_code) \ -do \ -{ \ - if (!(statement)) \ - { \ - return err_code; \ - } \ -} while (0) - - -/**@brief Macro for verifying statement to be true. It will cause the exterior function to return - * if the statement is not true. - * - * @param[in] statement Statement to test. - */ -#define VERIFY_TRUE_VOID(statement) VERIFY_TRUE((statement), ) - - -/**@brief Macro for verifying statement to be false. It will cause the exterior function to return - * err_code if the statement is not false. - * - * @param[in] statement Statement to test. - * @param[in] err_code Error value to return if test was invalid. - * - * @retval nothing, but will cause the exterior function to return @p err_code if @p statement - * is true. - */ -#define VERIFY_FALSE(statement, err_code) \ -do \ -{ \ - if ((statement)) \ - { \ - return err_code; \ - } \ -} while (0) - - -/**@brief Macro for verifying statement to be false. It will cause the exterior function to return - * if the statement is not false. - * - * @param[in] statement Statement to test. - */ -#define VERIFY_FALSE_VOID(statement) VERIFY_FALSE((statement), ) - - -/**@brief Macro for verifying that a function returned NRF_SUCCESS. It will cause the exterior - * function to return error code of statement if it is not @ref NRF_SUCCESS. - * - * @param[in] statement Statement to check against NRF_SUCCESS. - */ -#define VERIFY_SUCCESS(statement) \ -do \ -{ \ - uint32_t _err_code = (uint32_t) (statement); \ - if (_err_code != NRF_SUCCESS) \ - { \ - return _err_code; \ - } \ -} while(0) - - -/**@brief Macro for verifying that a function returned NRF_SUCCESS. It will cause the exterior - * function to return if the err_code is not @ref NRF_SUCCESS. - * - * @param[in] err_code The error code to check. - */ -#define VERIFY_SUCCESS_VOID(err_code) VERIFY_TRUE_VOID((err_code) == NRF_SUCCESS) - - -/**@brief Macro for verifying that the module is initialized. It will cause the exterior function to - * return @ref NRF_ERROR_INVALID_STATE if not. - * - * @note MODULE_INITIALIZED must be defined in each module using this macro. MODULE_INITIALIZED - * should be true if the module is initialized, false if not. - */ -#define VERIFY_MODULE_INITIALIZED() VERIFY_TRUE((MODULE_INITIALIZED), NRF_ERROR_INVALID_STATE) - - -/**@brief Macro for verifying that the module is initialized. It will cause the exterior function to - * return if not. - * - * @note MODULE_INITIALIZED must be defined in each module using this macro. MODULE_INITIALIZED - * should be true if the module is initialized, false if not. - */ -#define VERIFY_MODULE_INITIALIZED_VOID() VERIFY_TRUE_VOID((MODULE_INITIALIZED)) - - -/**@brief Macro for verifying that the module is initialized. It will cause the exterior function to - * return if not. - * - * @param[in] param The variable to check if is NULL. - */ -#define VERIFY_PARAM_NOT_NULL(param) VERIFY_FALSE(((param) == NULL), NRF_ERROR_NULL) - - -/**@brief Macro for verifying that the module is initialized. It will cause the exterior function to - * return if not. - * - * @param[in] param The variable to check if is NULL. - */ -#define VERIFY_PARAM_NOT_NULL_VOID(param) VERIFY_FALSE_VOID(((param) == NULL)) - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // SDK_MACROS_H__ - diff --git a/bsp/boards/nrf52840/sdk/components/libraries/util/sdk_mapped_flags.c b/bsp/boards/nrf52840/sdk/components/libraries/util/sdk_mapped_flags.c deleted file mode 100644 index 7bbc4fa8e6..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/util/sdk_mapped_flags.c +++ /dev/null @@ -1,220 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include "sdk_mapped_flags.h" -#include -#include -#include -#include "compiler_abstraction.h" - - -// Test whether the flag collection type is large enough to hold all the flags. If this fails, -// reduce SDK_MAPPED_FLAGS_N_KEYS or increase the size of sdk_mapped_flags_t. -STATIC_ASSERT((sizeof(sdk_mapped_flags_t) * SDK_MAPPED_FLAGS_N_KEYS_PER_BYTE) >= SDK_MAPPED_FLAGS_N_KEYS); - - -/**@brief Function for setting the state of a flag to true. - * - * @note This function does not check whether the index is valid. - * - * @param[in] p_flags The collection of flags to modify. - * @param[in] index The index of the flag to modify. - */ -static __INLINE void sdk_mapped_flags_set_by_index(sdk_mapped_flags_t * p_flags, uint16_t index) -{ - *p_flags |= (1U << index); -} - - -/**@brief Function for setting the state of a flag to false. - * - * @note This function does not check whether the index is valid. - * - * @param[in] p_flags The collection of flags to modify. - * @param[in] index The index of the flag to modify. - */ -static __INLINE void sdk_mapped_flags_clear_by_index(sdk_mapped_flags_t * p_flags, uint16_t index) -{ - *p_flags &= ~(1U << index); -} - - -/**@brief Function for getting the state of a flag. - * - * @note This function does not check whether the index is valid. - * - * @param[in] p_flags The collection of flags to read. - * @param[in] index The index of the flag to get. - */ -static __INLINE bool sdk_mapped_flags_get_by_index(sdk_mapped_flags_t flags, uint16_t index) -{ - return ((flags & (1 << index)) != 0); -} - - - -uint16_t sdk_mapped_flags_first_key_index_get(sdk_mapped_flags_t flags) -{ - for (uint16_t i = 0; i < SDK_MAPPED_FLAGS_N_KEYS; i++) - { - if (sdk_mapped_flags_get_by_index(flags, i)) - { - return i; - } - } - return SDK_MAPPED_FLAGS_INVALID_INDEX; -} - - -void sdk_mapped_flags_update_by_key(uint16_t * p_keys, - sdk_mapped_flags_t * p_flags, - uint16_t key, - bool value) -{ - sdk_mapped_flags_bulk_update_by_key(p_keys, p_flags, 1, key, value); -} - - -void sdk_mapped_flags_bulk_update_by_key(uint16_t * p_keys, - sdk_mapped_flags_t * p_flags, - uint32_t n_flag_collections, - uint16_t key, - bool value) -{ - if ((p_keys != NULL) && (p_flags != NULL) && (n_flag_collections > 0)) - { - for (uint32_t i = 0; i < SDK_MAPPED_FLAGS_N_KEYS; i++) - { - if (p_keys[i] == key) - { - for (uint32_t j = 0; j < n_flag_collections; j++) - { - if (value) - { - sdk_mapped_flags_set_by_index(&p_flags[j], i); - } - else - { - sdk_mapped_flags_clear_by_index(&p_flags[j], i); - } - } - return; - } - } - } -} - - -bool sdk_mapped_flags_get_by_key_w_idx(uint16_t * p_keys, - sdk_mapped_flags_t flags, - uint16_t key, - uint8_t * p_index) -{ - if (p_keys != NULL) - { - for (uint32_t i = 0; i < SDK_MAPPED_FLAGS_N_KEYS; i++) - { - if (p_keys[i] == key) - { - if (p_index != NULL) - { - *p_index = i; - } - return sdk_mapped_flags_get_by_index(flags, i); - } - } - } - if (p_index != NULL) - { - *p_index = SDK_MAPPED_FLAGS_N_KEYS; - } - return false; -} - - -bool sdk_mapped_flags_get_by_key(uint16_t * p_keys, sdk_mapped_flags_t flags, uint16_t key) -{ - if (p_keys != NULL) - { - for (uint32_t i = 0; i < SDK_MAPPED_FLAGS_N_KEYS; i++) - { - if (p_keys[i] == key) - { - return sdk_mapped_flags_get_by_index(flags, i); - } - } - } - return false; -} - - -sdk_mapped_flags_key_list_t sdk_mapped_flags_key_list_get(uint16_t * p_keys, - sdk_mapped_flags_t flags) -{ - sdk_mapped_flags_key_list_t key_list; - key_list.len = 0; - - if (p_keys != NULL) - { - for (uint32_t i = 0; i < SDK_MAPPED_FLAGS_N_KEYS; i++) - { - if (sdk_mapped_flags_get_by_index(flags, i)) - { - key_list.flag_keys[key_list.len++] = p_keys[i]; - } - } - } - - return key_list; -} - - -uint32_t sdk_mapped_flags_n_flags_set(sdk_mapped_flags_t flags) -{ - uint32_t n_flags_set = 0; - - for (uint32_t i = 0; i < SDK_MAPPED_FLAGS_N_KEYS; i++) - { - if (sdk_mapped_flags_get_by_index(flags, i)) - { - n_flags_set += 1; - } - } - return n_flags_set; -} diff --git a/bsp/boards/nrf52840/sdk/components/libraries/util/sdk_mapped_flags.h b/bsp/boards/nrf52840/sdk/components/libraries/util/sdk_mapped_flags.h deleted file mode 100644 index c0130b59ce..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/util/sdk_mapped_flags.h +++ /dev/null @@ -1,199 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef SDK_MAPPED_FLAGS_H__ -#define SDK_MAPPED_FLAGS_H__ - -#include -#include -#include "app_util.h" -#include "compiler_abstraction.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @file - * @defgroup sdk_mapped_flags Mapped flags - * @ingroup app_common - * @{ - * @brief Module for writing and reading flags that are associated - * with keys. - * - * @details The flags are represented as bits in a bitmap called a flag collection. The keys - * are uint16_t. Each flag collection contains all flags of the same type, one flag for - * each key. - * - * The mapped flags module does not keep the flag states, nor the list of keys. These are - * provided in the API calls. A key's index in the key list determines which bit in the - * flag collection is associated with it. This module does not ever edit the key list, and - * does not edit flags except in function calls that take the flag collection as a pointer. - * - */ - -#define SDK_MAPPED_FLAGS_N_KEYS 32 /**< The number of keys to keep flags for. This is also the number of flags in a flag collection. If changing this value, you might also need change the width of the sdk_mapped_flags_t type. */ -#define SDK_MAPPED_FLAGS_N_KEYS_PER_BYTE 8 /**< The number of flags that fit in one byte. */ -#define SDK_MAPPED_FLAGS_INVALID_INDEX 0xFFFF /**< A flag index guaranteed to be invalid. */ - -typedef uint32_t sdk_mapped_flags_t; /**< The bitmap to hold flags. Each flag is one bit, and each bit represents the flag state associated with one key. */ - - -/**@brief Type used to present a subset of the registered keys. - */ -typedef struct -{ - uint32_t len; /**< The length of the list. */ - uint16_t flag_keys[SDK_MAPPED_FLAGS_N_KEYS]; /**< The list of keys. */ -} sdk_mapped_flags_key_list_t; - - -/**@brief Function for getting the first index at which the flag is true in the provided - * collection. - * - * @param[in] flags The flag collection to search for a flag set to true. - * - * @return The first index that has its flag set to true. If none were found, the - * function returns @ref SDK_MAPPED_FLAGS_INVALID_INDEX. - */ -uint16_t sdk_mapped_flags_first_key_index_get(sdk_mapped_flags_t flags); - - -/**@brief Function for updating the state of a flag. - * - * @param[in] p_keys The list of associated keys (assumed to have a length of - * @ref SDK_MAPPED_FLAGS_N_KEYS). - * @param[out] p_flags The flag collection to modify. - * @param[in] key The key to modify the flag of. - * @param[in] value The state to set the flag to. - */ -void sdk_mapped_flags_update_by_key(uint16_t * p_keys, - sdk_mapped_flags_t * p_flags, - uint16_t key, - bool value); - - -/**@brief Function for updating the state of the same flag in multiple flag collections. - * - * @details The key and value are the same for all flag collections in the p_flags array. - * - * @param[in] p_keys The list of associated keys (assumed to have a length of - * @ref SDK_MAPPED_FLAGS_N_KEYS). - * @param[out] p_flags The flag collections to modify. - * @param[out] n_flag_collections The number of flag collections in p_flags. - * @param[in] key The key to modify the flag of. - * @param[in] value The state to set the flag to. - */ -void sdk_mapped_flags_bulk_update_by_key(uint16_t * p_keys, - sdk_mapped_flags_t * p_flags, - uint32_t n_flag_collections, - uint16_t key, - bool value); - - -/**@brief Function for getting the state of a specific flag. - * - * @param[in] p_keys The list of associated keys (assumed to have a length of - * @ref SDK_MAPPED_FLAGS_N_KEYS). - * @param[in] flags The flag collection to read from. - * @param[in] key The key to get the flag for. - * - * @return The state of the flag. - */ -bool sdk_mapped_flags_get_by_key(uint16_t * p_keys, sdk_mapped_flags_t flags, uint16_t key); - - -/**@brief Function for getting the state of a specific flag. - * - * @param[in] p_keys The list of associated keys (assumed to have a length of - * @ref SDK_MAPPED_FLAGS_N_KEYS). - * @param[in] flags The flag collection from which to read. - * @param[in] key The key for which to get the flag. - * @param[out] p_index If not NULL, the index of the key. - * - * @return The state of the flag. - */ -bool sdk_mapped_flags_get_by_key_w_idx(uint16_t * p_keys, - sdk_mapped_flags_t flags, - uint16_t key, - uint8_t * p_index); - - -/**@brief Function for getting a list of all keys that have a specific flag set to true. - * - * @param[in] p_keys The list of associated keys (assumed to have a length of - * @ref SDK_MAPPED_FLAGS_N_KEYS). - * @param[in] flags The flag collection to search. - * - * @return The list of keys. - */ -sdk_mapped_flags_key_list_t sdk_mapped_flags_key_list_get(uint16_t * p_keys, - sdk_mapped_flags_t flags); - - -/**@brief Function for getting the number of keys that have a specific flag set to true. - * - * @param[in] flags The flag collection to search. - * - * @return The number of keys. - */ -uint32_t sdk_mapped_flags_n_flags_set(sdk_mapped_flags_t flags); - - -/**@brief Function for querying whether any flags in the collection are set. - * - * @param[in] flags The flag collection to query. - * - * @retval true If one or more flags are set to true. - * @retval false Otherwise. - */ -static __INLINE bool sdk_mapped_flags_any_set(sdk_mapped_flags_t flags) -{ - return (flags != 0); -} - - -/** @} */ - - -#ifdef __cplusplus -} -#endif - -#endif /* SDK_MAPPED_FLAGS_H__ */ diff --git a/bsp/boards/nrf52840/sdk/components/libraries/util/sdk_os.h b/bsp/boards/nrf52840/sdk/components/libraries/util/sdk_os.h deleted file mode 100644 index 20182c9750..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/util/sdk_os.h +++ /dev/null @@ -1,76 +0,0 @@ -/** - * Copyright (c) 2013 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -/** @cond */ -/**@file - * - * @defgroup sdk_os SDK OS Abstraction - * @ingroup experimental_api - * @details In order to made SDK modules independent of use of an embedded OS, and permit - * application with varied task architecture, SDK abstracts the OS specific - * elements here in order to make all other modules agnostic to the OS or task - * architecture. - * @{ - */ - -#ifndef SDK_OS_H__ -#define SDK_OS_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#define SDK_MUTEX_DEFINE(X) -#define SDK_MUTEX_INIT(X) -#define SDK_MUTEX_LOCK(X) -#define SDK_MUTEX_UNLOCK(X) - -/** - * @defgroup os_data_type Data types. - */ - -/** @} */ -/** @endcond */ - -#ifdef __cplusplus -} -#endif - -#endif // SDK_OS_H__ - diff --git a/bsp/boards/nrf52840/sdk/components/libraries/util/sdk_resources.h b/bsp/boards/nrf52840/sdk/components/libraries/util/sdk_resources.h deleted file mode 100644 index b227ac3cb7..0000000000 --- a/bsp/boards/nrf52840/sdk/components/libraries/util/sdk_resources.h +++ /dev/null @@ -1,86 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -/** @file - * @brief Definition file for resource usage by SoftDevice, ESB and Gazell. - */ - -#ifndef SDK_RESOURCES_H__ -#define SDK_RESOURCES_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined(SOFTDEVICE_PRESENT) || defined (BLE_STACK_SUPPORT_REQD) || defined (ANT_STACK_SUPPORT_REQD) - #include "nrf_sd_def.h" -#else - #define SD_PPI_RESTRICTED 0uL /**< 1 if PPI peripheral is restricted, 0 otherwise. */ - #define SD_PPI_CHANNELS_USED 0uL /**< PPI channels utilized by SotfDevice (not available to th spplication). */ - #define SD_PPI_GROUPS_USED 0uL /**< PPI groups utilized by SotfDevice (not available to th spplication). */ - #define SD_TIMERS_USED 0uL /**< Timers used by SoftDevice. */ - #define SD_SWI_USED 0uL /**< Software interrupts used by SoftDevice. */ -#endif - -#ifdef GAZELL_PRESENT - #include "nrf_gzll_resources.h" -#else - #define GZLL_PPI_CHANNELS_USED 0uL /**< PPI channels utilized by Gazell (not available to th spplication). */ - #define GZLL_TIMERS_USED 0uL /**< Timers used by Gazell. */ - #define GZLL_SWI_USED 0uL /**< Software interrupts used by Gazell */ -#endif - -#ifdef ESB_PRESENT - #include "nrf_esb_resources.h" -#else - #define ESB_PPI_CHANNELS_USED 0uL /**< PPI channels utilized by ESB (not available to th spplication). */ - #define ESB_TIMERS_USED 0uL /**< Timers used by ESB. */ - #define ESB_SWI_USED 0uL /**< Software interrupts used by ESB */ -#endif - -#define NRF_PPI_CHANNELS_USED (SD_PPI_CHANNELS_USED | GZLL_PPI_CHANNELS_USED | ESB_PPI_CHANNELS_USED) -#define NRF_PPI_GROUPS_USED (SD_PPI_GROUPS_USED) -#define NRF_SWI_USED (SD_SWI_USED | GZLL_SWI_USED | ESB_SWI_USED) -#define NRF_TIMERS_USED (SD_TIMERS_USED | GZLL_TIMERS_USED | ESB_TIMERS_USED) - -#ifdef __cplusplus -} -#endif - -#endif // SDK_RESOURCES_H__ diff --git a/bsp/boards/nrf52840/sdk/components/sdk_validation.h b/bsp/boards/nrf52840/sdk/components/sdk_validation.h deleted file mode 100644 index 379f0afaec..0000000000 --- a/bsp/boards/nrf52840/sdk/components/sdk_validation.h +++ /dev/null @@ -1,305 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef SDK_VALIDATION_H -#define SDK_VALIDATION_H - -#include "nrf_peripherals.h" -#include "sdk_config.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// Validate peripheral availibility - -#if ((defined(SAADC_ENABLED)) && (SAADC_ENABLED > 0) && (!defined(SAADC_PRESENT))) -#error "SAADC not present in selected MCU." -#endif - -#if ((defined(ADC_ENABLED)) && (ADC_ENABLED > 0) && (!defined(ADC_PRESENT))) -#error "SAADC not present in selected MCU." -#endif - -#if ((defined(I2S_ENABLED)) && (I2S_ENABLED > 0) && (!defined(I2S_PRESENT))) -#error "I2S not present in selected MCU." -#endif - -#if ((defined(COMP_ENABLED)) && (COMP_ENABLED > 0) && (!defined(COMP_PRESENT))) -#error "COMP not present in selected MCU." -#endif - -#if ((defined(LPCOMP_ENABLED)) && (LPCOMP_ENABLED > 0) && (!defined(LPCOMP_PRESENT))) -#error "LPCOMP not present in selected MCU." -#endif - -#if ((defined(SPIS0_ENABLED)) && (SPIS0_ENABLED > 0) && (!defined(SPIS_PRESENT))) -#error "SPIS0 instance not present in selected MCU." -#endif - -#if ((defined(EGU_ENABLED)) && (EGU_ENABLED > 0) && (!defined(EGU_PRESENT))) -#error "EGU instance not present in selected MCU." -#endif - -#if ((defined(NFC_HAL_ENABLED)) && (NFC_HAL_ENABLED > 0) && (!defined(NFCT_PRESENT))) -#error "NFC TAG not present in selected MCU." -#endif - -// Validate count of instances - -#if ((defined(RTC2_ENABLED)) && (RTC2_ENABLED > 0) && (RTC_COUNT < 2)) -#error "RTC2 not present in selected MCU." -#endif - -#if ((defined(TWIS0_ENABLED) || defined(TWIS1_ENABLED)) &&\ - ((TWIS0_ENABLED + TWIS1_ENABLED) > 0) &&\ - (!defined(TWIS_PRESENT))) -#error "TWIS not present in selected MCU." -#endif - -#if ((defined(SPIS2_ENABLED)) && (SPIS2_ENABLED > 0) && (SPIS_COUNT < 2)) -#error "SPI2/SPIS2 instance not present in selected MCU." -#endif - -#if ((defined(TIMER3_ENABLED) || defined(TIMER4_ENABLED)) &&\ - ((TIMER3_ENABLED + TIMER4_ENABLED ) > 0) &&\ - (TIMER_COUNT < 5)) -#error "TIMER3 and TIMER4 not present in selected MCU." -#endif - -// Validate peripheral sharing feature -#if !NRFX_CHECK(NRFX_PRS_ENABLED) - -#if ((defined(TWIM0_ENABLED) && defined(TWIS0_ENABLED)) &&\ - ((TWIM0_ENABLED + TWIS0_ENABLED) > 1)) -#error "Peripherals overlap. TWIM0, TWIS0 - only one of these can be enabled." -#endif - -#if ((defined(TWIM0_ENABLED) && defined(SPIM0_ENABLED)) &&\ - ((TWIM0_ENABLED + SPIM0_ENABLED) > 1)) -#error "Peripherals overlap. TWIM0, SPIM0 - only one of these can be enabled." -#endif - -#if ((defined(TWIM0_ENABLED) && defined(SPIS0_ENABLED)) &&\ - ((TWIM0_ENABLED + SPIS0_ENABLED) > 1)) -#error "Peripherals overlap. TWIM0, SPIS0 - only one of these can be enabled." -#endif - -#if ((defined(TWIM0_ENABLED) && defined(SPI0_ENABLED)) &&\ - ((TWIM0_ENABLED + SPI0_ENABLED) > 1)) -#error "Peripherals overlap. TWIM0, SPI0 - only one of these can be enabled." -#endif - -#if ((defined(TWIM0_ENABLED) && defined(TWI0_ENABLED)) &&\ - ((TWIM0_ENABLED + TWI0_ENABLED) > 1)) -#error "Peripherals overlap. TWIM0, TWI0 - only one of these can be enabled." -#endif - -#if ((defined(TWIS0_ENABLED) && defined(SPIM0_ENABLED)) &&\ - ((TWIS0_ENABLED + SPIM0_ENABLED) > 1)) -#error "Peripherals overlap. TWIS0, SPIM0 - only one of these can be enabled." -#endif - -#if ((defined(TWIS0_ENABLED) && defined(SPIS0_ENABLED)) &&\ - ((TWIS0_ENABLED + SPIS0_ENABLED) > 1)) -#error "Peripherals overlap. TWIS0, SPIS0 - only one of these can be enabled." -#endif - -#if ((defined(TWIS0_ENABLED) && defined(SPI0_ENABLED)) &&\ - ((TWIS0_ENABLED + SPI0_ENABLED) > 1)) -#error "Peripherals overlap. TWIS0, SPI0 - only one of these can be enabled." -#endif - -#if ((defined(TWIS0_ENABLED) && defined(TWI0_ENABLED)) &&\ - ((TWIS0_ENABLED + TWI0_ENABLED) > 1)) -#error "Peripherals overlap. TWIS0, TWI0 - only one of these can be enabled." -#endif - -#if ((defined(SPIM0_ENABLED) && defined(SPIS0_ENABLED)) &&\ - ((SPIM0_ENABLED + SPIS0_ENABLED) > 1)) -#error "Peripherals overlap. SPIM0, SPIS0 - only one of these can be enabled." -#endif - -#if ((defined(SPIM0_ENABLED) && defined(SPI0_ENABLED)) &&\ - ((SPIM0_ENABLED + SPI0_ENABLED) > 1)) -#error "Peripherals overlap. SPIM0, SPI0 - only one of these can be enabled." -#endif - -#if ((defined(SPIM0_ENABLED) && defined(TWI0_ENABLED)) &&\ - ((SPIM0_ENABLED + TWI0_ENABLED) > 1)) -#error "Peripherals overlap. SPIM0, TWI0 - only one of these can be enabled." -#endif - -#if ((defined(SPIS0_ENABLED) && defined(SPI0_ENABLED)) &&\ - ((SPIS0_ENABLED + SPI0_ENABLED) > 1)) -#error "Peripherals overlap. SPIS0, SPI0 - only one of these can be enabled." -#endif - -#if ((defined(SPIS0_ENABLED) && defined(TWI0_ENABLED)) &&\ - ((SPIS0_ENABLED + TWI0_ENABLED) > 1)) -#error "Peripherals overlap. SPIS0, TWI0 - only one of these can be enabled." -#endif - -#if ((defined(SPI0_ENABLED) && defined(TWI0_ENABLED)) &&\ - ((SPI0_ENABLED + TWI0_ENABLED) > 1)) -#error "Peripherals overlap. SPI0, TWI0 - only one of these can be enabled." -#endif - -#if ((defined(TWIM1_ENABLED) && defined(TWIS1_ENABLED)) &&\ - ((TWIM1_ENABLED + TWIS1_ENABLED) > 1)) -#error "Peripherals overlap. TWIM1, TWIS1 - only one of these can be enabled." -#endif - -#if ((defined(TWIM1_ENABLED) && defined(SPIM1_ENABLED)) &&\ - ((TWIM1_ENABLED + SPIM1_ENABLED) > 1)) -#error "Peripherals overlap. TWIM1, SPIM1 - only one of these can be enabled." -#endif - -#if ((defined(TWIM1_ENABLED) && defined(SPIS1_ENABLED)) &&\ - ((TWIM1_ENABLED + SPIS1_ENABLED) > 1)) -#error "Peripherals overlap. TWIM1, SPIS1 - only one of these can be enabled." -#endif - -#if ((defined(TWIM1_ENABLED) && defined(SPI1_ENABLED)) &&\ - ((TWIM1_ENABLED + SPI1_ENABLED) > 1)) -#error "Peripherals overlap. TWIM1, SPI1 - only one of these can be enabled." -#endif - -#if ((defined(TWIM1_ENABLED) && defined(TWI1_ENABLED)) &&\ - ((TWIM1_ENABLED + TWI1_ENABLED) > 1)) -#error "Peripherals overlap. TWIM1, TWI1 - only one of these can be enabled." -#endif - -#if ((defined(TWIS1_ENABLED) && defined(SPIM1_ENABLED)) &&\ - ((TWIS1_ENABLED + SPIM1_ENABLED) > 1)) -#error "Peripherals overlap. TWIS1, SPIM1 - only one of these can be enabled." -#endif - -#if ((defined(TWIS1_ENABLED) && defined(SPIS1_ENABLED)) &&\ - ((TWIS1_ENABLED + SPIS1_ENABLED) > 1)) -#error "Peripherals overlap. TWIS1, SPIS1 - only one of these can be enabled." -#endif - -#if ((defined(TWIS1_ENABLED) && defined(SPI1_ENABLED)) &&\ - ((TWIS1_ENABLED + SPI1_ENABLED) > 1)) -#error "Peripherals overlap. TWIS1, SPI1 - only one of these can be enabled." -#endif - -#if ((defined(TWIS1_ENABLED) && defined(TWI1_ENABLED)) &&\ - ((TWIS1_ENABLED + TWI1_ENABLED) > 1)) -#error "Peripherals overlap. TWIS1, TWI1 - only one of these can be enabled." -#endif - -#if ((defined(SPIM1_ENABLED) && defined(SPIS1_ENABLED)) &&\ - ((SPIM1_ENABLED + SPIS1_ENABLED) > 1)) -#error "Peripherals overlap. SPIM1, SPIS1 - only one of these can be enabled." -#endif - -#if ((defined(SPIM1_ENABLED) && defined(SPI1_ENABLED)) &&\ - ((SPIM1_ENABLED + SPI1_ENABLED) > 1)) -#error "Peripherals overlap. SPIM1, SPI1 - only one of these can be enabled." -#endif - -#if ((defined(SPIM1_ENABLED) && defined(TWI1_ENABLED)) &&\ - ((SPIM1_ENABLED + TWI1_ENABLED) > 1)) -#error "Peripherals overlap. SPIM1, TWI1 - only one of these can be enabled." -#endif - -#if ((defined(SPIS1_ENABLED) && defined(SPI1_ENABLED)) &&\ - ((SPIS1_ENABLED + SPI1_ENABLED) > 1)) -#error "Peripherals overlap. SPIS1, SPI1 - only one of these can be enabled." -#endif - -#if ((defined(SPIS1_ENABLED) && defined(TWI1_ENABLED)) &&\ - ((SPIS1_ENABLED + TWI1_ENABLED) > 1)) -#error "Peripherals overlap. SPIS1, TWI1 - only one of these can be enabled." -#endif - -#if ((defined(SPI1_ENABLED) && defined(TWI1_ENABLED)) &&\ - ((SPI1_ENABLED + TWI1_ENABLED) > 1)) -#error "Peripherals overlap. SPI1, TWI1 - only one of these can be enabled." -#endif - -#if ((defined(SPI2_ENABLED) && defined(SPIS2_ENABLED)) &&\ - ((SPI2_ENABLED + SPIS2_ENABLED) > 1)) -#error "Peripherals overlap. SPI2, SPIS2 - only one of these can be enabled." -#endif - -#if ((defined(SPIM2_ENABLED) && defined(SPIS2_ENABLED)) &&\ - ((SPI2_ENABLED + SPIS2_ENABLED) > 1)) -#error "Peripherals overlap. SPIM2, SPIS2 - only one of these can be enabled." -#endif - -#if ((defined(SPIM2_ENABLED) && defined(SPI2_ENABLED)) &&\ - ((SPI2_ENABLED + SPIS2_ENABLED) > 1)) -#error "Peripherals overlap. SPIM2, SPI2 - only one of these can be enabled." -#endif - -#endif // !NRFX_CHECK(NRFX_PRS_ENABLED) - -#ifdef NFCT_PRESENT - -#if ((defined(NFC_HAL_ENABLED) && defined(CLOCK_ENABLED)) &&\ - ((NFC_HAL_ENABLED) && (!CLOCK_ENABLED))) -#error "NFC_HAL requires CLOCK to work. NFC_HAL can not be enabled without CLOCK." -#endif - -#if ((defined(NFC_HAL_ENABLED) && defined(TIMER4_ENABLED)) &&\ - ((NFC_HAL_ENABLED + TIMER4_ENABLED) > 1)) -#error "TIMER4 is used by NFC_HAL. NFC_HAL, TIMER4 - only one of these can be enabled." -#endif - -#endif -// Complex driver validation -#ifdef LPCOMP_PRESENT - -#if ((defined(COMP_ENABLED) && defined(LPCOMP_ENABLED)) && \ - (!NRFX_CHECK(NRFX_PRS_ENABLED)) && \ - ((COMP_ENABLED + LPCOMP_ENABLED) > 1)) -#error "Peripherals overlap. COMP, LPCOMP - only one of these can be enabled." -#endif - -#endif - - -#ifdef __cplusplus -} -#endif - -#endif // SDK_VALIDATION_H diff --git a/bsp/boards/nrf52840/sdk/components/toolchain/arm/uicr_config.h b/bsp/boards/nrf52840/sdk/components/toolchain/arm/uicr_config.h deleted file mode 100644 index 079e12260b..0000000000 --- a/bsp/boards/nrf52840/sdk/components/toolchain/arm/uicr_config.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - * Copyright (c) 2013 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/* Template files (including this one) are application specific and therefore expected to - be copied into the application project folder prior to its use! */ - -#ifndef _UICR_CONFIG_H -#define _UICR_CONFIG_H - -/*lint ++flb "Enter library region" */ - -#include - -/* - * Include this file in your project if you want to include in your compiled code files data - * for the User Information Configuration Registers (UICR) area; see nRF51 Series Reference - * Manual chapter User Information Configuration Registers. This file declares one variable - * per register of the UICR area and informs the linker where to place them. To include - * the desired value in the desired address, uncomment the variable with the proper address - * at the target area and update the assignment value. - * - * Please note that UICR values are stored in a reserved area of the flash and should only be - * stored into when downloading a hex file. Do not use these defined variables to store data - * at run time. - * - * Note as well that this file uses one non-standard attribute ("at"). It will only function - * with the ARMCC compiler toolset. - * - * Note that the hex file generated when this file is included will fail to download when using - * the standard download algorithm provided by Nordic. See example project "uicr_config_example" - * in any of the board example folders for an example of the recommended download method as well - * as the documentation that follows with the SDK. nrfjprog can be used as normal. - * - * Please note as well that if you are using a SoftDevice the UICR_CLENR0 address will - * already be in use. Do not uncomment that line. - */ - -// const uint32_t UICR_CLENR0 __attribute__((at(0x10001000))) __attribute__((used)) = 0xFFFFFFFF; // WARNING: This address might be used by the SoftDevice. Use with care. -// const uint32_t UICR_RBPCONF __attribute__((at(0x10001004))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_XTALFREQ __attribute__((at(0x10001008))) __attribute__((used)) = 0xFFFFFFFF; - -// const uint32_t UICR_ADDR_0x80 __attribute__((at(0x10001080))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0x84 __attribute__((at(0x10001084))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0x88 __attribute__((at(0x10001088))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0x8C __attribute__((at(0x1000108C))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0x90 __attribute__((at(0x10001090))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0x94 __attribute__((at(0x10001094))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0x98 __attribute__((at(0x10001098))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0x9C __attribute__((at(0x1000109C))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0xA0 __attribute__((at(0x100010A0))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0xA4 __attribute__((at(0x100010A4))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0xA8 __attribute__((at(0x100010A8))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0xAC __attribute__((at(0x100010AC))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0xB0 __attribute__((at(0x100010B0))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0xB4 __attribute__((at(0x100010B4))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0xB8 __attribute__((at(0x100010B8))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0xBC __attribute__((at(0x100010BC))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0xC0 __attribute__((at(0x100010C0))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0xC4 __attribute__((at(0x100010C4))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0xC8 __attribute__((at(0x100010C8))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0xCC __attribute__((at(0x100010CC))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0xD0 __attribute__((at(0x100010D0))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0xD4 __attribute__((at(0x100010D4))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0xD8 __attribute__((at(0x100010D8))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0xDC __attribute__((at(0x100010DC))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0xE0 __attribute__((at(0x100010E0))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0xE4 __attribute__((at(0x100010E4))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0xE8 __attribute__((at(0x100010E8))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0xEC __attribute__((at(0x100010EC))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0xF0 __attribute__((at(0x100010F0))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0xF4 __attribute__((at(0x100010F4))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0xF8 __attribute__((at(0x100010F8))) __attribute__((used)) = 0xFFFFFFFF; -// const uint32_t UICR_ADDR_0xFC __attribute__((at(0x100010FC))) __attribute__((used)) = 0xFFFFFFFF; - -/*lint --flb "Leave library region" */ - -#endif //_UICR_CONFIG_H diff --git a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/dsp/license.txt b/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/dsp/license.txt deleted file mode 100644 index a4487ffcf9..0000000000 --- a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/dsp/license.txt +++ /dev/null @@ -1,28 +0,0 @@ -All pre-build libraries contained in the folders "ARM" and "GCC" -are guided by the following license: - -Copyright (C) 2009-2014 ARM Limited. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. diff --git a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/arm_common_tables.h b/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/arm_common_tables.h deleted file mode 100644 index d5d72417bd..0000000000 --- a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/arm_common_tables.h +++ /dev/null @@ -1,136 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. October 2015 -* $Revision: V.1.4.5 a -* -* Project: CMSIS DSP Library -* Title: arm_common_tables.h -* -* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern const uint16_t armBitRevTable[1024]; -extern const q15_t armRecipTableQ15[64]; -extern const q31_t armRecipTableQ31[64]; -/* extern const q31_t realCoefAQ31[1024]; */ -/* extern const q31_t realCoefBQ31[1024]; */ -extern const float32_t twiddleCoef_16[32]; -extern const float32_t twiddleCoef_32[64]; -extern const float32_t twiddleCoef_64[128]; -extern const float32_t twiddleCoef_128[256]; -extern const float32_t twiddleCoef_256[512]; -extern const float32_t twiddleCoef_512[1024]; -extern const float32_t twiddleCoef_1024[2048]; -extern const float32_t twiddleCoef_2048[4096]; -extern const float32_t twiddleCoef_4096[8192]; -#define twiddleCoef twiddleCoef_4096 -extern const q31_t twiddleCoef_16_q31[24]; -extern const q31_t twiddleCoef_32_q31[48]; -extern const q31_t twiddleCoef_64_q31[96]; -extern const q31_t twiddleCoef_128_q31[192]; -extern const q31_t twiddleCoef_256_q31[384]; -extern const q31_t twiddleCoef_512_q31[768]; -extern const q31_t twiddleCoef_1024_q31[1536]; -extern const q31_t twiddleCoef_2048_q31[3072]; -extern const q31_t twiddleCoef_4096_q31[6144]; -extern const q15_t twiddleCoef_16_q15[24]; -extern const q15_t twiddleCoef_32_q15[48]; -extern const q15_t twiddleCoef_64_q15[96]; -extern const q15_t twiddleCoef_128_q15[192]; -extern const q15_t twiddleCoef_256_q15[384]; -extern const q15_t twiddleCoef_512_q15[768]; -extern const q15_t twiddleCoef_1024_q15[1536]; -extern const q15_t twiddleCoef_2048_q15[3072]; -extern const q15_t twiddleCoef_4096_q15[6144]; -extern const float32_t twiddleCoef_rfft_32[32]; -extern const float32_t twiddleCoef_rfft_64[64]; -extern const float32_t twiddleCoef_rfft_128[128]; -extern const float32_t twiddleCoef_rfft_256[256]; -extern const float32_t twiddleCoef_rfft_512[512]; -extern const float32_t twiddleCoef_rfft_1024[1024]; -extern const float32_t twiddleCoef_rfft_2048[2048]; -extern const float32_t twiddleCoef_rfft_4096[4096]; - - -/* floating-point bit reversal tables */ -#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) -#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) -#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) -#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) -#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) -#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) -#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) -#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; - -/* fixed-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) -#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) -#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) -#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) -#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) -#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) -#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) -#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; - -/* Tables for Fast Math Sine and Cosine */ -extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; -extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; -extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; - -#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/arm_const_structs.h b/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/arm_const_structs.h deleted file mode 100644 index 54595f55d4..0000000000 --- a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/arm_const_structs.h +++ /dev/null @@ -1,79 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_const_structs.h -* -* Description: This file has constant structs that are initialized for -* user convenience. For example, some can be given as -* arguments to the arm_cfft_f32() function. -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_CONST_STRUCTS_H -#define _ARM_CONST_STRUCTS_H - -#include "arm_math.h" -#include "arm_common_tables.h" - - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; - - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; - - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; - -#endif diff --git a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/arm_math.h b/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/arm_math.h deleted file mode 100644 index 0be65d335c..0000000000 --- a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/arm_math.h +++ /dev/null @@ -1,7030 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2015 ARM Limited. All rights reserved. -* -* $Date: 20. October 2015 -* $Revision: V1.4.5 b -* -* Project: CMSIS DSP Library -* Title: arm_math.h -* -* Description: Public header file for CMSIS DSP Library -* -* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. - * -------------------------------------------------------------------- */ - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -/* ignore some GCC warnings */ -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" -#endif - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined(ARM_MATH_CM7) - #include "core_cm7.h" -#elif defined (ARM_MATH_CM4) - #include "core_cm4.h" -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_CM0PLUS) - #include "core_cm0plus.h" - #define ARM_MATH_CM0_FAMILY -#else - #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI -#define PI 3.14159265358979f -#endif - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define FAST_MATH_TABLE_SIZE 512 -#define FAST_MATH_Q31_SHIFT (32 - 10) -#define FAST_MATH_Q15_SHIFT (16 - 10) -#define CONTROLLER_Q31_SHIFT (32 - 9) -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x400000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - /** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#if defined __CC_ARM - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED __attribute__((unused)) - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - -#elif defined __GNUC__ - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - -#elif defined __ICCARM__ - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED - -#elif defined __CSMC__ - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED - -#elif defined __TASKING__ - #define __SIMD32_TYPE __unaligned int32_t - #define CMSIS_UNUSED - -#else - #error Unknown compiler -#endif - -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) -#define __SIMD64(addr) (*(int64_t **) & (addr)) - -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -#endif - - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - static __INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - static __INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - static __INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - static __INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - static __INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - -/* - #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) - #define __CLZ __clz - #endif - */ -/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) - static __INLINE uint32_t __CLZ( - q31_t data); - - static __INLINE uint32_t __CLZ( - q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while ((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return (count); - } -#endif - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. - */ - - static __INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - q31_t out; - uint32_t tempVal; - uint32_t index, i; - uint32_t signBits; - - if (in > 0) - { - signBits = ((uint32_t) (__CLZ( in) - 1)); - } - else - { - signBits = ((uint32_t) (__CLZ(-in) - 1)); - } - - /* Convert input sample to 1.31 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 24); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (uint32_t) (((q63_t) in * out) >> 31); - tempVal = 0x7FFFFFFFu - tempVal; - /* 1.31 with exp 1 */ - /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ - out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - } - - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. - */ - static __INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - q15_t out = 0; - uint32_t tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if (in > 0) - { - signBits = ((uint32_t)(__CLZ( in) - 17)); - } - else - { - signBits = ((uint32_t)(__CLZ(-in) - 17)); - } - - /* Convert input sample to 1.15 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 8); - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (uint32_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFFu - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0_FAMILY) - static __INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if (x > 0) - { - posMax = (posMax - 1); - - if (x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if (x < negMin) - { - x = negMin; - } - } - return (x); - } -#endif /* end of ARM_MATH_CM0_FAMILY */ - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - static __INLINE uint32_t __QADD8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - static __INLINE uint32_t __QSUB8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - static __INLINE uint32_t __QADD16( - uint32_t x, - uint32_t y) - { -/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ - q31_t r = 0, s = 0; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - static __INLINE uint32_t __SHADD16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - static __INLINE uint32_t __QSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - static __INLINE uint32_t __SHSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - static __INLINE uint32_t __QASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - static __INLINE uint32_t __SHASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - static __INLINE uint32_t __QSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - static __INLINE uint32_t __SHSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - static __INLINE uint32_t __SMUSDX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - static __INLINE uint32_t __SMUADX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - static __INLINE int32_t __QADD( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); - } - - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - static __INLINE int32_t __QSUB( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); - } - - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - static __INLINE uint32_t __SMLAD( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - static __INLINE uint32_t __SMLADX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - static __INLINE uint32_t __SMLSDX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - static __INLINE uint64_t __SMLALD( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - static __INLINE uint64_t __SMLALDX( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - static __INLINE uint32_t __SMUAD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - static __INLINE uint32_t __SMUSD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SXTB16 for M3 and M0 processors - */ - static __INLINE uint32_t __SXTB16( - uint32_t x) - { - return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | - ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); - } - -#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps + blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps + blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps + blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps + blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] S points to an instance of the Q7 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] S points to an instance of the Q15 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] S points to an instance of the Q31 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] S points to an instance of the floating-point FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q15; - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_casd_df1_inst_f32; - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float64_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f64; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q31; - - - /** - * @brief Floating-point matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pScratch); - - - /** - * @brief Q31, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q31 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix scaling. - * @param[in] pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - - - /** - * @brief Q15 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#ifdef ARM_MATH_CM0_FAMILY - q15_t A1; - q15_t A2; -#else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ -#endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] S points to an instance of the q15 PID Control structure - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - -/* Deprecated */ - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q15; - -void arm_cfft_q15( - const arm_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q31; - -void arm_cfft_q31( - const arm_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_f32; - - void arm_cfft_f32( - const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ -typedef struct - { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f32 ; - -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); - -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] S points to an instance of the Q31 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] S points to an instance of the Q15 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - - /** - * @brief Floating-point vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Dot product of floating-point vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - - /** - * @brief Dot product of Q7 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - - /** - * @brief Dot product of Q15 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Dot product of Q31 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen + srcBLen-1. - */ - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen + srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen + srcBLen-1. - */ - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen + srcBLen-1. - */ - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen + srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen + srcBLen-1. - */ - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen + srcBLen-1. - */ - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen + srcBLen-1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen + srcBLen-1. - */ - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen + srcBLen-2]. - */ - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen + srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen + srcBLen-2]. - */ - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen + srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen + srcBLen-2]. - */ - arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen + srcBLen-2]. - */ - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen + srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q7 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen + srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen + srcBLen-2]. - */ - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps + blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps + blockSize-1. */ - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps + blockSize-1. */ - } arm_fir_decimate_instance_f32; - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] S points to an instance of the floating-point FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize + phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize + phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength + numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_stereo_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f64; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_stereo_df2T_f32( - const arm_biquad_cascade_stereo_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f64( - const arm_biquad_cascade_df2T_instance_f64 * S, - float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_stereo_df2T_init_f32( - arm_biquad_cascade_stereo_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f64( - arm_biquad_cascade_df2T_instance_f64 * S, - uint8_t numStages, - float64_t * pCoeffs, - float64_t * pState); - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages + blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages + 1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages + blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages + 1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages + blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages + 1. */ - } arm_iir_lattice_instance_f32; - - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages + 1. - * @param[in] pState points to the state buffer. The array is of length numStages + blockSize-1. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages + 1. - * @param[in] pState points to the state buffer. The array is of length numStages + blockSize. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the Q15 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages + 1. - * @param[in] pState points to state buffer. The array is of length numStages + blockSize. - * @param[in] blockSize number of samples to process per call. - */ - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps + blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps + blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps + blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q31; - - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps + blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps + blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps + blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Correlation of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Correlation of Q15 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay + blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay + blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay + blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay + blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] S points to an instance of the floating-point sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] S points to an instance of the Q31 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] S points to an instance of the Q15 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] S points to an instance of the Q7 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cos output. - */ - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCosVal); - - - /** - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cosine output. - */ - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - static __INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - static __INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - static __INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - -#ifndef ARM_MATH_CM0_FAMILY - __SIMD32_TYPE *vstate; - - /* Implementation of PID controller */ - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); -#else - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; -#endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f64( - const arm_matrix_instance_f64 * src, - arm_matrix_instance_f64 * dst); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - */ - static __INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - } - - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - static __INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - */ - static __INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; - } - - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - static __INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * The function implements the forward Park transform. - * - */ - static __INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - } - - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - static __INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - */ - static __INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - static __INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - static __INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if (i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if ((uint32_t)i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - - } - - /* returns output value */ - return (y); - } - - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - static __INLINE q31_t arm_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (q31_t)0xFFF00000) >> 20); - - if (index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if (index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - } - } - - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - static __INLINE q15_t arm_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (int32_t)0xFFF00000) >> 20); - - if (index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if (index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (q15_t) (y >> 20); - } - } - - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - static __INLINE q7_t arm_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) - { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - - if (index >= (nValues - 1)) - { - return (pYData[nValues - 1]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (q7_t) (y >> 20); - } - } - - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - float32_t arm_sin_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q31_t arm_sin_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q15_t arm_sin_q15( - q15_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - float32_t arm_cos_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q31_t arm_cos_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate, and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - static __INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t * pOut) - { - if (in >= 0.0f) - { - -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); -#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined(__GNUC__) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) - __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); -#else - *pOut = sqrtf(in); -#endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); - - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); - - /** - * @} end of SQRT group - */ - - - /** - * @brief floating-point Circular write function. - */ - static __INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - static __INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if (dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q15 Circular write function. - */ - static __INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q15 Circular Read function. - */ - static __INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if (dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - static __INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q7 Circular Read function. - */ - static __INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if (dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - - /** - * @brief Mean value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Mean value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Floating-point complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - - /** - * @brief Q31 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - - /** - * @brief Floating-point complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - */ - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[in] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF + 1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF + 1) * (1-(x-XF))*(y-YF)
-   *           + f(XF + 1, YF + 1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - static __INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) - { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - } - - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - static __INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; - x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; - y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return ((q31_t)(acc << 2)); - } - - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - static __INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return ((q15_t)(acc >> 36)); - } - - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - static __INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return ((q7_t)(acc >> 40)); - } - - /** - * @} end of BilinearInterpolate group - */ - - -/* SMMLAR */ -#define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMLSR */ -#define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMULR */ -#define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -/* SMMLA */ -#define multAcc_32x32_keep32(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - -/* SMMLS */ -#define multSub_32x32_keep32(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -/* SMMUL */ -#define mult_32x32_keep32(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - - -#if defined ( __CC_ARM ) - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") - #else - #define LOW_OPTIMIZATION_EXIT - #endif - - /* Enter low optimization region - place directly above function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__GNUC__) - #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__ICCARM__) - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define LOW_OPTIMIZATION_EXIT - - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__CSMC__) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__TASKING__) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#endif - - -#ifdef __cplusplus -} -#endif - - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -#endif /* _ARM_MATH_H */ - -/** - * - * End of file. - */ diff --git a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/cmsis_armcc.h b/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/cmsis_armcc.h deleted file mode 100644 index f2bb66a09a..0000000000 --- a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/cmsis_armcc.h +++ /dev/null @@ -1,734 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_ARMCC_H -#define __CMSIS_ARMCC_H - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xFFU); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xFFU); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - - -#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() do {\ - __schedule_barrier();\ - __isb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() do {\ - __schedule_barrier();\ - __dsb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() do {\ - __schedule_barrier();\ - __dmb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - #define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ - return(result); -} -#endif - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) -#else - #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) -#else - #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) -#else - #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXB(value, ptr) __strex(value, ptr) -#else - #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXH(value, ptr) __strex(value, ptr) -#else - #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXW(value, ptr) __strex(value, ptr) -#else - #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ - -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32U) ) >> 32U)) - -#endif /* (__CORTEX_M >= 0x04) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/cmsis_gcc.h b/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/cmsis_gcc.h deleted file mode 100644 index d868f2e64b..0000000000 --- a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/cmsis_gcc.h +++ /dev/null @@ -1,1373 +0,0 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03U) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03U) */ - - -#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); -} - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x04) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -#endif /* __CMSIS_GCC_H */ diff --git a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_cm0.h b/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_cm0.h deleted file mode 100644 index 70b5b424bb..0000000000 --- a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_cm0.h +++ /dev/null @@ -1,798 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M0 - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000U - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for (;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_cm0plus.h b/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_cm0plus.h deleted file mode 100644 index 58ef33938d..0000000000 --- a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_cm0plus.h +++ /dev/null @@ -1,914 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex-M0+ - @{ - */ - -/* CMSIS CM0+ definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ - __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000U - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if (__VTOR_PRESENT == 1U) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0+ header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0+ Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for (;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_cm3.h b/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_cm3.h deleted file mode 100644 index 915ba1149a..0000000000 --- a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_cm3.h +++ /dev/null @@ -1,1763 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200U - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201U) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1U]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for (;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_cm7.h b/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_cm7.h deleted file mode 100644 index 92054b880e..0000000000 --- a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_cm7.h +++ /dev/null @@ -1,2512 +0,0 @@ -/**************************************************************************//** - * @file core_cm7.h - * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM7_H_GENERIC -#define __CORE_CM7_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M7 - @{ - */ - -/* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x07U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ -#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM7_H_DEPENDANT -#define __CORE_CM7_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM7_REV - #define __CM7_REV 0x0000U - #warning "__CM7_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0U - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0U - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DTCM_PRESENT - #define __DTCM_PRESENT 0U - #warning "__DTCM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M7 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1U]; - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED3[93U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ - -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ -#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ - -#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ -#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED3[981U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and FP Feature Register 2 Definitions */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1U) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for (;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = SCB->MVFR0; - if ((mvfr0 & 0x00000FF0UL) == 0x220UL) - { - return 2UL; /* Double + Single precision FPU */ - } - else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) - { - return 1UL; /* Single precision FPU */ - } - else - { - return 0UL; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## Cache functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) - - -/** - \brief Enable I-Cache - \details Turns on I-Cache - */ -__STATIC_INLINE void SCB_EnableICache (void) -{ - #if (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable I-Cache - \details Turns off I-Cache - */ -__STATIC_INLINE void SCB_DisableICache (void) -{ - #if (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate I-Cache - \details Invalidates I-Cache - */ -__STATIC_INLINE void SCB_InvalidateICache (void) -{ - #if (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Enable D-Cache - \details Turns on D-Cache - */ -__STATIC_INLINE void SCB_EnableDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while (sets--); - __DSB(); - - SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable D-Cache - \details Turns off D-Cache - */ -__STATIC_INLINE void SCB_DisableDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while (sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate D-Cache - \details Invalidates D-Cache - */ -__STATIC_INLINE void SCB_InvalidateDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while (sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean D-Cache - \details Cleans D-Cache - */ -__STATIC_INLINE void SCB_CleanDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | - ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while (sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean & Invalidate D-Cache - \details Cleans and Invalidates D-Cache - */ -__STATIC_INLINE void SCB_CleanInvalidateDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while (sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Invalidate by address - \details Invalidates D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t)addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCIMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean by address - \details Cleans D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean and Invalidate by address - \details Cleans and invalidates D_Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCIMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/*@} end of CMSIS_Core_CacheFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_cmFunc.h b/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_cmFunc.h deleted file mode 100644 index cb1ebf89a3..0000000000 --- a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_cmFunc.h +++ /dev/null @@ -1,86 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - -#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_cmInstr.h b/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_cmInstr.h deleted file mode 100644 index a0a506458d..0000000000 --- a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_cmInstr.h +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_cmSimd.h b/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_cmSimd.h deleted file mode 100644 index 4d76bf9018..0000000000 --- a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_cmSimd.h +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************//** - * @file core_cmSimd.h - * @brief CMSIS Cortex-M SIMD Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMSIMD_H -#define __CORE_CMSIMD_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CMSIMD_H */ diff --git a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_sc000.h b/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_sc000.h deleted file mode 100644 index 43ec9c3bd4..0000000000 --- a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_sc000.h +++ /dev/null @@ -1,926 +0,0 @@ -/**************************************************************************//** - * @file core_sc000.h - * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC000_H_GENERIC -#define __CORE_SC000_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC000 - @{ - */ - -/* CMSIS SC000 definitions */ -#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ - __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (000U) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC000_H_DEPENDANT -#define __CORE_SC000_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC000_REV - #define __SC000_REV 0x0000U - #warning "__SC000_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC000 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - uint32_t RESERVED1[154U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the SC000 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of SC000 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for (;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_sc300.h b/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_sc300.h deleted file mode 100644 index 420a655e46..0000000000 --- a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_sc300.h +++ /dev/null @@ -1,1745 +0,0 @@ -/**************************************************************************//** - * @file core_sc300.h - * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC300_H_GENERIC -#define __CORE_SC300_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC3000 - @{ - */ - -/* CMSIS SC300 definitions */ -#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ - __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (300U) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC300_H_DEPENDANT -#define __CORE_SC300_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC300_REV - #define __SC300_REV 0x0000U - #warning "__SC300_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC300 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED1[129U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - uint32_t RESERVED1[1U]; -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for (;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/boards/nrf52840/sdk/components/toolchain/gcc/Makefile.common b/bsp/boards/nrf52840/sdk/components/toolchain/gcc/Makefile.common deleted file mode 100644 index 61197539a6..0000000000 --- a/bsp/boards/nrf52840/sdk/components/toolchain/gcc/Makefile.common +++ /dev/null @@ -1,307 +0,0 @@ -# Copyright (c) 2016 - 2017, Nordic Semiconductor ASA -# -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without modification, -# are permitted provided that the following conditions are met: -# -# 1. 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$(call get_inc_paths, \ - $(INC_FOLDERS) $(call target_specific, INC_FOLDERS, $(1)))) -endef - -# $1 target name -define define_target -$(eval OUTPUT_FILE := $(OUTPUT_DIRECTORY)/$(strip $(1))) \ -$(eval $(1): $(OUTPUT_FILE).out $(OUTPUT_FILE).hex $(OUTPUT_FILE).bin \ - ; @echo DONE $(strip $(1))) \ -$(call prepare_build, $(1), $(OUTPUT_FILE).inc, $(OUTPUT_FILE).out) -endef - -# $1 target name -# $2 library file name -define define_library -$(eval OUTPUT_FILE := $(OUTPUT_DIRECTORY)/$(strip $(1))) \ -$(eval $(1) := $(2)) \ -$(call prepare_build, $(1), $(OUTPUT_FILE).inc, $(1)) -endef - -# $1 content to be dumped -# Invokes another instance of MAKE to dump the specified content to stdout, -# which may be then redirected in shell to a file and this way stored there. -# MAKE in version prior to 4.0 does not provide the $(file ...) function. -define dump -$(eval CONTENT_TO_DUMP := $(1)) \ -"$(MAKE)" -s --no-print-directory \ - -f "$(TEMPLATE_PATH)/dump.mk" VARIABLE=CONTENT_TO_DUMP -endef -export CONTENT_TO_DUMP - -.PHONY: $(TARGETS) all - -all: $(TARGETS) - -# Create build directories -$(OUTPUT_DIRECTORY): - $(MK) $@ -$(OUTPUT_DIRECTORY)/%/.: | $(OUTPUT_DIRECTORY) - cd $(OUTPUT_DIRECTORY) && $(MK) $* - -$(OUTPUT_DIRECTORY)/%.inc: Makefile | $(OUTPUT_DIRECTORY) - $(info Generating $@) - $(NO_ECHO)$(call dump, $(call target_specific, INC_PATHS, $*)) > $@ - -# $1 command -# $2 flags -# $3 message -define run -$(info $(call PROGRESS,$(3) file: $(notdir $($@)))) \ -$(NO_ECHO)$(1) -MP -MD -c -o $@ $(call get_path,$($@)) $(2) $(INC_PATHS) -endef - -# Create object files from C source files -%.c.o: - $(call run,$(CC) -std=c99,$(CFLAGS),Compiling) - -# Create object files from C++ source files -%.cpp.o: - $(call run,$(CXX),$(CFLAGS) $(CXXFLAGS),Compiling) - -# Create object files from assembly source files -%.S.o %.s.o.o: - $(call run,$(CC) -x assembler-with-cpp,$(ASMFLAGS),Assembling) - -ifeq ($(PASS_LINKER_INPUT_VIA_FILE),1) -GENERATE_LD_INPUT_FILE = $(call dump, $^ $(LIB_FILES)) > $(@:.out=.in) -LD_INPUT = @$(@:.out=.in) -else -GENERATE_LD_INPUT_FILE = -LD_INPUT = $^ $(LIB_FILES) -endif - -# Link object files -%.out: - $(info $(call PROGRESS,Linking target: $@)) - $(NO_ECHO)$(GENERATE_LD_INPUT_FILE) - $(NO_ECHO)$(CC) $(LDFLAGS) $(LD_INPUT) -Wl,-Map=$(@:.out=.map) -o $@ - $(NO_ECHO)$(SIZE) $@ - -# Create binary .bin file from the .out file -%.bin: %.out - $(info Preparing: $@) - $(NO_ECHO)$(OBJCOPY) -O binary $< $@ - -# Create binary .hex file from the .out file -%.hex: %.out - $(info Preparing: $@) - $(NO_ECHO)$(OBJCOPY) -O ihex $< $@ - -endif # ifneq (,$(filter clean, $(MAKECMDGOALS))) diff --git a/bsp/boards/nrf52840/sdk/components/toolchain/gcc/Makefile.posix b/bsp/boards/nrf52840/sdk/components/toolchain/gcc/Makefile.posix deleted file mode 100644 index 757c41b181..0000000000 --- a/bsp/boards/nrf52840/sdk/components/toolchain/gcc/Makefile.posix +++ /dev/null @@ -1,3 +0,0 @@ -GNU_INSTALL_ROOT ?= /usr/local/gcc-arm-none-eabi-6-2017-q2-update/bin/ -GNU_VERSION ?= 6.3.1 -GNU_PREFIX ?= arm-none-eabi diff --git a/bsp/boards/nrf52840/sdk/components/toolchain/gcc/Makefile.windows b/bsp/boards/nrf52840/sdk/components/toolchain/gcc/Makefile.windows deleted file mode 100644 index f659ac82c8..0000000000 --- a/bsp/boards/nrf52840/sdk/components/toolchain/gcc/Makefile.windows +++ /dev/null @@ -1,3 +0,0 @@ -GNU_INSTALL_ROOT := C:/Program Files (x86)/GNU Tools ARM Embedded/6 2017-q2-update/bin/ -GNU_VERSION := 6.3.1 -GNU_PREFIX := arm-none-eabi diff --git a/bsp/boards/nrf52840/sdk/components/toolchain/gcc/dump.mk b/bsp/boards/nrf52840/sdk/components/toolchain/gcc/dump.mk deleted file mode 100644 index 8b1299f3f1..0000000000 --- a/bsp/boards/nrf52840/sdk/components/toolchain/gcc/dump.mk +++ /dev/null @@ -1,2 +0,0 @@ -$(info $($(VARIABLE))) -all: ; diff --git a/bsp/boards/nrf52840/sdk/components/toolchain/gcc/gcc_nrf51_common.ld b/bsp/boards/nrf52840/sdk/components/toolchain/gcc/gcc_nrf51_common.ld deleted file mode 100644 index 266835b94d..0000000000 --- a/bsp/boards/nrf52840/sdk/components/toolchain/gcc/gcc_nrf51_common.ld +++ /dev/null @@ -1,164 +0,0 @@ -/* Linker script for Nordic Semiconductor nRF5 devices - * - * Version: Sourcery G++ 4.5-1 - * Support: https://support.codesourcery.com/GNUToolchain/ - * - * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc. - * - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - */ -OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.Vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - *(.eh_frame*) - . = ALIGN(4); - } > FLASH - - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - . = ALIGN(4); - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - . = ALIGN(4); - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - *(.preinit_array) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - *(SORT(.init_array.*)) - *(.init_array) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - *(SORT(.fini_array.*)) - *(.fini_array) - PROVIDE_HIDDEN (__fini_array_end = .); - - *(.jcr) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY): - { - __end__ = .; - end = __end__; - *(.heap*) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} - diff --git a/bsp/boards/nrf52840/sdk/components/toolchain/iar/iar_nrf51_blank_xxaa.icf b/bsp/boards/nrf52840/sdk/components/toolchain/iar/iar_nrf51_blank_xxaa.icf deleted file mode 100644 index a05fa11d01..0000000000 --- a/bsp/boards/nrf52840/sdk/components/toolchain/iar/iar_nrf51_blank_xxaa.icf +++ /dev/null @@ -1,31 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x800; -define symbol __ICFEDIT_size_heap__ = 0x800; -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -keep { section .intvec }; -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, - block HEAP }; diff --git a/bsp/boards/nrf52840/sdk/components/toolchain/iar/iar_nrf51_blank_xxac.icf b/bsp/boards/nrf52840/sdk/components/toolchain/iar/iar_nrf51_blank_xxac.icf deleted file mode 100644 index ee54a3ce47..0000000000 --- a/bsp/boards/nrf52840/sdk/components/toolchain/iar/iar_nrf51_blank_xxac.icf +++ /dev/null @@ -1,31 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x800; -define symbol __ICFEDIT_size_heap__ = 0x800; -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -keep { section .intvec }; -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, - block HEAP }; diff --git a/bsp/boards/nrf52840/sdk/config/nrf52840/armgcc/generic_gcc_nrf52.ld b/bsp/boards/nrf52840/sdk/config/nrf52840/armgcc/generic_gcc_nrf52.ld deleted file mode 100644 index 447bcb12d6..0000000000 --- a/bsp/boards/nrf52840/sdk/config/nrf52840/armgcc/generic_gcc_nrf52.ld +++ /dev/null @@ -1,117 +0,0 @@ -/* Linker script to configure memory regions. */ - -SEARCH_DIR(.) -GROUP(-lgcc -lc -lnosys) - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x26000, LENGTH = 0xda000 - RAM (rwx) : ORIGIN = 0x200057b8, LENGTH = 0x3a848 -} - -SECTIONS -{ -} - -SECTIONS -{ - . = ALIGN(4); - .mem_section_dummy_ram : - { - } - .cli_sorted_cmd_ptrs : - { - PROVIDE(__start_cli_sorted_cmd_ptrs = .); - KEEP(*(.cli_sorted_cmd_ptrs)) - PROVIDE(__stop_cli_sorted_cmd_ptrs = .); - } > RAM - .fs_data : - { - PROVIDE(__start_fs_data = .); - KEEP(*(.fs_data)) - PROVIDE(__stop_fs_data = .); - } > RAM - .log_dynamic_data : - { - PROVIDE(__start_log_dynamic_data = .); - KEEP(*(SORT(.log_dynamic_data*))) - PROVIDE(__stop_log_dynamic_data = .); - } > RAM - -} INSERT AFTER .data; - -SECTIONS -{ - .mem_section_dummy_rom : - { - } - .sdh_ble_observers : - { - PROVIDE(__start_sdh_ble_observers = .); - KEEP(*(SORT(.sdh_ble_observers*))) - PROVIDE(__stop_sdh_ble_observers = .); - } > FLASH - .sdh_soc_observers : - { - PROVIDE(__start_sdh_soc_observers = .); - KEEP(*(SORT(.sdh_soc_observers*))) - PROVIDE(__stop_sdh_soc_observers = .); - } > FLASH - .sdh_state_observers : - { - PROVIDE(__start_sdh_state_observers = .); - KEEP(*(SORT(.sdh_state_observers*))) - PROVIDE(__stop_sdh_state_observers = .); - } > FLASH - .sdh_stack_observers : - { - PROVIDE(__start_sdh_stack_observers = .); - KEEP(*(SORT(.sdh_stack_observers*))) - PROVIDE(__stop_sdh_stack_observers = .); - } > FLASH - .sdh_req_observers : - { - PROVIDE(__start_sdh_req_observers = .); - KEEP(*(SORT(.sdh_req_observers*))) - PROVIDE(__stop_sdh_req_observers = .); - } > FLASH - .nrf_queue : - { - PROVIDE(__start_nrf_queue = .); - KEEP(*(.nrf_queue)) - PROVIDE(__stop_nrf_queue = .); - } > FLASH - .nrf_balloc : - { - PROVIDE(__start_nrf_balloc = .); - KEEP(*(.nrf_balloc)) - PROVIDE(__stop_nrf_balloc = .); - } > FLASH - .cli_command : - { - PROVIDE(__start_cli_command = .); - KEEP(*(.cli_command)) - PROVIDE(__stop_cli_command = .); - } > FLASH - .crypto_data : - { - PROVIDE(__start_crypto_data = .); - KEEP(*(SORT(.crypto_data*))) - PROVIDE(__stop_crypto_data = .); - } > FLASH - .pwr_mgmt_data : - { - PROVIDE(__start_pwr_mgmt_data = .); - KEEP(*(SORT(.pwr_mgmt_data*))) - PROVIDE(__stop_pwr_mgmt_data = .); - } > FLASH - .log_const_data : - { - PROVIDE(__start_log_const_data = .); - KEEP(*(SORT(.log_const_data*))) - PROVIDE(__stop_log_const_data = .); - } > FLASH - -} INSERT AFTER .text - -INCLUDE "nrf_common.ld" diff --git a/bsp/boards/nrf52840/sdk/config/nrf52840/config/sdk_config.h b/bsp/boards/nrf52840/sdk/config/nrf52840/config/sdk_config.h deleted file mode 100644 index 3ece11f347..0000000000 --- a/bsp/boards/nrf52840/sdk/config/nrf52840/config/sdk_config.h +++ /dev/null @@ -1,12106 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - - -#ifndef SDK_CONFIG_H -#define SDK_CONFIG_H -// <<< Use Configuration Wizard in Context Menu >>>\n -#ifdef USE_APP_CONFIG -#include "app_config.h" -#endif -// nRF_BLE - -//========================================================== -// BLE_ADVERTISING_ENABLED - ble_advertising - Advertising module - - -#ifndef BLE_ADVERTISING_ENABLED -#define BLE_ADVERTISING_ENABLED 0 -#endif - -// BLE_DTM_ENABLED - ble_dtm - Module for testing RF/PHY using DTM commands - - -#ifndef BLE_DTM_ENABLED -#define BLE_DTM_ENABLED 0 -#endif - -// BLE_RACP_ENABLED - ble_racp - Record Access Control Point library - - -#ifndef BLE_RACP_ENABLED -#define BLE_RACP_ENABLED 0 -#endif - -// NRF_BLE_QWR_ENABLED - nrf_ble_qwr - Queued writes support module (prepare/execute write) -//========================================================== -#ifndef NRF_BLE_QWR_ENABLED -#define NRF_BLE_QWR_ENABLED 0 -#endif -// NRF_BLE_QWR_MAX_ATTR - Maximum number of attribute handles that can be registered. This number must be adjusted according to the number of attributes for which Queued Writes will be enabled. If it is zero, the module will reject all Queued Write requests. -#ifndef NRF_BLE_QWR_MAX_ATTR -#define NRF_BLE_QWR_MAX_ATTR 0 -#endif - -// - -// PEER_MANAGER_ENABLED - peer_manager - Peer Manager -//========================================================== -#ifndef PEER_MANAGER_ENABLED -#define PEER_MANAGER_ENABLED 0 -#endif -// PM_MAX_REGISTRANTS - Number of event handlers that can be registered. -#ifndef PM_MAX_REGISTRANTS -#define PM_MAX_REGISTRANTS 3 -#endif - -// PM_FLASH_BUFFERS - Number of internal buffers for flash operations. -// Decrease this value to lower RAM usage. - -#ifndef PM_FLASH_BUFFERS -#define PM_FLASH_BUFFERS 2 -#endif - -// PM_CENTRAL_ENABLED - Enable/disable central-specific Peer Manager functionality. - - -// Enable/disable central-specific Peer Manager functionality. - -#ifndef PM_CENTRAL_ENABLED -#define PM_CENTRAL_ENABLED 1 -#endif - -// PM_SERVICE_CHANGED_ENABLED - Enable/disable the service changed management for GATT server in Peer Manager. - - -// If not using a GATT server, or using a server wihout a service changed characteristic, -// disable this to save code space. - -#ifndef PM_SERVICE_CHANGED_ENABLED -#define PM_SERVICE_CHANGED_ENABLED 1 -#endif - -// PM_PEER_RANKS_ENABLED - Enable/disable the peer rank management in Peer Manager. - - -// Set this to false to save code space if not using the peer rank API. - -#ifndef PM_PEER_RANKS_ENABLED -#define PM_PEER_RANKS_ENABLED 1 -#endif - -// - -// -//========================================================== - -// nRF_BLE_Services - -//========================================================== -// BLE_ANCS_C_ENABLED - ble_ancs_c - Apple Notification Service Client - - -#ifndef BLE_ANCS_C_ENABLED -#define BLE_ANCS_C_ENABLED 0 -#endif - -// BLE_ANS_C_ENABLED - ble_ans_c - Alert Notification Service Client - - -#ifndef BLE_ANS_C_ENABLED -#define BLE_ANS_C_ENABLED 0 -#endif - -// BLE_BAS_C_ENABLED - ble_bas_c - Battery Service Client - - -#ifndef BLE_BAS_C_ENABLED -#define BLE_BAS_C_ENABLED 0 -#endif - -// BLE_BAS_ENABLED - ble_bas - Battery Service -//========================================================== -#ifndef BLE_BAS_ENABLED -#define BLE_BAS_ENABLED 0 -#endif -// BLE_BAS_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef BLE_BAS_CONFIG_LOG_ENABLED -#define BLE_BAS_CONFIG_LOG_ENABLED 0 -#endif -// BLE_BAS_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef BLE_BAS_CONFIG_LOG_LEVEL -#define BLE_BAS_CONFIG_LOG_LEVEL 3 -#endif - -// BLE_BAS_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef BLE_BAS_CONFIG_INFO_COLOR -#define BLE_BAS_CONFIG_INFO_COLOR 0 -#endif - -// BLE_BAS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef BLE_BAS_CONFIG_DEBUG_COLOR -#define BLE_BAS_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// BLE_CSCS_ENABLED - ble_cscs - Cycling Speed and Cadence Service - - -#ifndef BLE_CSCS_ENABLED -#define BLE_CSCS_ENABLED 0 -#endif - -// BLE_CTS_C_ENABLED - ble_cts_c - Current Time Service Client - - -#ifndef BLE_CTS_C_ENABLED -#define BLE_CTS_C_ENABLED 0 -#endif - -// BLE_DIS_ENABLED - ble_dis - Device Information Service - - -#ifndef BLE_DIS_ENABLED -#define BLE_DIS_ENABLED 0 -#endif - -// BLE_GLS_ENABLED - ble_gls - Glucose Service - - -#ifndef BLE_GLS_ENABLED -#define BLE_GLS_ENABLED 0 -#endif - -// BLE_HIDS_ENABLED - ble_hids - Human Interface Device Service - - -#ifndef BLE_HIDS_ENABLED -#define BLE_HIDS_ENABLED 0 -#endif - -// BLE_HRS_C_ENABLED - ble_hrs_c - Heart Rate Service Client - - -#ifndef BLE_HRS_C_ENABLED -#define BLE_HRS_C_ENABLED 0 -#endif - -// BLE_HRS_ENABLED - ble_hrs - Heart Rate Service - - -#ifndef BLE_HRS_ENABLED -#define BLE_HRS_ENABLED 0 -#endif - -// BLE_HTS_ENABLED - ble_hts - Health Thermometer Service - - -#ifndef BLE_HTS_ENABLED -#define BLE_HTS_ENABLED 0 -#endif - -// BLE_IAS_C_ENABLED - ble_ias_c - Immediate Alert Service Client - - -#ifndef BLE_IAS_C_ENABLED -#define BLE_IAS_C_ENABLED 0 -#endif - -// BLE_IAS_ENABLED - ble_ias - Immediate Alert Service -//========================================================== -#ifndef BLE_IAS_ENABLED -#define BLE_IAS_ENABLED 0 -#endif -// BLE_IAS_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef BLE_IAS_CONFIG_LOG_ENABLED -#define BLE_IAS_CONFIG_LOG_ENABLED 0 -#endif -// BLE_IAS_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef BLE_IAS_CONFIG_LOG_LEVEL -#define BLE_IAS_CONFIG_LOG_LEVEL 3 -#endif - -// BLE_IAS_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef BLE_IAS_CONFIG_INFO_COLOR -#define BLE_IAS_CONFIG_INFO_COLOR 0 -#endif - -// BLE_IAS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef BLE_IAS_CONFIG_DEBUG_COLOR -#define BLE_IAS_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// BLE_LBS_C_ENABLED - ble_lbs_c - Nordic LED Button Service Client - - -#ifndef BLE_LBS_C_ENABLED -#define BLE_LBS_C_ENABLED 0 -#endif - -// BLE_LBS_ENABLED - ble_lbs - LED Button Service - - -#ifndef BLE_LBS_ENABLED -#define BLE_LBS_ENABLED 0 -#endif - -// BLE_LLS_ENABLED - ble_lls - Link Loss Service - - -#ifndef BLE_LLS_ENABLED -#define BLE_LLS_ENABLED 0 -#endif - -// BLE_NUS_C_ENABLED - ble_nus_c - Nordic UART Central Service - - -#ifndef BLE_NUS_C_ENABLED -#define BLE_NUS_C_ENABLED 0 -#endif - -// BLE_NUS_ENABLED - ble_nus - Nordic UART Service -//========================================================== -#ifndef BLE_NUS_ENABLED -#define BLE_NUS_ENABLED 0 -#endif -// BLE_NUS_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef BLE_NUS_CONFIG_LOG_ENABLED -#define BLE_NUS_CONFIG_LOG_ENABLED 0 -#endif -// BLE_NUS_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef BLE_NUS_CONFIG_LOG_LEVEL -#define BLE_NUS_CONFIG_LOG_LEVEL 3 -#endif - -// BLE_NUS_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef BLE_NUS_CONFIG_INFO_COLOR -#define BLE_NUS_CONFIG_INFO_COLOR 0 -#endif - -// BLE_NUS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef BLE_NUS_CONFIG_DEBUG_COLOR -#define BLE_NUS_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// BLE_RSCS_C_ENABLED - ble_rscs_c - Running Speed and Cadence Client - - -#ifndef BLE_RSCS_C_ENABLED -#define BLE_RSCS_C_ENABLED 0 -#endif - -// BLE_RSCS_ENABLED - ble_rscs - Running Speed and Cadence Service - - -#ifndef BLE_RSCS_ENABLED -#define BLE_RSCS_ENABLED 0 -#endif - -// BLE_TPS_ENABLED - ble_tps - TX Power Service - - -#ifndef BLE_TPS_ENABLED -#define BLE_TPS_ENABLED 0 -#endif - -// -//========================================================== - -// nRF_Core - -//========================================================== -// NRF_MPU_ENABLED - nrf_mpu - Module for MPU -//========================================================== -#ifndef NRF_MPU_ENABLED -#define NRF_MPU_ENABLED 0 -#endif -// NRF_MPU_CLI_CMDS - Enable CLI commands specific to the module - - -#ifndef NRF_MPU_CLI_CMDS -#define NRF_MPU_CLI_CMDS 0 -#endif - -// - -// NRF_STACK_GUARD_ENABLED - nrf_stack_guard - Module for Protecting Stack -//========================================================== -#ifndef NRF_STACK_GUARD_ENABLED -#define NRF_STACK_GUARD_ENABLED 0 -#endif -// NRF_STACK_GUARD_CONFIG_SIZE - Size of stack guard - -// <5=> 32 bytes -// <6=> 64 bytes -// <7=> 128 bytes -// <8=> 256 bytes -// <9=> 512 bytes -// <10=> 1024 bytes -// <11=> 2048 bytes -// <12=> 4096 bytes - -#ifndef NRF_STACK_GUARD_CONFIG_SIZE -#define NRF_STACK_GUARD_CONFIG_SIZE 7 -#endif - -// - -// -//========================================================== - -// nRF_Crypto - -//========================================================== -// NRF_CRYPTO_ENABLED - nrf_crypto - Cryptography library -//========================================================== -#ifndef NRF_CRYPTO_ENABLED -#define NRF_CRYPTO_ENABLED 1 -#endif -// NRF_CRYPTO_ALLOCATOR - Memory allocator - - -// Choose memory allocator used by nrf_crypto. Default is alloca if possible or nrf_malloc otherwise. If 'User macros' are selected then user have to create 'nrf_crypto_allocator.h' file containing NRF_CRYPTO_ALLOC, NRF_CRYPTO_FREE and NRF_CRYPTO_ALLOC_ON_STACK -// <0=> Default -// <1=> User macros -// <2=> On stack (alloca) -// <3=> C dynamic memory (malloc) -// <4=> SDK Memory Manager (nrf_malloc) - -#ifndef NRF_CRYPTO_ALLOCATOR -#define NRF_CRYPTO_ALLOCATOR 0 -#endif - -// NRF_CRYPTO_BACKEND_CC310_BL_ENABLED - Enable the ARM Cryptocell CC310 reduced backend. - -// The CC310 hardware-accelerated cryptography backend with reduced functionality and footprint (only available on nRF52840). -//========================================================== -#ifndef NRF_CRYPTO_BACKEND_CC310_BL_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_BL_ENABLED 0 -#endif -// NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED - Enable the secp224r1 elliptic curve support using CC310_BL. - - -#ifndef NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED 0 -#endif - -// NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED - Enable the secp256r1 elliptic curve support using CC310_BL. - - -#ifndef NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_CC310_BL_HASH_SHA256_ENABLED - CC310_BL SHA-256 hash functionality. - - -// CC310_BL backend implementation for hardware-accelerated SHA-256. - -#ifndef NRF_CRYPTO_BACKEND_CC310_BL_HASH_SHA256_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_SHA256_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_CC310_BL_HASH_LITTLE_ENDIAN_DIGEST_ENABLED - nrf_cc310_bl hash outputs digests in little endian - - -// Makes the nRF SH hash functions output digests in little endian format. Only for use in nRF SDK DFU! - -#ifndef NRF_CRYPTO_BACKEND_CC310_BL_HASH_LITTLE_ENDIAN_DIGEST_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_LITTLE_ENDIAN_DIGEST_ENABLED 0 -#endif - -// NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED - nrf_cc310_bl buffers to RAM before running hash operation - - -// Enabling this makes hashing of addresses in FLASH range possible. Size of buffer allocated for hashing is set by NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE - -#ifndef NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED 0 -#endif - -// NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE - nrf_cc310_bl hash outputs digests in little endian -// Makes the nrf_cc310_bl hash functions output digests in little endian format. Only for use in nRF SDK DFU! - -#ifndef NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE -#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE 4096 -#endif - -// NRF_CRYPTO_BACKEND_CC310_BL_ECC_LITTLE_ENDIAN_ENABLED - Enable non-standard little endian byte order in nrf_cc310_bl ECC functions. - - -// This affects parameters for all nrf_cc310_bl ECC APIs (raw keys, signature, digest). Only for use in nRF SDK DFU! - -#ifndef NRF_CRYPTO_BACKEND_CC310_BL_ECC_LITTLE_ENDIAN_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_BL_ECC_LITTLE_ENDIAN_ENABLED 0 -#endif - -// - -// NRF_CRYPTO_BACKEND_CC310_ENABLED - Enable the ARM Cryptocell CC310 backend. - -// The CC310 hardware-accelerated cryptography backend (only available on nRF52840). -//========================================================== -#ifndef NRF_CRYPTO_BACKEND_CC310_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_ENABLED 0 -#endif -// NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED - Enable the AES CBC mode using CC310. - - -#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED - Enable the AES CTR mode using CC310. - - -#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED - Enable the AES ECB mode using CC310. - - -#ifndef NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED - Enable the AES CBC_MAC mode using CC310. - - -#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED - Enable the AES CMAC mode using CC310. - - -#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED - Enable the AES CCM mode using CC310. - - -#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED - Enable the AES CCM* mode using CC310. - - -#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED - Enable the CHACHA-POLY mode using CC310. - - -#ifndef NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED - Enable the secp160r1 elliptic curve support using CC310. - - -#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED - Enable the secp160r2 elliptic curve support using CC310. - - -#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED - Enable the secp192r1 elliptic curve support using CC310. - - -#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED - Enable the secp224r1 elliptic curve support using CC310. - - -#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED - Enable the secp256r1 elliptic curve support using CC310. - - -#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED - Enable the secp384r1 elliptic curve support using CC310. - - -#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED - Enable the secp521r1 elliptic curve support using CC310. - - -#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED - Enable the secp160k1 elliptic curve support using CC310. - - -#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED - Enable the secp192k1 elliptic curve support using CC310. - - -#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED - Enable the secp224k1 elliptic curve support using CC310. - - -#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED - Enable the secp256k1 elliptic curve support using CC310. - - -#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_CC310_HASH_SHA256_ENABLED - CC310 SHA-256 hash functionality. - - -// CC310 backend implementation for hardware-accelerated SHA-256. - -#ifndef NRF_CRYPTO_BACKEND_CC310_HASH_SHA256_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_HASH_SHA256_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_CC310_HASH_SHA512_ENABLED - CC310 SHA-512 hash functionality - - -// CC310 backend implementation for SHA-512 (in software). - -#ifndef NRF_CRYPTO_BACKEND_CC310_HASH_SHA512_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_HASH_SHA512_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_CC310_HMAC_SHA256_ENABLED - CC310 HMAC using SHA-256 - - -// CC310 backend implementation for HMAC using hardware-accelerated SHA-256. - -#ifndef NRF_CRYPTO_BACKEND_CC310_HMAC_SHA256_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_HMAC_SHA256_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_CC310_HMAC_SHA512_ENABLED - CC310 HMAC using SHA-512 - - -// CC310 backend implementation for HMAC using SHA-512 (in software). - -#ifndef NRF_CRYPTO_BACKEND_CC310_HMAC_SHA512_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_HMAC_SHA512_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED - Enable RNG support using CC310. - - -#ifndef NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED -#define NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED 1 -#endif - -// - -// NRF_CRYPTO_BACKEND_CIFRA_ENABLED - Enable the Cifra backend. -//========================================================== -#ifndef NRF_CRYPTO_BACKEND_CIFRA_ENABLED -#define NRF_CRYPTO_BACKEND_CIFRA_ENABLED 0 -#endif -// NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED - Enable the AES EAX mode using Cifra. - - -#ifndef NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED -#define NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED 1 -#endif - -// - -// NRF_CRYPTO_BACKEND_MBEDTLS_ENABLED - Enable the mbed TLS backend. -//========================================================== -#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ENABLED -#define NRF_CRYPTO_BACKEND_MBEDTLS_ENABLED 0 -#endif -// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED - Enable the AES CBC mode mbed TLS. - - -#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED -#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED - Enable the AES CTR mode using mbed TLS. - - -#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED -#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED - Enable the AES CFB mode using mbed TLS. - - -#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED -#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED - Enable the AES ECB mode using mbed TLS. - - -#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED -#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED - Enable the AES CBC MAC mode using mbed TLS. - - -#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED -#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED - Enable the AES CMAC mode using mbed TLS. - - -#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED -#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED - Enable the AES CCM mode using mbed TLS. - - -#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED -#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED - Enable the AES GCM mode using mbed TLS. - - -#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED -#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192R1_ENABLED - Enable secp192r1 (NIST 192-bit) curve - - -// Enable this setting if you need secp192r1 (NIST 192-bit) support using MBEDTLS - -#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192R1_ENABLED -#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192R1_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224R1_ENABLED - Enable secp224r1 (NIST 224-bit) curve - - -// Enable this setting if you need secp224r1 (NIST 224-bit) support using MBEDTLS - -#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224R1_ENABLED -#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224R1_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256R1_ENABLED - Enable secp256r1 (NIST 256-bit) curve - - -// Enable this setting if you need secp256r1 (NIST 256-bit) support using MBEDTLS - -#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256R1_ENABLED -#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256R1_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP384R1_ENABLED - Enable secp384r1 (NIST 384-bit) curve - - -// Enable this setting if you need secp384r1 (NIST 384-bit) support using MBEDTLS - -#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP384R1_ENABLED -#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP384R1_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP521R1_ENABLED - Enable secp521r1 (NIST 521-bit) curve - - -// Enable this setting if you need secp521r1 (NIST 521-bit) support using MBEDTLS - -#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP521R1_ENABLED -#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP521R1_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192K1_ENABLED - Enable secp192k1 (Koblitz 192-bit) curve - - -// Enable this setting if you need secp192k1 (Koblitz 192-bit) support using MBEDTLS - -#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192K1_ENABLED -#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192K1_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224K1_ENABLED - Enable secp224k1 (Koblitz 224-bit) curve - - -// Enable this setting if you need secp224k1 (Koblitz 224-bit) support using MBEDTLS - -#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224K1_ENABLED -#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224K1_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256K1_ENABLED - Enable secp256k1 (Koblitz 256-bit) curve - - -// Enable this setting if you need secp256k1 (Koblitz 256-bit) support using MBEDTLS - -#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256K1_ENABLED -#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256K1_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP256R1_ENABLED - Enable bp256r1 (Brainpool 256-bit) curve - - -// Enable this setting if you need bp256r1 (Brainpool 256-bit) support using MBEDTLS - -#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP256R1_ENABLED -#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP256R1_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP384R1_ENABLED - Enable bp384r1 (Brainpool 384-bit) curve - - -// Enable this setting if you need bp384r1 (Brainpool 384-bit) support using MBEDTLS - -#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP384R1_ENABLED -#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP384R1_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP512R1_ENABLED - Enable bp512r1 (Brainpool 512-bit) curve - - -// Enable this setting if you need bp512r1 (Brainpool 512-bit) support using MBEDTLS - -#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP512R1_ENABLED -#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP512R1_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_CURVE25519_ENABLED - Enable Curve25519 curve - - -// Enable this setting if you need Curve25519 support using MBEDTLS - -#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_CURVE25519_ENABLED -#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_CURVE25519_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA256_ENABLED - Enable mbed TLS SHA-256 hash functionality. - - -// mbed TLS backend implementation for SHA-256. - -#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA256_ENABLED -#define NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA256_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA512_ENABLED - Enable mbed TLS SHA-512 hash functionality. - - -// mbed TLS backend implementation for SHA-512. - -#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA512_ENABLED -#define NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA512_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA256_ENABLED - Enable mbed TLS HMAC using SHA-256. - - -// mbed TLS backend implementation for HMAC using SHA-256. - -#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA256_ENABLED -#define NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA256_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA512_ENABLED - Enable mbed TLS HMAC using SHA-512. - - -// mbed TLS backend implementation for HMAC using SHA-512. - -#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA512_ENABLED -#define NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA512_ENABLED 1 -#endif - -// - -// NRF_CRYPTO_BACKEND_MICRO_ECC_ENABLED - Enable the micro-ecc backend. -//========================================================== -#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ENABLED -#define NRF_CRYPTO_BACKEND_MICRO_ECC_ENABLED 0 -#endif -// NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP192R1_ENABLED - Enable secp192r1 (NIST 192-bit) curve - - -// Enable this setting if you need secp192r1 (NIST 192-bit) support using micro-ecc - -#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP192R1_ENABLED -#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP192R1_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP224R1_ENABLED - Enable secp224r1 (NIST 224-bit) curve - - -// Enable this setting if you need secp224r1 (NIST 224-bit) support using micro-ecc - -#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP224R1_ENABLED -#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP224R1_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256R1_ENABLED - Enable secp256r1 (NIST 256-bit) curve - - -// Enable this setting if you need secp256r1 (NIST 256-bit) support using micro-ecc - -#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256R1_ENABLED -#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256R1_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256K1_ENABLED - Enable secp256k1 (Koblitz 256-bit) curve - - -// Enable this setting if you need secp256k1 (Koblitz 256-bit) support using micro-ecc - -#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256K1_ENABLED -#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256K1_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_MICRO_ECC_PUBLIC_KEY_TRUSTED_ENABLED - Always trust raw public key (it will cause a security issue if the public key comes from an untrusted source) - - -// Enable this setting if you want to reduce flash usage. Only for use in nRF SDK DFU! Never enable it if the raw public key comes from an untrusted source. - -#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_PUBLIC_KEY_TRUSTED_ENABLED -#define NRF_CRYPTO_BACKEND_MICRO_ECC_PUBLIC_KEY_TRUSTED_ENABLED 0 -#endif - -// NRF_CRYPTO_BACKEND_MICRO_ECC_LITTLE_ENDIAN_ENABLED - Enable non-standard little endian byte order. - - -// This affects parameters for all ECC API (raw keys, signature, digest, shared secret). Only for use in nRF SDK DFU! - -#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_LITTLE_ENDIAN_ENABLED -#define NRF_CRYPTO_BACKEND_MICRO_ECC_LITTLE_ENDIAN_ENABLED 0 -#endif - -// - -// NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED - Enable the nRF HW RNG backend. - -// The nRF HW backend provide access to RNG peripheral in nRF5x devices. -//========================================================== -#ifndef NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED -#define NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED 0 -#endif -// NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED - Enable mbed TLS CTR-DRBG algorithm. - - -// Enable mbed TLS CTR-DRBG standardized by NIST (NIST SP 800-90A Rev. 1). The nRF HW RNG is used as an entropy source for seeding. - -#ifndef NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED -#define NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED 1 -#endif - -// - -// NRF_CRYPTO_BACKEND_NRF_SW_ENABLED - Enable the legacy nRFx sw for crypto. - -// The nRF SW cryptography backend (only used in bootloader context). -//========================================================== -#ifndef NRF_CRYPTO_BACKEND_NRF_SW_ENABLED -#define NRF_CRYPTO_BACKEND_NRF_SW_ENABLED 0 -#endif -// NRF_CRYPTO_BACKEND_NRF_SW_HASH_SHA256_ENABLED - nRF SW hash backend support for SHA-256 - - -// The nRF SW backend provide access to nRF SDK legacy hash implementation of SHA-256. - -#ifndef NRF_CRYPTO_BACKEND_NRF_SW_HASH_SHA256_ENABLED -#define NRF_CRYPTO_BACKEND_NRF_SW_HASH_SHA256_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_NRF_SW_HASH_LITTLE_ENDIAN_DIGEST_ENABLED - nRF SW hash outputs digests in little endian - - -// Makes the nRF SH hash functions output digests in little endian format. Only for use in nRF SDK DFU! - -#ifndef NRF_CRYPTO_BACKEND_NRF_SW_HASH_LITTLE_ENDIAN_DIGEST_ENABLED -#define NRF_CRYPTO_BACKEND_NRF_SW_HASH_LITTLE_ENDIAN_DIGEST_ENABLED 1 -#endif - -// - -// NRF_CRYPTO_BACKEND_OBERON_ENABLED - Enable the Oberon backend - -// The Oberon backend -//========================================================== -#ifndef NRF_CRYPTO_BACKEND_OBERON_ENABLED -#define NRF_CRYPTO_BACKEND_OBERON_ENABLED 0 -#endif -// NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED - Enable the CHACHA-POLY mode using Oberon. - - -#ifndef NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED -#define NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_OBERON_ECC_SECP256R1_ENABLED - Enable secp256r1 curve - - -// Enable this setting if you need secp256r1 curve support using Oberon library - -#ifndef NRF_CRYPTO_BACKEND_OBERON_ECC_SECP256R1_ENABLED -#define NRF_CRYPTO_BACKEND_OBERON_ECC_SECP256R1_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_OBERON_ECC_CURVE25519_ENABLED - Enable Curve25519 ECDH - - -// Enable this setting if you need Curve25519 ECDH support using Oberon library - -#ifndef NRF_CRYPTO_BACKEND_OBERON_ECC_CURVE25519_ENABLED -#define NRF_CRYPTO_BACKEND_OBERON_ECC_CURVE25519_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_OBERON_ECC_ED25519_ENABLED - Enable Ed25519 signature scheme - - -// Enable this setting if you need Ed25519 support using Oberon library - -#ifndef NRF_CRYPTO_BACKEND_OBERON_ECC_ED25519_ENABLED -#define NRF_CRYPTO_BACKEND_OBERON_ECC_ED25519_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_OBERON_HASH_SHA256_ENABLED - Oberon SHA-256 hash functionality - - -// Oberon backend implementation for SHA-256. - -#ifndef NRF_CRYPTO_BACKEND_OBERON_HASH_SHA256_ENABLED -#define NRF_CRYPTO_BACKEND_OBERON_HASH_SHA256_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_OBERON_HASH_SHA512_ENABLED - Oberon SHA-512 hash functionality - - -// Oberon backend implementation for SHA-512. - -#ifndef NRF_CRYPTO_BACKEND_OBERON_HASH_SHA512_ENABLED -#define NRF_CRYPTO_BACKEND_OBERON_HASH_SHA512_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA256_ENABLED - Oberon HMAC using SHA-256 - - -// Oberon backend implementation for HMAC using SHA-256. - -#ifndef NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA256_ENABLED -#define NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA256_ENABLED 1 -#endif - -// NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA512_ENABLED - Oberon HMAC using SHA-512 - - -// Oberon backend implementation for HMAC using SHA-512. - -#ifndef NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA512_ENABLED -#define NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA512_ENABLED 1 -#endif - -// - -// - -// -//========================================================== - -// nRF_DFU - -//========================================================== -// ble_dfu - Device Firmware Update - -//========================================================== -// BLE_DFU_ENABLED - Enable DFU Service. - - -#ifndef BLE_DFU_ENABLED -#define BLE_DFU_ENABLED 0 -#endif - -// NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS - Buttonless DFU supports bonds. - - -#ifndef NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS -#define NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS 0 -#endif - -// -//========================================================== - -// -//========================================================== - -// nRF_Drivers - -//========================================================== -// CLOCK_ENABLED - nrf_drv_clock - CLOCK peripheral driver - legacy layer -//========================================================== -#ifndef CLOCK_ENABLED -#define CLOCK_ENABLED 0 -#endif -// CLOCK_CONFIG_LF_SRC - LF Clock Source - -// <0=> RC -// <1=> XTAL -// <2=> Synth - -#ifndef CLOCK_CONFIG_LF_SRC -#define CLOCK_CONFIG_LF_SRC 1 -#endif - -// CLOCK_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef CLOCK_CONFIG_IRQ_PRIORITY -#define CLOCK_CONFIG_IRQ_PRIORITY 7 -#endif - -// - -// COMP_ENABLED - nrf_drv_comp - COMP peripheral driver - legacy layer -//========================================================== -#ifndef COMP_ENABLED -#define COMP_ENABLED 0 -#endif -// COMP_CONFIG_REF - Reference voltage - -// <0=> Internal 1.2V -// <1=> Internal 1.8V -// <2=> Internal 2.4V -// <4=> VDD -// <7=> ARef - -#ifndef COMP_CONFIG_REF -#define COMP_CONFIG_REF 1 -#endif - -// COMP_CONFIG_MAIN_MODE - Main mode - -// <0=> Single ended -// <1=> Differential - -#ifndef COMP_CONFIG_MAIN_MODE -#define COMP_CONFIG_MAIN_MODE 0 -#endif - -// COMP_CONFIG_SPEED_MODE - Speed mode - -// <0=> Low power -// <1=> Normal -// <2=> High speed - -#ifndef COMP_CONFIG_SPEED_MODE -#define COMP_CONFIG_SPEED_MODE 2 -#endif - -// COMP_CONFIG_HYST - Hystheresis - -// <0=> No -// <1=> 50mV - -#ifndef COMP_CONFIG_HYST -#define COMP_CONFIG_HYST 0 -#endif - -// COMP_CONFIG_ISOURCE - Current Source - -// <0=> Off -// <1=> 2.5 uA -// <2=> 5 uA -// <3=> 10 uA - -#ifndef COMP_CONFIG_ISOURCE -#define COMP_CONFIG_ISOURCE 0 -#endif - -// COMP_CONFIG_INPUT - Analog input - -// <0=> 0 -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef COMP_CONFIG_INPUT -#define COMP_CONFIG_INPUT 0 -#endif - -// COMP_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef COMP_CONFIG_IRQ_PRIORITY -#define COMP_CONFIG_IRQ_PRIORITY 7 -#endif - -// - -// EGU_ENABLED - nrf_drv_swi - SWI(EGU) peripheral driver - legacy layer - - -#ifndef EGU_ENABLED -#define EGU_ENABLED 0 -#endif - -// GPIOTE_ENABLED - nrf_drv_gpiote - GPIOTE peripheral driver - legacy layer -//========================================================== -#ifndef GPIOTE_ENABLED -#define GPIOTE_ENABLED 0 -#endif -// GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins -#ifndef GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS -#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 -#endif - -// GPIOTE_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef GPIOTE_CONFIG_IRQ_PRIORITY -#define GPIOTE_CONFIG_IRQ_PRIORITY 7 -#endif - -// - -// I2S_ENABLED - nrf_drv_i2s - I2S peripheral driver - legacy layer -//========================================================== -#ifndef I2S_ENABLED -#define I2S_ENABLED 0 -#endif -// I2S_CONFIG_SCK_PIN - SCK pin <0-31> - - -#ifndef I2S_CONFIG_SCK_PIN -#define I2S_CONFIG_SCK_PIN 31 -#endif - -// I2S_CONFIG_LRCK_PIN - LRCK pin <1-31> - - -#ifndef I2S_CONFIG_LRCK_PIN -#define I2S_CONFIG_LRCK_PIN 30 -#endif - -// I2S_CONFIG_MCK_PIN - MCK pin -#ifndef I2S_CONFIG_MCK_PIN -#define I2S_CONFIG_MCK_PIN 255 -#endif - -// I2S_CONFIG_SDOUT_PIN - SDOUT pin <0-31> - - -#ifndef I2S_CONFIG_SDOUT_PIN -#define I2S_CONFIG_SDOUT_PIN 29 -#endif - -// I2S_CONFIG_SDIN_PIN - SDIN pin <0-31> - - -#ifndef I2S_CONFIG_SDIN_PIN -#define I2S_CONFIG_SDIN_PIN 28 -#endif - -// I2S_CONFIG_MASTER - Mode - -// <0=> Master -// <1=> Slave - -#ifndef I2S_CONFIG_MASTER -#define I2S_CONFIG_MASTER 0 -#endif - -// I2S_CONFIG_FORMAT - Format - -// <0=> I2S -// <1=> Aligned - -#ifndef I2S_CONFIG_FORMAT -#define I2S_CONFIG_FORMAT 0 -#endif - -// I2S_CONFIG_ALIGN - Alignment - -// <0=> Left -// <1=> Right - -#ifndef I2S_CONFIG_ALIGN -#define I2S_CONFIG_ALIGN 0 -#endif - -// I2S_CONFIG_SWIDTH - Sample width (bits) - -// <0=> 8 -// <1=> 16 -// <2=> 24 - -#ifndef I2S_CONFIG_SWIDTH -#define I2S_CONFIG_SWIDTH 1 -#endif - -// I2S_CONFIG_CHANNELS - Channels - -// <0=> Stereo -// <1=> Left -// <2=> Right - -#ifndef I2S_CONFIG_CHANNELS -#define I2S_CONFIG_CHANNELS 1 -#endif - -// I2S_CONFIG_MCK_SETUP - MCK behavior - -// <0=> Disabled -// <2147483648=> 32MHz/2 -// <1342177280=> 32MHz/3 -// <1073741824=> 32MHz/4 -// <805306368=> 32MHz/5 -// <671088640=> 32MHz/6 -// <536870912=> 32MHz/8 -// <402653184=> 32MHz/10 -// <369098752=> 32MHz/11 -// <285212672=> 32MHz/15 -// <268435456=> 32MHz/16 -// <201326592=> 32MHz/21 -// <184549376=> 32MHz/23 -// <142606336=> 32MHz/30 -// <138412032=> 32MHz/31 -// <134217728=> 32MHz/32 -// <100663296=> 32MHz/42 -// <68157440=> 32MHz/63 -// <34340864=> 32MHz/125 - -#ifndef I2S_CONFIG_MCK_SETUP -#define I2S_CONFIG_MCK_SETUP 536870912 -#endif - -// I2S_CONFIG_RATIO - MCK/LRCK ratio - -// <0=> 32x -// <1=> 48x -// <2=> 64x -// <3=> 96x -// <4=> 128x -// <5=> 192x -// <6=> 256x -// <7=> 384x -// <8=> 512x - -#ifndef I2S_CONFIG_RATIO -#define I2S_CONFIG_RATIO 2000 -#endif - -// I2S_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef I2S_CONFIG_IRQ_PRIORITY -#define I2S_CONFIG_IRQ_PRIORITY 7 -#endif - -// I2S_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef I2S_CONFIG_LOG_ENABLED -#define I2S_CONFIG_LOG_ENABLED 0 -#endif -// I2S_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef I2S_CONFIG_LOG_LEVEL -#define I2S_CONFIG_LOG_LEVEL 3 -#endif - -// I2S_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef I2S_CONFIG_INFO_COLOR -#define I2S_CONFIG_INFO_COLOR 0 -#endif - -// I2S_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef I2S_CONFIG_DEBUG_COLOR -#define I2S_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// LPCOMP_ENABLED - nrf_drv_lpcomp - LPCOMP peripheral driver - legacy layer -//========================================================== -#ifndef LPCOMP_ENABLED -#define LPCOMP_ENABLED 0 -#endif -// LPCOMP_CONFIG_REFERENCE - Reference voltage - -// <0=> Supply 1/8 -// <1=> Supply 2/8 -// <2=> Supply 3/8 -// <3=> Supply 4/8 -// <4=> Supply 5/8 -// <5=> Supply 6/8 -// <6=> Supply 7/8 -// <8=> Supply 1/16 (nRF52) -// <9=> Supply 3/16 (nRF52) -// <10=> Supply 5/16 (nRF52) -// <11=> Supply 7/16 (nRF52) -// <12=> Supply 9/16 (nRF52) -// <13=> Supply 11/16 (nRF52) -// <14=> Supply 13/16 (nRF52) -// <15=> Supply 15/16 (nRF52) -// <7=> External Ref 0 -// <65543=> External Ref 1 - -#ifndef LPCOMP_CONFIG_REFERENCE -#define LPCOMP_CONFIG_REFERENCE 3 -#endif - -// LPCOMP_CONFIG_DETECTION - Detection - -// <0=> Crossing -// <1=> Up -// <2=> Down - -#ifndef LPCOMP_CONFIG_DETECTION -#define LPCOMP_CONFIG_DETECTION 2 -#endif - -// LPCOMP_CONFIG_INPUT - Analog input - -// <0=> 0 -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef LPCOMP_CONFIG_INPUT -#define LPCOMP_CONFIG_INPUT 0 -#endif - -// LPCOMP_CONFIG_HYST - Hysteresis - - -#ifndef LPCOMP_CONFIG_HYST -#define LPCOMP_CONFIG_HYST 0 -#endif - -// LPCOMP_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef LPCOMP_CONFIG_IRQ_PRIORITY -#define LPCOMP_CONFIG_IRQ_PRIORITY 7 -#endif - -// - -// NRFX_CLOCK_ENABLED - nrfx_clock - CLOCK peripheral driver -//========================================================== -#ifndef NRFX_CLOCK_ENABLED -#define NRFX_CLOCK_ENABLED 0 -#endif -// NRFX_CLOCK_CONFIG_LF_SRC - LF Clock Source - -// <0=> RC -// <1=> XTAL -// <2=> Synth - -#ifndef NRFX_CLOCK_CONFIG_LF_SRC -#define NRFX_CLOCK_CONFIG_LF_SRC 1 -#endif - -// NRFX_CLOCK_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_CLOCK_CONFIG_IRQ_PRIORITY -#define NRFX_CLOCK_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_CLOCK_CONFIG_LOG_ENABLED -#define NRFX_CLOCK_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_CLOCK_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_CLOCK_CONFIG_LOG_LEVEL -#define NRFX_CLOCK_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_CLOCK_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_CLOCK_CONFIG_INFO_COLOR -#define NRFX_CLOCK_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_CLOCK_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_CLOCK_CONFIG_DEBUG_COLOR -#define NRFX_CLOCK_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_COMP_ENABLED - nrfx_comp - COMP peripheral driver -//========================================================== -#ifndef NRFX_COMP_ENABLED -#define NRFX_COMP_ENABLED 0 -#endif -// NRFX_COMP_CONFIG_REF - Reference voltage - -// <0=> Internal 1.2V -// <1=> Internal 1.8V -// <2=> Internal 2.4V -// <4=> VDD -// <7=> ARef - -#ifndef NRFX_COMP_CONFIG_REF -#define NRFX_COMP_CONFIG_REF 1 -#endif - -// NRFX_COMP_CONFIG_MAIN_MODE - Main mode - -// <0=> Single ended -// <1=> Differential - -#ifndef NRFX_COMP_CONFIG_MAIN_MODE -#define NRFX_COMP_CONFIG_MAIN_MODE 0 -#endif - -// NRFX_COMP_CONFIG_SPEED_MODE - Speed mode - -// <0=> Low power -// <1=> Normal -// <2=> High speed - -#ifndef NRFX_COMP_CONFIG_SPEED_MODE -#define NRFX_COMP_CONFIG_SPEED_MODE 2 -#endif - -// NRFX_COMP_CONFIG_HYST - Hystheresis - -// <0=> No -// <1=> 50mV - -#ifndef NRFX_COMP_CONFIG_HYST -#define NRFX_COMP_CONFIG_HYST 0 -#endif - -// NRFX_COMP_CONFIG_ISOURCE - Current Source - -// <0=> Off -// <1=> 2.5 uA -// <2=> 5 uA -// <3=> 10 uA - -#ifndef NRFX_COMP_CONFIG_ISOURCE -#define NRFX_COMP_CONFIG_ISOURCE 0 -#endif - -// NRFX_COMP_CONFIG_INPUT - Analog input - -// <0=> 0 -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_COMP_CONFIG_INPUT -#define NRFX_COMP_CONFIG_INPUT 0 -#endif - -// NRFX_COMP_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_COMP_CONFIG_IRQ_PRIORITY -#define NRFX_COMP_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_COMP_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_COMP_CONFIG_LOG_ENABLED -#define NRFX_COMP_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_COMP_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_COMP_CONFIG_LOG_LEVEL -#define NRFX_COMP_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_COMP_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_COMP_CONFIG_INFO_COLOR -#define NRFX_COMP_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_COMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_COMP_CONFIG_DEBUG_COLOR -#define NRFX_COMP_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_GPIOTE_ENABLED - nrfx_gpiote - GPIOTE peripheral driver -//========================================================== -#ifndef NRFX_GPIOTE_ENABLED -#define NRFX_GPIOTE_ENABLED 0 -#endif -// NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins -#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS -#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 -#endif - -// NRFX_GPIOTE_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_GPIOTE_CONFIG_IRQ_PRIORITY -#define NRFX_GPIOTE_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED -#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_GPIOTE_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL -#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_GPIOTE_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_GPIOTE_CONFIG_INFO_COLOR -#define NRFX_GPIOTE_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_GPIOTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_GPIOTE_CONFIG_DEBUG_COLOR -#define NRFX_GPIOTE_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_I2S_ENABLED - nrfx_i2s - I2S peripheral driver -//========================================================== -#ifndef NRFX_I2S_ENABLED -#define NRFX_I2S_ENABLED 0 -#endif -// NRFX_I2S_CONFIG_SCK_PIN - SCK pin <0-31> - - -#ifndef NRFX_I2S_CONFIG_SCK_PIN -#define NRFX_I2S_CONFIG_SCK_PIN 31 -#endif - -// NRFX_I2S_CONFIG_LRCK_PIN - LRCK pin <1-31> - - -#ifndef NRFX_I2S_CONFIG_LRCK_PIN -#define NRFX_I2S_CONFIG_LRCK_PIN 30 -#endif - -// NRFX_I2S_CONFIG_MCK_PIN - MCK pin -#ifndef NRFX_I2S_CONFIG_MCK_PIN -#define NRFX_I2S_CONFIG_MCK_PIN 255 -#endif - -// NRFX_I2S_CONFIG_SDOUT_PIN - SDOUT pin <0-31> - - -#ifndef NRFX_I2S_CONFIG_SDOUT_PIN -#define NRFX_I2S_CONFIG_SDOUT_PIN 29 -#endif - -// NRFX_I2S_CONFIG_SDIN_PIN - SDIN pin <0-31> - - -#ifndef NRFX_I2S_CONFIG_SDIN_PIN -#define NRFX_I2S_CONFIG_SDIN_PIN 28 -#endif - -// NRFX_I2S_CONFIG_MASTER - Mode - -// <0=> Master -// <1=> Slave - -#ifndef NRFX_I2S_CONFIG_MASTER -#define NRFX_I2S_CONFIG_MASTER 0 -#endif - -// NRFX_I2S_CONFIG_FORMAT - Format - -// <0=> I2S -// <1=> Aligned - -#ifndef NRFX_I2S_CONFIG_FORMAT -#define NRFX_I2S_CONFIG_FORMAT 0 -#endif - -// NRFX_I2S_CONFIG_ALIGN - Alignment - -// <0=> Left -// <1=> Right - -#ifndef NRFX_I2S_CONFIG_ALIGN -#define NRFX_I2S_CONFIG_ALIGN 0 -#endif - -// NRFX_I2S_CONFIG_SWIDTH - Sample width (bits) - -// <0=> 8 -// <1=> 16 -// <2=> 24 - -#ifndef NRFX_I2S_CONFIG_SWIDTH -#define NRFX_I2S_CONFIG_SWIDTH 1 -#endif - -// NRFX_I2S_CONFIG_CHANNELS - Channels - -// <0=> Stereo -// <1=> Left -// <2=> Right - -#ifndef NRFX_I2S_CONFIG_CHANNELS -#define NRFX_I2S_CONFIG_CHANNELS 1 -#endif - -// NRFX_I2S_CONFIG_MCK_SETUP - MCK behavior - -// <0=> Disabled -// <2147483648=> 32MHz/2 -// <1342177280=> 32MHz/3 -// <1073741824=> 32MHz/4 -// <805306368=> 32MHz/5 -// <671088640=> 32MHz/6 -// <536870912=> 32MHz/8 -// <402653184=> 32MHz/10 -// <369098752=> 32MHz/11 -// <285212672=> 32MHz/15 -// <268435456=> 32MHz/16 -// <201326592=> 32MHz/21 -// <184549376=> 32MHz/23 -// <142606336=> 32MHz/30 -// <138412032=> 32MHz/31 -// <134217728=> 32MHz/32 -// <100663296=> 32MHz/42 -// <68157440=> 32MHz/63 -// <34340864=> 32MHz/125 - -#ifndef NRFX_I2S_CONFIG_MCK_SETUP -#define NRFX_I2S_CONFIG_MCK_SETUP 536870912 -#endif - -// NRFX_I2S_CONFIG_RATIO - MCK/LRCK ratio - -// <0=> 32x -// <1=> 48x -// <2=> 64x -// <3=> 96x -// <4=> 128x -// <5=> 192x -// <6=> 256x -// <7=> 384x -// <8=> 512x - -#ifndef NRFX_I2S_CONFIG_RATIO -#define NRFX_I2S_CONFIG_RATIO 2000 -#endif - -// NRFX_I2S_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_I2S_CONFIG_IRQ_PRIORITY -#define NRFX_I2S_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_I2S_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_I2S_CONFIG_LOG_ENABLED -#define NRFX_I2S_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_I2S_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_I2S_CONFIG_LOG_LEVEL -#define NRFX_I2S_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_I2S_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_I2S_CONFIG_INFO_COLOR -#define NRFX_I2S_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_I2S_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_I2S_CONFIG_DEBUG_COLOR -#define NRFX_I2S_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_LPCOMP_ENABLED - nrfx_lpcomp - LPCOMP peripheral driver -//========================================================== -#ifndef NRFX_LPCOMP_ENABLED -#define NRFX_LPCOMP_ENABLED 0 -#endif -// NRFX_LPCOMP_CONFIG_REFERENCE - Reference voltage - -// <0=> Supply 1/8 -// <1=> Supply 2/8 -// <2=> Supply 3/8 -// <3=> Supply 4/8 -// <4=> Supply 5/8 -// <5=> Supply 6/8 -// <6=> Supply 7/8 -// <8=> Supply 1/16 (nRF52) -// <9=> Supply 3/16 (nRF52) -// <10=> Supply 5/16 (nRF52) -// <11=> Supply 7/16 (nRF52) -// <12=> Supply 9/16 (nRF52) -// <13=> Supply 11/16 (nRF52) -// <14=> Supply 13/16 (nRF52) -// <15=> Supply 15/16 (nRF52) -// <7=> External Ref 0 -// <65543=> External Ref 1 - -#ifndef NRFX_LPCOMP_CONFIG_REFERENCE -#define NRFX_LPCOMP_CONFIG_REFERENCE 3 -#endif - -// NRFX_LPCOMP_CONFIG_DETECTION - Detection - -// <0=> Crossing -// <1=> Up -// <2=> Down - -#ifndef NRFX_LPCOMP_CONFIG_DETECTION -#define NRFX_LPCOMP_CONFIG_DETECTION 2 -#endif - -// NRFX_LPCOMP_CONFIG_INPUT - Analog input - -// <0=> 0 -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_LPCOMP_CONFIG_INPUT -#define NRFX_LPCOMP_CONFIG_INPUT 0 -#endif - -// NRFX_LPCOMP_CONFIG_HYST - Hysteresis - - -#ifndef NRFX_LPCOMP_CONFIG_HYST -#define NRFX_LPCOMP_CONFIG_HYST 0 -#endif - -// NRFX_LPCOMP_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_LPCOMP_CONFIG_IRQ_PRIORITY -#define NRFX_LPCOMP_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_LPCOMP_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED -#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_LPCOMP_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL -#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_LPCOMP_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_LPCOMP_CONFIG_INFO_COLOR -#define NRFX_LPCOMP_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_LPCOMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_LPCOMP_CONFIG_DEBUG_COLOR -#define NRFX_LPCOMP_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_PDM_ENABLED - nrfx_pdm - PDM peripheral driver -//========================================================== -#ifndef NRFX_PDM_ENABLED -#define NRFX_PDM_ENABLED 0 -#endif -// NRFX_PDM_CONFIG_MODE - Mode - -// <0=> Stereo -// <1=> Mono - -#ifndef NRFX_PDM_CONFIG_MODE -#define NRFX_PDM_CONFIG_MODE 1 -#endif - -// NRFX_PDM_CONFIG_EDGE - Edge - -// <0=> Left falling -// <1=> Left rising - -#ifndef NRFX_PDM_CONFIG_EDGE -#define NRFX_PDM_CONFIG_EDGE 0 -#endif - -// NRFX_PDM_CONFIG_CLOCK_FREQ - Clock frequency - -// <134217728=> 1000k -// <138412032=> 1032k (default) -// <142606336=> 1067k - -#ifndef NRFX_PDM_CONFIG_CLOCK_FREQ -#define NRFX_PDM_CONFIG_CLOCK_FREQ 138412032 -#endif - -// NRFX_PDM_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_PDM_CONFIG_IRQ_PRIORITY -#define NRFX_PDM_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_PDM_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_PDM_CONFIG_LOG_ENABLED -#define NRFX_PDM_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_PDM_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_PDM_CONFIG_LOG_LEVEL -#define NRFX_PDM_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_PDM_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_PDM_CONFIG_INFO_COLOR -#define NRFX_PDM_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_PDM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_PDM_CONFIG_DEBUG_COLOR -#define NRFX_PDM_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_POWER_ENABLED - nrfx_power - POWER peripheral driver -//========================================================== -#ifndef NRFX_POWER_ENABLED -#define NRFX_POWER_ENABLED 0 -#endif -// NRFX_POWER_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_POWER_CONFIG_IRQ_PRIORITY -#define NRFX_POWER_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_POWER_CONFIG_DEFAULT_DCDCEN - The default configuration of main DCDC regulator - - -// This settings means only that components for DCDC regulator are installed and it can be enabled. - -#ifndef NRFX_POWER_CONFIG_DEFAULT_DCDCEN -#define NRFX_POWER_CONFIG_DEFAULT_DCDCEN 0 -#endif - -// NRFX_POWER_CONFIG_DEFAULT_DCDCENHV - The default configuration of High Voltage DCDC regulator - - -// This settings means only that components for DCDC regulator are installed and it can be enabled. - -#ifndef NRFX_POWER_CONFIG_DEFAULT_DCDCENHV -#define NRFX_POWER_CONFIG_DEFAULT_DCDCENHV 0 -#endif - -// - -// NRFX_PPI_ENABLED - nrfx_ppi - PPI peripheral allocator -//========================================================== -#ifndef NRFX_PPI_ENABLED -#define NRFX_PPI_ENABLED 0 -#endif -// NRFX_PPI_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_PPI_CONFIG_LOG_ENABLED -#define NRFX_PPI_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_PPI_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_PPI_CONFIG_LOG_LEVEL -#define NRFX_PPI_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_PPI_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_PPI_CONFIG_INFO_COLOR -#define NRFX_PPI_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_PPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_PPI_CONFIG_DEBUG_COLOR -#define NRFX_PPI_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_PWM_ENABLED - nrfx_pwm - PWM peripheral driver -//========================================================== -#ifndef NRFX_PWM_ENABLED -#define NRFX_PWM_ENABLED 0 -#endif -// NRFX_PWM0_ENABLED - Enable PWM0 instance - - -#ifndef NRFX_PWM0_ENABLED -#define NRFX_PWM0_ENABLED 0 -#endif - -// NRFX_PWM1_ENABLED - Enable PWM1 instance - - -#ifndef NRFX_PWM1_ENABLED -#define NRFX_PWM1_ENABLED 0 -#endif - -// NRFX_PWM2_ENABLED - Enable PWM2 instance - - -#ifndef NRFX_PWM2_ENABLED -#define NRFX_PWM2_ENABLED 0 -#endif - -// NRFX_PWM3_ENABLED - Enable PWM3 instance - - -#ifndef NRFX_PWM3_ENABLED -#define NRFX_PWM3_ENABLED 0 -#endif - -// NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin <0-31> - - -#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN -#define NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN 31 -#endif - -// NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin <0-31> - - -#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN -#define NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN 31 -#endif - -// NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin <0-31> - - -#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN -#define NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN 31 -#endif - -// NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin <0-31> - - -#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN -#define NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN 31 -#endif - -// NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK - Base clock - -// <0=> 16 MHz -// <1=> 8 MHz -// <2=> 4 MHz -// <3=> 2 MHz -// <4=> 1 MHz -// <5=> 500 kHz -// <6=> 250 kHz -// <7=> 125 kHz - -#ifndef NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK -#define NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK 4 -#endif - -// NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE - Count mode - -// <0=> Up -// <1=> Up and Down - -#ifndef NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE -#define NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE 0 -#endif - -// NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE - Top value -#ifndef NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE -#define NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE 1000 -#endif - -// NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE - Load mode - -// <0=> Common -// <1=> Grouped -// <2=> Individual -// <3=> Waveform - -#ifndef NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE -#define NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE 0 -#endif - -// NRFX_PWM_DEFAULT_CONFIG_STEP_MODE - Step mode - -// <0=> Auto -// <1=> Triggered - -#ifndef NRFX_PWM_DEFAULT_CONFIG_STEP_MODE -#define NRFX_PWM_DEFAULT_CONFIG_STEP_MODE 0 -#endif - -// NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_PWM_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_PWM_CONFIG_LOG_ENABLED -#define NRFX_PWM_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_PWM_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_PWM_CONFIG_LOG_LEVEL -#define NRFX_PWM_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_PWM_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_PWM_CONFIG_INFO_COLOR -#define NRFX_PWM_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_PWM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_PWM_CONFIG_DEBUG_COLOR -#define NRFX_PWM_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_QDEC_ENABLED - nrfx_qdec - QDEC peripheral driver -//========================================================== -#ifndef NRFX_QDEC_ENABLED -#define NRFX_QDEC_ENABLED 0 -#endif -// NRFX_QDEC_CONFIG_REPORTPER - Report period - -// <0=> 10 Samples -// <1=> 40 Samples -// <2=> 80 Samples -// <3=> 120 Samples -// <4=> 160 Samples -// <5=> 200 Samples -// <6=> 240 Samples -// <7=> 280 Samples - -#ifndef NRFX_QDEC_CONFIG_REPORTPER -#define NRFX_QDEC_CONFIG_REPORTPER 0 -#endif - -// NRFX_QDEC_CONFIG_SAMPLEPER - Sample period - -// <0=> 128 us -// <1=> 256 us -// <2=> 512 us -// <3=> 1024 us -// <4=> 2048 us -// <5=> 4096 us -// <6=> 8192 us -// <7=> 16384 us - -#ifndef NRFX_QDEC_CONFIG_SAMPLEPER -#define NRFX_QDEC_CONFIG_SAMPLEPER 7 -#endif - -// NRFX_QDEC_CONFIG_PIO_A - A pin <0-31> - - -#ifndef NRFX_QDEC_CONFIG_PIO_A -#define NRFX_QDEC_CONFIG_PIO_A 31 -#endif - -// NRFX_QDEC_CONFIG_PIO_B - B pin <0-31> - - -#ifndef NRFX_QDEC_CONFIG_PIO_B -#define NRFX_QDEC_CONFIG_PIO_B 31 -#endif - -// NRFX_QDEC_CONFIG_PIO_LED - LED pin <0-31> - - -#ifndef NRFX_QDEC_CONFIG_PIO_LED -#define NRFX_QDEC_CONFIG_PIO_LED 31 -#endif - -// NRFX_QDEC_CONFIG_LEDPRE - LED pre -#ifndef NRFX_QDEC_CONFIG_LEDPRE -#define NRFX_QDEC_CONFIG_LEDPRE 511 -#endif - -// NRFX_QDEC_CONFIG_LEDPOL - LED polarity - -// <0=> Active low -// <1=> Active high - -#ifndef NRFX_QDEC_CONFIG_LEDPOL -#define NRFX_QDEC_CONFIG_LEDPOL 1 -#endif - -// NRFX_QDEC_CONFIG_DBFEN - Debouncing enable - - -#ifndef NRFX_QDEC_CONFIG_DBFEN -#define NRFX_QDEC_CONFIG_DBFEN 0 -#endif - -// NRFX_QDEC_CONFIG_SAMPLE_INTEN - Sample ready interrupt enable - - -#ifndef NRFX_QDEC_CONFIG_SAMPLE_INTEN -#define NRFX_QDEC_CONFIG_SAMPLE_INTEN 0 -#endif - -// NRFX_QDEC_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_QDEC_CONFIG_IRQ_PRIORITY -#define NRFX_QDEC_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_QDEC_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED -#define NRFX_QDEC_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_QDEC_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL -#define NRFX_QDEC_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_QDEC_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_QDEC_CONFIG_INFO_COLOR -#define NRFX_QDEC_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_QDEC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_QDEC_CONFIG_DEBUG_COLOR -#define NRFX_QDEC_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_QSPI_ENABLED - nrfx_qspi - QSPI peripheral driver -//========================================================== -#ifndef NRFX_QSPI_ENABLED -#define NRFX_QSPI_ENABLED 0 -#endif -// NRFX_QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns). <0-255> - - -#ifndef NRFX_QSPI_CONFIG_SCK_DELAY -#define NRFX_QSPI_CONFIG_SCK_DELAY 1 -#endif - -// NRFX_QSPI_CONFIG_XIP_OFFSET - Address offset in the external memory for Execute in Place operation. -#ifndef NRFX_QSPI_CONFIG_XIP_OFFSET -#define NRFX_QSPI_CONFIG_XIP_OFFSET 0 -#endif - -// NRFX_QSPI_CONFIG_READOC - Number of data lines and opcode used for reading. - -// <0=> FastRead -// <1=> Read2O -// <2=> Read2IO -// <3=> Read4O -// <4=> Read4IO - -#ifndef NRFX_QSPI_CONFIG_READOC -#define NRFX_QSPI_CONFIG_READOC 0 -#endif - -// NRFX_QSPI_CONFIG_WRITEOC - Number of data lines and opcode used for writing. - -// <0=> PP -// <1=> PP2O -// <2=> PP4O -// <3=> PP4IO - -#ifndef NRFX_QSPI_CONFIG_WRITEOC -#define NRFX_QSPI_CONFIG_WRITEOC 0 -#endif - -// NRFX_QSPI_CONFIG_ADDRMODE - Addressing mode. - -// <0=> 24bit -// <1=> 32bit - -#ifndef NRFX_QSPI_CONFIG_ADDRMODE -#define NRFX_QSPI_CONFIG_ADDRMODE 0 -#endif - -// NRFX_QSPI_CONFIG_MODE - SPI mode. - -// <0=> Mode 0 -// <1=> Mode 1 - -#ifndef NRFX_QSPI_CONFIG_MODE -#define NRFX_QSPI_CONFIG_MODE 0 -#endif - -// NRFX_QSPI_CONFIG_FREQUENCY - Frequency divider. - -// <0=> 32MHz/1 -// <1=> 32MHz/2 -// <2=> 32MHz/3 -// <3=> 32MHz/4 -// <4=> 32MHz/5 -// <5=> 32MHz/6 -// <6=> 32MHz/7 -// <7=> 32MHz/8 -// <8=> 32MHz/9 -// <9=> 32MHz/10 -// <10=> 32MHz/11 -// <11=> 32MHz/12 -// <12=> 32MHz/13 -// <13=> 32MHz/14 -// <14=> 32MHz/15 -// <15=> 32MHz/16 - -#ifndef NRFX_QSPI_CONFIG_FREQUENCY -#define NRFX_QSPI_CONFIG_FREQUENCY 15 -#endif - -// NRFX_QSPI_PIN_SCK - SCK pin value. -#ifndef NRFX_QSPI_PIN_SCK -#define NRFX_QSPI_PIN_SCK NRF_QSPI_PIN_NOT_CONNECTED -#endif - -// NRFX_QSPI_PIN_CSN - CSN pin value. -#ifndef NRFX_QSPI_PIN_CSN -#define NRFX_QSPI_PIN_CSN NRF_QSPI_PIN_NOT_CONNECTED -#endif - -// NRFX_QSPI_PIN_IO0 - IO0 pin value. -#ifndef NRFX_QSPI_PIN_IO0 -#define NRFX_QSPI_PIN_IO0 NRF_QSPI_PIN_NOT_CONNECTED -#endif - -// NRFX_QSPI_PIN_IO1 - IO1 pin value. -#ifndef NRFX_QSPI_PIN_IO1 -#define NRFX_QSPI_PIN_IO1 NRF_QSPI_PIN_NOT_CONNECTED -#endif - -// NRFX_QSPI_PIN_IO2 - IO2 pin value. -#ifndef NRFX_QSPI_PIN_IO2 -#define NRFX_QSPI_PIN_IO2 NRF_QSPI_PIN_NOT_CONNECTED -#endif - -// NRFX_QSPI_PIN_IO3 - IO3 pin value. -#ifndef NRFX_QSPI_PIN_IO3 -#define NRFX_QSPI_PIN_IO3 NRF_QSPI_PIN_NOT_CONNECTED -#endif - -// NRFX_QSPI_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_QSPI_CONFIG_IRQ_PRIORITY -#define NRFX_QSPI_CONFIG_IRQ_PRIORITY 7 -#endif - -// - -// NRFX_RNG_ENABLED - nrfx_rng - RNG peripheral driver -//========================================================== -#ifndef NRFX_RNG_ENABLED -#define NRFX_RNG_ENABLED 0 -#endif -// NRFX_RNG_CONFIG_ERROR_CORRECTION - Error correction - - -#ifndef NRFX_RNG_CONFIG_ERROR_CORRECTION -#define NRFX_RNG_CONFIG_ERROR_CORRECTION 1 -#endif - -// NRFX_RNG_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_RNG_CONFIG_IRQ_PRIORITY -#define NRFX_RNG_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_RNG_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_RNG_CONFIG_LOG_ENABLED -#define NRFX_RNG_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_RNG_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_RNG_CONFIG_LOG_LEVEL -#define NRFX_RNG_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_RNG_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_RNG_CONFIG_INFO_COLOR -#define NRFX_RNG_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_RNG_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_RNG_CONFIG_DEBUG_COLOR -#define NRFX_RNG_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_RTC_ENABLED - nrfx_rtc - RTC peripheral driver -//========================================================== -#ifndef NRFX_RTC_ENABLED -#define NRFX_RTC_ENABLED 0 -#endif -// NRFX_RTC0_ENABLED - Enable RTC0 instance - - -#ifndef NRFX_RTC0_ENABLED -#define NRFX_RTC0_ENABLED 0 -#endif - -// NRFX_RTC1_ENABLED - Enable RTC1 instance - - -#ifndef NRFX_RTC1_ENABLED -#define NRFX_RTC1_ENABLED 0 -#endif - -// NRFX_RTC2_ENABLED - Enable RTC2 instance - - -#ifndef NRFX_RTC2_ENABLED -#define NRFX_RTC2_ENABLED 0 -#endif - -// NRFX_RTC_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt -#ifndef NRFX_RTC_MAXIMUM_LATENCY_US -#define NRFX_RTC_MAXIMUM_LATENCY_US 2000 -#endif - -// NRFX_RTC_DEFAULT_CONFIG_FREQUENCY - Frequency <16-32768> - - -#ifndef NRFX_RTC_DEFAULT_CONFIG_FREQUENCY -#define NRFX_RTC_DEFAULT_CONFIG_FREQUENCY 32768 -#endif - -// NRFX_RTC_DEFAULT_CONFIG_RELIABLE - Ensures safe compare event triggering - - -#ifndef NRFX_RTC_DEFAULT_CONFIG_RELIABLE -#define NRFX_RTC_DEFAULT_CONFIG_RELIABLE 0 -#endif - -// NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_RTC_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_RTC_CONFIG_LOG_ENABLED -#define NRFX_RTC_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_RTC_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_RTC_CONFIG_LOG_LEVEL -#define NRFX_RTC_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_RTC_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_RTC_CONFIG_INFO_COLOR -#define NRFX_RTC_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_RTC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_RTC_CONFIG_DEBUG_COLOR -#define NRFX_RTC_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_SAADC_ENABLED - nrfx_saadc - SAADC peripheral driver -//========================================================== -#ifndef NRFX_SAADC_ENABLED -#define NRFX_SAADC_ENABLED 0 -#endif -// NRFX_SAADC_CONFIG_RESOLUTION - Resolution - -// <0=> 8 bit -// <1=> 10 bit -// <2=> 12 bit -// <3=> 14 bit - -#ifndef NRFX_SAADC_CONFIG_RESOLUTION -#define NRFX_SAADC_CONFIG_RESOLUTION 1 -#endif - -// NRFX_SAADC_CONFIG_OVERSAMPLE - Sample period - -// <0=> Disabled -// <1=> 2x -// <2=> 4x -// <3=> 8x -// <4=> 16x -// <5=> 32x -// <6=> 64x -// <7=> 128x -// <8=> 256x - -#ifndef NRFX_SAADC_CONFIG_OVERSAMPLE -#define NRFX_SAADC_CONFIG_OVERSAMPLE 0 -#endif - -// NRFX_SAADC_CONFIG_LP_MODE - Enabling low power mode - - -#ifndef NRFX_SAADC_CONFIG_LP_MODE -#define NRFX_SAADC_CONFIG_LP_MODE 0 -#endif - -// NRFX_SAADC_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_SAADC_CONFIG_IRQ_PRIORITY -#define NRFX_SAADC_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_SAADC_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED -#define NRFX_SAADC_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_SAADC_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL -#define NRFX_SAADC_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_SAADC_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SAADC_CONFIG_INFO_COLOR -#define NRFX_SAADC_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_SAADC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SAADC_CONFIG_DEBUG_COLOR -#define NRFX_SAADC_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_SPIM_ENABLED - nrfx_spim - SPIM peripheral driver -//========================================================== -#ifndef NRFX_SPIM_ENABLED -#define NRFX_SPIM_ENABLED 0 -#endif -// NRFX_SPIM0_ENABLED - Enable SPIM0 instance - - -#ifndef NRFX_SPIM0_ENABLED -#define NRFX_SPIM0_ENABLED 0 -#endif - -// NRFX_SPIM1_ENABLED - Enable SPIM1 instance - - -#ifndef NRFX_SPIM1_ENABLED -#define NRFX_SPIM1_ENABLED 0 -#endif - -// NRFX_SPIM2_ENABLED - Enable SPIM2 instance - - -#ifndef NRFX_SPIM2_ENABLED -#define NRFX_SPIM2_ENABLED 0 -#endif - -// NRFX_SPIM3_ENABLED - Enable SPIM3 instance - - -#ifndef NRFX_SPIM3_ENABLED -#define NRFX_SPIM3_ENABLED 0 -#endif - -// NRFX_SPIM_EXTENDED_ENABLED - Enable extended SPIM features - - -#ifndef NRFX_SPIM_EXTENDED_ENABLED -#define NRFX_SPIM_EXTENDED_ENABLED 0 -#endif - -// NRFX_SPIM_MISO_PULL_CFG - MISO pin pull configuration. - -// <0=> NRF_GPIO_PIN_NOPULL -// <1=> NRF_GPIO_PIN_PULLDOWN -// <3=> NRF_GPIO_PIN_PULLUP - -#ifndef NRFX_SPIM_MISO_PULL_CFG -#define NRFX_SPIM_MISO_PULL_CFG 1 -#endif - -// NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_SPIM_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED -#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_SPIM_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL -#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_SPIM_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SPIM_CONFIG_INFO_COLOR -#define NRFX_SPIM_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_SPIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SPIM_CONFIG_DEBUG_COLOR -#define NRFX_SPIM_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver -//========================================================== -#ifndef NRFX_SPIS_ENABLED -#define NRFX_SPIS_ENABLED 0 -#endif -// NRFX_SPIS0_ENABLED - Enable SPIS0 instance - - -#ifndef NRFX_SPIS0_ENABLED -#define NRFX_SPIS0_ENABLED 0 -#endif - -// NRFX_SPIS1_ENABLED - Enable SPIS1 instance - - -#ifndef NRFX_SPIS1_ENABLED -#define NRFX_SPIS1_ENABLED 0 -#endif - -// NRFX_SPIS2_ENABLED - Enable SPIS2 instance - - -#ifndef NRFX_SPIS2_ENABLED -#define NRFX_SPIS2_ENABLED 0 -#endif - -// NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_SPIS_DEFAULT_DEF - SPIS default DEF character <0-255> - - -#ifndef NRFX_SPIS_DEFAULT_DEF -#define NRFX_SPIS_DEFAULT_DEF 255 -#endif - -// NRFX_SPIS_DEFAULT_ORC - SPIS default ORC character <0-255> - - -#ifndef NRFX_SPIS_DEFAULT_ORC -#define NRFX_SPIS_DEFAULT_ORC 255 -#endif - -// NRFX_SPIS_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED -#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_SPIS_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL -#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_SPIS_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SPIS_CONFIG_INFO_COLOR -#define NRFX_SPIS_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_SPIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SPIS_CONFIG_DEBUG_COLOR -#define NRFX_SPIS_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_SPI_ENABLED - nrfx_spi - SPI peripheral driver -//========================================================== -#ifndef NRFX_SPI_ENABLED -#define NRFX_SPI_ENABLED 0 -#endif -// NRFX_SPI0_ENABLED - Enable SPI0 instance - - -#ifndef NRFX_SPI0_ENABLED -#define NRFX_SPI0_ENABLED 0 -#endif - -// NRFX_SPI1_ENABLED - Enable SPI1 instance - - -#ifndef NRFX_SPI1_ENABLED -#define NRFX_SPI1_ENABLED 0 -#endif - -// NRFX_SPI2_ENABLED - Enable SPI2 instance - - -#ifndef NRFX_SPI2_ENABLED -#define NRFX_SPI2_ENABLED 0 -#endif - -// NRFX_SPI_MISO_PULL_CFG - MISO pin pull configuration. - -// <0=> NRF_GPIO_PIN_NOPULL -// <1=> NRF_GPIO_PIN_PULLDOWN -// <3=> NRF_GPIO_PIN_PULLUP - -#ifndef NRFX_SPI_MISO_PULL_CFG -#define NRFX_SPI_MISO_PULL_CFG 1 -#endif - -// NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_SPI_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_SPI_CONFIG_LOG_ENABLED -#define NRFX_SPI_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_SPI_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_SPI_CONFIG_LOG_LEVEL -#define NRFX_SPI_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_SPI_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SPI_CONFIG_INFO_COLOR -#define NRFX_SPI_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_SPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SPI_CONFIG_DEBUG_COLOR -#define NRFX_SPI_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_SWI_ENABLED - nrfx_swi - SWI/EGU peripheral allocator -//========================================================== -#ifndef NRFX_SWI_ENABLED -#define NRFX_SWI_ENABLED 0 -#endif -// NRFX_EGU_ENABLED - Enable EGU support - - -#ifndef NRFX_EGU_ENABLED -#define NRFX_EGU_ENABLED 0 -#endif - -// NRFX_SWI0_DISABLED - Exclude SWI0 from being utilized by the driver - - -#ifndef NRFX_SWI0_DISABLED -#define NRFX_SWI0_DISABLED 0 -#endif - -// NRFX_SWI1_DISABLED - Exclude SWI1 from being utilized by the driver - - -#ifndef NRFX_SWI1_DISABLED -#define NRFX_SWI1_DISABLED 0 -#endif - -// NRFX_SWI2_DISABLED - Exclude SWI2 from being utilized by the driver - - -#ifndef NRFX_SWI2_DISABLED -#define NRFX_SWI2_DISABLED 0 -#endif - -// NRFX_SWI3_DISABLED - Exclude SWI3 from being utilized by the driver - - -#ifndef NRFX_SWI3_DISABLED -#define NRFX_SWI3_DISABLED 0 -#endif - -// NRFX_SWI4_DISABLED - Exclude SWI4 from being utilized by the driver - - -#ifndef NRFX_SWI4_DISABLED -#define NRFX_SWI4_DISABLED 0 -#endif - -// NRFX_SWI5_DISABLED - Exclude SWI5 from being utilized by the driver - - -#ifndef NRFX_SWI5_DISABLED -#define NRFX_SWI5_DISABLED 0 -#endif - -// NRFX_SWI_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_SWI_CONFIG_LOG_ENABLED -#define NRFX_SWI_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_SWI_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_SWI_CONFIG_LOG_LEVEL -#define NRFX_SWI_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_SWI_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SWI_CONFIG_INFO_COLOR -#define NRFX_SWI_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_SWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SWI_CONFIG_DEBUG_COLOR -#define NRFX_SWI_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_TIMER_ENABLED - nrfx_timer - TIMER periperal driver -//========================================================== -#ifndef NRFX_TIMER_ENABLED -#define NRFX_TIMER_ENABLED 0 -#endif -// NRFX_TIMER0_ENABLED - Enable TIMER0 instance - - -#ifndef NRFX_TIMER0_ENABLED -#define NRFX_TIMER0_ENABLED 0 -#endif - -// NRFX_TIMER1_ENABLED - Enable TIMER1 instance - - -#ifndef NRFX_TIMER1_ENABLED -#define NRFX_TIMER1_ENABLED 0 -#endif - -// NRFX_TIMER2_ENABLED - Enable TIMER2 instance - - -#ifndef NRFX_TIMER2_ENABLED -#define NRFX_TIMER2_ENABLED 0 -#endif - -// NRFX_TIMER3_ENABLED - Enable TIMER3 instance - - -#ifndef NRFX_TIMER3_ENABLED -#define NRFX_TIMER3_ENABLED 0 -#endif - -// NRFX_TIMER4_ENABLED - Enable TIMER4 instance - - -#ifndef NRFX_TIMER4_ENABLED -#define NRFX_TIMER4_ENABLED 0 -#endif - -// NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY - Timer frequency if in Timer mode - -// <0=> 16 MHz -// <1=> 8 MHz -// <2=> 4 MHz -// <3=> 2 MHz -// <4=> 1 MHz -// <5=> 500 kHz -// <6=> 250 kHz -// <7=> 125 kHz -// <8=> 62.5 kHz -// <9=> 31.25 kHz - -#ifndef NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY -#define NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY 0 -#endif - -// NRFX_TIMER_DEFAULT_CONFIG_MODE - Timer mode or operation - -// <0=> Timer -// <1=> Counter - -#ifndef NRFX_TIMER_DEFAULT_CONFIG_MODE -#define NRFX_TIMER_DEFAULT_CONFIG_MODE 0 -#endif - -// NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH - Timer counter bit width - -// <0=> 16 bit -// <1=> 8 bit -// <2=> 24 bit -// <3=> 32 bit - -#ifndef NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH -#define NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH 0 -#endif - -// NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_TIMER_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED -#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_TIMER_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL -#define NRFX_TIMER_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TIMER_CONFIG_INFO_COLOR -#define NRFX_TIMER_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TIMER_CONFIG_DEBUG_COLOR -#define NRFX_TIMER_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_TWIM_ENABLED - nrfx_twim - TWIM peripheral driver -//========================================================== -#ifndef NRFX_TWIM_ENABLED -#define NRFX_TWIM_ENABLED 0 -#endif -// NRFX_TWIM0_ENABLED - Enable TWIM0 instance - - -#ifndef NRFX_TWIM0_ENABLED -#define NRFX_TWIM0_ENABLED 0 -#endif - -// NRFX_TWIM1_ENABLED - Enable TWIM1 instance - - -#ifndef NRFX_TWIM1_ENABLED -#define NRFX_TWIM1_ENABLED 0 -#endif - -// NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY - Frequency - -// <26738688=> 100k -// <67108864=> 250k -// <104857600=> 400k - -#ifndef NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY -#define NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY 26738688 -#endif - -// NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit - - -#ifndef NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT -#define NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 -#endif - -// NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_TWIM_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED -#define NRFX_TWIM_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_TWIM_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL -#define NRFX_TWIM_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_TWIM_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TWIM_CONFIG_INFO_COLOR -#define NRFX_TWIM_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_TWIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TWIM_CONFIG_DEBUG_COLOR -#define NRFX_TWIM_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_TWIS_ENABLED - nrfx_twis - TWIS peripheral driver -//========================================================== -#ifndef NRFX_TWIS_ENABLED -#define NRFX_TWIS_ENABLED 0 -#endif -// NRFX_TWIS0_ENABLED - Enable TWIS0 instance - - -#ifndef NRFX_TWIS0_ENABLED -#define NRFX_TWIS0_ENABLED 0 -#endif - -// NRFX_TWIS1_ENABLED - Enable TWIS1 instance - - -#ifndef NRFX_TWIS1_ENABLED -#define NRFX_TWIS1_ENABLED 0 -#endif - -// NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once - - -// Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code. - -#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY -#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 -#endif - -// NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode - - -// Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources. - -#ifndef NRFX_TWIS_NO_SYNC_MODE -#define NRFX_TWIS_NO_SYNC_MODE 0 -#endif - -// NRFX_TWIS_DEFAULT_CONFIG_ADDR0 - Address0 -#ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR0 -#define NRFX_TWIS_DEFAULT_CONFIG_ADDR0 0 -#endif - -// NRFX_TWIS_DEFAULT_CONFIG_ADDR1 - Address1 -#ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR1 -#define NRFX_TWIS_DEFAULT_CONFIG_ADDR1 0 -#endif - -// NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL - SCL pin pull configuration - -// <0=> Disabled -// <1=> Pull down -// <3=> Pull up - -#ifndef NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL -#define NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL 0 -#endif - -// NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL - SDA pin pull configuration - -// <0=> Disabled -// <1=> Pull down -// <3=> Pull up - -#ifndef NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL -#define NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL 0 -#endif - -// NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_TWIS_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED -#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_TWIS_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL -#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_TWIS_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TWIS_CONFIG_INFO_COLOR -#define NRFX_TWIS_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_TWIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TWIS_CONFIG_DEBUG_COLOR -#define NRFX_TWIS_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_TWI_ENABLED - nrfx_twi - TWI peripheral driver -//========================================================== -#ifndef NRFX_TWI_ENABLED -#define NRFX_TWI_ENABLED 0 -#endif -// NRFX_TWI0_ENABLED - Enable TWI0 instance - - -#ifndef NRFX_TWI0_ENABLED -#define NRFX_TWI0_ENABLED 0 -#endif - -// NRFX_TWI1_ENABLED - Enable TWI1 instance - - -#ifndef NRFX_TWI1_ENABLED -#define NRFX_TWI1_ENABLED 0 -#endif - -// NRFX_TWI_DEFAULT_CONFIG_FREQUENCY - Frequency - -// <26738688=> 100k -// <67108864=> 250k -// <104857600=> 400k - -#ifndef NRFX_TWI_DEFAULT_CONFIG_FREQUENCY -#define NRFX_TWI_DEFAULT_CONFIG_FREQUENCY 26738688 -#endif - -// NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit - - -#ifndef NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT -#define NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 -#endif - -// NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_TWI_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_TWI_CONFIG_LOG_ENABLED -#define NRFX_TWI_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_TWI_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_TWI_CONFIG_LOG_LEVEL -#define NRFX_TWI_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_TWI_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TWI_CONFIG_INFO_COLOR -#define NRFX_TWI_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_TWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TWI_CONFIG_DEBUG_COLOR -#define NRFX_TWI_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_UARTE_ENABLED - nrfx_uarte - UARTE peripheral driver -//========================================================== -#ifndef NRFX_UARTE_ENABLED -#define NRFX_UARTE_ENABLED 0 -#endif -// NRFX_UARTE0_ENABLED - Enable UARTE0 instance -#ifndef NRFX_UARTE0_ENABLED -#define NRFX_UARTE0_ENABLED 0 -#endif - -// NRFX_UARTE1_ENABLED - Enable UARTE1 instance -#ifndef NRFX_UARTE1_ENABLED -#define NRFX_UARTE1_ENABLED 0 -#endif - -// NRFX_UARTE_DEFAULT_CONFIG_HWFC - Hardware Flow Control - -// <0=> Disabled -// <1=> Enabled - -#ifndef NRFX_UARTE_DEFAULT_CONFIG_HWFC -#define NRFX_UARTE_DEFAULT_CONFIG_HWFC 0 -#endif - -// NRFX_UARTE_DEFAULT_CONFIG_PARITY - Parity - -// <0=> Excluded -// <14=> Included - -#ifndef NRFX_UARTE_DEFAULT_CONFIG_PARITY -#define NRFX_UARTE_DEFAULT_CONFIG_PARITY 0 -#endif - -// NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE - Default Baudrate - -// <323584=> 1200 baud -// <643072=> 2400 baud -// <1290240=> 4800 baud -// <2576384=> 9600 baud -// <3862528=> 14400 baud -// <5152768=> 19200 baud -// <7716864=> 28800 baud -// <8388608=> 31250 baud -// <10289152=> 38400 baud -// <15007744=> 56000 baud -// <15400960=> 57600 baud -// <20615168=> 76800 baud -// <30801920=> 115200 baud -// <61865984=> 230400 baud -// <67108864=> 250000 baud -// <121634816=> 460800 baud -// <251658240=> 921600 baud -// <268435456=> 1000000 baud - -#ifndef NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE -#define NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE 30801920 -#endif - -// NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_UARTE_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED -#define NRFX_UARTE_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_UARTE_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL -#define NRFX_UARTE_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_UARTE_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_UARTE_CONFIG_INFO_COLOR -#define NRFX_UARTE_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_UARTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_UARTE_CONFIG_DEBUG_COLOR -#define NRFX_UARTE_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_UART_ENABLED - nrfx_uart - UART peripheral driver -//========================================================== -#ifndef NRFX_UART_ENABLED -#define NRFX_UART_ENABLED 0 -#endif -// NRFX_UART0_ENABLED - Enable UART0 instance -#ifndef NRFX_UART0_ENABLED -#define NRFX_UART0_ENABLED 0 -#endif - -// NRFX_UART_DEFAULT_CONFIG_HWFC - Hardware Flow Control - -// <0=> Disabled -// <1=> Enabled - -#ifndef NRFX_UART_DEFAULT_CONFIG_HWFC -#define NRFX_UART_DEFAULT_CONFIG_HWFC 0 -#endif - -// NRFX_UART_DEFAULT_CONFIG_PARITY - Parity - -// <0=> Excluded -// <14=> Included - -#ifndef NRFX_UART_DEFAULT_CONFIG_PARITY -#define NRFX_UART_DEFAULT_CONFIG_PARITY 0 -#endif - -// NRFX_UART_DEFAULT_CONFIG_BAUDRATE - Default Baudrate - -// <323584=> 1200 baud -// <643072=> 2400 baud -// <1290240=> 4800 baud -// <2576384=> 9600 baud -// <3866624=> 14400 baud -// <5152768=> 19200 baud -// <7729152=> 28800 baud -// <8388608=> 31250 baud -// <10309632=> 38400 baud -// <15007744=> 56000 baud -// <15462400=> 57600 baud -// <20615168=> 76800 baud -// <30924800=> 115200 baud -// <61845504=> 230400 baud -// <67108864=> 250000 baud -// <123695104=> 460800 baud -// <247386112=> 921600 baud -// <268435456=> 1000000 baud - -#ifndef NRFX_UART_DEFAULT_CONFIG_BAUDRATE -#define NRFX_UART_DEFAULT_CONFIG_BAUDRATE 30924800 -#endif - -// NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_UART_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_UART_CONFIG_LOG_ENABLED -#define NRFX_UART_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_UART_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_UART_CONFIG_LOG_LEVEL -#define NRFX_UART_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_UART_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_UART_CONFIG_INFO_COLOR -#define NRFX_UART_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_UART_CONFIG_DEBUG_COLOR -#define NRFX_UART_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_WDT_ENABLED - nrfx_wdt - WDT peripheral driver -//========================================================== -#ifndef NRFX_WDT_ENABLED -#define NRFX_WDT_ENABLED 0 -#endif -// NRFX_WDT_CONFIG_BEHAVIOUR - WDT behavior in CPU SLEEP or HALT mode - -// <1=> Run in SLEEP, Pause in HALT -// <8=> Pause in SLEEP, Run in HALT -// <9=> Run in SLEEP and HALT -// <0=> Pause in SLEEP and HALT - -#ifndef NRFX_WDT_CONFIG_BEHAVIOUR -#define NRFX_WDT_CONFIG_BEHAVIOUR 1 -#endif - -// NRFX_WDT_CONFIG_RELOAD_VALUE - Reload value <15-4294967295> - - -#ifndef NRFX_WDT_CONFIG_RELOAD_VALUE -#define NRFX_WDT_CONFIG_RELOAD_VALUE 2000 -#endif - -// NRFX_WDT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_WDT_CONFIG_IRQ_PRIORITY -#define NRFX_WDT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_WDT_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_WDT_CONFIG_LOG_ENABLED -#define NRFX_WDT_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_WDT_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_WDT_CONFIG_LOG_LEVEL -#define NRFX_WDT_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_WDT_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_WDT_CONFIG_INFO_COLOR -#define NRFX_WDT_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_WDT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_WDT_CONFIG_DEBUG_COLOR -#define NRFX_WDT_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// PDM_ENABLED - nrf_drv_pdm - PDM peripheral driver - legacy layer -//========================================================== -#ifndef PDM_ENABLED -#define PDM_ENABLED 0 -#endif -// PDM_CONFIG_MODE - Mode - -// <0=> Stereo -// <1=> Mono - -#ifndef PDM_CONFIG_MODE -#define PDM_CONFIG_MODE 1 -#endif - -// PDM_CONFIG_EDGE - Edge - -// <0=> Left falling -// <1=> Left rising - -#ifndef PDM_CONFIG_EDGE -#define PDM_CONFIG_EDGE 0 -#endif - -// PDM_CONFIG_CLOCK_FREQ - Clock frequency - -// <134217728=> 1000k -// <138412032=> 1032k (default) -// <142606336=> 1067k - -#ifndef PDM_CONFIG_CLOCK_FREQ -#define PDM_CONFIG_CLOCK_FREQ 138412032 -#endif - -// PDM_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef PDM_CONFIG_IRQ_PRIORITY -#define PDM_CONFIG_IRQ_PRIORITY 7 -#endif - -// - -// POWER_ENABLED - nrf_drv_power - POWER peripheral driver - legacy layer -//========================================================== -#ifndef POWER_ENABLED -#define POWER_ENABLED 0 -#endif -// POWER_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef POWER_CONFIG_IRQ_PRIORITY -#define POWER_CONFIG_IRQ_PRIORITY 7 -#endif - -// POWER_CONFIG_DEFAULT_DCDCEN - The default configuration of main DCDC regulator - - -// This settings means only that components for DCDC regulator are installed and it can be enabled. - -#ifndef POWER_CONFIG_DEFAULT_DCDCEN -#define POWER_CONFIG_DEFAULT_DCDCEN 0 -#endif - -// POWER_CONFIG_DEFAULT_DCDCENHV - The default configuration of High Voltage DCDC regulator - - -// This settings means only that components for DCDC regulator are installed and it can be enabled. - -#ifndef POWER_CONFIG_DEFAULT_DCDCENHV -#define POWER_CONFIG_DEFAULT_DCDCENHV 0 -#endif - -// - -// PPI_ENABLED - nrf_drv_ppi - PPI peripheral driver - legacy layer - - -#ifndef PPI_ENABLED -#define PPI_ENABLED 0 -#endif - -// PWM_ENABLED - nrf_drv_pwm - PWM peripheral driver - legacy layer -//========================================================== -#ifndef PWM_ENABLED -#define PWM_ENABLED 0 -#endif -// PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin <0-31> - - -#ifndef PWM_DEFAULT_CONFIG_OUT0_PIN -#define PWM_DEFAULT_CONFIG_OUT0_PIN 31 -#endif - -// PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin <0-31> - - -#ifndef PWM_DEFAULT_CONFIG_OUT1_PIN -#define PWM_DEFAULT_CONFIG_OUT1_PIN 31 -#endif - -// PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin <0-31> - - -#ifndef PWM_DEFAULT_CONFIG_OUT2_PIN -#define PWM_DEFAULT_CONFIG_OUT2_PIN 31 -#endif - -// PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin <0-31> - - -#ifndef PWM_DEFAULT_CONFIG_OUT3_PIN -#define PWM_DEFAULT_CONFIG_OUT3_PIN 31 -#endif - -// PWM_DEFAULT_CONFIG_BASE_CLOCK - Base clock - -// <0=> 16 MHz -// <1=> 8 MHz -// <2=> 4 MHz -// <3=> 2 MHz -// <4=> 1 MHz -// <5=> 500 kHz -// <6=> 250 kHz -// <7=> 125 kHz - -#ifndef PWM_DEFAULT_CONFIG_BASE_CLOCK -#define PWM_DEFAULT_CONFIG_BASE_CLOCK 4 -#endif - -// PWM_DEFAULT_CONFIG_COUNT_MODE - Count mode - -// <0=> Up -// <1=> Up and Down - -#ifndef PWM_DEFAULT_CONFIG_COUNT_MODE -#define PWM_DEFAULT_CONFIG_COUNT_MODE 0 -#endif - -// PWM_DEFAULT_CONFIG_TOP_VALUE - Top value -#ifndef PWM_DEFAULT_CONFIG_TOP_VALUE -#define PWM_DEFAULT_CONFIG_TOP_VALUE 1000 -#endif - -// PWM_DEFAULT_CONFIG_LOAD_MODE - Load mode - -// <0=> Common -// <1=> Grouped -// <2=> Individual -// <3=> Waveform - -#ifndef PWM_DEFAULT_CONFIG_LOAD_MODE -#define PWM_DEFAULT_CONFIG_LOAD_MODE 0 -#endif - -// PWM_DEFAULT_CONFIG_STEP_MODE - Step mode - -// <0=> Auto -// <1=> Triggered - -#ifndef PWM_DEFAULT_CONFIG_STEP_MODE -#define PWM_DEFAULT_CONFIG_STEP_MODE 0 -#endif - -// PWM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef PWM_DEFAULT_CONFIG_IRQ_PRIORITY -#define PWM_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// PWM0_ENABLED - Enable PWM0 instance - - -#ifndef PWM0_ENABLED -#define PWM0_ENABLED 0 -#endif - -// PWM1_ENABLED - Enable PWM1 instance - - -#ifndef PWM1_ENABLED -#define PWM1_ENABLED 0 -#endif - -// PWM2_ENABLED - Enable PWM2 instance - - -#ifndef PWM2_ENABLED -#define PWM2_ENABLED 0 -#endif - -// PWM3_ENABLED - Enable PWM3 instance - - -#ifndef PWM3_ENABLED -#define PWM3_ENABLED 0 -#endif - -// - -// QDEC_ENABLED - nrf_drv_qdec - QDEC peripheral driver - legacy layer -//========================================================== -#ifndef QDEC_ENABLED -#define QDEC_ENABLED 0 -#endif -// QDEC_CONFIG_REPORTPER - Report period - -// <0=> 10 Samples -// <1=> 40 Samples -// <2=> 80 Samples -// <3=> 120 Samples -// <4=> 160 Samples -// <5=> 200 Samples -// <6=> 240 Samples -// <7=> 280 Samples - -#ifndef QDEC_CONFIG_REPORTPER -#define QDEC_CONFIG_REPORTPER 0 -#endif - -// QDEC_CONFIG_SAMPLEPER - Sample period - -// <0=> 128 us -// <1=> 256 us -// <2=> 512 us -// <3=> 1024 us -// <4=> 2048 us -// <5=> 4096 us -// <6=> 8192 us -// <7=> 16384 us - -#ifndef QDEC_CONFIG_SAMPLEPER -#define QDEC_CONFIG_SAMPLEPER 7 -#endif - -// QDEC_CONFIG_PIO_A - A pin <0-31> - - -#ifndef QDEC_CONFIG_PIO_A -#define QDEC_CONFIG_PIO_A 31 -#endif - -// QDEC_CONFIG_PIO_B - B pin <0-31> - - -#ifndef QDEC_CONFIG_PIO_B -#define QDEC_CONFIG_PIO_B 31 -#endif - -// QDEC_CONFIG_PIO_LED - LED pin <0-31> - - -#ifndef QDEC_CONFIG_PIO_LED -#define QDEC_CONFIG_PIO_LED 31 -#endif - -// QDEC_CONFIG_LEDPRE - LED pre -#ifndef QDEC_CONFIG_LEDPRE -#define QDEC_CONFIG_LEDPRE 511 -#endif - -// QDEC_CONFIG_LEDPOL - LED polarity - -// <0=> Active low -// <1=> Active high - -#ifndef QDEC_CONFIG_LEDPOL -#define QDEC_CONFIG_LEDPOL 1 -#endif - -// QDEC_CONFIG_DBFEN - Debouncing enable - - -#ifndef QDEC_CONFIG_DBFEN -#define QDEC_CONFIG_DBFEN 0 -#endif - -// QDEC_CONFIG_SAMPLE_INTEN - Sample ready interrupt enable - - -#ifndef QDEC_CONFIG_SAMPLE_INTEN -#define QDEC_CONFIG_SAMPLE_INTEN 0 -#endif - -// QDEC_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef QDEC_CONFIG_IRQ_PRIORITY -#define QDEC_CONFIG_IRQ_PRIORITY 7 -#endif - -// - -// QSPI_ENABLED - nrf_drv_qspi - QSPI peripheral driver - legacy layer -//========================================================== -#ifndef QSPI_ENABLED -#define QSPI_ENABLED 0 -#endif -// QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns). <0-255> - - -#ifndef QSPI_CONFIG_SCK_DELAY -#define QSPI_CONFIG_SCK_DELAY 1 -#endif - -// QSPI_CONFIG_XIP_OFFSET - Address offset in the external memory for Execute in Place operation. -#ifndef QSPI_CONFIG_XIP_OFFSET -#define QSPI_CONFIG_XIP_OFFSET 0 -#endif - -// QSPI_CONFIG_READOC - Number of data lines and opcode used for reading. - -// <0=> FastRead -// <1=> Read2O -// <2=> Read2IO -// <3=> Read4O -// <4=> Read4IO - -#ifndef QSPI_CONFIG_READOC -#define QSPI_CONFIG_READOC 0 -#endif - -// QSPI_CONFIG_WRITEOC - Number of data lines and opcode used for writing. - -// <0=> PP -// <1=> PP2O -// <2=> PP4O -// <3=> PP4IO - -#ifndef QSPI_CONFIG_WRITEOC -#define QSPI_CONFIG_WRITEOC 0 -#endif - -// QSPI_CONFIG_ADDRMODE - Addressing mode. - -// <0=> 24bit -// <1=> 32bit - -#ifndef QSPI_CONFIG_ADDRMODE -#define QSPI_CONFIG_ADDRMODE 0 -#endif - -// QSPI_CONFIG_MODE - SPI mode. - -// <0=> Mode 0 -// <1=> Mode 1 - -#ifndef QSPI_CONFIG_MODE -#define QSPI_CONFIG_MODE 0 -#endif - -// QSPI_CONFIG_FREQUENCY - Frequency divider. - -// <0=> 32MHz/1 -// <1=> 32MHz/2 -// <2=> 32MHz/3 -// <3=> 32MHz/4 -// <4=> 32MHz/5 -// <5=> 32MHz/6 -// <6=> 32MHz/7 -// <7=> 32MHz/8 -// <8=> 32MHz/9 -// <9=> 32MHz/10 -// <10=> 32MHz/11 -// <11=> 32MHz/12 -// <12=> 32MHz/13 -// <13=> 32MHz/14 -// <14=> 32MHz/15 -// <15=> 32MHz/16 - -#ifndef QSPI_CONFIG_FREQUENCY -#define QSPI_CONFIG_FREQUENCY 15 -#endif - -// QSPI_PIN_SCK - SCK pin value. -#ifndef QSPI_PIN_SCK -#define QSPI_PIN_SCK NRF_QSPI_PIN_NOT_CONNECTED -#endif - -// QSPI_PIN_CSN - CSN pin value. -#ifndef QSPI_PIN_CSN -#define QSPI_PIN_CSN NRF_QSPI_PIN_NOT_CONNECTED -#endif - -// QSPI_PIN_IO0 - IO0 pin value. -#ifndef QSPI_PIN_IO0 -#define QSPI_PIN_IO0 NRF_QSPI_PIN_NOT_CONNECTED -#endif - -// QSPI_PIN_IO1 - IO1 pin value. -#ifndef QSPI_PIN_IO1 -#define QSPI_PIN_IO1 NRF_QSPI_PIN_NOT_CONNECTED -#endif - -// QSPI_PIN_IO2 - IO2 pin value. -#ifndef QSPI_PIN_IO2 -#define QSPI_PIN_IO2 NRF_QSPI_PIN_NOT_CONNECTED -#endif - -// QSPI_PIN_IO3 - IO3 pin value. -#ifndef QSPI_PIN_IO3 -#define QSPI_PIN_IO3 NRF_QSPI_PIN_NOT_CONNECTED -#endif - -// QSPI_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef QSPI_CONFIG_IRQ_PRIORITY -#define QSPI_CONFIG_IRQ_PRIORITY 7 -#endif - -// - -// RNG_ENABLED - nrf_drv_rng - RNG peripheral driver - legacy layer -//========================================================== -#ifndef RNG_ENABLED -#define RNG_ENABLED 0 -#endif -// RNG_CONFIG_ERROR_CORRECTION - Error correction - - -#ifndef RNG_CONFIG_ERROR_CORRECTION -#define RNG_CONFIG_ERROR_CORRECTION 1 -#endif - -// RNG_CONFIG_POOL_SIZE - Pool size -#ifndef RNG_CONFIG_POOL_SIZE -#define RNG_CONFIG_POOL_SIZE 64 -#endif - -// RNG_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef RNG_CONFIG_IRQ_PRIORITY -#define RNG_CONFIG_IRQ_PRIORITY 7 -#endif - -// - -// RTC_ENABLED - nrf_drv_rtc - RTC peripheral driver - legacy layer -//========================================================== -#ifndef RTC_ENABLED -#define RTC_ENABLED 0 -#endif -// RTC_DEFAULT_CONFIG_FREQUENCY - Frequency <16-32768> - - -#ifndef RTC_DEFAULT_CONFIG_FREQUENCY -#define RTC_DEFAULT_CONFIG_FREQUENCY 32768 -#endif - -// RTC_DEFAULT_CONFIG_RELIABLE - Ensures safe compare event triggering - - -#ifndef RTC_DEFAULT_CONFIG_RELIABLE -#define RTC_DEFAULT_CONFIG_RELIABLE 0 -#endif - -// RTC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef RTC_DEFAULT_CONFIG_IRQ_PRIORITY -#define RTC_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// RTC0_ENABLED - Enable RTC0 instance - - -#ifndef RTC0_ENABLED -#define RTC0_ENABLED 0 -#endif - -// RTC1_ENABLED - Enable RTC1 instance - - -#ifndef RTC1_ENABLED -#define RTC1_ENABLED 0 -#endif - -// RTC2_ENABLED - Enable RTC2 instance - - -#ifndef RTC2_ENABLED -#define RTC2_ENABLED 0 -#endif - -// NRF_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt -#ifndef NRF_MAXIMUM_LATENCY_US -#define NRF_MAXIMUM_LATENCY_US 2000 -#endif - -// - -// SAADC_ENABLED - nrf_drv_saadc - SAADC peripheral driver - legacy layer -//========================================================== -#ifndef SAADC_ENABLED -#define SAADC_ENABLED 0 -#endif -// SAADC_CONFIG_RESOLUTION - Resolution - -// <0=> 8 bit -// <1=> 10 bit -// <2=> 12 bit -// <3=> 14 bit - -#ifndef SAADC_CONFIG_RESOLUTION -#define SAADC_CONFIG_RESOLUTION 1 -#endif - -// SAADC_CONFIG_OVERSAMPLE - Sample period - -// <0=> Disabled -// <1=> 2x -// <2=> 4x -// <3=> 8x -// <4=> 16x -// <5=> 32x -// <6=> 64x -// <7=> 128x -// <8=> 256x - -#ifndef SAADC_CONFIG_OVERSAMPLE -#define SAADC_CONFIG_OVERSAMPLE 0 -#endif - -// SAADC_CONFIG_LP_MODE - Enabling low power mode - - -#ifndef SAADC_CONFIG_LP_MODE -#define SAADC_CONFIG_LP_MODE 0 -#endif - -// SAADC_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef SAADC_CONFIG_IRQ_PRIORITY -#define SAADC_CONFIG_IRQ_PRIORITY 7 -#endif - -// - -// SPIS_ENABLED - nrf_drv_spis - SPIS peripheral driver - legacy layer -//========================================================== -#ifndef SPIS_ENABLED -#define SPIS_ENABLED 0 -#endif -// SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef SPIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// SPIS_DEFAULT_MODE - Mode - -// <0=> MODE_0 -// <1=> MODE_1 -// <2=> MODE_2 -// <3=> MODE_3 - -#ifndef SPIS_DEFAULT_MODE -#define SPIS_DEFAULT_MODE 0 -#endif - -// SPIS_DEFAULT_BIT_ORDER - SPIS default bit order - -// <0=> MSB first -// <1=> LSB first - -#ifndef SPIS_DEFAULT_BIT_ORDER -#define SPIS_DEFAULT_BIT_ORDER 0 -#endif - -// SPIS_DEFAULT_DEF - SPIS default DEF character <0-255> - - -#ifndef SPIS_DEFAULT_DEF -#define SPIS_DEFAULT_DEF 255 -#endif - -// SPIS_DEFAULT_ORC - SPIS default ORC character <0-255> - - -#ifndef SPIS_DEFAULT_ORC -#define SPIS_DEFAULT_ORC 255 -#endif - -// SPIS0_ENABLED - Enable SPIS0 instance - - -#ifndef SPIS0_ENABLED -#define SPIS0_ENABLED 0 -#endif - -// SPIS1_ENABLED - Enable SPIS1 instance - - -#ifndef SPIS1_ENABLED -#define SPIS1_ENABLED 0 -#endif - -// SPIS2_ENABLED - Enable SPIS2 instance - - -#ifndef SPIS2_ENABLED -#define SPIS2_ENABLED 0 -#endif - -// - -// SPI_ENABLED - nrf_drv_spi - SPI/SPIM peripheral driver - legacy layer -//========================================================== -#ifndef SPI_ENABLED -#define SPI_ENABLED 0 -#endif -// SPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef SPI_DEFAULT_CONFIG_IRQ_PRIORITY -#define SPI_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRF_SPI_DRV_MISO_PULLUP_CFG - MISO PIN pull-up configuration. - -// <0=> NRF_GPIO_PIN_NOPULL -// <1=> NRF_GPIO_PIN_PULLDOWN -// <3=> NRF_GPIO_PIN_PULLUP - -#ifndef NRF_SPI_DRV_MISO_PULLUP_CFG -#define NRF_SPI_DRV_MISO_PULLUP_CFG 1 -#endif - -// SPI0_ENABLED - Enable SPI0 instance -//========================================================== -#ifndef SPI0_ENABLED -#define SPI0_ENABLED 0 -#endif -// SPI0_USE_EASY_DMA - Use EasyDMA - - -#ifndef SPI0_USE_EASY_DMA -#define SPI0_USE_EASY_DMA 1 -#endif - -// - -// SPI1_ENABLED - Enable SPI1 instance -//========================================================== -#ifndef SPI1_ENABLED -#define SPI1_ENABLED 0 -#endif -// SPI1_USE_EASY_DMA - Use EasyDMA - - -#ifndef SPI1_USE_EASY_DMA -#define SPI1_USE_EASY_DMA 1 -#endif - -// - -// SPI2_ENABLED - Enable SPI2 instance -//========================================================== -#ifndef SPI2_ENABLED -#define SPI2_ENABLED 0 -#endif -// SPI2_USE_EASY_DMA - Use EasyDMA - - -#ifndef SPI2_USE_EASY_DMA -#define SPI2_USE_EASY_DMA 1 -#endif - -// - -// - -// TIMER_ENABLED - nrf_drv_timer - TIMER periperal driver - legacy layer -//========================================================== -#ifndef TIMER_ENABLED -#define TIMER_ENABLED 0 -#endif -// TIMER_DEFAULT_CONFIG_FREQUENCY - Timer frequency if in Timer mode - -// <0=> 16 MHz -// <1=> 8 MHz -// <2=> 4 MHz -// <3=> 2 MHz -// <4=> 1 MHz -// <5=> 500 kHz -// <6=> 250 kHz -// <7=> 125 kHz -// <8=> 62.5 kHz -// <9=> 31.25 kHz - -#ifndef TIMER_DEFAULT_CONFIG_FREQUENCY -#define TIMER_DEFAULT_CONFIG_FREQUENCY 0 -#endif - -// TIMER_DEFAULT_CONFIG_MODE - Timer mode or operation - -// <0=> Timer -// <1=> Counter - -#ifndef TIMER_DEFAULT_CONFIG_MODE -#define TIMER_DEFAULT_CONFIG_MODE 0 -#endif - -// TIMER_DEFAULT_CONFIG_BIT_WIDTH - Timer counter bit width - -// <0=> 16 bit -// <1=> 8 bit -// <2=> 24 bit -// <3=> 32 bit - -#ifndef TIMER_DEFAULT_CONFIG_BIT_WIDTH -#define TIMER_DEFAULT_CONFIG_BIT_WIDTH 0 -#endif - -// TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef TIMER_DEFAULT_CONFIG_IRQ_PRIORITY -#define TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// TIMER0_ENABLED - Enable TIMER0 instance - - -#ifndef TIMER0_ENABLED -#define TIMER0_ENABLED 0 -#endif - -// TIMER1_ENABLED - Enable TIMER1 instance - - -#ifndef TIMER1_ENABLED -#define TIMER1_ENABLED 0 -#endif - -// TIMER2_ENABLED - Enable TIMER2 instance - - -#ifndef TIMER2_ENABLED -#define TIMER2_ENABLED 0 -#endif - -// TIMER3_ENABLED - Enable TIMER3 instance - - -#ifndef TIMER3_ENABLED -#define TIMER3_ENABLED 0 -#endif - -// TIMER4_ENABLED - Enable TIMER4 instance - - -#ifndef TIMER4_ENABLED -#define TIMER4_ENABLED 0 -#endif - -// - -// TWIS_ENABLED - nrf_drv_twis - TWIS peripheral driver - legacy layer -//========================================================== -#ifndef TWIS_ENABLED -#define TWIS_ENABLED 0 -#endif -// TWIS0_ENABLED - Enable TWIS0 instance - - -#ifndef TWIS0_ENABLED -#define TWIS0_ENABLED 0 -#endif - -// TWIS1_ENABLED - Enable TWIS1 instance - - -#ifndef TWIS1_ENABLED -#define TWIS1_ENABLED 0 -#endif - -// TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once - - -// Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code. - -#ifndef TWIS_ASSUME_INIT_AFTER_RESET_ONLY -#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 -#endif - -// TWIS_NO_SYNC_MODE - Remove support for synchronous mode - - -// Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources. - -#ifndef TWIS_NO_SYNC_MODE -#define TWIS_NO_SYNC_MODE 0 -#endif - -// TWIS_DEFAULT_CONFIG_ADDR0 - Address0 -#ifndef TWIS_DEFAULT_CONFIG_ADDR0 -#define TWIS_DEFAULT_CONFIG_ADDR0 0 -#endif - -// TWIS_DEFAULT_CONFIG_ADDR1 - Address1 -#ifndef TWIS_DEFAULT_CONFIG_ADDR1 -#define TWIS_DEFAULT_CONFIG_ADDR1 0 -#endif - -// TWIS_DEFAULT_CONFIG_SCL_PULL - SCL pin pull configuration - -// <0=> Disabled -// <1=> Pull down -// <3=> Pull up - -#ifndef TWIS_DEFAULT_CONFIG_SCL_PULL -#define TWIS_DEFAULT_CONFIG_SCL_PULL 0 -#endif - -// TWIS_DEFAULT_CONFIG_SDA_PULL - SDA pin pull configuration - -// <0=> Disabled -// <1=> Pull down -// <3=> Pull up - -#ifndef TWIS_DEFAULT_CONFIG_SDA_PULL -#define TWIS_DEFAULT_CONFIG_SDA_PULL 0 -#endif - -// TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef TWIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// - -// TWI_ENABLED - nrf_drv_twi - TWI/TWIM peripheral driver - legacy layer -//========================================================== -#ifndef TWI_ENABLED -#define TWI_ENABLED 0 -#endif -// TWI_DEFAULT_CONFIG_FREQUENCY - Frequency - -// <26738688=> 100k -// <67108864=> 250k -// <104857600=> 400k - -#ifndef TWI_DEFAULT_CONFIG_FREQUENCY -#define TWI_DEFAULT_CONFIG_FREQUENCY 26738688 -#endif - -// TWI_DEFAULT_CONFIG_CLR_BUS_INIT - Enables bus clearing procedure during init - - -#ifndef TWI_DEFAULT_CONFIG_CLR_BUS_INIT -#define TWI_DEFAULT_CONFIG_CLR_BUS_INIT 0 -#endif - -// TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit - - -#ifndef TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT -#define TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 -#endif - -// TWI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef TWI_DEFAULT_CONFIG_IRQ_PRIORITY -#define TWI_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// TWI0_ENABLED - Enable TWI0 instance -//========================================================== -#ifndef TWI0_ENABLED -#define TWI0_ENABLED 0 -#endif -// TWI0_USE_EASY_DMA - Use EasyDMA (if present) - - -#ifndef TWI0_USE_EASY_DMA -#define TWI0_USE_EASY_DMA 0 -#endif - -// - -// TWI1_ENABLED - Enable TWI1 instance -//========================================================== -#ifndef TWI1_ENABLED -#define TWI1_ENABLED 0 -#endif -// TWI1_USE_EASY_DMA - Use EasyDMA (if present) - - -#ifndef TWI1_USE_EASY_DMA -#define TWI1_USE_EASY_DMA 0 -#endif - -// - -// - -// UART_ENABLED - nrf_drv_uart - UART/UARTE peripheral driver - legacy layer -//========================================================== -#ifndef UART_ENABLED -#define UART_ENABLED 0 -#endif -// UART_DEFAULT_CONFIG_HWFC - Hardware Flow Control - -// <0=> Disabled -// <1=> Enabled - -#ifndef UART_DEFAULT_CONFIG_HWFC -#define UART_DEFAULT_CONFIG_HWFC 0 -#endif - -// UART_DEFAULT_CONFIG_PARITY - Parity - -// <0=> Excluded -// <14=> Included - -#ifndef UART_DEFAULT_CONFIG_PARITY -#define UART_DEFAULT_CONFIG_PARITY 0 -#endif - -// UART_DEFAULT_CONFIG_BAUDRATE - Default Baudrate - -// <323584=> 1200 baud -// <643072=> 2400 baud -// <1290240=> 4800 baud -// <2576384=> 9600 baud -// <3862528=> 14400 baud -// <5152768=> 19200 baud -// <7716864=> 28800 baud -// <10289152=> 38400 baud -// <15400960=> 57600 baud -// <20615168=> 76800 baud -// <30801920=> 115200 baud -// <61865984=> 230400 baud -// <67108864=> 250000 baud -// <121634816=> 460800 baud -// <251658240=> 921600 baud -// <268435456=> 1000000 baud - -#ifndef UART_DEFAULT_CONFIG_BAUDRATE -#define UART_DEFAULT_CONFIG_BAUDRATE 30801920 -#endif - -// UART_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef UART_DEFAULT_CONFIG_IRQ_PRIORITY -#define UART_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// UART_EASY_DMA_SUPPORT - Driver supporting EasyDMA - - -#ifndef UART_EASY_DMA_SUPPORT -#define UART_EASY_DMA_SUPPORT 1 -#endif - -// UART_LEGACY_SUPPORT - Driver supporting Legacy mode - - -#ifndef UART_LEGACY_SUPPORT -#define UART_LEGACY_SUPPORT 1 -#endif - -// UART0_ENABLED - Enable UART0 instance -//========================================================== -#ifndef UART0_ENABLED -#define UART0_ENABLED 0 -#endif -// UART0_CONFIG_USE_EASY_DMA - Default setting for using EasyDMA - - -#ifndef UART0_CONFIG_USE_EASY_DMA -#define UART0_CONFIG_USE_EASY_DMA 1 -#endif - -// - -// UART1_ENABLED - Enable UART1 instance -//========================================================== -#ifndef UART1_ENABLED -#define UART1_ENABLED 0 -#endif -// - -// - -// USBD_ENABLED - nrf_drv_usbd - USB driver -//========================================================== -#ifndef USBD_ENABLED -#define USBD_ENABLED 0 -#endif -// USBD_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef USBD_CONFIG_IRQ_PRIORITY -#define USBD_CONFIG_IRQ_PRIORITY 7 -#endif - -// USBD_CONFIG_DMASCHEDULER_MODE - USBD SMA scheduler working scheme - -// <0=> Prioritized access -// <1=> Round Robin - -#ifndef USBD_CONFIG_DMASCHEDULER_MODE -#define USBD_CONFIG_DMASCHEDULER_MODE 0 -#endif - -// - -// WDT_ENABLED - nrf_drv_wdt - WDT peripheral driver - legacy layer -//========================================================== -#ifndef WDT_ENABLED -#define WDT_ENABLED 0 -#endif -// WDT_CONFIG_BEHAVIOUR - WDT behavior in CPU SLEEP or HALT mode - -// <1=> Run in SLEEP, Pause in HALT -// <8=> Pause in SLEEP, Run in HALT -// <9=> Run in SLEEP and HALT -// <0=> Pause in SLEEP and HALT - -#ifndef WDT_CONFIG_BEHAVIOUR -#define WDT_CONFIG_BEHAVIOUR 1 -#endif - -// WDT_CONFIG_RELOAD_VALUE - Reload value <15-4294967295> - - -#ifndef WDT_CONFIG_RELOAD_VALUE -#define WDT_CONFIG_RELOAD_VALUE 2000 -#endif - -// WDT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef WDT_CONFIG_IRQ_PRIORITY -#define WDT_CONFIG_IRQ_PRIORITY 7 -#endif - -// - -// -//========================================================== - -// nRF_Drivers_External - -//========================================================== -// NRF_TWI_SENSOR_ENABLED - nrf_twi_sensor - nRF TWI Sensor module - - -#ifndef NRF_TWI_SENSOR_ENABLED -#define NRF_TWI_SENSOR_ENABLED 0 -#endif - -// -//========================================================== - -// nRF_Libraries - -//========================================================== -// APP_GPIOTE_ENABLED - app_gpiote - GPIOTE events dispatcher - - -#ifndef APP_GPIOTE_ENABLED -#define APP_GPIOTE_ENABLED 0 -#endif - -// APP_PWM_ENABLED - app_pwm - PWM functionality - - -#ifndef APP_PWM_ENABLED -#define APP_PWM_ENABLED 0 -#endif - -// APP_SCHEDULER_ENABLED - app_scheduler - Events scheduler -//========================================================== -#ifndef APP_SCHEDULER_ENABLED -#define APP_SCHEDULER_ENABLED 0 -#endif -// APP_SCHEDULER_WITH_PAUSE - Enabling pause feature - - -#ifndef APP_SCHEDULER_WITH_PAUSE -#define APP_SCHEDULER_WITH_PAUSE 0 -#endif - -// APP_SCHEDULER_WITH_PROFILER - Enabling scheduler profiling - - -#ifndef APP_SCHEDULER_WITH_PROFILER -#define APP_SCHEDULER_WITH_PROFILER 0 -#endif - -// - -// APP_SDCARD_ENABLED - app_sdcard - SD/MMC card support using SPI -//========================================================== -#ifndef APP_SDCARD_ENABLED -#define APP_SDCARD_ENABLED 0 -#endif -// APP_SDCARD_SPI_INSTANCE - SPI instance used - -// <0=> 0 -// <1=> 1 -// <2=> 2 - -#ifndef APP_SDCARD_SPI_INSTANCE -#define APP_SDCARD_SPI_INSTANCE 0 -#endif - -// APP_SDCARD_FREQ_INIT - SPI frequency - -// <33554432=> 125 kHz -// <67108864=> 250 kHz -// <134217728=> 500 kHz -// <268435456=> 1 MHz -// <536870912=> 2 MHz -// <1073741824=> 4 MHz -// <2147483648=> 8 MHz - -#ifndef APP_SDCARD_FREQ_INIT -#define APP_SDCARD_FREQ_INIT 67108864 -#endif - -// APP_SDCARD_FREQ_DATA - SPI frequency - -// <33554432=> 125 kHz -// <67108864=> 250 kHz -// <134217728=> 500 kHz -// <268435456=> 1 MHz -// <536870912=> 2 MHz -// <1073741824=> 4 MHz -// <2147483648=> 8 MHz - -#ifndef APP_SDCARD_FREQ_DATA -#define APP_SDCARD_FREQ_DATA 1073741824 -#endif - -// - -// APP_TIMER_ENABLED - app_timer - Application timer functionality -//========================================================== -#ifndef APP_TIMER_ENABLED -#define APP_TIMER_ENABLED 0 -#endif -// APP_TIMER_CONFIG_RTC_FREQUENCY - Configure RTC prescaler. - -// <0=> 32768 Hz -// <1=> 16384 Hz -// <3=> 8192 Hz -// <7=> 4096 Hz -// <15=> 2048 Hz -// <31=> 1024 Hz - -#ifndef APP_TIMER_CONFIG_RTC_FREQUENCY -#define APP_TIMER_CONFIG_RTC_FREQUENCY 0 -#endif - -// APP_TIMER_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef APP_TIMER_CONFIG_IRQ_PRIORITY -#define APP_TIMER_CONFIG_IRQ_PRIORITY 7 -#endif - -// APP_TIMER_CONFIG_OP_QUEUE_SIZE - Capacity of timer requests queue. -// Size of the queue depends on how many timers are used -// in the system, how often timers are started and overall -// system latency. If queue size is too small app_timer calls -// will fail. - -#ifndef APP_TIMER_CONFIG_OP_QUEUE_SIZE -#define APP_TIMER_CONFIG_OP_QUEUE_SIZE 10 -#endif - -// APP_TIMER_CONFIG_USE_SCHEDULER - Enable scheduling app_timer events to app_scheduler - - -#ifndef APP_TIMER_CONFIG_USE_SCHEDULER -#define APP_TIMER_CONFIG_USE_SCHEDULER 0 -#endif - -// APP_TIMER_KEEPS_RTC_ACTIVE - Enable RTC always on - - -// If option is enabled RTC is kept running even if there is no active timers. -// This option can be used when app_timer is used for timestamping. - -#ifndef APP_TIMER_KEEPS_RTC_ACTIVE -#define APP_TIMER_KEEPS_RTC_ACTIVE 0 -#endif - -// App Timer Legacy configuration - Legacy configuration. - -//========================================================== -// APP_TIMER_WITH_PROFILER - Enable app_timer profiling - - -#ifndef APP_TIMER_WITH_PROFILER -#define APP_TIMER_WITH_PROFILER 0 -#endif - -// APP_TIMER_CONFIG_SWI_NUMBER - Configure SWI instance used. - - -#ifndef APP_TIMER_CONFIG_SWI_NUMBER -#define APP_TIMER_CONFIG_SWI_NUMBER 0 -#endif - -// -//========================================================== - -// - -// APP_USBD_AUDIO_ENABLED - app_usbd_audio - USB AUDIO class - - -#ifndef APP_USBD_AUDIO_ENABLED -#define APP_USBD_AUDIO_ENABLED 0 -#endif - -// APP_USBD_CDC_ACM_ENABLED - app_usbd_cdc_acm - USB CDC ACM class - - -#ifndef APP_USBD_CDC_ACM_ENABLED -#define APP_USBD_CDC_ACM_ENABLED 0 -#endif - -// APP_USBD_ENABLED - app_usbd - USB Device library -//========================================================== -#ifndef APP_USBD_ENABLED -#define APP_USBD_ENABLED 0 -#endif -// APP_USBD_VID - Vendor ID <0x0000-0xFFFF> - - -// Vendor ID ordered from USB IF: http://www.usb.org/developers/vendor/ - -#ifndef APP_USBD_VID -#define APP_USBD_VID 0 -#endif - -// APP_USBD_PID - Product ID <0x0000-0xFFFF> - - -// Selected Product ID - -#ifndef APP_USBD_PID -#define APP_USBD_PID 0 -#endif - -// APP_USBD_DEVICE_VER_MAJOR - Device version, major part <0-99> - - -// Device version, will be converted automatically to BCD notation. Use just decimal values. - -#ifndef APP_USBD_DEVICE_VER_MAJOR -#define APP_USBD_DEVICE_VER_MAJOR 1 -#endif - -// APP_USBD_DEVICE_VER_MINOR - Device version, minor part <0-99> - - -// Device version, will be converted automatically to BCD notation. Use just decimal values. - -#ifndef APP_USBD_DEVICE_VER_MINOR -#define APP_USBD_DEVICE_VER_MINOR 0 -#endif - -// APP_USBD_CONFIG_SELF_POWERED - Self powered - - -#ifndef APP_USBD_CONFIG_SELF_POWERED -#define APP_USBD_CONFIG_SELF_POWERED 1 -#endif - -// APP_USBD_CONFIG_MAX_POWER - MaxPower field in configuration descriptor in milliamps <0-500> - - -#ifndef APP_USBD_CONFIG_MAX_POWER -#define APP_USBD_CONFIG_MAX_POWER 500 -#endif - -// APP_USBD_CONFIG_POWER_EVENTS_PROCESS - Process power events - - -// Enable processing power events in USB event handler. - -#ifndef APP_USBD_CONFIG_POWER_EVENTS_PROCESS -#define APP_USBD_CONFIG_POWER_EVENTS_PROCESS 1 -#endif - -// APP_USBD_CONFIG_EVENT_QUEUE_ENABLE - Enable event queue - -// This is the default configuration when all the events are placed into internal queue. -// Disable it when external queue is used like app_scheduler or if you wish to process all events inside interrupts. -// Processing all events from the interrupt level adds requirement not to call any functions that modifies the USBD library state from the context higher than USB interrupt context. -// Functions that modify USBD state are functions for sleep, wakeup, start, stop, enable and disable. -//========================================================== -#ifndef APP_USBD_CONFIG_EVENT_QUEUE_ENABLE -#define APP_USBD_CONFIG_EVENT_QUEUE_ENABLE 1 -#endif -// APP_USBD_CONFIG_EVENT_QUEUE_SIZE - The size of event queue <16-64> - - -// The size of the queue for the events that would be processed in the main loop. - -#ifndef APP_USBD_CONFIG_EVENT_QUEUE_SIZE -#define APP_USBD_CONFIG_EVENT_QUEUE_SIZE 32 -#endif - -// APP_USBD_CONFIG_SOF_HANDLING_MODE - Change SOF events handling mode. - - -// Normal queue - SOF events are pushed normally into event queue. -// Compress queue - SOF events are counted and binded with other events or executed when queue is empty. -// This prevents queue from filling with SOF events. -// Interrupt - SOF events are processed in interrupt. -// <0=> Normal queue -// <1=> Compress queue -// <2=> Interrupt - -#ifndef APP_USBD_CONFIG_SOF_HANDLING_MODE -#define APP_USBD_CONFIG_SOF_HANDLING_MODE 1 -#endif - -// - -// APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE - Provide a function that generates timestamps for logs based on the current SOF - - -// The function app_usbd_sof_timestamp_get will be implemented if the logger is enabled. -// Use it when initializing the logger. -// SOF processing will be always enabled when this configuration parameter is active. -// Notice that this option is configured outside of APP_USBD_CONFIG_LOG_ENABLED. -// This means that it will work even if the logging in this very module is disabled. - -#ifndef APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE -#define APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE 0 -#endif - -// APP_USBD_CONFIG_LOG_ENABLED - Enable logging in the module -//========================================================== -#ifndef APP_USBD_CONFIG_LOG_ENABLED -#define APP_USBD_CONFIG_LOG_ENABLED 0 -#endif -// APP_USBD_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef APP_USBD_CONFIG_LOG_LEVEL -#define APP_USBD_CONFIG_LOG_LEVEL 3 -#endif - -// APP_USBD_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef APP_USBD_CONFIG_INFO_COLOR -#define APP_USBD_CONFIG_INFO_COLOR 0 -#endif - -// APP_USBD_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef APP_USBD_CONFIG_DEBUG_COLOR -#define APP_USBD_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// APP_USBD_HID_ENABLED - app_usbd_hid - USB HID class - - -#ifndef APP_USBD_HID_ENABLED -#define APP_USBD_HID_ENABLED 0 -#endif - -// APP_USBD_HID_GENERIC_ENABLED - app_usbd_hid_generic - USB HID generic - - -#ifndef APP_USBD_HID_GENERIC_ENABLED -#define APP_USBD_HID_GENERIC_ENABLED 0 -#endif - -// APP_USBD_HID_KBD_ENABLED - app_usbd_hid_kbd - USB HID keyboard - - -#ifndef APP_USBD_HID_KBD_ENABLED -#define APP_USBD_HID_KBD_ENABLED 0 -#endif - -// APP_USBD_HID_MOUSE_ENABLED - app_usbd_hid_mouse - USB HID mouse - - -#ifndef APP_USBD_HID_MOUSE_ENABLED -#define APP_USBD_HID_MOUSE_ENABLED 0 -#endif - -// APP_USBD_MSC_ENABLED - app_usbd_msc - USB MSC class - - -#ifndef APP_USBD_MSC_ENABLED -#define APP_USBD_MSC_ENABLED 0 -#endif - -// CRC16_ENABLED - crc16 - CRC16 calculation routines - - -#ifndef CRC16_ENABLED -#define CRC16_ENABLED 0 -#endif - -// CRC32_ENABLED - crc32 - CRC32 calculation routines - - -#ifndef CRC32_ENABLED -#define CRC32_ENABLED 0 -#endif - -// ECC_ENABLED - ecc - Elliptic Curve Cryptography Library - - -#ifndef ECC_ENABLED -#define ECC_ENABLED 0 -#endif - -// FDS_ENABLED - fds - Flash data storage module -//========================================================== -#ifndef FDS_ENABLED -#define FDS_ENABLED 0 -#endif -// Pages - Virtual page settings - -// Configure the number of virtual pages to use and their size. -//========================================================== -// FDS_VIRTUAL_PAGES - Number of virtual flash pages to use. -// One of the virtual pages is reserved by the system for garbage collection. -// Therefore, the minimum is two virtual pages: one page to store data and one page to be used by the system for garbage collection. -// The total amount of flash memory that is used by FDS amounts to @ref FDS_VIRTUAL_PAGES * @ref FDS_VIRTUAL_PAGE_SIZE * 4 bytes. - -#ifndef FDS_VIRTUAL_PAGES -#define FDS_VIRTUAL_PAGES 3 -#endif - -// FDS_VIRTUAL_PAGE_SIZE - The size of a virtual flash page. - - -// Expressed in number of 4-byte words. -// By default, a virtual page is the same size as a physical page. -// The size of a virtual page must be a multiple of the size of a physical page. -// <1024=> 1024 -// <2048=> 2048 - -#ifndef FDS_VIRTUAL_PAGE_SIZE -#define FDS_VIRTUAL_PAGE_SIZE 1024 -#endif - -// -//========================================================== - -// Backend - Backend configuration - -// Configure which nrf_fstorage backend is used by FDS to write to flash. -//========================================================== -// FDS_BACKEND - FDS flash backend. - - -// NRF_FSTORAGE_SD uses the nrf_fstorage_sd backend implementation using the SoftDevice API. Use this if you have a SoftDevice present. -// NRF_FSTORAGE_NVMC uses the nrf_fstorage_nvmc implementation. Use this setting if you don't use the SoftDevice. -// <1=> NRF_FSTORAGE_NVMC -// <2=> NRF_FSTORAGE_SD - -#ifndef FDS_BACKEND -#define FDS_BACKEND 2 -#endif - -// -//========================================================== - -// Queue - Queue settings - -//========================================================== -// FDS_OP_QUEUE_SIZE - Size of the internal queue. -// Increase this value if you frequently get synchronous FDS_ERR_NO_SPACE_IN_QUEUES errors. - -#ifndef FDS_OP_QUEUE_SIZE -#define FDS_OP_QUEUE_SIZE 4 -#endif - -// -//========================================================== - -// CRC - CRC functionality - -//========================================================== -// FDS_CRC_CHECK_ON_READ - Enable CRC checks. - -// Save a record's CRC when it is written to flash and check it when the record is opened. -// Records with an incorrect CRC can still be 'seen' by the user using FDS functions, but they cannot be opened. -// Additionally, they will not be garbage collected until they are deleted. -//========================================================== -#ifndef FDS_CRC_CHECK_ON_READ -#define FDS_CRC_CHECK_ON_READ 0 -#endif -// FDS_CRC_CHECK_ON_WRITE - Perform a CRC check on newly written records. - - -// Perform a CRC check on newly written records. -// This setting can be used to make sure that the record data was not altered while being written to flash. -// <1=> Enabled -// <0=> Disabled - -#ifndef FDS_CRC_CHECK_ON_WRITE -#define FDS_CRC_CHECK_ON_WRITE 0 -#endif - -// - -// -//========================================================== - -// Users - Number of users - -//========================================================== -// FDS_MAX_USERS - Maximum number of callbacks that can be registered. -#ifndef FDS_MAX_USERS -#define FDS_MAX_USERS 4 -#endif - -// -//========================================================== - -// - -// HARDFAULT_HANDLER_ENABLED - hardfault_default - HardFault default handler for debugging and release -//========================================================== -#ifndef HARDFAULT_HANDLER_ENABLED -#define HARDFAULT_HANDLER_ENABLED 0 -#endif -// HARDFAULT_HANDLER_GDB_PSP_BACKTRACE - Bypass the GDB problem with multiple stack pointers backtrace - - -// There is a known bug in GDB which causes it to incorrectly backtrace the code -// when multiple stack pointers are used (main and process stack pointers). -// This option enables the fix for that problem and allows to see the proper backtrace info. -// It makes it possible to trace the code to the exact point where a HardFault appeared. -// This option requires additional commands and may temporarily switch MSP stack to store data on PSP space. -// This is an optional parameter - enable it while debugging. -// Before a HardFault handler exits, the stack will be reverted to its previous value. - -#ifndef HARDFAULT_HANDLER_GDB_PSP_BACKTRACE -#define HARDFAULT_HANDLER_GDB_PSP_BACKTRACE 1 -#endif - -// - -// HCI_MEM_POOL_ENABLED - hci_mem_pool - memory pool implementation used by HCI -//========================================================== -#ifndef HCI_MEM_POOL_ENABLED -#define HCI_MEM_POOL_ENABLED 0 -#endif -// HCI_TX_BUF_SIZE - TX buffer size in bytes. -#ifndef HCI_TX_BUF_SIZE -#define HCI_TX_BUF_SIZE 600 -#endif - -// HCI_RX_BUF_SIZE - RX buffer size in bytes. -#ifndef HCI_RX_BUF_SIZE -#define HCI_RX_BUF_SIZE 600 -#endif - -// HCI_RX_BUF_QUEUE_SIZE - RX buffer queue size. -#ifndef HCI_RX_BUF_QUEUE_SIZE -#define HCI_RX_BUF_QUEUE_SIZE 4 -#endif - -// - -// HCI_SLIP_ENABLED - hci_slip - SLIP protocol implementation used by HCI -//========================================================== -#ifndef HCI_SLIP_ENABLED -#define HCI_SLIP_ENABLED 0 -#endif -// HCI_UART_BAUDRATE - Default Baudrate - -// <323584=> 1200 baud -// <643072=> 2400 baud -// <1290240=> 4800 baud -// <2576384=> 9600 baud -// <3862528=> 14400 baud -// <5152768=> 19200 baud -// <7716864=> 28800 baud -// <10289152=> 38400 baud -// <15400960=> 57600 baud -// <20615168=> 76800 baud -// <30801920=> 115200 baud -// <61865984=> 230400 baud -// <67108864=> 250000 baud -// <121634816=> 460800 baud -// <251658240=> 921600 baud -// <268435456=> 1000000 baud - -#ifndef HCI_UART_BAUDRATE -#define HCI_UART_BAUDRATE 30801920 -#endif - -// HCI_UART_FLOW_CONTROL - Hardware Flow Control - -// <0=> Disabled -// <1=> Enabled - -#ifndef HCI_UART_FLOW_CONTROL -#define HCI_UART_FLOW_CONTROL 0 -#endif - -// HCI_UART_RX_PIN - UART RX pin -#ifndef HCI_UART_RX_PIN -#define HCI_UART_RX_PIN 31 -#endif - -// HCI_UART_TX_PIN - UART TX pin -#ifndef HCI_UART_TX_PIN -#define HCI_UART_TX_PIN 31 -#endif - -// HCI_UART_RTS_PIN - UART RTS pin -#ifndef HCI_UART_RTS_PIN -#define HCI_UART_RTS_PIN 31 -#endif - -// HCI_UART_CTS_PIN - UART CTS pin -#ifndef HCI_UART_CTS_PIN -#define HCI_UART_CTS_PIN 31 -#endif - -// - -// HCI_TRANSPORT_ENABLED - hci_transport - HCI transport -//========================================================== -#ifndef HCI_TRANSPORT_ENABLED -#define HCI_TRANSPORT_ENABLED 0 -#endif -// HCI_MAX_PACKET_SIZE_IN_BITS - Maximum size of a single application packet in bits. -#ifndef HCI_MAX_PACKET_SIZE_IN_BITS -#define HCI_MAX_PACKET_SIZE_IN_BITS 8000 -#endif - -// - -// LED_SOFTBLINK_ENABLED - led_softblink - led_softblink module - - -#ifndef LED_SOFTBLINK_ENABLED -#define LED_SOFTBLINK_ENABLED 0 -#endif - -// LOW_POWER_PWM_ENABLED - low_power_pwm - low_power_pwm module - - -#ifndef LOW_POWER_PWM_ENABLED -#define LOW_POWER_PWM_ENABLED 0 -#endif - -// MEM_MANAGER_ENABLED - mem_manager - Dynamic memory allocator -//========================================================== -#ifndef MEM_MANAGER_ENABLED -#define MEM_MANAGER_ENABLED 0 -#endif -// MEMORY_MANAGER_SMALL_BLOCK_COUNT - Size of each memory blocks identified as 'small' block. <0-255> - - -#ifndef MEMORY_MANAGER_SMALL_BLOCK_COUNT -#define MEMORY_MANAGER_SMALL_BLOCK_COUNT 1 -#endif - -// MEMORY_MANAGER_SMALL_BLOCK_SIZE - Size of each memory blocks identified as 'small' block. -// Size of each memory blocks identified as 'small' block. Memory block are recommended to be word-sized. - -#ifndef MEMORY_MANAGER_SMALL_BLOCK_SIZE -#define MEMORY_MANAGER_SMALL_BLOCK_SIZE 32 -#endif - -// MEMORY_MANAGER_MEDIUM_BLOCK_COUNT - Size of each memory blocks identified as 'medium' block. <0-255> - - -#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_COUNT -#define MEMORY_MANAGER_MEDIUM_BLOCK_COUNT 0 -#endif - -// MEMORY_MANAGER_MEDIUM_BLOCK_SIZE - Size of each memory blocks identified as 'medium' block. -// Size of each memory blocks identified as 'medium' block. Memory block are recommended to be word-sized. - -#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_SIZE -#define MEMORY_MANAGER_MEDIUM_BLOCK_SIZE 256 -#endif - -// MEMORY_MANAGER_LARGE_BLOCK_COUNT - Size of each memory blocks identified as 'large' block. <0-255> - - -#ifndef MEMORY_MANAGER_LARGE_BLOCK_COUNT -#define MEMORY_MANAGER_LARGE_BLOCK_COUNT 0 -#endif - -// MEMORY_MANAGER_LARGE_BLOCK_SIZE - Size of each memory blocks identified as 'large' block. -// Size of each memory blocks identified as 'large' block. Memory block are recommended to be word-sized. - -#ifndef MEMORY_MANAGER_LARGE_BLOCK_SIZE -#define MEMORY_MANAGER_LARGE_BLOCK_SIZE 256 -#endif - -// MEMORY_MANAGER_XLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra large' block. <0-255> - - -#ifndef MEMORY_MANAGER_XLARGE_BLOCK_COUNT -#define MEMORY_MANAGER_XLARGE_BLOCK_COUNT 0 -#endif - -// MEMORY_MANAGER_XLARGE_BLOCK_SIZE - Size of each memory blocks identified as 'extra large' block. -// Size of each memory blocks identified as 'extra large' block. Memory block are recommended to be word-sized. - -#ifndef MEMORY_MANAGER_XLARGE_BLOCK_SIZE -#define MEMORY_MANAGER_XLARGE_BLOCK_SIZE 1320 -#endif - -// MEMORY_MANAGER_XXLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra large' block. <0-255> - - -#ifndef MEMORY_MANAGER_XXLARGE_BLOCK_COUNT -#define MEMORY_MANAGER_XXLARGE_BLOCK_COUNT 0 -#endif - -// MEMORY_MANAGER_XXLARGE_BLOCK_SIZE - Size of each memory blocks identified as 'extra extra large' block. -// Size of each memory blocks identified as 'extra extra large' block. Memory block are recommended to be word-sized. - -#ifndef MEMORY_MANAGER_XXLARGE_BLOCK_SIZE -#define MEMORY_MANAGER_XXLARGE_BLOCK_SIZE 3444 -#endif - -// MEMORY_MANAGER_XSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra small' block. <0-255> - - -#ifndef MEMORY_MANAGER_XSMALL_BLOCK_COUNT -#define MEMORY_MANAGER_XSMALL_BLOCK_COUNT 0 -#endif - -// MEMORY_MANAGER_XSMALL_BLOCK_SIZE - Size of each memory blocks identified as 'extra small' block. -// Size of each memory blocks identified as 'extra large' block. Memory block are recommended to be word-sized. - -#ifndef MEMORY_MANAGER_XSMALL_BLOCK_SIZE -#define MEMORY_MANAGER_XSMALL_BLOCK_SIZE 64 -#endif - -// MEMORY_MANAGER_XXSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra small' block. <0-255> - - -#ifndef MEMORY_MANAGER_XXSMALL_BLOCK_COUNT -#define MEMORY_MANAGER_XXSMALL_BLOCK_COUNT 0 -#endif - -// MEMORY_MANAGER_XXSMALL_BLOCK_SIZE - Size of each memory blocks identified as 'extra extra small' block. -// Size of each memory blocks identified as 'extra extra small' block. Memory block are recommended to be word-sized. - -#ifndef MEMORY_MANAGER_XXSMALL_BLOCK_SIZE -#define MEMORY_MANAGER_XXSMALL_BLOCK_SIZE 32 -#endif - -// MEM_MANAGER_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef MEM_MANAGER_CONFIG_LOG_ENABLED -#define MEM_MANAGER_CONFIG_LOG_ENABLED 0 -#endif -// MEM_MANAGER_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef MEM_MANAGER_CONFIG_LOG_LEVEL -#define MEM_MANAGER_CONFIG_LOG_LEVEL 3 -#endif - -// MEM_MANAGER_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef MEM_MANAGER_CONFIG_INFO_COLOR -#define MEM_MANAGER_CONFIG_INFO_COLOR 0 -#endif - -// MEM_MANAGER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef MEM_MANAGER_CONFIG_DEBUG_COLOR -#define MEM_MANAGER_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// MEM_MANAGER_DISABLE_API_PARAM_CHECK - Disable API parameter checks in the module. - - -#ifndef MEM_MANAGER_DISABLE_API_PARAM_CHECK -#define MEM_MANAGER_DISABLE_API_PARAM_CHECK 0 -#endif - -// - -// NRF_BALLOC_ENABLED - nrf_balloc - Block allocator module -//========================================================== -#ifndef NRF_BALLOC_ENABLED -#define NRF_BALLOC_ENABLED 1 -#endif -// NRF_BALLOC_CONFIG_DEBUG_ENABLED - Enables debug mode in the module. -//========================================================== -#ifndef NRF_BALLOC_CONFIG_DEBUG_ENABLED -#define NRF_BALLOC_CONFIG_DEBUG_ENABLED 0 -#endif -// NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS - Number of words used as head guard. <0-255> - - -#ifndef NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS -#define NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS 1 -#endif - -// NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS - Number of words used as tail guard. <0-255> - - -#ifndef NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS -#define NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS 1 -#endif - -// NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED - Enables basic checks in this module. - - -#ifndef NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED -#define NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED 0 -#endif - -// NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED - Enables double memory free check in this module. - - -#ifndef NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED -#define NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED 0 -#endif - -// NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED - Enables free memory corruption check in this module. - - -#ifndef NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED -#define NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED 0 -#endif - -// NRF_BALLOC_CLI_CMDS - Enable CLI commands specific to the module - - -#ifndef NRF_BALLOC_CLI_CMDS -#define NRF_BALLOC_CLI_CMDS 0 -#endif - -// - -// - -// NRF_CSENSE_ENABLED - nrf_csense - Capacitive sensor module -//========================================================== -#ifndef NRF_CSENSE_ENABLED -#define NRF_CSENSE_ENABLED 0 -#endif -// NRF_CSENSE_PAD_HYSTERESIS - Minimum value of change required to determine that a pad was touched. -#ifndef NRF_CSENSE_PAD_HYSTERESIS -#define NRF_CSENSE_PAD_HYSTERESIS 15 -#endif - -// NRF_CSENSE_PAD_DEVIATION - Minimum value measured on a pad required to take it into account while calculating the step. -#ifndef NRF_CSENSE_PAD_DEVIATION -#define NRF_CSENSE_PAD_DEVIATION 70 -#endif - -// NRF_CSENSE_MIN_PAD_VALUE - Minimum normalized value on a pad required to take its value into account. -#ifndef NRF_CSENSE_MIN_PAD_VALUE -#define NRF_CSENSE_MIN_PAD_VALUE 20 -#endif - -// NRF_CSENSE_MAX_PADS_NUMBER - Maximum number of pads used for one instance. -#ifndef NRF_CSENSE_MAX_PADS_NUMBER -#define NRF_CSENSE_MAX_PADS_NUMBER 20 -#endif - -// NRF_CSENSE_MAX_VALUE - Maximum normalized value obtained from measurement. -#ifndef NRF_CSENSE_MAX_VALUE -#define NRF_CSENSE_MAX_VALUE 1000 -#endif - -// NRF_CSENSE_OUTPUT_PIN - Output pin used by the low-level module. -// This is used when capacitive sensor does not use COMP. - -#ifndef NRF_CSENSE_OUTPUT_PIN -#define NRF_CSENSE_OUTPUT_PIN 26 -#endif - -// - -// NRF_DRV_CSENSE_ENABLED - nrf_drv_csense - Capacitive sensor low-level module -//========================================================== -#ifndef NRF_DRV_CSENSE_ENABLED -#define NRF_DRV_CSENSE_ENABLED 0 -#endif -// USE_COMP - Use the comparator to implement the capacitive sensor driver. - -// Due to Anomaly 84, COMP I_SOURCE is not functional. It has too high a varation. -//========================================================== -#ifndef USE_COMP -#define USE_COMP 0 -#endif -// TIMER0_FOR_CSENSE - First TIMER instance used by the driver (not used on nRF51). -#ifndef TIMER0_FOR_CSENSE -#define TIMER0_FOR_CSENSE 1 -#endif - -// TIMER1_FOR_CSENSE - Second TIMER instance used by the driver (not used on nRF51). -#ifndef TIMER1_FOR_CSENSE -#define TIMER1_FOR_CSENSE 2 -#endif - -// MEASUREMENT_PERIOD - Single measurement period. -// Time of a single measurement can be calculated as -// T = (1/2)*MEASUREMENT_PERIOD*(1/f_OSC) where f_OSC = I_SOURCE / (2C*(VUP-VDOWN) ). -// I_SOURCE, VUP, and VDOWN are values used to initialize COMP and C is the capacitance of the used pad. - -#ifndef MEASUREMENT_PERIOD -#define MEASUREMENT_PERIOD 20 -#endif - -// - -// - -// NRF_FPRINTF_ENABLED - nrf_fprintf - fprintf function. - - -#ifndef NRF_FPRINTF_ENABLED -#define NRF_FPRINTF_ENABLED 1 -#endif - -// NRF_FSTORAGE_ENABLED - nrf_fstorage - Flash abstraction library -//========================================================== -#ifndef NRF_FSTORAGE_ENABLED -#define NRF_FSTORAGE_ENABLED 0 -#endif -// nrf_fstorage - Common settings - -// Common settings to all fstorage implementations -//========================================================== -// NRF_FSTORAGE_PARAM_CHECK_DISABLED - Disable user input validation - - -// If selected, use ASSERT to validate user input. -// This effectively removes user input validation in production code. -// Recommended setting: OFF, only enable this setting if size is a major concern. - -#ifndef NRF_FSTORAGE_PARAM_CHECK_DISABLED -#define NRF_FSTORAGE_PARAM_CHECK_DISABLED 0 -#endif - -// -//========================================================== - -// nrf_fstorage_sd - Implementation using the SoftDevice - -// Configuration options for the fstorage implementation using the SoftDevice -//========================================================== -// NRF_FSTORAGE_SD_QUEUE_SIZE - Size of the internal queue of operations -// Increase this value if API calls frequently return the error @ref NRF_ERROR_NO_MEM. - -#ifndef NRF_FSTORAGE_SD_QUEUE_SIZE -#define NRF_FSTORAGE_SD_QUEUE_SIZE 4 -#endif - -// NRF_FSTORAGE_SD_MAX_RETRIES - Maximum number of attempts at executing an operation when the SoftDevice is busy -// Increase this value if events frequently return the @ref NRF_ERROR_TIMEOUT error. -// The SoftDevice might fail to schedule flash access due to high BLE activity. - -#ifndef NRF_FSTORAGE_SD_MAX_RETRIES -#define NRF_FSTORAGE_SD_MAX_RETRIES 8 -#endif - -// NRF_FSTORAGE_SD_MAX_WRITE_SIZE - Maximum number of bytes to be written to flash in a single operation -// This value must be a multiple of four. -// Lowering this value can increase the chances of the SoftDevice being able to execute flash operations in between radio activity. -// This value is bound by the maximum number of bytes that can be written to flash in a single call to @ref sd_flash_write. -// That is 1024 bytes for nRF51 ICs and 4096 bytes for nRF52 ICs. - -#ifndef NRF_FSTORAGE_SD_MAX_WRITE_SIZE -#define NRF_FSTORAGE_SD_MAX_WRITE_SIZE 4096 -#endif - -// -//========================================================== - -// - -// NRF_GFX_ENABLED - nrf_gfx - GFX module - - -#ifndef NRF_GFX_ENABLED -#define NRF_GFX_ENABLED 0 -#endif - -// NRF_MEMOBJ_ENABLED - nrf_memobj - Linked memory allocator module - - -#ifndef NRF_MEMOBJ_ENABLED -#define NRF_MEMOBJ_ENABLED 1 -#endif - -// NRF_PWR_MGMT_ENABLED - nrf_pwr_mgmt - Power management module -//========================================================== -#ifndef NRF_PWR_MGMT_ENABLED -#define NRF_PWR_MGMT_ENABLED 0 -#endif -// NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED - Enables pin debug in the module. - -// Selected pin will be set when CPU is in sleep mode. -//========================================================== -#ifndef NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED -#define NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED 0 -#endif -// NRF_PWR_MGMT_SLEEP_DEBUG_PIN - Pin number - -// <0=> 0 (P0.0) -// <1=> 1 (P0.1) -// <2=> 2 (P0.2) -// <3=> 3 (P0.3) -// <4=> 4 (P0.4) -// <5=> 5 (P0.5) -// <6=> 6 (P0.6) -// <7=> 7 (P0.7) -// <8=> 8 (P0.8) -// <9=> 9 (P0.9) -// <10=> 10 (P0.10) -// <11=> 11 (P0.11) -// <12=> 12 (P0.12) -// <13=> 13 (P0.13) -// <14=> 14 (P0.14) -// <15=> 15 (P0.15) -// <16=> 16 (P0.16) -// <17=> 17 (P0.17) -// <18=> 18 (P0.18) -// <19=> 19 (P0.19) -// <20=> 20 (P0.20) -// <21=> 21 (P0.21) -// <22=> 22 (P0.22) -// <23=> 23 (P0.23) -// <24=> 24 (P0.24) -// <25=> 25 (P0.25) -// <26=> 26 (P0.26) -// <27=> 27 (P0.27) -// <28=> 28 (P0.28) -// <29=> 29 (P0.29) -// <30=> 30 (P0.30) -// <31=> 31 (P0.31) -// <32=> 32 (P1.0) -// <33=> 33 (P1.1) -// <34=> 34 (P1.2) -// <35=> 35 (P1.3) -// <36=> 36 (P1.4) -// <37=> 37 (P1.5) -// <38=> 38 (P1.6) -// <39=> 39 (P1.7) -// <40=> 40 (P1.8) -// <41=> 41 (P1.9) -// <42=> 42 (P1.10) -// <43=> 43 (P1.11) -// <44=> 44 (P1.12) -// <45=> 45 (P1.13) -// <46=> 46 (P1.14) -// <47=> 47 (P1.15) -// <4294967295=> Not connected - -#ifndef NRF_PWR_MGMT_SLEEP_DEBUG_PIN -#define NRF_PWR_MGMT_SLEEP_DEBUG_PIN 31 -#endif - -// - -// NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED - Enables CPU usage monitor. - - -// Module will trace percentage of CPU usage in one second intervals. - -#ifndef NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED -#define NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED 0 -#endif - -// NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED - Enable standby timeout. -//========================================================== -#ifndef NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED -#define NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED 0 -#endif -// NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S - Standby timeout (in seconds). -// Shutdown procedure will begin no earlier than after this number of seconds. - -#ifndef NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S -#define NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S 3 -#endif - -// - -// NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED - Enables FPU event cleaning. - - -#ifndef NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED -#define NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED 0 -#endif - -// NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY - Blocked shutdown procedure will be retried every second. - - -#ifndef NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY -#define NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY 0 -#endif - -// NRF_PWR_MGMT_CONFIG_USE_SCHEDULER - Module will use @ref app_scheduler. - - -#ifndef NRF_PWR_MGMT_CONFIG_USE_SCHEDULER -#define NRF_PWR_MGMT_CONFIG_USE_SCHEDULER 0 -#endif - -// NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT - The number of priorities for module handlers. -// The number of stages of the shutdown process. - -#ifndef NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT -#define NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT 3 -#endif - -// - -// NRF_QUEUE_ENABLED - nrf_queue - Queue module -//========================================================== -#ifndef NRF_QUEUE_ENABLED -#define NRF_QUEUE_ENABLED 0 -#endif -// NRF_QUEUE_CLI_CMDS - Enable CLI commands specific to the module - - -#ifndef NRF_QUEUE_CLI_CMDS -#define NRF_QUEUE_CLI_CMDS 0 -#endif - -// - -// NRF_SECTION_ITER_ENABLED - nrf_section_iter - Section iterator - - -#ifndef NRF_SECTION_ITER_ENABLED -#define NRF_SECTION_ITER_ENABLED 1 -#endif - -// NRF_SORTLIST_ENABLED - nrf_sortlist - Sorted list - - -#ifndef NRF_SORTLIST_ENABLED -#define NRF_SORTLIST_ENABLED 0 -#endif - -// NRF_SPI_MNGR_ENABLED - nrf_spi_mngr - SPI transaction manager - - -#ifndef NRF_SPI_MNGR_ENABLED -#define NRF_SPI_MNGR_ENABLED 0 -#endif - -// NRF_STRERROR_ENABLED - nrf_strerror - Library for converting error code to string. - - -#ifndef NRF_STRERROR_ENABLED -#define NRF_STRERROR_ENABLED 1 -#endif - -// NRF_TWI_MNGR_ENABLED - nrf_twi_mngr - TWI transaction manager - - -#ifndef NRF_TWI_MNGR_ENABLED -#define NRF_TWI_MNGR_ENABLED 0 -#endif - -// SLIP_ENABLED - slip - SLIP encoding and decoding - - -#ifndef SLIP_ENABLED -#define SLIP_ENABLED 0 -#endif - -// TASK_MANAGER_ENABLED - task_manager - Task manager. -//========================================================== -#ifndef TASK_MANAGER_ENABLED -#define TASK_MANAGER_ENABLED 0 -#endif -// TASK_MANAGER_CLI_CMDS - Enable CLI commands specific to the module - - -#ifndef TASK_MANAGER_CLI_CMDS -#define TASK_MANAGER_CLI_CMDS 0 -#endif - -// TASK_MANAGER_CONFIG_MAX_TASKS - Maximum number of tasks which can be created -#ifndef TASK_MANAGER_CONFIG_MAX_TASKS -#define TASK_MANAGER_CONFIG_MAX_TASKS 2 -#endif - -// TASK_MANAGER_CONFIG_STACK_SIZE - Stack size for every task (power of 2) -#ifndef TASK_MANAGER_CONFIG_STACK_SIZE -#define TASK_MANAGER_CONFIG_STACK_SIZE 1024 -#endif - -// TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED - Enable stack profiling. - - -#ifndef TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED -#define TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED 1 -#endif - -// TASK_MANAGER_CONFIG_STACK_GUARD - Configures stack guard. - -// <0=> Disabled -// <4=> 32 bytes -// <5=> 64 bytes -// <6=> 128 bytes -// <7=> 256 bytes -// <8=> 512 bytes - -#ifndef TASK_MANAGER_CONFIG_STACK_GUARD -#define TASK_MANAGER_CONFIG_STACK_GUARD 7 -#endif - -// - -// app_button - buttons handling module - -//========================================================== -// BUTTON_ENABLED - Enables Button module - - -#ifndef BUTTON_ENABLED -#define BUTTON_ENABLED 0 -#endif - -// BUTTON_HIGH_ACCURACY_ENABLED - Enables GPIOTE high accuracy for buttons - - -#ifndef BUTTON_HIGH_ACCURACY_ENABLED -#define BUTTON_HIGH_ACCURACY_ENABLED 0 -#endif - -// -//========================================================== - -// nrf_cli - Command line interface - -//========================================================== -// NRF_CLI_ENABLED - Enable/disable the CLI module. - - -#ifndef NRF_CLI_ENABLED -#define NRF_CLI_ENABLED 0 -#endif - -// NRF_CLI_ARGC_MAX - Maximum number of parameters passed to the command handler. -#ifndef NRF_CLI_ARGC_MAX -#define NRF_CLI_ARGC_MAX 12 -#endif - -// NRF_CLI_BUILD_IN_CMDS_ENABLED - CLI built-in commands. - - -#ifndef NRF_CLI_BUILD_IN_CMDS_ENABLED -#define NRF_CLI_BUILD_IN_CMDS_ENABLED 1 -#endif - -// NRF_CLI_CMD_BUFF_SIZE - Maximum buffer size for a single command. -#ifndef NRF_CLI_CMD_BUFF_SIZE -#define NRF_CLI_CMD_BUFF_SIZE 128 -#endif - -// NRF_CLI_ECHO_STATUS - CLI echo status. If set, echo is ON. - - -#ifndef NRF_CLI_ECHO_STATUS -#define NRF_CLI_ECHO_STATUS 1 -#endif - -// NRF_CLI_WILDCARD_ENABLED - Enable wildcard functionality for CLI commands. - - -#ifndef NRF_CLI_WILDCARD_ENABLED -#define NRF_CLI_WILDCARD_ENABLED 0 -#endif - -// NRF_CLI_PRINTF_BUFF_SIZE - Maximum print buffer size. -#ifndef NRF_CLI_PRINTF_BUFF_SIZE -#define NRF_CLI_PRINTF_BUFF_SIZE 23 -#endif - -// NRF_CLI_HISTORY_ENABLED - Enable CLI history mode. -//========================================================== -#ifndef NRF_CLI_HISTORY_ENABLED -#define NRF_CLI_HISTORY_ENABLED 1 -#endif -// NRF_CLI_HISTORY_ELEMENT_SIZE - Size of one memory object reserved for CLI history. -#ifndef NRF_CLI_HISTORY_ELEMENT_SIZE -#define NRF_CLI_HISTORY_ELEMENT_SIZE 32 -#endif - -// NRF_CLI_HISTORY_ELEMENT_COUNT - Number of history memory objects. -#ifndef NRF_CLI_HISTORY_ELEMENT_COUNT -#define NRF_CLI_HISTORY_ELEMENT_COUNT 8 -#endif - -// - -// NRF_CLI_VT100_COLORS_ENABLED - CLI VT100 colors. - - -#ifndef NRF_CLI_VT100_COLORS_ENABLED -#define NRF_CLI_VT100_COLORS_ENABLED 1 -#endif - -// NRF_CLI_STATISTICS_ENABLED - Enable CLI statistics. - - -#ifndef NRF_CLI_STATISTICS_ENABLED -#define NRF_CLI_STATISTICS_ENABLED 1 -#endif - -// NRF_CLI_LOG_BACKEND - Enable logger backend interface. - - -#ifndef NRF_CLI_LOG_BACKEND -#define NRF_CLI_LOG_BACKEND 1 -#endif - -// NRF_CLI_USES_TASK_MANAGER_ENABLED - Enable CLI to use task_manager - - -#ifndef NRF_CLI_USES_TASK_MANAGER_ENABLED -#define NRF_CLI_USES_TASK_MANAGER_ENABLED 0 -#endif - -// -//========================================================== - -// -//========================================================== - -// nRF_Log - -//========================================================== -// NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED - nrf_log_str_formatter - Log string formatter - - -#ifndef NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED -#define NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED 1 -#endif - -// nrf_log - Logger - -//========================================================== -// NRF_LOG_ENABLED - Logging module for nRF5 SDK -//========================================================== -#ifndef NRF_LOG_ENABLED -#define NRF_LOG_ENABLED 0 -#endif -// NRF_LOG_USES_COLORS - If enabled then ANSI escape code for colors is prefixed to every string -//========================================================== -#ifndef NRF_LOG_USES_COLORS -#define NRF_LOG_USES_COLORS 0 -#endif -// NRF_LOG_COLOR_DEFAULT - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_LOG_COLOR_DEFAULT -#define NRF_LOG_COLOR_DEFAULT 0 -#endif - -// NRF_LOG_ERROR_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_LOG_ERROR_COLOR -#define NRF_LOG_ERROR_COLOR 2 -#endif - -// NRF_LOG_WARNING_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_LOG_WARNING_COLOR -#define NRF_LOG_WARNING_COLOR 4 -#endif - -// - -// NRF_LOG_DEFAULT_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRF_LOG_DEFAULT_LEVEL -#define NRF_LOG_DEFAULT_LEVEL 3 -#endif - -// NRF_LOG_DEFERRED - Enable deffered logger. - - -// Log data is buffered and can be processed in idle. - -#ifndef NRF_LOG_DEFERRED -#define NRF_LOG_DEFERRED 1 -#endif - -// NRF_LOG_BUFSIZE - Size of the buffer for storing logs (in bytes). - - -// Must be power of 2 and multiple of 4. -// If NRF_LOG_DEFERRED = 0 then buffer size can be reduced to minimum. -// <128=> 128 -// <256=> 256 -// <512=> 512 -// <1024=> 1024 -// <2048=> 2048 -// <4096=> 4096 -// <8192=> 8192 -// <16384=> 16384 - -#ifndef NRF_LOG_BUFSIZE -#define NRF_LOG_BUFSIZE 1024 -#endif - -// NRF_LOG_ALLOW_OVERFLOW - Configures behavior when circular buffer is full. - - -// If set then oldest logs are overwritten. Otherwise a -// marker is injected informing about overflow. - -#ifndef NRF_LOG_ALLOW_OVERFLOW -#define NRF_LOG_ALLOW_OVERFLOW 1 -#endif - -// NRF_LOG_USES_TIMESTAMP - Enable timestamping - -// Function for getting the timestamp is provided by the user -//========================================================== -#ifndef NRF_LOG_USES_TIMESTAMP -#define NRF_LOG_USES_TIMESTAMP 0 -#endif -// NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY - Default frequency of the timestamp (in Hz) -#ifndef NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY -#define NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY 32768 -#endif - -// - -// NRF_LOG_FILTERS_ENABLED - Enable dynamic filtering of logs. - - -#ifndef NRF_LOG_FILTERS_ENABLED -#define NRF_LOG_FILTERS_ENABLED 0 -#endif - -// NRF_LOG_CLI_CMDS - Enable CLI commands for the module. - - -#ifndef NRF_LOG_CLI_CMDS -#define NRF_LOG_CLI_CMDS 0 -#endif - -// Log message pool - Configuration of log message pool - -//========================================================== -// NRF_LOG_MSGPOOL_ELEMENT_SIZE - Size of a single element in the pool of memory objects. -// If a small value is set, then performance of logs processing -// is degraded because data is fragmented. Bigger value impacts -// RAM memory utilization. The size is set to fit a message with -// a timestamp and up to 2 arguments in a single memory object. - -#ifndef NRF_LOG_MSGPOOL_ELEMENT_SIZE -#define NRF_LOG_MSGPOOL_ELEMENT_SIZE 20 -#endif - -// NRF_LOG_MSGPOOL_ELEMENT_COUNT - Number of elements in the pool of memory objects -// If a small value is set, then it may lead to a deadlock -// in certain cases if backend has high latency and holds -// multiple messages for long time. Bigger value impacts -// RAM memory usage. - -#ifndef NRF_LOG_MSGPOOL_ELEMENT_COUNT -#define NRF_LOG_MSGPOOL_ELEMENT_COUNT 8 -#endif - -// -//========================================================== - -// - -// nrf_log module configuration - -//========================================================== -// nrf_log in nRF_Core - -//========================================================== -// NRF_MPU_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRF_MPU_CONFIG_LOG_ENABLED -#define NRF_MPU_CONFIG_LOG_ENABLED 0 -#endif -// NRF_MPU_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRF_MPU_CONFIG_LOG_LEVEL -#define NRF_MPU_CONFIG_LOG_LEVEL 3 -#endif - -// NRF_MPU_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_MPU_CONFIG_INFO_COLOR -#define NRF_MPU_CONFIG_INFO_COLOR 0 -#endif - -// NRF_MPU_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_MPU_CONFIG_DEBUG_COLOR -#define NRF_MPU_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// NRF_STACK_GUARD_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRF_STACK_GUARD_CONFIG_LOG_ENABLED -#define NRF_STACK_GUARD_CONFIG_LOG_ENABLED 0 -#endif -// NRF_STACK_GUARD_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRF_STACK_GUARD_CONFIG_LOG_LEVEL -#define NRF_STACK_GUARD_CONFIG_LOG_LEVEL 3 -#endif - -// NRF_STACK_GUARD_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_STACK_GUARD_CONFIG_INFO_COLOR -#define NRF_STACK_GUARD_CONFIG_INFO_COLOR 0 -#endif - -// NRF_STACK_GUARD_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_STACK_GUARD_CONFIG_DEBUG_COLOR -#define NRF_STACK_GUARD_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// TASK_MANAGER_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef TASK_MANAGER_CONFIG_LOG_ENABLED -#define TASK_MANAGER_CONFIG_LOG_ENABLED 0 -#endif -// TASK_MANAGER_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef TASK_MANAGER_CONFIG_LOG_LEVEL -#define TASK_MANAGER_CONFIG_LOG_LEVEL 3 -#endif - -// TASK_MANAGER_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef TASK_MANAGER_CONFIG_INFO_COLOR -#define TASK_MANAGER_CONFIG_INFO_COLOR 0 -#endif - -// TASK_MANAGER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef TASK_MANAGER_CONFIG_DEBUG_COLOR -#define TASK_MANAGER_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// -//========================================================== - -// nrf_log in nRF_Drivers - -//========================================================== -// CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef CLOCK_CONFIG_LOG_ENABLED -#define CLOCK_CONFIG_LOG_ENABLED 0 -#endif -// CLOCK_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef CLOCK_CONFIG_LOG_LEVEL -#define CLOCK_CONFIG_LOG_LEVEL 3 -#endif - -// CLOCK_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef CLOCK_CONFIG_INFO_COLOR -#define CLOCK_CONFIG_INFO_COLOR 0 -#endif - -// CLOCK_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef CLOCK_CONFIG_DEBUG_COLOR -#define CLOCK_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// COMP_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef COMP_CONFIG_LOG_ENABLED -#define COMP_CONFIG_LOG_ENABLED 0 -#endif -// COMP_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef COMP_CONFIG_LOG_LEVEL -#define COMP_CONFIG_LOG_LEVEL 3 -#endif - -// COMP_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef COMP_CONFIG_INFO_COLOR -#define COMP_CONFIG_INFO_COLOR 0 -#endif - -// COMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef COMP_CONFIG_DEBUG_COLOR -#define COMP_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef GPIOTE_CONFIG_LOG_ENABLED -#define GPIOTE_CONFIG_LOG_ENABLED 0 -#endif -// GPIOTE_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef GPIOTE_CONFIG_LOG_LEVEL -#define GPIOTE_CONFIG_LOG_LEVEL 3 -#endif - -// GPIOTE_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef GPIOTE_CONFIG_INFO_COLOR -#define GPIOTE_CONFIG_INFO_COLOR 0 -#endif - -// GPIOTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef GPIOTE_CONFIG_DEBUG_COLOR -#define GPIOTE_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// LPCOMP_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef LPCOMP_CONFIG_LOG_ENABLED -#define LPCOMP_CONFIG_LOG_ENABLED 0 -#endif -// LPCOMP_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef LPCOMP_CONFIG_LOG_LEVEL -#define LPCOMP_CONFIG_LOG_LEVEL 3 -#endif - -// LPCOMP_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef LPCOMP_CONFIG_INFO_COLOR -#define LPCOMP_CONFIG_INFO_COLOR 0 -#endif - -// LPCOMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef LPCOMP_CONFIG_DEBUG_COLOR -#define LPCOMP_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// PDM_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef PDM_CONFIG_LOG_ENABLED -#define PDM_CONFIG_LOG_ENABLED 0 -#endif -// PDM_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef PDM_CONFIG_LOG_LEVEL -#define PDM_CONFIG_LOG_LEVEL 3 -#endif - -// PDM_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef PDM_CONFIG_INFO_COLOR -#define PDM_CONFIG_INFO_COLOR 0 -#endif - -// PDM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef PDM_CONFIG_DEBUG_COLOR -#define PDM_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// PPI_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef PPI_CONFIG_LOG_ENABLED -#define PPI_CONFIG_LOG_ENABLED 0 -#endif -// PPI_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef PPI_CONFIG_LOG_LEVEL -#define PPI_CONFIG_LOG_LEVEL 3 -#endif - -// PPI_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef PPI_CONFIG_INFO_COLOR -#define PPI_CONFIG_INFO_COLOR 0 -#endif - -// PPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef PPI_CONFIG_DEBUG_COLOR -#define PPI_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// PWM_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef PWM_CONFIG_LOG_ENABLED -#define PWM_CONFIG_LOG_ENABLED 0 -#endif -// PWM_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef PWM_CONFIG_LOG_LEVEL -#define PWM_CONFIG_LOG_LEVEL 3 -#endif - -// PWM_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef PWM_CONFIG_INFO_COLOR -#define PWM_CONFIG_INFO_COLOR 0 -#endif - -// PWM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef PWM_CONFIG_DEBUG_COLOR -#define PWM_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// QDEC_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef QDEC_CONFIG_LOG_ENABLED -#define QDEC_CONFIG_LOG_ENABLED 0 -#endif -// QDEC_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef QDEC_CONFIG_LOG_LEVEL -#define QDEC_CONFIG_LOG_LEVEL 3 -#endif - -// QDEC_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef QDEC_CONFIG_INFO_COLOR -#define QDEC_CONFIG_INFO_COLOR 0 -#endif - -// QDEC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef QDEC_CONFIG_DEBUG_COLOR -#define QDEC_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// RNG_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef RNG_CONFIG_LOG_ENABLED -#define RNG_CONFIG_LOG_ENABLED 0 -#endif -// RNG_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef RNG_CONFIG_LOG_LEVEL -#define RNG_CONFIG_LOG_LEVEL 3 -#endif - -// RNG_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef RNG_CONFIG_INFO_COLOR -#define RNG_CONFIG_INFO_COLOR 0 -#endif - -// RNG_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef RNG_CONFIG_DEBUG_COLOR -#define RNG_CONFIG_DEBUG_COLOR 0 -#endif - -// RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED - Enables logging of random numbers. - - -#ifndef RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED -#define RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED 0 -#endif - -// - -// RTC_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef RTC_CONFIG_LOG_ENABLED -#define RTC_CONFIG_LOG_ENABLED 0 -#endif -// RTC_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef RTC_CONFIG_LOG_LEVEL -#define RTC_CONFIG_LOG_LEVEL 3 -#endif - -// RTC_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef RTC_CONFIG_INFO_COLOR -#define RTC_CONFIG_INFO_COLOR 0 -#endif - -// RTC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef RTC_CONFIG_DEBUG_COLOR -#define RTC_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// SAADC_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef SAADC_CONFIG_LOG_ENABLED -#define SAADC_CONFIG_LOG_ENABLED 0 -#endif -// SAADC_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef SAADC_CONFIG_LOG_LEVEL -#define SAADC_CONFIG_LOG_LEVEL 3 -#endif - -// SAADC_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef SAADC_CONFIG_INFO_COLOR -#define SAADC_CONFIG_INFO_COLOR 0 -#endif - -// SAADC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef SAADC_CONFIG_DEBUG_COLOR -#define SAADC_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// SPIS_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef SPIS_CONFIG_LOG_ENABLED -#define SPIS_CONFIG_LOG_ENABLED 0 -#endif -// SPIS_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef SPIS_CONFIG_LOG_LEVEL -#define SPIS_CONFIG_LOG_LEVEL 3 -#endif - -// SPIS_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef SPIS_CONFIG_INFO_COLOR -#define SPIS_CONFIG_INFO_COLOR 0 -#endif - -// SPIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef SPIS_CONFIG_DEBUG_COLOR -#define SPIS_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// SPI_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef SPI_CONFIG_LOG_ENABLED -#define SPI_CONFIG_LOG_ENABLED 0 -#endif -// SPI_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef SPI_CONFIG_LOG_LEVEL -#define SPI_CONFIG_LOG_LEVEL 3 -#endif - -// SPI_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef SPI_CONFIG_INFO_COLOR -#define SPI_CONFIG_INFO_COLOR 0 -#endif - -// SPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef SPI_CONFIG_DEBUG_COLOR -#define SPI_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// TIMER_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef TIMER_CONFIG_LOG_ENABLED -#define TIMER_CONFIG_LOG_ENABLED 0 -#endif -// TIMER_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef TIMER_CONFIG_LOG_LEVEL -#define TIMER_CONFIG_LOG_LEVEL 3 -#endif - -// TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef TIMER_CONFIG_INFO_COLOR -#define TIMER_CONFIG_INFO_COLOR 0 -#endif - -// TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef TIMER_CONFIG_DEBUG_COLOR -#define TIMER_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// TWIS_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef TWIS_CONFIG_LOG_ENABLED -#define TWIS_CONFIG_LOG_ENABLED 0 -#endif -// TWIS_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef TWIS_CONFIG_LOG_LEVEL -#define TWIS_CONFIG_LOG_LEVEL 3 -#endif - -// TWIS_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef TWIS_CONFIG_INFO_COLOR -#define TWIS_CONFIG_INFO_COLOR 0 -#endif - -// TWIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef TWIS_CONFIG_DEBUG_COLOR -#define TWIS_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// TWI_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef TWI_CONFIG_LOG_ENABLED -#define TWI_CONFIG_LOG_ENABLED 0 -#endif -// TWI_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef TWI_CONFIG_LOG_LEVEL -#define TWI_CONFIG_LOG_LEVEL 3 -#endif - -// TWI_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef TWI_CONFIG_INFO_COLOR -#define TWI_CONFIG_INFO_COLOR 0 -#endif - -// TWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef TWI_CONFIG_DEBUG_COLOR -#define TWI_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// UART_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef UART_CONFIG_LOG_ENABLED -#define UART_CONFIG_LOG_ENABLED 0 -#endif -// UART_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef UART_CONFIG_LOG_LEVEL -#define UART_CONFIG_LOG_LEVEL 3 -#endif - -// UART_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef UART_CONFIG_INFO_COLOR -#define UART_CONFIG_INFO_COLOR 0 -#endif - -// UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef UART_CONFIG_DEBUG_COLOR -#define UART_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// USBD_CONFIG_LOG_ENABLED - Enable logging in the module -//========================================================== -#ifndef USBD_CONFIG_LOG_ENABLED -#define USBD_CONFIG_LOG_ENABLED 0 -#endif -// USBD_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef USBD_CONFIG_LOG_LEVEL -#define USBD_CONFIG_LOG_LEVEL 3 -#endif - -// USBD_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef USBD_CONFIG_INFO_COLOR -#define USBD_CONFIG_INFO_COLOR 0 -#endif - -// USBD_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef USBD_CONFIG_DEBUG_COLOR -#define USBD_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// WDT_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef WDT_CONFIG_LOG_ENABLED -#define WDT_CONFIG_LOG_ENABLED 0 -#endif -// WDT_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef WDT_CONFIG_LOG_LEVEL -#define WDT_CONFIG_LOG_LEVEL 3 -#endif - -// WDT_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef WDT_CONFIG_INFO_COLOR -#define WDT_CONFIG_INFO_COLOR 0 -#endif - -// WDT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef WDT_CONFIG_DEBUG_COLOR -#define WDT_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// -//========================================================== - -// nrf_log in nRF_Libraries - -//========================================================== -// APP_TIMER_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef APP_TIMER_CONFIG_LOG_ENABLED -#define APP_TIMER_CONFIG_LOG_ENABLED 0 -#endif -// APP_TIMER_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef APP_TIMER_CONFIG_LOG_LEVEL -#define APP_TIMER_CONFIG_LOG_LEVEL 3 -#endif - -// APP_TIMER_CONFIG_INITIAL_LOG_LEVEL - Initial severity level if dynamic filtering is enabled. - - -// If module generates a lot of logs, initial log level can -// be decreased to prevent flooding. Severity level can be -// increased on instance basis. -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef APP_TIMER_CONFIG_INITIAL_LOG_LEVEL -#define APP_TIMER_CONFIG_INITIAL_LOG_LEVEL 3 -#endif - -// APP_TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef APP_TIMER_CONFIG_INFO_COLOR -#define APP_TIMER_CONFIG_INFO_COLOR 0 -#endif - -// APP_TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef APP_TIMER_CONFIG_DEBUG_COLOR -#define APP_TIMER_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// APP_USBD_CDC_ACM_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef APP_USBD_CDC_ACM_CONFIG_LOG_ENABLED -#define APP_USBD_CDC_ACM_CONFIG_LOG_ENABLED 0 -#endif -// APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL -#define APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL 3 -#endif - -// APP_USBD_CDC_ACM_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef APP_USBD_CDC_ACM_CONFIG_INFO_COLOR -#define APP_USBD_CDC_ACM_CONFIG_INFO_COLOR 0 -#endif - -// APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR -#define APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// APP_USBD_DUMMY_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef APP_USBD_DUMMY_CONFIG_LOG_ENABLED -#define APP_USBD_DUMMY_CONFIG_LOG_ENABLED 0 -#endif -// APP_USBD_DUMMY_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef APP_USBD_DUMMY_CONFIG_LOG_LEVEL -#define APP_USBD_DUMMY_CONFIG_LOG_LEVEL 3 -#endif - -// APP_USBD_DUMMY_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef APP_USBD_DUMMY_CONFIG_INFO_COLOR -#define APP_USBD_DUMMY_CONFIG_INFO_COLOR 0 -#endif - -// APP_USBD_DUMMY_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef APP_USBD_DUMMY_CONFIG_DEBUG_COLOR -#define APP_USBD_DUMMY_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// APP_USBD_MSC_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef APP_USBD_MSC_CONFIG_LOG_ENABLED -#define APP_USBD_MSC_CONFIG_LOG_ENABLED 0 -#endif -// APP_USBD_MSC_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef APP_USBD_MSC_CONFIG_LOG_LEVEL -#define APP_USBD_MSC_CONFIG_LOG_LEVEL 3 -#endif - -// APP_USBD_MSC_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef APP_USBD_MSC_CONFIG_INFO_COLOR -#define APP_USBD_MSC_CONFIG_INFO_COLOR 0 -#endif - -// APP_USBD_MSC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef APP_USBD_MSC_CONFIG_DEBUG_COLOR -#define APP_USBD_MSC_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_ENABLED -#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_ENABLED 0 -#endif -// APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL -#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL 3 -#endif - -// APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR -#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR 0 -#endif - -// APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR -#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// NRF_ATFIFO_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRF_ATFIFO_CONFIG_LOG_ENABLED -#define NRF_ATFIFO_CONFIG_LOG_ENABLED 0 -#endif -// NRF_ATFIFO_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRF_ATFIFO_CONFIG_LOG_LEVEL -#define NRF_ATFIFO_CONFIG_LOG_LEVEL 3 -#endif - -// NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL - Initial severity level if dynamic filtering is enabled - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL -#define NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL 3 -#endif - -// NRF_ATFIFO_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_ATFIFO_CONFIG_INFO_COLOR -#define NRF_ATFIFO_CONFIG_INFO_COLOR 0 -#endif - -// NRF_ATFIFO_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_ATFIFO_CONFIG_DEBUG_COLOR -#define NRF_ATFIFO_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// NRF_BALLOC_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRF_BALLOC_CONFIG_LOG_ENABLED -#define NRF_BALLOC_CONFIG_LOG_ENABLED 0 -#endif -// NRF_BALLOC_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRF_BALLOC_CONFIG_LOG_LEVEL -#define NRF_BALLOC_CONFIG_LOG_LEVEL 3 -#endif - -// NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL - Initial severity level if dynamic filtering is enabled. - - -// If module generates a lot of logs, initial log level can -// be decreased to prevent flooding. Severity level can be -// increased on instance basis. -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL -#define NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL 3 -#endif - -// NRF_BALLOC_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_BALLOC_CONFIG_INFO_COLOR -#define NRF_BALLOC_CONFIG_INFO_COLOR 0 -#endif - -// NRF_BALLOC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_BALLOC_CONFIG_DEBUG_COLOR -#define NRF_BALLOC_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// NRF_CLI_BLE_UART_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRF_CLI_BLE_UART_CONFIG_LOG_ENABLED -#define NRF_CLI_BLE_UART_CONFIG_LOG_ENABLED 0 -#endif -// NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL -#define NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL 3 -#endif - -// NRF_CLI_BLE_UART_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_CLI_BLE_UART_CONFIG_INFO_COLOR -#define NRF_CLI_BLE_UART_CONFIG_INFO_COLOR 0 -#endif - -// NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR -#define NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// NRF_CLI_LIBUARTE_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRF_CLI_LIBUARTE_CONFIG_LOG_ENABLED -#define NRF_CLI_LIBUARTE_CONFIG_LOG_ENABLED 0 -#endif -// NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL -#define NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL 3 -#endif - -// NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR -#define NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR 0 -#endif - -// NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR -#define NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// NRF_CLI_UART_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRF_CLI_UART_CONFIG_LOG_ENABLED -#define NRF_CLI_UART_CONFIG_LOG_ENABLED 0 -#endif -// NRF_CLI_UART_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRF_CLI_UART_CONFIG_LOG_LEVEL -#define NRF_CLI_UART_CONFIG_LOG_LEVEL 3 -#endif - -// NRF_CLI_UART_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_CLI_UART_CONFIG_INFO_COLOR -#define NRF_CLI_UART_CONFIG_INFO_COLOR 0 -#endif - -// NRF_CLI_UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_CLI_UART_CONFIG_DEBUG_COLOR -#define NRF_CLI_UART_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// NRF_LIBUARTE_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRF_LIBUARTE_CONFIG_LOG_ENABLED -#define NRF_LIBUARTE_CONFIG_LOG_ENABLED 0 -#endif -// NRF_LIBUARTE_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRF_LIBUARTE_CONFIG_LOG_LEVEL -#define NRF_LIBUARTE_CONFIG_LOG_LEVEL 3 -#endif - -// NRF_LIBUARTE_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_LIBUARTE_CONFIG_INFO_COLOR -#define NRF_LIBUARTE_CONFIG_INFO_COLOR 0 -#endif - -// NRF_LIBUARTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_LIBUARTE_CONFIG_DEBUG_COLOR -#define NRF_LIBUARTE_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// NRF_MEMOBJ_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRF_MEMOBJ_CONFIG_LOG_ENABLED -#define NRF_MEMOBJ_CONFIG_LOG_ENABLED 0 -#endif -// NRF_MEMOBJ_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRF_MEMOBJ_CONFIG_LOG_LEVEL -#define NRF_MEMOBJ_CONFIG_LOG_LEVEL 3 -#endif - -// NRF_MEMOBJ_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_MEMOBJ_CONFIG_INFO_COLOR -#define NRF_MEMOBJ_CONFIG_INFO_COLOR 0 -#endif - -// NRF_MEMOBJ_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_MEMOBJ_CONFIG_DEBUG_COLOR -#define NRF_MEMOBJ_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// NRF_PWR_MGMT_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRF_PWR_MGMT_CONFIG_LOG_ENABLED -#define NRF_PWR_MGMT_CONFIG_LOG_ENABLED 0 -#endif -// NRF_PWR_MGMT_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRF_PWR_MGMT_CONFIG_LOG_LEVEL -#define NRF_PWR_MGMT_CONFIG_LOG_LEVEL 3 -#endif - -// NRF_PWR_MGMT_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_PWR_MGMT_CONFIG_INFO_COLOR -#define NRF_PWR_MGMT_CONFIG_INFO_COLOR 0 -#endif - -// NRF_PWR_MGMT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_PWR_MGMT_CONFIG_DEBUG_COLOR -#define NRF_PWR_MGMT_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// NRF_QUEUE_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRF_QUEUE_CONFIG_LOG_ENABLED -#define NRF_QUEUE_CONFIG_LOG_ENABLED 0 -#endif -// NRF_QUEUE_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRF_QUEUE_CONFIG_LOG_LEVEL -#define NRF_QUEUE_CONFIG_LOG_LEVEL 3 -#endif - -// NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL - Initial severity level if dynamic filtering is enabled - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL -#define NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL 3 -#endif - -// NRF_QUEUE_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_QUEUE_CONFIG_INFO_COLOR -#define NRF_QUEUE_CONFIG_INFO_COLOR 0 -#endif - -// NRF_QUEUE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_QUEUE_CONFIG_DEBUG_COLOR -#define NRF_QUEUE_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// NRF_SDH_ANT_LOG_ENABLED - Enable logging in SoftDevice handler (ANT) module. -//========================================================== -#ifndef NRF_SDH_ANT_LOG_ENABLED -#define NRF_SDH_ANT_LOG_ENABLED 0 -#endif -// NRF_SDH_ANT_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRF_SDH_ANT_LOG_LEVEL -#define NRF_SDH_ANT_LOG_LEVEL 3 -#endif - -// NRF_SDH_ANT_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_SDH_ANT_INFO_COLOR -#define NRF_SDH_ANT_INFO_COLOR 0 -#endif - -// NRF_SDH_ANT_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_SDH_ANT_DEBUG_COLOR -#define NRF_SDH_ANT_DEBUG_COLOR 0 -#endif - -// - -// NRF_SDH_BLE_LOG_ENABLED - Enable logging in SoftDevice handler (BLE) module. -//========================================================== -#ifndef NRF_SDH_BLE_LOG_ENABLED -#define NRF_SDH_BLE_LOG_ENABLED 1 -#endif -// NRF_SDH_BLE_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRF_SDH_BLE_LOG_LEVEL -#define NRF_SDH_BLE_LOG_LEVEL 3 -#endif - -// NRF_SDH_BLE_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_SDH_BLE_INFO_COLOR -#define NRF_SDH_BLE_INFO_COLOR 0 -#endif - -// NRF_SDH_BLE_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_SDH_BLE_DEBUG_COLOR -#define NRF_SDH_BLE_DEBUG_COLOR 0 -#endif - -// - -// NRF_SDH_LOG_ENABLED - Enable logging in SoftDevice handler module. -//========================================================== -#ifndef NRF_SDH_LOG_ENABLED -#define NRF_SDH_LOG_ENABLED 1 -#endif -// NRF_SDH_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRF_SDH_LOG_LEVEL -#define NRF_SDH_LOG_LEVEL 3 -#endif - -// NRF_SDH_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_SDH_INFO_COLOR -#define NRF_SDH_INFO_COLOR 0 -#endif - -// NRF_SDH_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_SDH_DEBUG_COLOR -#define NRF_SDH_DEBUG_COLOR 0 -#endif - -// - -// NRF_SDH_SOC_LOG_ENABLED - Enable logging in SoftDevice handler (SoC) module. -//========================================================== -#ifndef NRF_SDH_SOC_LOG_ENABLED -#define NRF_SDH_SOC_LOG_ENABLED 1 -#endif -// NRF_SDH_SOC_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRF_SDH_SOC_LOG_LEVEL -#define NRF_SDH_SOC_LOG_LEVEL 3 -#endif - -// NRF_SDH_SOC_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_SDH_SOC_INFO_COLOR -#define NRF_SDH_SOC_INFO_COLOR 0 -#endif - -// NRF_SDH_SOC_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_SDH_SOC_DEBUG_COLOR -#define NRF_SDH_SOC_DEBUG_COLOR 0 -#endif - -// - -// NRF_SORTLIST_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRF_SORTLIST_CONFIG_LOG_ENABLED -#define NRF_SORTLIST_CONFIG_LOG_ENABLED 0 -#endif -// NRF_SORTLIST_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRF_SORTLIST_CONFIG_LOG_LEVEL -#define NRF_SORTLIST_CONFIG_LOG_LEVEL 3 -#endif - -// NRF_SORTLIST_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_SORTLIST_CONFIG_INFO_COLOR -#define NRF_SORTLIST_CONFIG_INFO_COLOR 0 -#endif - -// NRF_SORTLIST_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_SORTLIST_CONFIG_DEBUG_COLOR -#define NRF_SORTLIST_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// NRF_TWI_SENSOR_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRF_TWI_SENSOR_CONFIG_LOG_ENABLED -#define NRF_TWI_SENSOR_CONFIG_LOG_ENABLED 0 -#endif -// NRF_TWI_SENSOR_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRF_TWI_SENSOR_CONFIG_LOG_LEVEL -#define NRF_TWI_SENSOR_CONFIG_LOG_LEVEL 3 -#endif - -// NRF_TWI_SENSOR_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_TWI_SENSOR_CONFIG_INFO_COLOR -#define NRF_TWI_SENSOR_CONFIG_INFO_COLOR 0 -#endif - -// NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR -#define NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// -//========================================================== - -// nrf_log in nRF_Serialization - -//========================================================== -// SER_HAL_TRANSPORT_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef SER_HAL_TRANSPORT_CONFIG_LOG_ENABLED -#define SER_HAL_TRANSPORT_CONFIG_LOG_ENABLED 0 -#endif -// SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL -#define SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL 3 -#endif - -// SER_HAL_TRANSPORT_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef SER_HAL_TRANSPORT_CONFIG_INFO_COLOR -#define SER_HAL_TRANSPORT_CONFIG_INFO_COLOR 0 -#endif - -// SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR -#define SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// -//========================================================== - -// -//========================================================== - -// -//========================================================== - -// -//========================================================== - -// nRF_NFC - -//========================================================== -// NFC_AC_REC_ENABLED - nfc_ac_rec - NFC NDEF Alternative Carrier record encoder - - -#ifndef NFC_AC_REC_ENABLED -#define NFC_AC_REC_ENABLED 0 -#endif - -// NFC_AC_REC_PARSER_ENABLED - nfc_ac_rec_parser - Alternative Carrier record parser - - -#ifndef NFC_AC_REC_PARSER_ENABLED -#define NFC_AC_REC_PARSER_ENABLED 0 -#endif - -// NFC_BLE_OOB_ADVDATA_ENABLED - nfc_ble_oob_advdata - AD data for OOB pairing encoder -//========================================================== -#ifndef NFC_BLE_OOB_ADVDATA_ENABLED -#define NFC_BLE_OOB_ADVDATA_ENABLED 0 -#endif -// ADVANCED_ADVDATA_SUPPORT - Non-mandatory AD types for BLE OOB pairing are encoded inside the NDEF message (e.g. service UUIDs) - -// <1=> Enabled -// <0=> Disabled - -#ifndef ADVANCED_ADVDATA_SUPPORT -#define ADVANCED_ADVDATA_SUPPORT 0 -#endif - -// - -// NFC_BLE_OOB_ADVDATA_PARSER_ENABLED - nfc_ble_oob_advdata_parser - BLE OOB pairing AD data parser - - -#ifndef NFC_BLE_OOB_ADVDATA_PARSER_ENABLED -#define NFC_BLE_OOB_ADVDATA_PARSER_ENABLED 0 -#endif - -// NFC_BLE_PAIR_LIB_ENABLED - nfc_ble_pair_lib - Library parameters -//========================================================== -#ifndef NFC_BLE_PAIR_LIB_ENABLED -#define NFC_BLE_PAIR_LIB_ENABLED 0 -#endif -// NFC_BLE_PAIR_LIB_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NFC_BLE_PAIR_LIB_LOG_ENABLED -#define NFC_BLE_PAIR_LIB_LOG_ENABLED 0 -#endif -// NFC_BLE_PAIR_LIB_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NFC_BLE_PAIR_LIB_LOG_LEVEL -#define NFC_BLE_PAIR_LIB_LOG_LEVEL 3 -#endif - -// NFC_BLE_PAIR_LIB_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NFC_BLE_PAIR_LIB_INFO_COLOR -#define NFC_BLE_PAIR_LIB_INFO_COLOR 0 -#endif - -// NFC_BLE_PAIR_LIB_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NFC_BLE_PAIR_LIB_DEBUG_COLOR -#define NFC_BLE_PAIR_LIB_DEBUG_COLOR 0 -#endif - -// - -// NFC_BLE_PAIR_LIB_SECURITY_PARAMETERS - Common Peer Manager security parameters. - -//========================================================== -// BLE_NFC_SEC_PARAM_BOND - Enables device bonding. - -// If bonding is enabled at least one of the BLE_NFC_SEC_PARAM_KDIST options must be enabled. -//========================================================== -#ifndef BLE_NFC_SEC_PARAM_BOND -#define BLE_NFC_SEC_PARAM_BOND 1 -#endif -// BLE_NFC_SEC_PARAM_KDIST_OWN_ENC - Enables Long Term Key and Master Identification distribution by device. - - -#ifndef BLE_NFC_SEC_PARAM_KDIST_OWN_ENC -#define BLE_NFC_SEC_PARAM_KDIST_OWN_ENC 1 -#endif - -// BLE_NFC_SEC_PARAM_KDIST_OWN_ID - Enables Identity Resolving Key and Identity Address Information distribution by device. - - -#ifndef BLE_NFC_SEC_PARAM_KDIST_OWN_ID -#define BLE_NFC_SEC_PARAM_KDIST_OWN_ID 1 -#endif - -// BLE_NFC_SEC_PARAM_KDIST_PEER_ENC - Enables Long Term Key and Master Identification distribution by peer. - - -#ifndef BLE_NFC_SEC_PARAM_KDIST_PEER_ENC -#define BLE_NFC_SEC_PARAM_KDIST_PEER_ENC 1 -#endif - -// BLE_NFC_SEC_PARAM_KDIST_PEER_ID - Enables Identity Resolving Key and Identity Address Information distribution by peer. - - -#ifndef BLE_NFC_SEC_PARAM_KDIST_PEER_ID -#define BLE_NFC_SEC_PARAM_KDIST_PEER_ID 1 -#endif - -// - -// BLE_NFC_SEC_PARAM_MIN_KEY_SIZE - Minimal size of a security key. - -// <7=> 7 -// <8=> 8 -// <9=> 9 -// <10=> 10 -// <11=> 11 -// <12=> 12 -// <13=> 13 -// <14=> 14 -// <15=> 15 -// <16=> 16 - -#ifndef BLE_NFC_SEC_PARAM_MIN_KEY_SIZE -#define BLE_NFC_SEC_PARAM_MIN_KEY_SIZE 7 -#endif - -// BLE_NFC_SEC_PARAM_MAX_KEY_SIZE - Maximal size of a security key. - -// <7=> 7 -// <8=> 8 -// <9=> 9 -// <10=> 10 -// <11=> 11 -// <12=> 12 -// <13=> 13 -// <14=> 14 -// <15=> 15 -// <16=> 16 - -#ifndef BLE_NFC_SEC_PARAM_MAX_KEY_SIZE -#define BLE_NFC_SEC_PARAM_MAX_KEY_SIZE 16 -#endif - -// -//========================================================== - -// - -// NFC_BLE_PAIR_MSG_ENABLED - nfc_ble_pair_msg - NDEF message for OOB pairing encoder - - -#ifndef NFC_BLE_PAIR_MSG_ENABLED -#define NFC_BLE_PAIR_MSG_ENABLED 0 -#endif - -// NFC_CH_COMMON_ENABLED - nfc_ble_pair_common - OOB pairing common data - - -#ifndef NFC_CH_COMMON_ENABLED -#define NFC_CH_COMMON_ENABLED 0 -#endif - -// NFC_EP_OOB_REC_ENABLED - nfc_ep_oob_rec - EP record for BLE pairing encoder - - -#ifndef NFC_EP_OOB_REC_ENABLED -#define NFC_EP_OOB_REC_ENABLED 0 -#endif - -// NFC_HS_REC_ENABLED - nfc_hs_rec - Handover Select NDEF record encoder - - -#ifndef NFC_HS_REC_ENABLED -#define NFC_HS_REC_ENABLED 0 -#endif - -// NFC_LE_OOB_REC_ENABLED - nfc_le_oob_rec - LE record for BLE pairing encoder - - -#ifndef NFC_LE_OOB_REC_ENABLED -#define NFC_LE_OOB_REC_ENABLED 0 -#endif - -// NFC_LE_OOB_REC_PARSER_ENABLED - nfc_le_oob_rec_parser - LE record parser - - -#ifndef NFC_LE_OOB_REC_PARSER_ENABLED -#define NFC_LE_OOB_REC_PARSER_ENABLED 0 -#endif - -// NFC_NDEF_LAUNCHAPP_MSG_ENABLED - nfc_launchapp_msg - Encoding data for NDEF Application Launching message for NFC Tag - - -#ifndef NFC_NDEF_LAUNCHAPP_MSG_ENABLED -#define NFC_NDEF_LAUNCHAPP_MSG_ENABLED 0 -#endif - -// NFC_NDEF_LAUNCHAPP_REC_ENABLED - nfc_launchapp_rec - Encoding data for NDEF Application Launching record for NFC Tag - - -#ifndef NFC_NDEF_LAUNCHAPP_REC_ENABLED -#define NFC_NDEF_LAUNCHAPP_REC_ENABLED 0 -#endif - -// NFC_NDEF_MSG_ENABLED - nfc_ndef_msg - NFC NDEF Message generator module -//========================================================== -#ifndef NFC_NDEF_MSG_ENABLED -#define NFC_NDEF_MSG_ENABLED 0 -#endif -// NFC_NDEF_MSG_TAG_TYPE - NFC Tag Type - -// <2=> Type 2 Tag -// <4=> Type 4 Tag - -#ifndef NFC_NDEF_MSG_TAG_TYPE -#define NFC_NDEF_MSG_TAG_TYPE 2 -#endif - -// - -// NFC_NDEF_MSG_PARSER_ENABLED - nfc_ndef_msg_parser - NFC NDEF message parser module -//========================================================== -#ifndef NFC_NDEF_MSG_PARSER_ENABLED -#define NFC_NDEF_MSG_PARSER_ENABLED 0 -#endif -// NFC_NDEF_MSG_PARSER_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NFC_NDEF_MSG_PARSER_LOG_ENABLED -#define NFC_NDEF_MSG_PARSER_LOG_ENABLED 0 -#endif -// NFC_NDEF_MSG_PARSER_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NFC_NDEF_MSG_PARSER_LOG_LEVEL -#define NFC_NDEF_MSG_PARSER_LOG_LEVEL 3 -#endif - -// NFC_NDEF_MSG_PARSER_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NFC_NDEF_MSG_PARSER_INFO_COLOR -#define NFC_NDEF_MSG_PARSER_INFO_COLOR 0 -#endif - -// - -// - -// NFC_NDEF_RECORD_ENABLED - nfc_ndef_record - NFC NDEF Record generator module - - -#ifndef NFC_NDEF_RECORD_ENABLED -#define NFC_NDEF_RECORD_ENABLED 0 -#endif - -// NFC_NDEF_RECORD_PARSER_ENABLED - nfc_ndef_record_parser - NFC NDEF Record parser module -//========================================================== -#ifndef NFC_NDEF_RECORD_PARSER_ENABLED -#define NFC_NDEF_RECORD_PARSER_ENABLED 0 -#endif -// NFC_NDEF_RECORD_PARSER_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NFC_NDEF_RECORD_PARSER_LOG_ENABLED -#define NFC_NDEF_RECORD_PARSER_LOG_ENABLED 0 -#endif -// NFC_NDEF_RECORD_PARSER_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NFC_NDEF_RECORD_PARSER_LOG_LEVEL -#define NFC_NDEF_RECORD_PARSER_LOG_LEVEL 3 -#endif - -// NFC_NDEF_RECORD_PARSER_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NFC_NDEF_RECORD_PARSER_INFO_COLOR -#define NFC_NDEF_RECORD_PARSER_INFO_COLOR 0 -#endif - -// - -// - -// NFC_NDEF_TEXT_RECORD_ENABLED - nfc_text_rec - Encoding data for a text record for NFC Tag - - -#ifndef NFC_NDEF_TEXT_RECORD_ENABLED -#define NFC_NDEF_TEXT_RECORD_ENABLED 0 -#endif - -// NFC_NDEF_URI_MSG_ENABLED - nfc_uri_msg - Encoding data for NDEF message with URI record for NFC Tag - - -#ifndef NFC_NDEF_URI_MSG_ENABLED -#define NFC_NDEF_URI_MSG_ENABLED 0 -#endif - -// NFC_NDEF_URI_REC_ENABLED - nfc_uri_rec - Encoding data for a URI record for NFC Tag - - -#ifndef NFC_NDEF_URI_REC_ENABLED -#define NFC_NDEF_URI_REC_ENABLED 0 -#endif - -// NFC_T2T_HAL_ENABLED - nfc_t2t_hal - Hardware Abstraction Layer for NFC library. -//========================================================== -#ifndef NFC_T2T_HAL_ENABLED -#define NFC_T2T_HAL_ENABLED 0 -#endif -// NFCT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NFCT_CONFIG_IRQ_PRIORITY -#define NFCT_CONFIG_IRQ_PRIORITY 7 -#endif - -// HAL_NFC_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef HAL_NFC_CONFIG_LOG_ENABLED -#define HAL_NFC_CONFIG_LOG_ENABLED 0 -#endif -// HAL_NFC_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef HAL_NFC_CONFIG_LOG_LEVEL -#define HAL_NFC_CONFIG_LOG_LEVEL 3 -#endif - -// HAL_NFC_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef HAL_NFC_CONFIG_INFO_COLOR -#define HAL_NFC_CONFIG_INFO_COLOR 0 -#endif - -// HAL_NFC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef HAL_NFC_CONFIG_DEBUG_COLOR -#define HAL_NFC_CONFIG_DEBUG_COLOR 0 -#endif - -// HAL_NFC_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef HAL_NFC_CONFIG_LOG_LEVEL -#define HAL_NFC_CONFIG_LOG_LEVEL 3 -#endif - -// HAL_NFC_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef HAL_NFC_CONFIG_INFO_COLOR -#define HAL_NFC_CONFIG_INFO_COLOR 0 -#endif - -// HAL_NFC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef HAL_NFC_CONFIG_DEBUG_COLOR -#define HAL_NFC_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// HAL_NFC_CONFIG_DEBUG_PIN_ENABLED - Enables pin debug in the module. -//========================================================== -#ifndef HAL_NFC_CONFIG_DEBUG_PIN_ENABLED -#define HAL_NFC_CONFIG_DEBUG_PIN_ENABLED 0 -#endif -// HAL_NFC_HCLOCK_ON_DEBUG_PIN - Pin number - -// <0=> 0 (P0.0) -// <1=> 1 (P0.1) -// <2=> 2 (P0.2) -// <3=> 3 (P0.3) -// <4=> 4 (P0.4) -// <5=> 5 (P0.5) -// <6=> 6 (P0.6) -// <7=> 7 (P0.7) -// <8=> 8 (P0.8) -// <9=> 9 (P0.9) -// <10=> 10 (P0.10) -// <11=> 11 (P0.11) -// <12=> 12 (P0.12) -// <13=> 13 (P0.13) -// <14=> 14 (P0.14) -// <15=> 15 (P0.15) -// <16=> 16 (P0.16) -// <17=> 17 (P0.17) -// <18=> 18 (P0.18) -// <19=> 19 (P0.19) -// <20=> 20 (P0.20) -// <21=> 21 (P0.21) -// <22=> 22 (P0.22) -// <23=> 23 (P0.23) -// <24=> 24 (P0.24) -// <25=> 25 (P0.25) -// <26=> 26 (P0.26) -// <27=> 27 (P0.27) -// <28=> 28 (P0.28) -// <29=> 29 (P0.29) -// <30=> 30 (P0.30) -// <31=> 31 (P0.31) -// <32=> 32 (P1.0) -// <33=> 33 (P1.1) -// <34=> 34 (P1.2) -// <35=> 35 (P1.3) -// <36=> 36 (P1.4) -// <37=> 37 (P1.5) -// <38=> 38 (P1.6) -// <39=> 39 (P1.7) -// <40=> 40 (P1.8) -// <41=> 41 (P1.9) -// <42=> 42 (P1.10) -// <43=> 43 (P1.11) -// <44=> 44 (P1.12) -// <45=> 45 (P1.13) -// <46=> 46 (P1.14) -// <47=> 47 (P1.15) -// <4294967295=> Not connected - -#ifndef HAL_NFC_HCLOCK_ON_DEBUG_PIN -#define HAL_NFC_HCLOCK_ON_DEBUG_PIN 11 -#endif - -// HAL_NFC_HCLOCK_OFF_DEBUG_PIN - Pin number - -// <0=> 0 (P0.0) -// <1=> 1 (P0.1) -// <2=> 2 (P0.2) -// <3=> 3 (P0.3) -// <4=> 4 (P0.4) -// <5=> 5 (P0.5) -// <6=> 6 (P0.6) -// <7=> 7 (P0.7) -// <8=> 8 (P0.8) -// <9=> 9 (P0.9) -// <10=> 10 (P0.10) -// <11=> 11 (P0.11) -// <12=> 12 (P0.12) -// <13=> 13 (P0.13) -// <14=> 14 (P0.14) -// <15=> 15 (P0.15) -// <16=> 16 (P0.16) -// <17=> 17 (P0.17) -// <18=> 18 (P0.18) -// <19=> 19 (P0.19) -// <20=> 20 (P0.20) -// <21=> 21 (P0.21) -// <22=> 22 (P0.22) -// <23=> 23 (P0.23) -// <24=> 24 (P0.24) -// <25=> 25 (P0.25) -// <26=> 26 (P0.26) -// <27=> 27 (P0.27) -// <28=> 28 (P0.28) -// <29=> 29 (P0.29) -// <30=> 30 (P0.30) -// <31=> 31 (P0.31) -// <32=> 32 (P1.0) -// <33=> 33 (P1.1) -// <34=> 34 (P1.2) -// <35=> 35 (P1.3) -// <36=> 36 (P1.4) -// <37=> 37 (P1.5) -// <38=> 38 (P1.6) -// <39=> 39 (P1.7) -// <40=> 40 (P1.8) -// <41=> 41 (P1.9) -// <42=> 42 (P1.10) -// <43=> 43 (P1.11) -// <44=> 44 (P1.12) -// <45=> 45 (P1.13) -// <46=> 46 (P1.14) -// <47=> 47 (P1.15) -// <4294967295=> Not connected - -#ifndef HAL_NFC_HCLOCK_OFF_DEBUG_PIN -#define HAL_NFC_HCLOCK_OFF_DEBUG_PIN 12 -#endif - -// HAL_NFC_NFC_EVENT_DEBUG_PIN - Pin number - -// <0=> 0 (P0.0) -// <1=> 1 (P0.1) -// <2=> 2 (P0.2) -// <3=> 3 (P0.3) -// <4=> 4 (P0.4) -// <5=> 5 (P0.5) -// <6=> 6 (P0.6) -// <7=> 7 (P0.7) -// <8=> 8 (P0.8) -// <9=> 9 (P0.9) -// <10=> 10 (P0.10) -// <11=> 11 (P0.11) -// <12=> 12 (P0.12) -// <13=> 13 (P0.13) -// <14=> 14 (P0.14) -// <15=> 15 (P0.15) -// <16=> 16 (P0.16) -// <17=> 17 (P0.17) -// <18=> 18 (P0.18) -// <19=> 19 (P0.19) -// <20=> 20 (P0.20) -// <21=> 21 (P0.21) -// <22=> 22 (P0.22) -// <23=> 23 (P0.23) -// <24=> 24 (P0.24) -// <25=> 25 (P0.25) -// <26=> 26 (P0.26) -// <27=> 27 (P0.27) -// <28=> 28 (P0.28) -// <29=> 29 (P0.29) -// <30=> 30 (P0.30) -// <31=> 31 (P0.31) -// <32=> 32 (P1.0) -// <33=> 33 (P1.1) -// <34=> 34 (P1.2) -// <35=> 35 (P1.3) -// <36=> 36 (P1.4) -// <37=> 37 (P1.5) -// <38=> 38 (P1.6) -// <39=> 39 (P1.7) -// <40=> 40 (P1.8) -// <41=> 41 (P1.9) -// <42=> 42 (P1.10) -// <43=> 43 (P1.11) -// <44=> 44 (P1.12) -// <45=> 45 (P1.13) -// <46=> 46 (P1.14) -// <47=> 47 (P1.15) -// <4294967295=> Not connected - -#ifndef HAL_NFC_NFC_EVENT_DEBUG_PIN -#define HAL_NFC_NFC_EVENT_DEBUG_PIN 24 -#endif - -// HAL_NFC_DETECT_EVENT_DEBUG_PIN - Pin number - -// <0=> 0 (P0.0) -// <1=> 1 (P0.1) -// <2=> 2 (P0.2) -// <3=> 3 (P0.3) -// <4=> 4 (P0.4) -// <5=> 5 (P0.5) -// <6=> 6 (P0.6) -// <7=> 7 (P0.7) -// <8=> 8 (P0.8) -// <9=> 9 (P0.9) -// <10=> 10 (P0.10) -// <11=> 11 (P0.11) -// <12=> 12 (P0.12) -// <13=> 13 (P0.13) -// <14=> 14 (P0.14) -// <15=> 15 (P0.15) -// <16=> 16 (P0.16) -// <17=> 17 (P0.17) -// <18=> 18 (P0.18) -// <19=> 19 (P0.19) -// <20=> 20 (P0.20) -// <21=> 21 (P0.21) -// <22=> 22 (P0.22) -// <23=> 23 (P0.23) -// <24=> 24 (P0.24) -// <25=> 25 (P0.25) -// <26=> 26 (P0.26) -// <27=> 27 (P0.27) -// <28=> 28 (P0.28) -// <29=> 29 (P0.29) -// <30=> 30 (P0.30) -// <31=> 31 (P0.31) -// <32=> 32 (P1.0) -// <33=> 33 (P1.1) -// <34=> 34 (P1.2) -// <35=> 35 (P1.3) -// <36=> 36 (P1.4) -// <37=> 37 (P1.5) -// <38=> 38 (P1.6) -// <39=> 39 (P1.7) -// <40=> 40 (P1.8) -// <41=> 41 (P1.9) -// <42=> 42 (P1.10) -// <43=> 43 (P1.11) -// <44=> 44 (P1.12) -// <45=> 45 (P1.13) -// <46=> 46 (P1.14) -// <47=> 47 (P1.15) -// <4294967295=> Not connected - -#ifndef HAL_NFC_DETECT_EVENT_DEBUG_PIN -#define HAL_NFC_DETECT_EVENT_DEBUG_PIN 25 -#endif - -// HAL_NFC_TIMER4_EVENT_DEBUG_PIN - Pin number - -// <0=> 0 (P0.0) -// <1=> 1 (P0.1) -// <2=> 2 (P0.2) -// <3=> 3 (P0.3) -// <4=> 4 (P0.4) -// <5=> 5 (P0.5) -// <6=> 6 (P0.6) -// <7=> 7 (P0.7) -// <8=> 8 (P0.8) -// <9=> 9 (P0.9) -// <10=> 10 (P0.10) -// <11=> 11 (P0.11) -// <12=> 12 (P0.12) -// <13=> 13 (P0.13) -// <14=> 14 (P0.14) -// <15=> 15 (P0.15) -// <16=> 16 (P0.16) -// <17=> 17 (P0.17) -// <18=> 18 (P0.18) -// <19=> 19 (P0.19) -// <20=> 20 (P0.20) -// <21=> 21 (P0.21) -// <22=> 22 (P0.22) -// <23=> 23 (P0.23) -// <24=> 24 (P0.24) -// <25=> 25 (P0.25) -// <26=> 26 (P0.26) -// <27=> 27 (P0.27) -// <28=> 28 (P0.28) -// <29=> 29 (P0.29) -// <30=> 30 (P0.30) -// <31=> 31 (P0.31) -// <32=> 32 (P1.0) -// <33=> 33 (P1.1) -// <34=> 34 (P1.2) -// <35=> 35 (P1.3) -// <36=> 36 (P1.4) -// <37=> 37 (P1.5) -// <38=> 38 (P1.6) -// <39=> 39 (P1.7) -// <40=> 40 (P1.8) -// <41=> 41 (P1.9) -// <42=> 42 (P1.10) -// <43=> 43 (P1.11) -// <44=> 44 (P1.12) -// <45=> 45 (P1.13) -// <46=> 46 (P1.14) -// <47=> 47 (P1.15) -// <4294967295=> Not connected - -#ifndef HAL_NFC_TIMER4_EVENT_DEBUG_PIN -#define HAL_NFC_TIMER4_EVENT_DEBUG_PIN 28 -#endif - -// HAL_NFC_HCLOCK_ON_DEBUG_PIN - Pin number - -// <0=> 0 (P0.0) -// <1=> 1 (P0.1) -// <2=> 2 (P0.2) -// <3=> 3 (P0.3) -// <4=> 4 (P0.4) -// <5=> 5 (P0.5) -// <6=> 6 (P0.6) -// <7=> 7 (P0.7) -// <8=> 8 (P0.8) -// <9=> 9 (P0.9) -// <10=> 10 (P0.10) -// <11=> 11 (P0.11) -// <12=> 12 (P0.12) -// <13=> 13 (P0.13) -// <14=> 14 (P0.14) -// <15=> 15 (P0.15) -// <16=> 16 (P0.16) -// <17=> 17 (P0.17) -// <18=> 18 (P0.18) -// <19=> 19 (P0.19) -// <20=> 20 (P0.20) -// <21=> 21 (P0.21) -// <22=> 22 (P0.22) -// <23=> 23 (P0.23) -// <24=> 24 (P0.24) -// <25=> 25 (P0.25) -// <26=> 26 (P0.26) -// <27=> 27 (P0.27) -// <28=> 28 (P0.28) -// <29=> 29 (P0.29) -// <30=> 30 (P0.30) -// <31=> 31 (P0.31) -// <32=> 32 (P1.0) -// <33=> 33 (P1.1) -// <34=> 34 (P1.2) -// <35=> 35 (P1.3) -// <36=> 36 (P1.4) -// <37=> 37 (P1.5) -// <38=> 38 (P1.6) -// <39=> 39 (P1.7) -// <40=> 40 (P1.8) -// <41=> 41 (P1.9) -// <42=> 42 (P1.10) -// <43=> 43 (P1.11) -// <44=> 44 (P1.12) -// <45=> 45 (P1.13) -// <46=> 46 (P1.14) -// <47=> 47 (P1.15) -// <4294967295=> Not connected - -#ifndef HAL_NFC_HCLOCK_ON_DEBUG_PIN -#define HAL_NFC_HCLOCK_ON_DEBUG_PIN 31 -#endif - -// HAL_NFC_HCLOCK_OFF_DEBUG_PIN - Pin number - -// <0=> 0 (P0.0) -// <1=> 1 (P0.1) -// <2=> 2 (P0.2) -// <3=> 3 (P0.3) -// <4=> 4 (P0.4) -// <5=> 5 (P0.5) -// <6=> 6 (P0.6) -// <7=> 7 (P0.7) -// <8=> 8 (P0.8) -// <9=> 9 (P0.9) -// <10=> 10 (P0.10) -// <11=> 11 (P0.11) -// <12=> 12 (P0.12) -// <13=> 13 (P0.13) -// <14=> 14 (P0.14) -// <15=> 15 (P0.15) -// <16=> 16 (P0.16) -// <17=> 17 (P0.17) -// <18=> 18 (P0.18) -// <19=> 19 (P0.19) -// <20=> 20 (P0.20) -// <21=> 21 (P0.21) -// <22=> 22 (P0.22) -// <23=> 23 (P0.23) -// <24=> 24 (P0.24) -// <25=> 25 (P0.25) -// <26=> 26 (P0.26) -// <27=> 27 (P0.27) -// <28=> 28 (P0.28) -// <29=> 29 (P0.29) -// <30=> 30 (P0.30) -// <31=> 31 (P0.31) -// <32=> 32 (P1.0) -// <33=> 33 (P1.1) -// <34=> 34 (P1.2) -// <35=> 35 (P1.3) -// <36=> 36 (P1.4) -// <37=> 37 (P1.5) -// <38=> 38 (P1.6) -// <39=> 39 (P1.7) -// <40=> 40 (P1.8) -// <41=> 41 (P1.9) -// <42=> 42 (P1.10) -// <43=> 43 (P1.11) -// <44=> 44 (P1.12) -// <45=> 45 (P1.13) -// <46=> 46 (P1.14) -// <47=> 47 (P1.15) -// <4294967295=> Not connected - -#ifndef HAL_NFC_HCLOCK_OFF_DEBUG_PIN -#define HAL_NFC_HCLOCK_OFF_DEBUG_PIN 31 -#endif - -// HAL_NFC_NFC_EVENT_DEBUG_PIN - Pin number - -// <0=> 0 (P0.0) -// <1=> 1 (P0.1) -// <2=> 2 (P0.2) -// <3=> 3 (P0.3) -// <4=> 4 (P0.4) -// <5=> 5 (P0.5) -// <6=> 6 (P0.6) -// <7=> 7 (P0.7) -// <8=> 8 (P0.8) -// <9=> 9 (P0.9) -// <10=> 10 (P0.10) -// <11=> 11 (P0.11) -// <12=> 12 (P0.12) -// <13=> 13 (P0.13) -// <14=> 14 (P0.14) -// <15=> 15 (P0.15) -// <16=> 16 (P0.16) -// <17=> 17 (P0.17) -// <18=> 18 (P0.18) -// <19=> 19 (P0.19) -// <20=> 20 (P0.20) -// <21=> 21 (P0.21) -// <22=> 22 (P0.22) -// <23=> 23 (P0.23) -// <24=> 24 (P0.24) -// <25=> 25 (P0.25) -// <26=> 26 (P0.26) -// <27=> 27 (P0.27) -// <28=> 28 (P0.28) -// <29=> 29 (P0.29) -// <30=> 30 (P0.30) -// <31=> 31 (P0.31) -// <32=> 32 (P1.0) -// <33=> 33 (P1.1) -// <34=> 34 (P1.2) -// <35=> 35 (P1.3) -// <36=> 36 (P1.4) -// <37=> 37 (P1.5) -// <38=> 38 (P1.6) -// <39=> 39 (P1.7) -// <40=> 40 (P1.8) -// <41=> 41 (P1.9) -// <42=> 42 (P1.10) -// <43=> 43 (P1.11) -// <44=> 44 (P1.12) -// <45=> 45 (P1.13) -// <46=> 46 (P1.14) -// <47=> 47 (P1.15) -// <4294967295=> Not connected - -#ifndef HAL_NFC_NFC_EVENT_DEBUG_PIN -#define HAL_NFC_NFC_EVENT_DEBUG_PIN 31 -#endif - -// HAL_NFC_DETECT_EVENT_DEBUG_PIN - Pin number - -// <0=> 0 (P0.0) -// <1=> 1 (P0.1) -// <2=> 2 (P0.2) -// <3=> 3 (P0.3) -// <4=> 4 (P0.4) -// <5=> 5 (P0.5) -// <6=> 6 (P0.6) -// <7=> 7 (P0.7) -// <8=> 8 (P0.8) -// <9=> 9 (P0.9) -// <10=> 10 (P0.10) -// <11=> 11 (P0.11) -// <12=> 12 (P0.12) -// <13=> 13 (P0.13) -// <14=> 14 (P0.14) -// <15=> 15 (P0.15) -// <16=> 16 (P0.16) -// <17=> 17 (P0.17) -// <18=> 18 (P0.18) -// <19=> 19 (P0.19) -// <20=> 20 (P0.20) -// <21=> 21 (P0.21) -// <22=> 22 (P0.22) -// <23=> 23 (P0.23) -// <24=> 24 (P0.24) -// <25=> 25 (P0.25) -// <26=> 26 (P0.26) -// <27=> 27 (P0.27) -// <28=> 28 (P0.28) -// <29=> 29 (P0.29) -// <30=> 30 (P0.30) -// <31=> 31 (P0.31) -// <32=> 32 (P1.0) -// <33=> 33 (P1.1) -// <34=> 34 (P1.2) -// <35=> 35 (P1.3) -// <36=> 36 (P1.4) -// <37=> 37 (P1.5) -// <38=> 38 (P1.6) -// <39=> 39 (P1.7) -// <40=> 40 (P1.8) -// <41=> 41 (P1.9) -// <42=> 42 (P1.10) -// <43=> 43 (P1.11) -// <44=> 44 (P1.12) -// <45=> 45 (P1.13) -// <46=> 46 (P1.14) -// <47=> 47 (P1.15) -// <4294967295=> Not connected - -#ifndef HAL_NFC_DETECT_EVENT_DEBUG_PIN -#define HAL_NFC_DETECT_EVENT_DEBUG_PIN 31 -#endif - -// HAL_NFC_TIMER4_EVENT_DEBUG_PIN - Pin number - -// <0=> 0 (P0.0) -// <1=> 1 (P0.1) -// <2=> 2 (P0.2) -// <3=> 3 (P0.3) -// <4=> 4 (P0.4) -// <5=> 5 (P0.5) -// <6=> 6 (P0.6) -// <7=> 7 (P0.7) -// <8=> 8 (P0.8) -// <9=> 9 (P0.9) -// <10=> 10 (P0.10) -// <11=> 11 (P0.11) -// <12=> 12 (P0.12) -// <13=> 13 (P0.13) -// <14=> 14 (P0.14) -// <15=> 15 (P0.15) -// <16=> 16 (P0.16) -// <17=> 17 (P0.17) -// <18=> 18 (P0.18) -// <19=> 19 (P0.19) -// <20=> 20 (P0.20) -// <21=> 21 (P0.21) -// <22=> 22 (P0.22) -// <23=> 23 (P0.23) -// <24=> 24 (P0.24) -// <25=> 25 (P0.25) -// <26=> 26 (P0.26) -// <27=> 27 (P0.27) -// <28=> 28 (P0.28) -// <29=> 29 (P0.29) -// <30=> 30 (P0.30) -// <31=> 31 (P0.31) -// <32=> 32 (P1.0) -// <33=> 33 (P1.1) -// <34=> 34 (P1.2) -// <35=> 35 (P1.3) -// <36=> 36 (P1.4) -// <37=> 37 (P1.5) -// <38=> 38 (P1.6) -// <39=> 39 (P1.7) -// <40=> 40 (P1.8) -// <41=> 41 (P1.9) -// <42=> 42 (P1.10) -// <43=> 43 (P1.11) -// <44=> 44 (P1.12) -// <45=> 45 (P1.13) -// <46=> 46 (P1.14) -// <47=> 47 (P1.15) -// <4294967295=> Not connected - -#ifndef HAL_NFC_TIMER4_EVENT_DEBUG_PIN -#define HAL_NFC_TIMER4_EVENT_DEBUG_PIN 31 -#endif - -// - -// - -// NFC_T2T_PARSER_ENABLED - nfc_type_2_tag_parser - Parser for decoding Type 2 Tag data -//========================================================== -#ifndef NFC_T2T_PARSER_ENABLED -#define NFC_T2T_PARSER_ENABLED 0 -#endif -// NFC_T2T_PARSER_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NFC_T2T_PARSER_LOG_ENABLED -#define NFC_T2T_PARSER_LOG_ENABLED 0 -#endif -// NFC_T2T_PARSER_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NFC_T2T_PARSER_LOG_LEVEL -#define NFC_T2T_PARSER_LOG_LEVEL 3 -#endif - -// NFC_T2T_PARSER_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NFC_T2T_PARSER_INFO_COLOR -#define NFC_T2T_PARSER_INFO_COLOR 0 -#endif - -// - -// - -// NFC_T4T_APDU_ENABLED - nfc_t4t_apdu - APDU encoder/decoder for Type 4 Tag -//========================================================== -#ifndef NFC_T4T_APDU_ENABLED -#define NFC_T4T_APDU_ENABLED 0 -#endif -// NFC_T4T_APDU_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NFC_T4T_APDU_LOG_ENABLED -#define NFC_T4T_APDU_LOG_ENABLED 0 -#endif -// NFC_T4T_APDU_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NFC_T4T_APDU_LOG_LEVEL -#define NFC_T4T_APDU_LOG_LEVEL 3 -#endif - -// NFC_T4T_APDU_LOG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NFC_T4T_APDU_LOG_COLOR -#define NFC_T4T_APDU_LOG_COLOR 0 -#endif - -// - -// - -// NFC_T4T_CC_FILE_PARSER_ENABLED - nfc_t4t_cc_file - Capability Container file for Type 4 Tag -//========================================================== -#ifndef NFC_T4T_CC_FILE_PARSER_ENABLED -#define NFC_T4T_CC_FILE_PARSER_ENABLED 0 -#endif -// NFC_T4T_CC_FILE_PARSER_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NFC_T4T_CC_FILE_PARSER_LOG_ENABLED -#define NFC_T4T_CC_FILE_PARSER_LOG_ENABLED 0 -#endif -// NFC_T4T_CC_FILE_PARSER_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NFC_T4T_CC_FILE_PARSER_LOG_LEVEL -#define NFC_T4T_CC_FILE_PARSER_LOG_LEVEL 3 -#endif - -// NFC_T4T_CC_FILE_PARSER_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NFC_T4T_CC_FILE_PARSER_INFO_COLOR -#define NFC_T4T_CC_FILE_PARSER_INFO_COLOR 0 -#endif - -// - -// - -// NFC_T4T_HAL_ENABLED - nfc_t4t_hal - Hardware Abstraction Layer for NFC library. -//========================================================== -#ifndef NFC_T4T_HAL_ENABLED -#define NFC_T4T_HAL_ENABLED 0 -#endif -// NFCT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NFCT_CONFIG_IRQ_PRIORITY -#define NFCT_CONFIG_IRQ_PRIORITY 7 -#endif - -// HAL_NFC_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef HAL_NFC_CONFIG_LOG_ENABLED -#define HAL_NFC_CONFIG_LOG_ENABLED 0 -#endif -// HAL_NFC_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef HAL_NFC_CONFIG_LOG_LEVEL -#define HAL_NFC_CONFIG_LOG_LEVEL 3 -#endif - -// HAL_NFC_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef HAL_NFC_CONFIG_INFO_COLOR -#define HAL_NFC_CONFIG_INFO_COLOR 0 -#endif - -// HAL_NFC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef HAL_NFC_CONFIG_DEBUG_COLOR -#define HAL_NFC_CONFIG_DEBUG_COLOR 0 -#endif - -// HAL_NFC_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef HAL_NFC_CONFIG_LOG_LEVEL -#define HAL_NFC_CONFIG_LOG_LEVEL 3 -#endif - -// HAL_NFC_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef HAL_NFC_CONFIG_INFO_COLOR -#define HAL_NFC_CONFIG_INFO_COLOR 0 -#endif - -// HAL_NFC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef HAL_NFC_CONFIG_DEBUG_COLOR -#define HAL_NFC_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// HAL_NFC_CONFIG_DEBUG_PIN_ENABLED - Enables pin debug in the module. -//========================================================== -#ifndef HAL_NFC_CONFIG_DEBUG_PIN_ENABLED -#define HAL_NFC_CONFIG_DEBUG_PIN_ENABLED 0 -#endif -// HAL_NFC_HCLOCK_ON_DEBUG_PIN - Pin number - -// <0=> 0 (P0.0) -// <1=> 1 (P0.1) -// <2=> 2 (P0.2) -// <3=> 3 (P0.3) -// <4=> 4 (P0.4) -// <5=> 5 (P0.5) -// <6=> 6 (P0.6) -// <7=> 7 (P0.7) -// <8=> 8 (P0.8) -// <9=> 9 (P0.9) -// <10=> 10 (P0.10) -// <11=> 11 (P0.11) -// <12=> 12 (P0.12) -// <13=> 13 (P0.13) -// <14=> 14 (P0.14) -// <15=> 15 (P0.15) -// <16=> 16 (P0.16) -// <17=> 17 (P0.17) -// <18=> 18 (P0.18) -// <19=> 19 (P0.19) -// <20=> 20 (P0.20) -// <21=> 21 (P0.21) -// <22=> 22 (P0.22) -// <23=> 23 (P0.23) -// <24=> 24 (P0.24) -// <25=> 25 (P0.25) -// <26=> 26 (P0.26) -// <27=> 27 (P0.27) -// <28=> 28 (P0.28) -// <29=> 29 (P0.29) -// <30=> 30 (P0.30) -// <31=> 31 (P0.31) -// <32=> 32 (P1.0) -// <33=> 33 (P1.1) -// <34=> 34 (P1.2) -// <35=> 35 (P1.3) -// <36=> 36 (P1.4) -// <37=> 37 (P1.5) -// <38=> 38 (P1.6) -// <39=> 39 (P1.7) -// <40=> 40 (P1.8) -// <41=> 41 (P1.9) -// <42=> 42 (P1.10) -// <43=> 43 (P1.11) -// <44=> 44 (P1.12) -// <45=> 45 (P1.13) -// <46=> 46 (P1.14) -// <47=> 47 (P1.15) -// <4294967295=> Not connected - -#ifndef HAL_NFC_HCLOCK_ON_DEBUG_PIN -#define HAL_NFC_HCLOCK_ON_DEBUG_PIN 31 -#endif - -// HAL_NFC_HCLOCK_OFF_DEBUG_PIN - Pin number - -// <0=> 0 (P0.0) -// <1=> 1 (P0.1) -// <2=> 2 (P0.2) -// <3=> 3 (P0.3) -// <4=> 4 (P0.4) -// <5=> 5 (P0.5) -// <6=> 6 (P0.6) -// <7=> 7 (P0.7) -// <8=> 8 (P0.8) -// <9=> 9 (P0.9) -// <10=> 10 (P0.10) -// <11=> 11 (P0.11) -// <12=> 12 (P0.12) -// <13=> 13 (P0.13) -// <14=> 14 (P0.14) -// <15=> 15 (P0.15) -// <16=> 16 (P0.16) -// <17=> 17 (P0.17) -// <18=> 18 (P0.18) -// <19=> 19 (P0.19) -// <20=> 20 (P0.20) -// <21=> 21 (P0.21) -// <22=> 22 (P0.22) -// <23=> 23 (P0.23) -// <24=> 24 (P0.24) -// <25=> 25 (P0.25) -// <26=> 26 (P0.26) -// <27=> 27 (P0.27) -// <28=> 28 (P0.28) -// <29=> 29 (P0.29) -// <30=> 30 (P0.30) -// <31=> 31 (P0.31) -// <32=> 32 (P1.0) -// <33=> 33 (P1.1) -// <34=> 34 (P1.2) -// <35=> 35 (P1.3) -// <36=> 36 (P1.4) -// <37=> 37 (P1.5) -// <38=> 38 (P1.6) -// <39=> 39 (P1.7) -// <40=> 40 (P1.8) -// <41=> 41 (P1.9) -// <42=> 42 (P1.10) -// <43=> 43 (P1.11) -// <44=> 44 (P1.12) -// <45=> 45 (P1.13) -// <46=> 46 (P1.14) -// <47=> 47 (P1.15) -// <4294967295=> Not connected - -#ifndef HAL_NFC_HCLOCK_OFF_DEBUG_PIN -#define HAL_NFC_HCLOCK_OFF_DEBUG_PIN 31 -#endif - -// HAL_NFC_NFC_EVENT_DEBUG_PIN - Pin number - -// <0=> 0 (P0.0) -// <1=> 1 (P0.1) -// <2=> 2 (P0.2) -// <3=> 3 (P0.3) -// <4=> 4 (P0.4) -// <5=> 5 (P0.5) -// <6=> 6 (P0.6) -// <7=> 7 (P0.7) -// <8=> 8 (P0.8) -// <9=> 9 (P0.9) -// <10=> 10 (P0.10) -// <11=> 11 (P0.11) -// <12=> 12 (P0.12) -// <13=> 13 (P0.13) -// <14=> 14 (P0.14) -// <15=> 15 (P0.15) -// <16=> 16 (P0.16) -// <17=> 17 (P0.17) -// <18=> 18 (P0.18) -// <19=> 19 (P0.19) -// <20=> 20 (P0.20) -// <21=> 21 (P0.21) -// <22=> 22 (P0.22) -// <23=> 23 (P0.23) -// <24=> 24 (P0.24) -// <25=> 25 (P0.25) -// <26=> 26 (P0.26) -// <27=> 27 (P0.27) -// <28=> 28 (P0.28) -// <29=> 29 (P0.29) -// <30=> 30 (P0.30) -// <31=> 31 (P0.31) -// <32=> 32 (P1.0) -// <33=> 33 (P1.1) -// <34=> 34 (P1.2) -// <35=> 35 (P1.3) -// <36=> 36 (P1.4) -// <37=> 37 (P1.5) -// <38=> 38 (P1.6) -// <39=> 39 (P1.7) -// <40=> 40 (P1.8) -// <41=> 41 (P1.9) -// <42=> 42 (P1.10) -// <43=> 43 (P1.11) -// <44=> 44 (P1.12) -// <45=> 45 (P1.13) -// <46=> 46 (P1.14) -// <47=> 47 (P1.15) -// <4294967295=> Not connected - -#ifndef HAL_NFC_NFC_EVENT_DEBUG_PIN -#define HAL_NFC_NFC_EVENT_DEBUG_PIN 31 -#endif - -// HAL_NFC_DETECT_EVENT_DEBUG_PIN - Pin number - -// <0=> 0 (P0.0) -// <1=> 1 (P0.1) -// <2=> 2 (P0.2) -// <3=> 3 (P0.3) -// <4=> 4 (P0.4) -// <5=> 5 (P0.5) -// <6=> 6 (P0.6) -// <7=> 7 (P0.7) -// <8=> 8 (P0.8) -// <9=> 9 (P0.9) -// <10=> 10 (P0.10) -// <11=> 11 (P0.11) -// <12=> 12 (P0.12) -// <13=> 13 (P0.13) -// <14=> 14 (P0.14) -// <15=> 15 (P0.15) -// <16=> 16 (P0.16) -// <17=> 17 (P0.17) -// <18=> 18 (P0.18) -// <19=> 19 (P0.19) -// <20=> 20 (P0.20) -// <21=> 21 (P0.21) -// <22=> 22 (P0.22) -// <23=> 23 (P0.23) -// <24=> 24 (P0.24) -// <25=> 25 (P0.25) -// <26=> 26 (P0.26) -// <27=> 27 (P0.27) -// <28=> 28 (P0.28) -// <29=> 29 (P0.29) -// <30=> 30 (P0.30) -// <31=> 31 (P0.31) -// <32=> 32 (P1.0) -// <33=> 33 (P1.1) -// <34=> 34 (P1.2) -// <35=> 35 (P1.3) -// <36=> 36 (P1.4) -// <37=> 37 (P1.5) -// <38=> 38 (P1.6) -// <39=> 39 (P1.7) -// <40=> 40 (P1.8) -// <41=> 41 (P1.9) -// <42=> 42 (P1.10) -// <43=> 43 (P1.11) -// <44=> 44 (P1.12) -// <45=> 45 (P1.13) -// <46=> 46 (P1.14) -// <47=> 47 (P1.15) -// <4294967295=> Not connected - -#ifndef HAL_NFC_DETECT_EVENT_DEBUG_PIN -#define HAL_NFC_DETECT_EVENT_DEBUG_PIN 31 -#endif - -// HAL_NFC_TIMER4_EVENT_DEBUG_PIN - Pin number - -// <0=> 0 (P0.0) -// <1=> 1 (P0.1) -// <2=> 2 (P0.2) -// <3=> 3 (P0.3) -// <4=> 4 (P0.4) -// <5=> 5 (P0.5) -// <6=> 6 (P0.6) -// <7=> 7 (P0.7) -// <8=> 8 (P0.8) -// <9=> 9 (P0.9) -// <10=> 10 (P0.10) -// <11=> 11 (P0.11) -// <12=> 12 (P0.12) -// <13=> 13 (P0.13) -// <14=> 14 (P0.14) -// <15=> 15 (P0.15) -// <16=> 16 (P0.16) -// <17=> 17 (P0.17) -// <18=> 18 (P0.18) -// <19=> 19 (P0.19) -// <20=> 20 (P0.20) -// <21=> 21 (P0.21) -// <22=> 22 (P0.22) -// <23=> 23 (P0.23) -// <24=> 24 (P0.24) -// <25=> 25 (P0.25) -// <26=> 26 (P0.26) -// <27=> 27 (P0.27) -// <28=> 28 (P0.28) -// <29=> 29 (P0.29) -// <30=> 30 (P0.30) -// <31=> 31 (P0.31) -// <32=> 32 (P1.0) -// <33=> 33 (P1.1) -// <34=> 34 (P1.2) -// <35=> 35 (P1.3) -// <36=> 36 (P1.4) -// <37=> 37 (P1.5) -// <38=> 38 (P1.6) -// <39=> 39 (P1.7) -// <40=> 40 (P1.8) -// <41=> 41 (P1.9) -// <42=> 42 (P1.10) -// <43=> 43 (P1.11) -// <44=> 44 (P1.12) -// <45=> 45 (P1.13) -// <46=> 46 (P1.14) -// <47=> 47 (P1.15) -// <4294967295=> Not connected - -#ifndef HAL_NFC_TIMER4_EVENT_DEBUG_PIN -#define HAL_NFC_TIMER4_EVENT_DEBUG_PIN 31 -#endif - -// HAL_NFC_HCLOCK_ON_DEBUG_PIN - Pin number - -// <0=> 0 (P0.0) -// <1=> 1 (P0.1) -// <2=> 2 (P0.2) -// <3=> 3 (P0.3) -// <4=> 4 (P0.4) -// <5=> 5 (P0.5) -// <6=> 6 (P0.6) -// <7=> 7 (P0.7) -// <8=> 8 (P0.8) -// <9=> 9 (P0.9) -// <10=> 10 (P0.10) -// <11=> 11 (P0.11) -// <12=> 12 (P0.12) -// <13=> 13 (P0.13) -// <14=> 14 (P0.14) -// <15=> 15 (P0.15) -// <16=> 16 (P0.16) -// <17=> 17 (P0.17) -// <18=> 18 (P0.18) -// <19=> 19 (P0.19) -// <20=> 20 (P0.20) -// <21=> 21 (P0.21) -// <22=> 22 (P0.22) -// <23=> 23 (P0.23) -// <24=> 24 (P0.24) -// <25=> 25 (P0.25) -// <26=> 26 (P0.26) -// <27=> 27 (P0.27) -// <28=> 28 (P0.28) -// <29=> 29 (P0.29) -// <30=> 30 (P0.30) -// <31=> 31 (P0.31) -// <32=> 32 (P1.0) -// <33=> 33 (P1.1) -// <34=> 34 (P1.2) -// <35=> 35 (P1.3) -// <36=> 36 (P1.4) -// <37=> 37 (P1.5) -// <38=> 38 (P1.6) -// <39=> 39 (P1.7) -// <40=> 40 (P1.8) -// <41=> 41 (P1.9) -// <42=> 42 (P1.10) -// <43=> 43 (P1.11) -// <44=> 44 (P1.12) -// <45=> 45 (P1.13) -// <46=> 46 (P1.14) -// <47=> 47 (P1.15) -// <4294967295=> Not connected - -#ifndef HAL_NFC_HCLOCK_ON_DEBUG_PIN -#define HAL_NFC_HCLOCK_ON_DEBUG_PIN 31 -#endif - -// HAL_NFC_HCLOCK_OFF_DEBUG_PIN - Pin number - -// <0=> 0 (P0.0) -// <1=> 1 (P0.1) -// <2=> 2 (P0.2) -// <3=> 3 (P0.3) -// <4=> 4 (P0.4) -// <5=> 5 (P0.5) -// <6=> 6 (P0.6) -// <7=> 7 (P0.7) -// <8=> 8 (P0.8) -// <9=> 9 (P0.9) -// <10=> 10 (P0.10) -// <11=> 11 (P0.11) -// <12=> 12 (P0.12) -// <13=> 13 (P0.13) -// <14=> 14 (P0.14) -// <15=> 15 (P0.15) -// <16=> 16 (P0.16) -// <17=> 17 (P0.17) -// <18=> 18 (P0.18) -// <19=> 19 (P0.19) -// <20=> 20 (P0.20) -// <21=> 21 (P0.21) -// <22=> 22 (P0.22) -// <23=> 23 (P0.23) -// <24=> 24 (P0.24) -// <25=> 25 (P0.25) -// <26=> 26 (P0.26) -// <27=> 27 (P0.27) -// <28=> 28 (P0.28) -// <29=> 29 (P0.29) -// <30=> 30 (P0.30) -// <31=> 31 (P0.31) -// <32=> 32 (P1.0) -// <33=> 33 (P1.1) -// <34=> 34 (P1.2) -// <35=> 35 (P1.3) -// <36=> 36 (P1.4) -// <37=> 37 (P1.5) -// <38=> 38 (P1.6) -// <39=> 39 (P1.7) -// <40=> 40 (P1.8) -// <41=> 41 (P1.9) -// <42=> 42 (P1.10) -// <43=> 43 (P1.11) -// <44=> 44 (P1.12) -// <45=> 45 (P1.13) -// <46=> 46 (P1.14) -// <47=> 47 (P1.15) -// <4294967295=> Not connected - -#ifndef HAL_NFC_HCLOCK_OFF_DEBUG_PIN -#define HAL_NFC_HCLOCK_OFF_DEBUG_PIN 31 -#endif - -// HAL_NFC_NFC_EVENT_DEBUG_PIN - Pin number - -// <0=> 0 (P0.0) -// <1=> 1 (P0.1) -// <2=> 2 (P0.2) -// <3=> 3 (P0.3) -// <4=> 4 (P0.4) -// <5=> 5 (P0.5) -// <6=> 6 (P0.6) -// <7=> 7 (P0.7) -// <8=> 8 (P0.8) -// <9=> 9 (P0.9) -// <10=> 10 (P0.10) -// <11=> 11 (P0.11) -// <12=> 12 (P0.12) -// <13=> 13 (P0.13) -// <14=> 14 (P0.14) -// <15=> 15 (P0.15) -// <16=> 16 (P0.16) -// <17=> 17 (P0.17) -// <18=> 18 (P0.18) -// <19=> 19 (P0.19) -// <20=> 20 (P0.20) -// <21=> 21 (P0.21) -// <22=> 22 (P0.22) -// <23=> 23 (P0.23) -// <24=> 24 (P0.24) -// <25=> 25 (P0.25) -// <26=> 26 (P0.26) -// <27=> 27 (P0.27) -// <28=> 28 (P0.28) -// <29=> 29 (P0.29) -// <30=> 30 (P0.30) -// <31=> 31 (P0.31) -// <32=> 32 (P1.0) -// <33=> 33 (P1.1) -// <34=> 34 (P1.2) -// <35=> 35 (P1.3) -// <36=> 36 (P1.4) -// <37=> 37 (P1.5) -// <38=> 38 (P1.6) -// <39=> 39 (P1.7) -// <40=> 40 (P1.8) -// <41=> 41 (P1.9) -// <42=> 42 (P1.10) -// <43=> 43 (P1.11) -// <44=> 44 (P1.12) -// <45=> 45 (P1.13) -// <46=> 46 (P1.14) -// <47=> 47 (P1.15) -// <4294967295=> Not connected - -#ifndef HAL_NFC_NFC_EVENT_DEBUG_PIN -#define HAL_NFC_NFC_EVENT_DEBUG_PIN 31 -#endif - -// HAL_NFC_DETECT_EVENT_DEBUG_PIN - Pin number - -// <0=> 0 (P0.0) -// <1=> 1 (P0.1) -// <2=> 2 (P0.2) -// <3=> 3 (P0.3) -// <4=> 4 (P0.4) -// <5=> 5 (P0.5) -// <6=> 6 (P0.6) -// <7=> 7 (P0.7) -// <8=> 8 (P0.8) -// <9=> 9 (P0.9) -// <10=> 10 (P0.10) -// <11=> 11 (P0.11) -// <12=> 12 (P0.12) -// <13=> 13 (P0.13) -// <14=> 14 (P0.14) -// <15=> 15 (P0.15) -// <16=> 16 (P0.16) -// <17=> 17 (P0.17) -// <18=> 18 (P0.18) -// <19=> 19 (P0.19) -// <20=> 20 (P0.20) -// <21=> 21 (P0.21) -// <22=> 22 (P0.22) -// <23=> 23 (P0.23) -// <24=> 24 (P0.24) -// <25=> 25 (P0.25) -// <26=> 26 (P0.26) -// <27=> 27 (P0.27) -// <28=> 28 (P0.28) -// <29=> 29 (P0.29) -// <30=> 30 (P0.30) -// <31=> 31 (P0.31) -// <32=> 32 (P1.0) -// <33=> 33 (P1.1) -// <34=> 34 (P1.2) -// <35=> 35 (P1.3) -// <36=> 36 (P1.4) -// <37=> 37 (P1.5) -// <38=> 38 (P1.6) -// <39=> 39 (P1.7) -// <40=> 40 (P1.8) -// <41=> 41 (P1.9) -// <42=> 42 (P1.10) -// <43=> 43 (P1.11) -// <44=> 44 (P1.12) -// <45=> 45 (P1.13) -// <46=> 46 (P1.14) -// <47=> 47 (P1.15) -// <4294967295=> Not connected - -#ifndef HAL_NFC_DETECT_EVENT_DEBUG_PIN -#define HAL_NFC_DETECT_EVENT_DEBUG_PIN 31 -#endif - -// HAL_NFC_TIMER4_EVENT_DEBUG_PIN - Pin number - -// <0=> 0 (P0.0) -// <1=> 1 (P0.1) -// <2=> 2 (P0.2) -// <3=> 3 (P0.3) -// <4=> 4 (P0.4) -// <5=> 5 (P0.5) -// <6=> 6 (P0.6) -// <7=> 7 (P0.7) -// <8=> 8 (P0.8) -// <9=> 9 (P0.9) -// <10=> 10 (P0.10) -// <11=> 11 (P0.11) -// <12=> 12 (P0.12) -// <13=> 13 (P0.13) -// <14=> 14 (P0.14) -// <15=> 15 (P0.15) -// <16=> 16 (P0.16) -// <17=> 17 (P0.17) -// <18=> 18 (P0.18) -// <19=> 19 (P0.19) -// <20=> 20 (P0.20) -// <21=> 21 (P0.21) -// <22=> 22 (P0.22) -// <23=> 23 (P0.23) -// <24=> 24 (P0.24) -// <25=> 25 (P0.25) -// <26=> 26 (P0.26) -// <27=> 27 (P0.27) -// <28=> 28 (P0.28) -// <29=> 29 (P0.29) -// <30=> 30 (P0.30) -// <31=> 31 (P0.31) -// <32=> 32 (P1.0) -// <33=> 33 (P1.1) -// <34=> 34 (P1.2) -// <35=> 35 (P1.3) -// <36=> 36 (P1.4) -// <37=> 37 (P1.5) -// <38=> 38 (P1.6) -// <39=> 39 (P1.7) -// <40=> 40 (P1.8) -// <41=> 41 (P1.9) -// <42=> 42 (P1.10) -// <43=> 43 (P1.11) -// <44=> 44 (P1.12) -// <45=> 45 (P1.13) -// <46=> 46 (P1.14) -// <47=> 47 (P1.15) -// <4294967295=> Not connected - -#ifndef HAL_NFC_TIMER4_EVENT_DEBUG_PIN -#define HAL_NFC_TIMER4_EVENT_DEBUG_PIN 31 -#endif - -// - -// - -// NFC_T4T_HL_DETECTION_PROCEDURES_ENABLED - nfc_t4t_hl_detection_procedures - NDEF Detection Procedure for Type 4 Tag -//========================================================== -#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_ENABLED -#define NFC_T4T_HL_DETECTION_PROCEDURES_ENABLED 0 -#endif -// NFC_T4T_HL_DETECTION_PROCEDURES_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_LOG_ENABLED -#define NFC_T4T_HL_DETECTION_PROCEDURES_LOG_ENABLED 0 -#endif -// NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL -#define NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL 3 -#endif - -// NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR -#define NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR 0 -#endif - -// - -// APDU_BUFF_SIZE - Size (in bytes) of the buffer for APDU storage -#ifndef APDU_BUFF_SIZE -#define APDU_BUFF_SIZE 250 -#endif - -// CC_STORAGE_BUFF_SIZE - Size (in bytes) of the buffer for CC file storage -#ifndef CC_STORAGE_BUFF_SIZE -#define CC_STORAGE_BUFF_SIZE 64 -#endif - -// - -// NFC_T4T_TLV_BLOCK_PARSER_ENABLED - nfc_t4t_tlv_block - TLV block for Type 4 Tag -//========================================================== -#ifndef NFC_T4T_TLV_BLOCK_PARSER_ENABLED -#define NFC_T4T_TLV_BLOCK_PARSER_ENABLED 0 -#endif -// NFC_T4T_TLV_BLOCK_PARSER_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NFC_T4T_TLV_BLOCK_PARSER_LOG_ENABLED -#define NFC_T4T_TLV_BLOCK_PARSER_LOG_ENABLED 0 -#endif -// NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL -#define NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL 3 -#endif - -// NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR -#define NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR 0 -#endif - -// - -// - -// -//========================================================== - -// nRF_SoftDevice - -//========================================================== -// NRF_SDH_BLE_ENABLED - nrf_sdh_ble - SoftDevice BLE event handler -//========================================================== -#ifndef NRF_SDH_BLE_ENABLED -#define NRF_SDH_BLE_ENABLED 0 -#endif -// BLE Stack configuration - Stack configuration parameters - -// The SoftDevice handler will configure the stack with these parameters when calling @ref nrf_sdh_ble_default_cfg_set. -// Other libraries might depend on these values; keep them up-to-date even if you are not explicitely calling @ref nrf_sdh_ble_default_cfg_set. -//========================================================== -// NRF_SDH_BLE_GAP_DATA_LENGTH <27-251> - - -// Requested BLE GAP data length to be negotiated. - -#ifndef NRF_SDH_BLE_GAP_DATA_LENGTH -#define NRF_SDH_BLE_GAP_DATA_LENGTH 27 -#endif - -// NRF_SDH_BLE_PERIPHERAL_LINK_COUNT - Maximum number of peripheral links. -#ifndef NRF_SDH_BLE_PERIPHERAL_LINK_COUNT -#define NRF_SDH_BLE_PERIPHERAL_LINK_COUNT 0 -#endif - -// NRF_SDH_BLE_CENTRAL_LINK_COUNT - Maximum number of central links. -#ifndef NRF_SDH_BLE_CENTRAL_LINK_COUNT -#define NRF_SDH_BLE_CENTRAL_LINK_COUNT 0 -#endif - -// NRF_SDH_BLE_TOTAL_LINK_COUNT - Total link count. -// Maximum number of total concurrent connections using the default configuration. - -#ifndef NRF_SDH_BLE_TOTAL_LINK_COUNT -#define NRF_SDH_BLE_TOTAL_LINK_COUNT 1 -#endif - -// NRF_SDH_BLE_GAP_EVENT_LENGTH - GAP event length. -// The time set aside for this connection on every connection interval in 1.25 ms units. - -#ifndef NRF_SDH_BLE_GAP_EVENT_LENGTH -#define NRF_SDH_BLE_GAP_EVENT_LENGTH 6 -#endif - -// NRF_SDH_BLE_GATT_MAX_MTU_SIZE - Static maximum MTU size. -#ifndef NRF_SDH_BLE_GATT_MAX_MTU_SIZE -#define NRF_SDH_BLE_GATT_MAX_MTU_SIZE 23 -#endif - -// NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE - Attribute Table size in bytes. The size must be a multiple of 4. -#ifndef NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE -#define NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE 1408 -#endif - -// NRF_SDH_BLE_VS_UUID_COUNT - The number of vendor-specific UUIDs. -#ifndef NRF_SDH_BLE_VS_UUID_COUNT -#define NRF_SDH_BLE_VS_UUID_COUNT 0 -#endif - -// NRF_SDH_BLE_SERVICE_CHANGED - Include the Service Changed characteristic in the Attribute Table. - - -#ifndef NRF_SDH_BLE_SERVICE_CHANGED -#define NRF_SDH_BLE_SERVICE_CHANGED 0 -#endif - -// -//========================================================== - -// BLE Observers - Observers and priority levels - -//========================================================== -// NRF_SDH_BLE_OBSERVER_PRIO_LEVELS - Total number of priority levels for BLE observers. -// This setting configures the number of priority levels available for BLE event handlers. -// The priority level of a handler determines the order in which it receives events, with respect to other handlers. - -#ifndef NRF_SDH_BLE_OBSERVER_PRIO_LEVELS -#define NRF_SDH_BLE_OBSERVER_PRIO_LEVELS 4 -#endif - -// BLE Observers priorities - Invididual priorities - -//========================================================== -// BLE_ADV_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Advertising module. - -#ifndef BLE_ADV_BLE_OBSERVER_PRIO -#define BLE_ADV_BLE_OBSERVER_PRIO 1 -#endif - -// BLE_ANCS_C_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Apple Notification Service Client. - -#ifndef BLE_ANCS_C_BLE_OBSERVER_PRIO -#define BLE_ANCS_C_BLE_OBSERVER_PRIO 2 -#endif - -// BLE_ANS_C_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Alert Notification Service Client. - -#ifndef BLE_ANS_C_BLE_OBSERVER_PRIO -#define BLE_ANS_C_BLE_OBSERVER_PRIO 2 -#endif - -// BLE_BAS_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Battery Service. - -#ifndef BLE_BAS_BLE_OBSERVER_PRIO -#define BLE_BAS_BLE_OBSERVER_PRIO 2 -#endif - -// BLE_BAS_C_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Battery Service Client. - -#ifndef BLE_BAS_C_BLE_OBSERVER_PRIO -#define BLE_BAS_C_BLE_OBSERVER_PRIO 2 -#endif - -// BLE_BPS_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Blood Pressure Service. - -#ifndef BLE_BPS_BLE_OBSERVER_PRIO -#define BLE_BPS_BLE_OBSERVER_PRIO 2 -#endif - -// BLE_CONN_PARAMS_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Connection parameters module. - -#ifndef BLE_CONN_PARAMS_BLE_OBSERVER_PRIO -#define BLE_CONN_PARAMS_BLE_OBSERVER_PRIO 1 -#endif - -// BLE_CONN_STATE_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Connection State module. - -#ifndef BLE_CONN_STATE_BLE_OBSERVER_PRIO -#define BLE_CONN_STATE_BLE_OBSERVER_PRIO 0 -#endif - -// BLE_CSCS_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Cycling Speed and Cadence Service. - -#ifndef BLE_CSCS_BLE_OBSERVER_PRIO -#define BLE_CSCS_BLE_OBSERVER_PRIO 2 -#endif - -// BLE_CTS_C_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Current Time Service Client. - -#ifndef BLE_CTS_C_BLE_OBSERVER_PRIO -#define BLE_CTS_C_BLE_OBSERVER_PRIO 2 -#endif - -// BLE_DB_DISC_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Database Discovery module. - -#ifndef BLE_DB_DISC_BLE_OBSERVER_PRIO -#define BLE_DB_DISC_BLE_OBSERVER_PRIO 1 -#endif - -// BLE_DFU_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the DFU Service. - -#ifndef BLE_DFU_BLE_OBSERVER_PRIO -#define BLE_DFU_BLE_OBSERVER_PRIO 2 -#endif - -// BLE_DIS_C_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Device Information Client. - -#ifndef BLE_DIS_C_BLE_OBSERVER_PRIO -#define BLE_DIS_C_BLE_OBSERVER_PRIO 2 -#endif - -// BLE_GLS_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Glucose Service. - -#ifndef BLE_GLS_BLE_OBSERVER_PRIO -#define BLE_GLS_BLE_OBSERVER_PRIO 2 -#endif - -// BLE_HIDS_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Human Interface Device Service. - -#ifndef BLE_HIDS_BLE_OBSERVER_PRIO -#define BLE_HIDS_BLE_OBSERVER_PRIO 2 -#endif - -// BLE_HRS_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Heart Rate Service. - -#ifndef BLE_HRS_BLE_OBSERVER_PRIO -#define BLE_HRS_BLE_OBSERVER_PRIO 2 -#endif - -// BLE_HRS_C_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Heart Rate Service Client. - -#ifndef BLE_HRS_C_BLE_OBSERVER_PRIO -#define BLE_HRS_C_BLE_OBSERVER_PRIO 2 -#endif - -// BLE_HTS_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Health Thermometer Service. - -#ifndef BLE_HTS_BLE_OBSERVER_PRIO -#define BLE_HTS_BLE_OBSERVER_PRIO 2 -#endif - -// BLE_IAS_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Immediate Alert Service. - -#ifndef BLE_IAS_BLE_OBSERVER_PRIO -#define BLE_IAS_BLE_OBSERVER_PRIO 2 -#endif - -// BLE_IAS_C_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Immediate Alert Service Client. - -#ifndef BLE_IAS_C_BLE_OBSERVER_PRIO -#define BLE_IAS_C_BLE_OBSERVER_PRIO 2 -#endif - -// BLE_LBS_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the LED Button Service. - -#ifndef BLE_LBS_BLE_OBSERVER_PRIO -#define BLE_LBS_BLE_OBSERVER_PRIO 2 -#endif - -// BLE_LBS_C_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the LED Button Service Client. - -#ifndef BLE_LBS_C_BLE_OBSERVER_PRIO -#define BLE_LBS_C_BLE_OBSERVER_PRIO 2 -#endif - -// BLE_LESC_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the BLE LESC module. - -#ifndef BLE_LESC_OBSERVER_PRIO -#define BLE_LESC_OBSERVER_PRIO 2 -#endif - -// BLE_LLS_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Link Loss Service. - -#ifndef BLE_LLS_BLE_OBSERVER_PRIO -#define BLE_LLS_BLE_OBSERVER_PRIO 2 -#endif - -// BLE_LNS_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Location Navigation Service. - -#ifndef BLE_LNS_BLE_OBSERVER_PRIO -#define BLE_LNS_BLE_OBSERVER_PRIO 2 -#endif - -// BLE_NUS_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the UART Service. - -#ifndef BLE_NUS_BLE_OBSERVER_PRIO -#define BLE_NUS_BLE_OBSERVER_PRIO 2 -#endif - -// BLE_NUS_C_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the UART Central Service. - -#ifndef BLE_NUS_C_BLE_OBSERVER_PRIO -#define BLE_NUS_C_BLE_OBSERVER_PRIO 2 -#endif - -// BLE_OTS_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Object transfer service. - -#ifndef BLE_OTS_BLE_OBSERVER_PRIO -#define BLE_OTS_BLE_OBSERVER_PRIO 2 -#endif - -// BLE_OTS_C_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Object transfer service client. - -#ifndef BLE_OTS_C_BLE_OBSERVER_PRIO -#define BLE_OTS_C_BLE_OBSERVER_PRIO 2 -#endif - -// BLE_RSCS_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Running Speed and Cadence Service. - -#ifndef BLE_RSCS_BLE_OBSERVER_PRIO -#define BLE_RSCS_BLE_OBSERVER_PRIO 2 -#endif - -// BLE_RSCS_C_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Running Speed and Cadence Client. - -#ifndef BLE_RSCS_C_BLE_OBSERVER_PRIO -#define BLE_RSCS_C_BLE_OBSERVER_PRIO 2 -#endif - -// BLE_TPS_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the TX Power Service. - -#ifndef BLE_TPS_BLE_OBSERVER_PRIO -#define BLE_TPS_BLE_OBSERVER_PRIO 2 -#endif - -// BSP_BTN_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Button Control module. - -#ifndef BSP_BTN_BLE_OBSERVER_PRIO -#define BSP_BTN_BLE_OBSERVER_PRIO 1 -#endif - -// NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the NFC pairing library. - -#ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO -#define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1 -#endif - -// NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the NFC pairing library. - -#ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO -#define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1 -#endif - -// NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the NFC pairing library. - -#ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO -#define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1 -#endif - -// NRF_BLE_BMS_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Bond Management Service. - -#ifndef NRF_BLE_BMS_BLE_OBSERVER_PRIO -#define NRF_BLE_BMS_BLE_OBSERVER_PRIO 2 -#endif - -// NRF_BLE_CGMS_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Contiuon Glucose Monitoring Service. - -#ifndef NRF_BLE_CGMS_BLE_OBSERVER_PRIO -#define NRF_BLE_CGMS_BLE_OBSERVER_PRIO 2 -#endif - -// NRF_BLE_ES_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Eddystone module. - -#ifndef NRF_BLE_ES_BLE_OBSERVER_PRIO -#define NRF_BLE_ES_BLE_OBSERVER_PRIO 2 -#endif - -// NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the GATT Service Client. - -#ifndef NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO -#define NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO 2 -#endif - -// NRF_BLE_GATT_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the GATT module. - -#ifndef NRF_BLE_GATT_BLE_OBSERVER_PRIO -#define NRF_BLE_GATT_BLE_OBSERVER_PRIO 1 -#endif - -// NRF_BLE_QWR_BLE_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the Queued writes module. - -#ifndef NRF_BLE_QWR_BLE_OBSERVER_PRIO -#define NRF_BLE_QWR_BLE_OBSERVER_PRIO 2 -#endif - -// PM_BLE_OBSERVER_PRIO - Priority with which BLE events are dispatched to the Peer Manager module. -#ifndef PM_BLE_OBSERVER_PRIO -#define PM_BLE_OBSERVER_PRIO 1 -#endif - -// -//========================================================== - -// -//========================================================== - - -// - -// NRF_SDH_ENABLED - nrf_sdh - SoftDevice handler -//========================================================== -#ifndef NRF_SDH_ENABLED -#define NRF_SDH_ENABLED 0 -#endif -// Dispatch model - -// This setting configures how Stack events are dispatched to the application. -//========================================================== -// NRF_SDH_DISPATCH_MODEL - - -// NRF_SDH_DISPATCH_MODEL_INTERRUPT: SoftDevice events are passed to the application from the interrupt context. -// NRF_SDH_DISPATCH_MODEL_APPSH: SoftDevice events are scheduled using @ref app_scheduler. -// NRF_SDH_DISPATCH_MODEL_POLLING: SoftDevice events are to be fetched manually. -// <0=> NRF_SDH_DISPATCH_MODEL_INTERRUPT -// <1=> NRF_SDH_DISPATCH_MODEL_APPSH -// <2=> NRF_SDH_DISPATCH_MODEL_POLLING - -#ifndef NRF_SDH_DISPATCH_MODEL -#define NRF_SDH_DISPATCH_MODEL 0 -#endif - -// -//========================================================== - -// Clock - SoftDevice clock configuration - -//========================================================== -// NRF_SDH_CLOCK_LF_SRC - SoftDevice clock source. - -// <0=> NRF_CLOCK_LF_SRC_RC -// <1=> NRF_CLOCK_LF_SRC_XTAL -// <2=> NRF_CLOCK_LF_SRC_SYNTH - -#ifndef NRF_SDH_CLOCK_LF_SRC -#define NRF_SDH_CLOCK_LF_SRC 1 -#endif - -// NRF_SDH_CLOCK_LF_RC_CTIV - SoftDevice calibration timer interval. -#ifndef NRF_SDH_CLOCK_LF_RC_CTIV -#define NRF_SDH_CLOCK_LF_RC_CTIV 0 -#endif - -// NRF_SDH_CLOCK_LF_RC_TEMP_CTIV - SoftDevice calibration timer interval under constant temperature. -// How often (in number of calibration intervals) the RC oscillator shall be calibrated -// if the temperature has not changed. - -#ifndef NRF_SDH_CLOCK_LF_RC_TEMP_CTIV -#define NRF_SDH_CLOCK_LF_RC_TEMP_CTIV 0 -#endif - -// NRF_SDH_CLOCK_LF_ACCURACY - External clock accuracy used in the LL to compute timing. - -// <0=> NRF_CLOCK_LF_ACCURACY_250_PPM -// <1=> NRF_CLOCK_LF_ACCURACY_500_PPM -// <2=> NRF_CLOCK_LF_ACCURACY_150_PPM -// <3=> NRF_CLOCK_LF_ACCURACY_100_PPM -// <4=> NRF_CLOCK_LF_ACCURACY_75_PPM -// <5=> NRF_CLOCK_LF_ACCURACY_50_PPM -// <6=> NRF_CLOCK_LF_ACCURACY_30_PPM -// <7=> NRF_CLOCK_LF_ACCURACY_20_PPM -// <8=> NRF_CLOCK_LF_ACCURACY_10_PPM -// <9=> NRF_CLOCK_LF_ACCURACY_5_PPM -// <10=> NRF_CLOCK_LF_ACCURACY_2_PPM -// <11=> NRF_CLOCK_LF_ACCURACY_1_PPM - -#ifndef NRF_SDH_CLOCK_LF_ACCURACY -#define NRF_SDH_CLOCK_LF_ACCURACY 7 -#endif - -// -//========================================================== - -// SDH Observers - Observers and priority levels - -//========================================================== -// NRF_SDH_REQ_OBSERVER_PRIO_LEVELS - Total number of priority levels for request observers. -// This setting configures the number of priority levels available for the SoftDevice request event handlers. -// The priority level of a handler determines the order in which it receives events, with respect to other handlers. - -#ifndef NRF_SDH_REQ_OBSERVER_PRIO_LEVELS -#define NRF_SDH_REQ_OBSERVER_PRIO_LEVELS 2 -#endif - -// NRF_SDH_STATE_OBSERVER_PRIO_LEVELS - Total number of priority levels for state observers. -// This setting configures the number of priority levels available for the SoftDevice state event handlers. -// The priority level of a handler determines the order in which it receives events, with respect to other handlers. - -#ifndef NRF_SDH_STATE_OBSERVER_PRIO_LEVELS -#define NRF_SDH_STATE_OBSERVER_PRIO_LEVELS 2 -#endif - -// NRF_SDH_STACK_OBSERVER_PRIO_LEVELS - Total number of priority levels for stack event observers. -// This setting configures the number of priority levels available for the SoftDevice stack event handlers (ANT, BLE, SoC). -// The priority level of a handler determines the order in which it receives events, with respect to other handlers. - -#ifndef NRF_SDH_STACK_OBSERVER_PRIO_LEVELS -#define NRF_SDH_STACK_OBSERVER_PRIO_LEVELS 2 -#endif - - -// State Observers priorities - Invididual priorities - -//========================================================== -// CLOCK_CONFIG_STATE_OBSERVER_PRIO -// Priority with which state events are dispatched to the Clock driver. - -#ifndef CLOCK_CONFIG_STATE_OBSERVER_PRIO -#define CLOCK_CONFIG_STATE_OBSERVER_PRIO 0 -#endif - -// POWER_CONFIG_STATE_OBSERVER_PRIO -// Priority with which state events are dispatched to the Power driver. - -#ifndef POWER_CONFIG_STATE_OBSERVER_PRIO -#define POWER_CONFIG_STATE_OBSERVER_PRIO 0 -#endif - -// RNG_CONFIG_STATE_OBSERVER_PRIO -// Priority with which state events are dispatched to this module. - -#ifndef RNG_CONFIG_STATE_OBSERVER_PRIO -#define RNG_CONFIG_STATE_OBSERVER_PRIO 0 -#endif - -// -//========================================================== - -// Stack Event Observers priorities - Invididual priorities - -//========================================================== -// NRF_SDH_ANT_STACK_OBSERVER_PRIO -// This setting configures the priority with which ANT events are processed with respect to other events coming from the stack. -// Modify this setting if you need to have ANT events dispatched before or after other stack events, such as BLE or SoC. -// Zero is the highest priority. - -#ifndef NRF_SDH_ANT_STACK_OBSERVER_PRIO -#define NRF_SDH_ANT_STACK_OBSERVER_PRIO 0 -#endif - -// NRF_SDH_BLE_STACK_OBSERVER_PRIO -// This setting configures the priority with which BLE events are processed with respect to other events coming from the stack. -// Modify this setting if you need to have BLE events dispatched before or after other stack events, such as ANT or SoC. -// Zero is the highest priority. - -#ifndef NRF_SDH_BLE_STACK_OBSERVER_PRIO -#define NRF_SDH_BLE_STACK_OBSERVER_PRIO 0 -#endif - -// NRF_SDH_SOC_STACK_OBSERVER_PRIO -// This setting configures the priority with which SoC events are processed with respect to other events coming from the stack. -// Modify this setting if you need to have SoC events dispatched before or after other stack events, such as ANT or BLE. -// Zero is the highest priority. - -#ifndef NRF_SDH_SOC_STACK_OBSERVER_PRIO -#define NRF_SDH_SOC_STACK_OBSERVER_PRIO 0 -#endif - -// -//========================================================== - -// -//========================================================== - - -// - -// NRF_SDH_SOC_ENABLED - nrf_sdh_soc - SoftDevice SoC event handler -//========================================================== -#ifndef NRF_SDH_SOC_ENABLED -#define NRF_SDH_SOC_ENABLED 0 -#endif -// SoC Observers - Observers and priority levels - -//========================================================== -// NRF_SDH_SOC_OBSERVER_PRIO_LEVELS - Total number of priority levels for SoC observers. -// This setting configures the number of priority levels available for the SoC event handlers. -// The priority level of a handler determines the order in which it receives events, with respect to other handlers. - -#ifndef NRF_SDH_SOC_OBSERVER_PRIO_LEVELS -#define NRF_SDH_SOC_OBSERVER_PRIO_LEVELS 2 -#endif - -// SoC Observers priorities - Invididual priorities - -//========================================================== -// BLE_ADV_SOC_OBSERVER_PRIO -// Priority with which SoC events are dispatched to the Advertising module. - -#ifndef BLE_ADV_SOC_OBSERVER_PRIO -#define BLE_ADV_SOC_OBSERVER_PRIO 1 -#endif - -// BLE_DFU_SOC_OBSERVER_PRIO -// Priority with which BLE events are dispatched to the DFU Service. - -#ifndef BLE_DFU_SOC_OBSERVER_PRIO -#define BLE_DFU_SOC_OBSERVER_PRIO 1 -#endif - -// CLOCK_CONFIG_SOC_OBSERVER_PRIO -// Priority with which SoC events are dispatched to the Clock driver. - -#ifndef CLOCK_CONFIG_SOC_OBSERVER_PRIO -#define CLOCK_CONFIG_SOC_OBSERVER_PRIO 0 -#endif - -// POWER_CONFIG_SOC_OBSERVER_PRIO -// Priority with which SoC events are dispatched to the Power driver. - -#ifndef POWER_CONFIG_SOC_OBSERVER_PRIO -#define POWER_CONFIG_SOC_OBSERVER_PRIO 0 -#endif - -// -//========================================================== - -// -//========================================================== - - -// - -// -//========================================================== - -// <<< end of configuration section >>> -#endif //SDK_CONFIG_H - diff --git a/bsp/boards/nrf52840/sdk/config/nrf52840/ses/flash_placement.xml b/bsp/boards/nrf52840/sdk/config/nrf52840/ses/flash_placement.xml deleted file mode 100644 index 0b489f2a71..0000000000 --- a/bsp/boards/nrf52840/sdk/config/nrf52840/ses/flash_placement.xml +++ /dev/null @@ -1,50 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/apply_old_config.h b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/apply_old_config.h deleted file mode 100644 index 17fd381ee5..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/apply_old_config.h +++ /dev/null @@ -1,1385 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -#ifndef APPLY_OLD_CONFIG_H__ -#define APPLY_OLD_CONFIG_H__ - -//------------------------------------------------------------------------------ -// Peripheral Resource Sharing (PRS) - -#if defined(PERIPHERAL_RESOURCE_SHARING_ENABLED) - -#define NRFX_PRS_ENABLED PERIPHERAL_RESOURCE_SHARING_ENABLED -#define NRFX_PRS_BOX_0_ENABLED PERIPHERAL_RESOURCE_SHARING_ENABLED -#define NRFX_PRS_BOX_1_ENABLED PERIPHERAL_RESOURCE_SHARING_ENABLED -#define NRFX_PRS_BOX_2_ENABLED PERIPHERAL_RESOURCE_SHARING_ENABLED -#define NRFX_PRS_BOX_3_ENABLED PERIPHERAL_RESOURCE_SHARING_ENABLED -#define NRFX_PRS_BOX_4_ENABLED PERIPHERAL_RESOURCE_SHARING_ENABLED - -#if defined(COMMON_CONFIG_LOG_ENABLED) -#undef NRFX_PRS_CONFIG_LOG_ENABLED -#define NRFX_PRS_CONFIG_LOG_ENABLED COMMON_CONFIG_LOG_ENABLED -#endif -#if defined(COMMON_CONFIG_LOG_LEVEL) -#undef NRFX_PRS_CONFIG_LOG_LEVEL -#define NRFX_PRS_CONFIG_LOG_LEVEL COMMON_CONFIG_LOG_LEVEL -#endif -#if defined(COMMON_CONFIG_INFO_COLOR) -#undef NRFX_PRS_CONFIG_INFO_COLOR -#define NRFX_PRS_CONFIG_INFO_COLOR COMMON_CONFIG_INFO_COLOR -#endif -#if defined(COMMON_CONFIG_DEBUG_COLOR) -#undef NRFX_PRS_CONFIG_DEBUG_COLOR -#define NRFX_PRS_CONFIG_DEBUG_COLOR COMMON_CONFIG_DEBUG_COLOR -#endif - -#endif // defined(PERIPHERAL_RESOURCE_SHARING_ENABLED) - -//------------------------------------------------------------------------------ -// CLOCK - -#if defined(CLOCK_ENABLED) - -#undef NRFX_CLOCK_ENABLED -#define NRFX_CLOCK_ENABLED CLOCK_ENABLED - -#if defined(CLOCK_CONFIG_LF_SRC) -#undef NRFX_CLOCK_CONFIG_LF_SRC -#define NRFX_CLOCK_CONFIG_LF_SRC CLOCK_CONFIG_LF_SRC -#endif -#if defined(CLOCK_CONFIG_IRQ_PRIORITY) -#undef NRFX_CLOCK_CONFIG_IRQ_PRIORITY -#define NRFX_CLOCK_CONFIG_IRQ_PRIORITY CLOCK_CONFIG_IRQ_PRIORITY -#endif - -#if defined(CLOCK_CONFIG_LOG_ENABLED) -#undef NRFX_CLOCK_CONFIG_LOG_ENABLED -#define NRFX_CLOCK_CONFIG_LOG_ENABLED CLOCK_CONFIG_LOG_ENABLED -#endif -#if defined(CLOCK_CONFIG_LOG_LEVEL) -#undef NRFX_CLOCK_CONFIG_LOG_LEVEL -#define NRFX_CLOCK_CONFIG_LOG_LEVEL CLOCK_CONFIG_LOG_LEVEL -#endif -#if defined(CLOCK_CONFIG_INFO_COLOR) -#undef NRFX_CLOCK_CONFIG_INFO_COLOR -#define NRFX_CLOCK_CONFIG_INFO_COLOR CLOCK_CONFIG_INFO_COLOR -#endif -#if defined(CLOCK_CONFIG_DEBUG_COLOR) -#undef NRFX_CLOCK_CONFIG_DEBUG_COLOR -#define NRFX_CLOCK_CONFIG_DEBUG_COLOR CLOCK_CONFIG_DEBUG_COLOR -#endif - -#endif // defined(CLOCK_ENABLED) - -//------------------------------------------------------------------------------ -// COMP - -#if defined(COMP_ENABLED) - -#undef NRFX_COMP_ENABLED -#define NRFX_COMP_ENABLED COMP_ENABLED - -#if defined(COMP_CONFIG_REF) -#undef NRFX_COMP_CONFIG_REF -#define NRFX_COMP_CONFIG_REF COMP_CONFIG_REF -#endif -#if defined(COMP_CONFIG_MAIN_MODE) -#undef NRFX_COMP_CONFIG_MAIN_MODE -#define NRFX_COMP_CONFIG_MAIN_MODE COMP_CONFIG_MAIN_MODE -#endif -#if defined(COMP_CONFIG_SPEED_MODE) -#undef NRFX_COMP_CONFIG_SPEED_MODE -#define NRFX_COMP_CONFIG_SPEED_MODE COMP_CONFIG_SPEED_MODE -#endif -#if defined(COMP_CONFIG_HYST) -#undef NRFX_COMP_CONFIG_HYST -#define NRFX_COMP_CONFIG_HYST COMP_CONFIG_HYST -#endif -#if defined(COMP_CONFIG_ISOURCE) -#undef NRFX_COMP_CONFIG_ISOURCE -#define NRFX_COMP_CONFIG_ISOURCE COMP_CONFIG_ISOURCE -#endif -#if defined(COMP_CONFIG_INPUT) -#undef NRFX_COMP_CONFIG_INPUT -#define NRFX_COMP_CONFIG_INPUT COMP_CONFIG_INPUT -#endif -#if defined(COMP_CONFIG_IRQ_PRIORITY) -#undef NRFX_COMP_CONFIG_IRQ_PRIORITY -#define NRFX_COMP_CONFIG_IRQ_PRIORITY COMP_CONFIG_IRQ_PRIORITY -#endif - -#if defined(COMP_CONFIG_LOG_ENABLED) -#undef NRFX_COMP_CONFIG_LOG_ENABLED -#define NRFX_COMP_CONFIG_LOG_ENABLED COMP_CONFIG_LOG_ENABLED -#endif -#if defined(COMP_CONFIG_LOG_LEVEL) -#undef NRFX_COMP_CONFIG_LOG_LEVEL -#define NRFX_COMP_CONFIG_LOG_LEVEL COMP_CONFIG_LOG_LEVEL -#endif -#if defined(COMP_CONFIG_INFO_COLOR) -#undef NRFX_COMP_CONFIG_INFO_COLOR -#define NRFX_COMP_CONFIG_INFO_COLOR COMP_CONFIG_INFO_COLOR -#endif -#if defined(COMP_CONFIG_DEBUG_COLOR) -#undef NRFX_COMP_CONFIG_DEBUG_COLOR -#define NRFX_COMP_CONFIG_DEBUG_COLOR COMP_CONFIG_DEBUG_COLOR -#endif - -#endif // defined(COMP_ENABLED) - -//------------------------------------------------------------------------------ -// GPIOTE - -#if defined(GPIOTE_ENABLED) - -#undef NRFX_GPIOTE_ENABLED -#define NRFX_GPIOTE_ENABLED GPIOTE_ENABLED - -#if defined(GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS) -#undef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS -#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS -#endif - -#if defined(GPIOTE_CONFIG_IRQ_PRIORITY) -#undef NRFX_GPIOTE_CONFIG_IRQ_PRIORITY -#define NRFX_GPIOTE_CONFIG_IRQ_PRIORITY GPIOTE_CONFIG_IRQ_PRIORITY -#endif - -#if defined(GPIOTE_CONFIG_LOG_ENABLED) -#undef NRFX_GPIOTE_CONFIG_LOG_ENABLED -#define NRFX_GPIOTE_CONFIG_LOG_ENABLED GPIOTE_CONFIG_LOG_ENABLED -#endif -#if defined(GPIOTE_CONFIG_LOG_LEVEL) -#undef NRFX_GPIOTE_CONFIG_LOG_LEVEL -#define NRFX_GPIOTE_CONFIG_LOG_LEVEL GPIOTE_CONFIG_LOG_LEVEL -#endif -#if defined(GPIOTE_CONFIG_INFO_COLOR) -#undef NRFX_GPIOTE_CONFIG_INFO_COLOR -#define NRFX_GPIOTE_CONFIG_INFO_COLOR GPIOTE_CONFIG_INFO_COLOR -#endif -#if defined(GPIOTE_CONFIG_DEBUG_COLOR) -#undef NRFX_GPIOTE_CONFIG_DEBUG_COLOR -#define NRFX_GPIOTE_CONFIG_DEBUG_COLOR GPIOTE_CONFIG_DEBUG_COLOR -#endif - -#endif // defined(GPIOTE_ENABLED) - -//------------------------------------------------------------------------------ -// I2S - -#if defined(I2S_ENABLED) - -#undef NRFX_I2S_ENABLED -#define NRFX_I2S_ENABLED I2S_ENABLED - -#if defined(I2S_CONFIG_SCK_PIN) -#undef NRFX_I2S_CONFIG_SCK_PIN -#define NRFX_I2S_CONFIG_SCK_PIN I2S_CONFIG_SCK_PIN -#endif -#if defined(I2S_CONFIG_LRCK_PIN) -#undef NRFX_I2S_CONFIG_LRCK_PIN -#define NRFX_I2S_CONFIG_LRCK_PIN I2S_CONFIG_LRCK_PIN -#endif -#if defined(I2S_CONFIG_MCK_PIN) -#undef NRFX_I2S_CONFIG_MCK_PIN -#define NRFX_I2S_CONFIG_MCK_PIN I2S_CONFIG_MCK_PIN -#endif -#if defined(I2S_CONFIG_SDOUT_PIN) -#undef NRFX_I2S_CONFIG_SDOUT_PIN -#define NRFX_I2S_CONFIG_SDOUT_PIN I2S_CONFIG_SDOUT_PIN -#endif -#if defined(I2S_CONFIG_SDIN_PIN) -#undef NRFX_I2S_CONFIG_SDIN_PIN -#define NRFX_I2S_CONFIG_SDIN_PIN I2S_CONFIG_SDIN_PIN -#endif - -#if defined(I2S_CONFIG_MASTER) -#undef NRFX_I2S_CONFIG_MASTER -#define NRFX_I2S_CONFIG_MASTER I2S_CONFIG_MASTER -#endif -#if defined(I2S_CONFIG_FORMAT) -#undef NRFX_I2S_CONFIG_FORMAT -#define NRFX_I2S_CONFIG_FORMAT I2S_CONFIG_FORMAT -#endif -#if defined(I2S_CONFIG_ALIGN) -#undef NRFX_I2S_CONFIG_ALIGN -#define NRFX_I2S_CONFIG_ALIGN I2S_CONFIG_ALIGN -#endif -#if defined(I2S_CONFIG_SWIDTH) -#undef NRFX_I2S_CONFIG_SWIDTH -#define NRFX_I2S_CONFIG_SWIDTH I2S_CONFIG_SWIDTH -#endif -#if defined(I2S_CONFIG_CHANNELS) -#undef NRFX_I2S_CONFIG_CHANNELS -#define NRFX_I2S_CONFIG_CHANNELS I2S_CONFIG_CHANNELS -#endif -#if defined(I2S_CONFIG_MCK_SETUP) -#undef NRFX_I2S_CONFIG_MCK_SETUP -#define NRFX_I2S_CONFIG_MCK_SETUP I2S_CONFIG_MCK_SETUP -#endif -#if defined(I2S_CONFIG_RATIO) -#undef NRFX_I2S_CONFIG_RATIO -#define NRFX_I2S_CONFIG_RATIO I2S_CONFIG_RATIO -#endif -#if defined(I2S_CONFIG_IRQ_PRIORITY) -#undef NRFX_I2S_CONFIG_IRQ_PRIORITY -#define NRFX_I2S_CONFIG_IRQ_PRIORITY I2S_CONFIG_IRQ_PRIORITY -#endif - -#if defined(I2S_CONFIG_LOG_ENABLED) -#undef NRFX_I2S_CONFIG_LOG_ENABLED -#define NRFX_I2S_CONFIG_LOG_ENABLED I2S_CONFIG_LOG_ENABLED -#endif -#if defined(I2S_CONFIG_LOG_LEVEL) -#undef NRFX_I2S_CONFIG_LOG_LEVEL -#define NRFX_I2S_CONFIG_LOG_LEVEL I2S_CONFIG_LOG_LEVEL -#endif -#if defined(I2S_CONFIG_INFO_COLOR) -#undef NRFX_I2S_CONFIG_INFO_COLOR -#define NRFX_I2S_CONFIG_INFO_COLOR I2S_CONFIG_INFO_COLOR -#endif -#if defined(I2S_CONFIG_DEBUG_COLOR) -#undef NRFX_I2S_CONFIG_DEBUG_COLOR -#define NRFX_I2S_CONFIG_DEBUG_COLOR I2S_CONFIG_DEBUG_COLOR -#endif - -#endif // defined(I2S_ENABLED) - -//------------------------------------------------------------------------------ -// LPCOMP - -#if defined(LPCOMP_ENABLED) - -#undef NRFX_LPCOMP_ENABLED -#define NRFX_LPCOMP_ENABLED LPCOMP_ENABLED - -#if defined(LPCOMP_CONFIG_REFERENCE) -#undef NRFX_LPCOMP_CONFIG_REFERENCE -#define NRFX_LPCOMP_CONFIG_REFERENCE LPCOMP_CONFIG_REFERENCE -#endif -#if defined(LPCOMP_CONFIG_DETECTION) -#undef NRFX_LPCOMP_CONFIG_DETECTION -#define NRFX_LPCOMP_CONFIG_DETECTION LPCOMP_CONFIG_DETECTION -#endif -#if defined(LPCOMP_CONFIG_INPUT) -#undef NRFX_LPCOMP_CONFIG_INPUT -#define NRFX_LPCOMP_CONFIG_INPUT LPCOMP_CONFIG_INPUT -#endif -#if defined(LPCOMP_CONFIG_HYST) -#undef NRFX_LPCOMP_CONFIG_HYST -#define NRFX_LPCOMP_CONFIG_HYST LPCOMP_CONFIG_HYST -#endif -#if defined(LPCOMP_CONFIG_IRQ_PRIORITY) -#undef NRFX_LPCOMP_CONFIG_IRQ_PRIORITY -#define NRFX_LPCOMP_CONFIG_IRQ_PRIORITY LPCOMP_CONFIG_IRQ_PRIORITY -#endif - -#if defined(LPCOMP_CONFIG_LOG_ENABLED) -#undef NRFX_LPCOMP_CONFIG_LOG_ENABLED -#define NRFX_LPCOMP_CONFIG_LOG_ENABLED LPCOMP_CONFIG_LOG_ENABLED -#endif -#if defined(LPCOMP_CONFIG_LOG_LEVEL) -#undef NRFX_LPCOMP_CONFIG_LOG_LEVEL -#define NRFX_LPCOMP_CONFIG_LOG_LEVEL LPCOMP_CONFIG_LOG_LEVEL -#endif -#if defined(LPCOMP_CONFIG_INFO_COLOR) -#undef NRFX_LPCOMP_CONFIG_INFO_COLOR -#define NRFX_LPCOMP_CONFIG_INFO_COLOR LPCOMP_CONFIG_INFO_COLOR -#endif -#if defined(LPCOMP_CONFIG_DEBUG_COLOR) -#undef NRFX_LPCOMP_CONFIG_DEBUG_COLOR -#define NRFX_LPCOMP_CONFIG_DEBUG_COLOR LPCOMP_CONFIG_DEBUG_COLOR -#endif - -#endif // defined(LPCOMP_ENABLED) - -//------------------------------------------------------------------------------ -// PDM - -#if defined(PDM_ENABLED) - -#undef NRFX_PDM_ENABLED -#define NRFX_PDM_ENABLED PDM_ENABLED - -#if defined(PDM_CONFIG_MODE) -#undef NRFX_PDM_CONFIG_MODE -#define NRFX_PDM_CONFIG_MODE PDM_CONFIG_MODE -#endif -#if defined(PDM_CONFIG_EDGE) -#undef NRFX_PDM_CONFIG_EDGE -#define NRFX_PDM_CONFIG_EDGE PDM_CONFIG_EDGE -#endif -#if defined(PDM_CONFIG_CLOCK_FREQ) -#undef NRFX_PDM_CONFIG_CLOCK_FREQ -#define NRFX_PDM_CONFIG_CLOCK_FREQ PDM_CONFIG_CLOCK_FREQ -#endif -#if defined(PDM_CONFIG_IRQ_PRIORITY) -#undef NRFX_PDM_CONFIG_IRQ_PRIORITY -#define NRFX_PDM_CONFIG_IRQ_PRIORITY PDM_CONFIG_IRQ_PRIORITY -#endif - -#if defined(PDM_CONFIG_LOG_ENABLED) -#undef NRFX_PDM_CONFIG_LOG_ENABLED -#define NRFX_PDM_CONFIG_LOG_ENABLED PDM_CONFIG_LOG_ENABLED -#endif -#if defined(PDM_CONFIG_LOG_LEVEL) -#undef NRFX_PDM_CONFIG_LOG_LEVEL -#define NRFX_PDM_CONFIG_LOG_LEVEL PDM_CONFIG_LOG_LEVEL -#endif -#if defined(PDM_CONFIG_INFO_COLOR) -#undef NRFX_PDM_CONFIG_INFO_COLOR -#define NRFX_PDM_CONFIG_INFO_COLOR PDM_CONFIG_INFO_COLOR -#endif -#if defined(PDM_CONFIG_DEBUG_COLOR) -#undef NRFX_PDM_CONFIG_DEBUG_COLOR -#define NRFX_PDM_CONFIG_DEBUG_COLOR PDM_CONFIG_DEBUG_COLOR -#endif - -#endif // defined(PDM_ENABLED) - -//------------------------------------------------------------------------------ -// POWER - -#if defined(POWER_ENABLED) - -#undef NRFX_POWER_ENABLED -#define NRFX_POWER_ENABLED POWER_ENABLED - -#if defined(POWER_CONFIG_IRQ_PRIORITY) -#undef NRFX_POWER_CONFIG_IRQ_PRIORITY -#define NRFX_POWER_CONFIG_IRQ_PRIORITY POWER_CONFIG_IRQ_PRIORITY -#endif - -#if defined(POWER_CONFIG_DEFAULT_DCDCEN) -#undef NRFX_POWER_CONFIG_DEFAULT_DCDCEN -#define NRFX_POWER_CONFIG_DEFAULT_DCDCEN POWER_CONFIG_DEFAULT_DCDCEN -#endif -#if defined(POWER_CONFIG_DEFAULT_DCDCENHV) -#undef NRFX_POWER_CONFIG_DEFAULT_DCDCENHV -#define NRFX_POWER_CONFIG_DEFAULT_DCDCENHV POWER_CONFIG_DEFAULT_DCDCENHV -#endif - -#endif // defined(POWER_ENABLED) - -//------------------------------------------------------------------------------ -// PPI - -#if defined(PPI_ENABLED) - -#undef NRFX_PPI_ENABLED -#define NRFX_PPI_ENABLED PPI_ENABLED - -#if defined(PPI_CONFIG_LOG_ENABLED) -#undef NRFX_PPI_CONFIG_LOG_ENABLED -#define NRFX_PPI_CONFIG_LOG_ENABLED PPI_CONFIG_LOG_ENABLED -#endif -#if defined(PPI_CONFIG_LOG_LEVEL) -#undef NRFX_PPI_CONFIG_LOG_LEVEL -#define NRFX_PPI_CONFIG_LOG_LEVEL PPI_CONFIG_LOG_LEVEL -#endif -#if defined(PPI_CONFIG_INFO_COLOR) -#undef NRFX_PPI_CONFIG_INFO_COLOR -#define NRFX_PPI_CONFIG_INFO_COLOR PPI_CONFIG_INFO_COLOR -#endif -#if defined(PPI_CONFIG_DEBUG_COLOR) -#undef NRFX_PPI_CONFIG_DEBUG_COLOR -#define NRFX_PPI_CONFIG_DEBUG_COLOR PPI_CONFIG_DEBUG_COLOR -#endif - -#endif // defined(PPI_ENABLED) - -//------------------------------------------------------------------------------ -// PWM - -#if defined(PWM_ENABLED) - -#undef NRFX_PWM_ENABLED -#define NRFX_PWM_ENABLED PWM_ENABLED - -#if defined(PWM0_ENABLED) -#undef NRFX_PWM0_ENABLED -#define NRFX_PWM0_ENABLED PWM0_ENABLED -#endif -#if defined(PWM1_ENABLED) -#undef NRFX_PWM1_ENABLED -#define NRFX_PWM1_ENABLED PWM1_ENABLED -#endif -#if defined(PWM2_ENABLED) -#undef NRFX_PWM2_ENABLED -#define NRFX_PWM2_ENABLED PWM2_ENABLED -#endif -#if defined(PWM3_ENABLED) -#undef NRFX_PWM3_ENABLED -#define NRFX_PWM3_ENABLED PWM3_ENABLED -#endif - -#if defined(PWM_DEFAULT_CONFIG_OUT0_PIN) -#undef NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN -#define NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN PWM_DEFAULT_CONFIG_OUT0_PIN -#endif -#if defined(PWM_DEFAULT_CONFIG_OUT1_PIN) -#undef NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN -#define NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN PWM_DEFAULT_CONFIG_OUT1_PIN -#endif -#if defined(PWM_DEFAULT_CONFIG_OUT2_PIN) -#undef NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN -#define NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN PWM_DEFAULT_CONFIG_OUT2_PIN -#endif -#if defined(PWM_DEFAULT_CONFIG_OUT3_PIN) -#undef NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN -#define NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN PWM_DEFAULT_CONFIG_OUT3_PIN -#endif -#if defined(PWM_DEFAULT_CONFIG_BASE_CLOCK) -#undef NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK -#define NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK PWM_DEFAULT_CONFIG_BASE_CLOCK -#endif -#if defined(PWM_DEFAULT_CONFIG_COUNT_MODE) -#undef NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE -#define NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE PWM_DEFAULT_CONFIG_COUNT_MODE -#endif -#if defined(PWM_DEFAULT_CONFIG_TOP_VALUE) -#undef NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE -#define NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE PWM_DEFAULT_CONFIG_TOP_VALUE -#endif -#if defined(PWM_DEFAULT_CONFIG_LOAD_MODE) -#undef NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE -#define NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE PWM_DEFAULT_CONFIG_LOAD_MODE -#endif -#if defined(PWM_DEFAULT_CONFIG_STEP_MODE) -#undef NRFX_PWM_DEFAULT_CONFIG_STEP_MODE -#define NRFX_PWM_DEFAULT_CONFIG_STEP_MODE PWM_DEFAULT_CONFIG_STEP_MODE -#endif -#if defined(PWM_DEFAULT_CONFIG_IRQ_PRIORITY) -#undef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY PWM_DEFAULT_CONFIG_IRQ_PRIORITY -#endif - -#if defined(PWM_CONFIG_LOG_ENABLED) -#undef NRFX_PWM_CONFIG_LOG_ENABLED -#define NRFX_PWM_CONFIG_LOG_ENABLED PWM_CONFIG_LOG_ENABLED -#endif -#if defined(PWM_CONFIG_LOG_LEVEL) -#undef NRFX_PWM_CONFIG_LOG_LEVEL -#define NRFX_PWM_CONFIG_LOG_LEVEL PWM_CONFIG_LOG_LEVEL -#endif -#if defined(PWM_CONFIG_INFO_COLOR) -#undef NRFX_PWM_CONFIG_INFO_COLOR -#define NRFX_PWM_CONFIG_INFO_COLOR PWM_CONFIG_INFO_COLOR -#endif -#if defined(PWM_CONFIG_DEBUG_COLOR) -#undef NRFX_PWM_CONFIG_DEBUG_COLOR -#define NRFX_PWM_CONFIG_DEBUG_COLOR PWM_CONFIG_DEBUG_COLOR -#endif - -#if defined(PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED) -#undef NRFX_PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED -#define NRFX_PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED -#endif -#if defined(PWM_NRF52_ANOMALY_109_EGU_INSTANCE) -#undef NRFX_PWM_NRF52_ANOMALY_109_EGU_INSTANCE -#define NRFX_PWM_NRF52_ANOMALY_109_EGU_INSTANCE PWM_NRF52_ANOMALY_109_EGU_INSTANCE -#endif - -#endif // defined(PWM_ENABLED) - -//------------------------------------------------------------------------------ -// QDEC - -#if defined(QDEC_ENABLED) - -#undef NRFX_QDEC_ENABLED -#define NRFX_QDEC_ENABLED QDEC_ENABLED - -#if defined(QDEC_CONFIG_REPORTPER) -#undef NRFX_QDEC_CONFIG_REPORTPER -#define NRFX_QDEC_CONFIG_REPORTPER QDEC_CONFIG_REPORTPER -#endif -#if defined(QDEC_CONFIG_SAMPLEPER) -#undef NRFX_QDEC_CONFIG_SAMPLEPER -#define NRFX_QDEC_CONFIG_SAMPLEPER QDEC_CONFIG_SAMPLEPER -#endif -#if defined(QDEC_CONFIG_PIO_A) -#undef NRFX_QDEC_CONFIG_PIO_A -#define NRFX_QDEC_CONFIG_PIO_A QDEC_CONFIG_PIO_A -#endif -#if defined(QDEC_CONFIG_PIO_B) -#undef NRFX_QDEC_CONFIG_PIO_B -#define NRFX_QDEC_CONFIG_PIO_B QDEC_CONFIG_PIO_B -#endif -#if defined(QDEC_CONFIG_PIO_LED) -#undef NRFX_QDEC_CONFIG_PIO_LED -#define NRFX_QDEC_CONFIG_PIO_LED QDEC_CONFIG_PIO_LED -#endif -#if defined(QDEC_CONFIG_LEDPRE) -#undef NRFX_QDEC_CONFIG_LEDPRE -#define NRFX_QDEC_CONFIG_LEDPRE QDEC_CONFIG_LEDPRE -#endif -#if defined(QDEC_CONFIG_LEDPOL) -#undef NRFX_QDEC_CONFIG_LEDPOL -#define NRFX_QDEC_CONFIG_LEDPOL QDEC_CONFIG_LEDPOL -#endif -#if defined(QDEC_CONFIG_DBFEN) -#undef NRFX_QDEC_CONFIG_DBFEN -#define NRFX_QDEC_CONFIG_DBFEN QDEC_CONFIG_DBFEN -#endif -#if defined(QDEC_CONFIG_SAMPLE_INTEN) -#undef NRFX_QDEC_CONFIG_SAMPLE_INTEN -#define NRFX_QDEC_CONFIG_SAMPLE_INTEN QDEC_CONFIG_SAMPLE_INTEN -#endif -#if defined(QDEC_CONFIG_IRQ_PRIORITY) -#undef NRFX_QDEC_CONFIG_IRQ_PRIORITY -#define NRFX_QDEC_CONFIG_IRQ_PRIORITY QDEC_CONFIG_IRQ_PRIORITY -#endif - -#if defined(QDEC_CONFIG_LOG_ENABLED) -#undef NRFX_QDEC_CONFIG_LOG_ENABLED -#define NRFX_QDEC_CONFIG_LOG_ENABLED QDEC_CONFIG_LOG_ENABLED -#endif -#if defined(QDEC_CONFIG_LOG_LEVEL) -#undef NRFX_QDEC_CONFIG_LOG_LEVEL -#define NRFX_QDEC_CONFIG_LOG_LEVEL QDEC_CONFIG_LOG_LEVEL -#endif -#if defined(QDEC_CONFIG_INFO_COLOR) -#undef NRFX_QDEC_CONFIG_INFO_COLOR -#define NRFX_QDEC_CONFIG_INFO_COLOR QDEC_CONFIG_INFO_COLOR -#endif -#if defined(QDEC_CONFIG_DEBUG_COLOR) -#undef NRFX_QDEC_CONFIG_DEBUG_COLOR -#define NRFX_QDEC_CONFIG_DEBUG_COLOR QDEC_CONFIG_DEBUG_COLOR -#endif - -#endif // defined(QDEC_ENABLED) - -//------------------------------------------------------------------------------ -// QSPI - -#if defined(QSPI_ENABLED) - -#undef NRFX_QSPI_ENABLED -#define NRFX_QSPI_ENABLED QSPI_ENABLED - -#if defined(QSPI_CONFIG_SCK_DELAY) -#undef NRFX_QSPI_CONFIG_SCK_DELAY -#define NRFX_QSPI_CONFIG_SCK_DELAY QSPI_CONFIG_SCK_DELAY -#endif -#if defined(QSPI_CONFIG_XIP_OFFSET) -#undef NRFX_QSPI_CONFIG_XIP_OFFSET -#define NRFX_QSPI_CONFIG_XIP_OFFSET QSPI_CONFIG_XIP_OFFSET -#endif -#if defined(QSPI_CONFIG_READOC) -#undef NRFX_QSPI_CONFIG_READOC -#define NRFX_QSPI_CONFIG_READOC QSPI_CONFIG_READOC -#endif -#if defined(QSPI_CONFIG_WRITEOC) -#undef NRFX_QSPI_CONFIG_WRITEOC -#define NRFX_QSPI_CONFIG_WRITEOC QSPI_CONFIG_WRITEOC -#endif -#if defined(QSPI_CONFIG_ADDRMODE) -#undef NRFX_QSPI_CONFIG_ADDRMODE -#define NRFX_QSPI_CONFIG_ADDRMODE QSPI_CONFIG_ADDRMODE -#endif -#if defined(QSPI_CONFIG_MODE) -#undef NRFX_QSPI_CONFIG_MODE -#define NRFX_QSPI_CONFIG_MODE QSPI_CONFIG_MODE -#endif -#if defined(QSPI_CONFIG_FREQUENCY) -#undef NRFX_QSPI_CONFIG_FREQUENCY -#define NRFX_QSPI_CONFIG_FREQUENCY QSPI_CONFIG_FREQUENCY -#endif -#if defined(QSPI_CONFIG_IRQ_PRIORITY) -#undef NRFX_QSPI_CONFIG_IRQ_PRIORITY -#define NRFX_QSPI_CONFIG_IRQ_PRIORITY QSPI_CONFIG_IRQ_PRIORITY -#endif - -#if defined(QSPI_PIN_SCK) -#undef NRFX_QSPI_PIN_SCK -#define NRFX_QSPI_PIN_SCK QSPI_PIN_SCK -#endif -#if defined(QSPI_PIN_CSN) -#undef NRFX_QSPI_PIN_CSN -#define NRFX_QSPI_PIN_CSN QSPI_PIN_CSN -#endif -#if defined(QSPI_PIN_IO0) -#undef NRFX_QSPI_PIN_IO0 -#define NRFX_QSPI_PIN_IO0 QSPI_PIN_IO0 -#endif -#if defined(QSPI_PIN_IO0) -#undef NRFX_QSPI_PIN_IO0 -#define NRFX_QSPI_PIN_IO0 QSPI_PIN_IO0 -#endif -#if defined(QSPI_PIN_IO1) -#undef NRFX_QSPI_PIN_IO1 -#define NRFX_QSPI_PIN_IO1 QSPI_PIN_IO1 -#endif -#if defined(QSPI_PIN_IO2) -#undef NRFX_QSPI_PIN_IO2 -#define NRFX_QSPI_PIN_IO2 QSPI_PIN_IO2 -#endif -#if defined(QSPI_PIN_IO3) -#undef NRFX_QSPI_PIN_IO3 -#define NRFX_QSPI_PIN_IO3 QSPI_PIN_IO3 -#endif - -#endif // defined(QSPI_ENABLED) - -//------------------------------------------------------------------------------ -// RNG - -#if defined(RNG_ENABLED) - -#undef NRFX_RNG_ENABLED -#define NRFX_RNG_ENABLED RNG_ENABLED - -#if defined(RNG_CONFIG_ERROR_CORRECTION) -#undef NRFX_RNG_CONFIG_ERROR_CORRECTION -#define NRFX_RNG_CONFIG_ERROR_CORRECTION RNG_CONFIG_ERROR_CORRECTION -#endif - -#if defined(RNG_CONFIG_IRQ_PRIORITY) -#undef NRFX_RNG_CONFIG_IRQ_PRIORITY -#define NRFX_RNG_CONFIG_IRQ_PRIORITY RNG_CONFIG_IRQ_PRIORITY -#endif - -#if defined(RNG_CONFIG_LOG_ENABLED) -#undef NRFX_RNG_CONFIG_LOG_ENABLED -#define NRFX_RNG_CONFIG_LOG_ENABLED RNG_CONFIG_LOG_ENABLED -#endif -#if defined(RNG_CONFIG_LOG_LEVEL) -#undef NRFX_RNG_CONFIG_LOG_LEVEL -#define NRFX_RNG_CONFIG_LOG_LEVEL RNG_CONFIG_LOG_LEVEL -#endif -#if defined(RNG_CONFIG_INFO_COLOR) -#undef NRFX_RNG_CONFIG_INFO_COLOR -#define NRFX_RNG_CONFIG_INFO_COLOR RNG_CONFIG_INFO_COLOR -#endif -#if defined(RNG_CONFIG_DEBUG_COLOR) -#undef NRFX_RNG_CONFIG_DEBUG_COLOR -#define NRFX_RNG_CONFIG_DEBUG_COLOR RNG_CONFIG_DEBUG_COLOR -#endif - -#endif // defined(RNG_ENABLED) - -//------------------------------------------------------------------------------ -// RTC - -#if defined(RTC_ENABLED) - -#undef NRFX_RTC_ENABLED -#define NRFX_RTC_ENABLED RTC_ENABLED - -#if defined(RTC0_ENABLED) -#undef NRFX_RTC0_ENABLED -#define NRFX_RTC0_ENABLED RTC0_ENABLED -#endif -#if defined(RTC1_ENABLED) -#undef NRFX_RTC1_ENABLED -#define NRFX_RTC1_ENABLED RTC1_ENABLED -#endif -#if defined(RTC2_ENABLED) -#undef NRFX_RTC2_ENABLED -#define NRFX_RTC2_ENABLED RTC2_ENABLED -#endif - -#if defined(RTC_DEFAULT_CONFIG_FREQUENCY) -#undef NRFX_RTC_DEFAULT_CONFIG_FREQUENCY -#define NRFX_RTC_DEFAULT_CONFIG_FREQUENCY RTC_DEFAULT_CONFIG_FREQUENCY -#endif -#if defined(RTC_DEFAULT_CONFIG_RELIABLE) -#undef NRFX_RTC_DEFAULT_CONFIG_RELIABLE -#define NRFX_RTC_DEFAULT_CONFIG_RELIABLE RTC_DEFAULT_CONFIG_RELIABLE -#endif -#if defined(RTC_DEFAULT_CONFIG_IRQ_PRIORITY) -#undef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY RTC_DEFAULT_CONFIG_IRQ_PRIORITY -#endif - -#if defined(NRF_MAXIMUM_LATENCY_US) -#undef NRFX_RTC_MAXIMUM_LATENCY_US -#define NRFX_RTC_MAXIMUM_LATENCY_US NRF_MAXIMUM_LATENCY_US -#endif - -#if defined(RTC_CONFIG_LOG_ENABLED) -#undef NRFX_RTC_CONFIG_LOG_ENABLED -#define NRFX_RTC_CONFIG_LOG_ENABLED RTC_CONFIG_LOG_ENABLED -#endif -#if defined(RTC_CONFIG_LOG_LEVEL) -#undef NRFX_RTC_CONFIG_LOG_LEVEL -#define NRFX_RTC_CONFIG_LOG_LEVEL RTC_CONFIG_LOG_LEVEL -#endif -#if defined(RTC_CONFIG_INFO_COLOR) -#undef NRFX_RTC_CONFIG_INFO_COLOR -#define NRFX_RTC_CONFIG_INFO_COLOR RTC_CONFIG_INFO_COLOR -#endif -#if defined(RTC_CONFIG_DEBUG_COLOR) -#undef NRFX_RTC_CONFIG_DEBUG_COLOR -#define NRFX_RTC_CONFIG_DEBUG_COLOR RTC_CONFIG_DEBUG_COLOR -#endif - -#endif // defined(RTC_ENABLED) - -//------------------------------------------------------------------------------ -// SAADC - -#if defined(SAADC_ENABLED) - -#undef NRFX_SAADC_ENABLED -#define NRFX_SAADC_ENABLED SAADC_ENABLED - -#if defined(SAADC_CONFIG_RESOLUTION) -#undef NRFX_SAADC_CONFIG_RESOLUTION -#define NRFX_SAADC_CONFIG_RESOLUTION SAADC_CONFIG_RESOLUTION -#endif -#if defined(SAADC_CONFIG_OVERSAMPLE) -#undef NRFX_SAADC_CONFIG_OVERSAMPLE -#define NRFX_SAADC_CONFIG_OVERSAMPLE SAADC_CONFIG_OVERSAMPLE -#endif -#if defined(SAADC_CONFIG_LP_MODE) -#undef NRFX_SAADC_CONFIG_LP_MODE -#define NRFX_SAADC_CONFIG_LP_MODE SAADC_CONFIG_LP_MODE -#endif -#if defined(SAADC_CONFIG_IRQ_PRIORITY) -#undef NRFX_SAADC_CONFIG_IRQ_PRIORITY -#define NRFX_SAADC_CONFIG_IRQ_PRIORITY SAADC_CONFIG_IRQ_PRIORITY -#endif - -#if defined(SAADC_CONFIG_LOG_ENABLED) -#undef NRFX_SAADC_CONFIG_LOG_ENABLED -#define NRFX_SAADC_CONFIG_LOG_ENABLED SAADC_CONFIG_LOG_ENABLED -#endif -#if defined(SAADC_CONFIG_LOG_LEVEL) -#undef NRFX_SAADC_CONFIG_LOG_LEVEL -#define NRFX_SAADC_CONFIG_LOG_LEVEL SAADC_CONFIG_LOG_LEVEL -#endif -#if defined(SAADC_CONFIG_INFO_COLOR) -#undef NRFX_SAADC_CONFIG_INFO_COLOR -#define NRFX_SAADC_CONFIG_INFO_COLOR SAADC_CONFIG_INFO_COLOR -#endif -#if defined(SAADC_CONFIG_DEBUG_COLOR) -#undef NRFX_SAADC_CONFIG_DEBUG_COLOR -#define NRFX_SAADC_CONFIG_DEBUG_COLOR SAADC_CONFIG_DEBUG_COLOR -#endif - -#endif // defined(SAADC_ENABLED) - -//------------------------------------------------------------------------------ -// SPI - -#if defined(SPI_ENABLED) - -#undef NRFX_SPI_ENABLED -#define NRFX_SPI_ENABLED \ - (SPI_ENABLED && (NRFX_SPI0_ENABLED || NRFX_SPI1_ENABLED || NRFX_SPI2_ENABLED)) -#undef NRFX_SPIM_ENABLED -#define NRFX_SPIM_ENABLED \ - (SPI_ENABLED && (NRFX_SPIM0_ENABLED || NRFX_SPIM1_ENABLED || NRFX_SPIM2_ENABLED)) - -#if defined(SPI_PRESENT) && !defined(SPIM_PRESENT) - -#undef NRFX_SPI0_ENABLED -#define NRFX_SPI0_ENABLED SPI0_ENABLED -#undef NRFX_SPIM0_ENABLED -#define NRFX_SPIM0_ENABLED 0 - -#undef NRFX_SPI1_ENABLED -#define NRFX_SPI1_ENABLED SPI1_ENABLED -#undef NRFX_SPIM1_ENABLED -#define NRFX_SPIM1_ENABLED 0 - -#undef NRFX_SPI2_ENABLED -#define NRFX_SPI2_ENABLED SPI2_ENABLED -#undef NRFX_SPIM2_ENABLED -#define NRFX_SPIM2_ENABLED 0 - -#elif !defined(SPI_PRESENT) && defined(SPIM_PRESENT) - -#undef NRFX_SPI0_ENABLED -#define NRFX_SPI0_ENABLED 0 -#undef NRFX_SPIM0_ENABLED -#define NRFX_SPIM0_ENABLED SPI0_ENABLED - -#undef NRFX_SPI1_ENABLED -#define NRFX_SPI1_ENABLED 0 -#undef NRFX_SPIM1_ENABLED -#define NRFX_SPIM1_ENABLED SPI1_ENABLED - -#undef NRFX_SPI2_ENABLED -#define NRFX_SPI2_ENABLED 0 -#undef NRFX_SPIM2_ENABLED -#define NRFX_SPIM2_ENABLED SPI2_ENABLED - -#else // -> defined(SPI_PRESENT) && defined(SPIM_PRESENT) - -#undef NRFX_SPI0_ENABLED -#define NRFX_SPI0_ENABLED (SPI0_ENABLED && !SPI0_USE_EASY_DMA) -#undef NRFX_SPIM0_ENABLED -#define NRFX_SPIM0_ENABLED (SPI0_ENABLED && SPI0_USE_EASY_DMA) - -#undef NRFX_SPI1_ENABLED -#define NRFX_SPI1_ENABLED (SPI1_ENABLED && !SPI1_USE_EASY_DMA) -#undef NRFX_SPIM1_ENABLED -#define NRFX_SPIM1_ENABLED (SPI1_ENABLED && SPI1_USE_EASY_DMA) - -#undef NRFX_SPI2_ENABLED -#define NRFX_SPI2_ENABLED (SPI2_ENABLED && !SPI2_USE_EASY_DMA) -#undef NRFX_SPIM2_ENABLED -#define NRFX_SPIM2_ENABLED (SPI2_ENABLED && SPI2_USE_EASY_DMA) - -#endif // -> defined(SPI_PRESENT) && defined(SPIM_PRESENT) - -#if defined(NRF_SPI_DRV_MISO_PULLUP_CFG) -#undef NRFX_SPI_MISO_PULL_CFG -#define NRFX_SPI_MISO_PULL_CFG NRF_SPI_DRV_MISO_PULLUP_CFG -#undef NRFX_SPIM_MISO_PULL_CFG -#define NRFX_SPIM_MISO_PULL_CFG NRF_SPI_DRV_MISO_PULLUP_CFG -#endif - -#if defined(SPI_DEFAULT_CONFIG_IRQ_PRIORITY) -#undef NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY SPI_DEFAULT_CONFIG_IRQ_PRIORITY -#undef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY SPI_DEFAULT_CONFIG_IRQ_PRIORITY -#endif - -#if defined(SPI_CONFIG_LOG_ENABLED) -#undef NRFX_SPI_CONFIG_LOG_ENABLED -#define NRFX_SPI_CONFIG_LOG_ENABLED SPI_CONFIG_LOG_ENABLED -#undef NRFX_SPIM_CONFIG_LOG_ENABLED -#define NRFX_SPIM_CONFIG_LOG_ENABLED SPI_CONFIG_LOG_ENABLED -#endif -#if defined(SPI_CONFIG_LOG_LEVEL) -#undef NRFX_SPI_CONFIG_LOG_LEVEL -#define NRFX_SPI_CONFIG_LOG_LEVEL SPI_CONFIG_LOG_LEVEL -#undef NRFX_SPIM_CONFIG_LOG_LEVEL -#define NRFX_SPIM_CONFIG_LOG_LEVEL SPI_CONFIG_LOG_LEVEL -#endif -#if defined(SPI_CONFIG_INFO_COLOR) -#undef NRFX_SPI_CONFIG_INFO_COLOR -#define NRFX_SPI_CONFIG_INFO_COLOR SPI_CONFIG_INFO_COLOR -#undef NRFX_SPIM_CONFIG_INFO_COLOR -#define NRFX_SPIM_CONFIG_INFO_COLOR SPI_CONFIG_INFO_COLOR -#endif -#if defined(SPI_CONFIG_DEBUG_COLOR) -#undef NRFX_SPI_CONFIG_DEBUG_COLOR -#define NRFX_SPI_CONFIG_DEBUG_COLOR SPI_CONFIG_DEBUG_COLOR -#undef NRFX_SPIM_CONFIG_DEBUG_COLOR -#define NRFX_SPIM_CONFIG_DEBUG_COLOR SPI_CONFIG_DEBUG_COLOR -#endif - -#if defined(SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED) -#undef NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED -#define NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED -#endif - -#endif // defined(SPI_ENABLED) - -//------------------------------------------------------------------------------ -// SPIS - -#if defined(SPIS_ENABLED) - -#undef NRFX_SPIS_ENABLED -#define NRFX_SPIS_ENABLED SPIS_ENABLED - -#if defined(SPIS0_ENABLED) -#undef NRFX_SPIS0_ENABLED -#define NRFX_SPIS0_ENABLED SPIS0_ENABLED -#endif -#if defined(SPIS1_ENABLED) -#undef NRFX_SPIS1_ENABLED -#define NRFX_SPIS1_ENABLED SPIS1_ENABLED -#endif -#if defined(SPIS2_ENABLED) -#undef NRFX_SPIS2_ENABLED -#define NRFX_SPIS2_ENABLED SPIS2_ENABLED -#endif - -#if defined(SPIS_DEFAULT_CONFIG_IRQ_PRIORITY) -#undef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY SPIS_DEFAULT_CONFIG_IRQ_PRIORITY -#endif -#if defined(SPIS_DEFAULT_MODE) -#undef NRFX_SPIS_DEFAULT_MODE -#define NRFX_SPIS_DEFAULT_MODE SPIS_DEFAULT_MODE -#endif -#if defined(SPIS_DEFAULT_BIT_ORDER) -#undef NRFX_SPIS_DEFAULT_BIT_ORDER -#define NRFX_SPIS_DEFAULT_BIT_ORDER SPIS_DEFAULT_BIT_ORDER -#endif -#if defined(SPIS_DEFAULT_DEF) -#undef NRFX_SPIS_DEFAULT_DEF -#define NRFX_SPIS_DEFAULT_DEF SPIS_DEFAULT_DEF -#endif -#if defined(SPIS_DEFAULT_ORC) -#undef NRFX_SPIS_DEFAULT_ORC -#define NRFX_SPIS_DEFAULT_ORC SPIS_DEFAULT_ORC -#endif - -#if defined(SPIS_CONFIG_LOG_ENABLED) -#undef NRFX_SPIS_CONFIG_LOG_ENABLED -#define NRFX_SPIS_CONFIG_LOG_ENABLED SPIS_CONFIG_LOG_ENABLED -#endif -#if defined(SPIS_CONFIG_LOG_LEVEL) -#undef NRFX_SPIS_CONFIG_LOG_LEVEL -#define NRFX_SPIS_CONFIG_LOG_LEVEL SPIS_CONFIG_LOG_LEVEL -#endif -#if defined(SPIS_CONFIG_INFO_COLOR) -#undef NRFX_SPIS_CONFIG_INFO_COLOR -#define NRFX_SPIS_CONFIG_INFO_COLOR SPIS_CONFIG_INFO_COLOR -#endif -#if defined(SPIS_CONFIG_DEBUG_COLOR) -#undef NRFX_SPIS_CONFIG_DEBUG_COLOR -#define NRFX_SPIS_CONFIG_DEBUG_COLOR SPIS_CONFIG_DEBUG_COLOR -#endif - -#if defined(SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED) -#undef NRFX_SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED -#define NRFX_SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED -#endif - -#endif // defined(SPIS_ENABLED) - -//------------------------------------------------------------------------------ -// SWI - -#if defined(SWI_DISABLE0) -#undef NRFX_SWI0_DISABLED -#define NRFX_SWI0_DISABLED 1 -#endif -#if defined(SWI_DISABLE1) -#undef NRFX_SWI1_DISABLED -#define NRFX_SWI1_DISABLED 1 -#endif -#if defined(SWI_DISABLE2) -#undef NRFX_SWI2_DISABLED -#define NRFX_SWI2_DISABLED 1 -#endif -#if defined(SWI_DISABLE3) -#undef NRFX_SWI3_DISABLED -#define NRFX_SWI3_DISABLED 1 -#endif -#if defined(SWI_DISABLE4) -#undef NRFX_SWI4_DISABLED -#define NRFX_SWI4_DISABLED 1 -#endif -#if defined(SWI_DISABLE5) -#undef NRFX_SWI5_DISABLED -#define NRFX_SWI5_DISABLED 1 -#endif - -#if defined(EGU_ENABLED) -#undef NRFX_EGU_ENABLED -#define NRFX_EGU_ENABLED EGU_ENABLED -#endif - -#if defined(SWI_CONFIG_LOG_ENABLED) -#undef NRFX_SWI_CONFIG_LOG_ENABLED -#define NRFX_SWI_CONFIG_LOG_ENABLED SWI_CONFIG_LOG_ENABLED -#endif -#if defined(SWI_CONFIG_LOG_LEVEL) -#undef NRFX_SWI_CONFIG_LOG_LEVEL -#define NRFX_SWI_CONFIG_LOG_LEVEL SWI_CONFIG_LOG_LEVEL -#endif -#if defined(SWI_CONFIG_INFO_COLOR) -#undef NRFX_SWI_CONFIG_INFO_COLOR -#define NRFX_SWI_CONFIG_INFO_COLOR SWI_CONFIG_INFO_COLOR -#endif -#if defined(SWI_CONFIG_DEBUG_COLOR) -#undef NRFX_SWI_CONFIG_DEBUG_COLOR -#define NRFX_SWI_CONFIG_DEBUG_COLOR SWI_CONFIG_DEBUG_COLOR -#endif - -//------------------------------------------------------------------------------ -// SysTick - -#if defined(SYSTICK_ENABLED) - -#undef NRFX_SYSTICK_ENABLED -#define NRFX_SYSTICK_ENABLED SYSTICK_ENABLED - -#endif // defined(SYSTICK_ENABLED) - -//------------------------------------------------------------------------------ -// TIMER - -#if defined(TIMER_ENABLED) - -#undef NRFX_TIMER_ENABLED -#define NRFX_TIMER_ENABLED TIMER_ENABLED - -#if defined(TIMER0_ENABLED) -#undef NRFX_TIMER0_ENABLED -#define NRFX_TIMER0_ENABLED TIMER0_ENABLED -#endif -#if defined(TIMER1_ENABLED) -#undef NRFX_TIMER1_ENABLED -#define NRFX_TIMER1_ENABLED TIMER1_ENABLED -#endif -#if defined(TIMER2_ENABLED) -#undef NRFX_TIMER2_ENABLED -#define NRFX_TIMER2_ENABLED TIMER2_ENABLED -#endif -#if defined(TIMER3_ENABLED) -#undef NRFX_TIMER3_ENABLED -#define NRFX_TIMER3_ENABLED TIMER3_ENABLED -#endif -#if defined(TIMER4_ENABLED) -#undef NRFX_TIMER4_ENABLED -#define NRFX_TIMER4_ENABLED TIMER4_ENABLED -#endif - -#if defined(TIMER_DEFAULT_CONFIG_FREQUENCY) -#undef NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY -#define NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY TIMER_DEFAULT_CONFIG_FREQUENCY -#endif -#if defined(TIMER_DEFAULT_CONFIG_MODE) -#undef NRFX_TIMER_DEFAULT_CONFIG_MODE -#define NRFX_TIMER_DEFAULT_CONFIG_MODE TIMER_DEFAULT_CONFIG_MODE -#endif -#if defined(TIMER_DEFAULT_CONFIG_BIT_WIDTH) -#undef NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH -#define NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH TIMER_DEFAULT_CONFIG_BIT_WIDTH -#endif -#if defined(TIMER_DEFAULT_CONFIG_IRQ_PRIORITY) -#undef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY TIMER_DEFAULT_CONFIG_IRQ_PRIORITY -#endif - -#if defined(TIMER_CONFIG_LOG_ENABLED) -#undef NRFX_TIMER_CONFIG_LOG_ENABLED -#define NRFX_TIMER_CONFIG_LOG_ENABLED TIMER_CONFIG_LOG_ENABLED -#endif -#if defined(TIMER_CONFIG_LOG_LEVEL) -#undef NRFX_TIMER_CONFIG_LOG_LEVEL -#define NRFX_TIMER_CONFIG_LOG_LEVEL TIMER_CONFIG_LOG_LEVEL -#endif -#if defined(TIMER_CONFIG_INFO_COLOR) -#undef NRFX_TIMER_CONFIG_INFO_COLOR -#define NRFX_TIMER_CONFIG_INFO_COLOR TIMER_CONFIG_INFO_COLOR -#endif -#if defined(TIMER_CONFIG_DEBUG_COLOR) -#undef NRFX_TIMER_CONFIG_DEBUG_COLOR -#define NRFX_TIMER_CONFIG_DEBUG_COLOR TIMER_CONFIG_DEBUG_COLOR -#endif - -#endif // defined(TIMER_ENABLED) - -//------------------------------------------------------------------------------ -// TWI -#define TWI_ONLY ( defined(TWI_PRESENT) && !defined(TWIM_PRESENT)) -#define TWIM_ONLY (!defined(TWI_PRESENT) && defined(TWIM_PRESENT)) -#define TWI_AND_TWIM ( defined(TWI_PRESENT) && defined(TWIM_PRESENT)) - -#if defined(TWI_ENABLED) - -#undef NRFX_TWI_ENABLED -#define NRFX_TWI_ENABLED (TWI_ENABLED && (NRFX_TWI0_ENABLED || NRFX_TWI1_ENABLED)) -#undef NRFX_TWIM_ENABLED -#define NRFX_TWIM_ENABLED (TWI_ENABLED && (NRFX_TWIM0_ENABLED || NRFX_TWIM1_ENABLED)) - -#if defined(TWI_PRESENT) && !defined(TWIM_PRESENT) - -#undef NRFX_TWI0_ENABLED -#define NRFX_TWI0_ENABLED TWI0_ENABLED -#undef NRFX_TWIM0_ENABLED -#define NRFX_TWIM0_ENABLED 0 - -#undef NRFX_TWI1_ENABLED -#define NRFX_TWI1_ENABLED TWI1_ENABLED -#undef NRFX_TWIM1_ENABLED -#define NRFX_TWIM1_ENABLED 0 - -#elif !defined(TWI_PRESENT) && defined(TWIM_PRESENT) - -#undef NRFX_TWI0_ENABLED -#define NRFX_TWI0_ENABLED 0 -#undef NRFX_TWIM0_ENABLED -#define NRFX_TWIM0_ENABLED TWI0_ENABLED - -#undef NRFX_TWI1_ENABLED -#define NRFX_TWI1_ENABLED 0 -#undef NRFX_TWIM1_ENABLED -#define NRFX_TWIM1_ENABLED TWI1_ENABLED - -#else // -> defined(TWI_PRESENT) && defined(TWIM_PRESENT) - -#undef NRFX_TWI0_ENABLED -#define NRFX_TWI0_ENABLED (TWI0_ENABLED && !TWI0_USE_EASY_DMA) -#undef NRFX_TWIM0_ENABLED -#define NRFX_TWIM0_ENABLED (TWI0_ENABLED && TWI0_USE_EASY_DMA) - -#undef NRFX_TWI1_ENABLED -#define NRFX_TWI1_ENABLED (TWI1_ENABLED && !TWI1_USE_EASY_DMA) -#undef NRFX_TWIM1_ENABLED -#define NRFX_TWIM1_ENABLED (TWI1_ENABLED && TWI1_USE_EASY_DMA) - -#endif // -> defined(TWI_PRESENT) && defined(TWIM_PRESENT) - -#if defined(TWI_DEFAULT_CONFIG_FREQUENCY) -#undef NRFX_TWI_DEFAULT_CONFIG_FREQUENCY -#define NRFX_TWI_DEFAULT_CONFIG_FREQUENCY TWI_DEFAULT_CONFIG_FREQUENCY -#undef NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY -#define NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY TWI_DEFAULT_CONFIG_FREQUENCY -#endif -#if defined(TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT) -#undef NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT -#define NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT -#undef NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT -#define NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT -#endif -#if defined(TWI_DEFAULT_CONFIG_IRQ_PRIORITY) -#undef NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY TWI_DEFAULT_CONFIG_IRQ_PRIORITY -#undef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY TWI_DEFAULT_CONFIG_IRQ_PRIORITY -#endif - -#if defined(TWI_CONFIG_LOG_ENABLED) -#undef NRFX_TWI_CONFIG_LOG_ENABLED -#define NRFX_TWI_CONFIG_LOG_ENABLED TWI_CONFIG_LOG_ENABLED -#undef NRFX_TWIM_CONFIG_LOG_ENABLED -#define NRFX_TWIM_CONFIG_LOG_ENABLED TWI_CONFIG_LOG_ENABLED -#endif -#if defined(TWI_CONFIG_LOG_LEVEL) -#undef NRFX_TWI_CONFIG_LOG_LEVEL -#define NRFX_TWI_CONFIG_LOG_LEVEL TWI_CONFIG_LOG_LEVEL -#undef NRFX_TWIM_CONFIG_LOG_LEVEL -#define NRFX_TWIM_CONFIG_LOG_LEVEL TWI_CONFIG_LOG_LEVEL -#endif -#if defined(TWI_CONFIG_INFO_COLOR) -#undef NRFX_TWI_CONFIG_INFO_COLOR -#define NRFX_TWI_CONFIG_INFO_COLOR TWI_CONFIG_INFO_COLOR -#undef NRFX_TWIM_CONFIG_INFO_COLOR -#define NRFX_TWIM_CONFIG_INFO_COLOR TWI_CONFIG_INFO_COLOR -#endif -#if defined(TWI_CONFIG_DEBUG_COLOR) -#undef NRFX_TWI_CONFIG_DEBUG_COLOR -#define NRFX_TWI_CONFIG_DEBUG_COLOR TWI_CONFIG_DEBUG_COLOR -#undef NRFX_TWIM_CONFIG_DEBUG_COLOR -#define NRFX_TWIM_CONFIG_DEBUG_COLOR TWI_CONFIG_DEBUG_COLOR -#endif - -#if defined(TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED) -#undef NRFX_TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED -#define NRFX_TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED -#endif - -#endif // defined(TWI_ENABLED) - -//------------------------------------------------------------------------------ -// TWIS - -#if defined(TWIS_ENABLED) - -#undef NRFX_TWIS_ENABLED -#define NRFX_TWIS_ENABLED TWIS_ENABLED - -#if defined(TWIS0_ENABLED) -#undef NRFX_TWIS0_ENABLED -#define NRFX_TWIS0_ENABLED TWIS0_ENABLED -#endif -#if defined(TWIS1_ENABLED) -#undef NRFX_TWIS1_ENABLED -#define NRFX_TWIS1_ENABLED TWIS1_ENABLED -#endif - -#if defined(TWIS_ASSUME_INIT_AFTER_RESET_ONLY) -#undef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY -#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY TWIS_ASSUME_INIT_AFTER_RESET_ONLY -#endif -#if defined(TWIS_NO_SYNC_MODE) -#undef NRFX_TWIS_NO_SYNC_MODE -#define NRFX_TWIS_NO_SYNC_MODE TWIS_NO_SYNC_MODE -#endif - -#if defined(TWIS_DEFAULT_CONFIG_ADDR0) -#undef NRFX_TWIS_DEFAULT_CONFIG_ADDR0 -#define NRFX_TWIS_DEFAULT_CONFIG_ADDR0 TWIS_DEFAULT_CONFIG_ADDR0 -#endif -#if defined(TWIS_DEFAULT_CONFIG_ADDR1) -#undef NRFX_TWIS_DEFAULT_CONFIG_ADDR1 -#define NRFX_TWIS_DEFAULT_CONFIG_ADDR1 TWIS_DEFAULT_CONFIG_ADDR1 -#endif -#if defined(TWIS_DEFAULT_CONFIG_SCL_PULL) -#undef NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL -#define NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL TWIS_DEFAULT_CONFIG_SCL_PULL -#endif -#if defined(TWIS_DEFAULT_CONFIG_SDA_PULL) -#undef NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL -#define NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL TWIS_DEFAULT_CONFIG_SDA_PULL -#endif -#if defined(TWIS_DEFAULT_CONFIG_IRQ_PRIORITY) -#undef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY TWIS_DEFAULT_CONFIG_IRQ_PRIORITY -#endif - -#if defined(TWIS_CONFIG_LOG_ENABLED) -#undef NRFX_TWIS_CONFIG_LOG_ENABLED -#define NRFX_TWIS_CONFIG_LOG_ENABLED TWIS_CONFIG_LOG_ENABLED -#endif -#if defined(TWIS_CONFIG_LOG_LEVEL) -#undef NRFX_TWIS_CONFIG_LOG_LEVEL -#define NRFX_TWIS_CONFIG_LOG_LEVEL TWIS_CONFIG_LOG_LEVEL -#endif -#if defined(TWIS_CONFIG_INFO_COLOR) -#undef NRFX_TWIS_CONFIG_INFO_COLOR -#define NRFX_TWIS_CONFIG_INFO_COLOR TWIS_CONFIG_INFO_COLOR -#endif -#if defined(TWIS_CONFIG_DEBUG_COLOR) -#undef NRFX_TWIS_CONFIG_DEBUG_COLOR -#define NRFX_TWIS_CONFIG_DEBUG_COLOR TWIS_CONFIG_DEBUG_COLOR -#endif - -#endif // defined(TWIS_ENABLED) - -//------------------------------------------------------------------------------ -// UART - -#if defined(UART_ENABLED) - -#undef NRFX_UART_ENABLED -#define NRFX_UART_ENABLED (UART_ENABLED && NRFX_UART0_ENABLED) -#undef NRFX_UARTE_ENABLED -#define NRFX_UARTE_ENABLED (UART_ENABLED && (NRFX_UARTE0_ENABLED || NRFX_UARTE1_ENABLED)) - -#if defined(UART0_ENABLED) -#undef NRFX_UART0_ENABLED -#define NRFX_UART0_ENABLED (UART0_ENABLED && UART_LEGACY_SUPPORT) -#undef NRFX_UARTE0_ENABLED -#define NRFX_UARTE0_ENABLED (UART0_ENABLED && UART_EASY_DMA_SUPPORT) -#endif -#if defined(UART1_ENABLED) -#undef NRFX_UARTE1_ENABLED -#define NRFX_UARTE1_ENABLED (UART1_ENABLED && UART_EASY_DMA_SUPPORT) -#endif - -#if defined(UART_DEFAULT_CONFIG_HWFC) -#undef NRFX_UART_DEFAULT_CONFIG_HWFC -#define NRFX_UART_DEFAULT_CONFIG_HWFC UART_DEFAULT_CONFIG_HWFC -#undef NRFX_UARTE_DEFAULT_CONFIG_HWFC -#define NRFX_UARTE_DEFAULT_CONFIG_HWFC UART_DEFAULT_CONFIG_HWFC -#endif -#if defined(UART_DEFAULT_CONFIG_PARITY) -#undef NRFX_UART_DEFAULT_CONFIG_PARITY -#define NRFX_UART_DEFAULT_CONFIG_PARITY UART_DEFAULT_CONFIG_PARITY -#undef NRFX_UARTE_DEFAULT_CONFIG_PARITY -#define NRFX_UARTE_DEFAULT_CONFIG_PARITY UART_DEFAULT_CONFIG_PARITY -#endif -#if defined(UART_DEFAULT_CONFIG_BAUDRATE) -#undef NRFX_UART_DEFAULT_CONFIG_BAUDRATE -#define NRFX_UART_DEFAULT_CONFIG_BAUDRATE UART_DEFAULT_CONFIG_BAUDRATE -#undef NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE -#define NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE UART_DEFAULT_CONFIG_BAUDRATE -#endif -#if defined(UART_DEFAULT_CONFIG_IRQ_PRIORITY) -#undef NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY UART_DEFAULT_CONFIG_IRQ_PRIORITY -#undef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY UART_DEFAULT_CONFIG_IRQ_PRIORITY -#endif - -#if defined(UART_CONFIG_LOG_ENABLED) -#undef NRFX_UART_CONFIG_LOG_ENABLED -#define NRFX_UART_CONFIG_LOG_ENABLED UART_CONFIG_LOG_ENABLED -#undef NRFX_UARTE_CONFIG_LOG_ENABLED -#define NRFX_UARTE_CONFIG_LOG_ENABLED UART_CONFIG_LOG_ENABLED -#endif -#if defined(UART_CONFIG_LOG_LEVEL) -#undef NRFX_UART_CONFIG_LOG_LEVEL -#define NRFX_UART_CONFIG_LOG_LEVEL UART_CONFIG_LOG_LEVEL -#undef NRFX_UARTE_CONFIG_LOG_LEVEL -#define NRFX_UARTE_CONFIG_LOG_LEVEL UART_CONFIG_LOG_LEVEL -#endif -#if defined(UART_CONFIG_INFO_COLOR) -#undef NRFX_UART_CONFIG_INFO_COLOR -#define NRFX_UART_CONFIG_INFO_COLOR UART_CONFIG_INFO_COLOR -#undef NRFX_UARTE_CONFIG_INFO_COLOR -#define NRFX_UARTE_CONFIG_INFO_COLOR UART_CONFIG_INFO_COLOR -#endif -#if defined(UART_CONFIG_DEBUG_COLOR) -#undef NRFX_UART_CONFIG_DEBUG_COLOR -#define NRFX_UART_CONFIG_DEBUG_COLOR UART_CONFIG_DEBUG_COLOR -#undef NRFX_UARTE_CONFIG_DEBUG_COLOR -#define NRFX_UARTE_CONFIG_DEBUG_COLOR UART_CONFIG_DEBUG_COLOR -#endif - -#endif // defined(UART_ENABLED) - -//------------------------------------------------------------------------------ -// WDT - -#if defined(WDT_ENABLED) - -#undef NRFX_WDT_ENABLED -#define NRFX_WDT_ENABLED WDT_ENABLED - -#if defined(WDT_CONFIG_BEHAVIOUR) -#undef NRFX_WDT_CONFIG_BEHAVIOUR -#define NRFX_WDT_CONFIG_BEHAVIOUR WDT_CONFIG_BEHAVIOUR -#endif -#if defined(WDT_CONFIG_RELOAD_VALUE) -#undef NRFX_WDT_CONFIG_RELOAD_VALUE -#define NRFX_WDT_CONFIG_RELOAD_VALUE WDT_CONFIG_RELOAD_VALUE -#endif -#if defined(WDT_CONFIG_IRQ_PRIORITY) -#undef NRFX_WDT_CONFIG_IRQ_PRIORITY -#define NRFX_WDT_CONFIG_IRQ_PRIORITY WDT_CONFIG_IRQ_PRIORITY -#endif - -#if defined(WDT_CONFIG_LOG_ENABLED) -#undef NRFX_WDT_CONFIG_LOG_ENABLED -#define NRFX_WDT_CONFIG_LOG_ENABLED WDT_CONFIG_LOG_ENABLED -#endif -#if defined(WDT_CONFIG_LOG_LEVEL) -#undef NRFX_WDT_CONFIG_LOG_LEVEL -#define NRFX_WDT_CONFIG_LOG_LEVEL WDT_CONFIG_LOG_LEVEL -#endif -#if defined(WDT_CONFIG_INFO_COLOR) -#undef NRFX_WDT_CONFIG_INFO_COLOR -#define NRFX_WDT_CONFIG_INFO_COLOR WDT_CONFIG_INFO_COLOR -#endif -#if defined(WDT_CONFIG_DEBUG_COLOR) -#undef NRFX_WDT_CONFIG_DEBUG_COLOR -#define NRFX_WDT_CONFIG_DEBUG_COLOR WDT_CONFIG_DEBUG_COLOR -#endif - -#endif // defined(WDT_ENABLED) - -#endif // APPLY_OLD_CONFIG_H__ diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_clock.c b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_clock.c deleted file mode 100644 index 3c93659510..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_clock.c +++ /dev/null @@ -1,603 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include -#include "nrf_drv_clock.h" - -#if NRF_MODULE_ENABLED(CLOCK) - -#ifdef SOFTDEVICE_PRESENT -#include "nrf_sdh.h" -#include "nrf_sdh_soc.h" -#endif - -#define NRF_LOG_MODULE_NAME clock -#if CLOCK_CONFIG_LOG_ENABLED - #define NRF_LOG_LEVEL CLOCK_CONFIG_LOG_LEVEL - #define NRF_LOG_INFO_COLOR CLOCK_CONFIG_INFO_COLOR - #define NRF_LOG_DEBUG_COLOR CLOCK_CONFIG_DEBUG_COLOR -#else //CLOCK_CONFIG_LOG_ENABLED - #define NRF_LOG_LEVEL 0 -#endif //CLOCK_CONFIG_LOG_ENABLED -#include "nrf_log.h" -NRF_LOG_MODULE_REGISTER(); - -#define EVT_TO_STR(event) \ - (event == NRF_CLOCK_EVENT_HFCLKSTARTED ? "NRF_CLOCK_EVENT_HFCLKSTARTED" : \ - (event == NRF_CLOCK_EVENT_LFCLKSTARTED ? "NRF_CLOCK_EVENT_LFCLKSTARTED" : \ - (event == NRF_CLOCK_EVENT_DONE ? "NRF_CLOCK_EVENT_DONE" : \ - (event == NRF_CLOCK_EVENT_CTTO ? "NRF_CLOCK_EVENT_CTTO" : \ - "UNKNOWN EVENT")))) - - -/*lint -save -e652 */ -#define NRF_CLOCK_LFCLK_RC CLOCK_LFCLKSRC_SRC_RC -#define NRF_CLOCK_LFCLK_Xtal CLOCK_LFCLKSRC_SRC_Xtal -#define NRF_CLOCK_LFCLK_Synth CLOCK_LFCLKSRC_SRC_Synth -/*lint -restore */ - -#if (CLOCK_CONFIG_LF_SRC == NRF_CLOCK_LFCLK_RC) && !defined(SOFTDEVICE_PRESENT) -#define CALIBRATION_SUPPORT 1 -#else -#define CALIBRATION_SUPPORT 0 -#endif -typedef enum -{ - CAL_STATE_IDLE, - CAL_STATE_CT, - CAL_STATE_HFCLK_REQ, - CAL_STATE_CAL, - CAL_STATE_ABORT, -} nrf_drv_clock_cal_state_t; - -/**@brief CLOCK control block. */ -typedef struct -{ - bool module_initialized; /*< Indicate the state of module */ - volatile bool hfclk_on; /*< High-frequency clock state. */ - volatile bool lfclk_on; /*< Low-frequency clock state. */ - volatile uint32_t hfclk_requests; /*< High-frequency clock request counter. */ - volatile nrf_drv_clock_handler_item_t * p_hf_head; - volatile uint32_t lfclk_requests; /*< Low-frequency clock request counter. */ - volatile nrf_drv_clock_handler_item_t * p_lf_head; -#if CALIBRATION_SUPPORT - nrf_drv_clock_handler_item_t cal_hfclk_started_handler_item; - nrf_drv_clock_event_handler_t cal_done_handler; - volatile nrf_drv_clock_cal_state_t cal_state; -#endif // CALIBRATION_SUPPORT -} nrf_drv_clock_cb_t; - -static nrf_drv_clock_cb_t m_clock_cb; - -static void clock_irq_handler(nrfx_clock_evt_type_t evt); - -static void lfclk_stop(void) -{ -#if CALIBRATION_SUPPORT - nrfx_clock_calibration_timer_stop(); -#endif - -#ifdef SOFTDEVICE_PRESENT - // If LFCLK is requested to stop while SD is still enabled, - // it indicates an error in the application. - // Enabling SD should increment the LFCLK request. - ASSERT(!nrf_sdh_is_enabled()); -#endif // SOFTDEVICE_PRESENT - - nrfx_clock_lfclk_stop(); - m_clock_cb.lfclk_on = false; -} - -static void hfclk_start(void) -{ -#ifdef SOFTDEVICE_PRESENT - if (nrf_sdh_is_enabled()) - { - (void)sd_clock_hfclk_request(); - return; - } -#endif // SOFTDEVICE_PRESENT - - nrfx_clock_hfclk_start(); -} - -static void hfclk_stop(void) -{ -#ifdef SOFTDEVICE_PRESENT - if (nrf_sdh_is_enabled()) - { - (void)sd_clock_hfclk_release(); - m_clock_cb.hfclk_on = false; - return; - } -#endif // SOFTDEVICE_PRESENT - - nrfx_clock_hfclk_stop(); - m_clock_cb.hfclk_on = false; -} - -bool nrf_drv_clock_init_check(void) -{ - return m_clock_cb.module_initialized; -} - -ret_code_t nrf_drv_clock_init(void) -{ - ret_code_t err_code = NRF_SUCCESS; - if (m_clock_cb.module_initialized) - { - err_code = NRF_ERROR_MODULE_ALREADY_INITIALIZED; - } - else - { - m_clock_cb.p_hf_head = NULL; - m_clock_cb.hfclk_requests = 0; - m_clock_cb.p_lf_head = NULL; - m_clock_cb.lfclk_requests = 0; - err_code = nrfx_clock_init(clock_irq_handler); -#ifdef SOFTDEVICE_PRESENT - if (!nrf_sdh_is_enabled()) -#endif - { - nrfx_clock_enable(); - } - -#if CALIBRATION_SUPPORT - m_clock_cb.cal_state = CAL_STATE_IDLE; -#endif - - m_clock_cb.module_initialized = true; - } - - NRF_LOG_INFO("Function: %s, error code: %s.", - (uint32_t)__func__, - (uint32_t)NRF_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -void nrf_drv_clock_uninit(void) -{ - ASSERT(m_clock_cb.module_initialized); - nrfx_clock_disable(); - nrfx_clock_uninit(); -} - -static void item_enqueue(nrf_drv_clock_handler_item_t ** p_head, - nrf_drv_clock_handler_item_t * p_item) -{ - nrf_drv_clock_handler_item_t * p_next = *p_head; - while (p_next) - { - if (p_next == p_item) - { - return; - } - p_next = p_next->p_next; - } - - p_item->p_next = (*p_head ? *p_head : NULL); - *p_head = p_item; -} - -static nrf_drv_clock_handler_item_t * item_dequeue(nrf_drv_clock_handler_item_t ** p_head) -{ - nrf_drv_clock_handler_item_t * p_item = *p_head; - if (p_item) - { - *p_head = p_item->p_next; - } - return p_item; -} - -void nrf_drv_clock_lfclk_request(nrf_drv_clock_handler_item_t * p_handler_item) -{ - ASSERT(m_clock_cb.module_initialized); - - if (m_clock_cb.lfclk_on) - { - if (p_handler_item) - { - p_handler_item->event_handler(NRF_DRV_CLOCK_EVT_LFCLK_STARTED); - } - CRITICAL_REGION_ENTER(); - ++(m_clock_cb.lfclk_requests); - CRITICAL_REGION_EXIT(); - } - else - { - CRITICAL_REGION_ENTER(); - if (p_handler_item) - { - item_enqueue((nrf_drv_clock_handler_item_t **)&m_clock_cb.p_lf_head, - p_handler_item); - } - if (m_clock_cb.lfclk_requests == 0) - { - nrfx_clock_lfclk_start(); - } - ++(m_clock_cb.lfclk_requests); - CRITICAL_REGION_EXIT(); - } - - ASSERT(m_clock_cb.lfclk_requests > 0); -} - -void nrf_drv_clock_lfclk_release(void) -{ - ASSERT(m_clock_cb.module_initialized); - ASSERT(m_clock_cb.lfclk_requests > 0); - - CRITICAL_REGION_ENTER(); - --(m_clock_cb.lfclk_requests); - if (m_clock_cb.lfclk_requests == 0) - { - lfclk_stop(); - } - CRITICAL_REGION_EXIT(); -} - -bool nrf_drv_clock_lfclk_is_running(void) -{ - ASSERT(m_clock_cb.module_initialized); - -#ifdef SOFTDEVICE_PRESENT - if (nrf_sdh_is_enabled()) - { - return true; - } -#endif // SOFTDEVICE_PRESENT - - return nrfx_clock_lfclk_is_running(); -} - -void nrf_drv_clock_hfclk_request(nrf_drv_clock_handler_item_t * p_handler_item) -{ - ASSERT(m_clock_cb.module_initialized); - - if (m_clock_cb.hfclk_on) - { - if (p_handler_item) - { - p_handler_item->event_handler(NRF_DRV_CLOCK_EVT_HFCLK_STARTED); - } - CRITICAL_REGION_ENTER(); - ++(m_clock_cb.hfclk_requests); - CRITICAL_REGION_EXIT(); - } - else - { - CRITICAL_REGION_ENTER(); - if (p_handler_item) - { - item_enqueue((nrf_drv_clock_handler_item_t **)&m_clock_cb.p_hf_head, - p_handler_item); - } - if (m_clock_cb.hfclk_requests == 0) - { - hfclk_start(); - } - ++(m_clock_cb.hfclk_requests); - CRITICAL_REGION_EXIT(); - } - - ASSERT(m_clock_cb.hfclk_requests > 0); -} - -void nrf_drv_clock_hfclk_release(void) -{ - ASSERT(m_clock_cb.module_initialized); - ASSERT(m_clock_cb.hfclk_requests > 0); - - CRITICAL_REGION_ENTER(); - --(m_clock_cb.hfclk_requests); - if (m_clock_cb.hfclk_requests == 0) - { - hfclk_stop(); - } - CRITICAL_REGION_EXIT(); -} - -bool nrf_drv_clock_hfclk_is_running(void) -{ - ASSERT(m_clock_cb.module_initialized); - -#ifdef SOFTDEVICE_PRESENT - if (nrf_sdh_is_enabled()) - { - uint32_t is_running; - UNUSED_VARIABLE(sd_clock_hfclk_is_running(&is_running)); - return (is_running ? true : false); - } -#endif // SOFTDEVICE_PRESENT - - return nrfx_clock_hfclk_is_running(); -} - -#if CALIBRATION_SUPPORT -static void clock_calibration_hf_started(nrf_drv_clock_evt_type_t event) -{ - if (m_clock_cb.cal_state == CAL_STATE_ABORT) - { - nrf_drv_clock_hfclk_release(); - m_clock_cb.cal_state = CAL_STATE_IDLE; - if (m_clock_cb.cal_done_handler) - { - m_clock_cb.cal_done_handler(NRF_DRV_CLOCK_EVT_CAL_ABORTED); - } - } - else - { - ASSERT(event == NRF_DRV_CLOCK_EVT_HFCLK_STARTED); - if (nrfx_clock_calibration_start() != NRFX_SUCCESS) - { - ASSERT(false); - } - } -} -#endif // CALIBRATION_SUPPORT - -ret_code_t nrf_drv_clock_calibration_start(uint8_t interval, nrf_drv_clock_event_handler_t handler) -{ - ret_code_t err_code = NRF_SUCCESS; -#if CALIBRATION_SUPPORT - ASSERT(m_clock_cb.cal_state == CAL_STATE_IDLE); - if (m_clock_cb.lfclk_on == false) - { - err_code = NRF_ERROR_INVALID_STATE; - } - else if (m_clock_cb.cal_state == CAL_STATE_IDLE) - { - m_clock_cb.cal_done_handler = handler; - m_clock_cb.cal_hfclk_started_handler_item.event_handler = clock_calibration_hf_started; - if (interval == 0) - { - m_clock_cb.cal_state = CAL_STATE_HFCLK_REQ; - nrf_drv_clock_hfclk_request(&m_clock_cb.cal_hfclk_started_handler_item); - } - else - { - m_clock_cb.cal_state = CAL_STATE_CT; - nrfx_clock_calibration_timer_start(interval); - } - } - else - { - err_code = NRF_ERROR_BUSY; - } - NRF_LOG_WARNING("Function: %s, error code: %s.", - (uint32_t)__func__, - (uint32_t)NRF_LOG_ERROR_STRING_GET(err_code)); - return err_code; -#else - UNUSED_PARAMETER(interval); - UNUSED_PARAMETER(handler); - err_code = NRF_ERROR_FORBIDDEN; - NRF_LOG_WARNING("Function: %s, error code: %s.", - (uint32_t)__func__, - (uint32_t)NRF_LOG_ERROR_STRING_GET(err_code)); - return err_code; -#endif // CALIBRATION_SUPPORT -} - -ret_code_t nrf_drv_clock_calibration_abort(void) -{ - ret_code_t err_code = NRF_SUCCESS; -#if CALIBRATION_SUPPORT - CRITICAL_REGION_ENTER(); - switch (m_clock_cb.cal_state) - { - case CAL_STATE_CT: - nrfx_clock_calibration_timer_stop(); - m_clock_cb.cal_state = CAL_STATE_IDLE; - if (m_clock_cb.cal_done_handler) - { - m_clock_cb.cal_done_handler(NRF_DRV_CLOCK_EVT_CAL_ABORTED); - } - break; - case CAL_STATE_HFCLK_REQ: - /* fall through. */ - case CAL_STATE_CAL: - m_clock_cb.cal_state = CAL_STATE_ABORT; - break; - default: - break; - } - CRITICAL_REGION_EXIT(); - - NRF_LOG_INFO("Function: %s, error code: %s.", - (uint32_t)__func__, - (uint32_t)NRF_LOG_ERROR_STRING_GET(err_code)); - return err_code; -#else - err_code = NRF_ERROR_FORBIDDEN; - NRF_LOG_WARNING("Function: %s, error code: %s.", - (uint32_t)__func__, - (uint32_t)NRF_LOG_ERROR_STRING_GET(err_code)); - return err_code; -#endif // CALIBRATION_SUPPORT -} - -ret_code_t nrf_drv_clock_is_calibrating(bool * p_is_calibrating) -{ - ret_code_t err_code = NRF_SUCCESS; -#if CALIBRATION_SUPPORT - ASSERT(m_clock_cb.module_initialized); - *p_is_calibrating = (m_clock_cb.cal_state != CAL_STATE_IDLE); - NRF_LOG_INFO("Function: %s, error code: %s.", - (uint32_t)__func__, - (uint32_t)NRF_LOG_ERROR_STRING_GET(err_code)); - return err_code; -#else - UNUSED_PARAMETER(p_is_calibrating); - err_code = NRF_ERROR_FORBIDDEN; - NRF_LOG_WARNING("Function: %s, error code: %s.", - (uint32_t)__func__, - (uint32_t)NRF_LOG_ERROR_STRING_GET(err_code)); - return err_code; -#endif // CALIBRATION_SUPPORT -} - -__STATIC_INLINE void clock_clk_started_notify(nrf_drv_clock_evt_type_t evt_type) -{ - nrf_drv_clock_handler_item_t **p_head; - if (evt_type == NRF_DRV_CLOCK_EVT_HFCLK_STARTED) - { - p_head = (nrf_drv_clock_handler_item_t **)&m_clock_cb.p_hf_head; - } - else - { - p_head = (nrf_drv_clock_handler_item_t **)&m_clock_cb.p_lf_head; - } - - while (1) - { - nrf_drv_clock_handler_item_t * p_item = item_dequeue(p_head); - if (!p_item) - { - break; - } - - p_item->event_handler(evt_type); - } -} - -static void clock_irq_handler(nrfx_clock_evt_type_t evt) -{ - if (evt == NRFX_CLOCK_EVT_HFCLK_STARTED) - { - m_clock_cb.hfclk_on = true; - clock_clk_started_notify(NRF_DRV_CLOCK_EVT_HFCLK_STARTED); - } - if (evt == NRFX_CLOCK_EVT_LFCLK_STARTED) - { - m_clock_cb.lfclk_on = true; - clock_clk_started_notify(NRF_DRV_CLOCK_EVT_LFCLK_STARTED); - } -#if CALIBRATION_SUPPORT - if (evt == NRFX_CLOCK_EVT_CTTO) - { - nrf_drv_clock_hfclk_request(&m_clock_cb.cal_hfclk_started_handler_item); - } - - if (evt == NRFX_CLOCK_EVT_CAL_DONE) - { - nrf_drv_clock_hfclk_release(); - bool aborted = (m_clock_cb.cal_state == CAL_STATE_ABORT); - m_clock_cb.cal_state = CAL_STATE_IDLE; - if (m_clock_cb.cal_done_handler) - { - m_clock_cb.cal_done_handler(aborted ? - NRF_DRV_CLOCK_EVT_CAL_ABORTED : NRF_DRV_CLOCK_EVT_CAL_DONE); - } - } -#endif // CALIBRATION_SUPPORT -} - -#ifdef SOFTDEVICE_PRESENT -/** - * @brief SoftDevice SoC event handler. - * - * @param[in] evt_id SoC event. - * @param[in] p_context Context. - */ -static void soc_evt_handler(uint32_t evt_id, void * p_context) -{ - if (evt_id == NRF_EVT_HFCLKSTARTED) - { - m_clock_cb.hfclk_on = true; - clock_clk_started_notify(NRF_DRV_CLOCK_EVT_HFCLK_STARTED); - } -} -NRF_SDH_SOC_OBSERVER(m_soc_evt_observer, CLOCK_CONFIG_SOC_OBSERVER_PRIO, soc_evt_handler, NULL); - -/** - * @brief SoftDevice enable/disable state handler. - * - * @param[in] state State. - * @param[in] p_context Context. - */ -static void sd_state_evt_handler(nrf_sdh_state_evt_t state, void * p_context) -{ - switch (state) - { - case NRF_SDH_EVT_STATE_ENABLE_PREPARE: - NVIC_DisableIRQ(POWER_CLOCK_IRQn); - break; - - case NRF_SDH_EVT_STATE_ENABLED: - CRITICAL_REGION_ENTER(); - /* Make sure that nrf_drv_clock module is initialized */ - if (!m_clock_cb.module_initialized) - { - (void)nrf_drv_clock_init(); - } - /* SD is one of the LFCLK requesters, but it will enable it by itself. */ - ++(m_clock_cb.lfclk_requests); - m_clock_cb.lfclk_on = true; - CRITICAL_REGION_EXIT(); - break; - - case NRF_SDH_EVT_STATE_DISABLED: - /* Reinit interrupts */ - ASSERT(m_clock_cb.module_initialized); - nrfx_clock_enable(); - - /* SD leaves LFCLK enabled - disable it if it is no longer required. */ - nrf_drv_clock_lfclk_release(); - break; - - default: - break; - } -} - -NRF_SDH_STATE_OBSERVER(m_sd_state_observer, CLOCK_CONFIG_STATE_OBSERVER_PRIO) = -{ - .handler = sd_state_evt_handler, - .p_context = NULL, -}; - -#endif // SOFTDEVICE_PRESENT - -#undef NRF_CLOCK_LFCLK_RC -#undef NRF_CLOCK_LFCLK_Xtal -#undef NRF_CLOCK_LFCLK_Synth - -#endif // NRF_MODULE_ENABLED(CLOCK) diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_clock.h b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_clock.h deleted file mode 100644 index d38533a4c5..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_clock.h +++ /dev/null @@ -1,297 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef NRF_DRV_CLOCK_H__ -#define NRF_DRV_CLOCK_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_drv_clock Clock driver - legacy layer - * @{ - * @ingroup nrf_clock - * - * @brief Layer providing compatibility with the former API. - */ - -/** - * @brief Clock events. - */ -typedef enum -{ - NRF_DRV_CLOCK_EVT_HFCLK_STARTED, ///< HFCLK has been started. - NRF_DRV_CLOCK_EVT_LFCLK_STARTED, ///< LFCLK has been started. - NRF_DRV_CLOCK_EVT_CAL_DONE, ///< Calibration is done. - NRF_DRV_CLOCK_EVT_CAL_ABORTED, ///< Calibration has been aborted. -} nrf_drv_clock_evt_type_t; - -/** - * @brief Clock event handler. - * - * @param[in] event Event. - */ -typedef void (*nrf_drv_clock_event_handler_t)(nrf_drv_clock_evt_type_t event); - -// Forward declaration of the nrf_drv_clock_handler_item_t type. -typedef struct nrf_drv_clock_handler_item_s nrf_drv_clock_handler_item_t; - -struct nrf_drv_clock_handler_item_s -{ - nrf_drv_clock_handler_item_t * p_next; ///< A pointer to the next handler that should be called when the clock is started. - nrf_drv_clock_event_handler_t event_handler; ///< Function to be called when the clock is started. -}; - -/** - * @brief Function for checking if driver is already initialized - * - * @retval true Driver is initialized - * @retval false Driver is uninitialized - */ -bool nrf_drv_clock_init_check(void); - -/** - * @brief Function for initializing the nrf_drv_clock module. - * - * After initialization, the module is in power off state (clocks are not requested). - * - * @retval NRF_SUCCESS If the procedure was successful. - * @retval NRF_ERROR_MODULE_ALREADY_INITIALIZED If the driver was already initialized. - */ -ret_code_t nrf_drv_clock_init(void); - -/** - * @brief Function for uninitializing the clock module. - * - */ -void nrf_drv_clock_uninit(void); - -/** - * @brief Function for requesting the LFCLK. - * - * The low-frequency clock can be requested by different modules - * or contexts. The driver ensures that the clock will be started only when it is requested - * the first time. If the clock is not ready but it was already started, the handler item that is - * provided as an input parameter is added to the list of handlers that will be notified - * when the clock is started. If the clock is already enabled, user callback is called from the - * current context. - * - * The first request will start the selected LFCLK source. If an event handler is - * provided, it will be called once the LFCLK is started. If the LFCLK was already started at this - * time, the event handler will be called from the context of this function. Additionally, - * the @ref nrf_drv_clock_lfclk_is_running function can be polled to check if the clock has started. - * - * @note When a SoftDevice is enabled, the LFCLK is always running and the driver cannot control it. - * - * @note The handler item provided by the user cannot be an automatic variable. - * - * @param[in] p_handler_item A pointer to the event handler structure. - */ -void nrf_drv_clock_lfclk_request(nrf_drv_clock_handler_item_t * p_handler_item); - -/** - * @brief Function for releasing the LFCLK. - * - * If there are no more requests, the LFCLK source will be stopped. - * - * @note When a SoftDevice is enabled, the LFCLK is always running. - */ -void nrf_drv_clock_lfclk_release(void); - -/** - * @brief Function for checking the LFCLK state. - * - * @retval true If the LFCLK is running. - * @retval false If the LFCLK is not running. - */ -bool nrf_drv_clock_lfclk_is_running(void); - -/** - * @brief Function for requesting the high-accuracy source HFCLK. - * - * The high-accuracy source - * can be requested by different modules or contexts. The driver ensures that the high-accuracy - * clock will be started only when it is requested the first time. If the clock is not ready - * but it was already started, the handler item that is provided as an input parameter is added - * to the list of handlers that will be notified when the clock is started. - * - * If an event handler is provided, it will be called once the clock is started. If the clock was already - * started at this time, the event handler will be called from the context of this function. Additionally, - * the @ref nrf_drv_clock_hfclk_is_running function can be polled to check if the clock has started. - * - * @note If a SoftDevice is running, the clock is managed by the SoftDevice and all requests are handled by - * the SoftDevice. This function cannot be called from all interrupt priority levels in that case. - * @note The handler item provided by the user cannot be an automatic variable. - * - * @param[in] p_handler_item A pointer to the event handler structure. - */ -void nrf_drv_clock_hfclk_request(nrf_drv_clock_handler_item_t * p_handler_item); - -/** - * @brief Function for releasing the high-accuracy source HFCLK. - * - * If there are no more requests, the high-accuracy source will be released. - */ -void nrf_drv_clock_hfclk_release(void); - -/** - * @brief Function for checking the HFCLK state. - * - * @retval true If the HFCLK is running (for \nRFXX XTAL source). - * @retval false If the HFCLK is not running. - */ -bool nrf_drv_clock_hfclk_is_running(void); - -/** - * @brief Function for starting a single calibration process. - * - * This function can also delay the start of calibration by a user-specified value. The delay will use - * a low-power timer that is part of the CLOCK module. @ref nrf_drv_clock_is_calibrating can be called to - * check if calibration is still in progress. If a handler is provided, the user can be notified when - * calibration is completed. The ext calibration can be started from the handler context. - * - * The calibration process consists of three phases: - * - Delay (optional) - * - Requesting the high-accuracy HFCLK - * - Hardware-supported calibration - * - * @param[in] delay Time after which the calibration will be started (in 0.25 s units). - * @param[in] handler NULL or user function to be called when calibration is completed or aborted. - * - * @retval NRF_SUCCESS If the procedure was successful. - * @retval NRF_ERROR_FORBIDDEN If a SoftDevice is present or the selected LFCLK source is not an RC oscillator. - * @retval NRF_ERROR_INVALID_STATE If the low-frequency clock is off. - * @retval NRF_ERROR_BUSY If calibration is in progress. - */ -ret_code_t nrf_drv_clock_calibration_start(uint8_t delay, nrf_drv_clock_event_handler_t handler); - -/** - * @brief Function for aborting calibration. - * - * This function aborts on-going calibration. If calibration was started, it cannot be stopped. If a handler - * was provided by @ref nrf_drv_clock_calibration_start, this handler will be called once - * aborted calibration is completed. @ref nrf_drv_clock_is_calibrating can also be used to check - * if the system is calibrating. - * - * @retval NRF_SUCCESS If the procedure was successful. - * @retval NRF_ERROR_FORBIDDEN If a SoftDevice is present or the selected LFCLK source is not an RC oscillator. - */ -ret_code_t nrf_drv_clock_calibration_abort(void); - -/** - * @brief Function for checking if calibration is in progress. - * - * This function indicates that the system is - * in calibration if it is in any of the calibration process phases (see @ref nrf_drv_clock_calibration_start). - * - * @param[out] p_is_calibrating True if calibration is in progress, false if not. - * - * @retval NRF_SUCCESS If the procedure was successful. - * @retval NRF_ERROR_FORBIDDEN If a SoftDevice is present or the selected LFCLK source is not an RC oscillator. - */ -ret_code_t nrf_drv_clock_is_calibrating(bool * p_is_calibrating); - -/**@brief Function for returning a requested task address for the clock driver module. - * - * @param[in] task One of the peripheral tasks. - * - * @return Task address. - */ -__STATIC_INLINE uint32_t nrf_drv_clock_ppi_task_addr(nrf_clock_task_t task); - -/**@brief Function for returning a requested event address for the clock driver module. - * - * @param[in] event One of the peripheral events. - * - * @return Event address. - */ -__STATIC_INLINE uint32_t nrf_drv_clock_ppi_event_addr(nrf_clock_event_t event); - - -#ifdef SOFTDEVICE_PRESENT -/** - * @brief Function called by the SoftDevice handler if an @ref NRF_SOC_EVTS event is received from the SoftDevice. - * - * @param[in] evt_id One of NRF_SOC_EVTS values. - */ -void nrf_drv_clock_on_soc_event(uint32_t evt_id); - -/** - * @brief Function called by the SoftDevice handler when the SoftDevice has been enabled. - * - * This function is called just after the SoftDevice has been properly enabled. - * Its main purpose is to mark that LFCLK has been requested by SD. - */ -void nrf_drv_clock_on_sd_enable(void); - -/** - * @brief Function called by the SoftDevice handler when the SoftDevice has been disabled. - * - * This function is called just after the SoftDevice has been properly disabled. - * It has two purposes: - * 1. Releases the LFCLK from the SD. - * 2. Reinitializes an interrupt after the SD releases POWER_CLOCK_IRQ. - */ -void nrf_drv_clock_on_sd_disable(void); - -#endif -/** - *@} - **/ - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION -__STATIC_INLINE uint32_t nrf_drv_clock_ppi_task_addr(nrf_clock_task_t task) -{ - return nrf_clock_task_address_get(task); -} - -__STATIC_INLINE uint32_t nrf_drv_clock_ppi_event_addr(nrf_clock_event_t event) -{ - return nrf_clock_event_address_get(event); -} -#endif //SUPPRESS_INLINE_IMPLEMENTATION - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_CLOCK_H__ diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_common.h b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_common.h deleted file mode 100644 index 54be7fbfda..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_common.h +++ /dev/null @@ -1,63 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_DRV_COMMON_H__ -#define NRF_DRV_COMMON_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#define INTERRUPT_PRIORITY_VALIDATION(pri) STATIC_ASSERT(INTERRUPT_PRIORITY_IS_VALID((pri))) -#define INTERRUPT_PRIORITY_ASSERT(pri) ASSERT(INTERRUPT_PRIORITY_IS_VALID((pri))) - -#define nrf_drv_irq_handler_t nrfx_irq_handler_t -#define nrf_drv_bitpos_to_event nrfx_bitpos_to_event -#define nrf_drv_event_to_bitpos nrfx_event_to_bitpos -#define nrf_drv_get_IRQn nrfx_get_irq_number -#define nrf_drv_is_in_RAM nrfx_is_in_ram - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_COMMON_H__ diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_comp.h b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_comp.h deleted file mode 100644 index 30c7b8e31c..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_comp.h +++ /dev/null @@ -1,137 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_DRV_COMP_H__ -#define NRF_DRV_COMP_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_drv_comp COMP driver - legacy layer - * @{ - * @ingroup nrf_comp - * - * @brief @tagAPI52 Layer providing compatibility with the former API. - */ - -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_comp_config_t nrf_drv_comp_config_t; - -/** @brief Macro for forwarding the new implementation. */ -#define VOLTAGE_THRESHOLD_TO_INT NRFX_VOLTAGE_THRESHOLD_TO_INT -/** @brief Macro for forwarding the new implementation. */ -#define COMP_CONFIG_TH NRFX_COMP_CONFIG_TH -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_COMP_DEFAULT_CONFIG NRFX_COMP_DEFAULT_CONFIG - -/** @brief Macro for forwarding the new implementation. */ -#define comp_events_handler_t nrfx_comp_event_handler_t -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_COMP_SHORT_STOP_AFTER_CROSS_EVT NRFX_COMP_SHORT_STOP_AFTER_CROSS_EVT -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_COMP_SHORT_STOP_AFTER_UP_EVT NRFX_COMP_SHORT_STOP_AFTER_UP_EVT -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_COMP_SHORT_STOP_AFTER_DOWN_EVT NRFX_COMP_SHORT_STOP_AFTER_DOWN_EVT -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_comp_short_mask_t nrfx_comp_short_mask_t -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_COMP_EVT_EN_CROSS_MASK NRFX_COMP_EVT_EN_CROSS_MASK -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_COMP_EVT_EN_UP_MASK NRFX_COMP_EVT_EN_UP_MASK -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_COMP_EVT_EN_DOWN_MASK NRFX_COMP_EVT_EN_DOWN_MASK -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_COMP_EVT_EN_READY_MASK NRFX_COMP_EVT_EN_READY_MASK -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_comp_evt_en_mask_t nrfx_comp_evt_en_mask_t - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_comp_uninit nrfx_comp_uninit -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_comp_pin_select nrfx_comp_pin_select -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_comp_start nrfx_comp_start -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_comp_stop nrfx_comp_stop -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_comp_sample nrfx_comp_sample - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_comp_task_address_get nrfx_comp_task_address_get -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_comp_event_address_get nrfx_comp_event_address_get - -/** - * @brief Function for initializing the COMP driver. - * - * This function initializes the COMP driver, but does not enable the peripheral or any interrupts. - * To start the driver, call the function @ref nrf_drv_comp_start() after initialization. - * - * If no configuration structure is provided, the driver is initialized with the default settings. - * - * @param[in] p_config Pointer to the structure with initial configuration. - * @param[in] event_handler Handler function. - * - * @retval NRF_ERROR_INVALID_PARAM If the configuration is invalid. - * @retval NRF_ERROR_INVALID_STATE If the driver has already been initialized. - * @retval NRF_ERROR_BUSY If the LPCOMP driver is initialized. - */ -__STATIC_INLINE ret_code_t nrf_drv_comp_init(nrf_drv_comp_config_t const * p_config, - comp_events_handler_t event_handler) -{ - if (p_config == NULL) - { - static nrfx_comp_config_t const default_config = NRFX_COMP_DEFAULT_CONFIG(NRF_COMP_INPUT_0); - p_config = &default_config; - } - return nrfx_comp_init(p_config, event_handler); -} - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_COMP_H__ diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_gpiote.h b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_gpiote.h deleted file mode 100644 index c3f6a698b1..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_gpiote.h +++ /dev/null @@ -1,139 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef NRF_DRV_GPIOTE_H__ -#define NRF_DRV_GPIOTE_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_drv_gpiote GPIOTE driver - legacy layer - * @{ - * @ingroup nrf_gpiote - * @brief Layer providing compatibility with the former API. - */ - -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_gpiote_in_config_t nrf_drv_gpiote_in_config_t; -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_gpiote_pin_t nrf_drv_gpiote_pin_t; -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_gpiote_out_config_t nrf_drv_gpiote_out_config_t; -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_gpiote_evt_handler_t nrf_drv_gpiote_evt_handler_t; - -/** @brief Macro for forwarding the new implementation. */ -#define GPIOTE_CONFIG_IN_SENSE_LOTOHI NRFX_GPIOTE_CONFIG_IN_SENSE_LOTOHI -/** @brief Macro for forwarding the new implementation. */ -#define GPIOTE_CONFIG_IN_SENSE_HITOLO NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO -/** @brief Macro for forwarding the new implementation. */ -#define GPIOTE_CONFIG_IN_SENSE_TOGGLE NRFX_GPIOTE_CONFIG_IN_SENSE_TOGGLE -/** @brief Macro for forwarding the new implementation. */ -#define GPIOTE_RAW_CONFIG_IN_SENSE_LOTOHI NRFX_GPIOTE_RAW_CONFIG_IN_SENSE_LOTOHI -/** @brief Macro for forwarding the new implementation. */ -#define GPIOTE_RAW_CONFIG_IN_SENSE_HITOLO NRFX_GPIOTE_RAW_CONFIG_IN_SENSE_HITOLO -/** @brief Macro for forwarding the new implementation. */ -#define GPIOTE_RAW_CONFIG_IN_SENSE_TOGGLE NRFX_GPIOTE_RAW_CONFIG_IN_SENSE_TOGGLE -/** @brief Macro for forwarding the new implementation. */ -#define GPIOTE_CONFIG_OUT_SIMPLE NRFX_GPIOTE_CONFIG_OUT_SIMPLE -/** @brief Macro for forwarding the new implementation. */ -#define GPIOTE_CONFIG_OUT_TASK_LOW NRFX_GPIOTE_CONFIG_OUT_TASK_LOW -/** @brief Macro for forwarding the new implementation. */ -#define GPIOTE_CONFIG_OUT_TASK_HIGH NRFX_GPIOTE_CONFIG_OUT_TASK_HIGH -/** @brief Macro for forwarding the new implementation. */ -#define GPIOTE_CONFIG_OUT_TASK_TOGGLE NRFX_GPIOTE_CONFIG_OUT_TASK_TOGGLE - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_gpiote_init nrfx_gpiote_init -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_gpiote_is_init nrfx_gpiote_is_init -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_gpiote_uninit nrfx_gpiote_uninit -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_gpiote_out_init nrfx_gpiote_out_init -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_gpiote_out_uninit nrfx_gpiote_out_uninit -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_gpiote_out_set nrfx_gpiote_out_set -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_gpiote_out_clear nrfx_gpiote_out_clear -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_gpiote_out_toggle nrfx_gpiote_out_toggle -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_gpiote_out_task_enable nrfx_gpiote_out_task_enable -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_gpiote_out_task_disable nrfx_gpiote_out_task_disable -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_gpiote_out_task_addr_get nrfx_gpiote_out_task_addr_get -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_gpiote_in_init nrfx_gpiote_in_init -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_gpiote_in_uninit nrfx_gpiote_in_uninit -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_gpiote_in_event_enable nrfx_gpiote_in_event_enable -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_gpiote_in_event_disable nrfx_gpiote_in_event_disable -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_gpiote_in_is_set nrfx_gpiote_in_is_set -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_gpiote_in_event_addr_get nrfx_gpiote_in_event_addr_get -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_gpiote_set_task_addr_get nrfx_gpiote_set_task_addr_get -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_gpiote_clr_task_addr_get nrfx_gpiote_clr_task_addr_get -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_gpiote_out_task_force nrfx_gpiote_out_task_force -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_gpiote_out_task_trigger nrfx_gpiote_out_task_trigger -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_gpiote_set_task_trigger nrfx_gpiote_set_task_trigger -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_gpiote_clr_task_trigger nrfx_gpiote_clr_task_trigger - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif //NRF_DRV_GPIOTE_H__ diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_i2s.h b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_i2s.h deleted file mode 100644 index 11693aedfd..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_i2s.h +++ /dev/null @@ -1,110 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_DRV_I2S_H__ -#define NRF_DRV_I2S_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_drv_i2s I2S driver - legacy layer - * @{ - * @ingroup nrf_i2s - * - * @brief @tagAPI52 Layer providing compatibility with the former API. - */ - -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_i2s_config_t nrf_drv_i2s_config_t; -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_i2s_buffers_t nrf_drv_i2s_buffers_t; - -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_I2S_PIN_NOT_USED NRFX_I2S_PIN_NOT_USED -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_I2S_FLAG_SYNCHRONIZED_MODE NRFX_I2S_FLAG_SYNCHRONIZED_MODE -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_I2S_DEFAULT_CONFIG NRFX_I2S_DEFAULT_CONFIG -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_i2s_data_handler_t nrfx_i2s_data_handler_t - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_i2s_uninit nrfx_i2s_uninit -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_i2s_start nrfx_i2s_start -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_i2s_next_buffers_set nrfx_i2s_next_buffers_set -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_i2s_stop nrfx_i2s_stop - -/** - * @brief Function for initializing the I2S driver. - * - * @param[in] p_config Pointer to the structure with initial configuration. - * If NULL, the default configuration is used. - * @param[in] handler Data handler provided by the user. Must not be NULL. - * - * @retval NRF_SUCCESS If initialization was successful. - * @retval NRF_ERROR_INVALID_STATE If the driver was already initialized. - * @retval NRF_ERROR_INVALID_PARAM If the requested combination of configuration - * options is not allowed by the I2S peripheral. - */ -__STATIC_INLINE ret_code_t nrf_drv_i2s_init(nrf_drv_i2s_config_t const * p_config, - nrf_drv_i2s_data_handler_t handler) -{ - if (p_config == NULL) - { - static nrfx_i2s_config_t const default_config = NRFX_I2S_DEFAULT_CONFIG; - p_config = &default_config; - } - return nrfx_i2s_init(p_config, handler); -} - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_I2S_H__ diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_lpcomp.h b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_lpcomp.h deleted file mode 100644 index dc44432fb7..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_lpcomp.h +++ /dev/null @@ -1,82 +0,0 @@ -/** - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_DRV_LPCOMP_H__ -#define NRF_DRV_LPCOMP_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_drv_lpcomp LPCOMP driver - legacy layer - * @{ - * @ingroup nrf_lpcomp - * - * @brief Layer providing compatibility with the former API. - */ - -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_lpcomp_config_t nrf_drv_lpcomp_config_t; - -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_LPCOMP_DEFAULT_CONFIG NRFX_LPCOMP_DEFAULT_CONFIG - -/** @brief Macro for forwarding the new implementation. */ -#define lpcomp_events_handler_t nrfx_lpcomp_event_handler_t - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_lpcomp_init nrfx_lpcomp_init -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_lpcomp_uninit nrfx_lpcomp_uninit -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_lpcomp_enable nrfx_lpcomp_enable -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_lpcomp_disable nrfx_lpcomp_disable - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_LPCOMP_H__ diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_pdm.h b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_pdm.h deleted file mode 100644 index b8fc1ab16c..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_pdm.h +++ /dev/null @@ -1,116 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_DRV_PDM_H__ -#define NRF_DRV_PDM_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_drv_pdm PDM driver - legacy layer - * @{ - * @ingroup nrf_pdm - * - * @brief @tagAPI52 Layer providing compatibility with the former API. - */ - -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_pdm_config_t nrf_drv_pdm_config_t; -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_pdm_evt_t nrf_drv_pdm_evt_t; - -/** @brief Macro for forwarding the new implementation. */ -#define NRF_PDM_MAX_BUFFER_SIZE NRFX_PDM_MAX_BUFFER_SIZE -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_PDM_DEFAULT_CONFIG NRFX_PDM_DEFAULT_CONFIG - -/** @brief Macro for forwarding the new implementation. */ -#define PDM_NO_ERROR NRFX_PDM_NO_ERROR -/** @brief Macro for forwarding the new implementation. */ -#define PDM_ERROR_OVERFLOW NRFX_PDM_ERROR_OVERFLOW -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_pdm_error_t nrfx_pdm_error_t -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_pdm_event_handler_t nrfx_pdm_event_handler_t - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_pdm_uninit nrfx_pdm_uninit -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_pdm_task_address_get nrfx_pdm_task_address_get -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_pdm_enable_check nrfx_pdm_enable_check -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_pdm_start nrfx_pdm_start -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_pdm_stop nrfx_pdm_stop -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_pdm_buffer_set nrfx_pdm_buffer_set - -/** - * @brief Function for initializing the PDM interface. - * - * @param[in] p_config Pointer to the structure with initial configuration. Cannot be NULL. - * @param[in] event_handler Event handler provided by the user. Cannot be NULL. - * - * @retval NRF_SUCCESS If initialization was successful. - * @retval NRF_ERROR_INVALID_STATE If the driver is already initialized. - * @retval NRF_ERROR_INVALID_PARAM If invalid parameters were specified. - */ -__STATIC_INLINE ret_code_t nrf_drv_pdm_init(nrf_drv_pdm_config_t const * p_config, - nrf_drv_pdm_event_handler_t event_handler) -{ - if (p_config == NULL) - { - return NRFX_ERROR_INVALID_PARAM; - } - return nrfx_pdm_init(p_config, event_handler); -} - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_PDM_H__ diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_power.c b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_power.c deleted file mode 100644 index 87e7b0009f..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_power.c +++ /dev/null @@ -1,412 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include "sdk_common.h" -#if NRF_MODULE_ENABLED(POWER) -#include "nrf_drv_power.h" -#include -#ifdef SOFTDEVICE_PRESENT -#include "nrf_sdh.h" -#include "nrf_sdh_soc.h" -#endif - -#include - -// The structure with default configuration data. -static const nrfx_power_config_t m_drv_power_config_default = -{ - .dcdcen = NRFX_POWER_CONFIG_DEFAULT_DCDCEN, -#if NRF_POWER_HAS_VDDH - .dcdcenhv = NRFX_POWER_CONFIG_DEFAULT_DCDCENHV, -#endif -}; - -static bool m_initialized; - -bool nrf_drv_power_init_check(void) -{ - return m_initialized; -} - -ret_code_t nrf_drv_power_init(nrf_drv_power_config_t const * p_config) -{ -#ifdef SOFTDEVICE_PRESENT - if (nrf_sdh_is_enabled()) - { - return NRF_ERROR_INVALID_STATE; - } -#endif - if (p_config == NULL) - { - p_config = &m_drv_power_config_default; - } - - ret_code_t err_code = nrfx_power_init(p_config); - if (err_code == NRFX_SUCCESS) - { - m_initialized = true; - } - return err_code; -} - -void nrf_drv_power_uninit() -{ - nrfx_power_uninit(); - nrf_drv_power_pof_uninit(); -#if NRF_POWER_HAS_SLEEPEVT - nrf_drv_power_sleepevt_uninit(); -#endif -#if NRF_POWER_HAS_USBREG - nrf_drv_power_usbevt_uninit(); -#endif - m_initialized = false; -} - -ret_code_t nrf_drv_power_pof_init(nrf_drv_power_pofwarn_config_t const * p_config) -{ - ret_code_t err_code = NRF_SUCCESS; - nrfx_power_pof_init(p_config); -#ifdef SOFTDEVICE_PRESENT - if (nrf_sdh_is_enabled()) - { - /* Currently when SD is enabled - the configuration can be changed - * in very limited range. - * It is the SoftDevice limitation. - */ -#if NRF_POWER_HAS_VDDH - if (p_config->thrvddh != nrf_power_pofcon_vddh_get()) - { - /* Cannot change THRVDDH with current SD API */ - return NRF_ERROR_INVALID_STATE; - } -#endif - if (p_config->thr != nrf_power_pofcon_get(NULL)) - { - /* Only limited number of THR values are supported and - * the values taken by SD is different than the one in hardware - */ - uint8_t thr; - switch(p_config->thr) - { - case NRF_POWER_POFTHR_V21: - thr = NRF_POWER_THRESHOLD_V21; - break; - case NRF_POWER_POFTHR_V23: - thr = NRF_POWER_THRESHOLD_V23; - break; - case NRF_POWER_POFTHR_V25: - thr = NRF_POWER_THRESHOLD_V25; - break; - case NRF_POWER_POFTHR_V27: - thr = NRF_POWER_THRESHOLD_V27; - break; - default: - /* Cannot configure */ - nrfx_power_pof_uninit(); - return NRF_ERROR_INVALID_STATE; - } - err_code = sd_power_pof_threshold_set(thr); - if (err_code != NRF_SUCCESS) - { - return err_code; - } - } - err_code = sd_power_pof_enable(true); - } - else -#endif /* SOFTDEVICE_PRESENT */ - { - nrfx_power_pof_enable(p_config); - } - return err_code; -} - -void nrf_drv_power_pof_uninit() -{ -#ifdef SOFTDEVICE_PRESENT - if (nrf_sdh_is_enabled()) - { - ret_code_t err_code = sd_power_pof_enable(false); - ASSERT(err_code == NRF_SUCCESS); - UNUSED_VARIABLE(err_code); //handle no-debug case - } - else -#endif - { - nrfx_power_pof_disable(); - } - nrfx_power_pof_uninit(); -} - -#if NRF_POWER_HAS_SLEEPEVT -ret_code_t nrf_drv_power_sleepevt_init(nrf_drv_power_sleepevt_config_t const * p_config) -{ - if (p_config->handler != NULL) - { -#ifdef SOFTDEVICE_PRESENT - if (nrf_sdh_is_enabled()) - { - if ((p_config->en_enter) || (p_config->en_exit)) - { - return NRF_ERROR_INVALID_STATE; - } - } - else -#endif - { - nrfx_power_sleepevt_enable(p_config); - } - } - return NRF_SUCCESS; -} - -void nrf_drv_power_sleepevt_uninit(void) -{ -#ifdef SOFTDEVICE_PRESENT - if (nrf_sdh_is_enabled()) - { - /* Nothing to do */ - } - else -#endif - { - nrfx_power_sleepevt_disable(); - } - nrfx_power_sleepevt_uninit(); -} -#endif /* NRF_POWER_HAS_SLEEPEVT */ - -#if NRF_POWER_HAS_USBREG - -#ifdef SOFTDEVICE_PRESENT -static ret_code_t nrf_drv_power_sd_usbevt_enable(bool enable) -{ - ret_code_t err_code; - err_code = sd_power_usbdetected_enable(enable); - ASSERT(err_code == NRF_SUCCESS); - if (err_code != NRF_SUCCESS) - { - return err_code; - } - - err_code = sd_power_usbpwrrdy_enable(enable); - ASSERT(err_code == NRF_SUCCESS); - if (err_code != NRF_SUCCESS) - { - return err_code; - } - - err_code = sd_power_usbremoved_enable(enable); - ASSERT(err_code == NRF_SUCCESS); - return err_code; -} -#endif // SOFTDEVICE_PRESENT - -ret_code_t nrf_drv_power_usbevt_init(nrf_drv_power_usbevt_config_t const * p_config) -{ - nrf_drv_power_usbevt_uninit(); - nrfx_power_usbevt_init(p_config); -#ifdef SOFTDEVICE_PRESENT - if (nrf_sdh_is_enabled()) - { - ret_code_t err_code = nrf_drv_power_sd_usbevt_enable(true); - ASSERT(err_code == NRF_SUCCESS); - if (err_code != NRF_SUCCESS) - { - return err_code; - } - - uint32_t regstatus; - err_code = sd_power_usbregstatus_get(®status); - ASSERT(err_code == NRF_SUCCESS); - if (err_code != NRF_SUCCESS) - { - return err_code; - } - - if (regstatus & POWER_USBREGSTATUS_VBUSDETECT_Msk) - { - nrfx_power_usb_event_handler_t usbevt_handler = nrfx_power_usb_handler_get(); - ASSERT(usbevt_handler != NULL); - usbevt_handler(NRFX_POWER_USB_EVT_DETECTED); - } - } - else -#endif - { - nrfx_power_usbevt_enable(); - } - return NRF_SUCCESS; -} - -void nrf_drv_power_usbevt_uninit(void) -{ -#ifdef SOFTDEVICE_PRESENT - CRITICAL_REGION_ENTER(); - if (nrf_sdh_is_enabled()) - { - ret_code_t err_code = nrf_drv_power_sd_usbevt_enable(false); - ASSERT(err_code == NRF_SUCCESS); - UNUSED_VARIABLE(err_code); - } - else -#endif - { - nrfx_power_usbevt_disable(); - } -#ifdef SOFTDEVICE_PRESENT - CRITICAL_REGION_EXIT(); -#endif - nrfx_power_usbevt_uninit(); -} -#endif /* NRF_POWER_HAS_USBREG */ - -#ifdef SOFTDEVICE_PRESENT -static void nrf_drv_power_sdh_soc_evt_handler(uint32_t evt_id, void * p_context); -static void nrf_drv_power_sdh_state_evt_handler(nrf_sdh_state_evt_t state, void * p_context); - -NRF_SDH_SOC_OBSERVER(m_soc_observer, POWER_CONFIG_SOC_OBSERVER_PRIO, - nrf_drv_power_sdh_soc_evt_handler, NULL); - -NRF_SDH_STATE_OBSERVER(m_sd_observer, POWER_CONFIG_STATE_OBSERVER_PRIO) = -{ - .handler = nrf_drv_power_sdh_state_evt_handler, - .p_context = NULL -}; - -static void nrf_drv_power_sdh_soc_evt_handler(uint32_t evt_id, void * p_context) -{ - if (evt_id == NRF_EVT_POWER_FAILURE_WARNING) - { - nrfx_power_pofwarn_event_handler_t pofwarn_handler = nrfx_power_pof_handler_get(); - /* Cannot be null if event is enabled */ - ASSERT(pofwarn_handler != NULL); - pofwarn_handler(); - } - -#if NRF_POWER_HAS_USBREG - nrfx_power_usb_event_handler_t usbevt_handler = nrfx_power_usb_handler_get(); - if (usbevt_handler != NULL) - { - switch (evt_id) - { - case NRF_EVT_POWER_USB_POWER_READY: - usbevt_handler(NRFX_POWER_USB_EVT_READY); - break; - - case NRF_EVT_POWER_USB_DETECTED: - usbevt_handler(NRFX_POWER_USB_EVT_DETECTED); - break; - - case NRF_EVT_POWER_USB_REMOVED: - usbevt_handler(NRFX_POWER_USB_EVT_REMOVED); - break; - - default: - break; - - } - } -#endif -} - -static void nrf_drv_power_on_sd_enable(void) -{ - ASSERT(m_initialized); /* This module has to be enabled first */ - CRITICAL_REGION_ENTER(); - if (nrfx_power_pof_handler_get() != NULL) - { - ret_code_t err_code = sd_power_pof_enable(true); - ASSERT(err_code == NRF_SUCCESS); - UNUSED_VARIABLE(err_code); //handle no-debug case - } - CRITICAL_REGION_EXIT(); - -#if NRF_POWER_HAS_USBREG - if (nrfx_power_usb_handler_get() != NULL) - { - ret_code_t err_code = nrf_drv_power_sd_usbevt_enable(true); - ASSERT(err_code == NRF_SUCCESS); - UNUSED_VARIABLE(err_code); //handle no-debug case - } -#endif -} - -static void nrf_drv_power_on_sd_disable(void) -{ - /* Reinit interrupts */ - ASSERT(m_initialized); - NRFX_IRQ_PRIORITY_SET(POWER_CLOCK_IRQn, CLOCK_CONFIG_IRQ_PRIORITY); - NRFX_IRQ_ENABLE(POWER_CLOCK_IRQn); - if (nrfx_power_pof_handler_get() != NULL) - { - nrf_power_int_enable(NRF_POWER_INT_POFWARN_MASK); - } - -#if NRF_POWER_HAS_USBREG - if (nrfx_power_usb_handler_get() != NULL) - { - nrf_power_int_enable( - NRF_POWER_INT_USBDETECTED_MASK | - NRF_POWER_INT_USBREMOVED_MASK | - NRF_POWER_INT_USBPWRRDY_MASK); - } -#endif -} - -static void nrf_drv_power_sdh_state_evt_handler(nrf_sdh_state_evt_t state, void * p_context) -{ - switch (state) - { - case NRF_SDH_EVT_STATE_ENABLED: - nrf_drv_power_on_sd_enable(); - break; - - case NRF_SDH_EVT_STATE_DISABLED: - nrf_drv_power_on_sd_disable(); - break; - - default: - break; - } -} - -#endif // SOFTDEVICE_PRESENT -#endif //POWER_ENABLED diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_power.h b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_power.h deleted file mode 100644 index 4e615e8522..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_power.h +++ /dev/null @@ -1,232 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_DRV_POWER_H__ -#define NRF_DRV_POWER_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_drv_power POWER driver - legacy layer - * @{ - * @ingroup nrf_power - * - * @brief Layer providing compatibility with the former API. - */ - -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_power_config_t nrf_drv_power_config_t; -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_power_pofwarn_config_t nrf_drv_power_pofwarn_config_t; -#if NRF_POWER_HAS_SLEEPEVT || defined(__SDK_DOXYGEN__) -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_power_sleepevt_config_t nrf_drv_power_sleepevt_config_t; -#endif -#if NRF_POWER_HAS_USBREG || defined(__SDK_DOXYGEN__) -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_power_usbevt_config_t nrf_drv_power_usbevt_config_t; -#endif - -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_POWER_MODE_CONSTLAT NRFX_POWER_MODE_CONSTLAT -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_POWER_MODE_LOWPWR NRFX_POWER_MODE_LOWPWR -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_power_mode_t nrfx_power_mode_t -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_POWER_SLEEP_EVT_ENTER NRFX_POWER_SLEEP_EVT_ENTER -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_POWER_SLEEP_EVT_EXIT NRFX_POWER_SLEEP_EVT_EXIT -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_power_sleep_evt_t nrfx_power_sleep_evt_t -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_POWER_USB_EVT_DETECTED NRFX_POWER_USB_EVT_DETECTED -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_POWER_USB_EVT_REMOVED NRFX_POWER_USB_EVT_REMOVED -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_POWER_USB_EVT_READY NRFX_POWER_USB_EVT_READY -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_power_usb_evt_t nrfx_power_usb_evt_t -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_POWER_USB_STATE_DISCONNECTED NRFX_POWER_USB_STATE_DISCONNECTED -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_POWER_USB_STATE_CONNECTED NRFX_POWER_USB_STATE_CONNECTED -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_POWER_USB_STATE_READY NRFX_POWER_USB_STATE_READY -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_power_usb_state_t nrfx_power_usb_state_t -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_power_pofwarn_event_handler_t nrfx_power_pofwarn_event_handler_t -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_power_sleep_event_handler_t nrfx_power_sleep_event_handler_t -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_power_usb_event_handler_t nrfx_power_usb_event_handler_t - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_power_usbstatus_get nrfx_power_usbstatus_get - -/** - * @brief Function for checking if driver is already initialized - * - * This function is used to check whether common POWER_CLOCK interrupt - * should be disabled or not if @ref nrf_drv_clock tries to disable the interrupt. - * - * @retval true Driver is initialized - * @retval false Driver is uninitialized - * - * @sa nrf_drv_power_uninit - */ -bool nrf_drv_power_init_check(void); - -/** - * @brief Initialize power module driver - * - * Enabled power module driver would process all the interrupts from power system. - * - * @param[in] p_config Driver configuration. Can be NULL - the default configuration - * from @em sdk_config.h file would be used then. - * - * @retval NRF_ERROR_INVALID_STATE Power driver has to be enabled - * before SoftDevice. - * @retval NRF_ERROR_MODULE_ALREADY_INITIALIZED Module is initialized already. - * @retval NRF_SUCCESS Successfully initialized. - */ -ret_code_t nrf_drv_power_init(nrf_drv_power_config_t const * p_config); - -/** - * @brief Unintialize power module driver - * - * Disables all the interrupt handling in the module. - * - * @sa nrf_drv_power_init - */ -void nrf_drv_power_uninit(void); - -/** - * @brief Initialize power failure comparator - * - * Configures and setups the power failure comparator and enables it. - * - * @param[in] p_config Configuration with values and event handler. - * If event handler is set to NULL, interrupt would be disabled. - * - * @retval NRF_ERROR_INVALID_STATE POF is initialized when SD is enabled and - * the configuration differs from the old one and - * is not possible to be set using SD interface. - * @retval NRF_SUCCESS Successfully initialized and configured. - */ -ret_code_t nrf_drv_power_pof_init(nrf_drv_power_pofwarn_config_t const * p_config); - -/** - * @brief Turn off the power failure comparator - * - * Disables and clears the settings of the power failure comparator. - */ -void nrf_drv_power_pof_uninit(void); - -#if NRF_POWER_HAS_SLEEPEVT || defined(__SDK_DOXYGEN__) - -/** - * @brief Initialize sleep entering and exiting events processing - * - * Configures and setups the sleep event processing. - * - * @param[in] p_config Configuration with values and event handler. - * - * @sa nrf_drv_power_sleepevt_uninit - * - * @note Sleep events are not available when SoftDevice is enabled. - * @note If sleep event is enabled when SoftDevice is initialized, sleep events - * would be automatically disabled - it is the limitation of the - * SoftDevice itself. - * - * @retval NRF_ERROR_INVALID_STATE This event cannot be initialized - * when SD is enabled. - * @retval NRF_SUCCESS Successfully initialized and configured. - */ -ret_code_t nrf_drv_power_sleepevt_init(nrf_drv_power_sleepevt_config_t const * p_config); - -/** - * @brief Uninitialize sleep entering and exiting events processing - * - * @sa nrf_drv_power_sleepevt_init - */ -void nrf_drv_power_sleepevt_uninit(void); - -#endif // NRF_POWER_HAS_SLEEPEVT || defined(__SDK_DOXYGEN__) - -#if NRF_POWER_HAS_USBREG || defined(__SDK_DOXYGEN__) - -/** - * @brief Initialize USB power event processing - * - * Configures and setups the USB power event processing. - * - * @param[in] p_config Configuration with values and event handler. - * - * @sa nrf_drv_power_usbevt_uninit - * - * @retval NRF_ERROR_INVALID_STATE This event cannot be initialized - * when SD is enabled and SD does not support - * USB power events. - * @retval NRF_SUCCESS Successfully initialized and configured. - */ -ret_code_t nrf_drv_power_usbevt_init(nrf_drv_power_usbevt_config_t const * p_config); - -/** - * @brief Uninitalize USB power event processing - * - * @sa nrf_drv_power_usbevt_init - */ -void nrf_drv_power_usbevt_uninit(void); - -#endif // NRF_POWER_HAS_USBREG || defined(__SDK_DOXYGEN__) - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_POWER_H__ diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_ppi.c b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_ppi.c deleted file mode 100644 index 6413536b7e..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_ppi.c +++ /dev/null @@ -1,69 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include "nrf_drv_ppi.h" - -static nrfx_drv_state_t m_drv_state; /**< Driver state */ - -ret_code_t nrf_drv_ppi_init(void) -{ - if (m_drv_state == NRFX_DRV_STATE_UNINITIALIZED) - { - m_drv_state = NRFX_DRV_STATE_INITIALIZED; - } - else - { - return NRF_ERROR_MODULE_ALREADY_INITIALIZED; - } - return NRF_SUCCESS; -} - -ret_code_t nrf_drv_ppi_uninit(void) -{ - if (m_drv_state == NRFX_DRV_STATE_UNINITIALIZED) - { - return NRF_ERROR_INVALID_STATE; - } - - m_drv_state = NRFX_DRV_STATE_UNINITIALIZED; - nrfx_ppi_free_all(); - return NRF_SUCCESS; -} - diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_ppi.h b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_ppi.h deleted file mode 100644 index 978fa4b808..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_ppi.h +++ /dev/null @@ -1,130 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_DRV_PPI_H__ -#define NRF_DRV_PPI_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_drv_ppi PPI driver - legacy layer - * @{ - * @ingroup nrf_ppi - * - * @brief @tagAPI52 Layer providing compatibility with the former API. - */ - -/** @brief Macro for forwarding the new implementation. */ -#define NRF_PPI_ALL_APP_CHANNELS_MASK NRFX_PPI_ALL_APP_CHANNELS_MASK -/** @brief Macro for forwarding the new implementation. */ -#define NRF_PPI_PROG_APP_CHANNELS_MASK NRFX_PPI_PROG_APP_CHANNELS_MASK -/** @brief Macro for forwarding the new implementation. */ -#define NRF_PPI_ALL_APP_GROUPS_MASK NRFX_PPI_ALL_APP_GROUPS_MASK - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_ppi_channel_alloc nrfx_ppi_channel_alloc -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_ppi_channel_free nrfx_ppi_channel_free -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_ppi_channel_assign nrfx_ppi_channel_assign -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_ppi_channel_fork_assign nrfx_ppi_channel_fork_assign -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_ppi_channel_enable nrfx_ppi_channel_enable -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_ppi_channel_disable nrfx_ppi_channel_disable -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_ppi_channel_to_mask nrfx_ppi_channel_to_mask -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_ppi_channels_include_in_group nrfx_ppi_channels_include_in_group -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_ppi_channel_include_in_group nrfx_ppi_channel_include_in_group -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_ppi_channels_remove_from_group nrfx_ppi_channels_remove_from_group -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_ppi_channel_remove_from_group nrfx_ppi_channel_remove_from_group - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_ppi_group_alloc nrfx_ppi_group_alloc -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_ppi_group_free nrfx_ppi_group_free -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_ppi_group_clear nrfx_ppi_group_clear -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_ppi_group_enable nrfx_ppi_group_enable -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_ppi_group_disable nrfx_ppi_group_disable - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_ppi_task_addr_get nrfx_ppi_task_addr_get -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_ppi_task_addr_group_enable_get nrfx_ppi_task_addr_group_enable_get -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_ppi_task_addr_group_disable_get nrfx_ppi_task_addr_group_disable_get - -/** - * @brief Function for initializing PPI module. - * - * @retval NRF_SUCCESS If the module was successfully initialized. - * @retval NRF_ERROR_MODULE_ALREADY_INITIALIZED If the module has already been initialized. - */ -ret_code_t nrf_drv_ppi_init(void); - -/** - * @brief Function for uninitializing the PPI module. - * - * This function also disables all channels and clears the channel groups. - * - * @retval NRF_SUCCESS If the module was successfully uninitialized. - * @retval NRF_ERROR_INVALID_STATE If the module has not been initialized yet. - */ -ret_code_t nrf_drv_ppi_uninit(void); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_PPI_H__ diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_pwm.h b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_pwm.h deleted file mode 100644 index e949ff3f53..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_pwm.h +++ /dev/null @@ -1,135 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_DRV_PWM_H__ -#define NRF_DRV_PWM_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_drv_pwm PWM driver - legacy layer - * @{ - * @ingroup nrf_pwm - * - * @brief @tagAPI52 Layer providing compatibility with the former API. - */ - -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_pwm_t nrf_drv_pwm_t; -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_pwm_config_t nrf_drv_pwm_config_t; - -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_PWM_INSTANCE NRFX_PWM_INSTANCE -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_PWM_PIN_NOT_USED NRFX_PWM_PIN_NOT_USED -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_PWM_PIN_INVERTED NRFX_PWM_PIN_INVERTED -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_PWM_DEFAULT_CONFIG NRFX_PWM_DEFAULT_CONFIG - -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_PWM_FLAG_STOP NRFX_PWM_FLAG_STOP -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_PWM_FLAG_LOOP NRFX_PWM_FLAG_LOOP -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_PWM_FLAG_SIGNAL_END_SEQ0 NRFX_PWM_FLAG_SIGNAL_END_SEQ0 -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_PWM_FLAG_SIGNAL_END_SEQ1 NRFX_PWM_FLAG_SIGNAL_END_SEQ1 -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_PWM_FLAG_NO_EVT_FINISHED NRFX_PWM_FLAG_NO_EVT_FINISHED -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_PWM_FLAG_START_VIA_TASK NRFX_PWM_FLAG_START_VIA_TASK -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_pwm_flag_t nrfx_pwm_flag_t -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_PWM_EVT_FINISHED NRFX_PWM_EVT_FINISHED -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_PWM_EVT_END_SEQ0 NRFX_PWM_EVT_END_SEQ0 -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_PWM_EVT_END_SEQ1 NRFX_PWM_EVT_END_SEQ1 -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_PWM_EVT_STOPPED NRFX_PWM_EVT_STOPPED -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_pwm_evt_type_t nrfx_pwm_evt_type_t -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_pwm_handler_t nrfx_pwm_handler_t - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_pwm_init nrfx_pwm_init -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_pwm_uninit nrfx_pwm_uninit -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_pwm_simple_playback nrfx_pwm_simple_playback -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_pwm_complex_playback nrfx_pwm_complex_playback -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_pwm_step nrfx_pwm_step -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_pwm_stop nrfx_pwm_stop -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_pwm_is_stopped nrfx_pwm_is_stopped -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_pwm_sequence_update nrfx_pwm_sequence_update -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_pwm_sequence_values_update nrfx_pwm_sequence_values_update -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_pwm_sequence_length_update nrfx_pwm_sequence_length_update -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_pwm_sequence_repeats_update nrfx_pwm_sequence_repeats_update -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_pwm_sequence_end_delay_update nrfx_pwm_sequence_end_delay_update - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_pwm_task_address_get nrfx_pwm_task_address_get -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_pwm_event_address_get nrfx_pwm_event_address_get - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_PWM_H__ diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_qdec.h b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_qdec.h deleted file mode 100644 index e4e549b32b..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_qdec.h +++ /dev/null @@ -1,130 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_DRV_QDEC_H__ -#define NRF_DRV_QDEC_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_drv_qdec QDEC driver - legacy layer - * @{ - * @ingroup nrf_qdec - * - * @brief Layer providing compatibility with the former API. - */ - -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_qdec_config_t nrf_drv_qdec_config_t; -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_qdec_sample_data_evt_t nrf_drv_qdec_sample_data_evt_t; -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_qdec_report_data_evt_t nrf_drv_qdec_report_data_evt_t; -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_qdec_event_t nrf_drv_qdec_event_t; - -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_QDEC_DEFAULT_CONFIG NRFX_QDEC_DEFAULT_CONFIG - -/** @brief Macro for forwarding the new implementation. */ -#define qdec_event_handler_t nrfx_qdec_event_handler_t -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_qdec_uninit nrfx_qdec_uninit -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_qdec_enable nrfx_qdec_enable -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_qdec_disable nrfx_qdec_disable -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_qdec_accumulators_read nrfx_qdec_accumulators_read - -/** - * @brief Function for initializing QDEC. - * - * @param[in] p_config Pointer to the structure with initial configuration. - * @param[in] event_handler Event handler function. - * - * @retval NRF_SUCCESS If initialization was successful. - * @retval NRF_ERROR_INVALID_PARAM If invalid parameters were supplied. - * @retval NRF_ERROR_INVALID_STATE If QDEC was already initialized. - */ -__STATIC_INLINE ret_code_t nrf_drv_qdec_init(nrf_drv_qdec_config_t const * p_config, - qdec_event_handler_t event_handler) -{ - if (p_config == NULL) - { - static nrf_drv_qdec_config_t const default_config = NRFX_QDEC_DEFAULT_CONFIG; - p_config = &default_config; - } - return nrfx_qdec_init(p_config, event_handler); -} - -/** - * @brief Function for returning the address of a specific timer task. - * - * @param[in] task QDEC task. - * @param[out] p_task Task address. - */ -void nrf_drv_qdec_task_address_get(nrf_qdec_task_t task, uint32_t * p_task) -{ - *p_task = nrfx_qdec_task_address_get(task); -} - -/** - * @brief Function for returning the address of a specific timer event. - * - * @param[in] event QDEC event. - * @param[out] p_event Event address. - */ -void nrf_drv_qdec_event_address_get(nrf_qdec_event_t event, uint32_t * p_event) -{ - *p_event = nrfx_qdec_event_address_get(event); -} - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_QDEC_H__ diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_qspi.h b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_qspi.h deleted file mode 100644 index 25c4371fad..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_qspi.h +++ /dev/null @@ -1,122 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_DRV_QSPI_H__ -#define NRF_DRV_QSPI_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_drv_qspi QSPI driver - legacy layer - * @{ - * @ingroup nrf_qspi - * - * @brief @tagAPI52840 Layer providing compatibility with the former API. - */ - -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_qspi_config_t nrf_drv_qspi_config_t; - -#if QSPI_PIN_SCK == NRF_QSPI_PIN_NOT_CONNECTED - #undef QSPI_PIN_SCK - #define QSPI_PIN_SCK BSP_QSPI_SCK_PIN -#endif -#if QSPI_PIN_CSN == NRF_QSPI_PIN_NOT_CONNECTED - #undef QSPI_PIN_CSN - #define QSPI_PIN_CSN BSP_QSPI_CSN_PIN -#endif -#if QSPI_PIN_IO0 == NRF_QSPI_PIN_NOT_CONNECTED - #undef QSPI_PIN_IO0 - #define QSPI_PIN_IO0 BSP_QSPI_IO0_PIN -#endif -#if QSPI_PIN_IO1 == NRF_QSPI_PIN_NOT_CONNECTED - #undef QSPI_PIN_IO1 - #define QSPI_PIN_IO1 BSP_QSPI_IO1_PIN -#endif -#if QSPI_PIN_IO2 == NRF_QSPI_PIN_NOT_CONNECTED - #undef QSPI_PIN_IO2 - #define QSPI_PIN_IO2 BSP_QSPI_IO2_PIN -#endif -#if QSPI_PIN_IO3 == NRF_QSPI_PIN_NOT_CONNECTED - #undef QSPI_PIN_IO3 - #define QSPI_PIN_IO3 BSP_QSPI_IO3_PIN -#endif - -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_QSPI_DEFAULT_CONFIG NRFX_QSPI_DEFAULT_CONFIG -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_QSPI_DEFAULT_CINSTR NRFX_QSPI_DEFAULT_CINSTR -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_QSPI_EVENT_DONE NRFX_QSPI_EVENT_DONE -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_qspi_evt_t nrfx_qspi_evt_t -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_qspi_handler_t nrfx_qspi_handler_t - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_qspi_init nrfx_qspi_init -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_qspi_uninit nrfx_qspi_uninit -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_qspi_read nrfx_qspi_read -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_qspi_write nrfx_qspi_write -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_qspi_erase nrfx_qspi_erase -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_qspi_chip_erase nrfx_qspi_chip_erase -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_qspi_mem_busy_check nrfx_qspi_mem_busy_check -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_qspi_cinstr_xfer nrfx_qspi_cinstr_xfer -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_qspi_cinstr_quick_send nrfx_qspi_cinstr_quick_send - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_QSPI_H__ diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_rng.c b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_rng.c deleted file mode 100644 index 49d82f0cca..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_rng.c +++ /dev/null @@ -1,283 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include "sdk_common.h" -#if NRF_MODULE_ENABLED(RNG) - -#include -#include -#include "nrf_drv_rng.h" -#include "nordic_common.h" -#include "app_util_platform.h" -#include "nrf_assert.h" -#include "nrf_queue.h" - -#ifdef SOFTDEVICE_PRESENT - #include "nrf_sdh.h" -#endif // SOFTDEVICE_PRESENT - -#define NRF_LOG_MODULE_NAME rng - -#if RNG_CONFIG_LOG_ENABLED - #define NRF_LOG_LEVEL RNG_CONFIG_LOG_LEVEL - #define NRF_LOG_INFO_COLOR RNG_CONFIG_INFO_COLOR - #define NRF_LOG_DEBUG_COLOR RNG_CONFIG_DEBUG_COLOR -#else //RNG_CONFIG_LOG_ENABLED - #define NRF_LOG_LEVEL 0 -#endif //RNG_CONFIG_LOG_ENABLED -#include "nrf_log.h" -NRF_LOG_MODULE_REGISTER(); - -typedef struct -{ - nrfx_drv_state_t state; - nrf_drv_rng_config_t config; -} nrf_drv_rng_cb_t; - -static nrf_drv_rng_cb_t m_rng_cb; -NRF_QUEUE_DEF(uint8_t, m_rand_pool, RNG_CONFIG_POOL_SIZE, NRF_QUEUE_MODE_OVERFLOW); -static const nrf_drv_rng_config_t m_default_config = NRF_DRV_RNG_DEFAULT_CONFIG; - -#ifdef SOFTDEVICE_PRESENT - #define SD_RAND_POOL_SIZE (64) - - STATIC_ASSERT(RNG_CONFIG_POOL_SIZE == SD_RAND_POOL_SIZE); - - #define NRF_DRV_RNG_LOCK() CRITICAL_REGION_ENTER() - #define NRF_DRV_RNG_RELEASE() CRITICAL_REGION_EXIT() - #define NRF_DRV_RNG_SD_IS_ENABLED() nrf_sdh_is_enabled() -#else - #define NRF_DRV_RNG_LOCK() do { } while (0) - #define NRF_DRV_RNG_RELEASE() do { } while (0) - #define NRF_DRV_RNG_SD_IS_ENABLED() false -#endif // SOFTDEVICE_PRESENT - - -static void nrfx_rng_handler(uint8_t rng_val) -{ - NRF_DRV_RNG_LOCK(); - if (!NRF_DRV_RNG_SD_IS_ENABLED()) - { - UNUSED_RETURN_VALUE(nrf_queue_push(&m_rand_pool, &rng_val)); - - if (nrf_queue_is_full(&m_rand_pool)) - { - nrfx_rng_stop(); - } - - NRF_LOG_DEBUG("Event: NRF_RNG_EVENT_VALRDY."); - } - NRF_DRV_RNG_RELEASE(); - -} - -ret_code_t nrf_drv_rng_init(nrf_drv_rng_config_t const * p_config) -{ - ret_code_t err_code = NRF_SUCCESS; - if (m_rng_cb.state != NRFX_DRV_STATE_UNINITIALIZED) - { - return NRF_ERROR_MODULE_ALREADY_INITIALIZED; - } - - if (p_config == NULL) - { - p_config = &m_default_config; - } - m_rng_cb.config = *p_config; - - NRF_DRV_RNG_LOCK(); - - if (!NRF_DRV_RNG_SD_IS_ENABLED()) - { - err_code = nrfx_rng_init(&m_rng_cb.config, nrfx_rng_handler); - if (err_code != NRF_SUCCESS) - { - return err_code; - } - nrfx_rng_start(); - } - m_rng_cb.state = NRFX_DRV_STATE_INITIALIZED; - - NRF_DRV_RNG_RELEASE(); - - return err_code; -} - -void nrf_drv_rng_uninit(void) -{ - ASSERT(m_rng_cb.state == NRFX_DRV_STATE_INITIALIZED); - - NRF_DRV_RNG_LOCK(); - - if (!NRF_DRV_RNG_SD_IS_ENABLED()) - { - nrfx_rng_stop(); - nrfx_rng_uninit(); - } - - NRF_DRV_RNG_RELEASE(); - - nrf_queue_reset(&m_rand_pool); - m_rng_cb.state = NRFX_DRV_STATE_UNINITIALIZED; - NRF_LOG_INFO("Uninitialized."); -} - -void nrf_drv_rng_bytes_available(uint8_t * p_bytes_available) -{ - ASSERT(m_rng_cb.state == NRFX_DRV_STATE_INITIALIZED); - -#ifdef SOFTDEVICE_PRESENT - if (NRF_DRV_RNG_SD_IS_ENABLED()) - { - if (NRF_SUCCESS == sd_rand_application_bytes_available_get(p_bytes_available)) - { - return; - } - } -#endif // SOFTDEVICE_PRESENT - - *p_bytes_available = nrf_queue_utilization_get(&m_rand_pool); - - NRF_LOG_INFO("Function: %s, available bytes: %d.", (uint32_t)__func__, *p_bytes_available); -} - -ret_code_t nrf_drv_rng_rand(uint8_t * p_buff, uint8_t length) -{ - ret_code_t err_code = NRF_SUCCESS; - ASSERT(m_rng_cb.state == NRFX_DRV_STATE_INITIALIZED); - -#ifdef SOFTDEVICE_PRESENT - do { - bool sd_is_enabled; - NRF_DRV_RNG_LOCK(); - sd_is_enabled = NRF_DRV_RNG_SD_IS_ENABLED(); - if (!sd_is_enabled) -#endif // SOFTDEVICE_PRESENT - { - err_code = nrf_queue_read(&m_rand_pool, p_buff, (uint32_t)length); - nrfx_rng_start(); - } -#ifdef SOFTDEVICE_PRESENT - NRF_DRV_RNG_RELEASE(); - - if (sd_is_enabled) - { - err_code = sd_rand_application_vector_get(p_buff, length); - if (err_code == NRF_ERROR_SOC_RAND_NOT_ENOUGH_VALUES) - { - err_code = NRF_ERROR_NOT_FOUND; - } - } - } while (err_code == NRF_ERROR_SOFTDEVICE_NOT_ENABLED); -#endif // SOFTDEVICE_PRESENT - ASSERT((err_code == NRF_SUCCESS) || (err_code == NRF_ERROR_NOT_FOUND)); - -#if defined(RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED) && (RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED != 0) - NRF_LOG_DEBUG("Rand buffer data:"); - NRF_LOG_HEXDUMP_DEBUG((uint8_t *)p_buff, length); -#endif // RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED - NRF_LOG_WARNING("Function: %s, error code: %s.", - (uint32_t)__func__, - (uint32_t)NRF_LOG_ERROR_STRING_GET(err_code)); - - return err_code; -} - -void nrf_drv_rng_block_rand(uint8_t * p_buff, uint32_t length) -{ - ASSERT(m_rng_cb.state == NRFX_DRV_STATE_INITIALIZED); - - while (length) - { - uint32_t len = MIN(length, RNG_CONFIG_POOL_SIZE); - ret_code_t err_code; - - do { - err_code = nrf_drv_rng_rand(p_buff, len); - } while (err_code != NRF_SUCCESS); - - length -= len; - p_buff += len; - } - - NRF_LOG_DEBUG("Rand buffer data:"); - NRF_LOG_HEXDUMP_DEBUG((uint8_t *)p_buff, length); -} - -#ifdef SOFTDEVICE_PRESENT -static void sd_state_evt_handler(nrf_sdh_state_evt_t state, void * p_context) -{ - switch (state) - { - case NRF_SDH_EVT_STATE_ENABLE_PREPARE: - if (m_rng_cb.state == NRFX_DRV_STATE_INITIALIZED) - { - nrfx_rng_stop(); - nrfx_rng_uninit(); - } - break; - - case NRF_SDH_EVT_STATE_DISABLED: - NRF_DRV_RNG_LOCK(); - if (m_rng_cb.state == NRFX_DRV_STATE_INITIALIZED) - { - ret_code_t err_code = nrfx_rng_init(&m_rng_cb.config, nrfx_rng_handler); - if (err_code != NRF_SUCCESS) - { - ASSERT(false); - } - nrfx_rng_start(); - } - NRF_DRV_RNG_RELEASE(); - break; - - default: - break; - } -} - -NRF_SDH_STATE_OBSERVER(m_sd_state_observer, RNG_CONFIG_STATE_OBSERVER_PRIO) = -{ - .handler = sd_state_evt_handler, - .p_context = NULL, -}; - -#endif // SOFTDEVICE_PRESENT - -#endif // NRF_MODULE_ENABLED(RNG) diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_rng.h b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_rng.h deleted file mode 100644 index ecdbfc146a..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_rng.h +++ /dev/null @@ -1,115 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_DRV_RNG_H__ -#define NRF_DRV_RNG_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_drv_rng RNG driver - legacy layer - * @{ - * @ingroup nrf_rng - * - * @brief Layer providing compatibility with the former API. - */ - -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_rng_config_t nrf_drv_rng_config_t; - -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_RNG_DEFAULT_CONFIG NRFX_RNG_DEFAULT_CONFIG - -/** - * @brief Function for initializing the nrf_drv_rng module. - * - * @param[in] p_config Initial configuration. - * - * @retval NRF_SUCCESS Driver was successfully initialized. - * @retval NRF_ERROR_MODULE_ALREADY_INITIALIZED Driver was already initialized. - */ -ret_code_t nrf_drv_rng_init(nrf_drv_rng_config_t const * p_config); - -/** - * @brief Function for uninitializing the nrf_drv_rng module. - */ -void nrf_drv_rng_uninit(void); - -/** - * @brief Function for getting the number of currently available random bytes. - * - * @param[out] p_bytes_available The number of bytes currently available in the pool. - */ -void nrf_drv_rng_bytes_available(uint8_t * p_bytes_available); - -/** - * @brief Function for getting the vector of random numbers. - * - * @param[out] p_buff Pointer to uint8_t buffer for storing the bytes. - * @param[in] length Number of bytes to take from the pool and place in p_buff. - * - * @retval NRF_SUCCESS If the requested bytes were written to p_buff. - * @retval NRF_ERROR_NOT_FOUND If no bytes were written to the buffer because there were - * not enough bytes available in the pool. - */ -ret_code_t nrf_drv_rng_rand(uint8_t * p_buff, uint8_t length); - -/** - * @brief Blocking function for getting an arbitrary array of random numbers. - * - * @note This function may execute for a substantial amount of time depending on the length - * of the buffer required and on the state of the current internal pool of random numbers. - * - * @param[out] p_buff Pointer to uint8_t buffer for storing the bytes. - * @param[in] length Number of bytes place in p_buff. - */ -void nrf_drv_rng_block_rand(uint8_t * p_buff, uint32_t length); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_RNG_H__ diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_rtc.h b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_rtc.h deleted file mode 100644 index db246d34f7..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_rtc.h +++ /dev/null @@ -1,129 +0,0 @@ -/** - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_DRV_RTC_H__ -#define NRF_DRV_RTC_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_drv_rtc RTC driver - legacy layer - * @{ - * @ingroup nrf_rtc - * - * @brief Layer providing compatibility with the former API. - */ - -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_rtc_t nrf_drv_rtc_t; -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_rtc_config_t nrf_drv_rtc_config_t; - -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_RTC_INSTANCE NRFX_RTC_INSTANCE -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_RTC_DEFAULT_CONFIG NRFX_RTC_DEFAULT_CONFIG -/** @brief Macro for forwarding the new implementation. */ -#define RTC_US_TO_TICKS NRFX_RTC_US_TO_TICKS - -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_RTC_INT_COMPARE0 NRFX_RTC_INT_COMPARE0 -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_RTC_INT_COMPARE1 NRFX_RTC_INT_COMPARE1 -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_RTC_INT_COMPARE2 NRFX_RTC_INT_COMPARE2 -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_RTC_INT_COMPARE3 NRFX_RTC_INT_COMPARE3 -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_RTC_INT_TICK NRFX_RTC_INT_TICK -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_RTC_INT_OVERFLOW NRFX_RTC_INT_OVERFLOW -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_rtc_int_type_t nrfx_rtc_int_type_t -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_rtc_handler_t nrfx_rtc_handler_t - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_rtc_init nrfx_rtc_init -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_rtc_uninit nrfx_rtc_uninit -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_rtc_enable nrfx_rtc_enable -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_rtc_disable nrfx_rtc_disable -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_rtc_cc_set nrfx_rtc_cc_set -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_rtc_cc_disable nrfx_rtc_cc_disable -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_rtc_tick_enable nrfx_rtc_tick_enable -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_rtc_tick_disable nrfx_rtc_tick_disable -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_rtc_overflow_enable nrfx_rtc_overflow_enable -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_rtc_overflow_disable nrfx_rtc_overflow_disable -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_rtc_max_ticks_get nrfx_rtc_max_ticks_get -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_rtc_int_disable nrfx_rtc_int_disable -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_rtc_int_enable nrfx_rtc_int_enable -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_rtc_counter_get nrfx_rtc_counter_get -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_rtc_counter_clear nrfx_rtc_counter_clear - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_rtc_task_address_get nrfx_rtc_task_address_get -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_rtc_event_address_get nrfx_rtc_event_address_get - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_RTC_H__ diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_saadc.h b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_saadc.h deleted file mode 100644 index 2b615e56e6..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_saadc.h +++ /dev/null @@ -1,143 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_DRV_SAADC_H__ -#define NRF_DRV_SAADC_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_drv_saadc SAADC driver - legacy layer - * @{ - * @ingroup nrf_saadc - * - * @brief @tagAPI52 Layer providing compatibility with the former API. - */ - -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_saadc_config_t nrf_drv_saadc_config_t; - -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_SAADC_EVT_DONE NRFX_SAADC_EVT_DONE -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_SAADC_EVT_LIMIT NRFX_SAADC_EVT_LIMIT -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_SAADC_EVT_CALIBRATEDONE NRFX_SAADC_EVT_CALIBRATEDONE -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_saadc_evt_type_t nrfx_saadc_evt_type_t -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_saadc_done_evt_t nrfx_saadc_done_evt_t -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_saadc_limit_evt_t nrfx_saadc_limit_evt_t -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_saadc_evt_t nrfx_saadc_evt_t -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_saadc_event_handler_t nrfx_saadc_event_handler_t - -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_SAADC_LIMITH_DISABLED NRFX_SAADC_LIMITH_DISABLED -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_SAADC_LIMITL_DISABLED NRFX_SAADC_LIMITL_DISABLED -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_SAADC_DEFAULT_CONFIG NRFX_SAADC_DEFAULT_CONFIG -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_SAADC_DEFAULT_CHANNEL_CONFIG_SE \ - NRFX_SAADC_DEFAULT_CHANNEL_CONFIG_SE -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_SAADC_DEFAULT_CHANNEL_CONFIG_DIFFERENTIAL \ - NRFX_SAADC_DEFAULT_CHANNEL_CONFIG_DIFFERENTIAL - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_saadc_uninit nrfx_saadc_uninit -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_saadc_channel_init nrfx_saadc_channel_init -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_saadc_channel_uninit nrfx_saadc_channel_uninit -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_saadc_sample nrfx_saadc_sample -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_saadc_sample_convert nrfx_saadc_sample_convert -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_saadc_buffer_convert nrfx_saadc_buffer_convert -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_saadc_calibrate_offset nrfx_saadc_calibrate_offset -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_saadc_is_busy nrfx_saadc_is_busy -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_saadc_abort nrfx_saadc_abort -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_saadc_limits_set nrfx_saadc_limits_set - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_saadc_sample_task_get nrfx_saadc_sample_task_get - -/** - * @brief Function for initializing the SAADC. - * - * @param[in] p_config Pointer to the structure with initial configuration. - * If NULL, the default one is used. - * @param[in] event_handler Event handler provided by the user. - * - * @retval NRF_SUCCESS If initialization was successful. - * @retval NRF_ERROR_INVALID_STATE If the driver is already initialized. - * @retval NRF_ERROR_INVALID_PARAM If event_handler is NULL. - */ -__STATIC_INLINE ret_code_t nrf_drv_saadc_init(nrf_drv_saadc_config_t const * p_config, - nrf_drv_saadc_event_handler_t event_handler) -{ - if (p_config == NULL) - { - static const nrfx_saadc_config_t default_config = NRFX_SAADC_DEFAULT_CONFIG; - p_config = &default_config; - } - return nrfx_saadc_init(p_config, event_handler); -} - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_SAADC_H__ diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_spi.c b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_spi.c deleted file mode 100644 index fe2d2a4cd7..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_spi.c +++ /dev/null @@ -1,135 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include "nrf_drv_spi.h" - -#ifdef SPIM_PRESENT -#define INSTANCE_COUNT SPIM_COUNT -#else -#define INSTANCE_COUNT SPI_COUNT -#endif - -static nrf_drv_spi_evt_handler_t m_handlers[INSTANCE_COUNT]; -static void * m_contexts[INSTANCE_COUNT]; - -#ifdef SPIM_PRESENT -static void spim_evt_handler(nrfx_spim_evt_t const * p_event, - void * p_context) -{ - uint32_t inst_idx = (uint32_t)p_context; - nrf_drv_spi_evt_t const event = - { - .type = (nrf_drv_spi_evt_type_t)p_event->type, - .data = - { - .done = - { - .p_tx_buffer = p_event->xfer_desc.p_tx_buffer, - .tx_length = p_event->xfer_desc.tx_length, - .p_rx_buffer = p_event->xfer_desc.p_rx_buffer, - .rx_length = p_event->xfer_desc.rx_length, - } - } - }; - m_handlers[inst_idx](&event, m_contexts[inst_idx]); -} -#endif // SPIM_PRESENT - -#ifdef SPI_PRESENT -static void spi_evt_handler(nrfx_spi_evt_t const * p_event, - void * p_context) -{ - uint32_t inst_idx = (uint32_t)p_context; - nrf_drv_spi_evt_t const event = - { - .type = (nrf_drv_spi_evt_type_t)p_event->type, - .data = - { - .done = - { - .p_tx_buffer = p_event->xfer_desc.p_tx_buffer, - .tx_length = p_event->xfer_desc.tx_length, - .p_rx_buffer = p_event->xfer_desc.p_rx_buffer, - .rx_length = p_event->xfer_desc.rx_length, - } - } - }; - m_handlers[inst_idx](&event, m_contexts[inst_idx]); -} -#endif // SPI_PRESENT - -ret_code_t nrf_drv_spi_init(nrf_drv_spi_t const * const p_instance, - nrf_drv_spi_config_t const * p_config, - nrf_drv_spi_evt_handler_t handler, - void * p_context) -{ - uint32_t inst_idx = p_instance->inst_idx; - m_handlers[inst_idx] = handler; - m_contexts[inst_idx] = p_context; - - ret_code_t result = 0; - if (NRF_DRV_SPI_USE_SPIM) - { -#ifdef SPIM_PRESENT - nrfx_spim_config_t config_spim = NRFX_SPIM_DEFAULT_CONFIG; - config_spim.sck_pin = p_config->sck_pin; - config_spim.mosi_pin = p_config->mosi_pin; - config_spim.miso_pin = p_config->miso_pin; - config_spim.ss_pin = p_config->ss_pin; - config_spim.irq_priority = p_config->irq_priority; - config_spim.orc = p_config->orc; - config_spim.frequency = (nrf_spim_frequency_t)p_config->frequency; - config_spim.mode = (nrf_spim_mode_t)p_config->mode; - config_spim.bit_order = (nrf_spim_bit_order_t)p_config->bit_order; - result = nrfx_spim_init(&p_instance->u.spim, - &config_spim, - handler ? spim_evt_handler : NULL, - (void *)inst_idx); -#endif - } - else if (NRF_DRV_SPI_USE_SPI) - { - result = nrfx_spi_init(&p_instance->u.spi, - (nrfx_spi_config_t const *)p_config, - handler ? spi_evt_handler : NULL, - (void *)inst_idx); - } - return result; -} diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_spi.h b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_spi.h deleted file mode 100644 index af1396eee1..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_spi.h +++ /dev/null @@ -1,615 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_DRV_SPI_H__ -#define NRF_DRV_SPI_H__ - -#include -#ifdef SPIM_PRESENT - #include -#else - // Compilers (at least the smart ones) will remove the SPIM related code - // (blocks starting with "if (NRF_DRV_SPI_USE_SPIM)") when it is not used, - // but to perform the compilation they need the following definitions. - #define nrfx_spim_init(...) 0 - #define nrfx_spim_uninit(...) - #define nrfx_spim_start_task_get(...) 0 - #define nrfx_spim_end_event_get(...) 0 - #define nrfx_spim_abort(...) -#endif - -#ifdef SPI_PRESENT - #include -#else - // Compilers (at least the smart ones) will remove the SPI related code - // (blocks starting with "if (NRF_DRV_SPI_USE_SPI)") when it is not used, - // but to perform the compilation they need the following definitions. - #define nrfx_spi_init(...) 0 - #define nrfx_spi_uninit(...) - #define nrfx_spi_start_task_get(...) 0 - #define nrfx_spi_end_event_get(...) 0 - #define nrfx_spi_abort(...) - - // This part is for old modules that use directly SPI HAL definitions - // (to make them compilable for chips that have only SPIM). - #define NRF_SPI_FREQ_125K NRF_SPIM_FREQ_125K - #define NRF_SPI_FREQ_250K NRF_SPIM_FREQ_250K - #define NRF_SPI_FREQ_500K NRF_SPIM_FREQ_500K - #define NRF_SPI_FREQ_1M NRF_SPIM_FREQ_1M - #define NRF_SPI_FREQ_2M NRF_SPIM_FREQ_2M - #define NRF_SPI_FREQ_4M NRF_SPIM_FREQ_4M - #define NRF_SPI_FREQ_8M NRF_SPIM_FREQ_8M - #define NRF_SPI_MODE_0 NRF_SPIM_MODE_0 - #define NRF_SPI_MODE_1 NRF_SPIM_MODE_1 - #define NRF_SPI_MODE_2 NRF_SPIM_MODE_2 - #define NRF_SPI_MODE_3 NRF_SPIM_MODE_3 - #define NRF_SPI_BIT_ORDER_MSB_FIRST NRF_SPIM_BIT_ORDER_MSB_FIRST - #define NRF_SPI_BIT_ORDER_LSB_FIRST NRF_SPIM_BIT_ORDER_LSB_FIRST -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_drv_spi SPI master driver - * @{ - * @ingroup nrf_spi - * @brief Layer providing compatibility with the former API. - */ - -/** - * @brief SPI master driver instance data structure. - */ -typedef struct -{ - uint8_t inst_idx; - union - { -#ifdef SPIM_PRESENT - nrfx_spim_t spim; -#endif -#ifdef SPI_PRESENT - nrfx_spi_t spi; -#endif - } u; - bool use_easy_dma; -} nrf_drv_spi_t; - -/** - * @brief Macro for creating an SPI master driver instance. - */ -#define NRF_DRV_SPI_INSTANCE(id) NRF_DRV_SPI_INSTANCE_(id) -#define NRF_DRV_SPI_INSTANCE_(id) NRF_DRV_SPI_INSTANCE_ ## id -#if NRFX_CHECK(NRFX_SPIM0_ENABLED) - #define NRF_DRV_SPI_INSTANCE_0 \ - { 0, { .spim = NRFX_SPIM_INSTANCE(0) }, true } -#elif NRFX_CHECK(NRFX_SPI0_ENABLED) - #define NRF_DRV_SPI_INSTANCE_0 \ - { 0, { .spi = NRFX_SPI_INSTANCE(0) }, false } -#endif -#if NRFX_CHECK(NRFX_SPIM1_ENABLED) - #define NRF_DRV_SPI_INSTANCE_1 \ - { 1, { .spim = NRFX_SPIM_INSTANCE(1) }, true } -#elif NRFX_CHECK(NRFX_SPI1_ENABLED) - #define NRF_DRV_SPI_INSTANCE_1 \ - { 1, { .spi = NRFX_SPI_INSTANCE(1) }, false } -#endif -#if NRFX_CHECK(NRFX_SPIM2_ENABLED) - #define NRF_DRV_SPI_INSTANCE_2 \ - { 2, { .spim = NRFX_SPIM_INSTANCE(2) }, true } -#elif NRFX_CHECK(NRFX_SPI2_ENABLED) - #define NRF_DRV_SPI_INSTANCE_2 \ - { 2, { .spi = NRFX_SPI_INSTANCE(2) }, false } -#endif - -/** - * @brief This value can be provided instead of a pin number for signals MOSI, - * MISO, and Slave Select to specify that the given signal is not used and - * therefore does not need to be connected to a pin. - */ -#define NRF_DRV_SPI_PIN_NOT_USED 0xFF - -/** - * @brief SPI data rates. - */ -typedef enum -{ - NRF_DRV_SPI_FREQ_125K = NRF_SPI_FREQ_125K, ///< 125 kbps. - NRF_DRV_SPI_FREQ_250K = NRF_SPI_FREQ_250K, ///< 250 kbps. - NRF_DRV_SPI_FREQ_500K = NRF_SPI_FREQ_500K, ///< 500 kbps. - NRF_DRV_SPI_FREQ_1M = NRF_SPI_FREQ_1M, ///< 1 Mbps. - NRF_DRV_SPI_FREQ_2M = NRF_SPI_FREQ_2M, ///< 2 Mbps. - NRF_DRV_SPI_FREQ_4M = NRF_SPI_FREQ_4M, ///< 4 Mbps. - NRF_DRV_SPI_FREQ_8M = NRF_SPI_FREQ_8M ///< 8 Mbps. -} nrf_drv_spi_frequency_t; - -/** - * @brief SPI modes. - */ -typedef enum -{ - NRF_DRV_SPI_MODE_0 = NRF_SPI_MODE_0, ///< SCK active high, sample on leading edge of clock. - NRF_DRV_SPI_MODE_1 = NRF_SPI_MODE_1, ///< SCK active high, sample on trailing edge of clock. - NRF_DRV_SPI_MODE_2 = NRF_SPI_MODE_2, ///< SCK active low, sample on leading edge of clock. - NRF_DRV_SPI_MODE_3 = NRF_SPI_MODE_3 ///< SCK active low, sample on trailing edge of clock. -} nrf_drv_spi_mode_t; - -/** - * @brief SPI bit orders. - */ -typedef enum -{ - NRF_DRV_SPI_BIT_ORDER_MSB_FIRST = NRF_SPI_BIT_ORDER_MSB_FIRST, ///< Most significant bit shifted out first. - NRF_DRV_SPI_BIT_ORDER_LSB_FIRST = NRF_SPI_BIT_ORDER_LSB_FIRST ///< Least significant bit shifted out first. -} nrf_drv_spi_bit_order_t; - -/** - * @brief SPI master driver instance configuration structure. - */ -typedef struct -{ - uint8_t sck_pin; ///< SCK pin number. - uint8_t mosi_pin; ///< MOSI pin number (optional). - /**< Set to @ref NRF_DRV_SPI_PIN_NOT_USED - * if this signal is not needed. */ - uint8_t miso_pin; ///< MISO pin number (optional). - /**< Set to @ref NRF_DRV_SPI_PIN_NOT_USED - * if this signal is not needed. */ - uint8_t ss_pin; ///< Slave Select pin number (optional). - /**< Set to @ref NRF_DRV_SPI_PIN_NOT_USED - * if this signal is not needed. The driver - * supports only active low for this signal. - * If the signal should be active high, - * it must be controlled externally. */ - uint8_t irq_priority; ///< Interrupt priority. - uint8_t orc; ///< Over-run character. - /**< This character is used when all bytes from the TX buffer are sent, - but the transfer continues due to RX. */ - nrf_drv_spi_frequency_t frequency; ///< SPI frequency. - nrf_drv_spi_mode_t mode; ///< SPI mode. - nrf_drv_spi_bit_order_t bit_order; ///< SPI bit order. -} nrf_drv_spi_config_t; - -/** - * @brief SPI master instance default configuration. - */ -#define NRF_DRV_SPI_DEFAULT_CONFIG \ -{ \ - .sck_pin = NRF_DRV_SPI_PIN_NOT_USED, \ - .mosi_pin = NRF_DRV_SPI_PIN_NOT_USED, \ - .miso_pin = NRF_DRV_SPI_PIN_NOT_USED, \ - .ss_pin = NRF_DRV_SPI_PIN_NOT_USED, \ - .irq_priority = SPI_DEFAULT_CONFIG_IRQ_PRIORITY, \ - .orc = 0xFF, \ - .frequency = NRF_DRV_SPI_FREQ_4M, \ - .mode = NRF_DRV_SPI_MODE_0, \ - .bit_order = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST, \ -} - -#define NRF_DRV_SPI_FLAG_TX_POSTINC (1UL << 0) /**< TX buffer address incremented after transfer. */ -#define NRF_DRV_SPI_FLAG_RX_POSTINC (1UL << 1) /**< RX buffer address incremented after transfer. */ -#define NRF_DRV_SPI_FLAG_NO_XFER_EVT_HANDLER (1UL << 2) /**< Interrupt after each transfer is suppressed, and the event handler is not called. */ -#define NRF_DRV_SPI_FLAG_HOLD_XFER (1UL << 3) /**< Set up the transfer but do not start it. */ -#define NRF_DRV_SPI_FLAG_REPEATED_XFER (1UL << 4) /**< Flag indicating that the transfer will be executed multiple times. */ - -/** - * @brief Single transfer descriptor structure. - */ -typedef struct -{ - uint8_t const * p_tx_buffer; ///< Pointer to TX buffer. - uint8_t tx_length; ///< TX buffer length. - uint8_t * p_rx_buffer; ///< Pointer to RX buffer. - uint8_t rx_length; ///< RX buffer length. -}nrf_drv_spi_xfer_desc_t; - -/** - * @brief Macro for setting up single transfer descriptor. - * - * This macro is for internal use only. - */ -#define NRF_DRV_SPI_SINGLE_XFER(p_tx, tx_len, p_rx, rx_len) \ - { \ - .p_tx_buffer = (uint8_t const *)(p_tx), \ - .tx_length = (tx_len), \ - .p_rx_buffer = (p_rx), \ - .rx_length = (rx_len), \ - } - -/** - * @brief Macro for setting duplex TX RX transfer. - */ -#define NRF_DRV_SPI_XFER_TRX(p_tx_buf, tx_length, p_rx_buf, rx_length) \ - NRF_DRV_SPI_SINGLE_XFER(p_tx_buf, tx_length, p_rx_buf, rx_length) - -/** - * @brief Macro for setting TX transfer. - */ -#define NRF_DRV_SPI_XFER_TX(p_buf, length) \ - NRF_DRV_SPI_SINGLE_XFER(p_buf, length, NULL, 0) - -/** - * @brief Macro for setting RX transfer. - */ -#define NRF_DRV_SPI_XFER_RX(p_buf, length) \ - NRF_DRV_SPI_SINGLE_XFER(NULL, 0, p_buf, length) - -/** - * @brief SPI master driver event types, passed to the handler routine provided - * during initialization. - */ -typedef enum -{ - NRF_DRV_SPI_EVENT_DONE, ///< Transfer done. -} nrf_drv_spi_evt_type_t; - -typedef struct -{ - nrf_drv_spi_evt_type_t type; ///< Event type. - union - { - nrf_drv_spi_xfer_desc_t done; ///< Event data for DONE event. - } data; -} nrf_drv_spi_evt_t; - -/** - * @brief SPI master driver event handler type. - */ -typedef void (* nrf_drv_spi_evt_handler_t)(nrf_drv_spi_evt_t const * p_event, - void * p_context); - - -/** - * @brief Function for initializing the SPI master driver instance. - * - * This function configures and enables the specified peripheral. - * - * @note MISO pin has pull down enabled. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_config Pointer to the structure with the initial configuration. - * - * @param handler Event handler provided by the user. If NULL, transfers - * will be performed in blocking mode. - * @param p_context Context passed to event handler. - * - * @retval NRF_SUCCESS If initialization was successful. - * @retval NRF_ERROR_INVALID_STATE If the driver was already initialized. - * @retval NRF_ERROR_BUSY If some other peripheral with the same - * instance ID is already in use. This is - * possible only if PERIPHERAL_RESOURCE_SHARING_ENABLED - * is set to a value other than zero. - */ -ret_code_t nrf_drv_spi_init(nrf_drv_spi_t const * const p_instance, - nrf_drv_spi_config_t const * p_config, - nrf_drv_spi_evt_handler_t handler, - void * p_context); - -/** - * @brief Function for uninitializing the SPI master driver instance. - * - * @note Configuration of pins is kept. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -__STATIC_INLINE -void nrf_drv_spi_uninit(nrf_drv_spi_t const * const p_instance); - -/** - * @brief Function for starting the SPI data transfer. - * - * If an event handler was provided in the @ref nrf_drv_spi_init call, this function - * returns immediately and the handler is called when the transfer is done. - * Otherwise, the transfer is performed in blocking mode, which means that this function - * returns when the transfer is finished. - * - * @note Peripherals using EasyDMA (for example, SPIM) require the transfer buffers - * to be placed in the Data RAM region. If they are not and an SPIM instance is - * used, this function will fail with the error code NRF_ERROR_INVALID_ADDR. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_tx_buffer Pointer to the transmit buffer. Can be NULL - * if there is nothing to send. - * @param tx_buffer_length Length of the transmit buffer. - * @param[in] p_rx_buffer Pointer to the receive buffer. Can be NULL - * if there is nothing to receive. - * @param rx_buffer_length Length of the receive buffer. - * - * @retval NRF_SUCCESS If the operation was successful. - * @retval NRF_ERROR_BUSY If a previously started transfer has not finished - * yet. - * @retval NRF_ERROR_INVALID_ADDR If the provided buffers are not placed in the Data - * RAM region. - */ -__STATIC_INLINE -ret_code_t nrf_drv_spi_transfer(nrf_drv_spi_t const * const p_instance, - uint8_t const * p_tx_buffer, - uint8_t tx_buffer_length, - uint8_t * p_rx_buffer, - uint8_t rx_buffer_length); - -/** - * @brief Function for starting the SPI data transfer with additional option flags. - * - * Function enables customizing the transfer by using option flags. - * - * Additional options are provided using the flags parameter: - * - * - @ref NRF_DRV_SPI_FLAG_TX_POSTINC and @ref NRF_DRV_SPI_FLAG_RX_POSTINC: - * Post-incrementation of buffer addresses. Supported only by SPIM. - * - @ref NRF_DRV_SPI_FLAG_HOLD_XFER: Driver is not starting the transfer. Use this - * flag if the transfer is triggered externally by PPI. Supported only by SPIM. Use - * @ref nrf_drv_spi_start_task_get to get the address of the start task. - * - @ref NRF_DRV_SPI_FLAG_NO_XFER_EVT_HANDLER: No user event handler after transfer - * completion. This also means no interrupt at the end of the transfer. Supported only by SPIM. - * If @ref NRF_DRV_SPI_FLAG_NO_XFER_EVT_HANDLER is used, the driver does not set the instance into - * busy state, so you must ensure that the next transfers are set up when SPIM is not active. - * @ref nrf_drv_spi_end_event_get function can be used to detect end of transfer. Option can be used - * together with @ref NRF_DRV_SPI_FLAG_REPEATED_XFER to prepare a sequence of SPI transfers - * without interruptions. - * - @ref NRF_DRV_SPI_FLAG_REPEATED_XFER: Prepare for repeated transfers. You can set - * up a number of transfers that will be triggered externally (for example by PPI). An example is - * a TXRX transfer with the options @ref NRF_DRV_SPI_FLAG_RX_POSTINC, - * @ref NRF_DRV_SPI_FLAG_NO_XFER_EVT_HANDLER, and @ref NRF_DRV_SPI_FLAG_REPEATED_XFER. After the - * transfer is set up, a set of transfers can be triggered by PPI that will read, for example, - * the same register of an external component and put it into a RAM buffer without any interrupts. - * @ref nrf_drv_spi_end_event_get can be used to get the address of the END event, which can be - * used to count the number of transfers. If @ref NRF_DRV_SPI_FLAG_REPEATED_XFER is used, - * the driver does not set the instance into busy state, so you must ensure that the next - * transfers are set up when SPIM is not active. Supported only by SPIM. - * @note Function is intended to be used only in non-blocking mode. - * - * @param p_instance Pointer to the driver instance structure. - * @param p_xfer_desc Pointer to the transfer descriptor. - * @param flags Transfer options (0 for default settings). - * - * @retval NRF_SUCCESS If the procedure was successful. - * @retval NRF_ERROR_BUSY If the driver is not ready for a new transfer. - * @retval NRF_ERROR_NOT_SUPPORTED If the provided parameters are not supported. - * @retval NRF_ERROR_INVALID_ADDR If the provided buffers are not placed in the Data - * RAM region. - */ -__STATIC_INLINE -ret_code_t nrf_drv_spi_xfer(nrf_drv_spi_t const * const p_instance, - nrf_drv_spi_xfer_desc_t const * p_xfer_desc, - uint32_t flags); - -/** - * @brief Function for returning the address of a SPIM start task. - * - * This function should be used if @ref nrf_drv_spi_xfer was called with the flag @ref NRF_DRV_SPI_FLAG_HOLD_XFER. - * In that case, the transfer is not started by the driver, but it must be started externally by PPI. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @return Start task address. - */ -__STATIC_INLINE -uint32_t nrf_drv_spi_start_task_get(nrf_drv_spi_t const * p_instance); - -/** - * @brief Function for returning the address of a END SPIM event. - * - * A END event can be used to detect the end of a transfer if the @ref NRF_DRV_SPI_FLAG_NO_XFER_EVT_HANDLER - * option is used. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @return END event address. - */ -__STATIC_INLINE -uint32_t nrf_drv_spi_end_event_get(nrf_drv_spi_t const * p_instance); - -/** - * @brief Function for aborting ongoing transfer. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -__STATIC_INLINE -void nrf_drv_spi_abort(nrf_drv_spi_t const * p_instance); - - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -#if defined(SPI_PRESENT) && !defined(SPIM_PRESENT) -#define NRF_DRV_SPI_WITH_SPI -#elif !defined(SPI_PRESENT) && defined(SPIM_PRESENT) -#define NRF_DRV_SPI_WITH_SPIM -#else -#if (NRFX_CHECK(SPI0_ENABLED) && NRFX_CHECK(SPI0_USE_EASY_DMA)) || \ - (NRFX_CHECK(SPI1_ENABLED) && NRFX_CHECK(SPI1_USE_EASY_DMA)) || \ - (NRFX_CHECK(SPI2_ENABLED) && NRFX_CHECK(SPI2_USE_EASY_DMA)) - #define NRF_DRV_SPI_WITH_SPIM -#endif -#if (NRFX_CHECK(SPI0_ENABLED) && !NRFX_CHECK(SPI0_USE_EASY_DMA)) || \ - (NRFX_CHECK(SPI1_ENABLED) && !NRFX_CHECK(SPI1_USE_EASY_DMA)) || \ - (NRFX_CHECK(SPI2_ENABLED) && !NRFX_CHECK(SPI2_USE_EASY_DMA)) - #define NRF_DRV_SPI_WITH_SPI -#endif -#endif -#if defined(NRF_DRV_SPI_WITH_SPIM) && defined(NRF_DRV_SPI_WITH_SPI) - #define NRF_DRV_SPI_USE_SPIM (p_instance->use_easy_dma) -#elif defined(NRF_DRV_SPI_WITH_SPIM) - #define NRF_DRV_SPI_USE_SPIM true -#else - #define NRF_DRV_SPI_USE_SPIM false -#endif -#define NRF_DRV_SPI_USE_SPI (!NRF_DRV_SPI_USE_SPIM) - -__STATIC_INLINE -void nrf_drv_spi_uninit(nrf_drv_spi_t const * p_instance) -{ - if (NRF_DRV_SPI_USE_SPIM) - { - nrfx_spim_uninit(&p_instance->u.spim); - } - else if (NRF_DRV_SPI_USE_SPI) - { - nrfx_spi_uninit(&p_instance->u.spi); - } -} - -__STATIC_INLINE -ret_code_t nrf_drv_spi_transfer(nrf_drv_spi_t const * const p_instance, - uint8_t const * p_tx_buffer, - uint8_t tx_buffer_length, - uint8_t * p_rx_buffer, - uint8_t rx_buffer_length) -{ - ret_code_t result = 0; - if (NRF_DRV_SPI_USE_SPIM) - { - #ifdef SPIM_PRESENT - nrfx_spim_xfer_desc_t const spim_xfer_desc = - { - .p_tx_buffer = p_tx_buffer, - .tx_length = tx_buffer_length, - .p_rx_buffer = p_rx_buffer, - .rx_length = rx_buffer_length, - }; - result = nrfx_spim_xfer(&p_instance->u.spim, &spim_xfer_desc, 0); - #endif - } - else if (NRF_DRV_SPI_USE_SPI) - { - #ifdef SPI_PRESENT - nrfx_spi_xfer_desc_t const spi_xfer_desc = - { - .p_tx_buffer = p_tx_buffer, - .tx_length = tx_buffer_length, - .p_rx_buffer = p_rx_buffer, - .rx_length = rx_buffer_length, - }; - result = nrfx_spi_xfer(&p_instance->u.spi, &spi_xfer_desc, 0); - #endif - } - return result; -} - -__STATIC_INLINE -ret_code_t nrf_drv_spi_xfer(nrf_drv_spi_t const * const p_instance, - nrf_drv_spi_xfer_desc_t const * p_xfer_desc, - uint32_t flags) -{ - ret_code_t result = 0; - if (NRF_DRV_SPI_USE_SPIM) - { - #ifdef SPIM_PRESENT - nrfx_spim_xfer_desc_t const spim_xfer_desc = - { - .p_tx_buffer = p_xfer_desc->p_tx_buffer, - .tx_length = p_xfer_desc->tx_length, - .p_rx_buffer = p_xfer_desc->p_rx_buffer, - .rx_length = p_xfer_desc->rx_length, - }; - result = nrfx_spim_xfer(&p_instance->u.spim, &spim_xfer_desc, flags); - #endif - } - else if (NRF_DRV_SPI_USE_SPI) - { - #ifdef SPI_PRESENT - nrfx_spi_xfer_desc_t const spi_xfer_desc = - { - .p_tx_buffer = p_xfer_desc->p_tx_buffer, - .tx_length = p_xfer_desc->tx_length, - .p_rx_buffer = p_xfer_desc->p_rx_buffer, - .rx_length = p_xfer_desc->rx_length, - }; - result = nrfx_spi_xfer(&p_instance->u.spi, &spi_xfer_desc, flags); - #endif - } - return result; -} - -__STATIC_INLINE -uint32_t nrf_drv_spi_start_task_get(nrf_drv_spi_t const * p_instance) -{ - uint32_t result = 0; - if (NRF_DRV_SPI_USE_SPIM) - { - result = nrfx_spim_start_task_get(&p_instance->u.spim); - } - else if (NRF_DRV_SPI_USE_SPI) - { - NRFX_ASSERT(false); // not supported - result = 0; - } - return result; -} - -__STATIC_INLINE -uint32_t nrf_drv_spi_end_event_get(nrf_drv_spi_t const * p_instance) -{ - uint32_t result = 0; - if (NRF_DRV_SPI_USE_SPIM) - { - result = nrfx_spim_end_event_get(&p_instance->u.spim); - } - else if (NRF_DRV_SPI_USE_SPI) - { - NRFX_ASSERT(false); // not supported - result = 0; - } - return result; -} - -__STATIC_INLINE -void nrf_drv_spi_abort(nrf_drv_spi_t const * p_instance) -{ - if (NRF_DRV_SPI_USE_SPIM) - { - nrfx_spim_abort(&p_instance->u.spim); - } - else if (NRF_DRV_SPI_USE_SPI) - { - nrfx_spi_abort(&p_instance->u.spi); - } -} - -#endif // SUPPRESS_INLINE_IMPLEMENTATION - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_SPI_H__ diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_spis.c b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_spis.c deleted file mode 100644 index 373719bf4f..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_spis.c +++ /dev/null @@ -1,63 +0,0 @@ -/** - * Copyright (c) 2018 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include "nrf_drv_spis.h" - -static nrf_drv_spis_event_handler_t m_handlers[SPIS_COUNT]; - -static void spis_event_handler(nrfx_spis_evt_t const * p_event, - void * p_context) -{ - uint32_t inst_idx = (uint32_t)p_context; - m_handlers[inst_idx](*p_event); -} - -ret_code_t nrf_drv_spis_init(nrf_drv_spis_t const * const p_instance, - nrf_drv_spis_config_t const * p_config, - nrf_drv_spis_event_handler_t event_handler) -{ - uint32_t inst_idx = p_instance->drv_inst_idx; - m_handlers[inst_idx] = event_handler; - - return nrfx_spis_init(p_instance, - p_config, - spis_event_handler, - (void *)inst_idx); -} diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_spis.h b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_spis.h deleted file mode 100644 index c5fc2ed3f8..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_spis.h +++ /dev/null @@ -1,144 +0,0 @@ -/** - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_DRV_SPIS_H__ -#define NRF_DRV_SPIS_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_drv_spis SPIS driver - legacy layer - * @{ - * @ingroup nrf_spis - * - * @brief Layer providing compatibility with the former API. - */ - -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_spis_t nrf_drv_spis_t; -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_spis_config_t nrf_drv_spis_config_t; -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_spis_evt_t nrf_drv_spis_event_t; - -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_SPIS_INSTANCE NRFX_SPIS_INSTANCE -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_SPIS_DEFAULT_CONFIG NRFX_SPIS_DEFAULT_CONFIG -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_SPIS_DEFAULT_CSN_PULLUP NRFX_SPIS_DEFAULT_CSN_PULLUP -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_SPIS_DEFAULT_MISO_DRIVE NRFX_SPIS_DEFAULT_MISO_DRIVE -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_SPIS_PIN_NOT_USED NRFX_SPIS_PIN_NOT_USED - -/** @brief Macro for providing API backward compatibility. */ -#define NRF_DRV_SPIS_BIT_ORDER_LSB_FIRST NRF_SPIS_BIT_ORDER_LSB_FIRST -/** @brief Macro for providing API backward compatibility. */ -#define NRF_DRV_SPIS_BIT_ORDER_MSB_FIRST NRF_SPIS_BIT_ORDER_MSB_FIRST -/** @brief Macro for providing API backward compatibility. */ -#define nrf_drv_spis_endian_t nrf_spis_bit_order_t -/** @brief Macro for providing API backward compatibility. */ -#define NRF_DRV_SPIS_MODE_0 NRF_SPIS_MODE_0 -/** @brief Macro for providing API backward compatibility. */ -#define NRF_DRV_SPIS_MODE_1 NRF_SPIS_MODE_1 -/** @brief Macro for providing API backward compatibility. */ -#define NRF_DRV_SPIS_MODE_2 NRF_SPIS_MODE_2 -/** @brief Macro for providing API backward compatibility. */ -#define NRF_DRV_SPIS_MODE_3 NRF_SPIS_MODE_3 -/** @brief Macro for providing API backward compatibility. */ -#define nrf_drv_spis_mode_t nrf_spis_mode_t -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_SPIS_BUFFERS_SET_DONE NRFX_SPIS_BUFFERS_SET_DONE -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_SPIS_XFER_DONE NRFX_SPIS_XFER_DONE -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_SPIS_EVT_TYPE_MAX NRFX_SPIS_EVT_TYPE_MAX -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_spis_event_type_t nrfx_spis_evt_type_t - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_spis_uninit nrfx_spis_uninit -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_spis_buffers_set nrfx_spis_buffers_set - -/** @brief SPI slave event callback function type. - * - * @param[in] event SPI slave driver event. - */ -typedef void (*nrf_drv_spis_event_handler_t)(nrf_drv_spis_event_t event); - -/** @brief Function for initializing the SPI slave driver instance. - * - * @note When the nRF52 Anomaly 109 workaround for SPIS is enabled, this function - * initializes the GPIOTE driver as well, and uses one of GPIOTE channels - * to detect falling edges on CSN pin. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_config Pointer to the structure with the initial configuration. - * If NULL, the default configuration will be used. - * @param[in] event_handler Function to be called by the SPI slave driver upon event. - * - * @retval NRF_SUCCESS If the initialization was successful. - * @retval NRF_ERROR_INVALID_PARAM If an invalid parameter is supplied. - * @retval NRFX_ERROR_INVALID_STATE If the instance is already initialized. - * @retval NRF_ERROR_BUSY If some other peripheral with the same - * instance ID is already in use. This is - * possible only if PERIPHERAL_RESOURCE_SHARING_ENABLED - * is set to a value other than zero. - * @retval NRF_ERROR_INTERNAL GPIOTE channel for detecting falling edges - * on CSN pin cannot be initialized. Possible - * only when using nRF52 Anomaly 109 workaround. - */ -ret_code_t nrf_drv_spis_init(nrf_drv_spis_t const * const p_instance, - nrf_drv_spis_config_t const * p_config, - nrf_drv_spis_event_handler_t event_handler); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_SPIS_H__ diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_swi.c b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_swi.c deleted file mode 100644 index 431e4b3d64..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_swi.c +++ /dev/null @@ -1,66 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include "nrf_drv_swi.h" - -static nrfx_drv_state_t m_drv_state = NRFX_DRV_STATE_UNINITIALIZED; - -ret_code_t nrf_drv_swi_init(void) -{ - if (m_drv_state == NRFX_DRV_STATE_INITIALIZED) - { - return NRF_ERROR_MODULE_ALREADY_INITIALIZED; - } - - m_drv_state = NRFX_DRV_STATE_INITIALIZED; - return NRF_SUCCESS; -} - -ret_code_t nrf_drv_swi_uninit(void) -{ - if (m_drv_state == NRFX_DRV_STATE_UNINITIALIZED) - { - return NRF_ERROR_INVALID_STATE; - } - - nrfx_swi_all_free(); - m_drv_state = NRFX_DRV_STATE_UNINITIALIZED; - return NRF_SUCCESS; -} diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_swi.h b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_swi.h deleted file mode 100644 index 24e52e33ef..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_swi.h +++ /dev/null @@ -1,108 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_DRV_SWI_H__ -#define NRF_DRV_SWI_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_drv_swi SWI driver - legacy layer - * @{ - * @ingroup nrf_swi_egu - * - * @brief Layer providing compatibility with the former API. - */ - -/** @brief Macro for forwarding the new implementation. */ -#define NRF_SWI_UNALLOCATED NRFX_SWI_UNALLOCATED -/** @brief Macro for forwarding the new implementation. */ -#define SWI_DEFAULT_PRIORITY NRFX_SWI_DEFAULT_PRIORITY - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_swi_t nrfx_swi_t -/** @brief Macro for forwarding the new implementation. */ -#define nrf_swi_flags_t nrfx_swi_flags_t -/** @brief Macro for forwarding the new implementation. */ -#define nrf_swi_handler_t nrfx_swi_handler_t - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_swi_alloc nrfx_swi_alloc -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_swi_free nrfx_swi_free -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_swi_trigger nrfx_swi_trigger - -#if NRF_MODULE_ENABLED(EGU) || defined(__SDK_DOXYGEN__) -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_swi_task_trigger_address_get nrfx_swi_task_trigger_address_get -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_swi_event_triggered_address_get nrfx_swi_event_triggered_address_get -#endif // NRF_MODULE_ENABLED(EGU) || defined(__SDK_DOXYGEN__) - -/** - * @brief Function for initializing the SWI module. - * - * @retval NRF_SUCCESS If the module was successfully initialized. - * @retval NRF_ERROR_MODULE_ALREADY_INITIALIZED If the module has already been initialized. - */ -ret_code_t nrf_drv_swi_init(void); - -/** - * @brief Function for uninitializing the SWI module. - * - * This function also frees all SWIs. - * - * @retval NRF_SUCCESS If the module was successfully uninitialized. - * @retval NRF_ERROR_INVALID_STATE If the module has not been initialized yet. - */ -ret_code_t nrf_drv_swi_uninit(void); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_SWI_H__ diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_systick.h b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_systick.h deleted file mode 100644 index 440868c509..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_systick.h +++ /dev/null @@ -1,80 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_DRV_SYSTICK_H__ -#define NRF_DRV_SYSTICK_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_drv_systick ARM(R) SysTick driver - legacy layer - * @{ - * @ingroup nrf_systick - * - * @brief Layer providing compatibility with the former API. - */ - -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_systick_state_t nrf_drv_systick_state_t; - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_systick_init nrfx_systick_init -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_systick_get nrfx_systick_get -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_systick_test nrfx_systick_test -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_systick_delay_ticks nrfx_systick_delay_ticks -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_systick_delay_us nrfx_systick_delay_us -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_systick_delay_ms nrfx_systick_delay_ms - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_SYSTICK_H__ diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_timer.h b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_timer.h deleted file mode 100644 index 1e66c37102..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_timer.h +++ /dev/null @@ -1,121 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_DRV_TIMER_H__ -#define NRF_DRV_TIMER_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_drv_timer TIMER driver - legacy layer - * @{ - * @ingroup nrf_timer - * - * @brief Layer providing compatibility with the former API. - */ - -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_timer_t nrf_drv_timer_t; -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_timer_config_t nrf_drv_timer_config_t; - -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_TIMER_INSTANCE NRFX_TIMER_INSTANCE -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_TIMER_DEFAULT_CONFIG NRFX_TIMER_DEFAULT_CONFIG - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_timer_event_handler_t nrfx_timer_event_handler_t - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_timer_init nrfx_timer_init -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_timer_uninit nrfx_timer_uninit -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_timer_enable nrfx_timer_enable -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_timer_disable nrfx_timer_disable -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_timer_is_enabled nrfx_timer_is_enabled -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_timer_pause nrfx_timer_pause -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_timer_resume nrfx_timer_resume -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_timer_clear nrfx_timer_clear -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_timer_increment nrfx_timer_increment -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_timer_capture nrfx_timer_capture -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_timer_capture_get nrfx_timer_capture_get -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_timer_compare nrfx_timer_compare -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_timer_extended_compare nrfx_timer_extended_compare -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_timer_us_to_ticks nrfx_timer_us_to_ticks -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_timer_ms_to_ticks nrfx_timer_ms_to_ticks -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_timer_compare_int_enable nrfx_timer_compare_int_enable -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_timer_compare_int_disable nrfx_timer_compare_int_disable - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_timer_task_address_get nrfx_timer_task_address_get -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_timer_capture_task_address_get nrfx_timer_capture_task_address_get -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_timer_event_address_get nrfx_timer_event_address_get -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_timer_compare_event_address_get nrfx_timer_compare_event_address_get - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_TIMER_H__ diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_twi.c b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_twi.c deleted file mode 100644 index 6e7e82436a..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_twi.c +++ /dev/null @@ -1,192 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include "nrf_drv_twi.h" -#include -#include - -#ifdef TWIM_PRESENT -#define INSTANCE_COUNT TWIM_COUNT -#else -#define INSTANCE_COUNT TWI_COUNT -#endif - -#define SCL_PIN_INIT_CONF \ - ( (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \ - | (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) \ - | (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) \ - | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \ - | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos)) - -#define SDA_PIN_INIT_CONF SCL_PIN_INIT_CONF - -#define SDA_PIN_UNINIT_CONF \ - ( (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \ - | (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) \ - | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) \ - | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) \ - | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos)) - -#define SCL_PIN_UNINIT_CONF SDA_PIN_UNINIT_CONF - -#define SCL_PIN_INIT_CONF_CLR \ - ( (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \ - | (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) \ - | (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) \ - | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \ - | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos)) - -#define SDA_PIN_INIT_CONF_CLR SCL_PIN_INIT_CONF_CLR - -static nrf_drv_twi_evt_handler_t m_handlers[INSTANCE_COUNT]; -static void * m_contexts[INSTANCE_COUNT]; - -static void twi_clear_bus(nrf_drv_twi_config_t const * p_config) -{ - NRF_GPIO->PIN_CNF[p_config->scl] = SCL_PIN_INIT_CONF; - NRF_GPIO->PIN_CNF[p_config->sda] = SDA_PIN_INIT_CONF; - - nrf_gpio_pin_set(p_config->scl); - nrf_gpio_pin_set(p_config->sda); - - NRF_GPIO->PIN_CNF[p_config->scl] = SCL_PIN_INIT_CONF_CLR; - NRF_GPIO->PIN_CNF[p_config->sda] = SDA_PIN_INIT_CONF_CLR; - - nrf_delay_us(4); - - for (int i = 0; i < 9; i++) - { - if (nrf_gpio_pin_read(p_config->sda)) - { - if (i == 0) - { - return; - } - else - { - break; - } - } - nrf_gpio_pin_clear(p_config->scl); - nrf_delay_us(4); - nrf_gpio_pin_set(p_config->scl); - nrf_delay_us(4); - } - nrf_gpio_pin_clear(p_config->sda); - nrf_delay_us(4); - nrf_gpio_pin_set(p_config->sda); -} - -#ifdef TWIM_PRESENT -static void twim_evt_handler(nrfx_twim_evt_t const * p_event, - void * p_context) -{ - uint32_t inst_idx = (uint32_t)p_context; - nrf_drv_twi_evt_t const event = - { - .type = (nrf_drv_twi_evt_type_t)p_event->type, - .xfer_desc = - { - .type = (nrf_drv_twi_xfer_type_t)p_event->xfer_desc.type, - .address = p_event->xfer_desc.address, - .primary_length = p_event->xfer_desc.primary_length, - .secondary_length = p_event->xfer_desc.secondary_length, - .p_primary_buf = p_event->xfer_desc.p_primary_buf, - .p_secondary_buf = p_event->xfer_desc.p_secondary_buf, - } - }; - m_handlers[inst_idx](&event, m_contexts[inst_idx]); -} -#endif // TWIM_PRESENT - -#ifdef TWI_PRESENT -static void twi_evt_handler(nrfx_twi_evt_t const * p_event, - void * p_context) -{ - uint32_t inst_idx = (uint32_t)p_context; - nrf_drv_twi_evt_t const event = - { - .type = (nrf_drv_twi_evt_type_t)p_event->type, - .xfer_desc = - { - .type = (nrf_drv_twi_xfer_type_t)p_event->xfer_desc.type, - .address = p_event->xfer_desc.address, - .primary_length = p_event->xfer_desc.primary_length, - .secondary_length = p_event->xfer_desc.secondary_length, - .p_primary_buf = p_event->xfer_desc.p_primary_buf, - .p_secondary_buf = p_event->xfer_desc.p_secondary_buf, - } - }; - m_handlers[inst_idx](&event, m_contexts[inst_idx]); -} -#endif // TWI_PRESENT - -ret_code_t nrf_drv_twi_init(nrf_drv_twi_t const * p_instance, - nrf_drv_twi_config_t const * p_config, - nrf_drv_twi_evt_handler_t event_handler, - void * p_context) -{ - uint32_t inst_idx = p_instance->inst_idx; - m_handlers[inst_idx] = event_handler; - m_contexts[inst_idx] = p_context; - - if(p_config->clear_bus_init) - { - /* Send clocks (max 9) until slave device back from stuck mode */ - twi_clear_bus(p_config); - } - - ret_code_t result = 0; - if (NRF_DRV_TWI_USE_TWIM) - { - result = nrfx_twim_init(&p_instance->u.twim, - (nrfx_twim_config_t const *)p_config, - event_handler ? twim_evt_handler : NULL, - (void *)inst_idx); - } - else if (NRF_DRV_TWI_USE_TWI) - { - result = nrfx_twi_init(&p_instance->u.twi, - (nrfx_twi_config_t const *)p_config, - event_handler ? twi_evt_handler : NULL, - (void *)inst_idx); - } - return result; -} diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_twi.h b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_twi.h deleted file mode 100644 index cf8cb862f1..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_twi.h +++ /dev/null @@ -1,686 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_DRV_TWI_H__ -#define NRF_DRV_TWI_H__ - -#include -#ifdef TWIM_PRESENT - #include -#else - // Compilers (at least the smart ones) will remove the TWIM related code - // (blocks starting with "if (NRF_DRV_TWI_USE_TWIM)") when it is not used, - // but to perform the compilation they need the following definitions. - #define nrfx_twim_init(...) 0 - #define nrfx_twim_uninit(...) - #define nrfx_twim_enable(...) - #define nrfx_twim_disable(...) - #define nrfx_twim_tx(...) 0 - #define nrfx_twim_rx(...) 0 - #define nrfx_twim_is_busy(...) 0 - #define nrfx_twim_start_task_get(...) 0 - #define nrfx_twim_stopped_event_get(...) 0 -#endif - -#ifdef TWI_PRESENT - #include -#else - // Compilers (at least the smart ones) will remove the TWI related code - // (blocks starting with "if (NRF_DRV_TWI_USE_TWI)") when it is not used, - // but to perform the compilation they need the following definitions. - #define nrfx_twi_init(...) 0 - #define nrfx_twi_uninit(...) - #define nrfx_twi_enable(...) - #define nrfx_twi_disable(...) - #define nrfx_twi_tx(...) 0 - #define nrfx_twi_rx(...) 0 - #define nrfx_twi_is_busy(...) 0 - #define nrfx_twi_data_count_get(...) 0 - #define nrfx_twi_stopped_event_get(...) 0 - - // This part is for old modules that use directly TWI HAL definitions - // (to make them compilable for chips that have only TWIM). - #define NRF_TWI_ERROR_ADDRESS_NACK NRF_TWIM_ERROR_ADDRESS_NACK - #define NRF_TWI_ERROR_DATA_NACK NRF_TWIM_ERROR_DATA_NACK - #define NRF_TWI_FREQ_100K NRF_TWIM_FREQ_100K - #define NRF_TWI_FREQ_250K NRF_TWIM_FREQ_250K - #define NRF_TWI_FREQ_400K NRF_TWIM_FREQ_400K -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_drv_twi TWI driver - legacy layer - * @{ - * @ingroup nrf_twi - * @brief Layer providing compatibility with the former API. - */ - -/** - * @brief Structure for the TWI master driver instance. - */ -typedef struct -{ - uint8_t inst_idx; - union - { -#ifdef TWIM_PRESENT - nrfx_twim_t twim; -#endif -#ifdef TWI_PRESENT - nrfx_twi_t twi; -#endif - } u; - bool use_easy_dma; -} nrf_drv_twi_t; - -/** - * @brief Macro for creating a TWI master driver instance. - */ -#define NRF_DRV_TWI_INSTANCE(id) NRF_DRV_TWI_INSTANCE_(id) -#define NRF_DRV_TWI_INSTANCE_(id) NRF_DRV_TWI_INSTANCE_ ## id -#if NRFX_CHECK(NRFX_TWIM0_ENABLED) - #define NRF_DRV_TWI_INSTANCE_0 \ - { 0, { .twim = NRFX_TWIM_INSTANCE(0) }, true } -#elif NRFX_CHECK(NRFX_TWI0_ENABLED) - #define NRF_DRV_TWI_INSTANCE_0 \ - { 0, { .twi = NRFX_TWI_INSTANCE(0) }, false } -#endif -#if NRFX_CHECK(NRFX_TWIM1_ENABLED) - #define NRF_DRV_TWI_INSTANCE_1 \ - { 1, { .twim = NRFX_TWIM_INSTANCE(1) }, true } -#elif NRFX_CHECK(NRFX_TWI1_ENABLED) - #define NRF_DRV_TWI_INSTANCE_1 \ - { 1, { .twi = NRFX_TWI_INSTANCE(1) }, false } -#endif - -/** - * @brief TWI master clock frequency. - */ -typedef enum -{ - NRF_DRV_TWI_FREQ_100K = NRF_TWI_FREQ_100K , ///< 100 kbps. - NRF_DRV_TWI_FREQ_250K = NRF_TWI_FREQ_250K , ///< 250 kbps. - NRF_DRV_TWI_FREQ_400K = NRF_TWI_FREQ_400K ///< 400 kbps. -} nrf_drv_twi_frequency_t; - -/** - * @brief Structure for the TWI master driver instance configuration. - */ -typedef struct -{ - uint32_t scl; ///< SCL pin number. - uint32_t sda; ///< SDA pin number. - nrf_drv_twi_frequency_t frequency; ///< TWI frequency. - uint8_t interrupt_priority; ///< Interrupt priority. - bool clear_bus_init; ///< Clear bus during init. - bool hold_bus_uninit; ///< Hold pull up state on gpio pins after uninit. -} nrf_drv_twi_config_t; - -/** - * @brief TWI master driver instance default configuration. - */ -#define NRF_DRV_TWI_DEFAULT_CONFIG \ -{ \ - .frequency = (nrf_drv_twi_frequency_t)TWI_DEFAULT_CONFIG_FREQUENCY, \ - .scl = 31, \ - .sda = 31, \ - .interrupt_priority = TWI_DEFAULT_CONFIG_IRQ_PRIORITY, \ - .clear_bus_init = TWI_DEFAULT_CONFIG_CLR_BUS_INIT, \ - .hold_bus_uninit = TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT, \ -} - -#define NRF_DRV_TWI_FLAG_TX_POSTINC (1UL << 0) /**< TX buffer address incremented after transfer. */ -#define NRF_DRV_TWI_FLAG_RX_POSTINC (1UL << 1) /**< RX buffer address incremented after transfer. */ -#define NRF_DRV_TWI_FLAG_NO_XFER_EVT_HANDLER (1UL << 2) /**< Interrupt after each transfer is suppressed, and the event handler is not called. */ -#define NRF_DRV_TWI_FLAG_HOLD_XFER (1UL << 3) /**< Set up the transfer but do not start it. */ -#define NRF_DRV_TWI_FLAG_REPEATED_XFER (1UL << 4) /**< Flag indicating that the transfer will be executed multiple times. */ -#define NRF_DRV_TWI_FLAG_TX_NO_STOP (1UL << 5) /**< Flag indicating that the TX transfer will not end with a stop condition. */ - -/** - * @brief TWI master driver event types. - */ -typedef enum -{ - NRF_DRV_TWI_EVT_DONE, ///< Transfer completed event. - NRF_DRV_TWI_EVT_ADDRESS_NACK, ///< Error event: NACK received after sending the address. - NRF_DRV_TWI_EVT_DATA_NACK ///< Error event: NACK received after sending a data byte. -} nrf_drv_twi_evt_type_t; - -/** - * @brief TWI master driver transfer types. - */ -typedef enum -{ - NRF_DRV_TWI_XFER_TX, ///< TX transfer. - NRF_DRV_TWI_XFER_RX, ///< RX transfer. - NRF_DRV_TWI_XFER_TXRX, ///< TX transfer followed by RX transfer with repeated start. - NRF_DRV_TWI_XFER_TXTX ///< TX transfer followed by TX transfer with repeated start. -} nrf_drv_twi_xfer_type_t; - -/** - * @brief Structure for a TWI transfer descriptor. - */ -typedef struct -{ - nrf_drv_twi_xfer_type_t type; ///< Type of transfer. - uint8_t address; ///< Slave address. - uint8_t primary_length; ///< Number of bytes transferred. - uint8_t secondary_length; ///< Number of bytes transferred. - uint8_t * p_primary_buf; ///< Pointer to transferred data. - uint8_t * p_secondary_buf; ///< Pointer to transferred data. -} nrf_drv_twi_xfer_desc_t; - - -/**@brief Macro for setting the TX transfer descriptor. */ -#define NRF_DRV_TWI_XFER_DESC_TX(addr, p_data, length) \ - { \ - .type = NRF_DRV_TWI_XFER_TX, \ - .address = addr, \ - .primary_length = length, \ - .p_primary_buf = p_data, \ - } - -/**@brief Macro for setting the RX transfer descriptor. */ -#define NRF_DRV_TWI_XFER_DESC_RX(addr, p_data, length) \ - { \ - .type = NRF_DRV_TWI_XFER_RX, \ - .address = addr, \ - .primary_length = length, \ - .p_primary_buf = p_data, \ - } - -/**@brief Macro for setting the TXRX transfer descriptor. */ -#define NRF_DRV_TWI_XFER_DESC_TXRX(addr, p_tx, tx_len, p_rx, rx_len) \ - { \ - .type = NRF_DRV_TWI_XFER_TXRX, \ - .address = addr, \ - .primary_length = tx_len, \ - .secondary_length = rx_len, \ - .p_primary_buf = p_tx, \ - .p_secondary_buf = p_rx, \ - } - -/**@brief Macro for setting the TXTX transfer descriptor. */ -#define NRF_DRV_TWI_XFER_DESC_TXTX(addr, p_tx, tx_len, p_tx2, tx_len2) \ - { \ - .type = NRF_DRV_TWI_XFER_TXTX, \ - .address = addr, \ - .primary_length = tx_len, \ - .secondary_length = tx_len2, \ - .p_primary_buf = p_tx, \ - .p_secondary_buf = p_tx2, \ - } - -/** - * @brief Structure for a TWI event. - */ -typedef struct -{ - nrf_drv_twi_evt_type_t type; ///< Event type. - nrf_drv_twi_xfer_desc_t xfer_desc; ///< Transfer details. -} nrf_drv_twi_evt_t; - -/** - * @brief TWI event handler prototype. - */ -typedef void (* nrf_drv_twi_evt_handler_t)(nrf_drv_twi_evt_t const * p_event, - void * p_context); - -/** - * @brief Function for initializing the TWI driver instance. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_config Initial configuration. - * @param[in] event_handler Event handler provided by the user. If NULL, blocking mode is enabled. - * @param[in] p_context Context passed to event handler. - * - * @retval NRF_SUCCESS If initialization was successful. - * @retval NRF_ERROR_INVALID_STATE If the driver is in invalid state. - * @retval NRF_ERROR_BUSY If some other peripheral with the same - * instance ID is already in use. This is - * possible only if PERIPHERAL_RESOURCE_SHARING_ENABLED - * is set to a value other than zero. - */ -ret_code_t nrf_drv_twi_init(nrf_drv_twi_t const * p_instance, - nrf_drv_twi_config_t const * p_config, - nrf_drv_twi_evt_handler_t event_handler, - void * p_context); - -/** - * @brief Function for uninitializing the TWI instance. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -__STATIC_INLINE -void nrf_drv_twi_uninit(nrf_drv_twi_t const * p_instance); - -/** - * @brief Function for enabling the TWI instance. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -__STATIC_INLINE -void nrf_drv_twi_enable(nrf_drv_twi_t const * p_instance); - -/** - * @brief Function for disabling the TWI instance. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -__STATIC_INLINE -void nrf_drv_twi_disable(nrf_drv_twi_t const * p_instance); - -/** - * @brief Function for sending data to a TWI slave. - * - * The transmission will be stopped when an error occurs. If a transfer is ongoing, - * the function returns the error code @ref NRF_ERROR_BUSY. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] address Address of a specific slave device (only 7 LSB). - * @param[in] p_data Pointer to a transmit buffer. - * @param[in] length Number of bytes to send. - * @param[in] no_stop If set, the stop condition is not generated on the bus - * after the transfer has completed successfully (allowing - * for a repeated start in the next transfer). - * - * @retval NRF_SUCCESS If the procedure was successful. - * @retval NRF_ERROR_BUSY If the driver is not ready for a new transfer. - * @retval NRF_ERROR_INTERNAL If an error was detected by hardware. - * @retval NRF_ERROR_INVALID_ADDR If the EasyDMA is used and memory adress in not in RAM. - * @retval NRF_ERROR_DRV_TWI_ERR_ANACK If NACK received after sending the address in polling mode. - * @retval NRF_ERROR_DRV_TWI_ERR_DNACK If NACK received after sending a data byte in polling mode. - */ -__STATIC_INLINE -ret_code_t nrf_drv_twi_tx(nrf_drv_twi_t const * p_instance, - uint8_t address, - uint8_t const * p_data, - uint8_t length, - bool no_stop); - -/** - * @brief Function for reading data from a TWI slave. - * - * The transmission will be stopped when an error occurs. If a transfer is ongoing, - * the function returns the error code @ref NRF_ERROR_BUSY. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] address Address of a specific slave device (only 7 LSB). - * @param[in] p_data Pointer to a receive buffer. - * @param[in] length Number of bytes to be received. - * - * @retval NRF_SUCCESS If the procedure was successful. - * @retval NRF_ERROR_BUSY If the driver is not ready for a new transfer. - * @retval NRF_ERROR_INTERNAL If an error was detected by hardware. - * @retval NRF_ERROR_DRV_TWI_ERR_OVERRUN If the unread data was replaced by new data - * @retval NRF_ERROR_DRV_TWI_ERR_ANACK If NACK received after sending the address in polling mode. - * @retval NRF_ERROR_DRV_TWI_ERR_DNACK If NACK received after sending a data byte in polling mode. - */ -__STATIC_INLINE -ret_code_t nrf_drv_twi_rx(nrf_drv_twi_t const * p_instance, - uint8_t address, - uint8_t * p_data, - uint8_t length); - -/** - * @brief Function for preparing a TWI transfer. - * - * The following transfer types can be configured (@ref nrf_drv_twi_xfer_desc_t::type): - * - @ref NRF_DRV_TWI_XFER_TXRX: Write operation followed by a read operation (without STOP condition in between). - * - @ref NRF_DRV_TWI_XFER_TXTX: Write operation followed by a write operation (without STOP condition in between). - * - @ref NRF_DRV_TWI_XFER_TX: Write operation (with or without STOP condition). - * - @ref NRF_DRV_TWI_XFER_RX: Read operation (with STOP condition). - * - * Additional options are provided using the flags parameter: - * - @ref NRF_DRV_TWI_FLAG_TX_POSTINC and @ref NRF_DRV_TWI_FLAG_RX_POSTINC: Post-incrementation of buffer addresses. Supported only by TWIM. - * - @ref NRF_DRV_TWI_FLAG_NO_XFER_EVT_HANDLER: No user event handler after transfer completion. In most cases, this also means no interrupt at the end of the transfer. - * - @ref NRF_DRV_TWI_FLAG_HOLD_XFER: Driver is not starting the transfer. Use this flag if the transfer is triggered externally by PPI. Supported only by TWIM. - * Use @ref nrf_drv_twi_start_task_get to get the address of the start task. - * - @ref NRF_DRV_TWI_FLAG_REPEATED_XFER: Prepare for repeated transfers. You can set up a number of transfers that will be triggered externally (for example by PPI). - * An example is a TXRX transfer with the options @ref NRF_DRV_TWI_FLAG_RX_POSTINC, @ref NRF_DRV_TWI_FLAG_NO_XFER_EVT_HANDLER, and @ref NRF_DRV_TWI_FLAG_REPEATED_XFER. - * After the transfer is set up, a set of transfers can be triggered by PPI that will read, for example, the same register of an - * external component and put it into a RAM buffer without any interrupts. @ref nrf_drv_twi_stopped_event_get can be used to get the - * address of the STOPPED event, which can be used to count the number of transfers. If @ref NRF_DRV_TWI_FLAG_REPEATED_XFER is used, - * the driver does not set the driver instance into busy state, so you must ensure that the next transfers are set up - * when TWIM is not active. Supported only by TWIM. - * - @ref NRF_DRV_TWI_FLAG_TX_NO_STOP: No stop condition after TX transfer. - * - * @note - * Some flag combinations are invalid: - * - @ref NRF_DRV_TWI_FLAG_TX_NO_STOP with @ref nrf_drv_twi_xfer_desc_t::type different than @ref NRF_DRV_TWI_XFER_TX - * - @ref NRF_DRV_TWI_FLAG_REPEATED_XFER with @ref nrf_drv_twi_xfer_desc_t::type set to @ref NRF_DRV_TWI_XFER_TXTX - * - * If @ref nrf_drv_twi_xfer_desc_t::type is set to @ref NRF_DRV_TWI_XFER_TX and the @ref NRF_DRV_TWI_FLAG_TX_NO_STOP and @ref NRF_DRV_TWI_FLAG_REPEATED_XFER - * flags are set, two tasks must be used to trigger a transfer: TASKS_RESUME followed by TASKS_STARTTX. If no stop condition is generated, - * TWIM is in SUSPENDED state. Therefore, it must be resumed before the transfer can be started. - * - * @note - * This function should be used only if the instance is configured to work in non-blocking mode. If the function is used in blocking mode, the driver asserts. - * @note If you are using this function with TWI, the only supported flag is @ref NRF_DRV_TWI_FLAG_TX_NO_STOP. All other flags require TWIM. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_xfer_desc Pointer to the transfer descriptor. - * @param[in] flags Transfer options (0 for default settings). - * - * @retval NRF_SUCCESS If the procedure was successful. - * @retval NRF_ERROR_BUSY If the driver is not ready for a new transfer. - * @retval NRF_ERROR_NOT_SUPPORTED If the provided parameters are not supported. - * @retval NRF_ERROR_INTERNAL If an error was detected by hardware. - * @retval NRF_ERROR_INVALID_ADDR If the EasyDMA is used and memory adress in not in RAM - * @retval NRF_ERROR_DRV_TWI_ERR_OVERRUN If the unread data was replaced by new data (TXRX and RX) - * @retval NRF_ERROR_DRV_TWI_ERR_ANACK If NACK received after sending the address. - * @retval NRF_ERROR_DRV_TWI_ERR_DNACK If NACK received after sending a data byte. - */ -__STATIC_INLINE -ret_code_t nrf_drv_twi_xfer(nrf_drv_twi_t const * p_instance, - nrf_drv_twi_xfer_desc_t const * p_xfer_desc, - uint32_t flags); - -/** - * @brief Function for checking the TWI driver state. - * - * @param[in] p_instance TWI instance. - * - * @retval true If the TWI driver is currently busy performing a transfer. - * @retval false If the TWI driver is ready for a new transfer. - */ -__STATIC_INLINE -bool nrf_drv_twi_is_busy(nrf_drv_twi_t const * p_instance); - -/** - * @brief Function for getting the transferred data count. - * - * This function provides valid results only in legacy mode. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @return Data count. - */ -__STATIC_INLINE -uint32_t nrf_drv_twi_data_count_get(nrf_drv_twi_t const * const p_instance); - -/** - * @brief Function for returning the address of a TWI/TWIM start task. - * - * This function should be used if @ref nrf_drv_twi_xfer was called with the flag @ref NRF_DRV_TWI_FLAG_HOLD_XFER. - * In that case, the transfer is not started by the driver, but it must be started externally by PPI. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] xfer_type Transfer type used in the last call of the @ref nrf_drv_twi_xfer function. - * - * @return Start task address (TX or RX) depending on the value of xfer_type. - */ -__STATIC_INLINE -uint32_t nrf_drv_twi_start_task_get(nrf_drv_twi_t const * p_instance, nrf_drv_twi_xfer_type_t xfer_type); - -/** - * @brief Function for returning the address of a STOPPED TWI/TWIM event. - * - * A STOPPED event can be used to detect the end of a transfer if the @ref NRF_DRV_TWI_FLAG_NO_XFER_EVT_HANDLER - * option is used. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @return STOPPED event address. - */ -__STATIC_INLINE -uint32_t nrf_drv_twi_stopped_event_get(nrf_drv_twi_t const * p_instance); - - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -#if defined(TWI_PRESENT) && !defined(TWIM_PRESENT) -#define NRF_DRV_TWI_WITH_TWI -#elif !defined(TWI_PRESENT) && defined(TWIM_PRESENT) -#define NRF_DRV_TWI_WITH_TWIM -#else -#if (NRFX_CHECK(TWI0_ENABLED) && NRFX_CHECK(TWI0_USE_EASY_DMA)) || \ - (NRFX_CHECK(TWI1_ENABLED) && NRFX_CHECK(TWI1_USE_EASY_DMA)) - #define NRF_DRV_TWI_WITH_TWIM -#endif -#if (NRFX_CHECK(TWI0_ENABLED) && !NRFX_CHECK(TWI0_USE_EASY_DMA)) || \ - (NRFX_CHECK(TWI1_ENABLED) && !NRFX_CHECK(TWI1_USE_EASY_DMA)) - #define NRF_DRV_TWI_WITH_TWI -#endif -#endif -#if defined(NRF_DRV_TWI_WITH_TWIM) && defined(NRF_DRV_TWI_WITH_TWI) - #define NRF_DRV_TWI_USE_TWIM (p_instance->use_easy_dma) -#elif defined(NRF_DRV_TWI_WITH_TWIM) - #define NRF_DRV_TWI_USE_TWIM true -#else - #define NRF_DRV_TWI_USE_TWIM false -#endif -#define NRF_DRV_TWI_USE_TWI (!NRF_DRV_TWI_USE_TWIM) - -__STATIC_INLINE -void nrf_drv_twi_uninit(nrf_drv_twi_t const * p_instance) -{ - if (NRF_DRV_TWI_USE_TWIM) - { - nrfx_twim_uninit(&p_instance->u.twim); - } - else if (NRF_DRV_TWI_USE_TWI) - { - nrfx_twi_uninit(&p_instance->u.twi); - } -} - -__STATIC_INLINE -void nrf_drv_twi_enable(nrf_drv_twi_t const * p_instance) -{ - if (NRF_DRV_TWI_USE_TWIM) - { - nrfx_twim_enable(&p_instance->u.twim); - } - else if (NRF_DRV_TWI_USE_TWI) - { - nrfx_twi_enable(&p_instance->u.twi); - } -} - -__STATIC_INLINE -void nrf_drv_twi_disable(nrf_drv_twi_t const * p_instance) -{ - if (NRF_DRV_TWI_USE_TWIM) - { - nrfx_twim_disable(&p_instance->u.twim); - } - else if (NRF_DRV_TWI_USE_TWI) - { - nrfx_twi_disable(&p_instance->u.twi); - } -} - -__STATIC_INLINE -ret_code_t nrf_drv_twi_tx(nrf_drv_twi_t const * p_instance, - uint8_t address, - uint8_t const * p_data, - uint8_t length, - bool no_stop) -{ - ret_code_t result = 0; - if (NRF_DRV_TWI_USE_TWIM) - { - result = nrfx_twim_tx(&p_instance->u.twim, - address, p_data, length, no_stop); - } - else if (NRF_DRV_TWI_USE_TWI) - { - result = nrfx_twi_tx(&p_instance->u.twi, - address, p_data, length, no_stop); - } - return result; -} - -__STATIC_INLINE -ret_code_t nrf_drv_twi_rx(nrf_drv_twi_t const * p_instance, - uint8_t address, - uint8_t * p_data, - uint8_t length) -{ - ret_code_t result = 0; - if (NRF_DRV_TWI_USE_TWIM) - { - result = nrfx_twim_rx(&p_instance->u.twim, - address, p_data, length); - } - else if (NRF_DRV_TWI_USE_TWI) - { - result = nrfx_twi_rx(&p_instance->u.twi, - address, p_data, length); - } - return result; -} - -__STATIC_INLINE -ret_code_t nrf_drv_twi_xfer(nrf_drv_twi_t const * p_instance, - nrf_drv_twi_xfer_desc_t const * p_xfer_desc, - uint32_t flags) -{ - ret_code_t result = 0; - if (NRF_DRV_TWI_USE_TWIM) - { - #ifdef TWIM_PRESENT - nrfx_twim_xfer_desc_t const twim_xfer_desc = - { - .type = (nrfx_twim_xfer_type_t)p_xfer_desc->type, - .address = p_xfer_desc->address, - .primary_length = p_xfer_desc->primary_length, - .secondary_length = p_xfer_desc->secondary_length, - .p_primary_buf = p_xfer_desc->p_primary_buf, - .p_secondary_buf = p_xfer_desc->p_secondary_buf, - }; - result = nrfx_twim_xfer(&p_instance->u.twim, &twim_xfer_desc, flags); - #endif - } - else if (NRF_DRV_TWI_USE_TWI) - { - #ifdef TWI_PRESENT - nrfx_twi_xfer_desc_t const twi_xfer_desc = - { - .type = (nrfx_twi_xfer_type_t)p_xfer_desc->type, - .address = p_xfer_desc->address, - .primary_length = p_xfer_desc->primary_length, - .secondary_length = p_xfer_desc->secondary_length, - .p_primary_buf = p_xfer_desc->p_primary_buf, - .p_secondary_buf = p_xfer_desc->p_secondary_buf, - }; - result = nrfx_twi_xfer(&p_instance->u.twi, &twi_xfer_desc, flags); - #endif - } - return result; -} - -__STATIC_INLINE -bool nrf_drv_twi_is_busy(nrf_drv_twi_t const * p_instance) -{ - bool result = 0; - if (NRF_DRV_TWI_USE_TWIM) - { - result = nrfx_twim_is_busy(&p_instance->u.twim); - } - else if (NRF_DRV_TWI_USE_TWI) - { - result = nrfx_twi_is_busy(&p_instance->u.twi); - } - return result; -} - -__STATIC_INLINE -uint32_t nrf_drv_twi_data_count_get(nrf_drv_twi_t const * const p_instance) -{ - uint32_t result = 0; - if (NRF_DRV_TWI_USE_TWIM) - { - NRFX_ASSERT(false); // not supported - result = 0; - } - else if (NRF_DRV_TWI_USE_TWI) - { - result = nrfx_twi_data_count_get(&p_instance->u.twi); - } - return result; -} - -__STATIC_INLINE -uint32_t nrf_drv_twi_start_task_get(nrf_drv_twi_t const * p_instance, - nrf_drv_twi_xfer_type_t xfer_type) -{ - uint32_t result = 0; - if (NRF_DRV_TWI_USE_TWIM) - { - result = nrfx_twim_start_task_get(&p_instance->u.twim, - (nrfx_twim_xfer_type_t)xfer_type); - } - else if (NRF_DRV_TWI_USE_TWI) - { - NRFX_ASSERT(false); // not supported - result = 0; - } - return result; -} - -__STATIC_INLINE -uint32_t nrf_drv_twi_stopped_event_get(nrf_drv_twi_t const * p_instance) -{ - uint32_t result = 0; - if (NRF_DRV_TWI_USE_TWIM) - { - result = nrfx_twim_stopped_event_get(&p_instance->u.twim); - } - else if (NRF_DRV_TWI_USE_TWI) - { - result = nrfx_twi_stopped_event_get(&p_instance->u.twi); - } - return result; -} - -#endif // SUPPRESS_INLINE_IMPLEMENTATION - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_TWI_H__ diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_twis.h b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_twis.h deleted file mode 100644 index a79b1a6793..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_twis.h +++ /dev/null @@ -1,134 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_DRV_TWIS_H__ -#define NRF_DRV_TWIS_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_drv_twis TWIS driver - legacy layer - * @{ - * @ingroup nrf_twis - * - * @brief Layer providing compatibility with the former API. - */ - -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_twis_t nrf_drv_twis_t; -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_twis_config_t nrf_drv_twis_config_t; -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_twis_evt_t nrf_drv_twis_evt_t; - -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_TWIS_INSTANCE NRFX_TWIS_INSTANCE -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_TWIS_DEFAULT_CONFIG NRFX_TWIS_DEFAULT_CONFIG - -/** @brief Macro for forwarding the new implementation. */ -#define TWIS_EVT_READ_REQ NRFX_TWIS_EVT_READ_REQ -/** @brief Macro for forwarding the new implementation. */ -#define TWIS_EVT_READ_DONE NRFX_TWIS_EVT_READ_DONE -/** @brief Macro for forwarding the new implementation. */ -#define TWIS_EVT_READ_ERROR NRFX_TWIS_EVT_READ_ERROR -/** @brief Macro for forwarding the new implementation. */ -#define TWIS_EVT_WRITE_REQ NRFX_TWIS_EVT_WRITE_REQ -/** @brief Macro for forwarding the new implementation. */ -#define TWIS_EVT_WRITE_DONE NRFX_TWIS_EVT_WRITE_DONE -/** @brief Macro for forwarding the new implementation. */ -#define TWIS_EVT_WRITE_ERROR NRFX_TWIS_EVT_WRITE_ERROR -/** @brief Macro for forwarding the new implementation. */ -#define TWIS_EVT_GENERAL_ERROR NRFX_TWIS_EVT_GENERAL_ERROR -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_twis_evt_type_t nrfx_twis_evt_type_t -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_TWIS_ERROR_OVERFLOW NRFX_TWIS_ERROR_OVERFLOW -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_TWIS_ERROR_DATA_NACK NRFX_TWIS_ERROR_DATA_NACK -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_TWIS_ERROR_OVERREAD NRFX_TWIS_ERROR_OVERREAD -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_TWIS_ERROR_UNEXPECTED_EVENT NRFX_TWIS_ERROR_UNEXPECTED_EVENT -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_twis_error_t nrfx_twis_error_t -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_twis_event_handler_t nrfx_twis_event_handler_t - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_twis_init nrfx_twis_init -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_twis_uninit nrfx_twis_uninit -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_twis_enable nrfx_twis_enable -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_twis_disable nrfx_twis_disable -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_twis_error_get_and_clear nrfx_twis_error_get_and_clear -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_twis_tx_prepare nrfx_twis_tx_prepare -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_twis_tx_amount nrfx_twis_tx_amount -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_twis_rx_prepare nrfx_twis_rx_prepare -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_twis_rx_amount nrfx_twis_rx_amount -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_twis_is_busy nrfx_twis_is_busy -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_twis_is_waiting_tx_buff nrfx_twis_is_waiting_tx_buff -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_twis_is_waiting_rx_buff nrfx_twis_is_waiting_rx_buff -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_twis_is_pending_tx nrfx_twis_is_pending_tx -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_twis_is_pending_rx nrfx_twis_is_pending_rx - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_TWIS_H__ diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_uart.c b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_uart.c deleted file mode 100644 index 02d33280b3..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_uart.c +++ /dev/null @@ -1,135 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include "nrf_drv_uart.h" - -#ifdef UARTE_PRESENT -#define INSTANCE_COUNT UARTE_COUNT -#else -#define INSTANCE_COUNT UART_COUNT -#endif - -static nrf_uart_event_handler_t m_handlers[INSTANCE_COUNT]; -static void * m_contexts[INSTANCE_COUNT]; - -#if defined(UARTE_PRESENT) && defined(UART_PRESENT) -uint8_t nrf_drv_uart_use_easy_dma[INSTANCE_COUNT]; -#endif - -#if defined(NRF_DRV_UART_WITH_UARTE) -static void uarte_evt_handler(nrfx_uarte_event_t const * p_event, - void * p_context) -{ - uint32_t inst_idx = (uint32_t)p_context; - nrf_drv_uart_event_t event = - { - .type = (nrf_drv_uart_evt_type_t)p_event->type, - .data = - { - .error = - { - .rxtx = - { - .p_data = p_event->data.error.rxtx.p_data, - .bytes = p_event->data.error.rxtx.bytes, - }, - .error_mask = p_event->data.error.error_mask, - } - } - }; - m_handlers[inst_idx](&event, m_contexts[inst_idx]); -} -#endif // defined(NRF_DRV_UART_WITH_UARTE) - -#if defined(NRF_DRV_UART_WITH_UART) -static void uart_evt_handler(nrfx_uart_event_t const * p_event, - void * p_context) -{ - uint32_t inst_idx = (uint32_t)p_context; - nrf_drv_uart_event_t event = - { - .type = (nrf_drv_uart_evt_type_t)p_event->type, - .data = - { - .error = - { - .rxtx = - { - .p_data = p_event->data.error.rxtx.p_data, - .bytes = p_event->data.error.rxtx.bytes, - }, - .error_mask = p_event->data.error.error_mask, - } - } - }; - m_handlers[inst_idx](&event, m_contexts[inst_idx]); -} -#endif // defined(NRF_DRV_UART_WITH_UART) - -ret_code_t nrf_drv_uart_init(nrf_drv_uart_t const * p_instance, - nrf_drv_uart_config_t const * p_config, - nrf_uart_event_handler_t event_handler) -{ - uint32_t inst_idx = p_instance->inst_idx; - m_handlers[inst_idx] = event_handler; - m_contexts[inst_idx] = p_config->p_context; - -#if defined(NRF_DRV_UART_WITH_UARTE) && defined(NRF_DRV_UART_WITH_UART) - nrf_drv_uart_use_easy_dma[inst_idx] = p_config->use_easy_dma; -#endif - - nrf_drv_uart_config_t config = *p_config; - config.p_context = (void *)inst_idx; - - ret_code_t result = 0; - if (NRF_DRV_UART_USE_UARTE) - { - result = nrfx_uarte_init(&p_instance->uarte, - (nrfx_uarte_config_t const *)&config, - event_handler ? uarte_evt_handler : NULL); - } - else if (NRF_DRV_UART_USE_UART) - { - result = nrfx_uart_init(&p_instance->uart, - (nrfx_uart_config_t const *)&config, - event_handler ? uart_evt_handler : NULL); - } - return result; -} diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_uart.h b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_uart.h deleted file mode 100644 index 7ae028aaad..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_uart.h +++ /dev/null @@ -1,654 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_DRV_UART_H__ -#define NRF_DRV_UART_H__ - -#include - -#if defined(UARTE_PRESENT) && NRFX_CHECK(NRFX_UARTE_ENABLED) - #define NRF_DRV_UART_WITH_UARTE -#endif -#if defined(UART_PRESENT) && NRFX_CHECK(NRFX_UART_ENABLED) - #define NRF_DRV_UART_WITH_UART -#endif - -#if defined(NRF_DRV_UART_WITH_UARTE) - #include - #define NRF_DRV_UART_CREATE_UARTE(id) \ - .uarte = NRFX_UARTE_INSTANCE(id), -#else - // Compilers (at least the smart ones) will remove the UARTE related code - // (blocks starting with "if (NRF_DRV_UART_USE_UARTE)") when it is not used, - // but to perform the compilation they need the following definitions. - #define nrfx_uarte_init(...) 0 - #define nrfx_uarte_uninit(...) - #define nrfx_uarte_task_address_get(...) 0 - #define nrfx_uarte_event_address_get(...) 0 - #define nrfx_uarte_tx(...) 0 - #define nrfx_uarte_tx_in_progress(...) 0 - #define nrfx_uarte_tx_abort(...) - #define nrfx_uarte_rx(...) 0 - #define nrfx_uarte_rx_ready(...) 0 - #define nrfx_uarte_rx_abort(...) - #define nrfx_uarte_errorsrc_get(...) 0 - #define NRF_DRV_UART_CREATE_UARTE(id) -#endif - -#if defined(NRF_DRV_UART_WITH_UART) - #include - #define NRF_DRV_UART_CREATE_UART(id) \ - .uart = NRFX_UART_INSTANCE(id), -#else - // Compilers (at least the smart ones) will remove the UART related code - // (blocks starting with "if (NRF_DRV_UART_USE_UART)") when it is not used, - // but to perform the compilation they need the following definitions. - #define nrfx_uart_init(...) 0 - #define nrfx_uart_uninit(...) - #define nrfx_uart_task_address_get(...) 0 - #define nrfx_uart_event_address_get(...) 0 - #define nrfx_uart_tx(...) 0 - #define nrfx_uart_tx_in_progress(...) 0 - #define nrfx_uart_tx_abort(...) - #define nrfx_uart_rx(...) 0 - #define nrfx_uart_rx_enable(...) - #define nrfx_uart_rx_disable(...) - #define nrfx_uart_rx_ready(...) 0 - #define nrfx_uart_rx_abort(...) - #define nrfx_uart_errorsrc_get(...) 0 - #define NRF_DRV_UART_CREATE_UART(id) - - // This part is for old modules that use directly UART HAL definitions - // (to make them compilable for chips that have only UARTE). - #define NRF_UART_BAUDRATE_1200 NRF_UARTE_BAUDRATE_1200 - #define NRF_UART_BAUDRATE_2400 NRF_UARTE_BAUDRATE_2400 - #define NRF_UART_BAUDRATE_4800 NRF_UARTE_BAUDRATE_4800 - #define NRF_UART_BAUDRATE_9600 NRF_UARTE_BAUDRATE_9600 - #define NRF_UART_BAUDRATE_14400 NRF_UARTE_BAUDRATE_14400 - #define NRF_UART_BAUDRATE_19200 NRF_UARTE_BAUDRATE_19200 - #define NRF_UART_BAUDRATE_28800 NRF_UARTE_BAUDRATE_28800 - #define NRF_UART_BAUDRATE_38400 NRF_UARTE_BAUDRATE_38400 - #define NRF_UART_BAUDRATE_57600 NRF_UARTE_BAUDRATE_57600 - #define NRF_UART_BAUDRATE_76800 NRF_UARTE_BAUDRATE_76800 - #define NRF_UART_BAUDRATE_115200 NRF_UARTE_BAUDRATE_115200 - #define NRF_UART_BAUDRATE_230400 NRF_UARTE_BAUDRATE_230400 - #define NRF_UART_BAUDRATE_250000 NRF_UARTE_BAUDRATE_250000 - #define NRF_UART_BAUDRATE_460800 NRF_UARTE_BAUDRATE_460800 - #define NRF_UART_BAUDRATE_921600 NRF_UARTE_BAUDRATE_921600 - #define NRF_UART_BAUDRATE_1000000 NRF_UARTE_BAUDRATE_1000000 - typedef nrf_uarte_baudrate_t nrf_uart_baudrate_t; - #define NRF_UART_ERROR_OVERRUN_MASK NRF_UARTE_ERROR_OVERRUN_MASK - #define NRF_UART_ERROR_PARITY_MASK NRF_UARTE_ERROR_PARITY_MASK - #define NRF_UART_ERROR_FRAMING_MASK NRF_UARTE_ERROR_PARITY_MASK - #define NRF_UART_ERROR_BREAK_MASK NRF_UARTE_ERROR_BREAK_MASK - typedef nrf_uarte_error_mask_t nrf_uart_error_mask_t; - #define NRF_UART_HWFC_DISABLED NRF_UARTE_HWFC_DISABLED - #define NRF_UART_HWFC_ENABLED NRF_UARTE_HWFC_ENABLED - typedef nrf_uarte_hwfc_t nrf_uart_hwfc_t; - #define NRF_UART_PARITY_EXCLUDED NRF_UARTE_PARITY_EXCLUDED - #define NRF_UART_PARITY_INCLUDED NRF_UARTE_PARITY_INCLUDED - typedef nrf_uarte_parity_t nrf_uart_parity_t; - typedef nrf_uarte_task_t nrf_uart_task_t; - typedef nrf_uarte_event_t nrf_uart_event_t; - #define NRF_UART_PSEL_DISCONNECTED NRF_UARTE_PSEL_DISCONNECTED - #define nrf_uart_event_clear(...) -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_drv_uart UART driver - legacy layer - * @{ - * @ingroup nrf_uart - * @brief Layer providing compatibility with the former API. - */ - -/** - * @brief Structure for the UART driver instance. - */ -typedef struct -{ - uint8_t inst_idx; -#if defined(NRF_DRV_UART_WITH_UARTE) - nrfx_uarte_t uarte; -#endif -#if defined(NRF_DRV_UART_WITH_UART) - nrfx_uart_t uart; -#endif -} nrf_drv_uart_t; - -/** - * @brief Macro for creating an UART driver instance. - */ -#define NRF_DRV_UART_INSTANCE(id) \ -{ \ - .inst_idx = id, \ - NRF_DRV_UART_CREATE_UARTE(id) \ - NRF_DRV_UART_CREATE_UART(id) \ -} - -/** - * @brief Types of UART driver events. - */ -typedef enum -{ - NRF_DRV_UART_EVT_TX_DONE, ///< Requested TX transfer completed. - NRF_DRV_UART_EVT_RX_DONE, ///< Requested RX transfer completed. - NRF_DRV_UART_EVT_ERROR, ///< Error reported by UART peripheral. -} nrf_drv_uart_evt_type_t; - -/**@brief Structure for UART configuration. */ -typedef struct -{ - uint32_t pseltxd; ///< TXD pin number. - uint32_t pselrxd; ///< RXD pin number. - uint32_t pselcts; ///< CTS pin number. - uint32_t pselrts; ///< RTS pin number. - void * p_context; ///< Context passed to interrupt handler. - nrf_uart_hwfc_t hwfc; ///< Flow control configuration. - nrf_uart_parity_t parity; ///< Parity configuration. - nrf_uart_baudrate_t baudrate; ///< Baudrate. - uint8_t interrupt_priority; ///< Interrupt priority. -#if defined(NRF_DRV_UART_WITH_UARTE) && defined(NRF_DRV_UART_WITH_UART) - bool use_easy_dma; -#endif -} nrf_drv_uart_config_t; - -#if defined(NRF_DRV_UART_WITH_UARTE) && defined(NRF_DRV_UART_WITH_UART) -extern uint8_t nrf_drv_uart_use_easy_dma[]; -#define NRF_DRV_UART_DEFAULT_CONFIG_USE_EASY_DMA .use_easy_dma = true, -#else -#define NRF_DRV_UART_DEFAULT_CONFIG_USE_EASY_DMA -#endif - -/**@brief UART default configuration. */ -#define NRF_DRV_UART_DEFAULT_CONFIG \ -{ \ - .pseltxd = NRF_UART_PSEL_DISCONNECTED, \ - .pselrxd = NRF_UART_PSEL_DISCONNECTED, \ - .pselcts = NRF_UART_PSEL_DISCONNECTED, \ - .pselrts = NRF_UART_PSEL_DISCONNECTED, \ - .p_context = NULL, \ - .hwfc = (nrf_uart_hwfc_t)UART_DEFAULT_CONFIG_HWFC, \ - .parity = (nrf_uart_parity_t)UART_DEFAULT_CONFIG_PARITY, \ - .baudrate = (nrf_uart_baudrate_t)UART_DEFAULT_CONFIG_BAUDRATE, \ - .interrupt_priority = UART_DEFAULT_CONFIG_IRQ_PRIORITY, \ - NRF_DRV_UART_DEFAULT_CONFIG_USE_EASY_DMA \ -} - -/**@brief Structure for UART transfer completion event. */ -typedef struct -{ - uint8_t * p_data; ///< Pointer to memory used for transfer. - uint8_t bytes; ///< Number of bytes transfered. -} nrf_drv_uart_xfer_evt_t; - -/**@brief Structure for UART error event. */ -typedef struct -{ - nrf_drv_uart_xfer_evt_t rxtx; ///< Transfer details includes number of bytes transfered. - uint32_t error_mask;///< Mask of error flags that generated the event. -} nrf_drv_uart_error_evt_t; - -/**@brief Structure for UART event. */ -typedef struct -{ - nrf_drv_uart_evt_type_t type; ///< Event type. - union - { - nrf_drv_uart_xfer_evt_t rxtx; ///< Data provided for transfer completion events. - nrf_drv_uart_error_evt_t error;///< Data provided for error event. - } data; -} nrf_drv_uart_event_t; - -/** - * @brief UART interrupt event handler. - * - * @param[in] p_event Pointer to event structure. Event is allocated on the stack so it is available - * only within the context of the event handler. - * @param[in] p_context Context passed to interrupt handler, set on initialization. - */ -typedef void (*nrf_uart_event_handler_t)(nrf_drv_uart_event_t * p_event, void * p_context); - -/** - * @brief Function for initializing the UART driver. - * - * This function configures and enables UART. After this function GPIO pins are controlled by UART. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_config Initial configuration. - * @param[in] event_handler Event handler provided by the user. If not provided driver works in - * blocking mode. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_INVALID_STATE If driver is already initialized. - */ -ret_code_t nrf_drv_uart_init(nrf_drv_uart_t const * p_instance, - nrf_drv_uart_config_t const * p_config, - nrf_uart_event_handler_t event_handler); - -/** - * @brief Function for uninitializing the UART driver. - * @param[in] p_instance Pointer to the driver instance structure. - */ -__STATIC_INLINE -void nrf_drv_uart_uninit(nrf_drv_uart_t const * p_instance); - -/** - * @brief Function for getting the address of a specific UART task. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] task Task. - * - * @return Task address. - */ -__STATIC_INLINE -uint32_t nrf_drv_uart_task_address_get(nrf_drv_uart_t const * p_instance, - nrf_uart_task_t task); - -/** - * @brief Function for getting the address of a specific UART event. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] event Event. - * - * @return Event address. - */ -__STATIC_INLINE -uint32_t nrf_drv_uart_event_address_get(nrf_drv_uart_t const * p_instance, - nrf_uart_event_t event); - -/** - * @brief Function for sending data over UART. - * - * If an event handler was provided in nrf_drv_uart_init() call, this function - * returns immediately and the handler is called when the transfer is done. - * Otherwise, the transfer is performed in blocking mode, i.e. this function - * returns when the transfer is finished. Blocking mode is not using interrupt so - * there is no context switching inside the function. - * - * @note Peripherals using EasyDMA (i.e. UARTE) require that the transfer buffers - * are placed in the Data RAM region. If they are not and UARTE instance is - * used, this function will fail with error code NRFX_ERROR_INVALID_ADDR. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_data Pointer to data. - * @param[in] length Number of bytes to send. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_BUSY If driver is already transferring. - * @retval NRFX_ERROR_FORBIDDEN If the transfer was aborted from a different context - * (blocking mode only, also see @ref nrf_drv_uart_rx_disable). - * @retval NRFX_ERROR_INVALID_ADDR If p_data does not point to RAM buffer (UARTE only). - */ -__STATIC_INLINE -ret_code_t nrf_drv_uart_tx(nrf_drv_uart_t const * p_instance, - uint8_t const * const p_data, - uint8_t length); - -/** - * @brief Function for checking if UART is currently transmitting. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @retval true If UART is transmitting. - * @retval false If UART is not transmitting. - */ -__STATIC_INLINE -bool nrf_drv_uart_tx_in_progress(nrf_drv_uart_t const * p_instance); - -/** - * @brief Function for aborting any ongoing transmission. - * @note @ref NRF_DRV_UART_EVT_TX_DONE event will be generated in non-blocking mode. Event will - * contain number of bytes sent until abort was called. If Easy DMA is not used event will be - * called from the function context. If Easy DMA is used it will be called from UART interrupt - * context. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -__STATIC_INLINE -void nrf_drv_uart_tx_abort(nrf_drv_uart_t const * p_instance); - -/** - * @brief Function for receiving data over UART. - * - * If an event handler was provided in the nrf_drv_uart_init() call, this function - * returns immediately and the handler is called when the transfer is done. - * Otherwise, the transfer is performed in blocking mode, i.e. this function - * returns when the transfer is finished. Blocking mode is not using interrupt so - * there is no context switching inside the function. - * The receive buffer pointer is double buffered in non-blocking mode. The secondary - * buffer can be set immediately after starting the transfer and will be filled - * when the primary buffer is full. The double buffering feature allows - * receiving data continuously. - * - * @note Peripherals using EasyDMA (i.e. UARTE) require that the transfer buffers - * are placed in the Data RAM region. If they are not and UARTE driver instance - * is used, this function will fail with error code NRFX_ERROR_INVALID_ADDR. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_data Pointer to data. - * @param[in] length Number of bytes to receive. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_BUSY If the driver is already receiving - * (and the secondary buffer has already been set - * in non-blocking mode). - * @retval NRFX_ERROR_FORBIDDEN If the transfer was aborted from a different context - * (blocking mode only, also see @ref nrf_drv_uart_rx_disable). - * @retval NRFX_ERROR_INTERNAL If UART peripheral reported an error. - * @retval NRFX_ERROR_INVALID_ADDR If p_data does not point to RAM buffer (UARTE only). - */ -__STATIC_INLINE -ret_code_t nrf_drv_uart_rx(nrf_drv_uart_t const * p_instance, - uint8_t * p_data, - uint8_t length); - - - -/** - * @brief Function for testing the receiver state in blocking mode. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @retval true If the receiver has at least one byte of data to get. - * @retval false If the receiver is empty. - */ -__STATIC_INLINE -bool nrf_drv_uart_rx_ready(nrf_drv_uart_t const * p_instance); - -/** - * @brief Function for enabling the receiver. - * - * UART has a 6-byte-long RX FIFO and it is used to store incoming data. If a user does not call the - * UART receive function before the FIFO is filled, an overrun error will appear. Enabling the receiver - * without specifying an RX buffer is supported only in UART mode (without Easy DMA). The receiver must be - * explicitly closed by the user @sa nrf_drv_uart_rx_disable. This function asserts if the mode is wrong. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -__STATIC_INLINE -void nrf_drv_uart_rx_enable(nrf_drv_uart_t const * p_instance); - -/** - * @brief Function for disabling the receiver. - * - * This function must be called to close the receiver after it has been explicitly enabled by - * @sa nrf_drv_uart_rx_enable. The feature is supported only in UART mode (without Easy DMA). The function - * asserts if mode is wrong. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -__STATIC_INLINE -void nrf_drv_uart_rx_disable(nrf_drv_uart_t const * p_instance); - -/** - * @brief Function for aborting any ongoing reception. - * @note @ref NRF_DRV_UART_EVT_RX_DONE event will be generated in non-blocking mode. The event will - * contain the number of bytes received until abort was called. The event is called from UART interrupt - * context. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -__STATIC_INLINE -void nrf_drv_uart_rx_abort(nrf_drv_uart_t const * p_instance); - -/** - * @brief Function for reading error source mask. Mask contains values from @ref nrf_uart_error_mask_t. - * @note Function should be used in blocking mode only. In case of non-blocking mode, an error event is - * generated. Function clears error sources after reading. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @retval Mask of reported errors. - */ -__STATIC_INLINE -uint32_t nrf_drv_uart_errorsrc_get(nrf_drv_uart_t const * p_instance); - - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -#if defined(NRF_DRV_UART_WITH_UARTE) && defined(NRF_DRV_UART_WITH_UART) - #define NRF_DRV_UART_USE_UARTE (nrf_drv_uart_use_easy_dma[p_instance->inst_idx]) -#elif defined(NRF_DRV_UART_WITH_UARTE) - #define NRF_DRV_UART_USE_UARTE true -#else - #define NRF_DRV_UART_USE_UARTE false -#endif -#define NRF_DRV_UART_USE_UART (!NRF_DRV_UART_USE_UARTE) - -__STATIC_INLINE -void nrf_drv_uart_uninit(nrf_drv_uart_t const * p_instance) -{ - if (NRF_DRV_UART_USE_UARTE) - { - nrfx_uarte_uninit(&p_instance->uarte); - } - else if (NRF_DRV_UART_USE_UART) - { - nrfx_uart_uninit(&p_instance->uart); - } -} - -__STATIC_INLINE -uint32_t nrf_drv_uart_task_address_get(nrf_drv_uart_t const * p_instance, - nrf_uart_task_t task) -{ - uint32_t result = 0; - if (NRF_DRV_UART_USE_UARTE) - { - result = nrfx_uarte_task_address_get(&p_instance->uarte, - (nrf_uarte_task_t)task); - } - else if (NRF_DRV_UART_USE_UART) - { - result = nrfx_uart_task_address_get(&p_instance->uart, task); - } - return result; -} - -__STATIC_INLINE -uint32_t nrf_drv_uart_event_address_get(nrf_drv_uart_t const * p_instance, - nrf_uart_event_t event) -{ - uint32_t result = 0; - if (NRF_DRV_UART_USE_UARTE) - { - result = nrfx_uarte_event_address_get(&p_instance->uarte, - (nrf_uarte_event_t)event); - } - else if (NRF_DRV_UART_USE_UART) - { - result = nrfx_uart_event_address_get(&p_instance->uart, event); - } - return result; -} - -__STATIC_INLINE -ret_code_t nrf_drv_uart_tx(nrf_drv_uart_t const * p_instance, - uint8_t const * p_data, - uint8_t length) -{ - uint32_t result = 0; - if (NRF_DRV_UART_USE_UARTE) - { - result = nrfx_uarte_tx(&p_instance->uarte, - p_data, - length); - } - else if (NRF_DRV_UART_USE_UART) - { - result = nrfx_uart_tx(&p_instance->uart, - p_data, - length); - } - return result; -} - -__STATIC_INLINE -bool nrf_drv_uart_tx_in_progress(nrf_drv_uart_t const * p_instance) -{ - bool result = 0; - if (NRF_DRV_UART_USE_UARTE) - { - result = nrfx_uarte_tx_in_progress(&p_instance->uarte); - } - else if (NRF_DRV_UART_USE_UART) - { - result = nrfx_uart_tx_in_progress(&p_instance->uart); - } - return result; -} - -__STATIC_INLINE -void nrf_drv_uart_tx_abort(nrf_drv_uart_t const * p_instance) -{ - if (NRF_DRV_UART_USE_UARTE) - { - nrfx_uarte_tx_abort(&p_instance->uarte); - } - else if (NRF_DRV_UART_USE_UART) - { - nrfx_uart_tx_abort(&p_instance->uart); - } -} - -__STATIC_INLINE -ret_code_t nrf_drv_uart_rx(nrf_drv_uart_t const * p_instance, - uint8_t * p_data, - uint8_t length) -{ - uint32_t result = 0; - if (NRF_DRV_UART_USE_UARTE) - { - result = nrfx_uarte_rx(&p_instance->uarte, - p_data, - length); - } - else if (NRF_DRV_UART_USE_UART) - { - result = nrfx_uart_rx(&p_instance->uart, - p_data, - length); - } - return result; -} - -__STATIC_INLINE -bool nrf_drv_uart_rx_ready(nrf_drv_uart_t const * p_instance) -{ - bool result = 0; - if (NRF_DRV_UART_USE_UARTE) - { - result = nrfx_uarte_rx_ready(&p_instance->uarte); - } - else if (NRF_DRV_UART_USE_UART) - { - result = nrfx_uart_rx_ready(&p_instance->uart); - } - return result; -} - -__STATIC_INLINE -void nrf_drv_uart_rx_enable(nrf_drv_uart_t const * p_instance) -{ - if (NRF_DRV_UART_USE_UARTE) - { - NRFX_ASSERT(false); // not supported - } - else if (NRF_DRV_UART_USE_UART) - { - nrfx_uart_rx_enable(&p_instance->uart); - } -} - -__STATIC_INLINE -void nrf_drv_uart_rx_disable(nrf_drv_uart_t const * p_instance) -{ - if (NRF_DRV_UART_USE_UARTE) - { - NRFX_ASSERT(false); // not supported - } - else if (NRF_DRV_UART_USE_UART) - { - nrfx_uart_rx_disable(&p_instance->uart); - } -} - -__STATIC_INLINE -void nrf_drv_uart_rx_abort(nrf_drv_uart_t const * p_instance) -{ - if (NRF_DRV_UART_USE_UARTE) - { - nrfx_uarte_rx_abort(&p_instance->uarte); - } - else if (NRF_DRV_UART_USE_UART) - { - nrfx_uart_rx_abort(&p_instance->uart); - } -} - -__STATIC_INLINE -uint32_t nrf_drv_uart_errorsrc_get(nrf_drv_uart_t const * p_instance) -{ - uint32_t result = 0; - if (NRF_DRV_UART_USE_UARTE) - { - result = nrfx_uarte_errorsrc_get(&p_instance->uarte); - } - else if (NRF_DRV_UART_USE_UART) - { - nrf_uart_event_clear(p_instance->uart.p_reg, NRF_UART_EVENT_ERROR); - result = nrfx_uart_errorsrc_get(&p_instance->uart); - } - return result; -} - -#endif // SUPPRESS_INLINE_IMPLEMENTATION - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_UART_H__ diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_wdt.h b/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_wdt.h deleted file mode 100644 index 6681486051..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/legacy/nrf_drv_wdt.h +++ /dev/null @@ -1,111 +0,0 @@ -/** - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_DRV_WDT_H__ -#define NRF_DRV_WDT_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_drv_wdt WDT driver - legacy layer - * @{ - * @ingroup nrf_wdt - * - * @brief A layer providing compatibility with former API. - */ - -/** @brief Type definition for forwarding the new implementation. */ -typedef nrfx_wdt_config_t nrf_drv_wdt_config_t; - -/** @brief Macro for forwarding the new implementation. */ -#define NRF_DRV_WDT_DEAFULT_CONFIG NRFX_WDT_DEAFULT_CONFIG - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_wdt_event_handler_t nrfx_wdt_event_handler_t -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_wdt_channel_id nrfx_wdt_channel_id - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_wdt_channel_alloc nrfx_wdt_channel_alloc -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_wdt_enable nrfx_wdt_enable -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_wdt_feed nrfx_wdt_feed -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_wdt_channel_feed nrfx_wdt_channel_feed - -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_wdt_ppi_task_addr nrfx_wdt_ppi_task_addr -/** @brief Macro for forwarding the new implementation. */ -#define nrf_drv_wdt_ppi_event_addr nrfx_wdt_ppi_event_addr - -/** - * @brief This function initializes watchdog. - * - * @param[in] p_config Pointer to the structure with initial configuration. Default - * configuration used if NULL. - * @param[in] wdt_event_handler Specifies event handler provided by user. - * - * @note Function asserts if wdt_event_handler is NULL. - * - * @return NRF_SUCCESS on success, otherwise an error code. - */ -__STATIC_INLINE ret_code_t nrf_drv_wdt_init(nrf_drv_wdt_config_t const * p_config, - nrf_wdt_event_handler_t wdt_event_handler) -{ - if (p_config == NULL) - { - static const nrfx_wdt_config_t default_config = NRFX_WDT_DEAFULT_CONFIG; - p_config = &default_config; - } - return nrfx_wdt_init(p_config, wdt_event_handler); -} - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_WDT_H__ diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/nrfx_config.h b/bsp/boards/nrf52840/sdk/integration/nrfx/nrfx_config.h deleted file mode 100644 index b389828c39..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/nrfx_config.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_CONFIG_H__ -#define NRFX_CONFIG_H__ - -// TODO - temporary redirection -#include - -#endif // NRFX_CONFIG_H__ diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/nrfx_glue.h b/bsp/boards/nrf52840/sdk/integration/nrfx/nrfx_glue.h deleted file mode 100644 index 7e724e0938..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/nrfx_glue.h +++ /dev/null @@ -1,268 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_GLUE_H__ -#define NRFX_GLUE_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_glue nrfx_glue.h - * @{ - * @ingroup nrfx - * - * @brief This file contains macros that should be implemented according to - * the needs of the host environment into which @em nrfx is integrated. - */ - -#include - -#include - -//------------------------------------------------------------------------------ - -#include -/** - * @brief Macro for placing a runtime assertion. - * - * @param expression Expression to evaluate. - */ -#define NRFX_ASSERT(expression) ASSERT(expression) - -#include -/** - * @brief Macro for placing a compile time assertion. - * - * @param expression Expression to evaluate. - */ -#define NRFX_STATIC_ASSERT(expression) STATIC_ASSERT(expression) - -//------------------------------------------------------------------------------ - -#ifdef NRF51 -#ifdef SOFTDEVICE_PRESENT -#define INTERRUPT_PRIORITY_IS_VALID(pri) (((pri) == 1) || ((pri) == 3)) -#else -#define INTERRUPT_PRIORITY_IS_VALID(pri) ((pri) < 4) -#endif //SOFTDEVICE_PRESENT -#else -#ifdef SOFTDEVICE_PRESENT -#define INTERRUPT_PRIORITY_IS_VALID(pri) ((((pri) > 1) && ((pri) < 4)) || \ - (((pri) > 4) && ((pri) < 8))) -#else -#define INTERRUPT_PRIORITY_IS_VALID(pri) ((pri) < 8) -#endif //SOFTDEVICE_PRESENT -#endif //NRF52 - -/** - * @brief Macro for setting the priority of a specific IRQ. - * - * @param irq_number IRQ number. - * @param priority Priority to set. - */ -#define NRFX_IRQ_PRIORITY_SET(irq_number, priority) \ - _NRFX_IRQ_PRIORITY_SET(irq_number, priority) -static inline void _NRFX_IRQ_PRIORITY_SET(IRQn_Type irq_number, - uint8_t priority) -{ - ASSERT(INTERRUPT_PRIORITY_IS_VALID(priority)); - NVIC_SetPriority(irq_number, priority); -} - -/** - * @brief Macro for enabling a specific IRQ. - * - * @param irq_number IRQ number. - */ -#define NRFX_IRQ_ENABLE(irq_number) _NRFX_IRQ_ENABLE(irq_number) -static inline void _NRFX_IRQ_ENABLE(IRQn_Type irq_number) -{ - NVIC_ClearPendingIRQ(irq_number); - NVIC_EnableIRQ(irq_number); -} - -/** - * @brief Macro for checking if a specific IRQ is enabled. - * - * @param irq_number IRQ number. - * - * @retval true If the IRQ is enabled. - * @retval false Otherwise. - */ -#define NRFX_IRQ_IS_ENABLED(irq_number) _NRFX_IRQ_IS_ENABLED(irq_number) -static inline bool _NRFX_IRQ_IS_ENABLED(IRQn_Type irq_number) -{ - return 0 != (NVIC->ISER[irq_number / 32] & (1UL << (irq_number % 32))); -} - -/** - * @brief Macro for disabling a specific IRQ. - * - * @param irq_number IRQ number. - */ -#define NRFX_IRQ_DISABLE(irq_number) _NRFX_IRQ_DISABLE(irq_number) -static inline void _NRFX_IRQ_DISABLE(IRQn_Type irq_number) -{ - NVIC_DisableIRQ(irq_number); -} - -/** - * @brief Macro for setting a specific IRQ as pending. - * - * @param irq_number IRQ number. - */ -#define NRFX_IRQ_PENDING_SET(irq_number) _NRFX_IRQ_PENDING_SET(irq_number) -static inline void _NRFX_IRQ_PENDING_SET(IRQn_Type irq_number) -{ - NVIC_SetPendingIRQ(irq_number); -} - -/** - * @brief Macro for clearing the pending status of a specific IRQ. - * - * @param irq_number IRQ number. - */ -#define NRFX_IRQ_PENDING_CLEAR(irq_number) _NRFX_IRQ_PENDING_CLEAR(irq_number) -static inline void _NRFX_IRQ_PENDING_CLEAR(IRQn_Type irq_number) -{ - NVIC_ClearPendingIRQ(irq_number); -} - -/** - * @brief Macro for checking the pending status of a specific IRQ. - * - * @retval true If the IRQ is pending. - * @retval false Otherwise. - */ -#define NRFX_IRQ_IS_PENDING(irq_number) _NRFX_IRQ_IS_PENDING(irq_number) -static inline bool _NRFX_IRQ_IS_PENDING(IRQn_Type irq_number) -{ - return (NVIC_GetPendingIRQ(irq_number) == 1); -} - -#include -#include -/** - * @brief Macro for entering into a critical section. - */ -#define NRFX_CRITICAL_SECTION_ENTER() CRITICAL_REGION_ENTER() - -/** - * @brief Macro for exiting from a critical section. - */ -#define NRFX_CRITICAL_SECTION_EXIT() CRITICAL_REGION_EXIT() - -//------------------------------------------------------------------------------ - -/** - * @brief When set to a non-zero value, this macro specifies that - * @ref nrfx_coredep_delay_us uses a precise DWT-based solution. - * A compilation error is generated if the DWT unit is not present - * in the SoC used. - */ -#define NRFX_DELAY_DWT_BASED 0 - -#include - -#define NRFX_DELAY_US(us_time) nrfx_coredep_delay_us(us_time) - -//------------------------------------------------------------------------------ - -#include -/** - * @brief When set to a non-zero value, this macro specifies that the - * @ref nrfx_error_codes and the @ref ret_code_t type itself are defined - * in a customized way and the default definitions from @c - * should not be used. - */ -#define NRFX_CUSTOM_ERROR_CODES 1 - -typedef ret_code_t nrfx_err_t; - -#define NRFX_SUCCESS NRF_SUCCESS -#define NRFX_ERROR_INTERNAL NRF_ERROR_INTERNAL -#define NRFX_ERROR_NO_MEM NRF_ERROR_NO_MEM -#define NRFX_ERROR_NOT_SUPPORTED NRF_ERROR_NOT_SUPPORTED -#define NRFX_ERROR_INVALID_PARAM NRF_ERROR_INVALID_PARAM -#define NRFX_ERROR_INVALID_STATE NRF_ERROR_INVALID_STATE -#define NRFX_ERROR_INVALID_LENGTH NRF_ERROR_INVALID_LENGTH -#define NRFX_ERROR_TIMEOUT NRF_ERROR_TIMEOUT -#define NRFX_ERROR_FORBIDDEN NRF_ERROR_FORBIDDEN -#define NRFX_ERROR_NULL NRF_ERROR_NULL -#define NRFX_ERROR_INVALID_ADDR NRF_ERROR_INVALID_ADDR -#define NRFX_ERROR_BUSY NRF_ERROR_BUSY -#define NRFX_ERROR_ALREADY_INITIALIZED NRF_ERROR_MODULE_ALREADY_INITIALIZED - -#define NRFX_ERROR_DRV_TWI_ERR_OVERRUN NRF_ERROR_DRV_TWI_ERR_OVERRUN -#define NRFX_ERROR_DRV_TWI_ERR_ANACK NRF_ERROR_DRV_TWI_ERR_ANACK -#define NRFX_ERROR_DRV_TWI_ERR_DNACK NRF_ERROR_DRV_TWI_ERR_DNACK - -//------------------------------------------------------------------------------ - -#include -/** - * @brief Bitmask defining PPI channels reserved to be used outside of nrfx. - */ -#define NRFX_PPI_CHANNELS_USED NRF_PPI_CHANNELS_USED - -/** - * @brief Bitmask defining PPI groups reserved to be used outside of nrfx. - */ -#define NRFX_PPI_GROUPS_USED NRF_PPI_GROUPS_USED - -/** - * @brief Bitmask defining SWI instances reserved to be used outside of nrfx. - */ -#define NRFX_SWI_USED NRF_SWI_USED - -/** - * @brief Bitmask defining TIMER instances reserved to be used outside of nrfx. - */ -#define NRFX_TIMERS_USED NRF_TIMERS_USED - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_GLUE_H__ diff --git a/bsp/boards/nrf52840/sdk/integration/nrfx/nrfx_log.h b/bsp/boards/nrf52840/sdk/integration/nrfx/nrfx_log.h deleted file mode 100644 index 6020d2c991..0000000000 --- a/bsp/boards/nrf52840/sdk/integration/nrfx/nrfx_log.h +++ /dev/null @@ -1,152 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_LOG_H__ -#define NRFX_LOG_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined(NRFX_LOG_MODULE) -#define NRF_LOG_MODULE_NAME NRFX_LOG_MODULE - -#define NRFX_CONFIG_ENTRY(x) CONCAT_3(NRFX_, NRFX_LOG_MODULE, x) - -#if NRFX_CHECK(NRFX_CONFIG_ENTRY(_CONFIG_LOG_ENABLED)) -#define NRF_LOG_LEVEL NRFX_CONFIG_ENTRY(_CONFIG_LOG_LEVEL) -#define NRF_LOG_INFO_COLOR NRFX_CONFIG_ENTRY(_CONFIG_INFO_COLOR) -#define NRF_LOG_DEBUG_COLOR NRFX_CONFIG_ENTRY(_CONFIG_DEBUG_COLOR) -#else -#define NRF_LOG_LEVEL 0 -#endif -#endif // defined(NRFX_LOG_MODULE) - -#include - -#if defined(NRFX_LOG_MODULE) -NRF_LOG_MODULE_REGISTER(); -#endif - -#define TEST_MACRO_INFO(...) NRF_LOG_INFO(__VA_ARGS__) -/** - * @defgroup nrfx_log nrfx_log.h - * @{ - * @ingroup nrfx - * - * @brief This file contains macros that should be implemented according to - * the needs of the host environment into which @em nrfx is integrated. - */ - -/** - * @brief Macro for logging a message with the severity level ERROR. - */ -#define NRFX_LOG_ERROR(...) NRF_LOG_ERROR(__VA_ARGS__) - -/** - * @brief Macro for logging a message with the severity level WARNING. - */ -#define NRFX_LOG_WARNING(...) NRF_LOG_WARNING(__VA_ARGS__) - -/** - * @brief Macro for logging a message with the severity level INFO. - */ -#define NRFX_LOG_INFO(...) TEST_MACRO_INFO(__VA_ARGS__) - -/** - * @brief Macro for logging a message with the severity level DEBUG. - */ -#define NRFX_LOG_DEBUG(...) NRF_LOG_DEBUG(__VA_ARGS__) - - -/** - * @brief Macro for logging a memory dump with the severity level ERROR. - * - * @param[in] p_memory Pointer to the memory region to be dumped. - * @param[in] length Length of the memory region in bytes. - */ -#define NRFX_LOG_HEXDUMP_ERROR(p_memory, length) \ - NRF_LOG_HEXDUMP_ERROR(p_memory, length) - -/** - * @brief Macro for logging a memory dump with the severity level WARNING. - * - * @param[in] p_memory Pointer to the memory region to be dumped. - * @param[in] length Length of the memory region in bytes. - */ -#define NRFX_LOG_HEXDUMP_WARNING(p_memory, length) \ - NRF_LOG_HEXDUMP_WARNING(p_memory, length) - -/** - * @brief Macro for logging a memory dump with the severity level INFO. - * - * @param[in] p_memory Pointer to the memory region to be dumped. - * @param[in] length Length of the memory region in bytes. - */ -#define NRFX_LOG_HEXDUMP_INFO(p_memory, length) \ - NRF_LOG_HEXDUMP_INFO(p_memory, length) - -/** - * @brief Macro for logging a memory dump with the severity level DEBUG. - * - * @param[in] p_memory Pointer to the memory region to be dumped. - * @param[in] length Length of the memory region in bytes. - */ -#define NRFX_LOG_HEXDUMP_DEBUG(p_memory, length) \ - NRF_LOG_HEXDUMP_DEBUG(p_memory, length) - - -/** - * @brief Macro for getting the textual representation of a given error code. - * - * @param[in] error_code Error code. - * - * @return String containing the textual representation of the error code. - */ -#define NRFX_LOG_ERROR_STRING_GET(error_code) \ - NRF_LOG_ERROR_STRING_GET(error_code) - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_LOG_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/LICENSE b/bsp/boards/nrf52840/sdk/modules/nrfx/LICENSE deleted file mode 100644 index 9656ea8a39..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/LICENSE +++ /dev/null @@ -1,39 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrf_bitmask.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrf_bitmask.h deleted file mode 100644 index 4d6fe8913d..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrf_bitmask.h +++ /dev/null @@ -1,156 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_BITMASK_H -#define NRF_BITMASK_H - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_bitmask Bitmask module - * @{ - * @ingroup nrfx - * @brief Bitmask managing module. - */ - -#define BITMASK_BYTE_GET(abs_bit) ((abs_bit)/8) -#define BITMASK_RELBIT_GET(abs_bit) ((abs_bit) & 0x00000007) - -/** - * Function for checking if bit in the multi-byte bit mask is set. - * - * @param bit Bit index. - * @param p_mask A pointer to mask with bit fields. - * - * @return 0 if bit is not set, positive value otherwise. - */ -__STATIC_INLINE uint32_t nrf_bitmask_bit_is_set(uint32_t bit, void const * p_mask) -{ - uint8_t const * p_mask8 = (uint8_t const *)p_mask; - uint32_t byte_idx = BITMASK_BYTE_GET(bit); - bit = BITMASK_RELBIT_GET(bit); - return (1 << bit) & p_mask8[byte_idx]; -} - -/** - * Function for setting a bit in the multi-byte bit mask. - * - * @param bit Bit index. - * @param p_mask A pointer to mask with bit fields. - */ -__STATIC_INLINE void nrf_bitmask_bit_set(uint32_t bit, void * p_mask) -{ - uint8_t * p_mask8 = (uint8_t *)p_mask; - uint32_t byte_idx = BITMASK_BYTE_GET(bit); - bit = BITMASK_RELBIT_GET(bit); - p_mask8[byte_idx] |= (1 << bit); -} - -/** - * Function for clearing a bit in the multi-byte bit mask. - * - * @param bit Bit index. - * @param p_mask A pointer to mask with bit fields. - */ -__STATIC_INLINE void nrf_bitmask_bit_clear(uint32_t bit, void * p_mask) -{ - uint8_t * p_mask8 = (uint8_t *)p_mask; - uint32_t byte_idx = BITMASK_BYTE_GET(bit); - bit = BITMASK_RELBIT_GET(bit); - p_mask8[byte_idx] &= ~(1 << bit); -} - -/** - * Function for performing bitwise OR operation on two multi-byte bit masks. - * - * @param p_mask1 A pointer to the first bit mask. - * @param p_mask2 A pointer to the second bit mask. - * @param p_out_mask A pointer to the output bit mask. - * @param length Length of output mask in bytes. - */ -__STATIC_INLINE void nrf_bitmask_masks_or(void const * p_mask1, - void const * p_mask2, - void * p_out_mask, - uint32_t length) -{ - uint8_t const * p_mask8_1 = (uint8_t const *)p_mask1; - uint8_t const * p_mask8_2 = (uint8_t const *)p_mask2; - uint8_t * p_mask8_out = (uint8_t *)p_out_mask; - uint32_t i; - for (i = 0; i < length; i++) - { - p_mask8_out[i] = p_mask8_1[i] | p_mask8_2[i]; - } -} - -/** - * Function for performing bitwise AND operation on two multi-byte bit masks. - * - * @param p_mask1 A pointer to the first bit mask. - * @param p_mask2 A pointer to the second bit mask. - * @param p_out_mask A pointer to the output bit mask. - * @param length Length of output mask in bytes. - */ -__STATIC_INLINE void nrf_bitmask_masks_and(void const * p_mask1, - void const * p_mask2, - void * p_out_mask, - uint32_t length) -{ - uint8_t const * p_mask8_1 = (uint8_t const *)p_mask1; - uint8_t const * p_mask8_2 = (uint8_t const *)p_mask2; - uint8_t * p_mask8_out = (uint8_t *)p_out_mask; - uint32_t i; - for (i = 0; i < length; i++) - { - p_mask8_out[i] = p_mask8_1[i] & p_mask8_2[i]; - } -} - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_BITMASK_H diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_adc.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_adc.h deleted file mode 100644 index 924ffbc4eb..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_adc.h +++ /dev/null @@ -1,281 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_ADC_H__ -#define NRFX_ADC_H__ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_adc ADC driver - * @{ - * @ingroup nrf_adc - * @brief Analog-to-Digital Converter (ADC) peripheral driver. - */ - -/** - * @brief Driver event types. - */ -typedef enum -{ - NRFX_ADC_EVT_DONE, ///< Event generated when the buffer is filled with samples. - NRFX_ADC_EVT_SAMPLE, ///< Event generated when the requested channel is sampled. -} nrfx_adc_evt_type_t; - -/** - * @brief Analog-to-digital converter driver DONE event. - */ -typedef struct -{ - nrf_adc_value_t * p_buffer; ///< Pointer to the buffer with converted samples. - uint16_t size; ///< Number of samples in the buffer. -} nrfx_adc_done_evt_t; - -/** - * @brief Analog-to-digital converter driver SAMPLE event. - */ -typedef struct -{ - nrf_adc_value_t sample; ///< Converted sample. -} nrfx_adc_sample_evt_t; - -/** - * @brief Analog-to-digital converter driver event. - */ -typedef struct -{ - nrfx_adc_evt_type_t type; ///< Event type. - union - { - nrfx_adc_done_evt_t done; ///< Data for DONE event. - nrfx_adc_sample_evt_t sample; ///< Data for SAMPLE event. - } data; -} nrfx_adc_evt_t; - -/**@brief Macro for initializing the ADC channel with the default configuration. */ -#define NRFX_ADC_DEFAULT_CHANNEL(analog_input) \ - { \ - NULL, \ - { \ - .resolution = NRF_ADC_CONFIG_RES_10BIT, \ - .scaling = NRF_ADC_CONFIG_SCALING_INPUT_FULL_SCALE, \ - .reference = NRF_ADC_CONFIG_REF_VBG, \ - .input = (analog_input), \ - .extref = NRF_ADC_CONFIG_EXTREFSEL_NONE \ - } \ - } - -// Forward declaration of the nrfx_adc_channel_t type. -typedef struct nrfx_adc_channel_s nrfx_adc_channel_t; - -/** - * @brief ADC channel. - * - * This structure is defined by the user and used by the driver. Therefore, it should - * not be defined on the stack as a local variable. - */ -struct nrfx_adc_channel_s -{ - nrfx_adc_channel_t * p_next; ///< Pointer to the next enabled channel (for internal use). - nrf_adc_config_t config; ///< ADC configuration for the current channel. -}; - -/** - * @brief ADC configuration. - */ -typedef struct -{ - uint8_t interrupt_priority; ///< Priority of ADC interrupt. -} nrfx_adc_config_t; - -/** @brief ADC default configuration. */ -#define NRFX_ADC_DEFAULT_CONFIG \ -{ \ - .interrupt_priority = NRFX_ADC_CONFIG_IRQ_PRIORITY \ -} - -/** - * @brief User event handler prototype. - * - * This function is called when the requested number of samples has been processed. - * - * @param p_event Event. - */ -typedef void (*nrfx_adc_event_handler_t)(nrfx_adc_evt_t const * p_event); - -/** - * @brief Function for initializing the ADC. - * - * If a valid event handler is provided, the driver is initialized in non-blocking mode. - * If event_handler is NULL, the driver works in blocking mode. - * - * @param[in] p_config Pointer to the structure with initial configuration. - * @param[in] event_handler Event handler provided by the user. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_INVALID_STATE If the driver is already initialized. - */ -nrfx_err_t nrfx_adc_init(nrfx_adc_config_t const * p_config, - nrfx_adc_event_handler_t event_handler); - -/** - * @brief Function for uninitializing the ADC. - * - * This function stops all ongoing conversions and disables all channels. - */ -void nrfx_adc_uninit(void); - -/** - * @brief Function for enabling an ADC channel. - * - * This function configures and enables the channel. When @ref nrfx_adc_buffer_convert is - * called, all channels that have been enabled with this function are sampled. - * - * @note The channel instance variable @p p_channel is used by the driver as an item - * in a list. Therefore, it cannot be an automatic variable that is located on the stack. - */ -void nrfx_adc_channel_enable(nrfx_adc_channel_t * const p_channel); - -/** - * @brief Function for disabling an ADC channel. - */ -void nrfx_adc_channel_disable(nrfx_adc_channel_t * const p_channel); - -/** - * @brief Function for starting ADC sampling. - * - * This function triggers single ADC sampling. If more than one channel is enabled, the driver - * emulates scanning and all channels are sampled in the order they were enabled. - */ -void nrfx_adc_sample(void); - -/** - * @brief Function for executing a single ADC conversion. - * - * This function selects the desired input and starts a single conversion. If a valid pointer - * is provided for the result, the function blocks until the conversion is completed. Otherwise, the - * function returns when the conversion is started, and the result is provided in an event (driver - * must be initialized in non-blocking mode, otherwise an assertion will fail). The function will - * fail if ADC is busy. The channel does not need to be enabled to perform a single conversion. - * - * @param[in] p_channel Channel. - * @param[out] p_value Pointer to the location where the result should be placed. Unless NULL is - * provided, the function is blocking. - * - * @retval NRFX_SUCCESS If conversion was successful. - * @retval NRFX_ERROR_BUSY If the ADC driver is busy. - */ -nrfx_err_t nrfx_adc_sample_convert(nrfx_adc_channel_t const * const p_channel, - nrf_adc_value_t * p_value); - -/** - * @brief Function for converting data to the buffer. - * - * If the driver is initialized in non-blocking mode, this function returns when the first - * conversion is set up. When the buffer is filled, the application is notified by the event - * handler. If the driver is initialized in blocking mode, the function returns when the buffer is - * filled. - * - * Conversion is done on all enabled channels, but it is not triggered by this - * function. This function will prepare the ADC for sampling and then - * wait for the SAMPLE task. Sampling can be triggered manually by the @ref - * nrfx_adc_sample function or by PPI using the @ref NRF_ADC_TASK_START task. - * - * @note If more than one channel is enabled, the function emulates scanning, and - * a single START task will trigger conversion on all enabled channels. For example: - * If 3 channels are enabled and the user requests 6 samples, the completion event - * handler will be called after 2 START tasks. - * - * @note The application must adjust the sampling frequency. The maximum frequency - * depends on the sampling timer and the maximum latency of the ADC interrupt. If - * an interrupt is not handled before the next sampling is triggered, the sample - * will be lost. - * - * @param[in] buffer Result buffer. - * @param[in] size Buffer size in samples. - * - * @retval NRFX_SUCCESS If conversion was successful. - * @retval NRFX_ERROR_BUSY If the driver is busy. - */ -nrfx_err_t nrfx_adc_buffer_convert(nrf_adc_value_t * buffer, uint16_t size); - -/** - * @brief Function for retrieving the ADC state. - * - * @retval true If the ADC is busy. - * @retval false If the ADC is ready. - */ -bool nrfx_adc_is_busy(void); - -/** - * @brief Function for getting the address of the ADC START task. - * - * This function is used to get the address of the START task, which can be used to trigger ADC - * conversion. - * - * @return Start task address. - */ -__STATIC_INLINE uint32_t nrfx_adc_start_task_get(void); - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -__STATIC_INLINE uint32_t nrfx_adc_start_task_get(void) -{ - return nrf_adc_task_address_get(NRF_ADC_TASK_START); -} - -#endif - - -void nrfx_adc_irq_handler(void); - - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_ADC_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_clock.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_clock.h deleted file mode 100644 index 93bc65c2f6..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_clock.h +++ /dev/null @@ -1,223 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_CLOCK_H__ -#define NRFX_CLOCK_H__ - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_clock CLOCK driver - * @{ - * @ingroup nrf_clock - * @brief CLOCK peripheral driver. - */ - -/** - * @brief Clock events. - */ -typedef enum -{ - NRFX_CLOCK_EVT_HFCLK_STARTED, ///< HFCLK has been started. - NRFX_CLOCK_EVT_LFCLK_STARTED, ///< LFCLK has been started. - NRFX_CLOCK_EVT_CTTO, ///< Calibration timeout. - NRFX_CLOCK_EVT_CAL_DONE ///< Calibration has been done. -} nrfx_clock_evt_type_t; - -/** - * @brief Clock event handler. - * - * @param[in] event Event. - */ -typedef void (*nrfx_clock_event_handler_t)(nrfx_clock_evt_type_t event); - -/** - * @brief Function for initializing internal structures in the nrfx_clock module. - * - * After initialization, the module is in power off state (clocks are not started). - * - * @param[in] event_handler Event handler provided by the user. - * Must not be NULL. - * - * @retval NRFX_SUCCESS If the procedure was successful. - * @retval NRFX_ERROR_ALREADY_INITIALIZED If the driver was already initialized. - */ -nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler); - -/** - * @brief Function for enabling interrupts in the clock module. - */ -void nrfx_clock_enable(void); - -/** - * @brief Function for disabling interrupts in the clock module. - */ -void nrfx_clock_disable(void); - -/** - * @brief Function for uninitializing the clock module. - */ -void nrfx_clock_uninit(void); - -/** - * @brief Function for starting the LFCLK. - */ -void nrfx_clock_lfclk_start(void); - -/** - * @brief Function for stoping the LFCLK. - */ -void nrfx_clock_lfclk_stop(void); - -/** - * @brief Function for checking the LFCLK state. - * - * @retval true If the LFCLK is running. - * @retval false If the LFCLK is not running. - */ -__STATIC_INLINE bool nrfx_clock_lfclk_is_running(void); - -/** - * @brief Function for starting the high-accuracy source HFCLK. - */ -void nrfx_clock_hfclk_start(void); - -/** - * @brief Function for stoping external high-accuracy source HFCLK. - */ -void nrfx_clock_hfclk_stop(void); - -/** - * @brief Function for checking the HFCLK state. - * - * @retval true If the HFCLK is running (XTAL source). - * @retval false If the HFCLK is not running. - */ -__STATIC_INLINE bool nrfx_clock_hfclk_is_running(void); - -/** - * @brief Function for starting calibration of internal LFCLK. - * - * This function starts the calibration process. The process cannot be aborted. LFCLK and HFCLK - * must be running before this function is called. - * - * @retval NRFX_SUCCESS If the procedure was successful. - * @retval NRFX_ERROR_INVALID_STATE If the low-frequency of high-frequency clock is off. - * @retval NRFX_ERROR_BUSY If calibration is in progress. - */ -nrfx_err_t nrfx_clock_calibration_start(void); - -/** - * @brief Function for checking if calibration is in progress. - * - * This function indicates that the system is in calibration phase. - * - * @retval NRFX_SUCCESS If the procedure was successful. - * @retval NRFX_ERROR_BUSY If calibration is in progress. - */ -nrfx_err_t nrfx_clock_is_calibrating(void); - -/** - * @brief Function for starting calibration timer. - * @param interval Time after which the CTTO event and interrupt will be generated (in 0.25 s units). - */ -void nrfx_clock_calibration_timer_start(uint8_t interval); - -/** - * @brief Function for stoping calibration timer. - */ -void nrfx_clock_calibration_timer_stop(void); - -/**@brief Function for returning a requested task address for the clock driver module. - * - * @param[in] task One of the peripheral tasks. - * - * @return Task address. - */ -__STATIC_INLINE uint32_t nrfx_clock_ppi_task_addr(nrf_clock_task_t task); - -/**@brief Function for returning a requested event address for the clock driver module. - * - * @param[in] event One of the peripheral events. - * - * @return Event address. - */ -__STATIC_INLINE uint32_t nrfx_clock_ppi_event_addr(nrf_clock_event_t event); - - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION -__STATIC_INLINE uint32_t nrfx_clock_ppi_task_addr(nrf_clock_task_t task) -{ - return nrf_clock_task_address_get(task); -} - -__STATIC_INLINE uint32_t nrfx_clock_ppi_event_addr(nrf_clock_event_t event) -{ - return nrf_clock_event_address_get(event); -} - -__STATIC_INLINE bool nrfx_clock_hfclk_is_running(void) -{ - return nrf_clock_hf_is_running(NRF_CLOCK_HFCLK_HIGH_ACCURACY); -} - -__STATIC_INLINE bool nrfx_clock_lfclk_is_running(void) -{ - return nrf_clock_lf_is_running(); -} -#endif //SUPPRESS_INLINE_IMPLEMENTATION - - -void nrfx_clock_irq_handler(void); - - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_CLOCK_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_comp.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_comp.h deleted file mode 100644 index 15b6077d2a..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_comp.h +++ /dev/null @@ -1,247 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_COMP_H__ -#define NRFX_COMP_H__ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_comp COMP driver - * @{ - * @ingroup nrf_comp - * @brief Comparator (COMP) peripheral driver. - */ - -/** - * @brief Macro to convert the threshold voltage to an integer value - * (needed by the COMP_TH register). - * - * @param[in] vol Voltage to be changed to COMP_TH register value. This value - * must not be smaller than reference voltage divided by 64. - * @param[in] ref Reference voltage. - */ -#define NRFX_VOLTAGE_THRESHOLD_TO_INT(vol, ref) \ - (uint8_t)(((vol) > ((ref) / 64)) ? (NRFX_ROUNDED_DIV((vol) * 64,(ref)) - 1) : 0) - -/** - * @brief COMP event handler function type. - * @param[in] event COMP event. - */ -typedef void (* nrfx_comp_event_handler_t)(nrf_comp_event_t event); - -/** @brief COMP shortcut masks. */ -typedef enum -{ - NRFX_COMP_SHORT_STOP_AFTER_CROSS_EVT = COMP_SHORTS_CROSS_STOP_Msk, /*!< Shortcut between the CROSS event and the STOP task. */ - NRFX_COMP_SHORT_STOP_AFTER_UP_EVT = COMP_SHORTS_UP_STOP_Msk, /*!< Shortcut between the UP event and the STOP task. */ - NRFX_COMP_SHORT_STOP_AFTER_DOWN_EVT = COMP_SHORTS_DOWN_STOP_Msk /*!< Shortcut between the DOWN event and the STOP task. */ -} nrfx_comp_short_mask_t; - -/** @brief COMP events masks. */ -typedef enum -{ - NRFX_COMP_EVT_EN_CROSS_MASK = COMP_INTENSET_CROSS_Msk, /*!< CROSS event (generated after VIN+ == VIN-). */ - NRFX_COMP_EVT_EN_UP_MASK = COMP_INTENSET_UP_Msk, /*!< UP event (generated when VIN+ crosses VIN- while increasing). */ - NRFX_COMP_EVT_EN_DOWN_MASK = COMP_INTENSET_DOWN_Msk, /*!< DOWN event (generated when VIN+ crosses VIN- while decreasing). */ - NRFX_COMP_EVT_EN_READY_MASK = COMP_INTENSET_READY_Msk /*!< READY event (generated when the module is ready). */ -} nrfx_comp_evt_en_mask_t; - -/** @brief COMP configuration. */ -typedef struct -{ - nrf_comp_ref_t reference; /**< Reference selection. */ - nrf_comp_ext_ref_t ext_ref; /**< External analog reference selection. */ - nrf_comp_main_mode_t main_mode; /**< Main operation mode. */ - nrf_comp_th_t threshold; /**< Structure holding THDOWN and THUP values needed by the COMP_TH register. */ - nrf_comp_sp_mode_t speed_mode; /**< Speed and power mode. */ - nrf_comp_hyst_t hyst; /**< Comparator hysteresis.*/ -#if defined (COMP_ISOURCE_ISOURCE_Msk) || defined (__NRFX_DOXYGEN__) - nrf_isource_t isource; /**< Current source selected on analog input. */ -#endif - nrf_comp_input_t input; /**< Input to be monitored. */ - uint8_t interrupt_priority; /**< Interrupt priority. */ -} nrfx_comp_config_t; - -/** @brief COMP threshold default configuration. */ -#define NRFX_COMP_CONFIG_TH \ -{ \ - .th_down = NRFX_VOLTAGE_THRESHOLD_TO_INT(0.5, 1.8), \ - .th_up = NRFX_VOLTAGE_THRESHOLD_TO_INT(1.5, 1.8) \ -} - -/** @brief COMP driver default configuration including the COMP HAL configuration. */ -#if defined (COMP_ISOURCE_ISOURCE_Msk) || defined (__NRFX_DOXYGEN__) -#define NRFX_COMP_DEFAULT_CONFIG(_input) \ -{ \ - .reference = (nrf_comp_ref_t)NRFX_COMP_CONFIG_REF, \ - .main_mode = (nrf_comp_main_mode_t)NRFX_COMP_CONFIG_MAIN_MODE, \ - .threshold = NRFX_COMP_CONFIG_TH, \ - .speed_mode = (nrf_comp_sp_mode_t)NRFX_COMP_CONFIG_SPEED_MODE, \ - .hyst = (nrf_comp_hyst_t)NRFX_COMP_CONFIG_HYST, \ - .isource = (nrf_isource_t)NRFX_COMP_CONFIG_ISOURCE, \ - .input = (nrf_comp_input_t)_input, \ - .interrupt_priority = NRFX_COMP_CONFIG_IRQ_PRIORITY \ -} -#else -#define NRFX_COMP_DEFAULT_CONFIG(_input) \ -{ \ - .reference = (nrf_comp_ref_t)NRFX_COMP_CONFIG_REF, \ - .main_mode = (nrf_comp_main_mode_t)NRFX_COMP_CONFIG_MAIN_MODE, \ - .threshold = NRFX_COMP_CONFIG_TH, \ - .speed_mode = (nrf_comp_sp_mode_t)NRFX_COMP_CONFIG_SPEED_MODE, \ - .hyst = (nrf_comp_hyst_t)NRFX_COMP_CONFIG_HYST, \ - .input = (nrf_comp_input_t)_input, \ - .interrupt_priority = NRFX_COMP_CONFIG_IRQ_PRIORITY \ -} -#endif - -/** - * @brief Function for initializing the COMP driver. - * - * This function initializes the COMP driver, but does not enable the peripheral or any interrupts. - * To start the driver, call the function @ref nrfx_comp_start() after initialization. - * - * @param[in] p_config Pointer to the structure with initial configuration. - * @param[in] event_handler Event handler provided by the user. - * Must not be NULL. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_INVALID_STATE If the driver has already been initialized. - * @retval NRFX_ERROR_BUSY If the LPCOMP peripheral is already in use. - * This is possible only if @ref nrfx_prs module - * is enabled. - */ -nrfx_err_t nrfx_comp_init(nrfx_comp_config_t const * p_config, - nrfx_comp_event_handler_t event_handler); - - -/** - * @brief Function for uninitializing the COMP driver. - * - * This function uninitializes the COMP driver. The COMP peripheral and - * its interrupts are disabled, and local variables are cleaned. After this call, you must - * initialize the driver again by calling nrfx_comp_init() if you want to use it. - * - * @sa nrfx_comp_stop() - */ -void nrfx_comp_uninit(void); - -/** - * @brief Function for setting the analog input. - * - * @param[in] psel COMP analog pin selection. - */ -void nrfx_comp_pin_select(nrf_comp_input_t psel); - -/** - * @brief Function for starting the COMP peripheral and interrupts. - * - * Before calling this function, the driver must be initialized. This function - * enables the COMP peripheral and its interrupts. - * - * @param[in] comp_evt_en_mask Mask of events to be enabled. This parameter should be built as - * 'or' of elements from @ref nrfx_comp_evt_en_mask_t. - * @param[in] comp_shorts_mask Mask of shorts to be enabled. This parameter should be built as - * 'or' of elements from @ref nrfx_comp_short_mask_t. - * - * @sa nrfx_comp_init() - * - */ -void nrfx_comp_start(uint32_t comp_evt_en_mask, uint32_t comp_shorts_mask); - -/**@brief Function for stopping the COMP peripheral. - * - * Before calling this function, the driver must be enabled. This function disables the COMP - * peripheral and its interrupts. - * - * @sa nrfx_comp_uninit() - * - */ -void nrfx_comp_stop(void); - -/** - * @brief Function for copying the current state of the comparator result to the RESULT register. - * - * @retval 0 If the input voltage is below the threshold (VIN+ < VIN-). - * @retval 1 If the input voltage is above the threshold (VIN+ > VIN-). - */ -uint32_t nrfx_comp_sample(void); - -/** - * @brief Function for getting the address of a COMP task. - * - * @param[in] task COMP task. - * - * @return Address of the given COMP task. - */ -__STATIC_INLINE uint32_t nrfx_comp_task_address_get(nrf_comp_task_t task) -{ - return (uint32_t)nrf_comp_task_address_get(task); -} - -/** - * @brief Function for getting the address of a COMP event. - * - * @param[in] event COMP event. - * - * @return Address of the given COMP event. - */ -__STATIC_INLINE uint32_t nrfx_comp_event_address_get(nrf_comp_event_t event) -{ - return (uint32_t)nrf_comp_event_address_get(event); -} - - -void nrfx_comp_irq_handler(void); - - -/** @} **/ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_COMP_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_gpiote.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_gpiote.h deleted file mode 100644 index b7943bc980..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_gpiote.h +++ /dev/null @@ -1,423 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_GPIOTE_H__ -#define NRFX_GPIOTE_H__ - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_gpiote GPIOTE driver - * @{ - * @ingroup nrf_gpiote - * @brief GPIOTE peripheral driver. - */ - -/**@brief Input pin configuration. */ -typedef struct -{ - nrf_gpiote_polarity_t sense; /**< Transition that triggers interrupt. */ - nrf_gpio_pin_pull_t pull; /**< Pulling mode. */ - bool is_watcher : 1; /**< True when the input pin is tracking an output pin. */ - bool hi_accuracy : 1; /**< True when high accuracy (IN_EVENT) is used. */ - bool skip_gpio_setup : 1; /**< Do not change GPIO configuration */ -} nrfx_gpiote_in_config_t; - -/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect low-to-high transition. - * @details Set hi_accu to true to use IN_EVENT. */ -#define NRFX_GPIOTE_CONFIG_IN_SENSE_LOTOHI(hi_accu) \ - { \ - .is_watcher = false, \ - .hi_accuracy = hi_accu, \ - .pull = NRF_GPIO_PIN_NOPULL, \ - .sense = NRF_GPIOTE_POLARITY_LOTOHI, \ - } - -/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect high-to-low transition. - * @details Set hi_accu to true to use IN_EVENT. */ -#define NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO(hi_accu) \ - { \ - .is_watcher = false, \ - .hi_accuracy = hi_accu, \ - .pull = NRF_GPIO_PIN_NOPULL, \ - .sense = NRF_GPIOTE_POLARITY_HITOLO, \ - } - -/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect any change on the pin. - * @details Set hi_accu to true to use IN_EVENT.*/ -#define NRFX_GPIOTE_CONFIG_IN_SENSE_TOGGLE(hi_accu) \ - { \ - .is_watcher = false, \ - .hi_accuracy = hi_accu, \ - .pull = NRF_GPIO_PIN_NOPULL, \ - .sense = NRF_GPIOTE_POLARITY_TOGGLE, \ - } - -/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect low-to-high transition. - * @details Set hi_accu to true to use IN_EVENT. - * @note This macro prepares configuration that skips GPIO setup. */ -#define NRFX_GPIOTE_RAW_CONFIG_IN_SENSE_LOTOHI(hi_accu) \ - { \ - .is_watcher = false, \ - .hi_accuracy = hi_accu, \ - .pull = NRF_GPIO_PIN_NOPULL, \ - .sense = NRF_GPIOTE_POLARITY_LOTOHI, \ - .skip_gpio_setup = true, \ - } - -/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect high-to-low transition. - * @details Set hi_accu to true to use IN_EVENT. - * @note This macro prepares configuration that skips GPIO setup. */ -#define NRFX_GPIOTE_RAW_CONFIG_IN_SENSE_HITOLO(hi_accu) \ - { \ - .is_watcher = false, \ - .hi_accuracy = hi_accu, \ - .pull = NRF_GPIO_PIN_NOPULL, \ - .sense = NRF_GPIOTE_POLARITY_HITOLO, \ - .skip_gpio_setup = true, \ - } - -/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect any change on the pin. - * @details Set hi_accu to true to use IN_EVENT. - * @note This macro prepares configuration that skips GPIO setup. */ -#define NRFX_GPIOTE_RAW_CONFIG_IN_SENSE_TOGGLE(hi_accu) \ - { \ - .is_watcher = false, \ - .hi_accuracy = hi_accu, \ - .pull = NRF_GPIO_PIN_NOPULL, \ - .sense = NRF_GPIOTE_POLARITY_TOGGLE, \ - .skip_gpio_setup = true, \ - } - - -/**@brief Output pin configuration. */ -typedef struct -{ - nrf_gpiote_polarity_t action; /**< Configuration of the pin task. */ - nrf_gpiote_outinit_t init_state; /**< Initial state of the output pin. */ - bool task_pin; /**< True if the pin is controlled by a GPIOTE task. */ -} nrfx_gpiote_out_config_t; - -/**@brief Macro for configuring a pin to use as output. GPIOTE is not used for the pin. */ -#define NRFX_GPIOTE_CONFIG_OUT_SIMPLE(init_high) \ - { \ - .init_state = init_high ? NRF_GPIOTE_INITIAL_VALUE_HIGH : NRF_GPIOTE_INITIAL_VALUE_LOW, \ - .task_pin = false, \ - } - -/**@brief Macro for configuring a pin to use the GPIO OUT TASK to change the state from high to low. - * @details The task will clear the pin. Therefore, the pin is set initially. */ -#define NRFX_GPIOTE_CONFIG_OUT_TASK_LOW \ - { \ - .init_state = NRF_GPIOTE_INITIAL_VALUE_HIGH, \ - .task_pin = true, \ - .action = NRF_GPIOTE_POLARITY_HITOLO, \ - } - -/**@brief Macro for configuring a pin to use the GPIO OUT TASK to change the state from low to high. - * @details The task will set the pin. Therefore, the pin is cleared initially. */ -#define NRFX_GPIOTE_CONFIG_OUT_TASK_HIGH \ - { \ - .init_state = NRF_GPIOTE_INITIAL_VALUE_LOW, \ - .task_pin = true, \ - .action = NRF_GPIOTE_POLARITY_LOTOHI, \ - } - -/**@brief Macro for configuring a pin to use the GPIO OUT TASK to toggle the pin state. - * @details The initial pin state must be provided. */ -#define NRFX_GPIOTE_CONFIG_OUT_TASK_TOGGLE(init_high) \ - { \ - .init_state = init_high ? NRF_GPIOTE_INITIAL_VALUE_HIGH : NRF_GPIOTE_INITIAL_VALUE_LOW, \ - .task_pin = true, \ - .action = NRF_GPIOTE_POLARITY_TOGGLE, \ - } - -/** @brief Pin. */ -typedef uint32_t nrfx_gpiote_pin_t; - -/** - * @brief Pin event handler prototype. - * - * @param pin Pin that triggered this event. - * @param action Action that lead to triggering this event. - */ -typedef void (*nrfx_gpiote_evt_handler_t)(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action); - -/** - * @brief Function for initializing the GPIOTE module. - * - * @details Only static configuration is supported to prevent the shared - * resource being customized by the initiator. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_INVALID_STATE If the driver was already initialized. - */ -nrfx_err_t nrfx_gpiote_init(void); - -/** - * @brief Function for checking if the GPIOTE module is initialized. - * - * @details The GPIOTE module is a shared module. Therefore, you should check if - * the module is already initialized and skip initialization if it is. - * - * @retval true If the module is already initialized. - * @retval false If the module is not initialized. - */ -bool nrfx_gpiote_is_init(void); - -/** - * @brief Function for uninitializing the GPIOTE module. - */ -void nrfx_gpiote_uninit(void); - -/** - * @brief Function for initializing a GPIOTE output pin. - * @details The output pin can be controlled by the CPU or by PPI. The initial - * configuration specifies which mode is used. If PPI mode is used, the driver - * attempts to allocate one of the available GPIOTE channels. If no channel is - * available, an error is returned. - * - * @param[in] pin Pin. - * @param[in] p_config Initial configuration. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_INVALID_STATE If the driver is not initialized or the pin is already used. - * @retval NRFX_ERROR_NO_MEM If no GPIOTE channel is available. - */ -nrfx_err_t nrfx_gpiote_out_init(nrfx_gpiote_pin_t pin, - nrfx_gpiote_out_config_t const * p_config); - -/** - * @brief Function for uninitializing a GPIOTE output pin. - * @details The driver frees the GPIOTE channel if the output pin was using one. - * - * @param[in] pin Pin. - */ -void nrfx_gpiote_out_uninit(nrfx_gpiote_pin_t pin); - -/** - * @brief Function for setting a GPIOTE output pin. - * - * @param[in] pin Pin. - */ -void nrfx_gpiote_out_set(nrfx_gpiote_pin_t pin); - -/** - * @brief Function for clearing a GPIOTE output pin. - * - * @param[in] pin Pin. - */ -void nrfx_gpiote_out_clear(nrfx_gpiote_pin_t pin); - -/** - * @brief Function for toggling a GPIOTE output pin. - * - * @param[in] pin Pin. - */ -void nrfx_gpiote_out_toggle(nrfx_gpiote_pin_t pin); - -/** - * @brief Function for enabling a GPIOTE output pin task. - * - * @param[in] pin Pin. - */ -void nrfx_gpiote_out_task_enable(nrfx_gpiote_pin_t pin); - -/** - * @brief Function for disabling a GPIOTE output pin task. - * - * @param[in] pin Pin. - */ -void nrfx_gpiote_out_task_disable(nrfx_gpiote_pin_t pin); - -/** - * @brief Function for getting the address of a configurable GPIOTE task. - * - * @param[in] pin Pin. - * - * @return Address of OUT task. - */ -uint32_t nrfx_gpiote_out_task_addr_get(nrfx_gpiote_pin_t pin); - -#if defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__NRFX_DOXYGEN__) -/** - * @brief Function for getting the address of a configurable GPIOTE task. - * - * @param[in] pin Pin. - * - * @return Address of SET task. - */ -uint32_t nrfx_gpiote_set_task_addr_get(nrfx_gpiote_pin_t pin); -#endif // defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__NRFX_DOXYGEN__) - -#if defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__) -/** - * @brief Function for getting the address of a configurable GPIOTE task. - * - * @param[in] pin Pin. - * - * @return Address of CLR task. - */ -uint32_t nrfx_gpiote_clr_task_addr_get(nrfx_gpiote_pin_t pin); -#endif // defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__) - -/** - * @brief Function for initializing a GPIOTE input pin. - * @details The input pin can act in two ways: - * - lower accuracy but low power (high frequency clock not needed) - * - higher accuracy (high frequency clock required) - * - * The initial configuration specifies which mode is used. - * If high-accuracy mode is used, the driver attempts to allocate one - * of the available GPIOTE channels. If no channel is - * available, an error is returned. - * In low accuracy mode SENSE feature is used. In this case only one active pin - * can be detected at a time. It can be worked around by setting all of the used - * low accuracy pins to toggle mode. - * For more information about SENSE functionality, refer to Product Specification. - * - * @param[in] pin Pin. - * @param[in] p_config Initial configuration. - * @param[in] evt_handler User function to be called when the configured transition occurs. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_INVALID_STATE If the driver is not initialized or the pin is already used. - * @retval NRFX_ERROR_NO_MEM If no GPIOTE channel is available. - */ -nrfx_err_t nrfx_gpiote_in_init(nrfx_gpiote_pin_t pin, - nrfx_gpiote_in_config_t const * p_config, - nrfx_gpiote_evt_handler_t evt_handler); - -/** - * @brief Function for uninitializing a GPIOTE input pin. - * @details The driver frees the GPIOTE channel if the input pin was using one. - * - * @param[in] pin Pin. - */ -void nrfx_gpiote_in_uninit(nrfx_gpiote_pin_t pin); - -/** - * @brief Function for enabling sensing of a GPIOTE input pin. - * - * @details If the input pin is configured as high-accuracy pin, the function - * enables an IN_EVENT. Otherwise, the function enables the GPIO sense mechanism. - * Note that a PORT event is shared between multiple pins, therefore the - * interrupt is always enabled. - * - * @param[in] pin Pin. - * @param[in] int_enable True to enable the interrupt. Always valid for a high-accuracy pin. - */ -void nrfx_gpiote_in_event_enable(nrfx_gpiote_pin_t pin, bool int_enable); - -/** - * @brief Function for disabling a GPIOTE input pin. - * - * @param[in] pin Pin. - */ -void nrfx_gpiote_in_event_disable(nrfx_gpiote_pin_t pin); - -/** - * @brief Function for checking if a GPIOTE input pin is set. - * - * @param[in] pin Pin. - * - * @retval true If the input pin is set. - * @retval false If the input pin is not set. - */ -bool nrfx_gpiote_in_is_set(nrfx_gpiote_pin_t pin); - -/** - * @brief Function for getting the address of a GPIOTE input pin event. - * @details If the pin is configured to use low-accuracy mode, the address of the PORT event is returned. - * - * @param[in] pin Pin. - */ -uint32_t nrfx_gpiote_in_event_addr_get(nrfx_gpiote_pin_t pin); - -/** - * @brief Function for forcing a specific state on the pin configured as task. - * - * @param[in] pin Pin. - * @param[in] state Pin state. - */ -void nrfx_gpiote_out_task_force(nrfx_gpiote_pin_t pin, uint8_t state); - -/** - * @brief Function for triggering the task OUT manually. - * - * @param[in] pin Pin. - */ -void nrfx_gpiote_out_task_trigger(nrfx_gpiote_pin_t pin); - -#if defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__NRFX_DOXYGEN__) -/** - * @brief Function for triggering the task SET manually. - * - * @param[in] pin Pin. - */ -void nrfx_gpiote_set_task_trigger(nrfx_gpiote_pin_t pin); -#endif // defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__NRFX_DOXYGEN__) - -#if defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__) -/** - * @brief Function for triggering the task CLR manually. - * - * @param[in] pin Pin. - */ -void nrfx_gpiote_clr_task_trigger(nrfx_gpiote_pin_t pin); -#endif // defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__) - - -void nrfx_gpiote_irq_handler(void); - - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_GPIOTE_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_i2s.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_i2s.h deleted file mode 100644 index 5d95b39a90..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_i2s.h +++ /dev/null @@ -1,254 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_I2S_H__ -#define NRFX_I2S_H__ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_i2s I2S driver - * @{ - * @ingroup nrf_i2s - * @brief Inter-IC Sound (I2S) peripheral driver. - */ - - -/** - * @brief This value can be provided instead of a pin number for the signals - * SDOUT, SDIN, and MCK to specify that a given signal is not used - * and therefore does not need to be connected to a pin. - */ -#define NRFX_I2S_PIN_NOT_USED 0xFF - -/** @brief I2S driver configuration structure. */ -typedef struct -{ - uint8_t sck_pin; ///< SCK pin number. - uint8_t lrck_pin; ///< LRCK pin number. - uint8_t mck_pin; ///< MCK pin number. - /**< Optional. Use @ref NRFX_I2S_PIN_NOT_USED - * if this signal is not needed. */ - uint8_t sdout_pin; ///< SDOUT pin number. - /**< Optional. Use @ref NRFX_I2S_PIN_NOT_USED - * if this signal is not needed. */ - uint8_t sdin_pin; ///< SDIN pin number. - /**< Optional. Use @ref NRFX_I2S_PIN_NOT_USED - * if this signal is not needed. */ - uint8_t irq_priority; ///< Interrupt priority. - - nrf_i2s_mode_t mode; ///< Mode of operation. - nrf_i2s_format_t format; ///< Frame format. - nrf_i2s_align_t alignment; ///< Alignment of sample within a frame. - nrf_i2s_swidth_t sample_width; ///< Sample width. - nrf_i2s_channels_t channels; ///< Enabled channels. - nrf_i2s_mck_t mck_setup; ///< Master clock setup. - nrf_i2s_ratio_t ratio; ///< MCK/LRCK ratio. -} nrfx_i2s_config_t; - -/** @brief I2S driver buffers structure. */ -typedef struct -{ - uint32_t * p_rx_buffer; - uint32_t const * p_tx_buffer; -} nrfx_i2s_buffers_t; - -/** - * @brief I2S driver default configuration. - */ -#define NRFX_I2S_DEFAULT_CONFIG \ -{ \ - .sck_pin = NRFX_I2S_CONFIG_SCK_PIN, \ - .lrck_pin = NRFX_I2S_CONFIG_LRCK_PIN, \ - .mck_pin = NRFX_I2S_CONFIG_MCK_PIN, \ - .sdout_pin = NRFX_I2S_CONFIG_SDOUT_PIN, \ - .sdin_pin = NRFX_I2S_CONFIG_SDIN_PIN, \ - .irq_priority = NRFX_I2S_CONFIG_IRQ_PRIORITY, \ - .mode = (nrf_i2s_mode_t)NRFX_I2S_CONFIG_MASTER, \ - .format = (nrf_i2s_format_t)NRFX_I2S_CONFIG_FORMAT, \ - .alignment = (nrf_i2s_align_t)NRFX_I2S_CONFIG_ALIGN, \ - .sample_width = (nrf_i2s_swidth_t)NRFX_I2S_CONFIG_SWIDTH, \ - .channels = (nrf_i2s_channels_t)NRFX_I2S_CONFIG_CHANNELS, \ - .mck_setup = (nrf_i2s_mck_t)NRFX_I2S_CONFIG_MCK_SETUP, \ - .ratio = (nrf_i2s_ratio_t)NRFX_I2S_CONFIG_RATIO, \ -} - - -#define NRFX_I2S_STATUS_NEXT_BUFFERS_NEEDED (1UL << 0) - /**< The application should provide buffers that are to be used in the next - * part of the transfer. A call to @ref nrfx_i2s_next_buffers_set should - * be done before the currently used buffers are completely processed - * (i.e. the time remaining for supplying the next buffers depends on - * the used size of the buffers). */ - -/** - * @brief I2S driver data handler type. - * - * A data handling function of this type must be specified during initialization - * of the driver. The driver will call this function when it finishes using - * buffers passed to it by the application, and when it needs to be provided - * with buffers for the next part of the transfer. - * - * @note The @c p_released pointer passed to this function is temporary and - * will be invalid after the function returns, hence it cannot be stored - * and used later. If needed, the pointed content (i.e. buffers pointers) - * should be copied instead. - * - * @param[in] p_released Pointer to a structure with pointers to buffers - * passed previously to the driver that will no longer - * be access by it (they can be now safely released or - * used for another purpose, in particular for a next - * part of the transfer). - * This pointer will be NULL if the application did not - * supply the buffers for the next part of the transfer - * (via a call to @ref nrfx_i2s_next_buffers_set) since - * the previous time the data handler signaled such need. - * This means that data corruption occurred (the previous - * buffers are used for the second time) and no buffers - * can be released at the moment. - * Both pointers in this structure are NULL when the - * handler is called for the first time after a transfer - * is started, because no data has been transferred yet - * at this point. In all successive calls the pointers - * specify what has been sent (TX) and what has been - * received (RX) in the part of transfer that has just - * been completed (provided that a given direction is - * enabled, see @ref nrfx_i2s_start). - * @param[in] status Bit field describing the current status of the transfer. - * It can be 0 or a combination of the following flags: - * - @ref NRFX_I2S_STATUS_NEXT_BUFFERS_NEEDED - */ -typedef void (* nrfx_i2s_data_handler_t)(nrfx_i2s_buffers_t const * p_released, - uint32_t status); - - -/** - * @brief Function for initializing the I2S driver. - * - * @param[in] p_config Pointer to the structure with initial configuration. - * @param[in] handler Data handler provided by the user. Must not be NULL. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_INVALID_STATE If the driver was already initialized. - * @retval NRFX_ERROR_INVALID_PARAM If the requested combination of configuration - * options is not allowed by the I2S peripheral. - */ -nrfx_err_t nrfx_i2s_init(nrfx_i2s_config_t const * p_config, - nrfx_i2s_data_handler_t handler); - -/** @brief Function for uninitializing the I2S driver. */ -void nrfx_i2s_uninit(void); - -/** - * @brief Function for starting the continuous I2S transfer. - * - * The I2S data transfer can be performed in one of three modes: RX (reception) - * only, TX (transmission) only, or in both directions simultaneously. - * The mode is selected by specifying a proper buffer for a given direction - * in the call to this function or by passing NULL instead if this direction - * should be disabled. - * - * The length of the buffer (which is a common value for RX and TX if both - * directions are enabled) is specified in 32-bit words. One 32-bit memory - * word can either contain four 8-bit samples, two 16-bit samples, or one - * right-aligned 24-bit sample sign-extended to a 32-bit value. - * For a detailed memory mapping for different supported configurations, - * see the @linkProductSpecification52. - * - * @note Peripherals using EasyDMA (including I2S) require the transfer buffers - * to be placed in the Data RAM region. If this condition is not met, - * this function will fail with the error code NRFX_ERROR_INVALID_ADDR. - * - * @param[in] p_initial_buffers Pointer to a structure specifying the buffers - * to be used in the initial part of the transfer - * (buffers for all consecutive parts are provided - * through the data handler). - * @param[in] buffer_size Size of the buffers (in 32-bit words). - * Must not be 0. - * @param[in] flags Transfer options (0 for default settings). - * Currently, no additional flags are available. - * - * @retval NRFX_SUCCESS If the operation was successful. - * @retval NRFX_ERROR_INVALID_STATE If a transfer was already started or - * the driver has not been initialized. - * @retval NRFX_ERROR_INVALID_ADDR If the provided buffers are not placed - * in the Data RAM region. - */ -nrfx_err_t nrfx_i2s_start(nrfx_i2s_buffers_t const * p_initial_buffers, - uint16_t buffer_size, - uint8_t flags); - -/** - * @brief Function for supplying the buffers to be used in the next part of - * the transfer. - * - * The application should call this function when the data handler receives - * @ref NRFX_I2S_STATUS_NEXT_BUFFERS_NEEDED in the @c status parameter. - * The call can be done immediately from the data handler function or later, - * but it has to be done before the I2S peripheral finishes processing the - * buffers supplied previously. Otherwise, data corruption will occur. - * - * @sa nrfx_i2s_data_handler_t - * - * @retval NRFX_SUCCESS If the operation was successful. - * @retval NRFX_ERROR_INVALID_STATE If the buffers were already supplied or - * the peripheral is currently being stopped. - */ -nrfx_err_t nrfx_i2s_next_buffers_set(nrfx_i2s_buffers_t const * p_buffers); - -/** @brief Function for stopping the I2S transfer. */ -void nrfx_i2s_stop(void); - -/** @} */ - - -void nrfx_i2s_irq_handler(void); - - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_I2S_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_lpcomp.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_lpcomp.h deleted file mode 100644 index 45671bcacd..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_lpcomp.h +++ /dev/null @@ -1,150 +0,0 @@ -/** - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_LPCOMP_H__ -#define NRFX_LPCOMP_H__ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_lpcomp LPCOMP driver - * @{ - * @ingroup nrf_lpcomp - * @brief Low Power Comparator (LPCOMP) peripheral driver. - */ - -/** - * @brief LPCOMP event handler function type. - * @param[in] event LPCOMP event. - */ -typedef void (* nrfx_lpcomp_event_handler_t)(nrf_lpcomp_event_t event); - -/** @brief LPCOMP configuration. */ -typedef struct -{ - nrf_lpcomp_config_t hal; /**< LPCOMP HAL configuration. */ - nrf_lpcomp_input_t input; /**< Input to be monitored. */ - uint8_t interrupt_priority; /**< LPCOMP interrupt priority. */ -} nrfx_lpcomp_config_t; - -/** @brief LPCOMP driver default configuration including the LPCOMP HAL configuration. */ -#ifdef NRF52_SERIES -#define NRFX_LPCOMP_DEFAULT_CONFIG \ - { \ - .hal = { (nrf_lpcomp_ref_t)NRFX_LPCOMP_CONFIG_REFERENCE , \ - (nrf_lpcomp_detect_t)NRFX_LPCOMP_CONFIG_DETECTION, \ - (nrf_lpcomp_hysteresis_t)NRFX_LPCOMP_CONFIG_HYST }, \ - .input = (nrf_lpcomp_input_t)NRFX_LPCOMP_CONFIG_INPUT, \ - .interrupt_priority = NRFX_LPCOMP_CONFIG_IRQ_PRIORITY \ - } -#else -#define NRFX_LPCOMP_DEFAULT_CONFIG \ - { \ - .hal = { (nrf_lpcomp_ref_t)NRFX_LPCOMP_CONFIG_REFERENCE , \ - (nrf_lpcomp_detect_t)NRFX_LPCOMP_CONFIG_DETECTION }, \ - .input = (nrf_lpcomp_input_t)NRFX_LPCOMP_CONFIG_INPUT, \ - .interrupt_priority = NRFX_LPCOMP_CONFIG_IRQ_PRIORITY \ - } -#endif - -/** - * @brief Function for initializing the LPCOMP driver. - * - * This function initializes the LPCOMP driver, but does not enable the peripheral or any interrupts. - * To start the driver, call the function nrfx_lpcomp_enable() after initialization. - * - * @param[in] p_config Pointer to the structure with initial configuration. - * @param[in] event_handler Event handler provided by the user. - * Must not be NULL. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_INVALID_STATE If the driver has already been initialized. - * @retval NRFX_ERROR_BUSY If the COMP peripheral is already in use. - * This is possible only if @ref nrfx_prs module - * is enabled. - */ -nrfx_err_t nrfx_lpcomp_init(nrfx_lpcomp_config_t const * p_config, - nrfx_lpcomp_event_handler_t event_handler); - -/** - * @brief Function for uninitializing the LCOMP driver. - * - * This function uninitializes the LPCOMP driver. The LPCOMP peripheral and - * its interrupts are disabled, and local variables are cleaned. After this call, you must - * initialize the driver again by calling nrfx_lpcomp_init() if you want to use it. - * - * @sa nrfx_lpcomp_disable() - * @sa nrfx_lpcomp_init() - */ -void nrfx_lpcomp_uninit(void); - -/**@brief Function for enabling the LPCOMP peripheral and interrupts. - * - * Before calling this function, the driver must be initialized. This function - * enables the LPCOMP peripheral and its interrupts. - * - * @sa nrfx_lpcomp_disable() - */ -void nrfx_lpcomp_enable(void); - -/**@brief Function for disabling the LPCOMP peripheral. - * - * Before calling this function, the driver must be initialized. This function disables the LPCOMP - * peripheral and its interrupts. - * - * @sa nrfx_lpcomp_enable() - */ -void nrfx_lpcomp_disable(void); - - -void nrfx_lpcomp_irq_handler(void); - -/** @} **/ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_LPCOMP_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_pdm.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_pdm.h deleted file mode 100644 index 52e5513ae6..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_pdm.h +++ /dev/null @@ -1,214 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_PDM_H__ -#define NRFX_PDM_H__ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_pdm PDM driver - * @{ - * @ingroup nrf_pdm - * @brief Pulse Density Modulation (PDM) peripheral driver. - */ - - -#define NRFX_PDM_MAX_BUFFER_SIZE 32767 - - -/** - * @brief PDM error type. - */ -typedef enum -{ - NRFX_PDM_NO_ERROR = 0, - NRFX_PDM_ERROR_OVERFLOW = 1 -} nrfx_pdm_error_t; - -/** - * @brief PDM event structure. - */ -typedef struct -{ - bool buffer_requested; ///< Buffer request flag. - int16_t * buffer_released; ///< Pointer to the released buffer. Can be NULL. - nrfx_pdm_error_t error; ///< Error type. -} nrfx_pdm_evt_t; - -/** - * @brief PDM interface driver configuration structure. - */ -typedef struct -{ - nrf_pdm_mode_t mode; ///< Interface operation mode. - nrf_pdm_edge_t edge; ///< Sampling mode. - uint8_t pin_clk; ///< CLK pin. - uint8_t pin_din; ///< DIN pin. - nrf_pdm_freq_t clock_freq; ///< Clock frequency. - nrf_pdm_gain_t gain_l; ///< Left channel gain. - nrf_pdm_gain_t gain_r; ///< Right channel gain. - uint8_t interrupt_priority; ///< Interrupt priority. -} nrfx_pdm_config_t; - -/** - * @brief Macro for setting @ref nrfx_pdm_config_t to default settings - * in single ended mode. - * - * @param _pin_clk CLK output pin. - * @param _pin_din DIN input pin. - */ -#define NRFX_PDM_DEFAULT_CONFIG(_pin_clk, _pin_din) \ -{ \ - .mode = (nrf_pdm_mode_t)NRFX_PDM_CONFIG_MODE, \ - .edge = (nrf_pdm_edge_t)NRFX_PDM_CONFIG_EDGE, \ - .pin_clk = _pin_clk, \ - .pin_din = _pin_din, \ - .clock_freq = (nrf_pdm_freq_t)NRFX_PDM_CONFIG_CLOCK_FREQ, \ - .gain_l = NRF_PDM_GAIN_DEFAULT, \ - .gain_r = NRF_PDM_GAIN_DEFAULT, \ - .interrupt_priority = NRFX_PDM_CONFIG_IRQ_PRIORITY \ -} - -/** - * @brief Handler for PDM interface ready events. - * - * This event handler is called on a buffer request, an error or when a buffer - * is full and ready to be processed. - * - * @param[in] p_evt Pointer to the PDM event structure. - */ -typedef void (*nrfx_pdm_event_handler_t)(nrfx_pdm_evt_t const * const p_evt); - - -/** - * @brief Function for initializing the PDM interface. - * - * @param[in] p_config Pointer to the structure with initial configuration. - * @param[in] event_handler Event handler provided by the user. Cannot be NULL. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_INVALID_STATE If the driver is already initialized. - * @retval NRFX_ERROR_INVALID_PARAM If invalid configuration was specified. - */ -nrfx_err_t nrfx_pdm_init(nrfx_pdm_config_t const * p_config, - nrfx_pdm_event_handler_t event_handler); - -/** - * @brief Function for uninitializing the PDM interface. - * - * This function stops PDM sampling, if it is in progress. - */ -void nrfx_pdm_uninit(void); - -/** - * @brief Function for getting the address of a PDM interface task. - * - * @param[in] task Task. - * - * @return Task address. - */ -__STATIC_INLINE uint32_t nrfx_pdm_task_address_get(nrf_pdm_task_t task) -{ - return nrf_pdm_task_address_get(task); -} - -/** - * @brief Function for getting the state of the PDM interface. - * - * @retval true If the PDM interface is enabled. - * @retval false If the PDM interface is disabled. - */ -__STATIC_INLINE bool nrfx_pdm_enable_check(void) -{ - return nrf_pdm_enable_check(); -} - -/** - * @brief Function for starting PDM sampling. - * - * @retval NRFX_SUCCESS If sampling was started successfully or was already in progress. - * @retval NRFX_ERROR_BUSY If a previous start/stop operation is in progress. - */ -nrfx_err_t nrfx_pdm_start(void); - -/** - * @brief Function for stopping PDM sampling. - * - * When this function is called, the PDM interface is stopped after finishing - * the current frame. - * The event handler function might be called once more after calling this function. - * - * @retval NRFX_SUCCESS If sampling was stopped successfully or was already stopped before. - * @retval NRFX_ERROR_BUSY If a previous start/stop operation is in progress. - */ -nrfx_err_t nrfx_pdm_stop(void); - -/** - * @brief Function for supplying the sample buffer. - * - * Call this function after every buffer request event. - * - * @param[in] buffer Pointer to the receive buffer. Cannot be NULL. - * @param[in] buffer_length Length of the receive buffer in 16-bit words. - * - * @retval NRFX_SUCCESS If the buffer was applied successfully. - * @retval NRFX_ERROR_BUSY If the buffer was already supplied or the peripheral is currently being stopped. - * @retval NRFX_ERROR_INVALID_STATE If the driver was not initialized. - * @retval NRFX_ERROR_INVALID_PARAM If invalid parameters were provided. - */ -nrfx_err_t nrfx_pdm_buffer_set(int16_t * buffer, uint16_t buffer_length); - - -void nrfx_pdm_irq_handler(void); - - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_PDM_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_power.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_power.h deleted file mode 100644 index 254abd10d7..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_power.h +++ /dev/null @@ -1,382 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_POWER_H__ -#define NRFX_POWER_H__ - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_power POWER driver - * @{ - * @ingroup nrf_power - * @brief POWER peripheral driver. - */ - -/** - * @brief Power mode possible configurations - */ -typedef enum -{ - NRFX_POWER_MODE_CONSTLAT, /**< Constant latency mode */ - NRFX_POWER_MODE_LOWPWR /**< Low power mode */ -}nrfx_power_mode_t; - -#if NRF_POWER_HAS_SLEEPEVT || defined(__NRFX_DOXYGEN__) -/** - * @brief Events from power system - */ -typedef enum -{ - NRFX_POWER_SLEEP_EVT_ENTER, /**< CPU entered WFI/WFE sleep - * - * Keep in mind that if this interrupt is enabled, - * it means that CPU was waken up just after WFI by this interrupt. - */ - NRFX_POWER_SLEEP_EVT_EXIT /**< CPU exited WFI/WFE sleep */ -}nrfx_power_sleep_evt_t; -#endif /* NRF_POWER_HAS_SLEEPEVT */ - -#if NRF_POWER_HAS_USBREG || defined(__NRFX_DOXYGEN__) -/** - * @brief Events from USB power system - */ -typedef enum -{ - NRFX_POWER_USB_EVT_DETECTED, /**< USB power detected on the connector (plugged in). */ - NRFX_POWER_USB_EVT_REMOVED, /**< USB power removed from the connector. */ - NRFX_POWER_USB_EVT_READY /**< USB power regulator ready. */ -}nrfx_power_usb_evt_t; - -/** - * @brief USB power state - * - * The single enumerator that holds all data about current state of USB - * related POWER. - * - * Organized this way that higher power state has higher numeric value - */ -typedef enum -{ - NRFX_POWER_USB_STATE_DISCONNECTED, /**< No power on USB lines detected */ - NRFX_POWER_USB_STATE_CONNECTED, /**< The USB power is detected, but USB power regulator is not ready */ - NRFX_POWER_USB_STATE_READY /**< From the power point of view USB is ready for working */ -}nrfx_power_usb_state_t; -#endif /* NRF_POWER_HAS_USBREG */ - -/** - * @name Callback types - * - * Defined types of callback functions - * @{ - */ -/** - * @brief Event handler for power failure warning - */ -typedef void (*nrfx_power_pofwarn_event_handler_t)(void); - -#if NRF_POWER_HAS_SLEEPEVT || defined(__NRFX_DOXYGEN__) -/** - * @brief Event handler for entering/exiting sleep - * - * @param event Event type - */ -typedef void (*nrfx_power_sleep_event_handler_t)(nrfx_power_sleep_evt_t event); -#endif - -#if NRF_POWER_HAS_USBREG || defined(__NRFX_DOXYGEN__) -/** - * @brief Event handler for USB related power events - * - * @param event Event type - */ -typedef void (*nrfx_power_usb_event_handler_t)(nrfx_power_usb_evt_t event); -#endif -/** @} */ - -/** - * @brief General power configuration - * - * Parameters required to initialize power driver. - */ -typedef struct -{ - /** - * @brief Enable main DCDC regulator - * - * This bit only informs the driver that elements for DCDC regulator - * are installed and regulator can be used. - * The regulator would be enabled or disabled automatically - * by the hardware, basing on current power requirement. - */ - bool dcdcen:1; - -#if NRF_POWER_HAS_VDDH || defined(__NRFX_DOXYGEN__) - /** - * @brief Enable HV DCDC regulator - * - * This bit only informs the driver that elements for DCDC regulator - * are installed and regulator can be used. - * The regulator would be enabled or disabled automatically - * by the hardware, basing on current power requirement. - */ - bool dcdcenhv: 1; -#endif -}nrfx_power_config_t; - -/** - * @brief The configuration for power failure comparator - * - * Configuration used to enable and configure power failure comparator - */ -typedef struct -{ - nrfx_power_pofwarn_event_handler_t handler; //!< Event handler - nrf_power_pof_thr_t thr; //!< Threshold for power failure detection -#if NRF_POWER_HAS_VDDH || defined(__NRFX_DOXYGEN__) - nrf_power_pof_thrvddh_t thrvddh; //!< Threshold for power failure detection on VDDH pin -#endif -}nrfx_power_pofwarn_config_t; - -#if NRF_POWER_HAS_SLEEPEVT || defined(__NRFX_DOXYGEN__) -/** - * @brief The configuration of sleep event processing - * - * Configuration used to enable and configure sleep event handling - */ -typedef struct -{ - nrfx_power_sleep_event_handler_t handler; //!< Event handler - bool en_enter:1; //!< Enable event on sleep entering - bool en_exit :1; //!< Enable event on sleep exiting -}nrfx_power_sleepevt_config_t; -#endif - -#if NRF_POWER_HAS_USBREG || defined(__NRFX_DOXYGEN__) -/** - * @brief The configuration of USB related power events - * - * Configuration used to enable and configure USB power event handling - */ -typedef struct -{ - nrfx_power_usb_event_handler_t handler; //!< Event processing -}nrfx_power_usbevt_config_t; -#endif /* NRF_POWER_HAS_USBREG */ - -/** - * @brief Function for getting the handler of the power failure comparator. - * @return Handler of the power failure comparator. - */ -nrfx_power_pofwarn_event_handler_t nrfx_power_pof_handler_get(void); - -#if NRF_POWER_HAS_USBREG || defined(__NRFX_DOXYGEN__) -/** - * @brief Function for getting the handler of the USB power. - * @return Handler of the USB power. - */ -nrfx_power_usb_event_handler_t nrfx_power_usb_handler_get(void); -#endif - -/** - * @brief Initialize power module driver - * - * Enabled power module driver would process all the interrupts from power system. - * - * @param[in] p_config Pointer to the structure with initial configuration. - * - * @retval NRFX_SUCCESS Successfully initialized. - * @retval NRFX_ERROR_ALREADY_INITIALIZED Module was already initialized. - */ -nrfx_err_t nrfx_power_init(nrfx_power_config_t const * p_config); - -/** - * @brief Unintialize power module driver - * - * Disables all the interrupt handling in the module. - * - * @sa nrfx_power_init - */ -void nrfx_power_uninit(void); - -/** - * @brief Initialize power failure comparator - * - * Configures the power failure comparator. This function does not setup and enable it. - * Those steps can be done with functions @ref nrfx_power_pof_enable and @ref nrfx_power_pof_disable - * or with Softdevice API (when Softdevice is using). - * - * @param[in] p_config Configuration with values and event handler. - * If event handler is set to NULL, interrupt would be disabled. - */ -void nrfx_power_pof_init(nrfx_power_pofwarn_config_t const * p_config); - -/** - * @brief Enable power failure comparator - * Sets and enables interrupt of the power failure comparator. This functions cannot be using - * when Softdevice is enabled. If event handler set in init function is set to NULL, interrupt - * would be disabled. - * - * @param[in] p_config Configuration with values and event handler. - */ -void nrfx_power_pof_enable(nrfx_power_pofwarn_config_t const * p_config); - -/** - * @brief Disable the power failure comparator - * - * Disables the power failure comparator interrupt. - */ -void nrfx_power_pof_disable(void); - -/** - * @brief Clear the power failure comparator settings - * - * Clears the settings of the power failure comparator. - */ -void nrfx_power_pof_uninit(void); - -#if NRF_POWER_HAS_SLEEPEVT || defined(__NRFX_DOXYGEN__) -/** - * @brief Initialize sleep entering and exiting events processing - * - * Configures and setups the sleep event processing. - * - * @param[in] p_config Configuration with values and event handler. - * - * @sa nrfx_power_sleepevt_uninit - * - */ -void nrfx_power_sleepevt_init(nrfx_power_sleepevt_config_t const * p_config); - -/** - * @brief Enable sleep entering and exiting events processing - * - * @param[in] p_config Configuration with values and event handler. - */ -void nrfx_power_sleepevt_enable(nrfx_power_sleepevt_config_t const * p_config); - -/** - * @brief Disable sleep entering and exiting events processing - */ -void nrfx_power_sleepevt_disable(void); - -/** - * @brief Uninitialize sleep entering and exiting events processing - * - * @sa nrfx_power_sleepevt_init - */ -void nrfx_power_sleepevt_uninit(void); -#endif /* NRF_POWER_HAS_SLEEPEVT */ - -#if NRF_POWER_HAS_USBREG || defined(__NRFX_DOXYGEN__) -/** - * @brief Initialize USB power event processing - * - * Configures and setups the USB power event processing. - * - * @param[in] p_config Configuration with values and event handler. - * - * @sa nrfx_power_usbevt_uninit - */ -void nrfx_power_usbevt_init(nrfx_power_usbevt_config_t const * p_config); - -/** - * @brief Enable USB power event processing - */ -void nrfx_power_usbevt_enable(void); - -/** - * @brief Disable USB power event processing - */ -void nrfx_power_usbevt_disable(void); - -/** - * @brief Uninitalize USB power event processing - * - * @sa nrfx_power_usbevt_init - */ -void nrfx_power_usbevt_uninit(void); - -/** - * @brief Get the status of USB power - * - * @return Current USB power status - */ -__STATIC_INLINE nrfx_power_usb_state_t nrfx_power_usbstatus_get(void); - -#endif /* NRF_POWER_HAS_USBREG */ - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -#if NRF_POWER_HAS_USBREG -__STATIC_INLINE nrfx_power_usb_state_t nrfx_power_usbstatus_get(void) -{ - uint32_t status = nrf_power_usbregstatus_get(); - if(0 == (status & NRF_POWER_USBREGSTATUS_VBUSDETECT_MASK)) - { - return NRFX_POWER_USB_STATE_DISCONNECTED; - } - if(0 == (status & NRF_POWER_USBREGSTATUS_OUTPUTRDY_MASK)) - { - return NRFX_POWER_USB_STATE_CONNECTED; - } - return NRFX_POWER_USB_STATE_READY; -} -#endif /* NRF_POWER_HAS_USBREG */ - -#endif /* SUPPRESS_INLINE_IMPLEMENTATION */ - - -void nrfx_power_irq_handler(void); - - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* NRFX_POWER_H__ */ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_power_clock.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_power_clock.h deleted file mode 100644 index 17e33db2e7..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_power_clock.h +++ /dev/null @@ -1,90 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_POWER_CLOCK_H__ -#define NRFX_POWER_CLOCK_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - - -__STATIC_INLINE void nrfx_power_clock_irq_init(void); - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION -__STATIC_INLINE void nrfx_power_clock_irq_init(void) -{ - uint8_t priority; -#if NRFX_CHECK(NRFX_POWER_ENABLED) && NRFX_CHECK(NRFX_CLOCK_ENABLED) - #if NRFX_POWER_CONFIG_IRQ_PRIORITY != NRFX_CLOCK_CONFIG_IRQ_PRIORITY - #error "IRQ priority for POWER and CLOCK have to be the same. Check ." - #endif - priority = NRFX_POWER_CONFIG_IRQ_PRIORITY; -#elif NRFX_CHECK(NRFX_POWER_ENABLED) - priority = NRFX_POWER_CONFIG_IRQ_PRIORITY; -#elif NRFX_CHECK(NRFX_CLOCK_ENABLED) - priority = NRFX_CLOCK_CONFIG_IRQ_PRIORITY; -#endif - - if (!NRFX_IRQ_IS_ENABLED(POWER_CLOCK_IRQn)) - { - NRFX_IRQ_PRIORITY_SET(POWER_CLOCK_IRQn, priority); - NRFX_IRQ_ENABLE(POWER_CLOCK_IRQn); - } -} -#endif // SUPPRESS_INLINE_IMPLEMENTATION - - -#if NRFX_CHECK(NRFX_POWER_ENABLED) && NRFX_CHECK(NRFX_CLOCK_ENABLED) -void nrfx_power_clock_irq_handler(void); -#elif NRFX_CHECK(NRFX_POWER_ENABLED) -#define nrfx_power_irq_handler nrfx_power_clock_irq_handler -#elif NRFX_CHECK(NRFX_CLOCK_ENABLED) -#define nrfx_clock_irq_handler nrfx_power_clock_irq_handler -#endif - - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_POWER_CLOCK_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_ppi.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_ppi.h deleted file mode 100644 index c29d0cb601..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_ppi.h +++ /dev/null @@ -1,327 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_PPI_H__ -#define NRFX_PPI_H__ - -#include -#include - -/** - * @defgroup nrfx_ppi PPI allocator - * @{ - * @ingroup nrf_ppi - * @brief Programmable Peripheral Interconnect (PPI) allocator. - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef NRFX_PPI_CHANNELS_USED -#define NRFX_PPI_CHANNELS_USED 0 -#endif - -#ifndef NRFX_PPI_GROUPS_USED -#define NRFX_PPI_GROUPS_USED 0 -#endif - -#if PPI_CH_NUM > 16 -#define NRFX_PPI_ALL_APP_CHANNELS_MASK ((uint32_t)0xFFFFFFFFuL & ~(NRFX_PPI_CHANNELS_USED)) /**< All PPI channels available to the application. */ -#define NRFX_PPI_PROG_APP_CHANNELS_MASK ((uint32_t)0x000FFFFFuL & ~(NRFX_PPI_CHANNELS_USED)) /**< Programmable PPI channels available to the application. */ -#else -#define NRFX_PPI_ALL_APP_CHANNELS_MASK ((uint32_t)0xFFF0FFFFuL & ~(NRFX_PPI_CHANNELS_USED)) /**< All PPI channels available to the application. */ -#define NRFX_PPI_PROG_APP_CHANNELS_MASK ((uint32_t)0x0000FFFFuL & ~(NRFX_PPI_CHANNELS_USED)) /**< Programmable PPI channels available to the application. */ -#endif - -#define NRFX_PPI_ALL_APP_GROUPS_MASK (((1uL << PPI_GROUP_NUM) - 1) & ~(NRFX_PPI_GROUPS_USED)) /**< All PPI groups available to the application. */ - -/** - * @brief Function for uninitializing the PPI module. - * - * This function disables all channels and clears the channel groups. - */ -void nrfx_ppi_free_all(void); - -/** - * @brief Function for allocating a PPI channel. - * @details This function allocates the first unused PPI channel. - * - * @param[out] p_channel Pointer to the PPI channel that has been allocated. - * - * @retval NRFX_SUCCESS If the channel was successfully allocated. - * @retval NRFX_ERROR_NO_MEM If there is no available channel to be used. - */ -nrfx_err_t nrfx_ppi_channel_alloc(nrf_ppi_channel_t * p_channel); - -/** - * @brief Function for freeing a PPI channel. - * @details This function also disables the chosen channel. - * - * @param[in] channel PPI channel to be freed. - * - * @retval NRFX_SUCCESS If the channel was successfully freed. - * @retval NRFX_ERROR_INVALID_PARAM If the channel is not user-configurable. - */ -nrfx_err_t nrfx_ppi_channel_free(nrf_ppi_channel_t channel); - -/** - * @brief Function for assigning task and event endpoints to the PPI channel. - * - * @param[in] channel PPI channel to be assigned endpoints. - * @param[in] eep Event endpoint address. - * @param[in] tep Task endpoint address. - * - * @retval NRFX_SUCCESS If the channel was successfully assigned. - * @retval NRFX_ERROR_INVALID_STATE If the channel is not allocated for the user. - * @retval NRFX_ERROR_INVALID_PARAM If the channel is not user-configurable. - */ -nrfx_err_t nrfx_ppi_channel_assign(nrf_ppi_channel_t channel, uint32_t eep, uint32_t tep); - -/** - * @brief Function for assigning or clearing fork endpoint to the PPI channel. - * - * @param[in] channel PPI channel to be assigned endpoints. - * @param[in] fork_tep Fork task endpoint address or 0 to clear. - * - * @retval NRFX_SUCCESS If the channel was successfully assigned. - * @retval NRFX_ERROR_INVALID_STATE If the channel is not allocated for the user. - * @retval NRFX_ERROR_INVALID_PARAM If the channel is not user-configurable. - * @retval NRFX_ERROR_NOT_SUPPORTED If function is not supported. - */ -nrfx_err_t nrfx_ppi_channel_fork_assign(nrf_ppi_channel_t channel, uint32_t fork_tep); - -/** - * @brief Function for enabling a PPI channel. - * - * @param[in] channel PPI channel to be enabled. - * - * @retval NRFX_SUCCESS If the channel was successfully enabled. - * @retval NRFX_ERROR_INVALID_STATE If the user-configurable channel is not allocated. - * @retval NRFX_ERROR_INVALID_PARAM If the channel cannot be enabled by the user. - */ -nrfx_err_t nrfx_ppi_channel_enable(nrf_ppi_channel_t channel); - -/** - * @brief Function for disabling a PPI channel. - * - * @param[in] channel PPI channel to be disabled. - * - * @retval NRFX_SUCCESS If the channel was successfully disabled. - * @retval NRFX_ERROR_INVALID_STATE If the user-configurable channel is not allocated. - * @retval NRFX_ERROR_INVALID_PARAM If the channel cannot be disabled by the user. - */ -nrfx_err_t nrfx_ppi_channel_disable(nrf_ppi_channel_t channel); - -/** - * @brief Function for allocating a PPI channel group. - * @details This function allocates the first unused PPI group. - * - * @param[out] p_group Pointer to the PPI channel group that has been allocated. - * - * @retval NRFX_SUCCESS If the channel group was successfully allocated. - * @retval NRFX_ERROR_NO_MEM If there is no available channel group to be used. - */ -nrfx_err_t nrfx_ppi_group_alloc(nrf_ppi_channel_group_t * p_group); - -/** - * @brief Function for freeing a PPI channel group. - * @details This function also disables the chosen group. - * - * @param[in] group PPI channel group to be freed. - * - * @retval NRFX_SUCCESS If the channel group was successfully freed. - * @retval NRFX_ERROR_INVALID_PARAM If the channel group is not user-configurable. - */ -nrfx_err_t nrfx_ppi_group_free(nrf_ppi_channel_group_t group); - -/** - * @brief Compute a channel mask for NRF_PPI registers. - * - * @param[in] channel Channel number to transform to a mask. - * - * @retval Channel mask. - */ -__STATIC_INLINE uint32_t nrfx_ppi_channel_to_mask(nrf_ppi_channel_t channel) -{ - return (1uL << (uint32_t) channel); -} - -/** - * @brief Function for including multiple PPI channels in a channel group. - * - * @param[in] channel_mask PPI channels to be added. - * @param[in] group Channel group in which to include the channels. - * - * @retval NRFX_SUCCESS If the channels was successfully included. - * @retval NRFX_ERROR_INVALID_PARAM If group is not an application group or channels are not an - * application channels. - * @retval NRFX_ERROR_INVALID_STATE If group is not an allocated group. - */ -nrfx_err_t nrfx_ppi_channels_include_in_group(uint32_t channel_mask, - nrf_ppi_channel_group_t group); - -/** - * @brief Function for including a PPI channel in a channel group. - * - * @param[in] channel PPI channel to be added. - * @param[in] group Channel group in which to include the channel. - * - * @retval NRFX_SUCCESS If the channel was successfully included. - * @retval NRFX_ERROR_INVALID_PARAM If group is not an application group or channel is not an - * application channel. - * @retval NRFX_ERROR_INVALID_STATE If group is not an allocated group. - */ -__STATIC_INLINE nrfx_err_t nrfx_ppi_channel_include_in_group(nrf_ppi_channel_t channel, - nrf_ppi_channel_group_t group) -{ - return nrfx_ppi_channels_include_in_group(nrfx_ppi_channel_to_mask(channel), group); -} - -/** - * @brief Function for removing multiple PPI channels from a channel group. - * - * @param[in] channel_mask PPI channels to be removed. - * @param[in] group Channel group from which to remove the channels. - * - * @retval NRFX_SUCCESS If the channel was successfully removed. - * @retval NRFX_ERROR_INVALID_PARAM If group is not an application group or channels are not an - * application channels. - * @retval NRFX_ERROR_INVALID_STATE If group is not an allocated group. - */ -nrfx_err_t nrfx_ppi_channels_remove_from_group(uint32_t channel_mask, - nrf_ppi_channel_group_t group); - -/** - * @brief Function for removing a PPI channel from a channel group. - * - * @param[in] channel PPI channel to be removed. - * @param[in] group Channel group from which to remove the channel. - * - * @retval NRFX_SUCCESS If the channel was successfully removed. - * @retval NRFX_ERROR_INVALID_PARAM If group is not an application group or channel is not an - * application channel. - * @retval NRFX_ERROR_INVALID_STATE If group is not an allocated group. - */ -__STATIC_INLINE nrfx_err_t nrfx_ppi_channel_remove_from_group(nrf_ppi_channel_t channel, - nrf_ppi_channel_group_t group) -{ - return nrfx_ppi_channels_remove_from_group(nrfx_ppi_channel_to_mask(channel), group); -} - -/** - * @brief Function for clearing a PPI channel group. - * - * @param[in] group Channel group to be cleared. - * - * @retval NRFX_SUCCESS If the group was successfully cleared. - * @retval NRFX_ERROR_INVALID_PARAM If group is not an application group. - * @retval NRFX_ERROR_INVALID_STATE If group is not an allocated group. - */ -__STATIC_INLINE nrfx_err_t nrfx_ppi_group_clear(nrf_ppi_channel_group_t group) -{ - return nrfx_ppi_channels_remove_from_group(NRFX_PPI_ALL_APP_CHANNELS_MASK, group); -} - -/** - * @brief Function for enabling a PPI channel group. - * - * @param[in] group Channel group to be enabled. - * - * @retval NRFX_SUCCESS If the group was successfully enabled. - * @retval NRFX_ERROR_INVALID_PARAM If group is not an application group. - * @retval NRFX_ERROR_INVALID_STATE If group is not an allocated group. - */ -nrfx_err_t nrfx_ppi_group_enable(nrf_ppi_channel_group_t group); - -/** - * @brief Function for disabling a PPI channel group. - * - * @param[in] group Channel group to be disabled. - * - * @retval NRFX_SUCCESS If the group was successfully disabled. - * @retval NRFX_ERROR_INVALID_PARAM If group is not an application group. - * @retval NRFX_ERROR_INVALID_STATE If group is not an allocated group. - */ -nrfx_err_t nrfx_ppi_group_disable(nrf_ppi_channel_group_t group); - -/** - * @brief Function for getting the address of a PPI task. - * - * @param[in] task Task. - * - * @retval Task address. - */ -__STATIC_INLINE uint32_t nrfx_ppi_task_addr_get(nrf_ppi_task_t task) -{ - return (uint32_t) nrf_ppi_task_address_get(task); -} - -/** - * @brief Function for getting the address of a PPI group enable task. - * - * @param[in] group PPI channel group - * - * @retval Task address. - */ -__STATIC_INLINE uint32_t nrfx_ppi_task_addr_group_enable_get(nrf_ppi_channel_group_t group) -{ - return (uint32_t) nrf_ppi_task_group_enable_address_get(group); -} - -/** - * @brief Function for getting the address of a PPI group enable task. - * - * @param[in] group PPI channel group - * - * @retval Task address. - */ -__STATIC_INLINE uint32_t nrfx_ppi_task_addr_group_disable_get(nrf_ppi_channel_group_t group) -{ - return (uint32_t) nrf_ppi_task_group_disable_address_get(group); -} - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_PPI_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_pwm.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_pwm.h deleted file mode 100644 index 36ad975fba..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_pwm.h +++ /dev/null @@ -1,497 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_PWM_H__ -#define NRFX_PWM_H__ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_pwm PWM driver - * @{ - * @ingroup nrf_pwm - * @brief Pulse Width Modulation (PWM) peripheral driver. - */ - -/** - * @brief PWM driver instance data structure. - */ -typedef struct -{ - NRF_PWM_Type * p_registers; ///< Pointer to the structure with PWM peripheral instance registers. - uint8_t drv_inst_idx; ///< Driver instance index. -} nrfx_pwm_t; - -/** - * @brief Macro for creating a PWM driver instance. - */ -#define NRFX_PWM_INSTANCE(id) \ -{ \ - .p_registers = NRFX_CONCAT_2(NRF_PWM, id), \ - .drv_inst_idx = NRFX_CONCAT_3(NRFX_PWM, id, _INST_IDX), \ -} - -enum { -#if NRFX_CHECK(NRFX_PWM0_ENABLED) - NRFX_PWM0_INST_IDX, -#endif -#if NRFX_CHECK(NRFX_PWM1_ENABLED) - NRFX_PWM1_INST_IDX, -#endif -#if NRFX_CHECK(NRFX_PWM2_ENABLED) - NRFX_PWM2_INST_IDX, -#endif -#if NRFX_CHECK(NRFX_PWM3_ENABLED) - NRFX_PWM3_INST_IDX, -#endif - NRFX_PWM_ENABLED_COUNT -}; - -/** - * @brief This value can be provided instead of a pin number for any channel - * to specify that its output is not used and therefore does not need - * to be connected to a pin. - */ -#define NRFX_PWM_PIN_NOT_USED 0xFF - -/** - * @brief This value can be added to a pin number to inverse its polarity - * (set idle state = 1). - */ -#define NRFX_PWM_PIN_INVERTED 0x80 - -/** - * @brief PWM driver configuration structure. - */ -typedef struct -{ - uint8_t output_pins[NRF_PWM_CHANNEL_COUNT]; ///< Pin numbers for individual output channels (optional). - /**< Use @ref NRFX_PWM_PIN_NOT_USED - * if a given output channel is not needed. */ - uint8_t irq_priority; ///< Interrupt priority. - nrf_pwm_clk_t base_clock; ///< Base clock frequency. - nrf_pwm_mode_t count_mode; ///< Operating mode of the pulse generator counter. - uint16_t top_value; ///< Value up to which the pulse generator counter counts. - nrf_pwm_dec_load_t load_mode; ///< Mode of loading sequence data from RAM. - nrf_pwm_dec_step_t step_mode; ///< Mode of advancing the active sequence. -} nrfx_pwm_config_t; - -/** - * @brief PWM driver default configuration. - */ -#define NRFX_PWM_DEFAULT_CONFIG \ -{ \ - .output_pins = { NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN, \ - NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN, \ - NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN, \ - NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN }, \ - .irq_priority = NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY, \ - .base_clock = (nrf_pwm_clk_t)NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK, \ - .count_mode = (nrf_pwm_mode_t)NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE, \ - .top_value = NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE, \ - .load_mode = (nrf_pwm_dec_load_t)NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE, \ - .step_mode = (nrf_pwm_dec_step_t)NRFX_PWM_DEFAULT_CONFIG_STEP_MODE, \ -} - - -/** - * @brief PWM flags providing additional playback options. - */ -typedef enum -{ - NRFX_PWM_FLAG_STOP = 0x01, /**< When the requested playback is finished, - the peripheral should be stopped. - @note The STOP task is triggered when - the last value of the final sequence is - loaded from RAM, and the peripheral stops - at the end of the current PWM period. - For sequences with configured repeating - of duty cycle values, this might result in - less than the requested number of repeats - of the last value. */ - NRFX_PWM_FLAG_LOOP = 0x02, /**< When the requested playback is finished, - it should be started from the beginning. - This flag is ignored if used together - with @ref NRFX_PWM_FLAG_STOP. - @note The playback restart is done via a - shortcut configured in the PWM peripheral. - This shortcut triggers the proper starting - task when the final value of previous - playback is read from RAM and applied to - the pulse generator counter. - When this mechanism is used together with - the @ref NRF_PWM_STEP_TRIGGERED mode, - the playback restart will occur right - after switching to the final value (this - final value will be played only once). */ - NRFX_PWM_FLAG_SIGNAL_END_SEQ0 = 0x04, /**< The event handler should be - called when the last value - from sequence 0 is loaded. */ - NRFX_PWM_FLAG_SIGNAL_END_SEQ1 = 0x08, /**< The event handler should be - called when the last value - from sequence 1 is loaded. */ - NRFX_PWM_FLAG_NO_EVT_FINISHED = 0x10, /**< The playback finished event - (enabled by default) should be - suppressed. */ - NRFX_PWM_FLAG_START_VIA_TASK = 0x80, /**< The playback should not be - started directly by the called - function. Instead, the function - should only prepare it and - return the address of the task - to be triggered to start the - playback. */ -} nrfx_pwm_flag_t; - - -/** - * @brief PWM driver event type. - */ -typedef enum -{ - NRFX_PWM_EVT_FINISHED, ///< Sequence playback finished. - NRFX_PWM_EVT_END_SEQ0, /**< End of sequence 0 reached. Its data can be - safely modified now. */ - NRFX_PWM_EVT_END_SEQ1, /**< End of sequence 1 reached. Its data can be - safely modified now. */ - NRFX_PWM_EVT_STOPPED, ///< The PWM peripheral has been stopped. -} nrfx_pwm_evt_type_t; - -/** - * @brief PWM driver event handler type. - */ -typedef void (* nrfx_pwm_handler_t)(nrfx_pwm_evt_type_t event_type); - - -/** - * @brief Function for initializing the PWM driver. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_config Pointer to the structure with initial configuration. - * - * @param[in] handler Event handler provided by the user. If NULL is passed - * instead, event notifications are not done and PWM - * interrupts are disabled. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_INVALID_STATE If the driver was already initialized. - */ -nrfx_err_t nrfx_pwm_init(nrfx_pwm_t const * const p_instance, - nrfx_pwm_config_t const * p_config, - nrfx_pwm_handler_t handler); - -/** - * @brief Function for uninitializing the PWM driver. - * - * If any sequence playback is in progress, it is stopped immediately. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_pwm_uninit(nrfx_pwm_t const * const p_instance); - -/** - * @brief Function for starting a single sequence playback. - * - * To take advantage of the looping mechanism in the PWM peripheral, both - * sequences must be used (single sequence can be played back only once by - * the peripheral). Therefore, the provided sequence is internally set and - * played back as both sequence 0 and sequence 1. Consequently, if end of - * sequence notifications are required, events for both sequences should be - * used (that means that both the @ref NRFX_PWM_FLAG_SIGNAL_END_SEQ0 flag - * and the @ref NRFX_PWM_FLAG_SIGNAL_END_SEQ1 flag should be specified and - * the @ref NRFX_PWM_EVT_END_SEQ0 event and the @ref NRFX_PWM_EVT_END_SEQ1 - * event should be handled in the same way). - * - * Use the @ref NRFX_PWM_FLAG_START_VIA_TASK flag if you want the playback - * to be only prepared by this function, and you want to start it later by - * triggering a task (using PPI for instance). The function will then return - * the address of the task to be triggered. - * - * @note The array containing the duty cycle values for the specified sequence - * must be in RAM and cannot be allocated on stack. - * For detailed information, see @ref nrf_pwm_sequence_t. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_sequence Sequence to be played back. - * @param[in] playback_count Number of playbacks to be performed (must not be 0). - * @param[in] flags Additional options. Pass any combination of - * @ref nrfx_pwm_flag_t "playback flags", or 0 - * for default settings. - * - * @return Address of the task to be triggered to start the playback if the @ref - * NRFX_PWM_FLAG_START_VIA_TASK flag was used, 0 otherwise. - */ -uint32_t nrfx_pwm_simple_playback(nrfx_pwm_t const * const p_instance, - nrf_pwm_sequence_t const * p_sequence, - uint16_t playback_count, - uint32_t flags); - -/** - * @brief Function for starting a two-sequence playback. - * - * Use the @ref NRFX_PWM_FLAG_START_VIA_TASK flag if you want the playback - * to be only prepared by this function, and you want to start it later by - * triggering a task (using PPI for instance). The function will then return - * the address of the task to be triggered. - * - * @note The array containing the duty cycle values for the specified sequence - * must be in RAM and cannot be allocated on stack. - * For detailed information, see @ref nrf_pwm_sequence_t. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_sequence_0 First sequence to be played back. - * @param[in] p_sequence_1 Second sequence to be played back. - * @param[in] playback_count Number of playbacks to be performed (must not be 0). - * @param[in] flags Additional options. Pass any combination of - * @ref nrfx_pwm_flag_t "playback flags", or 0 - * for default settings. - * - * @return Address of the task to be triggered to start the playback if the @ref - * NRFX_PWM_FLAG_START_VIA_TASK flag was used, 0 otherwise. - */ -uint32_t nrfx_pwm_complex_playback(nrfx_pwm_t const * const p_instance, - nrf_pwm_sequence_t const * p_sequence_0, - nrf_pwm_sequence_t const * p_sequence_1, - uint16_t playback_count, - uint32_t flags); - -/** - * @brief Function for advancing the active sequence. - * - * This function only applies to @ref NRF_PWM_STEP_TRIGGERED mode. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -__STATIC_INLINE void nrfx_pwm_step(nrfx_pwm_t const * const p_instance); - -/** - * @brief Function for stopping the sequence playback. - * - * The playback is stopped at the end of the current PWM period. - * This means that if the active sequence is configured to repeat each duty - * cycle value for a certain number of PWM periods, the last played value - * might appear on the output less times than requested. - * - * @note This function can be instructed to wait until the playback is stopped - * (by setting @p wait_until_stopped to true). Note that, depending on - * the length of the PMW period, this might take a significant amount of - * time. Alternatively, the @ref nrfx_pwm_is_stopped function can be - * used to poll the status, or the @ref NRFX_PWM_EVT_STOPPED event can - * be used to get the notification when the playback is stopped, provided - * the event handler is defined. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] wait_until_stopped If true, the function will not return until - * the playback is stopped. - * - * @retval true If the PWM peripheral is stopped. - * @retval false If the PWM peripheral is not stopped. - */ -bool nrfx_pwm_stop(nrfx_pwm_t const * const p_instance, - bool wait_until_stopped); - -/** - * @brief Function for checking the status of the PWM peripheral. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @retval true If the PWM peripheral is stopped. - * @retval false If the PWM peripheral is not stopped. - */ -bool nrfx_pwm_is_stopped(nrfx_pwm_t const * const p_instance); - -/** - * @brief Function for updating the sequence data during playback. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] seq_id Identifier of the sequence (0 or 1). - * @param[in] p_sequence Pointer to the new sequence definition. - */ -__STATIC_INLINE void nrfx_pwm_sequence_update( - nrfx_pwm_t const * const p_instance, - uint8_t seq_id, - nrf_pwm_sequence_t const * p_sequence); - -/** - * @brief Function for updating the pointer to the duty cycle values - * in the specified sequence during playback. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] seq_id Identifier of the sequence (0 or 1). - * @param[in] values New pointer to the duty cycle values. - */ -__STATIC_INLINE void nrfx_pwm_sequence_values_update(nrfx_pwm_t const * const p_instance, - uint8_t seq_id, - nrf_pwm_values_t values); - -/** - * @brief Function for updating the number of duty cycle values - * in the specified sequence during playback. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] seq_id Identifier of the sequence (0 or 1). - * @param[in] length New number of the duty cycle values. - */ -__STATIC_INLINE void nrfx_pwm_sequence_length_update(nrfx_pwm_t const * const p_instance, - uint8_t seq_id, - uint16_t length); - -/** - * @brief Function for updating the number of repeats for duty cycle values - * in specified sequence during playback. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] seq_id Identifier of the sequence (0 or 1). - * @param[in] repeats New number of repeats. - */ -__STATIC_INLINE void nrfx_pwm_sequence_repeats_update(nrfx_pwm_t const * const p_instance, - uint8_t seq_id, - uint32_t repeats); - -/** - * @brief Function for updating the additional delay after the specified - * sequence during playback. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] seq_id Identifier of the sequence (0 or 1). - * @param[in] end_delay New end delay value (in PWM periods). - */ -__STATIC_INLINE void nrfx_pwm_sequence_end_delay_update(nrfx_pwm_t const * const p_instance, - uint8_t seq_id, - uint32_t end_delay); - -/** - * @brief Function for returning the address of a specified PWM task that can - * be used in PPI module. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] task Requested task. - * - * @return Task address. - */ -__STATIC_INLINE uint32_t nrfx_pwm_task_address_get(nrfx_pwm_t const * const p_instance, - nrf_pwm_task_t task); - -/**@brief Function for returning the address of a specified PWM event that can - * be used in PPI module. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] event Requested event. - * - * @return Event address. - */ -__STATIC_INLINE uint32_t nrfx_pwm_event_address_get(nrfx_pwm_t const * const p_instance, - nrf_pwm_event_t event); - - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -__STATIC_INLINE void nrfx_pwm_step(nrfx_pwm_t const * const p_instance) -{ - nrf_pwm_task_trigger(p_instance->p_registers, NRF_PWM_TASK_NEXTSTEP); -} - -__STATIC_INLINE void nrfx_pwm_sequence_update(nrfx_pwm_t const * const p_instance, - uint8_t seq_id, - nrf_pwm_sequence_t const * p_sequence) -{ - nrf_pwm_sequence_set(p_instance->p_registers, seq_id, p_sequence); -} - -__STATIC_INLINE void nrfx_pwm_sequence_values_update(nrfx_pwm_t const * const p_instance, - uint8_t seq_id, - nrf_pwm_values_t values) -{ - nrf_pwm_seq_ptr_set(p_instance->p_registers, seq_id, values.p_raw); -} - -__STATIC_INLINE void nrfx_pwm_sequence_length_update(nrfx_pwm_t const * const p_instance, - uint8_t seq_id, - uint16_t length) -{ - nrf_pwm_seq_cnt_set(p_instance->p_registers, seq_id, length); -} - -__STATIC_INLINE void nrfx_pwm_sequence_repeats_update(nrfx_pwm_t const * const p_instance, - uint8_t seq_id, - uint32_t repeats) -{ - nrf_pwm_seq_refresh_set(p_instance->p_registers, seq_id, repeats); -} - -__STATIC_INLINE void nrfx_pwm_sequence_end_delay_update(nrfx_pwm_t const * const p_instance, - uint8_t seq_id, - uint32_t end_delay) -{ - nrf_pwm_seq_end_delay_set(p_instance->p_registers, seq_id, end_delay); -} - -__STATIC_INLINE uint32_t nrfx_pwm_task_address_get(nrfx_pwm_t const * const p_instance, - nrf_pwm_task_t task) -{ - return nrf_pwm_task_address_get(p_instance->p_registers, task); -} - -__STATIC_INLINE uint32_t nrfx_pwm_event_address_get(nrfx_pwm_t const * const p_instance, - nrf_pwm_event_t event) -{ - return nrf_pwm_event_address_get(p_instance->p_registers, event); -} - -#endif // SUPPRESS_INLINE_IMPLEMENTATION - - -void nrfx_pwm_0_irq_handler(void); -void nrfx_pwm_1_irq_handler(void); -void nrfx_pwm_2_irq_handler(void); -void nrfx_pwm_3_irq_handler(void); - - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_PWM_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_qdec.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_qdec.h deleted file mode 100644 index 87e737a28d..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_qdec.h +++ /dev/null @@ -1,186 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_QDEC_H__ -#define NRFX_QDEC_H__ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_qdec QDEC driver - * @{ - * @ingroup nrf_qdec - * @brief Quadrature Decoder (QDEC) peripheral driver. - */ - -/**@brief QDEC configuration structure.*/ -typedef struct -{ - nrf_qdec_reportper_t reportper; /**< Report period in samples. */ - nrf_qdec_sampleper_t sampleper; /**< Sampling period in microseconds. */ - uint32_t psela; /**< Pin number for A input. */ - uint32_t pselb; /**< Pin number for B input. */ - uint32_t pselled; /**< Pin number for LED output. */ - uint32_t ledpre; /**< Time (in microseconds) how long LED is switched on before sampling. */ - nrf_qdec_ledpol_t ledpol; /**< Active LED polarity. */ - bool dbfen; /**< State of debouncing filter. */ - bool sample_inten; /**< Enabling sample ready interrupt. */ - uint8_t interrupt_priority; /**< QDEC interrupt priority. */ -} nrfx_qdec_config_t; - -/**@brief QDEC default configuration. */ -#define NRFX_QDEC_DEFAULT_CONFIG \ - { \ - .reportper = (nrf_qdec_reportper_t)NRFX_QDEC_CONFIG_REPORTPER, \ - .sampleper = (nrf_qdec_sampleper_t)NRFX_QDEC_CONFIG_SAMPLEPER, \ - .psela = NRFX_QDEC_CONFIG_PIO_A, \ - .pselb = NRFX_QDEC_CONFIG_PIO_B, \ - .pselled = NRFX_QDEC_CONFIG_PIO_LED, \ - .ledpre = NRFX_QDEC_CONFIG_LEDPRE, \ - .ledpol = (nrf_qdec_ledpol_t)NRFX_QDEC_CONFIG_LEDPOL, \ - .interrupt_priority = NRFX_QDEC_CONFIG_IRQ_PRIORITY, \ - .dbfen = NRFX_QDEC_CONFIG_DBFEN, \ - .sample_inten = NRFX_QDEC_CONFIG_SAMPLE_INTEN \ - } - -/**@brief QDEC sample event data.*/ -typedef struct -{ - int8_t value; /**< Sample value. */ -} nrfx_qdec_sample_data_evt_t; - -/**@brief QDEC report event data.*/ -typedef struct -{ - int16_t acc; /**< Accumulated transitions. */ - uint16_t accdbl; /**< Accumulated double transitions. */ -} nrfx_qdec_report_data_evt_t; - -/**@brief QDEC event handler structure. */ -typedef struct -{ - nrf_qdec_event_t type; - union - { - nrfx_qdec_sample_data_evt_t sample; /**< Sample event data. */ - nrfx_qdec_report_data_evt_t report; /**< Report event data. */ - } data; -} nrfx_qdec_event_t; - -/**@brief QDEC event handler. - * @param[in] event QDEC event structure. - */ -typedef void (*nrfx_qdec_event_handler_t)(nrfx_qdec_event_t event); - -/**@brief Function for initializing QDEC. - * - * @param[in] p_config Pointer to the structure with initial configuration. - * @param[in] event_handler Event handler provided by the user. - * Must not be NULL. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_INVALID_STATE If QDEC was already initialized. - */ -nrfx_err_t nrfx_qdec_init(nrfx_qdec_config_t const * p_config, - nrfx_qdec_event_handler_t event_handler); - -/**@brief Function for uninitializing QDEC. - * @note Function asserts if module is uninitialized. - */ -void nrfx_qdec_uninit(void); - -/**@brief Function for enabling QDEC. - * @note Function asserts if module is uninitialized or enabled. - */ -void nrfx_qdec_enable(void); - -/**@brief Function for disabling QDEC. - * @note Function asserts if module is uninitialized or disabled. - */ -void nrfx_qdec_disable(void); - -/**@brief Function for reading accumulated transitions QDEC. - * @note Function asserts if module is not enabled. - * @note Accumulators are cleared after reading. - * - * @param[out] p_acc Pointer to store accumulated transitions. - * @param[out] p_accdbl Pointer to store accumulated double transitions. - */ -void nrfx_qdec_accumulators_read(int16_t * p_acc, int16_t * p_accdbl); - -/** - * @brief Function for returning the address of a specific QDEC task. - * - * @param task QDEC task. - * - * @return Task address. - */ -__STATIC_INLINE uint32_t nrfx_qdec_task_address_get(nrf_qdec_task_t task) -{ - return (uint32_t)nrf_qdec_task_address_get(task); -} - -/** - * @brief Function for returning the address of a specific QDEC event. - * - * @param event QDEC event. - * - * @return Event address. - */ -__STATIC_INLINE uint32_t nrfx_qdec_event_address_get(nrf_qdec_event_t event) -{ - return (uint32_t)nrf_qdec_event_address_get(event); -} - - -void nrfx_qdec_irq_handler(void); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_QDEC_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_qspi.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_qspi.h deleted file mode 100644 index 4b182538d9..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_qspi.h +++ /dev/null @@ -1,297 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_QSPI_H__ -#define NRFX_QSPI_H__ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_qspi QSPI driver - * @{ - * @ingroup nrf_qspi - * @brief Quad Serial Peripheral Interface (QSPI) peripheral driver. - */ - -/** - * @brief QSPI driver instance configuration structure. - */ -typedef struct -{ - uint32_t xip_offset; /**< Address offset into the external memory for Execute in Place operation. */ - nrf_qspi_pins_t pins; /**< Pins configuration structure. */ - nrf_qspi_prot_conf_t prot_if; /**< Protocol layer interface configuration structure. */ - nrf_qspi_phy_conf_t phy_if; /**< Physical layer interface configuration structure. */ - uint8_t irq_priority; /**< Interrupt priority. */ -} nrfx_qspi_config_t; - -/** - * @brief QSPI instance default configuration. - */ -#define NRFX_QSPI_DEFAULT_CONFIG \ -{ \ - .xip_offset = NRFX_QSPI_CONFIG_XIP_OFFSET, \ - .pins = { \ - .sck_pin = NRFX_QSPI_PIN_SCK, \ - .csn_pin = NRFX_QSPI_PIN_CSN, \ - .io0_pin = NRFX_QSPI_PIN_IO0, \ - .io1_pin = NRFX_QSPI_PIN_IO1, \ - .io2_pin = NRFX_QSPI_PIN_IO2, \ - .io3_pin = NRFX_QSPI_PIN_IO3, \ - }, \ - .irq_priority = (uint8_t)NRFX_QSPI_CONFIG_IRQ_PRIORITY, \ - .prot_if = { \ - .readoc = (nrf_qspi_readoc_t)NRFX_QSPI_CONFIG_READOC, \ - .writeoc = (nrf_qspi_writeoc_t)NRFX_QSPI_CONFIG_WRITEOC, \ - .addrmode = (nrf_qspi_addrmode_t)NRFX_QSPI_CONFIG_ADDRMODE, \ - .dpmconfig = false, \ - }, \ - .phy_if = { \ - .sck_freq = (nrf_qspi_frequency_t)NRFX_QSPI_CONFIG_FREQUENCY, \ - .sck_delay = (uint8_t)NRFX_QSPI_CONFIG_SCK_DELAY, \ - .spi_mode = (nrf_qspi_spi_mode_t)NRFX_QSPI_CONFIG_MODE, \ - .dpmen = false \ - }, \ -} - -/** - * @brief QSPI custom instruction helper with default configuration. - */ -#define NRFX_QSPI_DEFAULT_CINSTR(opc, len) \ -{ \ - .opcode = (opc), \ - .length = (len), \ - .io2_level = false, \ - .io3_level = false, \ - .wipwait = false, \ - .wren = false \ -} - -/** - * @brief QSPI master driver event types, passed to the handler routine provided - * during initialization. - */ -typedef enum -{ - NRFX_QSPI_EVENT_DONE, /**< Transfer done. */ -} nrfx_qspi_evt_t; - -/** - * @brief QSPI driver event handler type. - */ -typedef void (*nrfx_qspi_handler_t)(nrfx_qspi_evt_t event, void * p_context); - -/** - * @brief Function for initializing the QSPI driver instance. - * - * This function configures the peripheral and its interrupts and activates it. During the - * activation process, the internal clocks are started and the QSPI peripheral tries to read - * the status byte to read the busy bit. Reading the status byte is done in a simple poll and wait - * mechanism. - * If the busy bit is 1, this indicates issues with the external memory device. As a result, - * @ref nrfx_qspi_init returns NRFX_ERROR_TIMEOUT. - * - * In case of issues: - * - Check the connection. - * - Make sure that the memory device does not perform other operations like erasing or writing. - * - Check if there is a short circuit. - * - * @param[in] p_config Pointer to the structure with initial configuration. - * @param[in] handler Event handler provided by the user. If NULL, transfers - * will be performed in blocking mode. - * @param[in] p_context Pointer to context. Use in interrupt handler. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_TIMEOUT If the peripheral cannot connect with external memory. - * @retval NRFX_ERROR_INVALID_STATE If the driver was already initialized. - * @retval NRFX_ERROR_INVALID_PARAM If the pin configuration was incorrect. - */ -nrfx_err_t nrfx_qspi_init(nrfx_qspi_config_t const * p_config, - nrfx_qspi_handler_t handler, - void * p_context); - -/** - * @brief Function for uninitializing the QSPI driver instance. - */ -void nrfx_qspi_uninit(void); - -/** - * @brief Function for reading data from QSPI memory. - * - * Write, read, and erase operations check memory device busy state before starting the operation. - * If the memory is busy, the resulting action depends on the mode in which the read operation is used: - * - blocking mode (without handler) - a delay occurs until the last operation still runs and - * until operation data is still being read. - * - interrupt mode (with handler) - event emission occurs after the last operation - * and reading of data are finished. - * - * @param[out] p_rx_buffer Pointer to the receive buffer. - * @param[in] rx_buffer_length Size of the data to read. - * @param[in] src_address Address in memory to read from. - * - * @retval NRFX_SUCCESS If the operation was successful (blocking mode) or operation - * was commissioned (handler mode). - * @retval NRFX_ERROR_BUSY If the driver currently handles another operation. - * @retval NRFX_ERROR_INVALID_ADDR If the provided buffer is not placed in the Data RAM region. - */ -nrfx_err_t nrfx_qspi_read(void * p_rx_buffer, - size_t rx_buffer_length, - uint32_t src_address); - -/** - * @brief Function for writing data to QSPI memory. - * - * Write, read, and erase operations check memory device busy state before starting the operation. - * If the memory is busy, the resulting action depends on the mode in which the write operation is used: - * - blocking mode (without handler) - a delay occurs until the last operation still runs and - * until operation data is still being sent. - * - interrupt mode (with handler) - event emission occurs after the last operation - * and sending of operation data are finished. - * To manually control operation execution in the memory device, use @ref nrfx_qspi_mem_busy_check - * after executing the write function. - * Remember that an incoming event signalizes only that data was sent to the memory device and the periheral - * before the write operation checked if memory was busy. - * - * @param[in] p_tx_buffer Pointer to the writing buffer. - * @param[in] tx_buffer_length Size of the data to write. - * @param[in] dst_address Address in memory to write to. - * - * @retval NRFX_SUCCESS If the operation was successful (blocking mode) or operation - * was commissioned (handler mode). - * @retval NRFX_ERROR_BUSY If the driver currently handles other operation. - * @retval NRFX_ERROR_INVALID_ADDR If the provided buffer is not placed in the Data RAM region. - */ -nrfx_err_t nrfx_qspi_write(void const * p_tx_buffer, - size_t tx_buffer_length, - uint32_t dst_address); - -/** - * @brief Function for starting erasing of one memory block - 4KB, 64KB, or the whole chip. - * - * Write, read, and erase operations check memory device busy state before starting the operation. - * If the memory is busy, the resulting action depends on the mode in which the erase operation is used: - * - blocking mode (without handler) - a delay occurs until the last operation still runs and - * until operation data is still being sent. - * - interrupt mode (with handler) - event emission occurs after the last operation - * and sending of operation data are finished. - * To manually control operation execution in the memory device, use @ref nrfx_qspi_mem_busy_check - * after executing the erase function. - * Remember that an incoming event signalizes only that data was sent to the memory device and the periheral - * before the erase operation checked if memory was busy. - * - * @param[in] length Size of data to erase. See @ref nrf_qspi_erase_len_t. - * @param[in] start_address Memory address to start erasing. If chip erase is performed, address - * field is ommited. - * - * @retval NRFX_SUCCESS If the operation was successful (blocking mode) or operation - * was commissioned (handler mode). - * @retval NRFX_ERROR_BUSY If the driver currently handles another operation. - */ -nrfx_err_t nrfx_qspi_erase(nrf_qspi_erase_len_t length, - uint32_t start_address); - -/** - * @brief Function for starting an erase operation of the whole chip. - * - * @retval NRFX_SUCCESS If the operation was successful (blocking mode) or operation - * was commissioned (handler mode). - * @retval NRFX_ERROR_BUSY If the driver currently handles another operation. - */ -nrfx_err_t nrfx_qspi_chip_erase(void); - -/** - * @brief Function for getting the current driver status and status byte of memory device with - * testing WIP (write in progress) bit. - * - * @retval NRFX_SUCCESS If the driver and memory are ready to handle a new operation. - * @retval NRFX_ERROR_BUSY If the driver or memory currently handle another operation. - */ -nrfx_err_t nrfx_qspi_mem_busy_check(void); - -/** - * @brief Function for sending operation code, sending data, and receiving data from the memory device. - * - * Use this function to transfer configuration data to memory and to receive data from memory. - * Pointers can be addresses from flash memory. - * This function is a synchronous function and should be used only if necessary. - * - * @param[in] p_config Pointer to the structure with opcode and transfer configuration. - * @param[in] p_tx_buffer Pointer to the array with data to send. Can be NULL if only opcode is transmitted. - * @param[out] p_rx_buffer Pointer to the array for data to receive. Can be NULL if there is nothing to receive. - * - * @retval NRFX_SUCCESS If the operation was successful. - * @retval NRFX_ERROR_TIMEOUT If the external memory is busy or there are connection issues. - * @retval NRFX_ERROR_BUSY If the driver currently handles other operation. - */ -nrfx_err_t nrfx_qspi_cinstr_xfer(nrf_qspi_cinstr_conf_t const * p_config, - void const * p_tx_buffer, - void * p_rx_buffer); -/** - * @brief Function for sending operation code and data to the memory device with simpler configuration. - * - * Use this function to transfer configuration data to memory and to receive data from memory. - * This function is a synchronous function and should be used only if necessary. - * - * @param[in] opcode Operation code. Sending first. - * @param[in] length Length of the data to send and opcode. See @ref nrf_qspi_cinstr_len_t. - * @param[in] p_tx_buffer Pointer to input data array. - * - * @retval NRFX_SUCCESS If the operation was successful. - * @retval NRFX_ERROR_BUSY If the driver currently handles another operation. - */ -nrfx_err_t nrfx_qspi_cinstr_quick_send(uint8_t opcode, - nrf_qspi_cinstr_len_t length, - void const * p_tx_buffer); - - -void nrfx_qspi_irq_handler(void); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_QSPI_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_rng.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_rng.h deleted file mode 100644 index 9b13ed5cd6..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_rng.h +++ /dev/null @@ -1,126 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef NRFX_RNG_H__ -#define NRFX_RNG_H__ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_rng RNG driver - * @{ - * @ingroup nrf_rng - * @brief Random Number Generator (RNG) peripheral driver. - */ - -/** - * @brief Struct for RNG configuration. - */ -typedef struct -{ - bool error_correction : 1; /**< Error correction flag. */ - uint8_t interrupt_priority; /**< interrupt priority */ -} nrfx_rng_config_t; - -/** - * @brief RNG default configuration. - * Basic usage: - * @code - * nrfx_rng_config_t config = NRFX_RNG_DEFAULT_CONFIG; - * if (nrfx_rng_init(&config, handler) - * { ... - * @endcode - */ -#define NRFX_RNG_DEFAULT_CONFIG \ - { \ - .error_correction = NRFX_RNG_CONFIG_ERROR_CORRECTION, \ - .interrupt_priority = NRFX_RNG_CONFIG_IRQ_PRIORITY, \ - } - -/** - * @brief RNG driver event handler type. - */ -typedef void (* nrfx_rng_evt_handler_t)(uint8_t rng_data); - -/** - * @brief Function for initializing the nrfx_rng module. - * - * @param[in] p_config Pointer to the structure with initial configuration. - * @param[in] handler Event handler provided by the user. Must not be NULL. - * - * @retval NRFX_SUCCESS Driver was successfully initialized. - * @retval NRFX_ERROR_ALREADY_INITIALIZED Driver was already initialized. - */ -nrfx_err_t nrfx_rng_init(nrfx_rng_config_t const * p_config, nrfx_rng_evt_handler_t handler); - -/** - * @brief Function for starting the random value generation. - * - * Function enables interrupts in perihperal and start them. - */ -void nrfx_rng_start(void); - -/** - * @brief Function for stoping the random value generation. - * - * Function disables interrupts in perihperal and stop generation of new random values. - */ -void nrfx_rng_stop(void); - -/** - * @brief Function for uninitializing the nrfx_rng module. - */ -void nrfx_rng_uninit(void); - - -void nrfx_rng_irq_handler(void); - - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_RNG_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_rtc.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_rtc.h deleted file mode 100644 index 3c5b7c990d..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_rtc.h +++ /dev/null @@ -1,369 +0,0 @@ -/** - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_RTC_H__ -#define NRFX_RTC_H__ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_rtc RTC driver - * @{ - * @ingroup nrf_rtc - * @brief Real Timer Counter (RTC) peripheral driver. - */ - -/**@brief Macro to convert microseconds into ticks. */ -#define NRFX_RTC_US_TO_TICKS(us,freq) (((us) * (freq)) / 1000000U) - -/**@brief RTC driver interrupt types. */ -typedef enum -{ - NRFX_RTC_INT_COMPARE0 = 0, /**< Interrupt from COMPARE0 event. */ - NRFX_RTC_INT_COMPARE1 = 1, /**< Interrupt from COMPARE1 event. */ - NRFX_RTC_INT_COMPARE2 = 2, /**< Interrupt from COMPARE2 event. */ - NRFX_RTC_INT_COMPARE3 = 3, /**< Interrupt from COMPARE3 event. */ - NRFX_RTC_INT_TICK = 4, /**< Interrupt from TICK event. */ - NRFX_RTC_INT_OVERFLOW = 5 /**< Interrupt from OVERFLOW event. */ -} nrfx_rtc_int_type_t; - -/**@brief RTC driver instance structure. */ -typedef struct -{ - NRF_RTC_Type * p_reg; /**< Pointer to instance register set. */ - IRQn_Type irq; /**< Instance IRQ ID. */ - uint8_t instance_id; /**< Instance index. */ - uint8_t cc_channel_count; /**< Number of capture/compare channels. */ -} nrfx_rtc_t; - -/**@brief Macro for creating RTC driver instance.*/ -#define NRFX_RTC_INSTANCE(id) \ -{ \ - .p_reg = NRFX_CONCAT_2(NRF_RTC, id), \ - .irq = NRFX_CONCAT_3(RTC, id, _IRQn), \ - .instance_id = NRFX_CONCAT_3(NRFX_RTC, id, _INST_IDX), \ - .cc_channel_count = NRF_RTC_CC_CHANNEL_COUNT(id), \ -} - -enum { -#if NRFX_CHECK(NRFX_RTC0_ENABLED) - NRFX_RTC0_INST_IDX, -#endif -#if NRFX_CHECK(NRFX_RTC1_ENABLED) - NRFX_RTC1_INST_IDX, -#endif -#if NRFX_CHECK(NRFX_RTC2_ENABLED) - NRFX_RTC2_INST_IDX, -#endif - NRFX_RTC_ENABLED_COUNT -}; - -/**@brief RTC driver instance configuration structure. */ -typedef struct -{ - uint16_t prescaler; /**< Prescaler. */ - uint8_t interrupt_priority; /**< Interrupt priority. */ - uint8_t tick_latency; /**< Maximum length of interrupt handler in ticks (max 7.7 ms). */ - bool reliable; /**< Reliable mode flag. */ -} nrfx_rtc_config_t; - -/**@brief RTC instance default configuration. */ -#define NRFX_RTC_DEFAULT_CONFIG \ -{ \ - .prescaler = RTC_FREQ_TO_PRESCALER(NRFX_RTC_DEFAULT_CONFIG_FREQUENCY), \ - .interrupt_priority = NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY, \ - .reliable = NRFX_RTC_DEFAULT_CONFIG_RELIABLE, \ - .tick_latency = NRFX_RTC_US_TO_TICKS(NRFX_RTC_MAXIMUM_LATENCY_US, \ - NRFX_RTC_DEFAULT_CONFIG_FREQUENCY), \ -} - -/**@brief RTC driver instance handler type. */ -typedef void (*nrfx_rtc_handler_t)(nrfx_rtc_int_type_t int_type); - -/**@brief Function for initializing the RTC driver instance. - * - * After initialization, the instance is in power off state. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_config Pointer to the structure with initial configuration. - * @param[in] handler Event handler provided by the user. - * Must not be NULL. - * - * @retval NRFX_SUCCESS If successfully initialized. - * @retval NRFX_ERROR_INVALID_STATE If the instance is already initialized. - */ -nrfx_err_t nrfx_rtc_init(nrfx_rtc_t const * const p_instance, - nrfx_rtc_config_t const * p_config, - nrfx_rtc_handler_t handler); - -/**@brief Function for uninitializing the RTC driver instance. - * - * After uninitialization, the instance is in idle state. The hardware should return to the state - * before initialization. The function asserts if the instance is in idle state. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_rtc_uninit(nrfx_rtc_t const * const p_instance); - -/**@brief Function for enabling the RTC driver instance. - * - * @note Function asserts if instance is enabled. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_rtc_enable(nrfx_rtc_t const * const p_instance); - -/**@brief Function for disabling the RTC driver instance. - * - * @note Function asserts if instance is disabled. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_rtc_disable(nrfx_rtc_t const * const p_instance); - -/**@brief Function for setting a compare channel. - * - * The function asserts if the instance is not initialized or if the channel parameter is - * wrong. The function powers on the instance if the instance was in power off state. - * - * The driver is not entering a critical section when configuring RTC, which means that it can be - * preempted for a certain amount of time. When the driver was preempted and the value to be set - * is short in time, there is a risk that the driver sets a compare value that is - * behind. If RTCn_CONFIG_RELIABLE is 1 for the given instance, the Reliable mode handles that case. - * However, to detect if the requested value is behind, this mode makes the following assumptions: - * - The maximum preemption time in ticks (8 - bit value) is known and is less than 7.7 ms - * (for prescaler = 0, RTC frequency 32 kHz). - * - The requested absolute compare value is not bigger than (0x00FFFFFF) - tick_latency. It is - * the user's responsibility to ensure that. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] channel One of the instance's channels. - * @param[in] val Absolute value to be set in the compare register. - * @param[in] enable_irq True to enable the interrupt. False to disable the interrupt. - * - * @retval NRFX_SUCCESS If the procedure was successful. - * @retval NRFX_ERROR_TIMEOUT If the compare was not set because the request value is behind the current counter - * value. This error can only be reported if RTCn_CONFIG_RELIABLE = 1. - */ -nrfx_err_t nrfx_rtc_cc_set(nrfx_rtc_t const * const p_instance, - uint32_t channel, - uint32_t val, - bool enable_irq); - -/**@brief Function for disabling a channel. - * - * This function disables channel events and channel interrupts. The function asserts if the instance is not - * initialized or if the channel parameter is wrong. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] channel One of the instance's channels. - * - * @retval NRFX_SUCCESS If the procedure was successful. - * @retval NRFX_ERROR_TIMEOUT If an interrupt was pending on the requested channel. - */ -nrfx_err_t nrfx_rtc_cc_disable(nrfx_rtc_t const * const p_instance, uint32_t channel); - -/**@brief Function for enabling tick. - * - * This function enables the tick event and optionally the interrupt. The function asserts if the instance is not - * powered on. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] enable_irq True to enable the interrupt. False to disable the interrupt. - */ -void nrfx_rtc_tick_enable(nrfx_rtc_t const * const p_instance, bool enable_irq); - -/**@brief Function for disabling tick. - * - * This function disables the tick event and interrupt. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_rtc_tick_disable(nrfx_rtc_t const * const p_instance); - -/**@brief Function for enabling overflow. - * - * This function enables the overflow event and optionally the interrupt. The function asserts if the instance is - * not powered on. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] enable_irq True to enable the interrupt. False to disable the interrupt. - */ -void nrfx_rtc_overflow_enable(nrfx_rtc_t const * const p_instance, bool enable_irq); - -/**@brief Function for disabling overflow. - * - * This function disables the overflow event and interrupt. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_rtc_overflow_disable(nrfx_rtc_t const * const p_instance); - -/**@brief Function for getting the maximum relative ticks value that can be set in the compare channel. - * - * When a stack (for example SoftDevice) is used and it occupies high priority interrupts, - * the application code can be interrupted at any moment for a certain period of time. - * If Reliable mode is enabled, the provided maximum latency is taken into account - * and the return value is smaller than the RTC counter resolution. - * If Reliable mode is disabled, the return value equals the counter resolution. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @retval ticks Maximum ticks value. - */ -uint32_t nrfx_rtc_max_ticks_get(nrfx_rtc_t const * const p_instance); - -/**@brief Function for disabling all instance interrupts. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_mask Pointer to the location where the mask is filled. - */ -__STATIC_INLINE void nrfx_rtc_int_disable(nrfx_rtc_t const * const p_instance, - uint32_t * p_mask); - -/**@brief Function for enabling instance interrupts. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] mask Mask of interrupts to enable. - */ -__STATIC_INLINE void nrfx_rtc_int_enable(nrfx_rtc_t const * const p_instance, uint32_t mask); - -/**@brief Function for retrieving the current counter value. - * - * This function asserts if the instance is not powered on or if p_val is NULL. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @retval value Counter value. - */ -__STATIC_INLINE uint32_t nrfx_rtc_counter_get(nrfx_rtc_t const * const p_instance); - -/**@brief Function for clearing the counter value. - * - * This function asserts if the instance is not powered on. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -__STATIC_INLINE void nrfx_rtc_counter_clear(nrfx_rtc_t const * const p_instance); - -/**@brief Function for returning a requested task address for the RTC driver instance. - * - * This function asserts if the output pointer is NULL. The task address can be used by the PPI module. - * - * @param[in] p_instance Pointer to the instance. - * @param[in] task One of the peripheral tasks. - * - * @retval Address of task register. - */ -__STATIC_INLINE uint32_t nrfx_rtc_task_address_get(nrfx_rtc_t const * const p_instance, - nrf_rtc_task_t task); - -/**@brief Function for returning a requested event address for the RTC driver instance. - * - * This function asserts if the output pointer is NULL. The event address can be used by the PPI module. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] event One of the peripheral events. - * - * @retval Address of event register. - */ -__STATIC_INLINE uint32_t nrfx_rtc_event_address_get(nrfx_rtc_t const * const p_instance, - nrf_rtc_event_t event); - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -__STATIC_INLINE void nrfx_rtc_int_disable(nrfx_rtc_t const * const p_instance, - uint32_t * p_mask) -{ - *p_mask = nrf_rtc_int_get(p_instance->p_reg); - nrf_rtc_int_disable(p_instance->p_reg, NRF_RTC_INT_TICK_MASK | - NRF_RTC_INT_OVERFLOW_MASK | - NRF_RTC_INT_COMPARE0_MASK | - NRF_RTC_INT_COMPARE1_MASK | - NRF_RTC_INT_COMPARE2_MASK | - NRF_RTC_INT_COMPARE3_MASK); -} - -__STATIC_INLINE void nrfx_rtc_int_enable(nrfx_rtc_t const * const p_instance, uint32_t mask) -{ - nrf_rtc_int_enable(p_instance->p_reg, mask); -} - -__STATIC_INLINE uint32_t nrfx_rtc_counter_get(nrfx_rtc_t const * const p_instance) -{ - return nrf_rtc_counter_get(p_instance->p_reg); -} - -__STATIC_INLINE void nrfx_rtc_counter_clear(nrfx_rtc_t const * const p_instance) -{ - nrf_rtc_task_trigger(p_instance->p_reg, NRF_RTC_TASK_CLEAR); -} - -__STATIC_INLINE uint32_t nrfx_rtc_task_address_get(nrfx_rtc_t const * const p_instance, - nrf_rtc_task_t task) -{ - return nrf_rtc_task_address_get(p_instance->p_reg, task); -} - -__STATIC_INLINE uint32_t nrfx_rtc_event_address_get(nrfx_rtc_t const * const p_instance, - nrf_rtc_event_t event) -{ - return nrf_rtc_event_address_get(p_instance->p_reg, event); -} -#endif // SUPPRESS_INLINE_IMPLEMENTATION - - -void nrfx_rtc_0_irq_handler(void); -void nrfx_rtc_1_irq_handler(void); -void nrfx_rtc_2_irq_handler(void); - - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_RTC_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_saadc.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_saadc.h deleted file mode 100644 index 3887a78725..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_saadc.h +++ /dev/null @@ -1,326 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_SAADC_H__ -#define NRFX_SAADC_H__ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_saadc SAADC driver - * @{ - * @ingroup nrf_saadc - * @brief Successive Approximation Analog-to-Digital Converter (SAADC) peripheral driver. - */ - -/** - * @brief Value that should be set as high limit to disable limit detection. - */ -#define NRFX_SAADC_LIMITH_DISABLED (2047) -/** - * @brief Value that should be set as low limit to disable limit detection. - */ -#define NRFX_SAADC_LIMITL_DISABLED (-2048) - -/** - * @brief Macro for setting @ref nrfx_saadc_config_t to default settings. - */ -#define NRFX_SAADC_DEFAULT_CONFIG \ -{ \ - .resolution = (nrf_saadc_resolution_t)NRFX_SAADC_CONFIG_RESOLUTION, \ - .oversample = (nrf_saadc_oversample_t)NRFX_SAADC_CONFIG_OVERSAMPLE, \ - .interrupt_priority = NRFX_SAADC_CONFIG_IRQ_PRIORITY, \ - .low_power_mode = NRFX_SAADC_CONFIG_LP_MODE \ -} - -/** - * @brief Macro for setting @ref nrf_saadc_channel_config_t to default settings - * in single ended mode. - * - * @param PIN_P Analog input. - */ -#define NRFX_SAADC_DEFAULT_CHANNEL_CONFIG_SE(PIN_P) \ -{ \ - .resistor_p = NRF_SAADC_RESISTOR_DISABLED, \ - .resistor_n = NRF_SAADC_RESISTOR_DISABLED, \ - .gain = NRF_SAADC_GAIN1_6, \ - .reference = NRF_SAADC_REFERENCE_INTERNAL, \ - .acq_time = NRF_SAADC_ACQTIME_10US, \ - .mode = NRF_SAADC_MODE_SINGLE_ENDED, \ - .burst = NRF_SAADC_BURST_DISABLED, \ - .pin_p = (nrf_saadc_input_t)(PIN_P), \ - .pin_n = NRF_SAADC_INPUT_DISABLED \ -} - -/** - * @brief Macro for setting @ref nrf_saadc_channel_config_t to default settings - * in differential mode. - * - * @param PIN_P Positive analog input. - * @param PIN_N Negative analog input. - */ -#define NRFX_SAADC_DEFAULT_CHANNEL_CONFIG_DIFFERENTIAL(PIN_P, PIN_N) \ -{ \ - .resistor_p = NRF_SAADC_RESISTOR_DISABLED, \ - .resistor_n = NRF_SAADC_RESISTOR_DISABLED, \ - .gain = NRF_SAADC_GAIN1_6, \ - .reference = NRF_SAADC_REFERENCE_INTERNAL, \ - .acq_time = NRF_SAADC_ACQTIME_10US, \ - .mode = NRF_SAADC_MODE_DIFFERENTIAL, \ - .pin_p = (nrf_saadc_input_t)(PIN_P), \ - .pin_n = (nrf_saadc_input_t)(PIN_N) \ -} - -/** - * @brief Analog-to-digital converter driver configuration structure. - */ -typedef struct -{ - nrf_saadc_resolution_t resolution; ///< Resolution configuration. - nrf_saadc_oversample_t oversample; ///< Oversampling configuration. - uint8_t interrupt_priority; ///< Interrupt priority. - bool low_power_mode; ///< Indicates if low power mode is active. -} nrfx_saadc_config_t; - -/** - * @brief Driver event types. - */ -typedef enum -{ - NRFX_SAADC_EVT_DONE, ///< Event generated when the buffer is filled with samples. - NRFX_SAADC_EVT_LIMIT, ///< Event generated after one of the limits is reached. - NRFX_SAADC_EVT_CALIBRATEDONE ///< Event generated when the calibration is complete. -} nrfx_saadc_evt_type_t; - -/** - * @brief Analog-to-digital converter driver done event data. - */ -typedef struct -{ - nrf_saadc_value_t * p_buffer; ///< Pointer to buffer with converted samples. - uint16_t size; ///< Number of samples in the buffer. -} nrfx_saadc_done_evt_t; - -/** - * @brief Analog-to-digital converter driver limit event data. - */ -typedef struct -{ - uint8_t channel; ///< Channel on which the limit was detected. - nrf_saadc_limit_t limit_type; ///< Type of limit detected. -} nrfx_saadc_limit_evt_t; - -/** - * @brief Analog-to-digital converter driver event structure. - */ -typedef struct -{ - nrfx_saadc_evt_type_t type; ///< Event type. - union - { - nrfx_saadc_done_evt_t done; ///< Data for @ref NRFX_SAADC_EVT_DONE event. - nrfx_saadc_limit_evt_t limit; ///< Data for @ref NRFX_SAADC_EVT_LIMIT event. - } data; -} nrfx_saadc_evt_t; - -/** - * @brief ADC event handler. - * - * @param[in] p_event Pointer to an ADC event. The event structure is allocated on - * the stack, so it is valid only within the context of - * the event handler. - */ -typedef void (* nrfx_saadc_event_handler_t)(nrfx_saadc_evt_t const * p_event); - -/** - * @brief Function for initializing the SAADC. - * - * @param[in] p_config Pointer to the structure with initial configuration. - * @param[in] event_handler Event handler provided by the user. - * Must not be NULL. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_INVALID_STATE If the driver is already initialized. - */ -nrfx_err_t nrfx_saadc_init(nrfx_saadc_config_t const * p_config, - nrfx_saadc_event_handler_t event_handler); - -/** - * @brief Function for uninitializing the SAADC. - * - * This function stops all ongoing conversions and disables all channels. - */ -void nrfx_saadc_uninit(void); - - -/** - * @brief Function for getting the address of a SAMPLE SAADC task. - * - * @return Task address. - */ -uint32_t nrfx_saadc_sample_task_get(void); - -/** - * @brief Function for initializing an SAADC channel. - * - * This function configures and enables the channel. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_INVALID_STATE If the ADC was not initialized. - * @retval NRFX_ERROR_NO_MEM If the specified channel was already allocated. - */ -nrfx_err_t nrfx_saadc_channel_init(uint8_t channel, - nrf_saadc_channel_config_t const * const p_config); - - -/** - * @brief Function for uninitializing an SAADC channel. - * - * @retval NRFX_SUCCESS If uninitialization was successful. - * @retval NRFX_ERROR_BUSY If the ADC is busy. - */ -nrfx_err_t nrfx_saadc_channel_uninit(uint8_t channel); - -/** - * @brief Function for starting SAADC sampling. - * - * @retval NRFX_SUCCESS If ADC sampling was triggered. - * @retval NRFX_ERROR_INVALID_STATE If ADC is in idle state. - */ -nrfx_err_t nrfx_saadc_sample(void); - -/** - * @brief Blocking function for executing a single ADC conversion. - * - * This function selects the desired input, starts a single conversion, - * waits for it to finish, and returns the result. - * - * The function will fail if ADC is busy. - * - * @param[in] channel Channel. - * @param[out] p_value Pointer to the location where the result should be placed. - * - * @retval NRFX_SUCCESS If conversion was successful. - * @retval NRFX_ERROR_BUSY If the ADC driver is busy. - */ -nrfx_err_t nrfx_saadc_sample_convert(uint8_t channel, nrf_saadc_value_t * p_value); - -/** - * @brief Function for issuing conversion of data to the buffer. - * - * This function is non-blocking. The application is notified about filling the buffer by the event - * handler. Conversion will be done on all enabled channels. If the ADC is in idle state, the - * function will set up Easy DMA for the conversion. The ADC will be ready for sampling and wait for - * the SAMPLE task. It can be triggered manually by the @ref nrfx_saadc_sample function or by PPI - * using the @ref NRF_SAADC_TASK_SAMPLE task. If one buffer is already set and the conversion is - * ongoing, calling this function will result in queuing the given buffer. The driver will start - * filling the issued buffer when the first one is completed. If the function is called again before - * the first buffer is filled or calibration is in progress, it will return with error. - * - * @param[in] buffer Result buffer. - * @param[in] size Buffer size in words. - * - * @retval NRFX_SUCCESS If conversion was successful. - * @retval NRFX_ERROR_BUSY If the driver already has two buffers set or calibration is in progress. - */ -nrfx_err_t nrfx_saadc_buffer_convert(nrf_saadc_value_t * buffer, uint16_t size); - -/** - * @brief Function for triggering the ADC offset calibration. - * - * This function is non-blocking. The application is notified about completion by the event handler. - * Calibration will also trigger DONE and RESULTDONE events. - * - * The function will fail if ADC is busy or calibration is already in progress. - * - * @retval NRFX_SUCCESS If calibration was started successfully. - * @retval NRFX_ERROR_BUSY If the ADC driver is busy. - */ -nrfx_err_t nrfx_saadc_calibrate_offset(void); - -/** - * @brief Function for retrieving the SAADC state. - * - * @retval true If the ADC is busy. - * @retval false If the ADC is ready. - */ -bool nrfx_saadc_is_busy(void); - -/** - * @brief Function for aborting ongoing and buffered conversions. - * @note @ref NRFX_SAADC_EVT_DONE event will be generated if there is a conversion in progress. - * Event will contain number of words in the sample buffer. - */ -void nrfx_saadc_abort(void); - -/** - * @brief Function for setting the SAADC channel limits. - * When limits are enabled and the result exceeds the defined bounds, the limit handler - * function is called. - * - * @param[in] channel SAADC channel number. - * @param[in] limit_low Lower limit (valid values from @ref NRFX_SAADC_LIMITL_DISABLED to - * @ref NRFX_SAADC_LIMITH_DISABLED). Conversion results below this value will - * trigger the handler function. Set to @ref NRFX_SAADC_LIMITL_DISABLED - * to disable this limit. - * @param[in] limit_high Upper limit (valid values from @ref NRFX_SAADC_LIMITL_DISABLED to - * @ref NRFX_SAADC_LIMITH_DISABLED). Conversion results above this value will - * trigger the handler function. Set to @ref NRFX_SAADC_LIMITH_DISABLED - * to disable this limit. - */ -void nrfx_saadc_limits_set(uint8_t channel, int16_t limit_low, int16_t limit_high); - - -void nrfx_saadc_irq_handler(void); - - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_SAADC_H__ - diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_spi.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_spi.h deleted file mode 100644 index 24f4de87c2..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_spi.h +++ /dev/null @@ -1,273 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_SPI_H__ -#define NRFX_SPI_H__ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_spi SPI driver - * @{ - * @ingroup nrf_spi - * @brief SPI peripheral driver. - */ - -/** - * @brief SPI master driver instance data structure. - */ -typedef struct -{ - NRF_SPI_Type * p_reg; ///< Pointer to a structure with SPI registers. - uint8_t drv_inst_idx; ///< Driver instance index. -} nrfx_spi_t; - -enum { -#if NRFX_CHECK(NRFX_SPI0_ENABLED) - NRFX_SPI0_INST_IDX, -#endif -#if NRFX_CHECK(NRFX_SPI1_ENABLED) - NRFX_SPI1_INST_IDX, -#endif -#if NRFX_CHECK(NRFX_SPI2_ENABLED) - NRFX_SPI2_INST_IDX, -#endif - NRFX_SPI_ENABLED_COUNT -}; - -/** - * @brief Macro for creating an SPI master driver instance. - */ -#define NRFX_SPI_INSTANCE(id) \ -{ \ - .p_reg = NRFX_CONCAT_2(NRF_SPI, id), \ - .drv_inst_idx = NRFX_CONCAT_3(NRFX_SPI, id, _INST_IDX), \ -} - -/** - * @brief This value can be provided instead of a pin number for signals MOSI, - * MISO, and Slave Select to specify that the given signal is not used and - * therefore does not need to be connected to a pin. - */ -#define NRFX_SPI_PIN_NOT_USED 0xFF - -/** - * @brief SPI master driver instance configuration structure. - */ -typedef struct -{ - uint8_t sck_pin; ///< SCK pin number. - uint8_t mosi_pin; ///< MOSI pin number (optional). - /**< Set to @ref NRFX_SPI_PIN_NOT_USED - * if this signal is not needed. */ - uint8_t miso_pin; ///< MISO pin number (optional). - /**< Set to @ref NRFX_SPI_PIN_NOT_USED - * if this signal is not needed. */ - uint8_t ss_pin; ///< Slave Select pin number (optional). - /**< Set to @ref NRFX_SPI_PIN_NOT_USED - * if this signal is not needed. The driver - * supports only active low for this signal. - * If the signal should be active high, - * it must be controlled externally. */ - uint8_t irq_priority; ///< Interrupt priority. - uint8_t orc; ///< Over-run character. - /**< This character is used when all bytes from the TX buffer are sent, - but the transfer continues due to RX. */ - nrf_spi_frequency_t frequency; ///< SPI frequency. - nrf_spi_mode_t mode; ///< SPI mode. - nrf_spi_bit_order_t bit_order; ///< SPI bit order. -} nrfx_spi_config_t; - -/** - * @brief SPI master instance default configuration. - */ -#define NRFX_SPI_DEFAULT_CONFIG \ -{ \ - .sck_pin = NRFX_SPI_PIN_NOT_USED, \ - .mosi_pin = NRFX_SPI_PIN_NOT_USED, \ - .miso_pin = NRFX_SPI_PIN_NOT_USED, \ - .ss_pin = NRFX_SPI_PIN_NOT_USED, \ - .irq_priority = NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY, \ - .orc = 0xFF, \ - .frequency = NRF_SPI_FREQ_4M, \ - .mode = NRF_SPI_MODE_0, \ - .bit_order = NRF_SPI_BIT_ORDER_MSB_FIRST, \ -} - -/** - * @brief Single transfer descriptor structure. - */ -typedef struct -{ - uint8_t const * p_tx_buffer; ///< Pointer to TX buffer. - size_t tx_length; ///< TX buffer length. - uint8_t * p_rx_buffer; ///< Pointer to RX buffer. - size_t rx_length; ///< RX buffer length. -} nrfx_spi_xfer_desc_t; - -/** - * @brief Macro for setting up single transfer descriptor. - * - * This macro is for internal use only. - */ -#define NRFX_SPI_SINGLE_XFER(p_tx, tx_len, p_rx, rx_len) \ - { \ - .p_tx_buffer = (uint8_t const *)(p_tx), \ - .tx_length = (tx_len), \ - .p_rx_buffer = (p_rx), \ - .rx_length = (rx_len), \ - } - -/** - * @brief Macro for setting duplex TX RX transfer. - */ -#define NRFX_SPI_XFER_TRX(p_tx_buf, tx_length, p_rx_buf, rx_length) \ - NRFX_SPI_SINGLE_XFER(p_tx_buf, tx_length, p_rx_buf, rx_length) - -/** - * @brief Macro for setting TX transfer. - */ -#define NRFX_SPI_XFER_TX(p_buf, length) \ - NRFX_SPI_SINGLE_XFER(p_buf, length, NULL, 0) - -/** - * @brief Macro for setting RX transfer. - */ -#define NRFX_SPI_XFER_RX(p_buf, length) \ - NRFX_SPI_SINGLE_XFER(NULL, 0, p_buf, length) - -/** - * @brief SPI master driver event types, passed to the handler routine provided - * during initialization. - */ -typedef enum -{ - NRFX_SPI_EVENT_DONE, ///< Transfer done. -} nrfx_spi_evt_type_t; - -typedef struct -{ - nrfx_spi_evt_type_t type; ///< Event type. - nrfx_spi_xfer_desc_t xfer_desc; ///< Transfer details. -} nrfx_spi_evt_t; - -/** - * @brief SPI master driver event handler type. - */ -typedef void (* nrfx_spi_evt_handler_t)(nrfx_spi_evt_t const * p_event, - void * p_context); - -/** - * @brief Function for initializing the SPI master driver instance. - * - * This function configures and enables the specified peripheral. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_config Pointer to the structure with initial configuration. - * - * @param handler Event handler provided by the user. If NULL, transfers - * will be performed in blocking mode. - * @param p_context Context passed to event handler. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_INVALID_STATE If the driver was already initialized. - * @retval NRFX_ERROR_BUSY If some other peripheral with the same - * instance ID is already in use. This is - * possible only if @ref nrfx_prs module - * is enabled. - */ -nrfx_err_t nrfx_spi_init(nrfx_spi_t const * const p_instance, - nrfx_spi_config_t const * p_config, - nrfx_spi_evt_handler_t handler, - void * p_context); - -/** - * @brief Function for uninitializing the SPI master driver instance. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_spi_uninit(nrfx_spi_t const * const p_instance); - -/** - * @brief Function for starting the SPI data transfer. - * - * If an event handler was provided in the @ref nrfx_spi_init call, this function - * returns immediately and the handler is called when the transfer is done. - * Otherwise, the transfer is performed in blocking mode, which means that this function - * returns when the transfer is finished. - * - * @param p_instance Pointer to the driver instance structure. - * @param p_xfer_desc Pointer to the transfer descriptor. - * @param flags Transfer options (0 for default settings). - * Currently, no additional flags are available. - * - * @retval NRFX_SUCCESS If the procedure was successful. - * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer. - * @retval NRFX_ERROR_NOT_SUPPORTED If the provided parameters are not supported. - */ -nrfx_err_t nrfx_spi_xfer(nrfx_spi_t const * const p_instance, - nrfx_spi_xfer_desc_t const * p_xfer_desc, - uint32_t flags); - -/** - * @brief Function for aborting ongoing transfer. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_spi_abort(nrfx_spi_t const * p_instance); - - -void nrfx_spi_0_irq_handler(void); -void nrfx_spi_1_irq_handler(void); -void nrfx_spi_2_irq_handler(void); - - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_SPI_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_spim.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_spim.h deleted file mode 100644 index 8eaccb7c6c..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_spim.h +++ /dev/null @@ -1,396 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_SPIM_H__ -#define NRFX_SPIM_H__ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_spim SPIM driver - * @{ - * @ingroup nrf_spim - * @brief SPIM peripheral driver. - */ - -/** - * @brief SPIM master driver instance data structure. - */ -typedef struct -{ - NRF_SPIM_Type * p_reg; ///< Pointer to a structure with SPIM registers. - uint8_t drv_inst_idx; ///< Driver instance index. -} nrfx_spim_t; - -enum { -#if NRFX_CHECK(NRFX_SPIM0_ENABLED) - NRFX_SPIM0_INST_IDX, -#endif -#if NRFX_CHECK(NRFX_SPIM1_ENABLED) - NRFX_SPIM1_INST_IDX, -#endif -#if NRFX_CHECK(NRFX_SPIM2_ENABLED) - NRFX_SPIM2_INST_IDX, -#endif -#if NRFX_CHECK(NRFX_SPIM3_ENABLED) - NRFX_SPIM3_INST_IDX, -#endif - NRFX_SPIM_ENABLED_COUNT -}; - -/** - * @brief Macro for creating an SPIM master driver instance. - */ -#define NRFX_SPIM_INSTANCE(id) \ -{ \ - .p_reg = NRFX_CONCAT_2(NRF_SPIM, id), \ - .drv_inst_idx = NRFX_CONCAT_3(NRFX_SPIM, id, _INST_IDX), \ -} - -/** - * @brief This value can be provided instead of a pin number for signals MOSI, - * MISO, and Slave Select to specify that the given signal is not used and - * therefore does not need to be connected to a pin. - */ -#define NRFX_SPIM_PIN_NOT_USED 0xFF - -/** - * @brief SPIM master driver instance configuration structure. - */ -typedef struct -{ - uint8_t sck_pin; ///< SCK pin number. - uint8_t mosi_pin; ///< MOSI pin number (optional). - /**< Set to @ref NRFX_SPIM_PIN_NOT_USED - * if this signal is not needed. */ - uint8_t miso_pin; ///< MISO pin number (optional). - /**< Set to @ref NRFX_SPIM_PIN_NOT_USED - * if this signal is not needed. */ - uint8_t ss_pin; ///< Slave Select pin number (optional). - /**< Set to @ref NRFX_SPIM_PIN_NOT_USED - * if this signal is not needed. */ - bool ss_active_high; ///< Polarity of the Slave Select pin during transmission. - uint8_t irq_priority; ///< Interrupt priority. - uint8_t orc; ///< Over-run character. - /**< This character is used when all bytes from the TX buffer are sent, - but the transfer continues due to RX. */ - nrf_spim_frequency_t frequency; ///< SPI frequency. - nrf_spim_mode_t mode; ///< SPI mode. - nrf_spim_bit_order_t bit_order; ///< SPI bit order. -#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) || defined(__NRFX_DOXYGEN__) - uint8_t dcx_pin; ///< D/CX pin number (optional). - uint8_t rx_delay; ///< Sample delay for input serial data on MISO. - /**< The value specifies the delay, in number of 64 MHz clock cycles - * (15.625 ns), from the the sampling edge of SCK (leading edge for - * CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until - * the input serial data is sampled.*/ - bool use_hw_ss; ///< Indication to use software or hardware controlled Slave Select pin. - uint8_t ss_duration; ///< Slave Select duration before and after transmission. - /**< Minimum duration between the edge of CSN and the edge of SCK and minimum - * duration of CSN must stay inactive between transactions. - * The value is specified in number of 64 MHz clock cycles (15.625 ns). - * Supported only for hardware controlled Slave Select.*/ -#endif -} nrfx_spim_config_t; - -#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) || defined(__NRFX_DOXYGEN__) -/** - * @brief SPIM master instance extended default configuration. - */ - #define NRFX_SPIM_DEFAULT_EXTENDED_CONFIG \ - .dcx_pin = NRFX_SPIM_PIN_NOT_USED, \ - .rx_delay = 0x00, \ - .ss_duration = 0x00, \ - .use_hw_ss = false, -#else - #define NRFX_SPIM_DEFAULT_EXTENDED_CONFIG -#endif - -/** - * @brief SPIM master instance default configuration. - */ -#define NRFX_SPIM_DEFAULT_CONFIG \ -{ \ - .sck_pin = NRFX_SPIM_PIN_NOT_USED, \ - .mosi_pin = NRFX_SPIM_PIN_NOT_USED, \ - .miso_pin = NRFX_SPIM_PIN_NOT_USED, \ - .ss_pin = NRFX_SPIM_PIN_NOT_USED, \ - .ss_active_high = false, \ - .irq_priority = NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY, \ - .orc = 0xFF, \ - .frequency = NRF_SPIM_FREQ_4M, \ - .mode = NRF_SPIM_MODE_0, \ - .bit_order = NRF_SPIM_BIT_ORDER_MSB_FIRST, \ - NRFX_SPIM_DEFAULT_EXTENDED_CONFIG \ -} - -#define NRFX_SPIM_FLAG_TX_POSTINC (1UL << 0) /**< TX buffer address incremented after transfer. */ -#define NRFX_SPIM_FLAG_RX_POSTINC (1UL << 1) /**< RX buffer address incremented after transfer. */ -#define NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER (1UL << 2) /**< Interrupt after each transfer is suppressed, and the event handler is not called. */ -#define NRFX_SPIM_FLAG_HOLD_XFER (1UL << 3) /**< Set up the transfer but do not start it. */ -#define NRFX_SPIM_FLAG_REPEATED_XFER (1UL << 4) /**< Flag indicating that the transfer will be executed multiple times. */ - -/** - * @brief Single transfer descriptor structure. - */ -typedef struct -{ - uint8_t const * p_tx_buffer; ///< Pointer to TX buffer. - size_t tx_length; ///< TX buffer length. - uint8_t * p_rx_buffer; ///< Pointer to RX buffer. - size_t rx_length; ///< RX buffer length. -} nrfx_spim_xfer_desc_t; - -/** - * @brief Macro for setting up single transfer descriptor. - * - * This macro is for internal use only. - */ -#define NRFX_SPIM_SINGLE_XFER(p_tx, tx_len, p_rx, rx_len) \ - { \ - .p_tx_buffer = (uint8_t const *)(p_tx), \ - .tx_length = (tx_len), \ - .p_rx_buffer = (p_rx), \ - .rx_length = (rx_len), \ - } - -/** - * @brief Macro for setting duplex TX RX transfer. - */ -#define NRFX_SPIM_XFER_TRX(p_tx_buf, tx_length, p_rx_buf, rx_length) \ - NRFX_SPIM_SINGLE_XFER(p_tx_buf, tx_length, p_rx_buf, rx_length) - -/** - * @brief Macro for setting TX transfer. - */ -#define NRFX_SPIM_XFER_TX(p_buf, length) \ - NRFX_SPIM_SINGLE_XFER(p_buf, length, NULL, 0) - -/** - * @brief Macro for setting RX transfer. - */ -#define NRFX_SPIM_XFER_RX(p_buf, length) \ - NRFX_SPIM_SINGLE_XFER(NULL, 0, p_buf, length) - -/** - * @brief SPIM master driver event types, passed to the handler routine provided - * during initialization. - */ -typedef enum -{ - NRFX_SPIM_EVENT_DONE, ///< Transfer done. -} nrfx_spim_evt_type_t; - -typedef struct -{ - nrfx_spim_evt_type_t type; ///< Event type. - nrfx_spim_xfer_desc_t xfer_desc; ///< Transfer details. -} nrfx_spim_evt_t; - -/** - * @brief SPIM master driver event handler type. - */ -typedef void (* nrfx_spim_evt_handler_t)(nrfx_spim_evt_t const * p_event, - void * p_context); - -/** - * @brief Function for initializing the SPI master driver instance. - * - * This function configures and enables the specified peripheral. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_config Pointer to the structure with initial configuration. - * - * @param handler Event handler provided by the user. If NULL, transfers - * will be performed in blocking mode. - * @param p_context Context passed to event handler. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_INVALID_STATE If the driver was already initialized. - * @retval NRFX_ERROR_BUSY If some other peripheral with the same - * instance ID is already in use. This is - * possible only if @ref nrfx_prs module - * is enabled. - * @retval NRFX_ERROR_NOT_SUPPORTED If requested configuration is not supported - * by the SPIM instance. - */ -nrfx_err_t nrfx_spim_init(nrfx_spim_t const * const p_instance, - nrfx_spim_config_t const * p_config, - nrfx_spim_evt_handler_t handler, - void * p_context); - -/** - * @brief Function for uninitializing the SPI master driver instance. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_spim_uninit(nrfx_spim_t const * const p_instance); - -/** - * @brief Function for starting the SPI data transfer. - * - * Additional options are provided using the @c flags parameter: - * - * - @ref NRFX_SPIM_FLAG_TX_POSTINC and @ref NRFX_SPIM_FLAG_RX_POSTINC: - * Post-incrementation of buffer addresses. Supported only by SPIM. - * - @ref NRFX_SPIM_FLAG_HOLD_XFER: Driver is not starting the transfer. Use this - * flag if the transfer is triggered externally by PPI. Supported only by SPIM. Use - * @ref nrfx_spim_start_task_get to get the address of the start task. - * - @ref NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER: No user event handler after transfer - * completion. This also means no interrupt at the end of the transfer. Supported only by SPIM. - * If @ref NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER is used, the driver does not set the instance into - * busy state, so you must ensure that the next transfers are set up when SPIM is not active. - * @ref nrfx_spim_end_event_get function can be used to detect end of transfer. Option can be used - * together with @ref NRFX_SPIM_FLAG_REPEATED_XFER to prepare a sequence of SPI transfers - * without interruptions. - * - @ref NRFX_SPIM_FLAG_REPEATED_XFER: Prepare for repeated transfers. You can set - * up a number of transfers that will be triggered externally (for example by PPI). An example is - * a TXRX transfer with the options @ref NRFX_SPIM_FLAG_RX_POSTINC, - * @ref NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER, and @ref NRFX_SPIM_FLAG_REPEATED_XFER. After the - * transfer is set up, a set of transfers can be triggered by PPI that will read, for example, - * the same register of an external component and put it into a RAM buffer without any interrupts. - * @ref nrfx_spim_end_event_get can be used to get the address of the END event, which can be - * used to count the number of transfers. If @ref NRFX_SPIM_FLAG_REPEATED_XFER is used, - * the driver does not set the instance into busy state, so you must ensure that the next - * transfers are set up when SPIM is not active. Supported only by SPIM. - * - * @note Peripherals using EasyDMA (including SPIM) require the transfer buffers - * to be placed in the Data RAM region. If this condition is not met, - * this function will fail with the error code NRFX_ERROR_INVALID_ADDR. - * - * @param p_instance Pointer to the driver instance structure. - * @param p_xfer_desc Pointer to the transfer descriptor. - * @param flags Transfer options (0 for default settings). - * - * @retval NRFX_SUCCESS If the procedure was successful. - * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer. - * @retval NRFX_ERROR_NOT_SUPPORTED If the provided parameters are not supported. - * @retval NRFX_ERROR_INVALID_ADDR If the provided buffers are not placed in the Data - * RAM region. - */ -nrfx_err_t nrfx_spim_xfer(nrfx_spim_t const * const p_instance, - nrfx_spim_xfer_desc_t const * p_xfer_desc, - uint32_t flags); - -#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) || defined(__NRFX_DOXYGEN__) -/** - * @brief Function for starting the SPI data transfer with DCX control. - * - * See @ref nrfx_spim_xfer for description of additional options of transfer - * provided by the @c flags parameter. - * - * @note Peripherals that use EasyDMA (including SPIM) require the transfer buffers - * to be placed in the Data RAM region. If this condition is not met, - * this function will fail with the error code NRFX_ERROR_INVALID_ADDR. - * - * @param p_instance Pointer to the driver instance structure. - * @param p_xfer_desc Pointer to the transfer descriptor. - * @param flags Transfer options (0 for default settings). - * @param cmd_length Length of the command bytes preceding the data - * bytes. The DCX line will be low during transmission - * of command bytes and high during transmission of data bytes. - * Maximum value available for dividing the transmitted bytes - * into command bytes and data bytes is @ref NRF_SPIM_DCX_CNT_ALL_CMD - 1. - * The @ref NRF_SPIM_DCX_CNT_ALL_CMD value passed as the - * @c cmd_length parameter causes all transmitted bytes - * to be marked as command bytes. - * - * @retval NRFX_SUCCESS If the procedure was successful. - * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer. - * @retval NRFX_ERROR_NOT_SUPPORTED If the provided parameters are not supported. - * @retval NRFX_ERROR_INVALID_ADDR If the provided buffers are not placed in the Data - * RAM region. - */ -nrfx_err_t nrfx_spim_xfer_dcx(nrfx_spim_t const * const p_instance, - nrfx_spim_xfer_desc_t const * p_xfer_desc, - uint32_t flags, - uint8_t cmd_length); -#endif - -/** - * @brief Function for returning the address of a SPIM start task. - * - * This function should be used if @ref nrfx_spim_xfer was called with the flag @ref NRFX_SPIM_FLAG_HOLD_XFER. - * In that case, the transfer is not started by the driver, but it must be started externally by PPI. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @return Start task address. - */ -uint32_t nrfx_spim_start_task_get(nrfx_spim_t const * p_instance); - -/** - * @brief Function for returning the address of a END SPIM event. - * - * The END event can be used to detect the end of a transfer - * if the @ref NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER option is used. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @return END event address. - */ -uint32_t nrfx_spim_end_event_get(nrfx_spim_t const * p_instance); - -/** - * @brief Function for aborting ongoing transfer. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_spim_abort(nrfx_spim_t const * p_instance); - - -void nrfx_spim_0_irq_handler(void); -void nrfx_spim_1_irq_handler(void); -void nrfx_spim_2_irq_handler(void); -void nrfx_spim_3_irq_handler(void); - - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_SPIM_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_spis.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_spis.h deleted file mode 100644 index cb32c4d19c..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_spis.h +++ /dev/null @@ -1,250 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_SPIS_H__ -#define NRFX_SPIS_H__ - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_spis SPI slave driver - * @{ - * @ingroup nrf_spis - * @brief SPI Slave peripheral driver. - */ - -/** @brief SPI slave driver instance data structure. */ -typedef struct -{ - NRF_SPIS_Type * p_reg; //!< Pointer to a structure with SPIS registers. - uint8_t drv_inst_idx; //!< Driver instance index. -} nrfx_spis_t; - -enum { -#if NRFX_CHECK(NRFX_SPIS0_ENABLED) - NRFX_SPIS0_INST_IDX, -#endif -#if NRFX_CHECK(NRFX_SPIS1_ENABLED) - NRFX_SPIS1_INST_IDX, -#endif -#if NRFX_CHECK(NRFX_SPIS2_ENABLED) - NRFX_SPIS2_INST_IDX, -#endif - NRFX_SPIS_ENABLED_COUNT -}; - -/** @brief Macro for creating an SPI slave driver instance. */ -#define NRFX_SPIS_INSTANCE(id) \ -{ \ - .p_reg = NRFX_CONCAT_2(NRF_SPIS, id), \ - .drv_inst_idx = NRFX_CONCAT_3(NRFX_SPIS, id, _INST_IDX), \ -} - -/** - * @brief This value can be provided instead of a pin number for the signals MOSI - * and MISO to specify that the given signal is not used and therefore - * does not need to be connected to a pin. - */ -#define NRFX_SPIS_PIN_NOT_USED 0xFF - -/** @brief Default pull-up configuration of the SPI CS. */ -#define NRFX_SPIS_DEFAULT_CSN_PULLUP NRF_GPIO_PIN_NOPULL -/** @brief Default drive configuration of the SPI MISO. */ -#define NRFX_SPIS_DEFAULT_MISO_DRIVE NRF_GPIO_PIN_S0S1 - -/** @brief SPI slave driver event types. */ -typedef enum -{ - NRFX_SPIS_BUFFERS_SET_DONE, //!< Memory buffer set event. Memory buffers have been set successfully to the SPI slave device, and SPI transaction can be done. - NRFX_SPIS_XFER_DONE, //!< SPI transaction event. SPI transaction has been completed. - NRFX_SPIS_EVT_TYPE_MAX //!< Enumeration upper bound. -} nrfx_spis_evt_type_t; - -/** @brief SPI slave driver event structure. */ -typedef struct -{ - nrfx_spis_evt_type_t evt_type; //!< Type of the event. - size_t rx_amount; //!< Number of bytes received in the last transaction. This parameter is only valid for @ref NRFX_SPIS_XFER_DONE events. - size_t tx_amount; //!< Number of bytes transmitted in the last transaction. This parameter is only valid for @ref NRFX_SPIS_XFER_DONE events. -} nrfx_spis_evt_t; - -/** @brief SPI slave instance default configuration. */ -#define NRFX_SPIS_DEFAULT_CONFIG \ -{ \ - .sck_pin = NRFX_SPIS_PIN_NOT_USED, \ - .mosi_pin = NRFX_SPIS_PIN_NOT_USED, \ - .miso_pin = NRFX_SPIS_PIN_NOT_USED, \ - .csn_pin = NRFX_SPIS_PIN_NOT_USED, \ - .mode = NRF_SPIS_MODE_0, \ - .bit_order = NRF_SPIS_BIT_ORDER_MSB_FIRST, \ - .csn_pullup = NRFX_SPIS_DEFAULT_CSN_PULLUP, \ - .miso_drive = NRFX_SPIS_DEFAULT_MISO_DRIVE, \ - .def = NRFX_SPIS_DEFAULT_DEF, \ - .orc = NRFX_SPIS_DEFAULT_ORC, \ - .irq_priority = NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY, \ -} - -/** @brief SPI peripheral device configuration data. */ -typedef struct -{ - uint32_t miso_pin; //!< SPI MISO pin (optional). - /**< Set @ref NRFX_SPIS_PIN_NOT_USED - * if this signal is not needed. */ - uint32_t mosi_pin; //!< SPI MOSI pin (optional). - /**< Set @ref NRFX_SPIS_PIN_NOT_USED - * if this signal is not needed. */ - uint32_t sck_pin; //!< SPI SCK pin. - uint32_t csn_pin; //!< SPI CSN pin. - nrf_spis_mode_t mode; //!< SPI mode. - nrf_spis_bit_order_t bit_order; //!< SPI transaction bit order. - nrf_gpio_pin_pull_t csn_pullup; //!< CSN pin pull-up configuration. - nrf_gpio_pin_drive_t miso_drive; //!< MISO pin drive configuration. - uint8_t def; //!< Character clocked out in case of an ignored transaction. - uint8_t orc; //!< Character clocked out after an over-read of the transmit buffer. - uint8_t irq_priority; //!< Interrupt priority. -} nrfx_spis_config_t; - - -/** - * @brief SPI slave driver event handler type. - * - * @param[in] p_event Pointer to the event structure. The structure is - * allocated on the stack so it is valid only until - * the event handler returns. - * @param[in] p_context Context set on initialization. - */ -typedef void (*nrfx_spis_event_handler_t)(nrfx_spis_evt_t const * p_event, - void * p_context); - -/** - * @brief Function for initializing the SPI slave driver instance. - * - * @note When the nRF52 Anomaly 109 workaround for SPIS is enabled, this function - * initializes the GPIOTE driver as well, and uses one of GPIOTE channels - * to detect falling edges on CSN pin. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_config Pointer to the structure with initial configuration. - * @param[in] event_handler Function to be called by the SPI slave driver upon event. - * Must not be NULL. - * @param[in] p_context Context passed to the event handler. - * - * @retval NRFX_SUCCESS If the initialization was successful. - * @retval NRFX_ERROR_INVALID_STATE If the instance is already initialized. - * @retval NRFX_ERROR_INVALID_PARAM If an invalid parameter is supplied. - * @retval NRFX_ERROR_BUSY If some other peripheral with the same - * instance ID is already in use. This is - * possible only if @ref nrfx_prs module - * is enabled. - * @retval NRFX_ERROR_INTERNAL GPIOTE channel for detecting falling edges - * on CSN pin cannot be initialized. Possible - * only when using nRF52 Anomaly 109 workaround. - */ -nrfx_err_t nrfx_spis_init(nrfx_spis_t const * const p_instance, - nrfx_spis_config_t const * p_config, - nrfx_spis_event_handler_t event_handler, - void * p_context); - -/** - * @brief Function for uninitializing the SPI slave driver instance. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_spis_uninit(nrfx_spis_t const * const p_instance); - -/** - * @brief Function for preparing the SPI slave instance for a single SPI transaction. - * - * This function prepares the SPI slave device to be ready for a single SPI transaction. It configures - * the SPI slave device to use the memory supplied with the function call in SPI transactions. - * - * When either the memory buffer configuration or the SPI transaction has been - * completed, the event callback function will be called with the appropriate event - * @ref nrfx_spis_evt_type_t. Note that the callback function can be called before returning from - * this function, because it is called from the SPI slave interrupt context. - * - * @note This function can be called from the callback function context. - * - * @note Client applications must call this function after every @ref NRFX_SPIS_XFER_DONE event if - * the SPI slave driver should be prepared for a possible new SPI transaction. - * - * @note Peripherals using EasyDMA (including SPIS) require the transfer buffers - * to be placed in the Data RAM region. If this condition is not met, - * this function will fail with the error code NRFX_ERROR_INVALID_ADDR. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_tx_buffer Pointer to the TX buffer. Can be NULL when the buffer length is zero. - * @param[in] p_rx_buffer Pointer to the RX buffer. Can be NULL when the buffer length is zero. - * @param[in] tx_buffer_length Length of the TX buffer in bytes. - * @param[in] rx_buffer_length Length of the RX buffer in bytes. - * - * @retval NRFX_SUCCESS If the operation was successful. - * @retval NRFX_ERROR_INVALID_STATE If the operation failed because the SPI slave device is in an incorrect state. - * @retval NRFX_ERROR_INVALID_ADDR If the provided buffers are not placed in the Data - * RAM region. - * @retval NRFX_ERROR_INVALID_LENGTH If provided lengths exceed the EasyDMA limits for the peripheral. - * @retval NRFX_ERROR_INTERNAL If the operation failed because of an internal error. - */ -nrfx_err_t nrfx_spis_buffers_set(nrfx_spis_t const * const p_instance, - uint8_t const * p_tx_buffer, - size_t tx_buffer_length, - uint8_t * p_rx_buffer, - size_t rx_buffer_length); - - -void nrfx_spis_0_irq_handler(void); -void nrfx_spis_1_irq_handler(void); -void nrfx_spis_2_irq_handler(void); - - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_SPIS_H__ - diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_swi.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_swi.h deleted file mode 100644 index 6671b9f454..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_swi.h +++ /dev/null @@ -1,222 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_SWI_H__ -#define NRFX_SWI_H__ - -#include - -#if NRFX_CHECK(NRFX_EGU_ENABLED) -#include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_swi SWI driver - * @{ - * @ingroup nrf_swi_egu - * - * @brief Driver for managing software interrupts (SWI). - */ - -/** @brief SWI instance. */ -typedef uint8_t nrfx_swi_t; - -/** - * @brief SWI user flags. - * - * User flags are set during the SWI trigger and passed to the callback function as an argument. - */ -typedef uint16_t nrfx_swi_flags_t; - -/** @brief Unallocated instance value. */ -#define NRFX_SWI_UNALLOCATED ((nrfx_swi_t)0xFFuL) - -/** @brief Default SWI priority. */ -#define NRFX_SWI_DEFAULT_PRIORITY APP_IRQ_PRIORITY_LOWEST - -/** - * @brief SWI handler function. - * - * @param swi SWI instance. - * @param flags User flags. - */ -typedef void (*nrfx_swi_handler_t)(nrfx_swi_t swi, nrfx_swi_flags_t flags); - - -/** - * @brief Function for allocating the first unused SWI instance and setting a handler. - * - * @param[out] p_swi Points to a place where the allocated SWI instance - * number is to be stored. - * @param[in] event_handler Event handler function. - * If NULL, no interrupt will be enabled. - * It can be NULL only if the EGU driver is enabled. - * For classic SWI, it must be a valid handler pointer. - * @param[in] irq_priority Interrupt priority. - * - * @retval NRFX_SUCCESS If the SWI was successfully allocated. - * @retval NRFX_ERROR_NO_MEM If there is no available SWI to be used. - */ -nrfx_err_t nrfx_swi_alloc(nrfx_swi_t * p_swi, - nrfx_swi_handler_t event_handler, - uint32_t irq_priority); - -/** - * @brief Function for freeing a previously allocated SWI. - * - * @param[in,out] p_swi SWI instance to free. The value is changed to - * @ref NRFX_SWI_UNALLOCATED on success. - */ -void nrfx_swi_free(nrfx_swi_t * p_swi); - -/** @brief Function for freeing all allocated SWIs. */ -void nrfx_swi_all_free(void); - -/** - * @brief Function for triggering the SWI. - * - * @param[in] swi SWI to trigger. - * @param[in] flag_number Number of user flag to trigger. - */ -void nrfx_swi_trigger(nrfx_swi_t swi, - uint8_t flag_number); - -/** - * @brief Function for checking if the specified SWI is currently allocated. - * - * @param[in] swi SWI instance. - * - * @retval true If the SWI instance is allocated. - * @retval false Otherwise. - */ -bool nrfx_swi_is_allocated(nrfx_swi_t swi); - -#if NRFX_CHECK(NRFX_EGU_ENABLED) || defined(__NRFX_DOXYGEN__) - -/** - * @brief Function for returning the base address of the EGU peripheral - * associated with the specified SWI instance. - * - * @param[in] swi SWI instance. - * - * @returns EGU base address or NULL if the specified SWI instance number - * is too high. - */ -__STATIC_INLINE NRF_EGU_Type * nrfx_swi_egu_instance_get(nrfx_swi_t swi) -{ -#if (EGU_COUNT < SWI_COUNT) - if (swi >= EGU_COUNT) - { - return NULL; - } -#endif - uint32_t offset = ((uint32_t)swi) * (NRF_EGU1_BASE - NRF_EGU0_BASE); - return (NRF_EGU_Type *)(NRF_EGU0_BASE + offset); -} - -/** - * @brief Function for returning the EGU trigger task address. - * - * @param[in] swi SWI instance. - * @param[in] channel Number of the EGU channel. - * - * @returns Address of EGU trigger task. - */ -__STATIC_INLINE uint32_t nrfx_swi_task_trigger_address_get(nrfx_swi_t swi, - uint8_t channel) -{ - NRFX_ASSERT(nrfx_swi_is_allocated(swi)); - - NRF_EGU_Type * p_egu = nrfx_swi_egu_instance_get(swi); -#if (EGU_COUNT < SWI_COUNT) - if (p_egu == NULL) - { - return 0; - } -#endif - - return (uint32_t)nrf_egu_task_trigger_address_get(p_egu, channel); -} - -/** - * @brief Function for returning the EGU triggered event address. - * - * @param[in] swi SWI instance. - * @param[in] channel Number of the EGU channel. - * - * @returns Address of EGU triggered event. - */ -__STATIC_INLINE uint32_t nrfx_swi_event_triggered_address_get(nrfx_swi_t swi, - uint8_t channel) -{ - NRFX_ASSERT(nrfx_swi_is_allocated(swi)); - - NRF_EGU_Type * p_egu = nrfx_swi_egu_instance_get(swi); -#if (EGU_COUNT < SWI_COUNT) - if (p_egu == NULL) - { - return 0; - } -#endif - - return (uint32_t)nrf_egu_event_triggered_address_get(p_egu, channel); -} - -#endif // NRFX_CHECK(NRFX_EGU_ENABLED) || defined(__NRFX_DOXYGEN__) - - -void nrfx_swi_0_irq_handler(void); -void nrfx_swi_1_irq_handler(void); -void nrfx_swi_2_irq_handler(void); -void nrfx_swi_3_irq_handler(void); -void nrfx_swi_4_irq_handler(void); -void nrfx_swi_5_irq_handler(void); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_SWI_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_systick.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_systick.h deleted file mode 100644 index 8f766717ad..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_systick.h +++ /dev/null @@ -1,135 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_SYSTICK_H__ -#define NRFX_SYSTICK_H__ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_systick ARM(R) SysTick driver - * @{ - * @ingroup nrf_systick - * - * @brief ARM(R) SysTick driver. - * - * This driver configures ARM(R) SysTick as a free-running timer. - * This timer is used to generate delays and pool for timeouts. - * Only relatively short timeouts are supported. - * The SysTick works on 64MHz and is 24-bits wide. - * It means that it overflows around 4 times per second and around 250 ms - * would be the highest supported time in the library. - * But it would be really hard to detect if overflow was generated without - * using interrupts. For safety we would limit the maximum delay range by half. - */ - -/** - * @brief The value type that holds the SysTick state - * - * This variable is used to count the requested timeout. - * @sa nrfx_systick_get - */ -typedef struct { - uint32_t time; //!< Registered time value -} nrfx_systick_state_t; - -/** - * @brief Configure and start the timer - * - * Function configures SysTick as a free-running timer without interrupt. - */ -void nrfx_systick_init(void); - -/** - * @brief Get current SysTick state - * - * Function gets current state of the SysTick timer. - * It can be used to check time-out by @ref nrfx_systick_test. - * - * @param[out] p_state The pointer to the state variable to be filled - */ -void nrfx_systick_get(nrfx_systick_state_t * p_state); - -/** - * @brief Test if specified time is up in relation to remembered state - * - * @param[in] p_state Remembered state set by @ref nrfx_systick_get - * @param[in] us Required time-out. - * - * @retval true If current time is higher than specified state plus given time-out. - * @retval false If current time is lower than specified state plus given time-out - */ -bool nrfx_systick_test(nrfx_systick_state_t const * p_state, uint32_t us); - -/** - * @brief Blocking delay in CPU ticks - * - * @param[in] ticks Number of CPU ticks to delay. - */ -void nrfx_systick_delay_ticks(uint32_t ticks); - -/** - * @brief Blocking delay in us - * - * @param[in] us Number of microseconds to delay. - */ -void nrfx_systick_delay_us(uint32_t us); - -/** - * @brief Blocking delay in ms - * - * This delay function removes the limits of the highest possible delay value. - * - * @param[in] ms Number of milliseconds to delay. - */ -void nrfx_systick_delay_ms(uint32_t ms); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* NRFX_SYSTICK_H__ */ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_timer.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_timer.h deleted file mode 100644 index e5a2630855..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_timer.h +++ /dev/null @@ -1,413 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_TIMER_H__ -#define NRFX_TIMER_H__ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_timer Timer driver - * @{ - * @ingroup nrf_timer - * @brief TIMER peripheral driver. - */ - -/** - * @brief Timer driver instance data structure. - */ -typedef struct -{ - NRF_TIMER_Type * p_reg; ///< Pointer to the structure with TIMER peripheral instance registers. - uint8_t instance_id; ///< Driver instance index. - uint8_t cc_channel_count; ///< Number of capture/compare channels. -} nrfx_timer_t; - -/** - * @brief Macro for creating a timer driver instance. - */ -#define NRFX_TIMER_INSTANCE(id) \ -{ \ - .p_reg = NRFX_CONCAT_2(NRF_TIMER, id), \ - .instance_id = NRFX_CONCAT_3(NRFX_TIMER, id, _INST_IDX), \ - .cc_channel_count = NRF_TIMER_CC_CHANNEL_COUNT(id), \ -} - -enum { -#if NRFX_CHECK(NRFX_TIMER0_ENABLED) - NRFX_TIMER0_INST_IDX, -#endif -#if NRFX_CHECK(NRFX_TIMER1_ENABLED) - NRFX_TIMER1_INST_IDX, -#endif -#if NRFX_CHECK(NRFX_TIMER2_ENABLED) - NRFX_TIMER2_INST_IDX, -#endif -#if NRFX_CHECK(NRFX_TIMER3_ENABLED) - NRFX_TIMER3_INST_IDX, -#endif -#if NRFX_CHECK(NRFX_TIMER4_ENABLED) - NRFX_TIMER4_INST_IDX, -#endif - NRFX_TIMER_ENABLED_COUNT -}; - -/** - * @brief Timer driver instance configuration structure. - */ -typedef struct -{ - nrf_timer_frequency_t frequency; ///< Frequency. - nrf_timer_mode_t mode; ///< Mode of operation. - nrf_timer_bit_width_t bit_width; ///< Bit width. - uint8_t interrupt_priority; ///< Interrupt priority. - void * p_context; ///< Context passed to interrupt handler. -} nrfx_timer_config_t; - -/** - * @brief Timer driver instance default configuration. - */ -#define NRFX_TIMER_DEFAULT_CONFIG \ -{ \ - .frequency = (nrf_timer_frequency_t)NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY,\ - .mode = (nrf_timer_mode_t)NRFX_TIMER_DEFAULT_CONFIG_MODE, \ - .bit_width = (nrf_timer_bit_width_t)NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH,\ - .interrupt_priority = NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY, \ - .p_context = NULL \ -} - -/** - * @brief Timer driver event handler type. - * - * @param[in] event_type Timer event. - * @param[in] p_context General purpose parameter set during initialization of - * the timer. This parameter can be used to pass - * additional information to the handler function, for - * example, the timer ID. - */ -typedef void (* nrfx_timer_event_handler_t)(nrf_timer_event_t event_type, - void * p_context); - -/** - * @brief Function for initializing the timer. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_config Pointer to the structure with initial configuration. - * @param[in] timer_event_handler Event handler provided by the user. - * Must not be NULL. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_INVALID_STATE If the instance is already initialized. - */ -nrfx_err_t nrfx_timer_init(nrfx_timer_t const * const p_instance, - nrfx_timer_config_t const * p_config, - nrfx_timer_event_handler_t timer_event_handler); - -/** - * @brief Function for uninitializing the timer. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_timer_uninit(nrfx_timer_t const * const p_instance); - -/** - * @brief Function for turning on the timer. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_timer_enable(nrfx_timer_t const * const p_instance); - -/** - * @brief Function for turning off the timer. - * - * Note that the timer will allow to enter the lowest possible SYSTEM_ON state - * only after this function is called. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_timer_disable(nrfx_timer_t const * const p_instance); - -/** - * @brief Function for checking the timer state. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @return True if timer is enabled, false otherwise. - */ -bool nrfx_timer_is_enabled(nrfx_timer_t const * const p_instance); - -/** - * @brief Function for pausing the timer. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_timer_pause(nrfx_timer_t const * const p_instance); - -/** - * @brief Function for resuming the timer. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_timer_resume(nrfx_timer_t const * const p_instance); - -/** - * @brief Function for clearing the timer. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_timer_clear(nrfx_timer_t const * const p_instance); - -/** - * @brief Function for incrementing the timer. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_timer_increment(nrfx_timer_t const * const p_instance); - -/** - * @brief Function for returning the address of a specific timer task. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] timer_task Timer task. - * - * @return Task address. - */ -__STATIC_INLINE uint32_t nrfx_timer_task_address_get(nrfx_timer_t const * const p_instance, - nrf_timer_task_t timer_task); - -/** - * @brief Function for returning the address of a specific timer capture task. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] channel Capture channel number. - * - * @return Task address. - */ -__STATIC_INLINE uint32_t nrfx_timer_capture_task_address_get(nrfx_timer_t const * const p_instance, - uint32_t channel); - -/** - * @brief Function for returning the address of a specific timer event. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] timer_event Timer event. - * - * @return Event address. - */ -__STATIC_INLINE uint32_t nrfx_timer_event_address_get(nrfx_timer_t const * const p_instance, - nrf_timer_event_t timer_event); - -/** - * @brief Function for returning the address of a specific timer compare event. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] channel Compare channel number. - * - * @return Event address. - */ -__STATIC_INLINE uint32_t nrfx_timer_compare_event_address_get(nrfx_timer_t const * const p_instance, - uint32_t channel); - -/** - * @brief Function for capturing the timer value. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] cc_channel Capture channel number. - * - * @return Captured value. - */ -uint32_t nrfx_timer_capture(nrfx_timer_t const * const p_instance, - nrf_timer_cc_channel_t cc_channel); - -/** - * @brief Function for returning the capture value from a specific channel. - * - * Use this function to read channel values when PPI is used for capturing. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] cc_channel Capture channel number. - * - * @return Captured value. - */ -__STATIC_INLINE uint32_t nrfx_timer_capture_get(nrfx_timer_t const * const p_instance, - nrf_timer_cc_channel_t cc_channel); - -/** - * @brief Function for setting the timer channel in compare mode. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] cc_channel Compare channel number. - * @param[in] cc_value Compare value. - * @param[in] enable_int Enable or disable the interrupt for the compare channel. - */ -void nrfx_timer_compare(nrfx_timer_t const * const p_instance, - nrf_timer_cc_channel_t cc_channel, - uint32_t cc_value, - bool enable_int); - -/** - * @brief Function for setting the timer channel in extended compare mode. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] cc_channel Compare channel number. - * @param[in] cc_value Compare value. - * @param[in] timer_short_mask Shortcut between the compare event on the channel - * and the timer task (STOP or CLEAR). - * @param[in] enable_int Enable or disable the interrupt for the compare - * channel. - */ -void nrfx_timer_extended_compare(nrfx_timer_t const * const p_instance, - nrf_timer_cc_channel_t cc_channel, - uint32_t cc_value, - nrf_timer_short_mask_t timer_short_mask, - bool enable_int); - -/** - * @brief Function for converting time in microseconds to timer ticks. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] time_us Time in microseconds. - * - * @return Number of ticks. - */ -__STATIC_INLINE uint32_t nrfx_timer_us_to_ticks(nrfx_timer_t const * const p_instance, - uint32_t time_us); - -/** - * @brief Function for converting time in milliseconds to timer ticks. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] time_ms Time in milliseconds. - * - * @return Number of ticks. - */ -__STATIC_INLINE uint32_t nrfx_timer_ms_to_ticks(nrfx_timer_t const * const p_instance, - uint32_t time_ms); - -/** - * @brief Function for enabling timer compare interrupt. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] channel Compare channel. - */ -void nrfx_timer_compare_int_enable(nrfx_timer_t const * const p_instance, - uint32_t channel); - -/** - * @brief Function for disabling timer compare interrupt. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] channel Compare channel. - */ -void nrfx_timer_compare_int_disable(nrfx_timer_t const * const p_instance, - uint32_t channel); - - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -__STATIC_INLINE uint32_t nrfx_timer_task_address_get(nrfx_timer_t const * const p_instance, - nrf_timer_task_t timer_task) -{ - return (uint32_t)nrf_timer_task_address_get(p_instance->p_reg, timer_task); -} - -__STATIC_INLINE uint32_t nrfx_timer_capture_task_address_get(nrfx_timer_t const * const p_instance, - uint32_t channel) -{ - NRFX_ASSERT(channel < p_instance->cc_channel_count); - return (uint32_t)nrf_timer_task_address_get(p_instance->p_reg, - nrf_timer_capture_task_get(channel)); -} - -__STATIC_INLINE uint32_t nrfx_timer_event_address_get(nrfx_timer_t const * const p_instance, - nrf_timer_event_t timer_event) -{ - return (uint32_t)nrf_timer_event_address_get(p_instance->p_reg, timer_event); -} - -__STATIC_INLINE uint32_t nrfx_timer_compare_event_address_get(nrfx_timer_t const * const p_instance, - uint32_t channel) -{ - NRFX_ASSERT(channel < p_instance->cc_channel_count); - return (uint32_t)nrf_timer_event_address_get(p_instance->p_reg, - nrf_timer_compare_event_get(channel)); -} - -__STATIC_INLINE uint32_t nrfx_timer_capture_get(nrfx_timer_t const * const p_instance, - nrf_timer_cc_channel_t cc_channel) -{ - return nrf_timer_cc_read(p_instance->p_reg, cc_channel); -} - -__STATIC_INLINE uint32_t nrfx_timer_us_to_ticks(nrfx_timer_t const * const p_instance, - uint32_t timer_us) -{ - return nrf_timer_us_to_ticks(timer_us, nrf_timer_frequency_get(p_instance->p_reg)); -} - -__STATIC_INLINE uint32_t nrfx_timer_ms_to_ticks(nrfx_timer_t const * const p_instance, - uint32_t timer_ms) -{ - return nrf_timer_ms_to_ticks(timer_ms, nrf_timer_frequency_get(p_instance->p_reg)); -} - -#endif // SUPPRESS_INLINE_IMPLEMENTATION - - -void nrfx_timer_0_irq_handler(void); -void nrfx_timer_1_irq_handler(void); -void nrfx_timer_2_irq_handler(void); -void nrfx_timer_3_irq_handler(void); -void nrfx_timer_4_irq_handler(void); - - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_TIMER_H__ - diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_twi.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_twi.h deleted file mode 100644 index 8d27e26bfc..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_twi.h +++ /dev/null @@ -1,368 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_TWI_H__ -#define NRFX_TWI_H__ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_twi TWI driver - * @{ - * @ingroup nrf_twi - * @brief TWI peripheral driver. - */ - -/** - * @brief Structure for the TWI master driver instance. - */ -typedef struct -{ - NRF_TWI_Type * p_twi; ///< Pointer to a structure with TWI registers. - uint8_t drv_inst_idx; ///< Driver instance index. -} nrfx_twi_t; - -/** - * @brief Macro for creating a TWI master driver instance. - */ -#define NRFX_TWI_INSTANCE(id) \ -{ \ - .p_twi = NRFX_CONCAT_2(NRF_TWI, id), \ - .drv_inst_idx = NRFX_CONCAT_3(NRFX_TWI, id, _INST_IDX), \ -} - -enum { -#if NRFX_CHECK(NRFX_TWI0_ENABLED) - NRFX_TWI0_INST_IDX, -#endif -#if NRFX_CHECK(NRFX_TWI1_ENABLED) - NRFX_TWI1_INST_IDX, -#endif - NRFX_TWI_ENABLED_COUNT -}; - -/** - * @brief Structure for the TWI master driver instance configuration. - */ -typedef struct -{ - uint32_t scl; ///< SCL pin number. - uint32_t sda; ///< SDA pin number. - nrf_twi_frequency_t frequency; ///< TWI frequency. - uint8_t interrupt_priority; ///< Interrupt priority. - bool hold_bus_uninit; ///< Hold pull up state on gpio pins after uninit. -} nrfx_twi_config_t; - -/** - * @brief TWI master driver instance default configuration. - */ -#define NRFX_TWI_DEFAULT_CONFIG \ -{ \ - .frequency = (nrf_twi_frequency_t)NRFX_TWI_DEFAULT_CONFIG_FREQUENCY, \ - .scl = 31, \ - .sda = 31, \ - .interrupt_priority = NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY, \ - .hold_bus_uninit = NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT, \ -} - -#define NRFX_TWI_FLAG_NO_XFER_EVT_HANDLER (1UL << 2) /**< Interrupt after each transfer is suppressed, and the event handler is not called. */ -#define NRFX_TWI_FLAG_TX_NO_STOP (1UL << 5) /**< Flag indicating that the TX transfer will not end with a stop condition. */ - -/** - * @brief TWI master driver event types. - */ -typedef enum -{ - NRFX_TWI_EVT_DONE, ///< Transfer completed event. - NRFX_TWI_EVT_ADDRESS_NACK, ///< Error event: NACK received after sending the address. - NRFX_TWI_EVT_DATA_NACK ///< Error event: NACK received after sending a data byte. -} nrfx_twi_evt_type_t; - -/** - * @brief TWI master driver transfer types. - */ -typedef enum -{ - NRFX_TWI_XFER_TX, ///< TX transfer. - NRFX_TWI_XFER_RX, ///< RX transfer. - NRFX_TWI_XFER_TXRX, ///< TX transfer followed by RX transfer with repeated start. - NRFX_TWI_XFER_TXTX ///< TX transfer followed by TX transfer with repeated start. -} nrfx_twi_xfer_type_t; - -/** - * @brief Structure for a TWI transfer descriptor. - */ -typedef struct -{ - nrfx_twi_xfer_type_t type; ///< Type of transfer. - uint8_t address; ///< Slave address. - size_t primary_length; ///< Number of bytes transferred. - size_t secondary_length; ///< Number of bytes transferred. - uint8_t * p_primary_buf; ///< Pointer to transferred data. - uint8_t * p_secondary_buf; ///< Pointer to transferred data. -} nrfx_twi_xfer_desc_t; - - -/**@brief Macro for setting the TX transfer descriptor. */ -#define NRFX_TWI_XFER_DESC_TX(addr, p_data, length) \ - { \ - .type = NRFX_TWI_XFER_TX, \ - .address = addr, \ - .primary_length = length, \ - .p_primary_buf = p_data, \ - } - -/**@brief Macro for setting the RX transfer descriptor. */ -#define NRFX_TWI_XFER_DESC_RX(addr, p_data, length) \ - { \ - .type = NRFX_TWI_XFER_RX, \ - .address = addr, \ - .primary_length = length, \ - .p_primary_buf = p_data, \ - } - -/**@brief Macro for setting the TXRX transfer descriptor. */ -#define NRFX_TWI_XFER_DESC_TXRX(addr, p_tx, tx_len, p_rx, rx_len) \ - { \ - .type = NRFX_TWI_XFER_TXRX, \ - .address = addr, \ - .primary_length = tx_len, \ - .secondary_length = rx_len, \ - .p_primary_buf = p_tx, \ - .p_secondary_buf = p_rx, \ - } - -/**@brief Macro for setting the TXTX transfer descriptor. */ -#define NRFX_TWI_XFER_DESC_TXTX(addr, p_tx, tx_len, p_tx2, tx_len2) \ - { \ - .type = NRFX_TWI_XFER_TXTX, \ - .address = addr, \ - .primary_length = tx_len, \ - .secondary_length = tx_len2, \ - .p_primary_buf = p_tx, \ - .p_secondary_buf = p_tx2, \ - } - -/** - * @brief Structure for a TWI event. - */ -typedef struct -{ - nrfx_twi_evt_type_t type; ///< Event type. - nrfx_twi_xfer_desc_t xfer_desc; ///< Transfer details. -} nrfx_twi_evt_t; - -/** - * @brief TWI event handler prototype. - */ -typedef void (* nrfx_twi_evt_handler_t)(nrfx_twi_evt_t const * p_event, - void * p_context); - -/** - * @brief Function for initializing the TWI driver instance. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_config Pointer to the structure with initial configuration. - * @param[in] event_handler Event handler provided by the user. If NULL, blocking mode is enabled. - * @param[in] p_context Context passed to event handler. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_INVALID_STATE If the driver is in invalid state. - * @retval NRFX_ERROR_BUSY If some other peripheral with the same - * instance ID is already in use. This is - * possible only if @ref nrfx_prs module - * is enabled. - */ -nrfx_err_t nrfx_twi_init(nrfx_twi_t const * p_instance, - nrfx_twi_config_t const * p_config, - nrfx_twi_evt_handler_t event_handler, - void * p_context); - -/** - * @brief Function for uninitializing the TWI instance. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_twi_uninit(nrfx_twi_t const * p_instance); - -/** - * @brief Function for enabling the TWI instance. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_twi_enable(nrfx_twi_t const * p_instance); - -/** - * @brief Function for disabling the TWI instance. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_twi_disable(nrfx_twi_t const * p_instance); - -/** - * @brief Function for sending data to a TWI slave. - * - * The transmission will be stopped when an error occurs. If a transfer is ongoing, - * the function returns the error code @ref NRFX_ERROR_BUSY. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] address Address of a specific slave device (only 7 LSB). - * @param[in] p_data Pointer to a transmit buffer. - * @param[in] length Number of bytes to send. - * @param[in] no_stop If set, the stop condition is not generated on the bus - * after the transfer has completed successfully (allowing - * for a repeated start in the next transfer). - * - * @retval NRFX_SUCCESS If the procedure was successful. - * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer. - * @retval NRFX_ERROR_INTERNAL If an error was detected by hardware. - * @retval NRFX_ERROR_DRV_TWI_ERR_ANACK If NACK received after sending the address in polling mode. - * @retval NRFX_ERROR_DRV_TWI_ERR_DNACK If NACK received after sending a data byte in polling mode. - */ -nrfx_err_t nrfx_twi_tx(nrfx_twi_t const * p_instance, - uint8_t address, - uint8_t const * p_data, - size_t length, - bool no_stop); - -/** - * @brief Function for reading data from a TWI slave. - * - * The transmission will be stopped when an error occurs. If a transfer is ongoing, - * the function returns the error code @ref NRFX_ERROR_BUSY. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] address Address of a specific slave device (only 7 LSB). - * @param[in] p_data Pointer to a receive buffer. - * @param[in] length Number of bytes to be received. - * - * @retval NRFX_SUCCESS If the procedure was successful. - * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer. - * @retval NRFX_ERROR_INTERNAL If an error was detected by hardware. - * @retval NRFX_ERROR_DRV_TWI_ERR_OVERRUN If the unread data was replaced by new data - * @retval NRFX_ERROR_DRV_TWI_ERR_ANACK If NACK received after sending the address in polling mode. - * @retval NRFX_ERROR_DRV_TWI_ERR_DNACK If NACK received after sending a data byte in polling mode. - */ -nrfx_err_t nrfx_twi_rx(nrfx_twi_t const * p_instance, - uint8_t address, - uint8_t * p_data, - size_t length); - -/** - * @brief Function for preparing a TWI transfer. - * - * The following transfer types can be configured (@ref nrfx_twi_xfer_desc_t::type): - * - @ref NRFX_TWI_XFER_TXRX: Write operation followed by a read operation (without STOP condition in between). - * - @ref NRFX_TWI_XFER_TXTX: Write operation followed by a write operation (without STOP condition in between). - * - @ref NRFX_TWI_XFER_TX: Write operation (with or without STOP condition). - * - @ref NRFX_TWI_XFER_RX: Read operation (with STOP condition). - * - * @note TXRX and TXTX transfers are supported only in non-blocking mode. - * - * Additional options are provided using the flags parameter: - * - @ref NRFX_TWI_FLAG_NO_XFER_EVT_HANDLER: No user event handler after transfer completion. In most cases, this also means no interrupt at the end of the transfer. - * - @ref NRFX_TWI_FLAG_TX_NO_STOP: No stop condition after TX transfer. - * - * @note - * Some flag combinations are invalid: - * - @ref NRFX_TWI_FLAG_TX_NO_STOP with @ref nrfx_twi_xfer_desc_t::type different than @ref NRFX_TWI_XFER_TX - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_xfer_desc Pointer to the transfer descriptor. - * @param[in] flags Transfer options (0 for default settings). - * - * @retval NRFX_SUCCESS If the procedure was successful. - * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer. - * @retval NRFX_ERROR_NOT_SUPPORTED If the provided parameters are not supported. - * @retval NRFX_ERROR_INTERNAL If an error was detected by hardware. - * @retval NRFX_ERROR_DRV_TWI_ERR_OVERRUN If the unread data was replaced by new data (TXRX and RX) - * @retval NRFX_ERROR_DRV_TWI_ERR_ANACK If NACK received after sending the address. - * @retval NRFX_ERROR_DRV_TWI_ERR_DNACK If NACK received after sending a data byte. - */ -nrfx_err_t nrfx_twi_xfer(nrfx_twi_t const * p_instance, - nrfx_twi_xfer_desc_t const * p_xfer_desc, - uint32_t flags); - -/** - * @brief Function for checking the TWI driver state. - * - * @param[in] p_instance TWI instance. - * - * @retval true If the TWI driver is currently busy performing a transfer. - * @retval false If the TWI driver is ready for a new transfer. - */ -bool nrfx_twi_is_busy(nrfx_twi_t const * p_instance); - -/** - * @brief Function for getting the transferred data count. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @return Data count. - */ -size_t nrfx_twi_data_count_get(nrfx_twi_t const * const p_instance); - -/** - * @brief Function for returning the address of a STOPPED TWI event. - * - * A STOPPED event can be used to detect the end of a transfer if the @ref NRFX_TWI_FLAG_NO_XFER_EVT_HANDLER - * option is used. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @return STOPPED event address. - */ -uint32_t nrfx_twi_stopped_event_get(nrfx_twi_t const * p_instance); - -void nrfx_twi_0_irq_handler(void); -void nrfx_twi_1_irq_handler(void); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_TWI_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_twim.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_twim.h deleted file mode 100644 index 309e6656f1..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_twim.h +++ /dev/null @@ -1,408 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_TWIM_H__ -#define NRFX_TWIM_H__ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_twim TWIM driver - * @{ - * @ingroup nrf_twim - * @brief TWIM peripheral driver. - */ - -/** - * @brief Structure for the TWI master driver instance. - */ -typedef struct -{ - NRF_TWIM_Type * p_twim; ///< Pointer to a structure with TWIM registers. - uint8_t drv_inst_idx; ///< Driver instance index. -} nrfx_twim_t; - -/** - * @brief Macro for creating a TWI master driver instance. - */ -#define NRFX_TWIM_INSTANCE(id) \ -{ \ - .p_twim = NRFX_CONCAT_2(NRF_TWIM, id), \ - .drv_inst_idx = NRFX_CONCAT_3(NRFX_TWIM, id, _INST_IDX), \ -} - -enum { -#if NRFX_CHECK(NRFX_TWIM0_ENABLED) - NRFX_TWIM0_INST_IDX, -#endif -#if NRFX_CHECK(NRFX_TWIM1_ENABLED) - NRFX_TWIM1_INST_IDX, -#endif - NRFX_TWIM_ENABLED_COUNT -}; - -/** - * @brief Structure for the TWI master driver instance configuration. - */ -typedef struct -{ - uint32_t scl; ///< SCL pin number. - uint32_t sda; ///< SDA pin number. - nrf_twim_frequency_t frequency; ///< TWIM frequency. - uint8_t interrupt_priority; ///< Interrupt priority. - bool hold_bus_uninit; ///< Hold pull up state on gpio pins after uninit. -} nrfx_twim_config_t; - -/** - * @brief TWI master driver instance default configuration. - */ -#define NRFX_TWIM_DEFAULT_CONFIG \ -{ \ - .frequency = (nrf_twim_frequency_t)NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY, \ - .scl = 31, \ - .sda = 31, \ - .interrupt_priority = NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY, \ - .hold_bus_uninit = NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT, \ -} - -#define NRFX_TWIM_FLAG_TX_POSTINC (1UL << 0) /**< TX buffer address incremented after transfer. */ -#define NRFX_TWIM_FLAG_RX_POSTINC (1UL << 1) /**< RX buffer address incremented after transfer. */ -#define NRFX_TWIM_FLAG_NO_XFER_EVT_HANDLER (1UL << 2) /**< Interrupt after each transfer is suppressed, and the event handler is not called. */ -#define NRFX_TWIM_FLAG_HOLD_XFER (1UL << 3) /**< Set up the transfer but do not start it. */ -#define NRFX_TWIM_FLAG_REPEATED_XFER (1UL << 4) /**< Flag indicating that the transfer will be executed multiple times. */ -#define NRFX_TWIM_FLAG_TX_NO_STOP (1UL << 5) /**< Flag indicating that the TX transfer will not end with a stop condition. */ - -/** - * @brief TWI master driver event types. - */ -typedef enum -{ - NRFX_TWIM_EVT_DONE, ///< Transfer completed event. - NRFX_TWIM_EVT_ADDRESS_NACK, ///< Error event: NACK received after sending the address. - NRFX_TWIM_EVT_DATA_NACK ///< Error event: NACK received after sending a data byte. -} nrfx_twim_evt_type_t; - -/** - * @brief TWI master driver transfer types. - */ -typedef enum -{ - NRFX_TWIM_XFER_TX, ///< TX transfer. - NRFX_TWIM_XFER_RX, ///< RX transfer. - NRFX_TWIM_XFER_TXRX, ///< TX transfer followed by RX transfer with repeated start. - NRFX_TWIM_XFER_TXTX ///< TX transfer followed by TX transfer with repeated start. -} nrfx_twim_xfer_type_t; - -/** - * @brief Structure for a TWI transfer descriptor. - */ -typedef struct -{ - nrfx_twim_xfer_type_t type; ///< Type of transfer. - uint8_t address; ///< Slave address. - size_t primary_length; ///< Number of bytes transferred. - size_t secondary_length; ///< Number of bytes transferred. - uint8_t * p_primary_buf; ///< Pointer to transferred data. - uint8_t * p_secondary_buf; ///< Pointer to transferred data. -} nrfx_twim_xfer_desc_t; - - -/**@brief Macro for setting the TX transfer descriptor. */ -#define NRFX_TWIM_XFER_DESC_TX(addr, p_data, length) \ - { \ - .type = NRFX_TWIM_XFER_TX, \ - .address = addr, \ - .primary_length = length, \ - .p_primary_buf = p_data, \ - } - -/**@brief Macro for setting the RX transfer descriptor. */ -#define NRFX_TWIM_XFER_DESC_RX(addr, p_data, length) \ - { \ - .type = NRFX_TWIM_XFER_RX, \ - .address = addr, \ - .primary_length = length, \ - .p_primary_buf = p_data, \ - } - -/**@brief Macro for setting the TXRX transfer descriptor. */ -#define NRFX_TWIM_XFER_DESC_TXRX(addr, p_tx, tx_len, p_rx, rx_len) \ - { \ - .type = NRFX_TWIM_XFER_TXRX, \ - .address = addr, \ - .primary_length = tx_len, \ - .secondary_length = rx_len, \ - .p_primary_buf = p_tx, \ - .p_secondary_buf = p_rx, \ - } - -/**@brief Macro for setting the TXTX transfer descriptor. */ -#define NRFX_TWIM_XFER_DESC_TXTX(addr, p_tx, tx_len, p_tx2, tx_len2) \ - { \ - .type = NRFX_TWIM_XFER_TXTX, \ - .address = addr, \ - .primary_length = tx_len, \ - .secondary_length = tx_len2, \ - .p_primary_buf = p_tx, \ - .p_secondary_buf = p_tx2, \ - } - -/** - * @brief Structure for a TWI event. - */ -typedef struct -{ - nrfx_twim_evt_type_t type; ///< Event type. - nrfx_twim_xfer_desc_t xfer_desc; ///< Transfer details. -} nrfx_twim_evt_t; - -/** - * @brief TWI event handler prototype. - */ -typedef void (* nrfx_twim_evt_handler_t)(nrfx_twim_evt_t const * p_event, - void * p_context); - -/** - * @brief Function for initializing the TWI driver instance. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_config Pointer to the structure with initial configuration. - * @param[in] event_handler Event handler provided by the user. If NULL, blocking mode is enabled. - * @param[in] p_context Context passed to event handler. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_INVALID_STATE If the driver is in invalid state. - * @retval NRFX_ERROR_BUSY If some other peripheral with the same - * instance ID is already in use. This is - * possible only if @ref nrfx_prs module - * is enabled. - */ -nrfx_err_t nrfx_twim_init(nrfx_twim_t const * p_instance, - nrfx_twim_config_t const * p_config, - nrfx_twim_evt_handler_t event_handler, - void * p_context); - -/** - * @brief Function for uninitializing the TWI instance. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_twim_uninit(nrfx_twim_t const * p_instance); - -/** - * @brief Function for enabling the TWI instance. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_twim_enable(nrfx_twim_t const * p_instance); - -/** - * @brief Function for disabling the TWI instance. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_twim_disable(nrfx_twim_t const * p_instance); - -/** - * @brief Function for sending data to a TWI slave. - * - * The transmission will be stopped when an error occurs. If a transfer is ongoing, - * the function returns the error code @ref NRFX_ERROR_BUSY. - * - * @note Peripherals using EasyDMA (including TWIM) require the transfer buffers - * to be placed in the Data RAM region. If this condition is not met, - * this function will fail with the error code NRFX_ERROR_INVALID_ADDR. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] address Address of a specific slave device (only 7 LSB). - * @param[in] p_data Pointer to a transmit buffer. - * @param[in] length Number of bytes to send. Maximum possible length is - * dependent on the used SoC (see the MAXCNT register - * description in the Product Specification). The driver - * checks it with assertion. - * @param[in] no_stop If set, the stop condition is not generated on the bus - * after the transfer has completed successfully (allowing - * for a repeated start in the next transfer). - * - * @retval NRFX_SUCCESS If the procedure was successful. - * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer. - * @retval NRFX_ERROR_INTERNAL If an error was detected by hardware. - * @retval NRFX_ERROR_INVALID_ADDR If the provided buffer is not placed in the Data RAM region. - * @retval NRFX_ERROR_DRV_TWI_ERR_ANACK If NACK received after sending the address in polling mode. - * @retval NRFX_ERROR_DRV_TWI_ERR_DNACK If NACK received after sending a data byte in polling mode. - */ -nrfx_err_t nrfx_twim_tx(nrfx_twim_t const * p_instance, - uint8_t address, - uint8_t const * p_data, - size_t length, - bool no_stop); - -/** - * @brief Function for reading data from a TWI slave. - * - * The transmission will be stopped when an error occurs. If a transfer is ongoing, - * the function returns the error code @ref NRFX_ERROR_BUSY. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] address Address of a specific slave device (only 7 LSB). - * @param[in] p_data Pointer to a receive buffer. - * @param[in] length Number of bytes to be received. Maximum possible length - * is dependent on the used SoC (see the MAXCNT register - * description in the Product Specification). The driver - * checks it with assertion. - * - * @retval NRFX_SUCCESS If the procedure was successful. - * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer. - * @retval NRFX_ERROR_INTERNAL If an error was detected by hardware. - * @retval NRFX_ERROR_DRV_TWI_ERR_ANACK If NACK received after sending the address in polling mode. - * @retval NRFX_ERROR_DRV_TWI_ERR_DNACK If NACK received after sending a data byte in polling mode. - */ -nrfx_err_t nrfx_twim_rx(nrfx_twim_t const * p_instance, - uint8_t address, - uint8_t * p_data, - size_t length); - -/** - * @brief Function for preparing a TWI transfer. - * - * The following transfer types can be configured (@ref nrfx_twim_xfer_desc_t::type): - * - @ref NRFX_TWIM_XFER_TXRX: Write operation followed by a read operation (without STOP condition in between). - * - @ref NRFX_TWIM_XFER_TXTX: Write operation followed by a write operation (without STOP condition in between). - * - @ref NRFX_TWIM_XFER_TX: Write operation (with or without STOP condition). - * - @ref NRFX_TWIM_XFER_RX: Read operation (with STOP condition). - * - * @note TXRX and TXTX transfers are supported only in non-blocking mode. - * - * Additional options are provided using the flags parameter: - * - @ref NRFX_TWIM_FLAG_TX_POSTINC and @ref NRFX_TWIM_FLAG_RX_POSTINC: Post-incrementation of buffer addresses. Supported only by TWIM. - * - @ref NRFX_TWIM_FLAG_NO_XFER_EVT_HANDLER: No user event handler after transfer completion. In most cases, this also means no interrupt at the end of the transfer. - * - @ref NRFX_TWIM_FLAG_HOLD_XFER: Driver is not starting the transfer. Use this flag if the transfer is triggered externally by PPI. Supported only by TWIM. - * Use @ref nrfx_twim_start_task_get to get the address of the start task. - * - @ref NRFX_TWIM_FLAG_REPEATED_XFER: Prepare for repeated transfers. You can set up a number of transfers that will be triggered externally (for example by PPI). - * An example is a TXRX transfer with the options @ref NRFX_TWIM_FLAG_RX_POSTINC, @ref NRFX_TWIM_FLAG_NO_XFER_EVT_HANDLER, and @ref NRFX_TWIM_FLAG_REPEATED_XFER. - * After the transfer is set up, a set of transfers can be triggered by PPI that will read, for example, the same register of an - * external component and put it into a RAM buffer without any interrupts. @ref nrfx_twim_stopped_event_get can be used to get the - * address of the STOPPED event, which can be used to count the number of transfers. If @ref NRFX_TWIM_FLAG_REPEATED_XFER is used, - * the driver does not set the driver instance into busy state, so you must ensure that the next transfers are set up - * when TWIM is not active. Supported only by TWIM. - * - @ref NRFX_TWIM_FLAG_TX_NO_STOP: No stop condition after TX transfer. - * - * @note - * Some flag combinations are invalid: - * - @ref NRFX_TWIM_FLAG_TX_NO_STOP with @ref nrfx_twim_xfer_desc_t::type different than @ref NRFX_TWIM_XFER_TX - * - @ref NRFX_TWIM_FLAG_REPEATED_XFER with @ref nrfx_twim_xfer_desc_t::type set to @ref NRFX_TWIM_XFER_TXTX - * - * If @ref nrfx_twim_xfer_desc_t::type is set to @ref NRFX_TWIM_XFER_TX and the @ref NRFX_TWIM_FLAG_TX_NO_STOP and @ref NRFX_TWIM_FLAG_REPEATED_XFER - * flags are set, two tasks must be used to trigger a transfer: TASKS_RESUME followed by TASKS_STARTTX. If no stop condition is generated, - * TWIM is in SUSPENDED state. Therefore, it must be resumed before the transfer can be started. - * - * @note Peripherals using EasyDMA (including TWIM) require the transfer buffers - * to be placed in the Data RAM region. If this condition is not met, - * this function will fail with the error code NRFX_ERROR_INVALID_ADDR. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_xfer_desc Pointer to the transfer descriptor. - * @param[in] flags Transfer options (0 for default settings). - * - * @retval NRFX_SUCCESS If the procedure was successful. - * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer. - * @retval NRFX_ERROR_NOT_SUPPORTED If the provided parameters are not supported. - * @retval NRFX_ERROR_INTERNAL If an error was detected by hardware. - * @retval NRFX_ERROR_INVALID_ADDR If the provided buffers are not placed in the Data RAM region. - * @retval NRFX_ERROR_DRV_TWI_ERR_ANACK If NACK received after sending the address. - * @retval NRFX_ERROR_DRV_TWI_ERR_DNACK If NACK received after sending a data byte. - */ -nrfx_err_t nrfx_twim_xfer(nrfx_twim_t const * p_instance, - nrfx_twim_xfer_desc_t const * p_xfer_desc, - uint32_t flags); - -/** - * @brief Function for checking the TWI driver state. - * - * @param[in] p_instance TWI instance. - * - * @retval true If the TWI driver is currently busy performing a transfer. - * @retval false If the TWI driver is ready for a new transfer. - */ -bool nrfx_twim_is_busy(nrfx_twim_t const * p_instance); - - -/** - * @brief Function for returning the address of a TWIM start task. - * - * This function should be used if @ref nrfx_twim_xfer was called with the flag @ref NRFX_TWIM_FLAG_HOLD_XFER. - * In that case, the transfer is not started by the driver, but it must be started externally by PPI. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] xfer_type Transfer type used in the last call of the @ref nrfx_twim_xfer function. - * - * @return Start task address (TX or RX) depending on the value of xfer_type. - */ -uint32_t nrfx_twim_start_task_get(nrfx_twim_t const * p_instance, nrfx_twim_xfer_type_t xfer_type); - -/** - * @brief Function for returning the address of a STOPPED TWIM event. - * - * A STOPPED event can be used to detect the end of a transfer if the @ref NRFX_TWIM_FLAG_NO_XFER_EVT_HANDLER - * option is used. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @return STOPPED event address. - */ -uint32_t nrfx_twim_stopped_event_get(nrfx_twim_t const * p_instance); - - -void nrfx_twim_0_irq_handler(void); -void nrfx_twim_1_irq_handler(void); - - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_TWIM_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_twis.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_twis.h deleted file mode 100644 index 587ca34872..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_twis.h +++ /dev/null @@ -1,405 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_TWIS_H__ -#define NRFX_TWIS_H__ - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_twis TWIS driver - * @{ - * @ingroup nrf_twis - * @brief Two Wire Slave interface (TWIS) peripheral driver. - */ - -/** - * @brief TWIS driver instance data structure. - */ -typedef struct -{ - NRF_TWIS_Type * p_reg; ///< Pointer to a structure with TWIS registers. - uint8_t drv_inst_idx; ///< Driver instance index. -} nrfx_twis_t; - -enum { -#if NRFX_CHECK(NRFX_TWIS0_ENABLED) - NRFX_TWIS0_INST_IDX, -#endif -#if NRFX_CHECK(NRFX_TWIS1_ENABLED) - NRFX_TWIS1_INST_IDX, -#endif - NRFX_TWIS_ENABLED_COUNT -}; - -/** - * @brief Macro for creating a TWIS driver instance. - */ -#define NRFX_TWIS_INSTANCE(id) \ -{ \ - .p_reg = NRFX_CONCAT_2(NRF_TWIS, id), \ - .drv_inst_idx = NRFX_CONCAT_3(NRFX_TWIS, id, _INST_IDX), \ -} - -/** - * @brief Event callback function event definitions. - */ -typedef enum -{ - NRFX_TWIS_EVT_READ_REQ, ///< Read request detected. - /**< If there is no buffer prepared, buf_req flag in the even will be set. - Call then @ref nrfx_twis_tx_prepare to give parameters for buffer. - */ - NRFX_TWIS_EVT_READ_DONE, ///< Read request has finished - free any data. - NRFX_TWIS_EVT_READ_ERROR, ///< Read request finished with error. - NRFX_TWIS_EVT_WRITE_REQ, ///< Write request detected. - /**< If there is no buffer prepared, buf_req flag in the even will be set. - Call then @ref nrfx_twis_rx_prepare to give parameters for buffer. - */ - NRFX_TWIS_EVT_WRITE_DONE, ///< Write request has finished - process data. - NRFX_TWIS_EVT_WRITE_ERROR, ///< Write request finished with error. - NRFX_TWIS_EVT_GENERAL_ERROR ///< Error that happens not inside WRITE or READ transaction. -} nrfx_twis_evt_type_t; - -/** - * @brief Possible error sources. - * - * This is flag enum - values from this enum can be connected using logical or operator. - * @note - * We could use directly @ref nrf_twis_error_t. Error type enum is redefined here because - * of possible future extension (eg. supporting timeouts and synchronous mode). - */ -typedef enum -{ - NRFX_TWIS_ERROR_OVERFLOW = NRF_TWIS_ERROR_OVERFLOW, /**< RX buffer overflow detected, and prevented. */ - NRFX_TWIS_ERROR_DATA_NACK = NRF_TWIS_ERROR_DATA_NACK, /**< NACK sent after receiving a data byte. */ - NRFX_TWIS_ERROR_OVERREAD = NRF_TWIS_ERROR_OVERREAD, /**< TX buffer over-read detected, and prevented. */ - NRFX_TWIS_ERROR_UNEXPECTED_EVENT = 1 << 8 /**< Unexpected event detected by state machine. */ -} nrfx_twis_error_t; - -/** - * @brief TWIS driver event structure. - */ -typedef struct -{ - nrfx_twis_evt_type_t type; ///< Event type. - union - { - bool buf_req; ///< Flag for @ref NRFX_TWIS_EVT_READ_REQ and @ref NRFX_TWIS_EVT_WRITE_REQ. - /**< Information if transmission buffer requires to be prepared. */ - uint32_t tx_amount; ///< Data for @ref NRFX_TWIS_EVT_READ_DONE. - uint32_t rx_amount; ///< Data for @ref NRFX_TWIS_EVT_WRITE_DONE. - uint32_t error; ///< Data for @ref NRFX_TWIS_EVT_GENERAL_ERROR. - } data; -} nrfx_twis_evt_t; - -/** - * @brief TWI slave event callback function type. - * - * @param[in] p_event Event information structure. - */ -typedef void (*nrfx_twis_event_handler_t)(nrfx_twis_evt_t const * p_event); - -/** - * @brief Structure for TWIS configuration. - */ -typedef struct -{ - uint32_t addr[2]; //!< Set addresses that this slave should respond. Set 0 to disable. - uint32_t scl; //!< SCL pin number. - uint32_t sda; //!< SDA pin number. - nrf_gpio_pin_pull_t scl_pull; //!< SCL pin pull. - nrf_gpio_pin_pull_t sda_pull; //!< SDA pin pull. - uint8_t interrupt_priority; //!< The priority of interrupt for the module to set. -} nrfx_twis_config_t; - -/** - * @brief Generate default configuration for TWIS driver instance. - */ -#define NRFX_TWIS_DEFAULT_CONFIG \ -{ \ - .addr = { NRFX_TWIS_DEFAULT_CONFIG_ADDR0, \ - NRFX_TWIS_DEFAULT_CONFIG_ADDR1 }, \ - .scl = 31, \ - .scl_pull = (nrf_gpio_pin_pull_t)NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL, \ - .sda = 31, \ - .sda_pull = (nrf_gpio_pin_pull_t)NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL, \ - .interrupt_priority = NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY \ -} - -/** - * @brief Function for initializing the TWIS driver instance. - * - * Function initializes and enables TWIS driver. - * @attention After driver initialization enable it by @ref nrfx_twis_enable. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @attention @em p_instance has to be global object. - * It would be used by interrupts so make it sure that object - * would not be destroyed when function is leaving. - * @param[in] p_config Pointer to the structure with initial configuration. - * @param[in] event_handler Event handler provided by the user. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_INVALID_STATE If the driver is already initialized. - * @retval NRFX_ERROR_BUSY If some other peripheral with the same - * instance ID is already in use. This is - * possible only if NRFX_PRS_ENABLED - * is set to a value other than zero. - */ -nrfx_err_t nrfx_twis_init(nrfx_twis_t const * p_instance, - nrfx_twis_config_t const * p_config, - nrfx_twis_event_handler_t event_handler); - -/** - * @brief Function for uninitializing the TWIS driver instance. - * - * Function initializes the peripheral and resets all registers to default values. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @note - * It is safe to call nrfx_twis_uninit even before initialization. - * Actually @ref nrfx_twis_init function calls this function to - * make sure that TWIS state is known. - * @note - * If TWIS driver was in uninitialized state before calling this function, - * selected pins would not be reset to default configuration. - */ -void nrfx_twis_uninit(nrfx_twis_t const * p_instance); - -/** - * @brief Enable TWIS instance. - * - * This function enables TWIS instance. - * Function defined if there is needs for dynamically enabling and disabling the peripheral. - * Use @ref nrfx_twis_enable and @ref nrfx_twis_disable functions. - * They do not change any configuration registers. - * - * @param p_instance Pointer to the driver instance structure. - */ -void nrfx_twis_enable(nrfx_twis_t const * p_instance); - -/** - * @brief Disable TWIS instance. - * - * Disabling TWIS instance gives possibility to turn off the TWIS while - * holding configuration done by @ref nrfx_twis_init. - * - * @param p_instance Pointer to the driver instance structure. - */ -void nrfx_twis_disable(nrfx_twis_t const * p_instance); - -/** - * @brief Get and clear last error flags. - * - * Function gets information about errors. - * This is also the only possibility to exit from error substate of the internal state machine. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @return Error flags defined in @ref nrfx_twis_error_t. - * @attention - * This function clears error state and flags. - */ -uint32_t nrfx_twis_error_get_and_clear(nrfx_twis_t const * p_instance); - - -/** - * @brief Prepare data for sending. - * - * This function should be used in response for @ref NRFX_TWIS_EVT_READ_REQ event. - * - * @note Peripherals using EasyDMA (including TWIS) require the transfer buffers - * to be placed in the Data RAM region. If this condition is not met, - * this function will fail with the error code NRFX_ERROR_INVALID_ADDR. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_buf Transmission buffer. - * @attention Transmission buffer has to be placed in RAM. - * @param size Maximum number of bytes that master may read from buffer given. - * - * @retval NRFX_SUCCESS Preparation finished properly. - * @retval NRFX_ERROR_INVALID_ADDR Given @em p_buf is not placed inside the RAM. - * @retval NRFX_ERROR_INVALID_LENGTH Wrong value in @em size parameter. - * @retval NRFX_ERROR_INVALID_STATE Module not initialized or not enabled. - */ -nrfx_err_t nrfx_twis_tx_prepare(nrfx_twis_t const * p_instance, - void const * p_buf, - size_t size); - -/** - * @brief Get number of transmitted bytes. - * - * Function returns number of bytes sent. - * This function may be called after @ref NRFX_TWIS_EVT_READ_DONE or @ref NRFX_TWIS_EVT_READ_ERROR events. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @return Number of bytes sent. - */ -__STATIC_INLINE size_t nrfx_twis_tx_amount(nrfx_twis_t const * p_instance); - -/** - * @brief Prepare data for receiving - * - * This function should be used in response for @ref NRFX_TWIS_EVT_WRITE_REQ event. - * - * @note Peripherals using EasyDMA (including TWIS) require the transfer buffers - * to be placed in the Data RAM region. If this condition is not met, - * this function will fail with the error code NRFX_ERROR_INVALID_ADDR. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_buf Buffer that would be filled with received data. - * @attention Receiving buffer has to be placed in RAM. - * @param size Size of the buffer (maximum amount of data to receive). - * - * @retval NRFX_SUCCESS Preparation finished properly. - * @retval NRFX_ERROR_INVALID_ADDR Given @em p_buf is not placed inside the RAM. - * @retval NRFX_ERROR_INVALID_LENGTH Wrong value in @em size parameter. - * @retval NRFX_ERROR_INVALID_STATE Module not initialized or not enabled. - */ -nrfx_err_t nrfx_twis_rx_prepare(nrfx_twis_t const * p_instance, - void * p_buf, - size_t size); - -/** - * @brief Get number of received bytes. - * - * Function returns number of bytes received. - * This function may be called after @ref NRFX_TWIS_EVT_WRITE_DONE or @ref NRFX_TWIS_EVT_WRITE_ERROR events. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @return Number of bytes received. - */ -__STATIC_INLINE size_t nrfx_twis_rx_amount(nrfx_twis_t const * p_instance); - -/** - * @brief Function checks if driver is busy right now. - * - * Actual driver substate is tested. - * If driver is in any other state than IDLE or ERROR this function returns true. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @retval true Driver is in state other than ERROR or IDLE. - * @retval false There is no transmission pending. - */ -bool nrfx_twis_is_busy(nrfx_twis_t const * p_instance); - -/** - * @brief Function checks if driver is waiting for tx buffer. - * - * If this function returns true, it means that driver is stalled expecting - * of the @ref nrfx_twis_tx_prepare function call. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @retval true Driver waits for @ref nrfx_twis_tx_prepare. - * @retval false Driver is not in the state where it waits for preparing tx buffer. - */ -bool nrfx_twis_is_waiting_tx_buff(nrfx_twis_t const * p_instance); - -/** - * @brief Function checks if driver is waiting for rx buffer. - * - * If this function returns true, it means that driver is staled expecting - * of the @ref nrfx_twis_rx_prepare function call. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @retval true Driver waits for @ref nrfx_twis_rx_prepare. - * @retval false Driver is not in the state where it waits for preparing rx buffer. - */ -bool nrfx_twis_is_waiting_rx_buff(nrfx_twis_t const * p_instance); - -/** - * @brief Check if driver is sending data. - * - * If this function returns true, it means that there is ongoing output transmission. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @retval true There is ongoing output transmission. - * @retval false Driver is in other state. - */ -bool nrfx_twis_is_pending_tx(nrfx_twis_t const * p_instance); - -/** - * @brief Check if driver is receiving data. - * - * If this function returns true, it means that there is ongoing input transmission. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @retval true There is ongoing input transmission. - * @retval false Driver is in other state. - */ -bool nrfx_twis_is_pending_rx(nrfx_twis_t const * p_instance); - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION -__STATIC_INLINE size_t nrfx_twis_tx_amount(nrfx_twis_t const * p_instance) -{ - return nrf_twis_tx_amount_get(p_instance->p_reg); -} - -__STATIC_INLINE size_t nrfx_twis_rx_amount(nrfx_twis_t const * p_instance) -{ - return nrf_twis_rx_amount_get(p_instance->p_reg); -} -#endif // SUPPRESS_INLINE_IMPLEMENTATION - - -void nrfx_twis_0_irq_handler(void); -void nrfx_twis_1_irq_handler(void); - - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_TWIS_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_uart.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_uart.h deleted file mode 100644 index e1ddbe8603..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_uart.h +++ /dev/null @@ -1,365 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_UART_H__ -#define NRFX_UART_H__ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_uart UART driver - * @{ - * @ingroup nrf_uart - * @brief UART peripheral driver. - */ - -/** - * @brief UART driver instance data structure. - */ -typedef struct -{ - NRF_UART_Type * p_reg; ///< Pointer to a structure with UART registers. - uint8_t drv_inst_idx; ///< Driver instance index. -} nrfx_uart_t; - -enum { -#if NRFX_CHECK(NRFX_UART0_ENABLED) - NRFX_UART0_INST_IDX, -#endif - NRFX_UART_ENABLED_COUNT -}; - -/** - * @brief Macro for creating a UART driver instance. - */ -#define NRFX_UART_INSTANCE(id) \ -{ \ - .p_reg = NRFX_CONCAT_2(NRF_UART, id), \ - .drv_inst_idx = NRFX_CONCAT_3(NRFX_UART, id, _INST_IDX), \ -} - -/** - * @brief Types of UART driver events. - */ -typedef enum -{ - NRFX_UART_EVT_TX_DONE, ///< Requested TX transfer completed. - NRFX_UART_EVT_RX_DONE, ///< Requested RX transfer completed. - NRFX_UART_EVT_ERROR, ///< Error reported by UART peripheral. -} nrfx_uart_evt_type_t; - -/** - * @brief Structure for UART configuration. - */ -typedef struct -{ - uint32_t pseltxd; ///< TXD pin number. - uint32_t pselrxd; ///< RXD pin number. - uint32_t pselcts; ///< CTS pin number. - uint32_t pselrts; ///< RTS pin number. - void * p_context; ///< Context passed to interrupt handler. - nrf_uart_hwfc_t hwfc; ///< Flow control configuration. - nrf_uart_parity_t parity; ///< Parity configuration. - nrf_uart_baudrate_t baudrate; ///< Baudrate. - uint8_t interrupt_priority; ///< Interrupt priority. -} nrfx_uart_config_t; - -/** - * @brief UART default configuration. - */ -#define NRFX_UART_DEFAULT_CONFIG \ -{ \ - .pseltxd = NRF_UART_PSEL_DISCONNECTED, \ - .pselrxd = NRF_UART_PSEL_DISCONNECTED, \ - .pselcts = NRF_UART_PSEL_DISCONNECTED, \ - .pselrts = NRF_UART_PSEL_DISCONNECTED, \ - .p_context = NULL, \ - .hwfc = (nrf_uart_hwfc_t)NRFX_UART_DEFAULT_CONFIG_HWFC, \ - .parity = (nrf_uart_parity_t)NRFX_UART_DEFAULT_CONFIG_PARITY, \ - .baudrate = (nrf_uart_baudrate_t)NRFX_UART_DEFAULT_CONFIG_BAUDRATE, \ - .interrupt_priority = NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY, \ -} - -/** - * @brief Structure for UART transfer completion event. - */ -typedef struct -{ - uint8_t * p_data; ///< Pointer to memory used for transfer. - uint32_t bytes; ///< Number of bytes transfered. -} nrfx_uart_xfer_evt_t; - -/** - * @brief Structure for UART error event. - */ -typedef struct -{ - nrfx_uart_xfer_evt_t rxtx; ///< Transfer details includes number of bytes transferred. - uint32_t error_mask; ///< Mask of error flags that generated the event. -} nrfx_uart_error_evt_t; - -/** - * @brief Structure for UART event. - */ -typedef struct -{ - nrfx_uart_evt_type_t type; ///< Event type. - union - { - nrfx_uart_xfer_evt_t rxtx; ///< Data provided for transfer completion events. - nrfx_uart_error_evt_t error; ///< Data provided for error event. - } data; -} nrfx_uart_event_t; - -/** - * @brief UART interrupt event handler. - * - * @param[in] p_event Pointer to event structure. Event is allocated on the stack so it is available - * only within the context of the event handler. - * @param[in] p_context Context passed to interrupt handler, set on initialization. - */ -typedef void (*nrfx_uart_event_handler_t)(nrfx_uart_event_t const * p_event, - void * p_context); - -/** - * @brief Function for initializing the UART driver. - * - * This function configures and enables UART. After this function GPIO pins are controlled by UART. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_config Pointer to the structure with initial configuration. - * @param[in] event_handler Event handler provided by the user. If not provided driver works in - * blocking mode. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_INVALID_STATE If driver is already initialized. - * @retval NRFX_ERROR_BUSY If some other peripheral with the same - * instance ID is already in use. This is - * possible only if @ref nrfx_prs module - * is enabled. - */ -nrfx_err_t nrfx_uart_init(nrfx_uart_t const * p_instance, - nrfx_uart_config_t const * p_config, - nrfx_uart_event_handler_t event_handler); - -/** - * @brief Function for uninitializing the UART driver. - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_uart_uninit(nrfx_uart_t const * p_instance); - -/** - * @brief Function for getting the address of a specific UART task. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] task Task. - * - * @return Task address. - */ -__STATIC_INLINE uint32_t nrfx_uart_task_address_get(nrfx_uart_t const * p_instance, - nrf_uart_task_t task); - -/** - * @brief Function for getting the address of a specific UART event. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] event Event. - * - * @return Event address. - */ -__STATIC_INLINE uint32_t nrfx_uart_event_address_get(nrfx_uart_t const * p_instance, - nrf_uart_event_t event); - -/** - * @brief Function for sending data over UART. - * - * If an event handler was provided in nrfx_uart_init() call, this function - * returns immediately and the handler is called when the transfer is done. - * Otherwise, the transfer is performed in blocking mode, i.e. this function - * returns when the transfer is finished. Blocking mode is not using interrupt - * so there is no context switching inside the function. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_data Pointer to data. - * @param[in] length Number of bytes to send. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_BUSY If driver is already transferring. - * @retval NRFX_ERROR_FORBIDDEN If the transfer was aborted from a different context - * (blocking mode only). - */ -nrfx_err_t nrfx_uart_tx(nrfx_uart_t const * p_instance, - uint8_t const * p_data, - size_t length); - -/** - * @brief Function for checking if UART is currently transmitting. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @retval true If UART is transmitting. - * @retval false If UART is not transmitting. - */ -bool nrfx_uart_tx_in_progress(nrfx_uart_t const * p_instance); - -/** - * @brief Function for aborting any ongoing transmission. - * @note @ref NRFX_UART_EVT_TX_DONE event will be generated in non-blocking mode. - * It will contain number of bytes sent until abort was called. The event - * handler will be called from the function context. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_uart_tx_abort(nrfx_uart_t const * p_instance); - -/** - * @brief Function for receiving data over UART. - * - * If an event handler was provided in the nrfx_uart_init() call, this function - * returns immediately and the handler is called when the transfer is done. - * Otherwise, the transfer is performed in blocking mode, i.e. this function - * returns when the transfer is finished. Blocking mode is not using interrupt so - * there is no context switching inside the function. - * The receive buffer pointer is double buffered in non-blocking mode. The secondary - * buffer can be set immediately after starting the transfer and will be filled - * when the primary buffer is full. The double buffering feature allows - * receiving data continuously. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_data Pointer to data. - * @param[in] length Number of bytes to receive. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_BUSY If the driver is already receiving - * (and the secondary buffer has already been set - * in non-blocking mode). - * @retval NRFX_ERROR_FORBIDDEN If the transfer was aborted from a different context - * (blocking mode only, also see @ref nrfx_uart_rx_disable). - * @retval NRFX_ERROR_INTERNAL If UART peripheral reported an error. - */ -nrfx_err_t nrfx_uart_rx(nrfx_uart_t const * p_instance, - uint8_t * p_data, - size_t length); - - - -/** - * @brief Function for testing the receiver state in blocking mode. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @retval true If the receiver has at least one byte of data to get. - * @retval false If the receiver is empty. - */ -bool nrfx_uart_rx_ready(nrfx_uart_t const * p_instance); - -/** - * @brief Function for enabling the receiver. - * - * UART has a 6-byte-long RX FIFO and it is used to store incoming data. If a user does not call the - * UART receive function before the FIFO is filled, an overrun error will appear. The receiver must be - * explicitly closed by the user @sa nrfx_uart_rx_disable. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_uart_rx_enable(nrfx_uart_t const * p_instance); - -/** - * @brief Function for disabling the receiver. - * - * This function must be called to close the receiver after it has been explicitly enabled by - * @sa nrfx_uart_rx_enable. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_uart_rx_disable(nrfx_uart_t const * p_instance); - -/** - * @brief Function for aborting any ongoing reception. - * @note @ref NRFX_UART_EVT_TX_DONE event will be generated in non-blocking mode. - * It will contain number of bytes received until abort was called. The event - * handler will be called from the UART interrupt context. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_uart_rx_abort(nrfx_uart_t const * p_instance); - -/** - * @brief Function for reading error source mask. Mask contains values from @ref nrf_uart_error_mask_t. - * @note Function should be used in blocking mode only. In case of non-blocking mode, an error event is - * generated. Function clears error sources after reading. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @retval Mask of reported errors. - */ -uint32_t nrfx_uart_errorsrc_get(nrfx_uart_t const * p_instance); - - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION -__STATIC_INLINE uint32_t nrfx_uart_task_address_get(nrfx_uart_t const * p_instance, - nrf_uart_task_t task) -{ - return nrf_uart_task_address_get(p_instance->p_reg, task); -} - -__STATIC_INLINE uint32_t nrfx_uart_event_address_get(nrfx_uart_t const * p_instance, - nrf_uart_event_t event) -{ - return nrf_uart_event_address_get(p_instance->p_reg, event); -} -#endif // SUPPRESS_INLINE_IMPLEMENTATION - - -void nrfx_uart_0_irq_handler(void); - - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_UART_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_uarte.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_uarte.h deleted file mode 100644 index 4dbf4bc8ad..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_uarte.h +++ /dev/null @@ -1,363 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_UARTE_H__ -#define NRFX_UARTE_H__ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_uarte UARTE driver - * @{ - * @ingroup nrf_uarte - * @brief UARTE peripheral driver. - */ - -/** - * @brief Structure for the UARTE driver instance. - */ -typedef struct -{ - NRF_UARTE_Type * p_reg; ///< Pointer to a structure with UARTE registers. - uint8_t drv_inst_idx; ///< Driver instance index. -} nrfx_uarte_t; - -enum { -#if NRFX_CHECK(NRFX_UARTE0_ENABLED) - NRFX_UARTE0_INST_IDX, -#endif -#if NRFX_CHECK(NRFX_UARTE1_ENABLED) - NRFX_UARTE1_INST_IDX, -#endif - NRFX_UARTE_ENABLED_COUNT -}; - -/** - * @brief Macro for creating a UARTE driver instance. - */ -#define NRFX_UARTE_INSTANCE(id) \ -{ \ - .p_reg = NRFX_CONCAT_2(NRF_UARTE, id), \ - .drv_inst_idx = NRFX_CONCAT_3(NRFX_UARTE, id, _INST_IDX), \ -} - -/** - * @brief Types of UARTE driver events. - */ -typedef enum -{ - NRFX_UARTE_EVT_TX_DONE, ///< Requested TX transfer completed. - NRFX_UARTE_EVT_RX_DONE, ///< Requested RX transfer completed. - NRFX_UARTE_EVT_ERROR, ///< Error reported by UART peripheral. -} nrfx_uarte_evt_type_t; - -/** - * @brief Structure for UARTE configuration. - */ -typedef struct -{ - uint32_t pseltxd; ///< TXD pin number. - uint32_t pselrxd; ///< RXD pin number. - uint32_t pselcts; ///< CTS pin number. - uint32_t pselrts; ///< RTS pin number. - void * p_context; ///< Context passed to interrupt handler. - nrf_uarte_hwfc_t hwfc; ///< Flow control configuration. - nrf_uarte_parity_t parity; ///< Parity configuration. - nrf_uarte_baudrate_t baudrate; ///< Baudrate. - uint8_t interrupt_priority; ///< Interrupt priority. -} nrfx_uarte_config_t; - -/** - * @brief UARTE default configuration. - */ -#define NRFX_UARTE_DEFAULT_CONFIG \ -{ \ - .pseltxd = NRF_UARTE_PSEL_DISCONNECTED, \ - .pselrxd = NRF_UARTE_PSEL_DISCONNECTED, \ - .pselcts = NRF_UARTE_PSEL_DISCONNECTED, \ - .pselrts = NRF_UARTE_PSEL_DISCONNECTED, \ - .p_context = NULL, \ - .hwfc = (nrf_uarte_hwfc_t)NRFX_UARTE_DEFAULT_CONFIG_HWFC, \ - .parity = (nrf_uarte_parity_t)NRFX_UARTE_DEFAULT_CONFIG_PARITY, \ - .baudrate = (nrf_uarte_baudrate_t)NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE, \ - .interrupt_priority = NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY, \ -} - -/** - * @brief Structure for UARTE transfer completion event. - */ -typedef struct -{ - uint8_t * p_data; ///< Pointer to memory used for transfer. - uint8_t bytes; ///< Number of bytes transfered. -} nrfx_uarte_xfer_evt_t; - -/** - * @brief Structure for UARTE error event. - */ -typedef struct -{ - nrfx_uarte_xfer_evt_t rxtx; ///< Transfer details includes number of bytes transferred. - uint32_t error_mask; ///< Mask of error flags that generated the event. -} nrfx_uarte_error_evt_t; - -/** - * @brief Structure for UARTE event. - */ -typedef struct -{ - nrfx_uarte_evt_type_t type; ///< Event type. - union - { - nrfx_uarte_xfer_evt_t rxtx; ///< Data provided for transfer completion events. - nrfx_uarte_error_evt_t error; ///< Data provided for error event. - } data; -} nrfx_uarte_event_t; - -/** - * @brief UARTE interrupt event handler. - * - * @param[in] p_event Pointer to event structure. Event is allocated on the stack so it is available - * only within the context of the event handler. - * @param[in] p_context Context passed to interrupt handler, set on initialization. - */ -typedef void (*nrfx_uarte_event_handler_t)(nrfx_uarte_event_t const * p_event, - void * p_context); - -/** - * @brief Function for initializing the UARTE driver. - * - * This function configures and enables UARTE. After this function GPIO pins are controlled by UARTE. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_config Pointer to the structure with initial configuration. - * @param[in] event_handler Event handler provided by the user. If not provided driver works in - * blocking mode. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_INVALID_STATE If driver is already initialized. - * @retval NRFX_ERROR_BUSY If some other peripheral with the same - * instance ID is already in use. This is - * possible only if @ref nrfx_prs module - * is enabled. - */ -nrfx_err_t nrfx_uarte_init(nrfx_uarte_t const * p_instance, - nrfx_uarte_config_t const * p_config, - nrfx_uarte_event_handler_t event_handler); - -/** - * @brief Function for uninitializing the UARTE driver. - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_uarte_uninit(nrfx_uarte_t const * p_instance); - -/** - * @brief Function for getting the address of a specific UARTE task. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] task Task. - * - * @return Task address. - */ -__STATIC_INLINE uint32_t nrfx_uarte_task_address_get(nrfx_uarte_t const * p_instance, - nrf_uarte_task_t task); - -/** - * @brief Function for getting the address of a specific UARTE event. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] event Event. - * - * @return Event address. - */ -__STATIC_INLINE uint32_t nrfx_uarte_event_address_get(nrfx_uarte_t const * p_instance, - nrf_uarte_event_t event); - -/** - * @brief Function for sending data over UARTE. - * - * If an event handler was provided in nrfx_uarte_init() call, this function - * returns immediately and the handler is called when the transfer is done. - * Otherwise, the transfer is performed in blocking mode, i.e. this function - * returns when the transfer is finished. Blocking mode is not using interrupt - * so there is no context switching inside the function. - * - * @note Peripherals using EasyDMA (including UARTE) require the transfer buffers - * to be placed in the Data RAM region. If this condition is not met, - * this function will fail with the error code NRFX_ERROR_INVALID_ADDR. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_data Pointer to data. - * @param[in] length Number of bytes to send. Maximum possible length is - * dependent on the used SoC (see the MAXCNT register - * description in the Product Specification). The driver - * checks it with assertion. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_BUSY If driver is already transferring. - * @retval NRFX_ERROR_FORBIDDEN If the transfer was aborted from a different context - * (blocking mode only). - * @retval NRFX_ERROR_INVALID_ADDR If p_data does not point to RAM buffer. - */ -nrfx_err_t nrfx_uarte_tx(nrfx_uarte_t const * p_instance, - uint8_t const * p_data, - size_t length); - -/** - * @brief Function for checking if UARTE is currently transmitting. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @retval true If UARTE is transmitting. - * @retval false If UARTE is not transmitting. - */ -bool nrfx_uarte_tx_in_progress(nrfx_uarte_t const * p_instance); - -/** - * @brief Function for aborting any ongoing transmission. - * @note @ref NRFX_UARTE_EVT_TX_DONE event will be generated in non-blocking mode. - * It will contain number of bytes sent until abort was called. The event - * handler will be called from UARTE interrupt context. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_uarte_tx_abort(nrfx_uarte_t const * p_instance); - -/** - * @brief Function for receiving data over UARTE. - * - * If an event handler was provided in the nrfx_uarte_init() call, this function - * returns immediately and the handler is called when the transfer is done. - * Otherwise, the transfer is performed in blocking mode, i.e. this function - * returns when the transfer is finished. Blocking mode is not using interrupt so - * there is no context switching inside the function. - * The receive buffer pointer is double buffered in non-blocking mode. The secondary - * buffer can be set immediately after starting the transfer and will be filled - * when the primary buffer is full. The double buffering feature allows - * receiving data continuously. - * - * @note Peripherals using EasyDMA (including UARTE) require the transfer buffers - * to be placed in the Data RAM region. If this condition is not met, - * this function will fail with the error code NRFX_ERROR_INVALID_ADDR. - * - * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_data Pointer to data. - * @param[in] length Number of bytes to receive. Maximum possible length is - * dependent on the used SoC (see the MAXCNT register - * description in the Product Specification). The driver - * checks it with assertion. - * - * @retval NRFX_SUCCESS If initialization was successful. - * @retval NRFX_ERROR_BUSY If the driver is already receiving - * (and the secondary buffer has already been set - * in non-blocking mode). - * @retval NRFX_ERROR_FORBIDDEN If the transfer was aborted from a different context - * (blocking mode only). - * @retval NRFX_ERROR_INTERNAL If UARTE peripheral reported an error. - * @retval NRFX_ERROR_INVALID_ADDR If p_data does not point to RAM buffer. - */ -nrfx_err_t nrfx_uarte_rx(nrfx_uarte_t const * p_instance, - uint8_t * p_data, - size_t length); - - - -/** - * @brief Function for testing the receiver state in blocking mode. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @retval true If the receiver has at least one byte of data to get. - * @retval false If the receiver is empty. - */ -bool nrfx_uarte_rx_ready(nrfx_uarte_t const * p_instance); - -/** - * @brief Function for aborting any ongoing reception. - * @note @ref NRFX_UARTE_EVT_RX_DONE event will be generated in non-blocking mode. - * It will contain number of bytes received until abort was called. The event - * handler will be called from UARTE interrupt context. - * - * @param[in] p_instance Pointer to the driver instance structure. - */ -void nrfx_uarte_rx_abort(nrfx_uarte_t const * p_instance); - -/** - * @brief Function for reading error source mask. Mask contains values from @ref nrf_uarte_error_mask_t. - * @note Function should be used in blocking mode only. In case of non-blocking mode, an error event is - * generated. Function clears error sources after reading. - * - * @param[in] p_instance Pointer to the driver instance structure. - * - * @retval Mask of reported errors. - */ -uint32_t nrfx_uarte_errorsrc_get(nrfx_uarte_t const * p_instance); - - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION -__STATIC_INLINE uint32_t nrfx_uarte_task_address_get(nrfx_uarte_t const * p_instance, - nrf_uarte_task_t task) -{ - return nrf_uarte_task_address_get(p_instance->p_reg, task); -} - -__STATIC_INLINE uint32_t nrfx_uarte_event_address_get(nrfx_uarte_t const * p_instance, - nrf_uarte_event_t event) -{ - return nrf_uarte_event_address_get(p_instance->p_reg, event); -} -#endif // SUPPRESS_INLINE_IMPLEMENTATION - - -void nrfx_uarte_0_irq_handler(void); -void nrfx_uarte_1_irq_handler(void); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_UARTE_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_wdt.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_wdt.h deleted file mode 100644 index 2be41249f6..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/include/nrfx_wdt.h +++ /dev/null @@ -1,156 +0,0 @@ -/** - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_WDT_H__ -#define NRFX_WDT_H__ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_wdt WDT driver - * @{ - * @ingroup nrf_wdt - * @brief Watchdog Timer (WDT) peripheral driver. - */ - -/**@brief Struct for WDT initialization. */ -typedef struct -{ - nrf_wdt_behaviour_t behaviour; /**< WDT behaviour when CPU in sleep/halt mode. */ - uint32_t reload_value; /**< WDT reload value in ms. */ - uint8_t interrupt_priority; /**< WDT interrupt priority */ -} nrfx_wdt_config_t; - -/**@brief WDT event handler function type. */ -typedef void (*nrfx_wdt_event_handler_t)(void); - -/**@brief WDT channel id type. */ -typedef nrf_wdt_rr_register_t nrfx_wdt_channel_id; - -#define NRFX_WDT_DEAFULT_CONFIG \ - { \ - .behaviour = (nrf_wdt_behaviour_t)NRFX_WDT_CONFIG_BEHAVIOUR, \ - .reload_value = NRFX_WDT_CONFIG_RELOAD_VALUE, \ - .interrupt_priority = NRFX_WDT_CONFIG_IRQ_PRIORITY, \ - } -/** - * @brief This function initializes watchdog. - * - * @param[in] p_config Pointer to the structure with initial configuration. - * @param[in] wdt_event_handler Event handler provided by the user. - * Must not be NULL. - * - * @return NRFX_SUCCESS on success, otherwise an error code. - */ -nrfx_err_t nrfx_wdt_init(nrfx_wdt_config_t const * p_config, - nrfx_wdt_event_handler_t wdt_event_handler); - -/** - * @brief This function allocate watchdog channel. - * - * @note This function can not be called after nrfx_wdt_start(void). - * - * @param[out] p_channel_id ID of granted channel. - * - * @return NRFX_SUCCESS on success, otherwise an error code. - */ -nrfx_err_t nrfx_wdt_channel_alloc(nrfx_wdt_channel_id * p_channel_id); - -/** - * @brief This function starts watchdog. - * - * @note After calling this function the watchdog is started, so the user needs to feed all allocated - * watchdog channels to avoid reset. At least one watchdog channel has to be allocated. - */ -void nrfx_wdt_enable(void); - -/** - * @brief This function feeds the watchdog. - * - * @details Function feeds all allocated watchdog channels. - */ -void nrfx_wdt_feed(void); - -/** - * @brief This function feeds the invidual watchdog channel. - * - * @param[in] channel_id ID of watchdog channel. - */ -void nrfx_wdt_channel_feed(nrfx_wdt_channel_id channel_id); - -/**@brief Function for returning a requested task address for the wdt driver module. - * - * @param[in] task One of the peripheral tasks. - * - * @retval Task address. - */ -__STATIC_INLINE uint32_t nrfx_wdt_ppi_task_addr(nrf_wdt_task_t task) -{ - return nrf_wdt_task_address_get(task); -} - -/**@brief Function for returning a requested event address for the wdt driver module. - * - * @param[in] event One of the peripheral events. - * - * @retval Event address - */ -__STATIC_INLINE uint32_t nrfx_wdt_ppi_event_addr(nrf_wdt_event_t event) -{ - return nrf_wdt_event_address_get(event); -} - - -void nrfx_wdt_irq_handler(void); - - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/nrfx_common.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/nrfx_common.h deleted file mode 100644 index 050cb2ce9a..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/nrfx_common.h +++ /dev/null @@ -1,269 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_COMMON_H__ -#define NRFX_COMMON_H__ - -#include -#include -#include - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_common Common module - * @{ - * @ingroup nrfx - * @brief Common module. - */ - -/** - * @brief Macro for checking if the specified identifier is defined and it has - * a non-zero value. - * - * Normally, preprocessors treat all undefined identifiers as having the value - * zero. However, some tools, like static code analyzers, may issue a warning - * when such identifier is evaluated. This macro gives the possibility to suppress - * such warnings only in places where this macro is used for evaluation, not in - * the whole analyzed code. - */ -#define NRFX_CHECK(module_enabled) (module_enabled) - -/** - * @brief Macro for concatenating two tokens in macro expansion. - * - * @note This macro is expanded in two steps so that tokens given as macros - * themselves are fully expanded before they are merged. - * - * @param p1 First token. - * @param p2 Second token. - * - * @return The two tokens merged into one, unless they cannot together form - * a valid token (in such case, the preprocessor issues a warning and - * does not perform the concatenation). - * - * @sa NRFX_CONCAT_3 - */ -#define NRFX_CONCAT_2(p1, p2) NRFX_CONCAT_2_(p1, p2) -/** - * @brief Internal macro used by @ref NRFX_CONCAT_2 to perform the expansion - * in two steps. - */ -#define NRFX_CONCAT_2_(p1, p2) p1 ## p2 - -/** - * @brief Macro for concatenating three tokens in macro expansion. - * - * @note This macro is expanded in two steps so that tokens given as macros - * themselves are fully expanded before they are merged. - * - * @param p1 First token. - * @param p2 Second token. - * @param p3 Third token. - * - * @return The three tokens merged into one, unless they cannot together form - * a valid token (in such case, the preprocessor issues a warning and - * does not perform the concatenation). - * - * @sa NRFX_CONCAT_2 - */ -#define NRFX_CONCAT_3(p1, p2, p3) NRFX_CONCAT_3_(p1, p2, p3) -/** - * @brief Internal macro used by @ref NRFX_CONCAT_3 to perform the expansion - * in two steps. - */ -#define NRFX_CONCAT_3_(p1, p2, p3) p1 ## p2 ## p3 - -/**@brief Macro for performing rounded integer division (as opposed to - * truncating the result). - * - * @param a Numerator. - * @param b Denominator. - * - * @return Rounded (integer) result of dividing @c a by @c b. - */ -#define NRFX_ROUNDED_DIV(a, b) (((a) + ((b) / 2)) / (b)) - -/**@brief Macro for checking if given lengths of EasyDMA transfers do not exceed - * the limit of the specified peripheral. - * - * @param peripheral Peripheral to check the lengths against. - * @param length1 First length to be checked. - * @param length2 Second length to be checked (pass 0 if not needed). - * - * @return - */ -#define NRFX_EASYDMA_LENGTH_VALIDATE(peripheral, length1, length2) \ - (((length1) < (1U << NRFX_CONCAT_2(peripheral, _EASYDMA_MAXCNT_SIZE))) && \ - ((length2) < (1U << NRFX_CONCAT_2(peripheral, _EASYDMA_MAXCNT_SIZE)))) - -/**@brief Macro for waiting until condition is met. - * - * @param[in] condition Condition to meet. - * @param[in] attempts Maximum number of condition checks. Must not be 0. - * @param[in] delay_us Delay between consecutive checks, in microseconds. - * @param[out] result Boolean variable to store the result of the wait process. - * Set to true if the condition is met or false otherwise. - */ -#define NRFX_WAIT_FOR(condition, attempts, delay_us, result) \ -do { \ - result = false; \ - uint32_t remaining_attempts = (attempts); \ - do { \ - if (condition) \ - { \ - result = true; \ - break; \ - } \ - NRFX_DELAY_US(delay_us); \ - } while (--remaining_attempts); \ -} while(0) - -/** - * @brief IRQ handler type. - */ -typedef void (* nrfx_irq_handler_t)(void); - -/** - * @brief Driver state. - */ -typedef enum -{ - NRFX_DRV_STATE_UNINITIALIZED, ///< Uninitialized. - NRFX_DRV_STATE_INITIALIZED, ///< Initialized but powered off. - NRFX_DRV_STATE_POWERED_ON, ///< Initialized and powered on. -} nrfx_drv_state_t; - - -/** - * @brief Function for checking if an object is placed in the Data RAM region. - * - * Several peripherals (the ones using EasyDMA) require the transfer buffers - * to be placed in the Data RAM region. This function can be used to check if - * this condition is met. - * - * @param[in] p_object Pointer to an object whose location is to be checked. - * - * @retval true If the pointed object is located in the Data RAM region. - * @retval false Otherwise. - */ -__STATIC_INLINE bool nrfx_is_in_ram(void const * p_object); - -/** - * @brief Function for getting the interrupt number for a specific peripheral. - * - * @param[in] p_reg Peripheral base pointer. - * - * @return Interrupt number associated with the pointed peripheral. - */ -__STATIC_INLINE IRQn_Type nrfx_get_irq_number(void const * p_reg); - -/** - * @brief Function for converting an INTEN register bit position to the - * corresponding event identifier. - * - * The event identifier is the offset between the event register address and - * the peripheral base address, and is equal (thus, can be directly cast) to - * the corresponding value of the enumerated type from HAL (nrf_*_event_t). - - * @param bit INTEN register bit position. - * - * @return Event identifier. - * - * @sa nrfx_event_to_bitpos - */ -__STATIC_INLINE uint32_t nrfx_bitpos_to_event(uint32_t bit); - -/** - * @brief Function for converting an event identifier to the corresponding - * INTEN register bit position. - * - * The event identifier is the offset between the event register address and - * the peripheral base address, and is equal (thus, can be directly cast) to - * the corresponding value of the enumerated type from HAL (nrf_*_event_t). - * - * @param event Event identifier. - * - * @return INTEN register bit position. - * - * @sa nrfx_bitpos_to_event - */ -__STATIC_INLINE uint32_t nrfx_event_to_bitpos(uint32_t event); - - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -__STATIC_INLINE bool nrfx_is_in_ram(void const * p_object) -{ - return ((((uint32_t)p_object) & 0xE0000000u) == 0x20000000u); -} - -__STATIC_INLINE IRQn_Type nrfx_get_irq_number(void const * p_reg) -{ - uint8_t irq_number = (uint8_t)(((uint32_t)p_reg) >> 12u); - return (IRQn_Type)irq_number; -} - -__STATIC_INLINE uint32_t nrfx_bitpos_to_event(uint32_t bit) -{ - static const uint32_t event_reg_offset = 0x100u; - return event_reg_offset + (bit * sizeof(uint32_t)); -} - -__STATIC_INLINE uint32_t nrfx_event_to_bitpos(uint32_t event) -{ - static const uint32_t event_reg_offset = 0x100u; - return (event - event_reg_offset) / sizeof(uint32_t); -} - -#endif - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_COMMON_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/nrfx_errors.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/nrfx_errors.h deleted file mode 100644 index 78cb22607f..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/nrfx_errors.h +++ /dev/null @@ -1,82 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_ERRORS_H__ -#define NRFX_ERRORS_H__ - -#if !NRFX_CHECK(NRFX_CUSTOM_ERROR_CODES) - -/** - * @defgroup nrfx_error_codes Global Error Codes - * @{ - * @ingroup nrfx - * - * @brief Global error codes definitions. - */ - -#define NRFX_ERROR_BASE_NUM 0x0BAD0000 -#define NRFX_ERROR_DRIVERS_BASE_NUM (NRFX_ERROR_BASE_NUM + 0x10000) - -/** @brief Enumerated type for error codes. */ -typedef enum { - NRFX_SUCCESS = (NRFX_ERROR_BASE_NUM + 0), ///< Operation performed successfully. - NRFX_ERROR_INTERNAL = (NRFX_ERROR_BASE_NUM + 1), ///< Internal error. - NRFX_ERROR_NO_MEM = (NRFX_ERROR_BASE_NUM + 2), ///< No memory for operation. - NRFX_ERROR_NOT_SUPPORTED = (NRFX_ERROR_BASE_NUM + 3), ///< Not supported. - NRFX_ERROR_INVALID_PARAM = (NRFX_ERROR_BASE_NUM + 4), ///< Invalid parameter. - NRFX_ERROR_INVALID_STATE = (NRFX_ERROR_BASE_NUM + 5), ///< Invalid state, operation disallowed in this state. - NRFX_ERROR_INVALID_LENGTH = (NRFX_ERROR_BASE_NUM + 6), ///< Invalid length. - NRFX_ERROR_TIMEOUT = (NRFX_ERROR_BASE_NUM + 7), ///< Operation timed out. - NRFX_ERROR_FORBIDDEN = (NRFX_ERROR_BASE_NUM + 8), ///< Operation is forbidden. - NRFX_ERROR_NULL = (NRFX_ERROR_BASE_NUM + 9), ///< Null pointer. - NRFX_ERROR_INVALID_ADDR = (NRFX_ERROR_BASE_NUM + 10), ///< Bad memory address. - NRFX_ERROR_BUSY = (NRFX_ERROR_BASE_NUM + 11), ///< Busy. - NRFX_ERROR_ALREADY_INITIALIZED = (NRFX_ERROR_BASE_NUM + 12), ///< Module already initialized. - - NRFX_ERROR_DRV_TWI_ERR_OVERRUN = (NRFX_ERROR_DRIVERS_BASE_NUM + 0), ///< TWI error: Overrun. - NRFX_ERROR_DRV_TWI_ERR_ANACK = (NRFX_ERROR_DRIVERS_BASE_NUM + 1), ///< TWI error: Address not acknowledged. - NRFX_ERROR_DRV_TWI_ERR_DNACK = (NRFX_ERROR_DRIVERS_BASE_NUM + 2) ///< TWI error: Data not acknowledged. -} nrfx_err_t; - -/** @} */ - -#endif // !NRFX_CHECK(NRFX_CUSTOM_ERROR_CODES) - -#endif // NRFX_ERRORS_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_adc.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_adc.c deleted file mode 100644 index be757a62b4..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_adc.c +++ /dev/null @@ -1,324 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include - -#if NRFX_CHECK(NRFX_ADC_ENABLED) - -#include - -#define NRFX_LOG_MODULE ADC -#include - -#define EVT_TO_STR(event) (event == NRF_ADC_EVENT_END ? "NRF_ADC_EVENT_END" : "UNKNOWN EVENT") - -typedef struct -{ - nrfx_adc_event_handler_t event_handler; - nrfx_adc_channel_t * p_head; - nrfx_adc_channel_t * p_current_conv; - nrf_adc_value_t * p_buffer; - uint16_t size; - uint16_t idx; - nrfx_drv_state_t state; -} adc_cb_t; - -static adc_cb_t m_cb; - -nrfx_err_t nrfx_adc_init(nrfx_adc_config_t const * p_config, - nrfx_adc_event_handler_t event_handler) -{ - NRFX_ASSERT(p_config); - nrfx_err_t err_code; - - if (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED) - { - err_code = NRFX_ERROR_INVALID_STATE; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - nrf_adc_event_clear(NRF_ADC_EVENT_END); - if (event_handler) - { - NRFX_IRQ_PRIORITY_SET(ADC_IRQn, p_config->interrupt_priority); - NRFX_IRQ_ENABLE(ADC_IRQn); - } - m_cb.event_handler = event_handler; - m_cb.state = NRFX_DRV_STATE_INITIALIZED; - - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -void nrfx_adc_uninit(void) -{ - m_cb.p_head = NULL; - NRFX_IRQ_DISABLE(ADC_IRQn); - nrf_adc_int_disable(NRF_ADC_INT_END_MASK); - nrf_adc_task_trigger(NRF_ADC_TASK_STOP); - - m_cb.state = NRFX_DRV_STATE_UNINITIALIZED; -} - -void nrfx_adc_channel_enable(nrfx_adc_channel_t * const p_channel) -{ - NRFX_ASSERT(!nrfx_adc_is_busy()); - - p_channel->p_next = NULL; - if (m_cb.p_head == NULL) - { - m_cb.p_head = p_channel; - } - else - { - nrfx_adc_channel_t * p_curr_channel = m_cb.p_head; - while (p_curr_channel->p_next != NULL) - { - NRFX_ASSERT(p_channel != p_curr_channel); - p_curr_channel = p_curr_channel->p_next; - } - p_curr_channel->p_next = p_channel; - } - - NRFX_LOG_INFO("Enabled."); -} - -void nrfx_adc_channel_disable(nrfx_adc_channel_t * const p_channel) -{ - NRFX_ASSERT(m_cb.p_head); - NRFX_ASSERT(!nrfx_adc_is_busy()); - - nrfx_adc_channel_t * p_curr_channel = m_cb.p_head; - nrfx_adc_channel_t * p_prev_channel = NULL; - while (p_curr_channel != p_channel) - { - p_prev_channel = p_curr_channel; - p_curr_channel = p_curr_channel->p_next; - NRFX_ASSERT(p_curr_channel != NULL); - } - if (p_prev_channel) - { - p_prev_channel->p_next = p_curr_channel->p_next; - } - else - { - m_cb.p_head = p_curr_channel->p_next; - } - - NRFX_LOG_INFO("Disabled."); -} - -void nrfx_adc_sample(void) -{ - NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); - NRFX_ASSERT(!nrf_adc_busy_check()); - nrf_adc_task_trigger(NRF_ADC_TASK_START); -} - -nrfx_err_t nrfx_adc_sample_convert(nrfx_adc_channel_t const * const p_channel, - nrf_adc_value_t * p_value) -{ - nrfx_err_t err_code; - - NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); - if (m_cb.state == NRFX_DRV_STATE_POWERED_ON) - { - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - else - { - m_cb.state = NRFX_DRV_STATE_POWERED_ON; - - nrf_adc_init(&p_channel->config); - nrf_adc_enable(); - nrf_adc_int_disable(NRF_ADC_INT_END_MASK); - nrf_adc_task_trigger(NRF_ADC_TASK_START); - if (p_value) - { - while (!nrf_adc_event_check(NRF_ADC_EVENT_END)) {} - nrf_adc_event_clear(NRF_ADC_EVENT_END); - *p_value = (nrf_adc_value_t)nrf_adc_result_get(); - nrf_adc_disable(); - - m_cb.state = NRFX_DRV_STATE_INITIALIZED; - } - else - { - NRFX_ASSERT(m_cb.event_handler); - m_cb.p_buffer = NULL; - nrf_adc_int_enable(NRF_ADC_INT_END_MASK); - } - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } -} - -static bool adc_sample_process() -{ - nrf_adc_event_clear(NRF_ADC_EVENT_END); - nrf_adc_disable(); - m_cb.p_buffer[m_cb.idx] = (nrf_adc_value_t)nrf_adc_result_get(); - m_cb.idx++; - if (m_cb.idx < m_cb.size) - { - bool task_trigger = false; - if (m_cb.p_current_conv->p_next == NULL) - { - m_cb.p_current_conv = m_cb.p_head; - } - else - { - m_cb.p_current_conv = m_cb.p_current_conv->p_next; - task_trigger = true; - } - nrf_adc_init(&m_cb.p_current_conv->config); - nrf_adc_enable(); - if (task_trigger) - { - nrf_adc_task_trigger(NRF_ADC_TASK_START); - } - return false; - } - else - { - return true; - } -} - -nrfx_err_t nrfx_adc_buffer_convert(nrf_adc_value_t * buffer, uint16_t size) -{ - NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); - - nrfx_err_t err_code; - - NRFX_LOG_INFO("Number of samples requested to convert: %d.", size); - - if (m_cb.state == NRFX_DRV_STATE_POWERED_ON) - { - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - else - { - m_cb.state = NRFX_DRV_STATE_POWERED_ON; - m_cb.p_current_conv = m_cb.p_head; - m_cb.size = size; - m_cb.idx = 0; - m_cb.p_buffer = buffer; - nrf_adc_init(&m_cb.p_current_conv->config); - nrf_adc_event_clear(NRF_ADC_EVENT_END); - nrf_adc_enable(); - if (m_cb.event_handler) - { - nrf_adc_int_enable(NRF_ADC_INT_END_MASK); - } - else - { - while (1) - { - while (!nrf_adc_event_check(NRF_ADC_EVENT_END)){} - - if (adc_sample_process()) - { - m_cb.state = NRFX_DRV_STATE_INITIALIZED; - break; - } - } - } - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } -} - -bool nrfx_adc_is_busy(void) -{ - NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); - return (m_cb.state == NRFX_DRV_STATE_POWERED_ON) ? true : false; -} - -void nrfx_adc_irq_handler(void) -{ - if (m_cb.p_buffer == NULL) - { - nrf_adc_event_clear(NRF_ADC_EVENT_END); - NRFX_LOG_DEBUG("Event: %s.",NRFX_LOG_ERROR_STRING_GET(NRF_ADC_EVENT_END)); - nrf_adc_int_disable(NRF_ADC_INT_END_MASK); - nrf_adc_disable(); - nrfx_adc_evt_t evt; - evt.type = NRFX_ADC_EVT_SAMPLE; - evt.data.sample.sample = (nrf_adc_value_t)nrf_adc_result_get(); - NRFX_LOG_DEBUG("ADC data:"); - NRFX_LOG_HEXDUMP_DEBUG((uint8_t *)(&evt.data.sample.sample), sizeof(nrf_adc_value_t)); - m_cb.state = NRFX_DRV_STATE_INITIALIZED; - m_cb.event_handler(&evt); - } - else if (adc_sample_process()) - { - NRFX_LOG_DEBUG("Event: %s.", NRFX_LOG_ERROR_STRING_GET(NRF_ADC_EVENT_END)); - nrf_adc_int_disable(NRF_ADC_INT_END_MASK); - nrfx_adc_evt_t evt; - evt.type = NRFX_ADC_EVT_DONE; - evt.data.done.p_buffer = m_cb.p_buffer; - evt.data.done.size = m_cb.size; - m_cb.state = NRFX_DRV_STATE_INITIALIZED; - NRFX_LOG_DEBUG("ADC data:"); - NRFX_LOG_HEXDUMP_DEBUG((uint8_t *)m_cb.p_buffer, m_cb.size * sizeof(nrf_adc_value_t)); - m_cb.event_handler(&evt); - } -} - -#endif // NRFX_CHECK(NRFX_ADC_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_clock.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_clock.c deleted file mode 100644 index f387bcc0f2..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_clock.c +++ /dev/null @@ -1,381 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include - -#if NRFX_CHECK(NRFX_CLOCK_ENABLED) - -#include - -#define NRFX_LOG_MODULE CLOCK -#include - -#if NRFX_CHECK(NRFX_POWER_ENABLED) -extern bool nrfx_power_irq_enabled; -#endif - -#define EVT_TO_STR(event) \ - (event == NRF_CLOCK_EVENT_HFCLKSTARTED ? "NRF_CLOCK_EVENT_HFCLKSTARTED" : \ - (event == NRF_CLOCK_EVENT_LFCLKSTARTED ? "NRF_CLOCK_EVENT_LFCLKSTARTED" : \ - (event == NRF_CLOCK_EVENT_DONE ? "NRF_CLOCK_EVENT_DONE" : \ - (event == NRF_CLOCK_EVENT_CTTO ? "NRF_CLOCK_EVENT_CTTO" : \ - "UNKNOWN EVENT")))) - - -/*lint -save -e652 */ -#define NRF_CLOCK_LFCLK_RC CLOCK_LFCLKSRC_SRC_RC -#define NRF_CLOCK_LFCLK_Xtal CLOCK_LFCLKSRC_SRC_Xtal -#define NRF_CLOCK_LFCLK_Synth CLOCK_LFCLKSRC_SRC_Synth -/*lint -restore */ - -#if (NRFX_CLOCK_CONFIG_LF_SRC == NRF_CLOCK_LFCLK_RC) -#define CALIBRATION_SUPPORT 1 -#else -#define CALIBRATION_SUPPORT 0 -#endif - -#if defined(NRF52810_XXAA) || \ - defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || \ - defined(NRF52840_XXAA) -// Enable workaround for nRF52 anomaly 192 (LFRC oscillator frequency is wrong -// after calibration, exceeding 500 ppm). -#define USE_WORKAROUND_FOR_ANOMALY_192 - -// Enable workaround for nRF52 anomaly 201 (EVENTS_HFCLKSTARTED might be generated twice). -#define USE_WORKAROUND_FOR_ANOMALY_201 -#endif - -typedef enum -{ - CAL_STATE_IDLE, - CAL_STATE_CAL -} nrfx_clock_cal_state_t; - -/**@brief CLOCK control block. */ -typedef struct -{ - nrfx_clock_event_handler_t event_handler; - bool module_initialized; /*< Indicate the state of module */ -#if defined(USE_WORKAROUND_FOR_ANOMALY_201) - bool hfclk_started; /*< Anomaly 201 workaround. */ -#endif - -#if CALIBRATION_SUPPORT - volatile nrfx_clock_cal_state_t cal_state; -#endif // CALIBRATION_SUPPORT -} nrfx_clock_cb_t; - -static nrfx_clock_cb_t m_clock_cb; - -/** - * This variable is used to check whether common POWER_CLOCK common interrupt - * should be disabled or not if @ref nrfx_power tries to disable the interrupt. - */ -#if NRFX_CHECK(NRFX_POWER_ENABLED) -bool nrfx_clock_irq_enabled; -#endif - -#if defined(NRF52832_XXAA) || defined(NRF52832_XXAB) - -// ANOMALY 132 - LFCLK needs to avoid frame from 66us to 138us after LFCLK stop. This solution -// applies delay of 138us before starting LFCLK. -#define ANOMALY_132_REQ_DELAY_US 138UL - -// nRF52832 is clocked with 64MHz. -#define ANOMALY_132_NRF52832_FREQ_MHZ 64UL - -// Convert time to cycles. -#define ANOMALY_132_DELAY_CYCLES (ANOMALY_132_REQ_DELAY_US * ANOMALY_132_NRF52832_FREQ_MHZ) - -/** - * @brief Function for applying delay of 138us before starting LFCLK. - */ -static void nrfx_clock_anomaly_132(void) -{ - uint32_t cyccnt_inital; - uint32_t core_debug; - uint32_t dwt_ctrl; - - // Preserve DEMCR register to do not influence into its configuration. Enable the trace and - // debug blocks. It is required to read and write data to DWT block. - core_debug = CoreDebug->DEMCR; - CoreDebug->DEMCR = core_debug | CoreDebug_DEMCR_TRCENA_Msk; - - // Preserve CTRL register in DWT block to do not influence into its configuration. Make sure - // that cycle counter is enabled. - dwt_ctrl = DWT->CTRL; - DWT->CTRL = dwt_ctrl | DWT_CTRL_CYCCNTENA_Msk; - - // Store start value of cycle counter. - cyccnt_inital = DWT->CYCCNT; - - // Delay required time. - while ((DWT->CYCCNT - cyccnt_inital) < ANOMALY_132_DELAY_CYCLES) - {} - - // Restore preserved registers. - DWT->CTRL = dwt_ctrl; - CoreDebug->DEMCR = core_debug; -} - -#endif // defined(NRF52832_XXAA) || defined(NRF52832_XXAB) - -nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler) -{ - NRFX_ASSERT(event_handler); - - nrfx_err_t err_code = NRFX_SUCCESS; - if (m_clock_cb.module_initialized) - { - err_code = NRFX_ERROR_ALREADY_INITIALIZED; - } - else - { -#if CALIBRATION_SUPPORT - m_clock_cb.cal_state = CAL_STATE_IDLE; -#endif - m_clock_cb.event_handler = event_handler; - m_clock_cb.module_initialized = true; -#if defined(USE_WORKAROUND_FOR_ANOMALY_201) - m_clock_cb.hfclk_started = false; -#endif - } - - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -void nrfx_clock_enable(void) -{ - NRFX_ASSERT(m_clock_cb.module_initialized); - nrfx_power_clock_irq_init(); - nrf_clock_lf_src_set((nrf_clock_lfclk_t)NRFX_CLOCK_CONFIG_LF_SRC); - -#if NRFX_CHECK(NRFX_POWER_ENABLED) - nrfx_clock_irq_enabled = true; -#endif - - NRFX_LOG_INFO("Module enabled."); -} - -void nrfx_clock_disable(void) -{ - NRFX_ASSERT(m_clock_cb.module_initialized); -#if NRFX_CHECK(NRFX_POWER_ENABLED) - NRFX_ASSERT(nrfx_clock_irq_enabled); - if (!nrfx_power_irq_enabled) -#endif - { - NRFX_IRQ_DISABLE(POWER_CLOCK_IRQn); - } - nrf_clock_int_disable(CLOCK_INTENSET_HFCLKSTARTED_Msk | - CLOCK_INTENSET_LFCLKSTARTED_Msk | - CLOCK_INTENSET_DONE_Msk | - CLOCK_INTENSET_CTTO_Msk); -#if NRFX_CHECK(NRFX_POWER_ENABLED) - nrfx_clock_irq_enabled = false; -#endif - NRFX_LOG_INFO("Module disabled."); -} - -void nrfx_clock_uninit(void) -{ - NRFX_ASSERT(m_clock_cb.module_initialized); - nrfx_clock_lfclk_stop(); - nrfx_clock_hfclk_stop(); - m_clock_cb.module_initialized = false; - NRFX_LOG_INFO("Uninitialized."); -} - -void nrfx_clock_lfclk_start(void) -{ - NRFX_ASSERT(m_clock_cb.module_initialized); - nrf_clock_event_clear(NRF_CLOCK_EVENT_LFCLKSTARTED); - nrf_clock_int_enable(NRF_CLOCK_INT_LF_STARTED_MASK); - -#if defined(NRF52832_XXAA) || defined(NRF52832_XXAB) - nrfx_clock_anomaly_132(); -#endif - - nrf_clock_task_trigger(NRF_CLOCK_TASK_LFCLKSTART); -} - -void nrfx_clock_lfclk_stop(void) -{ - NRFX_ASSERT(m_clock_cb.module_initialized); - nrf_clock_task_trigger(NRF_CLOCK_TASK_LFCLKSTOP); - while (nrf_clock_lf_is_running()) - {} -} - -void nrfx_clock_hfclk_start(void) -{ - NRFX_ASSERT(m_clock_cb.module_initialized); - nrf_clock_event_clear(NRF_CLOCK_EVENT_HFCLKSTARTED); - nrf_clock_int_enable(NRF_CLOCK_INT_HF_STARTED_MASK); - nrf_clock_task_trigger(NRF_CLOCK_TASK_HFCLKSTART); -} - -void nrfx_clock_hfclk_stop(void) -{ - NRFX_ASSERT(m_clock_cb.module_initialized); - nrf_clock_task_trigger(NRF_CLOCK_TASK_HFCLKSTOP); - while (nrf_clock_hf_is_running(NRF_CLOCK_HFCLK_HIGH_ACCURACY)) - {} -#if defined(USE_WORKAROUND_FOR_ANOMALY_201) - m_clock_cb.hfclk_started = false; -#endif -} - -nrfx_err_t nrfx_clock_calibration_start(void) -{ - nrfx_err_t err_code = NRFX_SUCCESS; -#if CALIBRATION_SUPPORT - if (nrfx_clock_hfclk_is_running() == false) - { - return NRFX_ERROR_INVALID_STATE; - } - - if (nrfx_clock_lfclk_is_running() == false) - { - return NRFX_ERROR_INVALID_STATE; - } - - if (m_clock_cb.cal_state == CAL_STATE_IDLE) - { - nrf_clock_event_clear(NRF_CLOCK_EVENT_DONE); - nrf_clock_int_enable(NRF_CLOCK_INT_DONE_MASK); - m_clock_cb.cal_state = CAL_STATE_CAL; -#if defined(USE_WORKAROUND_FOR_ANOMALY_192) - *(volatile uint32_t *)0x40000C34 = 0x00000002; -#endif - nrf_clock_task_trigger(NRF_CLOCK_TASK_CAL); - } - else - { - err_code = NRFX_ERROR_BUSY; - } -#endif // CALIBRATION_SUPPORT - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -nrfx_err_t nrfx_clock_is_calibrating(void) -{ -#if CALIBRATION_SUPPORT - if (m_clock_cb.cal_state == CAL_STATE_CAL) - { - return NRFX_ERROR_BUSY; - } -#endif - return NRFX_SUCCESS; -} - -void nrfx_clock_calibration_timer_start(uint8_t interval) -{ - nrf_clock_cal_timer_timeout_set(interval); - nrf_clock_event_clear(NRF_CLOCK_EVENT_CTTO); - nrf_clock_int_enable(NRF_CLOCK_INT_CTTO_MASK); - nrf_clock_task_trigger(NRF_CLOCK_TASK_CTSTART); -} - -void nrfx_clock_calibration_timer_stop(void) -{ - nrf_clock_int_disable(NRF_CLOCK_INT_CTTO_MASK); - nrf_clock_task_trigger(NRF_CLOCK_TASK_CTSTOP); -} - -void nrfx_clock_irq_handler(void) -{ - if (nrf_clock_event_check(NRF_CLOCK_EVENT_HFCLKSTARTED)) - { - nrf_clock_event_clear(NRF_CLOCK_EVENT_HFCLKSTARTED); - NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRF_CLOCK_EVENT_HFCLKSTARTED)); - nrf_clock_int_disable(NRF_CLOCK_INT_HF_STARTED_MASK); - -#if defined(USE_WORKAROUND_FOR_ANOMALY_201) - if (!m_clock_cb.hfclk_started) - { - m_clock_cb.hfclk_started = true; - m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED); - } -#else - m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED); -#endif - } - if (nrf_clock_event_check(NRF_CLOCK_EVENT_LFCLKSTARTED)) - { - nrf_clock_event_clear(NRF_CLOCK_EVENT_LFCLKSTARTED); - NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRF_CLOCK_EVENT_LFCLKSTARTED)); - nrf_clock_int_disable(NRF_CLOCK_INT_LF_STARTED_MASK); - - m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED); - } -#if CALIBRATION_SUPPORT - if (nrf_clock_event_check(NRF_CLOCK_EVENT_CTTO)) - { - nrf_clock_event_clear(NRF_CLOCK_EVENT_CTTO); - NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRF_CLOCK_EVENT_CTTO)); - nrf_clock_int_disable(NRF_CLOCK_INT_CTTO_MASK); - - m_clock_cb.event_handler(NRFX_CLOCK_EVT_CTTO); - } - - if (nrf_clock_event_check(NRF_CLOCK_EVENT_DONE)) - { -#if defined(USE_WORKAROUND_FOR_ANOMALY_192) - *(volatile uint32_t *)0x40000C34 = 0x00000000; -#endif - nrf_clock_event_clear(NRF_CLOCK_EVENT_DONE); - NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRF_CLOCK_EVENT_DONE)); - nrf_clock_int_disable(NRF_CLOCK_INT_DONE_MASK); - m_clock_cb.cal_state = CAL_STATE_IDLE; - m_clock_cb.event_handler(NRFX_CLOCK_EVT_CAL_DONE); - } -#endif // CALIBRATION_SUPPORT -} - -#undef NRF_CLOCK_LFCLK_RC -#undef NRF_CLOCK_LFCLK_Xtal -#undef NRF_CLOCK_LFCLK_Synth - -#endif // NRFX_CHECK(NRFX_CLOCK_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_comp.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_comp.c deleted file mode 100644 index fe7be5baf5..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_comp.c +++ /dev/null @@ -1,211 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include - -#if NRFX_CHECK(NRFX_COMP_ENABLED) - -#include -#include "prs/nrfx_prs.h" - -#define NRFX_LOG_MODULE COMP -#include - -#define EVT_TO_STR(event) \ - (event == NRF_COMP_EVENT_READY ? "NRF_COMP_EVENT_READY" : \ - (event == NRF_COMP_EVENT_DOWN ? "NRF_COMP_EVENT_DOWN" : \ - (event == NRF_COMP_EVENT_UP ? "NRF_COMP_EVENT_UP" : \ - (event == NRF_COMP_EVENT_CROSS ? "NRF_COMP_EVENT_CROSS" : \ - "UNKNOWN ERROR")))) - - -static nrfx_comp_event_handler_t m_comp_event_handler = NULL; -static nrfx_drv_state_t m_state = NRFX_DRV_STATE_UNINITIALIZED; - -static void comp_execute_handler(nrf_comp_event_t event, uint32_t event_mask) -{ - if (nrf_comp_event_check(event) && nrf_comp_int_enable_check(event_mask)) - { - nrf_comp_event_clear(event); - NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(event)); - - m_comp_event_handler(event); - } -} - -void nrfx_comp_irq_handler(void) -{ - comp_execute_handler(NRF_COMP_EVENT_READY, COMP_INTENSET_READY_Msk); - comp_execute_handler(NRF_COMP_EVENT_DOWN, COMP_INTENSET_DOWN_Msk); - comp_execute_handler(NRF_COMP_EVENT_UP, COMP_INTENSET_UP_Msk); - comp_execute_handler(NRF_COMP_EVENT_CROSS, COMP_INTENSET_CROSS_Msk); -} - - -nrfx_err_t nrfx_comp_init(nrfx_comp_config_t const * p_config, - nrfx_comp_event_handler_t event_handler) -{ - NRFX_ASSERT(p_config); - NRFX_ASSERT(event_handler); - nrfx_err_t err_code; - - if (m_state != NRFX_DRV_STATE_UNINITIALIZED) - { // COMP driver is already initialized - err_code = NRFX_ERROR_INVALID_STATE; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - m_comp_event_handler = event_handler; - -#if NRFX_CHECK(NRFX_PRS_ENABLED) - if (nrfx_prs_acquire(NRF_COMP, nrfx_comp_irq_handler) != NRFX_SUCCESS) - { - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } -#endif - - nrf_comp_task_trigger(NRF_COMP_TASK_STOP); - nrf_comp_enable(); - - // Clear events to be sure there are no leftovers. - nrf_comp_event_clear(NRF_COMP_EVENT_READY); - nrf_comp_event_clear(NRF_COMP_EVENT_DOWN); - nrf_comp_event_clear(NRF_COMP_EVENT_UP); - nrf_comp_event_clear(NRF_COMP_EVENT_CROSS); - - nrf_comp_ref_set(p_config->reference); - - //If external source is chosen, write to appropriate register. - if (p_config->reference == COMP_REFSEL_REFSEL_ARef) - { - nrf_comp_ext_ref_set(p_config->ext_ref); - } - - nrf_comp_th_set(p_config->threshold); - nrf_comp_main_mode_set(p_config->main_mode); - nrf_comp_speed_mode_set(p_config->speed_mode); - nrf_comp_hysteresis_set(p_config->hyst); -#if defined (COMP_ISOURCE_ISOURCE_Msk) - nrf_comp_isource_set(p_config->isource); -#endif - nrf_comp_shorts_disable(NRFX_COMP_SHORT_STOP_AFTER_CROSS_EVT | - NRFX_COMP_SHORT_STOP_AFTER_UP_EVT | - NRFX_COMP_SHORT_STOP_AFTER_DOWN_EVT); - nrf_comp_int_disable(COMP_INTENCLR_CROSS_Msk | - COMP_INTENCLR_UP_Msk | - COMP_INTENCLR_DOWN_Msk | - COMP_INTENCLR_READY_Msk); - - nrf_comp_input_select(p_config->input); - - NRFX_IRQ_PRIORITY_SET(COMP_LPCOMP_IRQn, p_config->interrupt_priority); - NRFX_IRQ_ENABLE(COMP_LPCOMP_IRQn); - - m_state = NRFX_DRV_STATE_INITIALIZED; - - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -void nrfx_comp_uninit(void) -{ - NRFX_ASSERT(m_state != NRFX_DRV_STATE_UNINITIALIZED); - NRFX_IRQ_DISABLE(COMP_LPCOMP_IRQn); - nrf_comp_disable(); -#if NRFX_CHECK(NRFX_PRS_ENABLED) - nrfx_prs_release(NRF_COMP); -#endif - m_state = NRFX_DRV_STATE_UNINITIALIZED; - m_comp_event_handler = NULL; - NRFX_LOG_INFO("Uninitialized."); -} - -void nrfx_comp_pin_select(nrf_comp_input_t psel) -{ - bool comp_enable_state = nrf_comp_enable_check(); - nrf_comp_task_trigger(NRF_COMP_TASK_STOP); - if (m_state == NRFX_DRV_STATE_POWERED_ON) - { - m_state = NRFX_DRV_STATE_INITIALIZED; - } - nrf_comp_disable(); - nrf_comp_input_select(psel); - if (comp_enable_state == true) - { - nrf_comp_enable(); - } -} - -void nrfx_comp_start(uint32_t comp_int_mask, uint32_t comp_shorts_mask) -{ - NRFX_ASSERT(m_state == NRFX_DRV_STATE_INITIALIZED); - nrf_comp_int_enable(comp_int_mask); - nrf_comp_shorts_enable(comp_shorts_mask); - nrf_comp_task_trigger(NRF_COMP_TASK_START); - m_state = NRFX_DRV_STATE_POWERED_ON; - NRFX_LOG_INFO("Enabled."); -} - -void nrfx_comp_stop(void) -{ - NRFX_ASSERT(m_state == NRFX_DRV_STATE_POWERED_ON); - nrf_comp_shorts_disable(UINT32_MAX); - nrf_comp_int_disable(UINT32_MAX); - nrf_comp_task_trigger(NRF_COMP_TASK_STOP); - m_state = NRFX_DRV_STATE_INITIALIZED; - NRFX_LOG_INFO("Disabled."); -} - -uint32_t nrfx_comp_sample() -{ - NRFX_ASSERT(m_state == NRFX_DRV_STATE_POWERED_ON); - nrf_comp_task_trigger(NRF_COMP_TASK_SAMPLE); - return nrf_comp_result_get(); -} - -#endif // NRFX_CHECK(NRFX_COMP_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_gpiote.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_gpiote.c deleted file mode 100644 index 9722b3b994..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_gpiote.c +++ /dev/null @@ -1,826 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include - -#if NRFX_CHECK(NRFX_GPIOTE_ENABLED) - -#include -#include "nrf_bitmask.h" -#include - -#define NRFX_LOG_MODULE GPIOTE -#include - - -#define FORBIDDEN_HANDLER_ADDRESS ((nrfx_gpiote_evt_handler_t)UINT32_MAX) -#define PIN_NOT_USED (-1) -#define PIN_USED (-2) -#define NO_CHANNELS (-1) -#define SENSE_FIELD_POS (6) -#define SENSE_FIELD_MASK (0xC0) - -/** - * @brief Macro for converting task-event index to an address of an event register. - * - * Macro utilizes the fact that registers are grouped together in ascending order. - */ -#define TE_IDX_TO_EVENT_ADDR(idx) (nrf_gpiote_events_t)((uint32_t)NRF_GPIOTE_EVENTS_IN_0 + \ - (sizeof(uint32_t) * (idx))) - -/** - * @brief Macro for converting task-event index of OUT task to an address of a task register. - * - * Macro utilizes the fact that registers are grouped together in ascending order. - */ -#define TE_OUT_IDX_TO_TASK_ADDR(idx) (nrf_gpiote_tasks_t)((uint32_t)NRF_GPIOTE_TASKS_OUT_0 + \ - (sizeof(uint32_t) * (idx))) - -#if defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__NRFX_DOXYGEN__) -/** - * @brief Macro for converting task-event index of SET task to an address of a task register. - * - * Macro utilizes the fact that registers are grouped together in ascending order. - */ -#define TE_SET_IDX_TO_TASK_ADDR(idx) (nrf_gpiote_tasks_t)((uint32_t)NRF_GPIOTE_TASKS_SET_0 + \ - (sizeof(uint32_t) * (idx))) - -#endif // defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__NRFX_DOXYGEN__) - -#if defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__) -/** - * @brief Macro for converting task-event index of CLR task to an address of a task register. - * - * Macro utilizes the fact that registers are grouped together in ascending order. - */ -#define TE_CLR_IDX_TO_TASK_ADDR(idx) (nrf_gpiote_tasks_t)((uint32_t)NRF_GPIOTE_TASKS_CLR_0 + \ - (sizeof(uint32_t) * (idx))) - -#endif // defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__) - -/*lint -save -e571*/ /* Suppress "Warning 571: Suspicious cast" */ -typedef struct -{ - nrfx_gpiote_evt_handler_t handlers[GPIOTE_CH_NUM + NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS]; - int8_t pin_assignments[NUMBER_OF_PINS]; - int8_t port_handlers_pins[NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS]; - uint8_t configured_pins[((NUMBER_OF_PINS)+7) / 8]; - nrfx_drv_state_t state; -} gpiote_control_block_t; - -static gpiote_control_block_t m_cb; - -__STATIC_INLINE bool pin_in_use(uint32_t pin) -{ - return (m_cb.pin_assignments[pin] != PIN_NOT_USED); -} - - -__STATIC_INLINE bool pin_in_use_as_non_task_out(uint32_t pin) -{ - return (m_cb.pin_assignments[pin] == PIN_USED); -} - - -__STATIC_INLINE bool pin_in_use_by_te(uint32_t pin) -{ - return (m_cb.pin_assignments[pin] >= 0 && m_cb.pin_assignments[pin] < GPIOTE_CH_NUM) ? - true : false; -} - - -__STATIC_INLINE bool pin_in_use_by_port(uint32_t pin) -{ - return (m_cb.pin_assignments[pin] >= GPIOTE_CH_NUM); -} - - -__STATIC_INLINE bool pin_in_use_by_gpiote(uint32_t pin) -{ - return (m_cb.pin_assignments[pin] >= 0); -} - - -__STATIC_INLINE void pin_in_use_by_te_set(uint32_t pin, - uint32_t channel_id, - nrfx_gpiote_evt_handler_t handler, - bool is_channel) -{ - m_cb.pin_assignments[pin] = channel_id; - m_cb.handlers[channel_id] = handler; - if (!is_channel) - { - m_cb.port_handlers_pins[channel_id - GPIOTE_CH_NUM] = (int8_t)pin; - } -} - - -__STATIC_INLINE void pin_in_use_set(uint32_t pin) -{ - m_cb.pin_assignments[pin] = PIN_USED; -} - - -__STATIC_INLINE void pin_in_use_clear(uint32_t pin) -{ - m_cb.pin_assignments[pin] = PIN_NOT_USED; -} - - -__STATIC_INLINE void pin_configured_set(uint32_t pin) -{ - nrf_bitmask_bit_set(pin, m_cb.configured_pins); -} - -__STATIC_INLINE void pin_configured_clear(uint32_t pin) -{ - nrf_bitmask_bit_clear(pin, m_cb.configured_pins); -} - -__STATIC_INLINE bool pin_configured_check(uint32_t pin) -{ - return 0 != nrf_bitmask_bit_is_set(pin, m_cb.configured_pins); -} - -__STATIC_INLINE int8_t channel_port_get(uint32_t pin) -{ - return m_cb.pin_assignments[pin]; -} - - -__STATIC_INLINE nrfx_gpiote_evt_handler_t channel_handler_get(uint32_t channel) -{ - return m_cb.handlers[channel]; -} - - -static int8_t channel_port_alloc(uint32_t pin, nrfx_gpiote_evt_handler_t handler, bool channel) -{ - int8_t channel_id = NO_CHANNELS; - uint32_t i; - - uint32_t start_idx = channel ? 0 : GPIOTE_CH_NUM; - uint32_t end_idx = - channel ? GPIOTE_CH_NUM : (GPIOTE_CH_NUM + NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS); - - // critical section - - for (i = start_idx; i < end_idx; i++) - { - if (m_cb.handlers[i] == FORBIDDEN_HANDLER_ADDRESS) - { - pin_in_use_by_te_set(pin, i, handler, channel); - channel_id = i; - break; - } - } - // critical section - return channel_id; -} - - -static void channel_free(uint8_t channel_id) -{ - m_cb.handlers[channel_id] = FORBIDDEN_HANDLER_ADDRESS; - if (channel_id >= GPIOTE_CH_NUM) - { - m_cb.port_handlers_pins[channel_id - GPIOTE_CH_NUM] = (int8_t)PIN_NOT_USED; - } -} - - -nrfx_err_t nrfx_gpiote_init(void) -{ - nrfx_err_t err_code; - - if (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED) - { - err_code = NRFX_ERROR_INVALID_STATE; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - uint8_t i; - - for (i = 0; i < NUMBER_OF_PINS; i++) - { - pin_in_use_clear(i); - } - - for (i = 0; i < (GPIOTE_CH_NUM + NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS); i++) - { - channel_free(i); - } - - memset(m_cb.configured_pins, 0, sizeof(m_cb.configured_pins)); - - NRFX_IRQ_PRIORITY_SET(GPIOTE_IRQn, NRFX_GPIOTE_CONFIG_IRQ_PRIORITY); - NRFX_IRQ_ENABLE(GPIOTE_IRQn); - nrf_gpiote_event_clear(NRF_GPIOTE_EVENTS_PORT); - nrf_gpiote_int_enable(GPIOTE_INTENSET_PORT_Msk); - m_cb.state = NRFX_DRV_STATE_INITIALIZED; - - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - - -bool nrfx_gpiote_is_init(void) -{ - return (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED) ? true : false; -} - - -void nrfx_gpiote_uninit(void) -{ - NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); - - uint32_t i; - - for (i = 0; i < NUMBER_OF_PINS; i++) - { - if (pin_in_use_as_non_task_out(i)) - { - nrfx_gpiote_out_uninit(i); - } - else if ( pin_in_use_by_gpiote(i)) - { - /* Disable gpiote_in is having the same effect on out pin as gpiote_out_uninit on - * so it can be called on all pins used by GPIOTE. - */ - nrfx_gpiote_in_uninit(i); - } - } - m_cb.state = NRFX_DRV_STATE_UNINITIALIZED; - NRFX_LOG_INFO("Uninitialized."); -} - - -nrfx_err_t nrfx_gpiote_out_init(nrfx_gpiote_pin_t pin, - nrfx_gpiote_out_config_t const * p_config) -{ - NRFX_ASSERT(pin < NUMBER_OF_PINS); - NRFX_ASSERT(m_cb.state == NRFX_DRV_STATE_INITIALIZED); - NRFX_ASSERT(p_config); - - nrfx_err_t err_code = NRFX_SUCCESS; - - if (pin_in_use(pin)) - { - err_code = NRFX_ERROR_INVALID_STATE; - } - else - { - if (p_config->task_pin) - { - int8_t channel = channel_port_alloc(pin, NULL, true); - - if (channel != NO_CHANNELS) - { - nrf_gpiote_task_configure((uint32_t)channel, - pin, - p_config->action, - p_config->init_state); - } - else - { - err_code = NRFX_ERROR_NO_MEM; - } - } - else - { - pin_in_use_set(pin); - } - - if (err_code == NRFX_SUCCESS) - { - if (p_config->init_state == NRF_GPIOTE_INITIAL_VALUE_HIGH) - { - nrf_gpio_pin_set(pin); - } - else - { - nrf_gpio_pin_clear(pin); - } - - nrf_gpio_cfg_output(pin); - pin_configured_set(pin); - } - } - - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - - -void nrfx_gpiote_out_uninit(nrfx_gpiote_pin_t pin) -{ - NRFX_ASSERT(pin < NUMBER_OF_PINS); - NRFX_ASSERT(pin_in_use(pin)); - - if (pin_in_use_by_te(pin)) - { - channel_free((uint8_t)channel_port_get(pin)); - nrf_gpiote_te_default((uint32_t)channel_port_get(pin)); - } - pin_in_use_clear(pin); - - if (pin_configured_check(pin)) - { - nrf_gpio_cfg_default(pin); - pin_configured_clear(pin); - } -} - - -void nrfx_gpiote_out_set(nrfx_gpiote_pin_t pin) -{ - NRFX_ASSERT(pin < NUMBER_OF_PINS); - NRFX_ASSERT(pin_in_use(pin)); - NRFX_ASSERT(!pin_in_use_by_te(pin)); - - nrf_gpio_pin_set(pin); -} - - -void nrfx_gpiote_out_clear(nrfx_gpiote_pin_t pin) -{ - NRFX_ASSERT(pin < NUMBER_OF_PINS); - NRFX_ASSERT(pin_in_use(pin)); - NRFX_ASSERT(!pin_in_use_by_te(pin)); - - nrf_gpio_pin_clear(pin); -} - - -void nrfx_gpiote_out_toggle(nrfx_gpiote_pin_t pin) -{ - NRFX_ASSERT(pin < NUMBER_OF_PINS); - NRFX_ASSERT(pin_in_use(pin)); - NRFX_ASSERT(!pin_in_use_by_te(pin)); - - nrf_gpio_pin_toggle(pin); -} - - -void nrfx_gpiote_out_task_enable(nrfx_gpiote_pin_t pin) -{ - NRFX_ASSERT(pin < NUMBER_OF_PINS); - NRFX_ASSERT(pin_in_use(pin)); - NRFX_ASSERT(pin_in_use_by_te(pin)); - - nrf_gpiote_task_enable((uint32_t)m_cb.pin_assignments[pin]); -} - - -void nrfx_gpiote_out_task_disable(nrfx_gpiote_pin_t pin) -{ - NRFX_ASSERT(pin < NUMBER_OF_PINS); - NRFX_ASSERT(pin_in_use(pin)); - NRFX_ASSERT(pin_in_use_by_te(pin)); - - nrf_gpiote_task_disable((uint32_t)m_cb.pin_assignments[pin]); -} - - -uint32_t nrfx_gpiote_out_task_addr_get(nrfx_gpiote_pin_t pin) -{ - NRFX_ASSERT(pin < NUMBER_OF_PINS); - NRFX_ASSERT(pin_in_use_by_te(pin)); - - nrf_gpiote_tasks_t task = TE_OUT_IDX_TO_TASK_ADDR((uint32_t)channel_port_get(pin)); - return nrf_gpiote_task_addr_get(task); -} - - -#if defined(GPIOTE_FEATURE_SET_PRESENT) -uint32_t nrfx_gpiote_set_task_addr_get(nrfx_gpiote_pin_t pin) -{ - NRFX_ASSERT(pin < NUMBER_OF_PINS); - NRFX_ASSERT(pin_in_use_by_te(pin)); - - nrf_gpiote_tasks_t task = TE_SET_IDX_TO_TASK_ADDR((uint32_t)channel_port_get(pin)); - return nrf_gpiote_task_addr_get(task); -} - - -#endif // defined(GPIOTE_FEATURE_SET_PRESENT) - -#if defined(GPIOTE_FEATURE_CLR_PRESENT) -uint32_t nrfx_gpiote_clr_task_addr_get(nrfx_gpiote_pin_t pin) -{ - NRFX_ASSERT(pin < NUMBER_OF_PINS); - NRFX_ASSERT(pin_in_use_by_te(pin)); - - nrf_gpiote_tasks_t task = TE_CLR_IDX_TO_TASK_ADDR((uint32_t)channel_port_get(pin)); - return nrf_gpiote_task_addr_get(task); -} - - -#endif // defined(GPIOTE_FEATURE_CLR_PRESENT) - -void nrfx_gpiote_out_task_force(nrfx_gpiote_pin_t pin, uint8_t state) -{ - NRFX_ASSERT(pin < NUMBER_OF_PINS); - NRFX_ASSERT(pin_in_use(pin)); - NRFX_ASSERT(pin_in_use_by_te(pin)); - - nrf_gpiote_outinit_t init_val = - state ? NRF_GPIOTE_INITIAL_VALUE_HIGH : NRF_GPIOTE_INITIAL_VALUE_LOW; - nrf_gpiote_task_force((uint32_t)m_cb.pin_assignments[pin], init_val); -} - - -void nrfx_gpiote_out_task_trigger(nrfx_gpiote_pin_t pin) -{ - NRFX_ASSERT(pin < NUMBER_OF_PINS); - NRFX_ASSERT(pin_in_use(pin)); - NRFX_ASSERT(pin_in_use_by_te(pin)); - - nrf_gpiote_tasks_t task = TE_OUT_IDX_TO_TASK_ADDR((uint32_t)channel_port_get(pin)); - nrf_gpiote_task_set(task); -} - - -#if defined(GPIOTE_FEATURE_SET_PRESENT) -void nrfx_gpiote_set_task_trigger(nrfx_gpiote_pin_t pin) -{ - NRFX_ASSERT(pin < NUMBER_OF_PINS); - NRFX_ASSERT(pin_in_use(pin)); - NRFX_ASSERT(pin_in_use_by_te(pin)); - - nrf_gpiote_tasks_t task = TE_SET_IDX_TO_TASK_ADDR((uint32_t)channel_port_get(pin)); - nrf_gpiote_task_set(task); -} - - -#endif // defined(GPIOTE_FEATURE_SET_PRESENT) - -#if defined(GPIOTE_FEATURE_CLR_PRESENT) -void nrfx_gpiote_clr_task_trigger(nrfx_gpiote_pin_t pin) -{ - NRFX_ASSERT(pin < NUMBER_OF_PINS); - NRFX_ASSERT(pin_in_use(pin)); - NRFX_ASSERT(pin_in_use_by_te(pin)); - - nrf_gpiote_tasks_t task = TE_CLR_IDX_TO_TASK_ADDR((uint32_t)channel_port_get(pin)); - nrf_gpiote_task_set(task); -} - - -#endif // defined(GPIOTE_FEATURE_CLR_PRESENT) - -nrfx_err_t nrfx_gpiote_in_init(nrfx_gpiote_pin_t pin, - nrfx_gpiote_in_config_t const * p_config, - nrfx_gpiote_evt_handler_t evt_handler) -{ - NRFX_ASSERT(pin < NUMBER_OF_PINS); - nrfx_err_t err_code = NRFX_SUCCESS; - - /* Only one GPIOTE channel can be assigned to one physical pin. */ - if (pin_in_use_by_gpiote(pin)) - { - err_code = NRFX_ERROR_INVALID_STATE; - } - else - { - int8_t channel = channel_port_alloc(pin, evt_handler, p_config->hi_accuracy); - if (channel != NO_CHANNELS) - { - if (!p_config->skip_gpio_setup) - { - if (p_config->is_watcher) - { - nrf_gpio_cfg_watcher(pin); - } - else - { - nrf_gpio_cfg_input(pin, p_config->pull); - } - pin_configured_set(pin); - } - - if (p_config->hi_accuracy) - { - nrf_gpiote_event_configure((uint32_t)channel, pin, p_config->sense); - } - else - { - m_cb.port_handlers_pins[channel - - GPIOTE_CH_NUM] |= (p_config->sense) << SENSE_FIELD_POS; - } - } - else - { - err_code = NRFX_ERROR_NO_MEM; - } - } - - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -void nrfx_gpiote_in_event_enable(nrfx_gpiote_pin_t pin, bool int_enable) -{ - NRFX_ASSERT(pin < NUMBER_OF_PINS); - NRFX_ASSERT(pin_in_use_by_gpiote(pin)); - if (pin_in_use_by_port(pin)) - { - uint8_t pin_and_sense = (uint8_t) - m_cb.port_handlers_pins[channel_port_get(pin) - GPIOTE_CH_NUM]; - nrf_gpiote_polarity_t polarity = - (nrf_gpiote_polarity_t)(pin_and_sense >> SENSE_FIELD_POS); - nrf_gpio_pin_sense_t sense; - if (polarity == NRF_GPIOTE_POLARITY_TOGGLE) - { - /* read current pin state and set for next sense to oposit */ - sense = (nrf_gpio_pin_read(pin)) ? - NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH; - } - else - { - sense = (polarity == NRF_GPIOTE_POLARITY_LOTOHI) ? - NRF_GPIO_PIN_SENSE_HIGH : NRF_GPIO_PIN_SENSE_LOW; - } - nrf_gpio_cfg_sense_set(pin, sense); - } - else if (pin_in_use_by_te(pin)) - { - int32_t channel = (int32_t)channel_port_get(pin); - nrf_gpiote_events_t event = TE_IDX_TO_EVENT_ADDR((uint32_t)channel); - - nrf_gpiote_event_enable((uint32_t)channel); - - nrf_gpiote_event_clear(event); - if (int_enable) - { - nrfx_gpiote_evt_handler_t handler = channel_handler_get((uint32_t)channel_port_get(pin)); - // Enable the interrupt only if event handler was provided. - if (handler) - { - nrf_gpiote_int_enable(1 << channel); - } - } - } -} - - -void nrfx_gpiote_in_event_disable(nrfx_gpiote_pin_t pin) -{ - NRFX_ASSERT(pin < NUMBER_OF_PINS); - NRFX_ASSERT(pin_in_use_by_gpiote(pin)); - if (pin_in_use_by_port(pin)) - { - nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE); - } - else if (pin_in_use_by_te(pin)) - { - int32_t channel = (int32_t)channel_port_get(pin); - nrf_gpiote_event_disable((uint32_t)channel); - nrf_gpiote_int_disable(1 << channel); - } -} - - -void nrfx_gpiote_in_uninit(nrfx_gpiote_pin_t pin) -{ - NRFX_ASSERT(pin < NUMBER_OF_PINS); - NRFX_ASSERT(pin_in_use_by_gpiote(pin)); - nrfx_gpiote_in_event_disable(pin); - if (pin_in_use_by_te(pin)) - { - nrf_gpiote_te_default((uint32_t)channel_port_get(pin)); - } - if (pin_configured_check(pin)) - { - nrf_gpio_cfg_default(pin); - pin_configured_clear(pin); - } - channel_free((uint8_t)channel_port_get(pin)); - pin_in_use_clear(pin); -} - - -bool nrfx_gpiote_in_is_set(nrfx_gpiote_pin_t pin) -{ - NRFX_ASSERT(pin < NUMBER_OF_PINS); - return nrf_gpio_pin_read(pin) ? true : false; -} - - -uint32_t nrfx_gpiote_in_event_addr_get(nrfx_gpiote_pin_t pin) -{ - NRFX_ASSERT(pin < NUMBER_OF_PINS); - NRFX_ASSERT(pin_in_use_by_port(pin) || pin_in_use_by_te(pin)); - - nrf_gpiote_events_t event = NRF_GPIOTE_EVENTS_PORT; - - if (pin_in_use_by_te(pin)) - { - event = TE_IDX_TO_EVENT_ADDR((uint32_t)channel_port_get(pin)); - } - return nrf_gpiote_event_addr_get(event); -} - - -void nrfx_gpiote_irq_handler(void) -{ - uint32_t status = 0; - uint32_t input[GPIO_COUNT] = {0}; - - /* collect status of all GPIOTE pin events. Processing is done once all are collected and cleared.*/ - uint32_t i; - nrf_gpiote_events_t event = NRF_GPIOTE_EVENTS_IN_0; - uint32_t mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK; - - for (i = 0; i < GPIOTE_CH_NUM; i++) - { - if (nrf_gpiote_event_is_set(event) && nrf_gpiote_int_is_enabled(mask)) - { - nrf_gpiote_event_clear(event); - status |= mask; - } - mask <<= 1; - /* Incrementing to next event, utilizing the fact that events are grouped together - * in ascending order. */ - event = (nrf_gpiote_events_t)((uint32_t)event + sizeof(uint32_t)); - } - - /* collect PORT status event, if event is set read pins state. Processing is postponed to the - * end of interrupt. */ - if (nrf_gpiote_event_is_set(NRF_GPIOTE_EVENTS_PORT)) - { - nrf_gpiote_event_clear(NRF_GPIOTE_EVENTS_PORT); - status |= (uint32_t)NRF_GPIOTE_INT_PORT_MASK; - nrf_gpio_ports_read(0, GPIO_COUNT, input); - } - - /* Process pin events. */ - if (status & NRF_GPIOTE_INT_IN_MASK) - { - mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK; - - for (i = 0; i < GPIOTE_CH_NUM; i++) - { - if (mask & status) - { - nrfx_gpiote_pin_t pin = nrf_gpiote_event_pin_get(i); - NRFX_LOG_DEBUG("Event in number: %d.", i); - nrf_gpiote_polarity_t polarity = nrf_gpiote_event_polarity_get(i); - nrfx_gpiote_evt_handler_t handler = channel_handler_get(i); - NRFX_LOG_DEBUG("Pin: %d, polarity: %d.", pin, polarity); - if (handler) - { - handler(pin, polarity); - } - } - mask <<= 1; - } - } - - if (status & (uint32_t)NRF_GPIOTE_INT_PORT_MASK) - { - /* Process port event. */ - uint32_t port_idx; - uint8_t repeat = 0; - uint32_t toggle_mask[GPIO_COUNT] = {0}; - uint32_t pins_to_check[GPIO_COUNT]; - - // Faster way of doing memset because in interrupt context. - for (port_idx = 0; port_idx < GPIO_COUNT; port_idx++) - { - pins_to_check[port_idx] = 0xFFFFFFFF; - } - - do - { - repeat = 0; - - for (i = 0; i < NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS; i++) - { - uint8_t pin_and_sense = (uint8_t)m_cb.port_handlers_pins[i]; - nrfx_gpiote_pin_t pin = (pin_and_sense & ~SENSE_FIELD_MASK); - - if ((m_cb.port_handlers_pins[i] != PIN_NOT_USED) - && nrf_bitmask_bit_is_set(pin, pins_to_check)) - { - nrf_gpiote_polarity_t polarity = - (nrf_gpiote_polarity_t)((pin_and_sense & - SENSE_FIELD_MASK) >> SENSE_FIELD_POS); - nrfx_gpiote_evt_handler_t handler = - channel_handler_get((uint32_t)channel_port_get(pin)); - if (handler || (polarity == NRF_GPIOTE_POLARITY_TOGGLE)) - { - if (polarity == NRF_GPIOTE_POLARITY_TOGGLE) - { - nrf_bitmask_bit_set(pin, toggle_mask); - } - nrf_gpio_pin_sense_t sense = nrf_gpio_pin_sense_get(pin); - uint32_t pin_state = nrf_bitmask_bit_is_set(pin, input); - if ((pin_state && (sense == NRF_GPIO_PIN_SENSE_HIGH)) || - (!pin_state && (sense == NRF_GPIO_PIN_SENSE_LOW)) ) - { - NRFX_LOG_DEBUG("PORT event for pin: %d, polarity: %d.", pin, polarity); - if (polarity == NRF_GPIOTE_POLARITY_TOGGLE) - { - nrf_gpio_pin_sense_t next_sense = - (sense == NRF_GPIO_PIN_SENSE_HIGH) ? - NRF_GPIO_PIN_SENSE_LOW : - NRF_GPIO_PIN_SENSE_HIGH; - nrf_gpio_cfg_sense_set(pin, next_sense); - ++repeat; - - } - if (handler) - { - handler(pin, polarity); - } - } - } - } - } - - if (repeat) - { - // When one of the pins in low-accuracy and toggle mode becomes active, - // it's sense mode is inverted to clear the internal SENSE signal. - // State of any other enabled low-accuracy input in toggle mode must be checked - // explicitly, because it does not trigger the interrput when SENSE signal is active. - // For more information about SENSE functionality, refer to Product Specification. - - uint32_t new_input[GPIO_COUNT]; - bool input_unchanged = true; - nrf_gpio_ports_read(0, GPIO_COUNT, new_input); - - // Faster way of doing memcmp because in interrupt context. - for (port_idx = 0; port_idx < GPIO_COUNT; port_idx++) - { - if (new_input[port_idx] != input[port_idx]) - { - input_unchanged = false; - break; - } - } - - if (input_unchanged) - { - // No change. - repeat = 0; - } - else - { - // Faster way of doing memcpy because in interrupt context. - for (port_idx = 0; port_idx < GPIO_COUNT; port_idx++) - { - input[port_idx] = new_input[port_idx]; - pins_to_check[port_idx] = toggle_mask[port_idx]; - } - } - } - } - while (repeat); - } -} - - -/*lint -restore*/ -#endif // NRFX_CHECK(NRFX_GPIOTE_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_i2s.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_i2s.c deleted file mode 100644 index f212986acb..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_i2s.c +++ /dev/null @@ -1,420 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include - -#if NRFX_CHECK(NRFX_I2S_ENABLED) - -#include -#include - -#define NRFX_LOG_MODULE I2S -#include - -#define EVT_TO_STR(event) \ - (event == NRF_I2S_EVENT_RXPTRUPD ? "NRF_I2S_EVENT_RXPTRUPD" : \ - (event == NRF_I2S_EVENT_TXPTRUPD ? "NRF_I2S_EVENT_TXPTRUPD" : \ - (event == NRF_I2S_EVENT_STOPPED ? "NRF_I2S_EVENT_STOPPED" : \ - "UNKNOWN EVENT"))) - -// Control block - driver instance local data. -typedef struct -{ - nrfx_i2s_data_handler_t handler; - nrfx_drv_state_t state; - - bool use_rx : 1; - bool use_tx : 1; - bool rx_ready : 1; - bool tx_ready : 1; - bool buffers_needed : 1; - bool buffers_reused : 1; - - uint16_t buffer_size; - nrfx_i2s_buffers_t next_buffers; - nrfx_i2s_buffers_t current_buffers; -} i2s_control_block_t; -static i2s_control_block_t m_cb; - - -static void configure_pins(nrfx_i2s_config_t const * p_config) -{ - uint32_t mck_pin, sdout_pin, sdin_pin; - - // Configure pins used by the peripheral: - - // - SCK and LRCK (required) - depending on the mode of operation these - // pins are configured as outputs (in Master mode) or inputs (in Slave - // mode). - if (p_config->mode == NRF_I2S_MODE_MASTER) - { - nrf_gpio_cfg_output(p_config->sck_pin); - nrf_gpio_cfg_output(p_config->lrck_pin); - } - else - { - nrf_gpio_cfg_input(p_config->sck_pin, NRF_GPIO_PIN_NOPULL); - nrf_gpio_cfg_input(p_config->lrck_pin, NRF_GPIO_PIN_NOPULL); - } - - // - MCK (optional) - always output, - if (p_config->mck_pin != NRFX_I2S_PIN_NOT_USED) - { - mck_pin = p_config->mck_pin; - nrf_gpio_cfg_output(mck_pin); - } - else - { - mck_pin = NRF_I2S_PIN_NOT_CONNECTED; - } - - // - SDOUT (optional) - always output, - if (p_config->sdout_pin != NRFX_I2S_PIN_NOT_USED) - { - sdout_pin = p_config->sdout_pin; - nrf_gpio_cfg_output(sdout_pin); - } - else - { - sdout_pin = NRF_I2S_PIN_NOT_CONNECTED; - } - - // - SDIN (optional) - always input. - if (p_config->sdin_pin != NRFX_I2S_PIN_NOT_USED) - { - sdin_pin = p_config->sdin_pin; - nrf_gpio_cfg_input(sdin_pin, NRF_GPIO_PIN_NOPULL); - } - else - { - sdin_pin = NRF_I2S_PIN_NOT_CONNECTED; - } - - nrf_i2s_pins_set(NRF_I2S, - p_config->sck_pin, - p_config->lrck_pin, - mck_pin, - sdout_pin, - sdin_pin); -} - - -nrfx_err_t nrfx_i2s_init(nrfx_i2s_config_t const * p_config, - nrfx_i2s_data_handler_t handler) -{ - NRFX_ASSERT(p_config); - NRFX_ASSERT(handler); - - nrfx_err_t err_code; - - if (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED) - { - err_code = NRFX_ERROR_INVALID_STATE; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - if (!nrf_i2s_configure(NRF_I2S, - p_config->mode, - p_config->format, - p_config->alignment, - p_config->sample_width, - p_config->channels, - p_config->mck_setup, - p_config->ratio)) - { - err_code = NRFX_ERROR_INVALID_PARAM; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - configure_pins(p_config); - - m_cb.handler = handler; - - NRFX_IRQ_PRIORITY_SET(I2S_IRQn, p_config->irq_priority); - NRFX_IRQ_ENABLE(I2S_IRQn); - - m_cb.state = NRFX_DRV_STATE_INITIALIZED; - - NRFX_LOG_INFO("Initialized."); - return NRFX_SUCCESS; -} - - -void nrfx_i2s_uninit(void) -{ - NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); - - nrfx_i2s_stop(); - - NRFX_IRQ_DISABLE(I2S_IRQn); - - nrf_i2s_pins_set(NRF_I2S, - NRF_I2S_PIN_NOT_CONNECTED, - NRF_I2S_PIN_NOT_CONNECTED, - NRF_I2S_PIN_NOT_CONNECTED, - NRF_I2S_PIN_NOT_CONNECTED, - NRF_I2S_PIN_NOT_CONNECTED); - - m_cb.state = NRFX_DRV_STATE_UNINITIALIZED; - NRFX_LOG_INFO("Uninitialized."); -} - - -nrfx_err_t nrfx_i2s_start(nrfx_i2s_buffers_t const * p_initial_buffers, - uint16_t buffer_size, - uint8_t flags) -{ - NRFX_ASSERT(p_initial_buffers != NULL); - NRFX_ASSERT(p_initial_buffers->p_rx_buffer != NULL || - p_initial_buffers->p_tx_buffer != NULL); - NRFX_ASSERT(buffer_size != 0); - (void)(flags); - - nrfx_err_t err_code; - - if (m_cb.state != NRFX_DRV_STATE_INITIALIZED) - { - err_code = NRFX_ERROR_INVALID_STATE; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - if (((p_initial_buffers->p_rx_buffer != NULL) - && !nrfx_is_in_ram(p_initial_buffers->p_rx_buffer)) - || - ((p_initial_buffers->p_tx_buffer != NULL) - && !nrfx_is_in_ram(p_initial_buffers->p_tx_buffer))) - { - err_code = NRFX_ERROR_INVALID_ADDR; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - m_cb.use_rx = (p_initial_buffers->p_rx_buffer != NULL); - m_cb.use_tx = (p_initial_buffers->p_tx_buffer != NULL); - m_cb.rx_ready = false; - m_cb.tx_ready = false; - m_cb.buffers_needed = false; - m_cb.buffer_size = buffer_size; - - // Set the provided initial buffers as next, they will become the current - // ones after the IRQ handler is called for the first time, what will occur - // right after the START task is triggered. - m_cb.next_buffers = *p_initial_buffers; - m_cb.current_buffers.p_rx_buffer = NULL; - m_cb.current_buffers.p_tx_buffer = NULL; - - nrf_i2s_transfer_set(NRF_I2S, - m_cb.buffer_size, - m_cb.next_buffers.p_rx_buffer, - m_cb.next_buffers.p_tx_buffer); - - nrf_i2s_enable(NRF_I2S); - - m_cb.state = NRFX_DRV_STATE_POWERED_ON; - - nrf_i2s_event_clear(NRF_I2S, NRF_I2S_EVENT_RXPTRUPD); - nrf_i2s_event_clear(NRF_I2S, NRF_I2S_EVENT_TXPTRUPD); - nrf_i2s_event_clear(NRF_I2S, NRF_I2S_EVENT_STOPPED); - nrf_i2s_int_enable(NRF_I2S, (m_cb.use_rx ? NRF_I2S_INT_RXPTRUPD_MASK : 0) | - (m_cb.use_tx ? NRF_I2S_INT_TXPTRUPD_MASK : 0) | - NRF_I2S_INT_STOPPED_MASK); - nrf_i2s_task_trigger(NRF_I2S, NRF_I2S_TASK_START); - - NRFX_LOG_INFO("Started."); - return NRFX_SUCCESS; -} - - -nrfx_err_t nrfx_i2s_next_buffers_set(nrfx_i2s_buffers_t const * p_buffers) -{ - NRFX_ASSERT(m_cb.state == NRFX_DRV_STATE_POWERED_ON); - NRFX_ASSERT(p_buffers); - - nrfx_err_t err_code; - - if (!m_cb.buffers_needed) - { - err_code = NRFX_ERROR_INVALID_STATE; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - if (((p_buffers->p_rx_buffer != NULL) - && !nrfx_is_in_ram(p_buffers->p_rx_buffer)) - || - ((p_buffers->p_tx_buffer != NULL) - && !nrfx_is_in_ram(p_buffers->p_tx_buffer))) - { - err_code = NRFX_ERROR_INVALID_ADDR; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - if (m_cb.use_tx) - { - NRFX_ASSERT(p_buffers->p_tx_buffer != NULL); - nrf_i2s_tx_buffer_set(NRF_I2S, p_buffers->p_tx_buffer); - } - if (m_cb.use_rx) - { - NRFX_ASSERT(p_buffers->p_rx_buffer != NULL); - nrf_i2s_rx_buffer_set(NRF_I2S, p_buffers->p_rx_buffer); - } - - m_cb.next_buffers = *p_buffers; - m_cb.buffers_needed = false; - - return NRFX_SUCCESS; -} - - -void nrfx_i2s_stop(void) -{ - NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); - - m_cb.buffers_needed = false; - - // First disable interrupts, then trigger the STOP task, so no spurious - // RXPTRUPD and TXPTRUPD events (see nRF52 anomaly 55) are processed. - nrf_i2s_int_disable(NRF_I2S, NRF_I2S_INT_RXPTRUPD_MASK | - NRF_I2S_INT_TXPTRUPD_MASK); - nrf_i2s_task_trigger(NRF_I2S, NRF_I2S_TASK_STOP); -} - - -void nrfx_i2s_irq_handler(void) -{ - if (nrf_i2s_event_check(NRF_I2S, NRF_I2S_EVENT_TXPTRUPD)) - { - nrf_i2s_event_clear(NRF_I2S, NRF_I2S_EVENT_TXPTRUPD); - m_cb.tx_ready = true; - if (m_cb.use_tx && m_cb.buffers_needed) - { - m_cb.buffers_reused = true; - } - } - if (nrf_i2s_event_check(NRF_I2S, NRF_I2S_EVENT_RXPTRUPD)) - { - nrf_i2s_event_clear(NRF_I2S, NRF_I2S_EVENT_RXPTRUPD); - m_cb.rx_ready = true; - if (m_cb.use_rx && m_cb.buffers_needed) - { - m_cb.buffers_reused = true; - } - } - - if (nrf_i2s_event_check(NRF_I2S, NRF_I2S_EVENT_STOPPED)) - { - nrf_i2s_event_clear(NRF_I2S, NRF_I2S_EVENT_STOPPED); - nrf_i2s_int_disable(NRF_I2S, NRF_I2S_INT_STOPPED_MASK); - nrf_i2s_disable(NRF_I2S); - - // When stopped, release all buffers, including these scheduled for - // the next transfer. - m_cb.handler(&m_cb.current_buffers, 0); - m_cb.handler(&m_cb.next_buffers, 0); - - m_cb.state = NRFX_DRV_STATE_INITIALIZED; - NRFX_LOG_INFO("Stopped."); - } - else - { - // Check if the requested transfer has been completed: - // - full-duplex mode - if ((m_cb.use_tx && m_cb.use_rx && m_cb.tx_ready && m_cb.rx_ready) || - // - TX only mode - (!m_cb.use_rx && m_cb.tx_ready) || - // - RX only mode - (!m_cb.use_tx && m_cb.rx_ready)) - { - m_cb.tx_ready = false; - m_cb.rx_ready = false; - - // If the application did not supply the buffers for the next - // part of the transfer until this moment, the current buffers - // cannot be released, since the I2S peripheral already started - // using them. Signal this situation to the application by - // passing NULL instead of the structure with released buffers. - if (m_cb.buffers_reused) - { - m_cb.buffers_reused = false; - // This will most likely be set at this point. However, there is - // a small time window between TXPTRUPD and RXPTRUPD events, - // and it is theoretically possible that next buffers will be - // set in this window, so to be sure this flag is set to true, - // set it explicitly. - m_cb.buffers_needed = true; - m_cb.handler(NULL, - NRFX_I2S_STATUS_NEXT_BUFFERS_NEEDED); - } - else - { - // Buffers that have been used by the I2S peripheral (current) - // are now released and will be returned to the application, - // and the ones scheduled to be used as next become the current - // ones. - nrfx_i2s_buffers_t released_buffers = m_cb.current_buffers; - m_cb.current_buffers = m_cb.next_buffers; - m_cb.next_buffers.p_rx_buffer = NULL; - m_cb.next_buffers.p_tx_buffer = NULL; - m_cb.buffers_needed = true; - m_cb.handler(&released_buffers, - NRFX_I2S_STATUS_NEXT_BUFFERS_NEEDED); - } - - } - } -} - -#endif // NRFX_CHECK(NRFX_I2S_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_lpcomp.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_lpcomp.c deleted file mode 100644 index f6b447d465..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_lpcomp.c +++ /dev/null @@ -1,174 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include - -#if NRFX_CHECK(NRFX_LPCOMP_ENABLED) - -#include -#include "prs/nrfx_prs.h" - -#define NRFX_LOG_MODULE LPCOMP -#include - -#define EVT_TO_STR(event) \ - (event == NRF_LPCOMP_EVENT_READY ? "NRF_LPCOMP_EVENT_READY" : \ - (event == NRF_LPCOMP_EVENT_DOWN ? "NRF_LPCOMP_EVENT_DOWN" : \ - (event == NRF_LPCOMP_EVENT_UP ? "NRF_LPCOMP_EVENT_UP" : \ - (event == NRF_LPCOMP_EVENT_CROSS ? "NRF_LPCOMP_EVENT_CROSS" : \ - "UNKNOWN EVENT")))) - - -static nrfx_lpcomp_event_handler_t m_lpcomp_event_handler = NULL; -static nrfx_drv_state_t m_state = NRFX_DRV_STATE_UNINITIALIZED; - -static void lpcomp_execute_handler(nrf_lpcomp_event_t event, uint32_t event_mask) -{ - if (nrf_lpcomp_event_check(event) && nrf_lpcomp_int_enable_check(event_mask)) - { - nrf_lpcomp_event_clear(event); - NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(event)); - - m_lpcomp_event_handler(event); - } -} - -void nrfx_lpcomp_irq_handler(void) -{ - lpcomp_execute_handler(NRF_LPCOMP_EVENT_READY, LPCOMP_INTENSET_READY_Msk); - lpcomp_execute_handler(NRF_LPCOMP_EVENT_DOWN, LPCOMP_INTENSET_DOWN_Msk); - lpcomp_execute_handler(NRF_LPCOMP_EVENT_UP, LPCOMP_INTENSET_UP_Msk); - lpcomp_execute_handler(NRF_LPCOMP_EVENT_CROSS, LPCOMP_INTENSET_CROSS_Msk); -} - -nrfx_err_t nrfx_lpcomp_init(nrfx_lpcomp_config_t const * p_config, - nrfx_lpcomp_event_handler_t event_handler) -{ - NRFX_ASSERT(p_config); - NRFX_ASSERT(event_handler); - nrfx_err_t err_code; - - if (m_state != NRFX_DRV_STATE_UNINITIALIZED) - { // LPCOMP driver is already initialized - err_code = NRFX_ERROR_INVALID_STATE; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - m_lpcomp_event_handler = event_handler; - -#if NRFX_CHECK(NRFX_PRS_ENABLED) - if (nrfx_prs_acquire(NRF_LPCOMP, nrfx_lpcomp_irq_handler) != NRFX_SUCCESS) - { - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } -#endif - - nrf_lpcomp_configure(&(p_config->hal)); - - nrf_lpcomp_input_select(p_config->input); - - switch (p_config->hal.detection) - { - case NRF_LPCOMP_DETECT_UP: - nrf_lpcomp_int_enable(LPCOMP_INTENSET_UP_Msk); - break; - - case NRF_LPCOMP_DETECT_DOWN: - nrf_lpcomp_int_enable(LPCOMP_INTENSET_DOWN_Msk); - break; - - case NRF_LPCOMP_DETECT_CROSS: - nrf_lpcomp_int_enable(LPCOMP_INTENSET_CROSS_Msk); - break; - - default: - break; - } - nrf_lpcomp_shorts_enable(NRF_LPCOMP_SHORT_READY_SAMPLE_MASK); - - NRFX_IRQ_PRIORITY_SET(LPCOMP_IRQn, p_config->interrupt_priority); - NRFX_IRQ_ENABLE(LPCOMP_IRQn); - - m_state = NRFX_DRV_STATE_INITIALIZED; - - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -void nrfx_lpcomp_uninit(void) -{ - NRFX_ASSERT(m_state != NRFX_DRV_STATE_UNINITIALIZED); - NRFX_IRQ_DISABLE(LPCOMP_IRQn); - nrfx_lpcomp_disable(); -#if NRFX_CHECK(NRFX_PRS_ENABLED) - nrfx_prs_release(NRF_LPCOMP); -#endif - m_state = NRFX_DRV_STATE_UNINITIALIZED; - m_lpcomp_event_handler = NULL; - NRFX_LOG_INFO("Uninitialized."); -} - -void nrfx_lpcomp_enable(void) -{ - NRFX_ASSERT(m_state == NRFX_DRV_STATE_INITIALIZED); - nrf_lpcomp_enable(); - nrf_lpcomp_task_trigger(NRF_LPCOMP_TASK_START); - m_state = NRFX_DRV_STATE_POWERED_ON; - NRFX_LOG_INFO("Enabled."); -} - -void nrfx_lpcomp_disable(void) -{ - NRFX_ASSERT(m_state == NRFX_DRV_STATE_POWERED_ON); - nrf_lpcomp_disable(); - nrf_lpcomp_task_trigger(NRF_LPCOMP_TASK_STOP); - m_state = NRFX_DRV_STATE_INITIALIZED; - NRFX_LOG_INFO("Disabled."); -} - -#endif // NRFX_CHECK(NRFX_LPCOMP_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_pdm.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_pdm.c deleted file mode 100644 index 135cc4950f..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_pdm.c +++ /dev/null @@ -1,370 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include - -#if NRFX_CHECK(NRFX_PDM_ENABLED) - -#include -#include - -#define NRFX_LOG_MODULE PDM -#include - -#define EVT_TO_STR(event) \ - (event == NRF_PDM_EVENT_STARTED ? "NRF_PDM_EVENT_STARTED" : \ - (event == NRF_PDM_EVENT_STOPPED ? "NRF_PDM_EVENT_STOPPED" : \ - (event == NRF_PDM_EVENT_END ? "NRF_PDM_EVENT_END" : \ - "UNKNOWN EVENT"))) - - -/** @brief PDM interface status. */ -typedef enum -{ - NRFX_PDM_STATE_IDLE, - NRFX_PDM_STATE_RUNNING, - NRFX_PDM_STATE_STARTING, - NRFX_PDM_STATE_STOPPING -} nrfx_pdm_state_t; - -/** @brief PDM interface control block.*/ -typedef struct -{ - nrfx_pdm_event_handler_t event_handler; ///< Event handler function pointer. - int16_t * buff_address[2]; ///< Sample buffers. - uint16_t buff_length[2]; ///< Length of the sample buffers. - nrfx_drv_state_t drv_state; ///< Driver state. - volatile nrfx_pdm_state_t op_state; ///< PDM peripheral operation state. - uint8_t active_buffer; ///< Number of currently active buffer. - uint8_t error; ///< Driver error flag. - volatile uint8_t irq_buff_request; ///< Request the next buffer in the ISR. -} nrfx_pdm_cb_t; - -static nrfx_pdm_cb_t m_cb; - - -void nrfx_pdm_irq_handler(void) -{ - if (nrf_pdm_event_check(NRF_PDM_EVENT_STARTED)) - { - nrf_pdm_event_clear(NRF_PDM_EVENT_STARTED); - NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRF_PDM_EVENT_STARTED)); - - uint8_t finished_buffer = m_cb.active_buffer; - - // Check if the next buffer was set before. - uint8_t next_buffer = (~m_cb.active_buffer) & 0x01; - if (m_cb.buff_address[next_buffer] || - m_cb.op_state == NRFX_PDM_STATE_STARTING) - { - nrfx_pdm_evt_t evt; - evt.error = NRFX_PDM_NO_ERROR; - m_cb.error = 0; - - // Release the full buffer if ready and request the next one. - if (m_cb.op_state == NRFX_PDM_STATE_STARTING) - { - evt.buffer_released = 0; - m_cb.op_state = NRFX_PDM_STATE_RUNNING; - } - else - { - evt.buffer_released = m_cb.buff_address[finished_buffer]; - m_cb.buff_address[finished_buffer] = 0; - m_cb.active_buffer = next_buffer; - } - evt.buffer_requested = true; - m_cb.event_handler(&evt); - } - else - { - // No next buffer available. Report an error. - // Do not request the new buffer as it was already done. - if (m_cb.error == 0) - { - nrfx_pdm_evt_t const evt = { - .buffer_requested = false, - .buffer_released = NULL, - .error = NRFX_PDM_ERROR_OVERFLOW - }; - m_cb.error = 1; - m_cb.event_handler(&evt); - } - } - - if (m_cb.op_state == NRFX_PDM_STATE_STARTING) - { - m_cb.op_state = NRFX_PDM_STATE_RUNNING; - } - } - else if (nrf_pdm_event_check(NRF_PDM_EVENT_STOPPED)) - { - nrf_pdm_event_clear(NRF_PDM_EVENT_STOPPED); - NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRF_PDM_EVENT_STOPPED)); - nrf_pdm_disable(); - m_cb.op_state = NRFX_PDM_STATE_IDLE; - - // Release the buffers. - nrfx_pdm_evt_t evt; - evt.error = NRFX_PDM_NO_ERROR; - evt.buffer_requested = false; - if (m_cb.buff_address[m_cb.active_buffer]) - { - evt.buffer_released = m_cb.buff_address[m_cb.active_buffer]; - m_cb.buff_address[m_cb.active_buffer] = 0; - m_cb.event_handler(&evt); - } - - uint8_t second_buffer = (~m_cb.active_buffer) & 0x01; - if (m_cb.buff_address[second_buffer]) - { - evt.buffer_released = m_cb.buff_address[second_buffer]; - m_cb.buff_address[second_buffer] = 0; - m_cb.event_handler(&evt); - } - m_cb.active_buffer = 0; - } - - if (m_cb.irq_buff_request) - { - nrfx_pdm_evt_t const evt = - { - .buffer_requested = true, - .buffer_released = NULL, - .error = NRFX_PDM_NO_ERROR, - }; - m_cb.irq_buff_request = 0; - m_cb.event_handler(&evt); - } -} - - -nrfx_err_t nrfx_pdm_init(nrfx_pdm_config_t const * p_config, - nrfx_pdm_event_handler_t event_handler) -{ - NRFX_ASSERT(p_config); - NRFX_ASSERT(event_handler); - nrfx_err_t err_code; - - if (m_cb.drv_state != NRFX_DRV_STATE_UNINITIALIZED) - { - err_code = NRFX_ERROR_INVALID_STATE; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - if (p_config->gain_l > NRF_PDM_GAIN_MAXIMUM || - p_config->gain_r > NRF_PDM_GAIN_MAXIMUM) - { - err_code = NRFX_ERROR_INVALID_PARAM; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - m_cb.buff_address[0] = 0; - m_cb.buff_address[1] = 0; - m_cb.active_buffer = 0; - m_cb.error = 0; - m_cb.event_handler = event_handler; - m_cb.op_state = NRFX_PDM_STATE_IDLE; - - nrf_pdm_clock_set(p_config->clock_freq); - nrf_pdm_mode_set(p_config->mode, p_config->edge); - nrf_pdm_gain_set(p_config->gain_l, p_config->gain_r); - - nrf_gpio_cfg_output(p_config->pin_clk); - nrf_gpio_pin_clear(p_config->pin_clk); - nrf_gpio_cfg_input(p_config->pin_din, NRF_GPIO_PIN_NOPULL); - nrf_pdm_psel_connect(p_config->pin_clk, p_config->pin_din); - - nrf_pdm_event_clear(NRF_PDM_EVENT_STARTED); - nrf_pdm_event_clear(NRF_PDM_EVENT_END); - nrf_pdm_event_clear(NRF_PDM_EVENT_STOPPED); - nrf_pdm_int_enable(NRF_PDM_INT_STARTED | NRF_PDM_INT_STOPPED); - NRFX_IRQ_PRIORITY_SET(PDM_IRQn, p_config->interrupt_priority); - NRFX_IRQ_ENABLE(PDM_IRQn); - m_cb.drv_state = NRFX_DRV_STATE_INITIALIZED; - - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -void nrfx_pdm_uninit(void) -{ - nrf_pdm_disable(); - nrf_pdm_psel_disconnect(); - m_cb.drv_state = NRFX_DRV_STATE_UNINITIALIZED; - NRFX_LOG_INFO("Uninitialized."); -} - -static void pdm_start() -{ - m_cb.drv_state = NRFX_DRV_STATE_POWERED_ON; - nrf_pdm_enable(); - nrf_pdm_event_clear(NRF_PDM_EVENT_STARTED); - nrf_pdm_task_trigger(NRF_PDM_TASK_START); -} - -static void pdm_buf_request() -{ - m_cb.irq_buff_request = 1; - NRFX_IRQ_PENDING_SET(PDM_IRQn); -} - -nrfx_err_t nrfx_pdm_start(void) -{ - NRFX_ASSERT(m_cb.drv_state != NRFX_DRV_STATE_UNINITIALIZED); - nrfx_err_t err_code; - - if (m_cb.op_state != NRFX_PDM_STATE_IDLE) - { - if (m_cb.op_state == NRFX_PDM_STATE_RUNNING) - { - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - m_cb.op_state = NRFX_PDM_STATE_STARTING; - pdm_buf_request(); - - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -nrfx_err_t nrfx_pdm_buffer_set(int16_t * buffer, uint16_t buffer_length) -{ - if (m_cb.drv_state == NRFX_DRV_STATE_UNINITIALIZED) - { - return NRFX_ERROR_INVALID_STATE; - } - if (m_cb.op_state == NRFX_PDM_STATE_STOPPING) - { - return NRFX_ERROR_BUSY; - } - if ((buffer == NULL) || (buffer_length > NRFX_PDM_MAX_BUFFER_SIZE)) - { - return NRFX_ERROR_INVALID_PARAM; - } - - nrfx_err_t err_code = NRFX_SUCCESS; - - // Enter the PDM critical section. - NRFX_IRQ_DISABLE(PDM_IRQn); - - uint8_t next_buffer = (~m_cb.active_buffer) & 0x01; - if (m_cb.op_state == NRFX_PDM_STATE_STARTING) - { - next_buffer = 0; - } - - if (m_cb.buff_address[next_buffer]) - { - // Buffer already set. - err_code = NRFX_ERROR_BUSY; - } - else - { - m_cb.buff_address[next_buffer] = buffer; - m_cb.buff_length[next_buffer] = buffer_length; - nrf_pdm_buffer_set((uint32_t *)buffer, buffer_length); - - if (m_cb.drv_state != NRFX_DRV_STATE_POWERED_ON) - { - pdm_start(); - } - } - - NRFX_IRQ_ENABLE(PDM_IRQn); - return err_code; -} - -nrfx_err_t nrfx_pdm_stop(void) -{ - NRFX_ASSERT(m_cb.drv_state != NRFX_DRV_STATE_UNINITIALIZED); - nrfx_err_t err_code; - - if (m_cb.op_state != NRFX_PDM_STATE_RUNNING) - { - if (m_cb.op_state == NRFX_PDM_STATE_IDLE || - m_cb.op_state == NRFX_PDM_STATE_STARTING) - { - nrf_pdm_disable(); - m_cb.op_state = NRFX_PDM_STATE_IDLE; - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - m_cb.drv_state = NRFX_DRV_STATE_INITIALIZED; - m_cb.op_state = NRFX_PDM_STATE_STOPPING; - - nrf_pdm_task_trigger(NRF_PDM_TASK_STOP); - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -#endif // NRFX_CHECK(NRFX_PDM_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_power.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_power.c deleted file mode 100644 index ab790944b7..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_power.c +++ /dev/null @@ -1,306 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include - -#if NRFX_CHECK(NRFX_POWER_ENABLED) - -#include - -#if NRFX_CHECK(NRFX_CLOCK_ENABLED) -extern bool nrfx_clock_irq_enabled; -#endif - -/** - * @internal - * @defgroup nrfx_power_internals POWER driver internals - * @ingroup nrfx_power - * - * Internal variables, auxiliary macros and functions of POWER driver. - * @{ - */ - -/** - * This variable is used to check whether common POWER_CLOCK common interrupt - * should be disabled or not if @ref nrfx_clock tries to disable the interrupt. - */ - -bool nrfx_power_irq_enabled; - -/** - * @brief The initialization flag - */ - -#define m_initialized nrfx_power_irq_enabled - -/** - * @brief The handler of power fail comparator warning event - */ -static nrfx_power_pofwarn_event_handler_t m_pofwarn_handler; - -#if NRF_POWER_HAS_SLEEPEVT || defined(__NRFX_DOXYGEN__) -/** - * @brief The handler of sleep event handler - */ -static nrfx_power_sleep_event_handler_t m_sleepevt_handler; -#endif - -#if NRF_POWER_HAS_USBREG || defined(__NRFX_DOXYGEN__) -/** - * @brief The handler of USB power events - */ -static nrfx_power_usb_event_handler_t m_usbevt_handler; -#endif - -/** @} */ - -nrfx_power_pofwarn_event_handler_t nrfx_power_pof_handler_get(void) -{ - return m_pofwarn_handler; -} - -#if NRF_POWER_HAS_USBREG -nrfx_power_usb_event_handler_t nrfx_power_usb_handler_get(void) -{ - return m_usbevt_handler; -} -#endif - -nrfx_err_t nrfx_power_init(nrfx_power_config_t const * p_config) -{ - NRFX_ASSERT(p_config); - if (m_initialized) - { - return NRFX_ERROR_ALREADY_INITIALIZED; - } - -#if NRF_POWER_HAS_VDDH - nrf_power_dcdcen_vddh_set(p_config->dcdcenhv); -#endif - nrf_power_dcdcen_set(p_config->dcdcen); - - nrfx_power_clock_irq_init(); - - m_initialized = true; - return NRFX_SUCCESS; -} - - -void nrfx_power_uninit(void) -{ - NRFX_ASSERT(m_initialized); - -#if NRFX_CHECK(NRFX_CLOCK_ENABLED) - if (!nrfx_clock_irq_enabled) -#endif - { - NRFX_IRQ_DISABLE(POWER_CLOCK_IRQn); - } - - nrfx_power_pof_uninit(); -#if NRF_POWER_HAS_SLEEPEVT || defined(__NRFX_DOXYGEN__) - nrfx_power_sleepevt_uninit(); -#endif -#if NRF_POWER_HAS_USBREG || defined(__NRFX_DOXYGEN__) - nrfx_power_usbevt_uninit(); -#endif - m_initialized = false; -} - -void nrfx_power_pof_init(nrfx_power_pofwarn_config_t const * p_config) -{ - NRFX_ASSERT(p_config != NULL); - - nrfx_power_pof_uninit(); - - if (p_config->handler != NULL) - { - m_pofwarn_handler = p_config->handler; - } -} - -void nrfx_power_pof_enable(nrfx_power_pofwarn_config_t const * p_config) -{ - nrf_power_pofcon_set(true, p_config->thr); -#if NRF_POWER_HAS_VDDH || defined(__NRFX_DOXYGEN__) - nrf_power_pofcon_vddh_set(p_config->thrvddh); -#endif - if (m_pofwarn_handler != NULL) - { - nrf_power_int_enable(NRF_POWER_INT_POFWARN_MASK); - } -} - -void nrfx_power_pof_disable(void) -{ - nrf_power_int_disable(NRF_POWER_INT_POFWARN_MASK); -} - -void nrfx_power_pof_uninit(void) -{ - m_pofwarn_handler = NULL; -} - -#if NRF_POWER_HAS_SLEEPEVT || defined(__NRFX_DOXYGEN__) -void nrfx_power_sleepevt_init(nrfx_power_sleepevt_config_t const * p_config) -{ - NRFX_ASSERT(p_config != NULL); - - nrfx_power_sleepevt_uninit(); - if (p_config->handler != NULL) - { - m_sleepevt_handler = p_config->handler; - } -} - -void nrfx_power_sleepevt_enable(nrfx_power_sleepevt_config_t const * p_config) -{ - uint32_t enmask = 0; - if (p_config->en_enter) - { - enmask |= NRF_POWER_INT_SLEEPENTER_MASK; - nrf_power_event_clear(NRF_POWER_EVENT_SLEEPENTER); - } - if (p_config->en_exit) - { - enmask |= NRF_POWER_INT_SLEEPEXIT_MASK; - nrf_power_event_clear(NRF_POWER_EVENT_SLEEPEXIT); - } - nrf_power_int_enable(enmask); -} - -void nrfx_power_sleepevt_disable(void) -{ - nrf_power_int_disable( - NRF_POWER_INT_SLEEPENTER_MASK | - NRF_POWER_INT_SLEEPEXIT_MASK); -} - -void nrfx_power_sleepevt_uninit(void) -{ - m_sleepevt_handler = NULL; -} -#endif /* NRF_POWER_HAS_SLEEPEVT */ - -#if NRF_POWER_HAS_USBREG || defined(__NRFX_DOXYGEN__) -void nrfx_power_usbevt_init(nrfx_power_usbevt_config_t const * p_config) -{ - nrfx_power_usbevt_uninit(); - if (p_config->handler != NULL) - { - m_usbevt_handler = p_config->handler; - } -} - -void nrfx_power_usbevt_enable(void) -{ - nrf_power_int_enable( - NRF_POWER_INT_USBDETECTED_MASK | - NRF_POWER_INT_USBREMOVED_MASK | - NRF_POWER_INT_USBPWRRDY_MASK); -} - -void nrfx_power_usbevt_disable(void) -{ - nrf_power_int_disable( - NRF_POWER_INT_USBDETECTED_MASK | - NRF_POWER_INT_USBREMOVED_MASK | - NRF_POWER_INT_USBPWRRDY_MASK); -} - -void nrfx_power_usbevt_uninit(void) -{ - m_usbevt_handler = NULL; -} -#endif /* NRF_POWER_HAS_USBREG */ - - -void nrfx_power_irq_handler(void) -{ - uint32_t enabled = nrf_power_int_enable_get(); - if ((0 != (enabled & NRF_POWER_INT_POFWARN_MASK)) && - nrf_power_event_get_and_clear(NRF_POWER_EVENT_POFWARN)) - { - /* Cannot be null if event is enabled */ - NRFX_ASSERT(m_pofwarn_handler != NULL); - m_pofwarn_handler(); - } -#if NRF_POWER_HAS_SLEEPEVT || defined(__NRFX_DOXYGEN__) - if ((0 != (enabled & NRF_POWER_INT_SLEEPENTER_MASK)) && - nrf_power_event_get_and_clear(NRF_POWER_EVENT_SLEEPENTER)) - { - /* Cannot be null if event is enabled */ - NRFX_ASSERT(m_sleepevt_handler != NULL); - m_sleepevt_handler(NRFX_POWER_SLEEP_EVT_ENTER); - } - if ((0 != (enabled & NRF_POWER_INT_SLEEPEXIT_MASK)) && - nrf_power_event_get_and_clear(NRF_POWER_EVENT_SLEEPEXIT)) - { - /* Cannot be null if event is enabled */ - NRFX_ASSERT(m_sleepevt_handler != NULL); - m_sleepevt_handler(NRFX_POWER_SLEEP_EVT_EXIT); - } -#endif -#if NRF_POWER_HAS_USBREG || defined(__NRFX_DOXYGEN__) - if ((0 != (enabled & NRF_POWER_INT_USBDETECTED_MASK)) && - nrf_power_event_get_and_clear(NRF_POWER_EVENT_USBDETECTED)) - { - /* Cannot be null if event is enabled */ - NRFX_ASSERT(m_usbevt_handler != NULL); - m_usbevt_handler(NRFX_POWER_USB_EVT_DETECTED); - } - if ((0 != (enabled & NRF_POWER_INT_USBREMOVED_MASK)) && - nrf_power_event_get_and_clear(NRF_POWER_EVENT_USBREMOVED)) - { - /* Cannot be null if event is enabled */ - NRFX_ASSERT(m_usbevt_handler != NULL); - m_usbevt_handler(NRFX_POWER_USB_EVT_REMOVED); - } - if ((0 != (enabled & NRF_POWER_INT_USBPWRRDY_MASK)) && - nrf_power_event_get_and_clear(NRF_POWER_EVENT_USBPWRRDY)) - { - /* Cannot be null if event is enabled */ - NRFX_ASSERT(m_usbevt_handler != NULL); - m_usbevt_handler(NRFX_POWER_USB_EVT_READY); - } -#endif -} - -#endif // NRFX_CHECK(NRFX_POWER_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_power_clock.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_power_clock.c deleted file mode 100644 index 0b52412996..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_power_clock.c +++ /dev/null @@ -1,52 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include -#include -#include - - -#if NRFX_CHECK(NRFX_POWER_ENABLED) && NRFX_CHECK(NRFX_CLOCK_ENABLED) -void nrfx_power_clock_irq_handler(void) -{ - nrfx_power_irq_handler(); - nrfx_clock_irq_handler(); -} -#endif diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_ppi.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_ppi.c deleted file mode 100644 index 0268a6df90..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_ppi.c +++ /dev/null @@ -1,534 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include - -#if NRFX_CHECK(NRFX_PPI_ENABLED) - -#include - -#define NRFX_LOG_MODULE_NAME PPI -#include - - -static uint32_t m_channels_allocated; /**< Bitmap representing channels availability. 1 when a channel is allocated, 0 otherwise. */ -static uint8_t m_groups_allocated; /**< Bitmap representing groups availability. 1 when a group is allocated, 0 otherwise.*/ - - -/** - * @brief Compute a group mask (needed for driver internals, not used for NRF_PPI registers). - * - * @param[in] group Group number to transform to a mask. - * - * @retval Group mask. - */ -__STATIC_INLINE uint32_t group_to_mask(nrf_ppi_channel_group_t group) -{ - return (1uL << (uint32_t) group); -} - - -/** - * @brief Check whether a channel is a programmable channel and can be used by an application. - * - * @param[in] channel Channel to check. - * - * @retval true The channel is a programmable application channel. - * @retval false The channel is used by a stack (for example SoftDevice) or is preprogrammed. - */ -__STATIC_INLINE bool is_programmable_app_channel(nrf_ppi_channel_t channel) -{ - return ((NRFX_PPI_PROG_APP_CHANNELS_MASK & nrfx_ppi_channel_to_mask(channel)) != 0); -} - - -/** - * @brief Check whether channels can be used by an application. - * - * @param[in] channel_mask Channel mask to check. - * - * @retval true All specified channels can be used by an application. - * @retval false At least one specified channel is used by a stack (for example SoftDevice). - */ -__STATIC_INLINE bool are_app_channels(uint32_t channel_mask) -{ - //lint -e(587) - return ((~(NRFX_PPI_ALL_APP_CHANNELS_MASK) & channel_mask) == 0); -} - - -/** - * @brief Check whether a channel can be used by an application. - * - * @param[in] channel Channel to check. - * - * @retval true The channel can be used by an application. - * @retval false The channel is used by a stack (for example SoftDevice). - */ -__STATIC_INLINE bool is_app_channel(nrf_ppi_channel_t channel) -{ - return are_app_channels(nrfx_ppi_channel_to_mask(channel)); -} - - -/** - * @brief Check whether a channel group can be used by an application. - * - * @param[in] group Group to check. - * - * @retval true The group is an application group. - * @retval false The group is not an application group (this group either does not exist or - * it is used by a stack (for example SoftDevice)). - */ -__STATIC_INLINE bool is_app_group(nrf_ppi_channel_group_t group) -{ - return ((NRFX_PPI_ALL_APP_GROUPS_MASK & group_to_mask(group)) != 0); -} - - -/** - * @brief Check whether a channel is allocated. - * - * @param[in] channel_num Channel number to check. - * - * @retval true The channel is allocated. - * @retval false The channel is not allocated. - */ -__STATIC_INLINE bool is_allocated_channel(nrf_ppi_channel_t channel) -{ - return ((m_channels_allocated & nrfx_ppi_channel_to_mask(channel)) != 0); -} - - -/** - * @brief Set channel allocated indication. - * - * @param[in] channel_num Specifies the channel to set the "allocated" indication. - */ -__STATIC_INLINE void channel_allocated_set(nrf_ppi_channel_t channel) -{ - m_channels_allocated |= nrfx_ppi_channel_to_mask(channel); -} - - -/** - * @brief Clear channel allocated indication. - * - * @param[in] channel_num Specifies the channel to clear the "allocated" indication. - */ -__STATIC_INLINE void channel_allocated_clr(nrf_ppi_channel_t channel) -{ - m_channels_allocated &= ~nrfx_ppi_channel_to_mask(channel); -} - - -/** - * @brief Clear all allocated channels. - */ -__STATIC_INLINE void channel_allocated_clr_all(void) -{ - m_channels_allocated &= ~NRFX_PPI_ALL_APP_CHANNELS_MASK; -} - - -/** - * @brief Check whether a group is allocated. - * - * @param[in] group_num Group number to check. - * - * @retval true The group is allocated. - * false The group is not allocated. - */ -__STATIC_INLINE bool is_allocated_group(nrf_ppi_channel_group_t group) -{ - return ((m_groups_allocated & group_to_mask(group)) != 0); -} - - -/** - * @brief Set group allocated indication. - * - * @param[in] group_num Specifies the group to set the "allocated" indication. - */ -__STATIC_INLINE void group_allocated_set(nrf_ppi_channel_group_t group) -{ - m_groups_allocated |= group_to_mask(group); -} - - -/** - * @brief Clear group allocated indication. - * - * @param[in] group_num Specifies the group to clear the "allocated" indication. - */ -__STATIC_INLINE void group_allocated_clr(nrf_ppi_channel_group_t group) -{ - m_groups_allocated &= ~group_to_mask(group); -} - - -/** - * @brief Clear all allocated groups. - */ -__STATIC_INLINE void group_allocated_clr_all() -{ - m_groups_allocated &= ~NRFX_PPI_ALL_APP_GROUPS_MASK; -} - - -void nrfx_ppi_free_all(void) -{ - uint32_t mask = NRFX_PPI_ALL_APP_GROUPS_MASK; - nrf_ppi_channel_group_t group; - - // Disable all channels and groups - nrf_ppi_channels_disable(NRFX_PPI_ALL_APP_CHANNELS_MASK); - - for (group = NRF_PPI_CHANNEL_GROUP0; mask != 0; mask &= ~group_to_mask(group), group++) - { - if (mask & group_to_mask(group)) - { - nrf_ppi_channel_group_clear(group); - } - } - channel_allocated_clr_all(); - group_allocated_clr_all(); -} - - -nrfx_err_t nrfx_ppi_channel_alloc(nrf_ppi_channel_t * p_channel) -{ - nrfx_err_t err_code = NRFX_SUCCESS; - nrf_ppi_channel_t channel; - uint32_t mask = 0; - err_code = NRFX_ERROR_NO_MEM; - - mask = NRFX_PPI_PROG_APP_CHANNELS_MASK; - for (channel = NRF_PPI_CHANNEL0; - mask != 0; - mask &= ~nrfx_ppi_channel_to_mask(channel), channel++) - { - NRFX_CRITICAL_SECTION_ENTER(); - if ((mask & nrfx_ppi_channel_to_mask(channel)) && (!is_allocated_channel(channel))) - { - channel_allocated_set(channel); - *p_channel = channel; - err_code = NRFX_SUCCESS; - } - NRFX_CRITICAL_SECTION_EXIT(); - if (err_code == NRFX_SUCCESS) - { - NRFX_LOG_INFO("Allocated channel: %d.", channel); - break; - } - } - - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - - -nrfx_err_t nrfx_ppi_channel_free(nrf_ppi_channel_t channel) -{ - nrfx_err_t err_code = NRFX_SUCCESS; - - if (!is_programmable_app_channel(channel)) - { - err_code = NRFX_ERROR_INVALID_PARAM; - } - else - { - // First disable this channel - nrf_ppi_channel_disable(channel); - NRFX_CRITICAL_SECTION_ENTER(); - channel_allocated_clr(channel); - NRFX_CRITICAL_SECTION_EXIT(); - } - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - - -nrfx_err_t nrfx_ppi_channel_assign(nrf_ppi_channel_t channel, uint32_t eep, uint32_t tep) -{ - if ((uint32_t *)eep == NULL || (uint32_t *)tep == NULL) - { - return NRFX_ERROR_NULL; - } - - nrfx_err_t err_code = NRFX_SUCCESS; - - if (!is_programmable_app_channel(channel)) - { - err_code = NRFX_ERROR_INVALID_PARAM; - } - else if (!is_allocated_channel(channel)) - { - err_code = NRFX_ERROR_INVALID_STATE; - } - else - { - nrf_ppi_channel_endpoint_setup(channel, eep, tep); - NRFX_LOG_INFO("Assigned channel: %d, event end point: %x, task end point: %x.", - channel, - eep, - tep); - } - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -nrfx_err_t nrfx_ppi_channel_fork_assign(nrf_ppi_channel_t channel, uint32_t fork_tep) -{ - nrfx_err_t err_code = NRFX_SUCCESS; -#ifdef PPI_FEATURE_FORKS_PRESENT - if (!is_programmable_app_channel(channel)) - { - err_code = NRFX_ERROR_INVALID_PARAM; - } - else if (!is_allocated_channel(channel)) - { - err_code = NRFX_ERROR_INVALID_STATE; - } - else - { - nrf_ppi_fork_endpoint_setup(channel, fork_tep); - NRFX_LOG_INFO("Fork assigned channel: %d, task end point: %d.", channel, fork_tep); - } - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -#else - err_code = NRFX_ERROR_NOT_SUPPORTED; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -#endif -} - -nrfx_err_t nrfx_ppi_channel_enable(nrf_ppi_channel_t channel) -{ - nrfx_err_t err_code = NRFX_SUCCESS; - - if (!is_app_channel(channel)) - { - err_code = NRFX_ERROR_INVALID_PARAM; - } - else if (is_programmable_app_channel(channel) && !is_allocated_channel(channel)) - { - err_code = NRFX_ERROR_INVALID_STATE; - } - else - { - nrf_ppi_channel_enable(channel); - } - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - - -nrfx_err_t nrfx_ppi_channel_disable(nrf_ppi_channel_t channel) -{ - nrfx_err_t err_code = NRFX_SUCCESS; - - if (!is_app_channel(channel)) - { - err_code = NRFX_ERROR_INVALID_PARAM; - } - else if (is_programmable_app_channel(channel) && !is_allocated_channel(channel)) - { - err_code = NRFX_ERROR_INVALID_STATE; - } - else - { - nrf_ppi_channel_disable(channel); - err_code = NRFX_SUCCESS; - } - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - - -nrfx_err_t nrfx_ppi_group_alloc(nrf_ppi_channel_group_t * p_group) -{ - nrfx_err_t err_code; - uint32_t mask = 0; - nrf_ppi_channel_group_t group; - - err_code = NRFX_ERROR_NO_MEM; - - mask = NRFX_PPI_ALL_APP_GROUPS_MASK; - for (group = NRF_PPI_CHANNEL_GROUP0; mask != 0; mask &= ~group_to_mask(group), group++) - { - NRFX_CRITICAL_SECTION_ENTER(); - if ((mask & group_to_mask(group)) && (!is_allocated_group(group))) - { - group_allocated_set(group); - *p_group = group; - err_code = NRFX_SUCCESS; - } - NRFX_CRITICAL_SECTION_EXIT(); - if (err_code == NRFX_SUCCESS) - { - NRFX_LOG_INFO("Allocated group: %d.", group); - break; - } - } - - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - - -nrfx_err_t nrfx_ppi_group_free(nrf_ppi_channel_group_t group) -{ - nrfx_err_t err_code = NRFX_SUCCESS; - - if (!is_app_group(group)) - { - err_code = NRFX_ERROR_INVALID_PARAM; - } - if (!is_allocated_group(group)) - { - err_code = NRFX_ERROR_INVALID_STATE; - } - else - { - nrf_ppi_group_disable(group); - NRFX_CRITICAL_SECTION_ENTER(); - group_allocated_clr(group); - NRFX_CRITICAL_SECTION_EXIT(); - } - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - - -nrfx_err_t nrfx_ppi_group_enable(nrf_ppi_channel_group_t group) -{ - nrfx_err_t err_code = NRFX_SUCCESS; - - if (!is_app_group(group)) - { - err_code = NRFX_ERROR_INVALID_PARAM; - } - else if (!is_allocated_group(group)) - { - err_code = NRFX_ERROR_INVALID_STATE; - } - else - { - nrf_ppi_group_enable(group); - } - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - - -nrfx_err_t nrfx_ppi_group_disable(nrf_ppi_channel_group_t group) -{ - nrfx_err_t err_code = NRFX_SUCCESS; - - if (!is_app_group(group)) - { - err_code = NRFX_ERROR_INVALID_PARAM; - } - else - { - nrf_ppi_group_disable(group); - } - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -nrfx_err_t nrfx_ppi_channels_remove_from_group(uint32_t channel_mask, - nrf_ppi_channel_group_t group) -{ - nrfx_err_t err_code = NRFX_SUCCESS; - - if (!is_app_group(group)) - { - err_code = NRFX_ERROR_INVALID_PARAM; - } - else if (!is_allocated_group(group)) - { - err_code = NRFX_ERROR_INVALID_STATE; - } - else if (!are_app_channels(channel_mask)) - { - err_code = NRFX_ERROR_INVALID_PARAM; - } - else - { - NRFX_CRITICAL_SECTION_ENTER(); - nrf_ppi_channels_remove_from_group(channel_mask, group); - NRFX_CRITICAL_SECTION_EXIT(); - } - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -nrfx_err_t nrfx_ppi_channels_include_in_group(uint32_t channel_mask, - nrf_ppi_channel_group_t group) -{ - nrfx_err_t err_code = NRFX_SUCCESS; - - if (!is_app_group(group)) - { - err_code = NRFX_ERROR_INVALID_PARAM; - } - else if (!is_allocated_group(group)) - { - err_code = NRFX_ERROR_INVALID_STATE; - } - else if (!are_app_channels(channel_mask)) - { - err_code = NRFX_ERROR_INVALID_PARAM; - } - else - { - NRFX_CRITICAL_SECTION_ENTER(); - nrf_ppi_channels_include_in_group(channel_mask, group); - NRFX_CRITICAL_SECTION_EXIT(); - } - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} -#endif // NRFX_CHECK(NRFX_PPI_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_pwm.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_pwm.c deleted file mode 100644 index 812843bff2..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_pwm.c +++ /dev/null @@ -1,515 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include - -#if NRFX_CHECK(NRFX_PWM_ENABLED) - -#if !(NRFX_CHECK(NRFX_PWM0_ENABLED) || NRFX_CHECK(NRFX_PWM1_ENABLED) || \ - NRFX_CHECK(NRFX_PWM2_ENABLED) || NRFX_CHECK(NRFX_PWM3_ENABLED)) -#error "No enabled PWM instances. Check ." -#endif - -#include -#include - -#define NRFX_LOG_MODULE PWM -#include - -#if NRFX_CHECK(NRFX_PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED) -// The workaround uses interrupts to wake up the CPU and ensure it is active -// when PWM is about to start a DMA transfer. For initial transfer, done when -// a playback is started via PPI, a specific EGU instance is used to generate -// an interrupt. During the playback, the PWM interrupt triggered on SEQEND -// event of a preceding sequence is used to protect the transfer done for -// the next sequence to be played. -#include -#define USE_DMA_ISSUE_WORKAROUND -#endif -#if defined(USE_DMA_ISSUE_WORKAROUND) -#define EGU_IRQn(i) EGU_IRQn_(i) -#define EGU_IRQn_(i) SWI##i##_EGU##i##_IRQn -#define EGU_IRQHandler(i) EGU_IRQHandler_(i) -#define EGU_IRQHandler_(i) nrfx_swi_##i##_irq_handler -#define DMA_ISSUE_EGU_IDX NRFX_PWM_NRF52_ANOMALY_109_EGU_INSTANCE -#define DMA_ISSUE_EGU NRFX_CONCAT_2(NRF_EGU, DMA_ISSUE_EGU_IDX) -#define DMA_ISSUE_EGU_IRQn EGU_IRQn(DMA_ISSUE_EGU_IDX) -#define DMA_ISSUE_EGU_IRQHandler EGU_IRQHandler(DMA_ISSUE_EGU_IDX) -#endif - -// Control block - driver instance local data. -typedef struct -{ -#if defined(USE_DMA_ISSUE_WORKAROUND) - uint32_t starting_task_address; -#endif - nrfx_pwm_handler_t handler; - nrfx_drv_state_t volatile state; - uint8_t flags; -} pwm_control_block_t; -static pwm_control_block_t m_cb[NRFX_PWM_ENABLED_COUNT]; - -static void configure_pins(nrfx_pwm_t const * const p_instance, - nrfx_pwm_config_t const * p_config) -{ - uint32_t out_pins[NRF_PWM_CHANNEL_COUNT]; - uint8_t i; - - for (i = 0; i < NRF_PWM_CHANNEL_COUNT; ++i) - { - uint8_t output_pin = p_config->output_pins[i]; - if (output_pin != NRFX_PWM_PIN_NOT_USED) - { - bool inverted = output_pin & NRFX_PWM_PIN_INVERTED; - out_pins[i] = output_pin & ~NRFX_PWM_PIN_INVERTED; - - if (inverted) - { - nrf_gpio_pin_set(out_pins[i]); - } - else - { - nrf_gpio_pin_clear(out_pins[i]); - } - - nrf_gpio_cfg_output(out_pins[i]); - } - else - { - out_pins[i] = NRF_PWM_PIN_NOT_CONNECTED; - } - } - - nrf_pwm_pins_set(p_instance->p_registers, out_pins); -} - - -nrfx_err_t nrfx_pwm_init(nrfx_pwm_t const * const p_instance, - nrfx_pwm_config_t const * p_config, - nrfx_pwm_handler_t handler) -{ - NRFX_ASSERT(p_config); - - nrfx_err_t err_code; - - pwm_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - - if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED) - { - err_code = NRFX_ERROR_INVALID_STATE; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - p_cb->handler = handler; - - configure_pins(p_instance, p_config); - - nrf_pwm_enable(p_instance->p_registers); - nrf_pwm_configure(p_instance->p_registers, - p_config->base_clock, p_config->count_mode, p_config->top_value); - nrf_pwm_decoder_set(p_instance->p_registers, - p_config->load_mode, p_config->step_mode); - - nrf_pwm_shorts_set(p_instance->p_registers, 0); - nrf_pwm_int_set(p_instance->p_registers, 0); - nrf_pwm_event_clear(p_instance->p_registers, NRF_PWM_EVENT_LOOPSDONE); - nrf_pwm_event_clear(p_instance->p_registers, NRF_PWM_EVENT_SEQEND0); - nrf_pwm_event_clear(p_instance->p_registers, NRF_PWM_EVENT_SEQEND1); - nrf_pwm_event_clear(p_instance->p_registers, NRF_PWM_EVENT_STOPPED); - - // The workaround for nRF52 Anomaly 109 "protects" DMA transfers by handling - // interrupts generated on SEQEND0 and SEQEND1 events (this ensures that - // the 64 MHz clock is ready when data for the next sequence to be played - // is read). Therefore, the PWM interrupt must be enabled even if the event - // handler is not used. -#if defined(USE_DMA_ISSUE_WORKAROUND) - NRFX_IRQ_PRIORITY_SET(DMA_ISSUE_EGU_IRQn, p_config->irq_priority); - NRFX_IRQ_ENABLE(DMA_ISSUE_EGU_IRQn); -#else - if (p_cb->handler) -#endif - { - NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_instance->p_registers), - p_config->irq_priority); - NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_instance->p_registers)); - } - - p_cb->state = NRFX_DRV_STATE_INITIALIZED; - - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - - -void nrfx_pwm_uninit(nrfx_pwm_t const * const p_instance) -{ - pwm_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); - - NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_instance->p_registers)); -#if defined(USE_DMA_ISSUE_WORKAROUND) - NRFX_IRQ_DISABLE(DMA_ISSUE_EGU_IRQn); -#endif - - nrf_pwm_disable(p_instance->p_registers); - - p_cb->state = NRFX_DRV_STATE_UNINITIALIZED; -} - - -static uint32_t start_playback(nrfx_pwm_t const * const p_instance, - pwm_control_block_t * p_cb, - uint8_t flags, - nrf_pwm_task_t starting_task) -{ - p_cb->state = NRFX_DRV_STATE_POWERED_ON; - p_cb->flags = flags; - - if (p_cb->handler) - { - // The notification about finished playback is by default enabled, - // but this can be suppressed. - // The notification that the peripheral has stopped is always enabled. - uint32_t int_mask = NRF_PWM_INT_LOOPSDONE_MASK | - NRF_PWM_INT_STOPPED_MASK; - - // The workaround for nRF52 Anomaly 109 "protects" DMA transfers by - // handling interrupts generated on SEQEND0 and SEQEND1 events (see - // 'nrfx_pwm_init'), hence these events must be always enabled - // to generate interrupts. - // However, the user handler is called for them only when requested - // (see 'irq_handler'). -#if defined(USE_DMA_ISSUE_WORKAROUND) - int_mask |= NRF_PWM_INT_SEQEND0_MASK | NRF_PWM_INT_SEQEND1_MASK; -#else - if (flags & NRFX_PWM_FLAG_SIGNAL_END_SEQ0) - { - int_mask |= NRF_PWM_INT_SEQEND0_MASK; - } - if (flags & NRFX_PWM_FLAG_SIGNAL_END_SEQ1) - { - int_mask |= NRF_PWM_INT_SEQEND1_MASK; - } -#endif - if (flags & NRFX_PWM_FLAG_NO_EVT_FINISHED) - { - int_mask &= ~NRF_PWM_INT_LOOPSDONE_MASK; - } - - nrf_pwm_int_set(p_instance->p_registers, int_mask); - } -#if defined(USE_DMA_ISSUE_WORKAROUND) - else - { - nrf_pwm_int_set(p_instance->p_registers, - NRF_PWM_INT_SEQEND0_MASK | NRF_PWM_INT_SEQEND1_MASK); - } -#endif - - nrf_pwm_event_clear(p_instance->p_registers, NRF_PWM_EVENT_STOPPED); - - if (flags & NRFX_PWM_FLAG_START_VIA_TASK) - { - uint32_t starting_task_address = - nrf_pwm_task_address_get(p_instance->p_registers, starting_task); - -#if defined(USE_DMA_ISSUE_WORKAROUND) - // To "protect" the initial DMA transfer it is required to start - // the PWM by triggering the proper task from EGU interrupt handler, - // it is not safe to do it directly via PPI. - p_cb->starting_task_address = starting_task_address; - nrf_egu_int_enable(DMA_ISSUE_EGU, - nrf_egu_int_get(DMA_ISSUE_EGU, p_instance->drv_inst_idx)); - return (uint32_t)nrf_egu_task_trigger_address_get(DMA_ISSUE_EGU, - p_instance->drv_inst_idx); -#else - return starting_task_address; -#endif - } - - nrf_pwm_task_trigger(p_instance->p_registers, starting_task); - return 0; -} - - -uint32_t nrfx_pwm_simple_playback(nrfx_pwm_t const * const p_instance, - nrf_pwm_sequence_t const * p_sequence, - uint16_t playback_count, - uint32_t flags) -{ - pwm_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); - NRFX_ASSERT(playback_count > 0); - NRFX_ASSERT(nrfx_is_in_ram(p_sequence->values.p_raw)); - - // To take advantage of the looping mechanism, we need to use both sequences - // (single sequence can be played back only once). - nrf_pwm_sequence_set(p_instance->p_registers, 0, p_sequence); - nrf_pwm_sequence_set(p_instance->p_registers, 1, p_sequence); - bool odd = (playback_count & 1); - nrf_pwm_loop_set(p_instance->p_registers, - (playback_count / 2) + (odd ? 1 : 0)); - - uint32_t shorts_mask; - if (flags & NRFX_PWM_FLAG_STOP) - { - shorts_mask = NRF_PWM_SHORT_LOOPSDONE_STOP_MASK; - } - else if (flags & NRFX_PWM_FLAG_LOOP) - { - shorts_mask = odd ? NRF_PWM_SHORT_LOOPSDONE_SEQSTART1_MASK - : NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK; - } - else - { - shorts_mask = 0; - } - nrf_pwm_shorts_set(p_instance->p_registers, shorts_mask); - - NRFX_LOG_INFO("Function: %s, sequence length: %d.", - __func__, - p_sequence->length); - NRFX_LOG_DEBUG("Sequence data:"); - NRFX_LOG_HEXDUMP_DEBUG((uint8_t *)p_sequence->values.p_raw, - p_sequence->length * sizeof(uint16_t)); - return start_playback(p_instance, p_cb, flags, - odd ? NRF_PWM_TASK_SEQSTART1 : NRF_PWM_TASK_SEQSTART0); -} - - -uint32_t nrfx_pwm_complex_playback(nrfx_pwm_t const * const p_instance, - nrf_pwm_sequence_t const * p_sequence_0, - nrf_pwm_sequence_t const * p_sequence_1, - uint16_t playback_count, - uint32_t flags) -{ - pwm_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); - NRFX_ASSERT(playback_count > 0); - NRFX_ASSERT(nrfx_is_in_ram(p_sequence_0->values.p_raw)); - NRFX_ASSERT(nrfx_is_in_ram(p_sequence_1->values.p_raw)); - - nrf_pwm_sequence_set(p_instance->p_registers, 0, p_sequence_0); - nrf_pwm_sequence_set(p_instance->p_registers, 1, p_sequence_1); - nrf_pwm_loop_set(p_instance->p_registers, playback_count); - - uint32_t shorts_mask; - if (flags & NRFX_PWM_FLAG_STOP) - { - shorts_mask = NRF_PWM_SHORT_LOOPSDONE_STOP_MASK; - } - else if (flags & NRFX_PWM_FLAG_LOOP) - { - shorts_mask = NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK; - } - else - { - shorts_mask = 0; - } - nrf_pwm_shorts_set(p_instance->p_registers, shorts_mask); - - NRFX_LOG_INFO("Function: %s, sequence 0 length: %d.", - __func__, - p_sequence_0->length); - NRFX_LOG_INFO("Function: %s, sequence 1 length: %d.", - __func__, - p_sequence_1->length); - NRFX_LOG_DEBUG("Sequence 0 data:"); - NRFX_LOG_HEXDUMP_DEBUG(p_sequence_0->values.p_raw, - p_sequence_0->length * sizeof(uint16_t)); - NRFX_LOG_DEBUG("Sequence 1 data:"); - NRFX_LOG_HEXDUMP_DEBUG(p_sequence_1->values.p_raw, - p_sequence_1->length * sizeof(uint16_t)); - return start_playback(p_instance, p_cb, flags, NRF_PWM_TASK_SEQSTART0); -} - - -bool nrfx_pwm_stop(nrfx_pwm_t const * const p_instance, - bool wait_until_stopped) -{ - NRFX_ASSERT(m_cb[p_instance->drv_inst_idx].state != NRFX_DRV_STATE_UNINITIALIZED); - - bool ret_val = false; - - if (nrfx_pwm_is_stopped(p_instance)) - { - ret_val = true; - } - else - { - nrf_pwm_task_trigger(p_instance->p_registers, NRF_PWM_TASK_STOP); - - do { - if (nrfx_pwm_is_stopped(p_instance)) - { - ret_val = true; - break; - } - } while (wait_until_stopped); - } - - NRFX_LOG_INFO("%s returned %d.", __func__, ret_val); - return ret_val; -} - - -bool nrfx_pwm_is_stopped(nrfx_pwm_t const * const p_instance) -{ - pwm_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); - - bool ret_val = false; - - // If the event handler is used (interrupts are enabled), the state will - // be changed in interrupt handler when the STOPPED event occurs. - if (p_cb->state != NRFX_DRV_STATE_POWERED_ON) - { - ret_val = true; - } - // If interrupts are disabled, we must check the STOPPED event here. - if (nrf_pwm_event_check(p_instance->p_registers, NRF_PWM_EVENT_STOPPED)) - { - p_cb->state = NRFX_DRV_STATE_INITIALIZED; - NRFX_LOG_INFO("Disabled."); - ret_val = true; - } - - NRFX_LOG_INFO("%s returned %d.", __func__, ret_val); - return ret_val; -} - - -static void irq_handler(NRF_PWM_Type * p_pwm, pwm_control_block_t * p_cb) -{ - // The user handler is called for SEQEND0 and SEQEND1 events only when the - // user asks for it (by setting proper flags when starting the playback). - if (nrf_pwm_event_check(p_pwm, NRF_PWM_EVENT_SEQEND0)) - { - nrf_pwm_event_clear(p_pwm, NRF_PWM_EVENT_SEQEND0); - if ((p_cb->flags & NRFX_PWM_FLAG_SIGNAL_END_SEQ0) && p_cb->handler) - { - p_cb->handler(NRFX_PWM_EVT_END_SEQ0); - } - } - if (nrf_pwm_event_check(p_pwm, NRF_PWM_EVENT_SEQEND1)) - { - nrf_pwm_event_clear(p_pwm, NRF_PWM_EVENT_SEQEND1); - if ((p_cb->flags & NRFX_PWM_FLAG_SIGNAL_END_SEQ1) && p_cb->handler) - { - p_cb->handler(NRFX_PWM_EVT_END_SEQ1); - } - } - // For LOOPSDONE the handler is called by default, but the user can disable - // this (via flags). - if (nrf_pwm_event_check(p_pwm, NRF_PWM_EVENT_LOOPSDONE)) - { - nrf_pwm_event_clear(p_pwm, NRF_PWM_EVENT_LOOPSDONE); - if (!(p_cb->flags & NRFX_PWM_FLAG_NO_EVT_FINISHED) && p_cb->handler) - { - p_cb->handler(NRFX_PWM_EVT_FINISHED); - } - } - - // The STOPPED event is always propagated to the user handler. - if (nrf_pwm_event_check(p_pwm, NRF_PWM_EVENT_STOPPED)) - { - nrf_pwm_event_clear(p_pwm, NRF_PWM_EVENT_STOPPED); - - p_cb->state = NRFX_DRV_STATE_INITIALIZED; - if (p_cb->handler) - { - p_cb->handler(NRFX_PWM_EVT_STOPPED); - } - } -} - - -#if defined(USE_DMA_ISSUE_WORKAROUND) -// See 'start_playback' why this is needed. -void DMA_ISSUE_EGU_IRQHandler(void) -{ - int i; - for (i = 0; i < NRFX_PWM_ENABLED_COUNT; ++i) - { - volatile uint32_t * p_event_reg = - nrf_egu_event_triggered_address_get(DMA_ISSUE_EGU, i); - if (*p_event_reg) - { - *p_event_reg = 0; - *(volatile uint32_t *)(m_cb[i].starting_task_address) = 1; - } - } -} -#endif - - -#if NRFX_CHECK(NRFX_PWM0_ENABLED) -void nrfx_pwm_0_irq_handler(void) -{ - irq_handler(NRF_PWM0, &m_cb[NRFX_PWM0_INST_IDX]); -} -#endif - -#if NRFX_CHECK(NRFX_PWM1_ENABLED) -void nrfx_pwm_1_irq_handler(void) -{ - irq_handler(NRF_PWM1, &m_cb[NRFX_PWM1_INST_IDX]); -} -#endif - -#if NRFX_CHECK(NRFX_PWM2_ENABLED) -void nrfx_pwm_2_irq_handler(void) -{ - irq_handler(NRF_PWM2, &m_cb[NRFX_PWM2_INST_IDX]); -} -#endif - -#if NRFX_CHECK(NRFX_PWM3_ENABLED) -void nrfx_pwm_3_irq_handler(void) -{ - irq_handler(NRF_PWM3, &m_cb[NRFX_PWM3_INST_IDX]); -} -#endif - -#endif // NRFX_CHECK(NRFX_PWM_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_qdec.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_qdec.c deleted file mode 100644 index 40273a74da..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_qdec.c +++ /dev/null @@ -1,201 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include - -#if NRFX_CHECK(NRFX_QDEC_ENABLED) - -#include -#include - -#define NRFX_LOG_MODULE QDEC -#include - -#define EVT_TO_STR(event) \ - (event == NRF_QDEC_EVENT_SAMPLERDY ? "NRF_QDEC_EVENT_SAMPLERDY" : \ - (event == NRF_QDEC_EVENT_REPORTRDY ? "NRF_QDEC_EVENT_REPORTRDY" : \ - (event == NRF_QDEC_EVENT_ACCOF ? "NRF_QDEC_EVENT_ACCOF" : \ - "UNKNOWN EVENT"))) - - -static nrfx_qdec_event_handler_t m_qdec_event_handler = NULL; -static nrfx_drv_state_t m_state = NRFX_DRV_STATE_UNINITIALIZED; - -void nrfx_qdec_irq_handler(void) -{ - nrfx_qdec_event_t event; - if ( nrf_qdec_event_check(NRF_QDEC_EVENT_SAMPLERDY) && - nrf_qdec_int_enable_check(NRF_QDEC_INT_SAMPLERDY_MASK) ) - { - nrf_qdec_event_clear(NRF_QDEC_EVENT_SAMPLERDY); - NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRF_QDEC_EVENT_SAMPLERDY)); - - event.type = NRF_QDEC_EVENT_SAMPLERDY; - event.data.sample.value = (int8_t)nrf_qdec_sample_get(); - m_qdec_event_handler(event); - } - - if ( nrf_qdec_event_check(NRF_QDEC_EVENT_REPORTRDY) && - nrf_qdec_int_enable_check(NRF_QDEC_INT_REPORTRDY_MASK) ) - { - nrf_qdec_event_clear(NRF_QDEC_EVENT_REPORTRDY); - NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRF_QDEC_EVENT_REPORTRDY)); - - event.type = NRF_QDEC_EVENT_REPORTRDY; - - event.data.report.acc = (int16_t)nrf_qdec_accread_get(); - event.data.report.accdbl = (uint16_t)nrf_qdec_accdblread_get(); - m_qdec_event_handler(event); - } - - if ( nrf_qdec_event_check(NRF_QDEC_EVENT_ACCOF) && - nrf_qdec_int_enable_check(NRF_QDEC_INT_ACCOF_MASK) ) - { - nrf_qdec_event_clear(NRF_QDEC_EVENT_ACCOF); - NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRF_QDEC_EVENT_ACCOF)); - - event.type = NRF_QDEC_EVENT_ACCOF; - m_qdec_event_handler(event); - } -} - - -nrfx_err_t nrfx_qdec_init(nrfx_qdec_config_t const * p_config, - nrfx_qdec_event_handler_t event_handler) -{ - NRFX_ASSERT(p_config); - NRFX_ASSERT(event_handler); - nrfx_err_t err_code; - - if (m_state != NRFX_DRV_STATE_UNINITIALIZED) - { - err_code = NRFX_ERROR_INVALID_STATE; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - m_qdec_event_handler = event_handler; - - nrf_qdec_sampleper_set(p_config->sampleper); - nrf_gpio_cfg_input(p_config->pselled, NRF_GPIO_PIN_NOPULL); - nrf_gpio_cfg_input(p_config->psela, NRF_GPIO_PIN_NOPULL); - nrf_gpio_cfg_input(p_config->pselb, NRF_GPIO_PIN_NOPULL); - nrf_qdec_pio_assign(p_config->psela, p_config->pselb, p_config->pselled); - nrf_qdec_ledpre_set(p_config->ledpre); - nrf_qdec_ledpol_set(p_config->ledpol); - nrf_qdec_shorts_enable(NRF_QDEC_SHORT_REPORTRDY_READCLRACC_MASK); - - if (p_config->dbfen) - { - nrf_qdec_dbfen_enable(); - } - else - { - nrf_qdec_dbfen_disable(); - } - - uint32_t int_mask = NRF_QDEC_INT_ACCOF_MASK; - - if (p_config->reportper != NRF_QDEC_REPORTPER_DISABLED) - { - nrf_qdec_reportper_set(p_config->reportper); - int_mask |= NRF_QDEC_INT_REPORTRDY_MASK; - } - - if (p_config->sample_inten) - { - int_mask |= NRF_QDEC_INT_SAMPLERDY_MASK; - } - - nrf_qdec_int_enable(int_mask); - NRFX_IRQ_PRIORITY_SET(QDEC_IRQn, p_config->interrupt_priority); - NRFX_IRQ_ENABLE(QDEC_IRQn); - - m_state = NRFX_DRV_STATE_INITIALIZED; - - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -void nrfx_qdec_uninit(void) -{ - NRFX_ASSERT(m_state != NRFX_DRV_STATE_UNINITIALIZED); - nrfx_qdec_disable(); - NRFX_IRQ_DISABLE(QDEC_IRQn); - m_state = NRFX_DRV_STATE_UNINITIALIZED; - NRFX_LOG_INFO("Uninitialized."); -} - -void nrfx_qdec_enable(void) -{ - NRFX_ASSERT(m_state == NRFX_DRV_STATE_INITIALIZED); - nrf_qdec_enable(); - nrf_qdec_task_trigger(NRF_QDEC_TASK_START); - m_state = NRFX_DRV_STATE_POWERED_ON; - NRFX_LOG_INFO("Enabled."); -} - -void nrfx_qdec_disable(void) -{ - NRFX_ASSERT(m_state == NRFX_DRV_STATE_POWERED_ON); - nrf_qdec_task_trigger(NRF_QDEC_TASK_STOP); - nrf_qdec_disable(); - m_state = NRFX_DRV_STATE_INITIALIZED; - NRFX_LOG_INFO("Disabled."); -} - -void nrfx_qdec_accumulators_read(int16_t * p_acc, int16_t * p_accdbl) -{ - NRFX_ASSERT(m_state == NRFX_DRV_STATE_POWERED_ON); - nrf_qdec_task_trigger(NRF_QDEC_TASK_READCLRACC); - - *p_acc = (int16_t)nrf_qdec_accread_get(); - *p_accdbl = (int16_t)nrf_qdec_accdblread_get(); - - NRFX_LOG_DEBUG("Accumulators data, ACC register:"); - NRFX_LOG_HEXDUMP_DEBUG((uint8_t *)p_acc, sizeof(p_acc[0])); - NRFX_LOG_DEBUG("Accumulators data, ACCDBL register:"); - NRFX_LOG_HEXDUMP_DEBUG((uint8_t *)p_accdbl, sizeof(p_accdbl[0])); -} - -#endif // NRFX_CHECK(NRFX_QDEC_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_qspi.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_qspi.c deleted file mode 100644 index 59eed976f0..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_qspi.c +++ /dev/null @@ -1,337 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include - -#if NRFX_CHECK(NRFX_QSPI_ENABLED) - -#include - - -/** - * @brief Command byte used to read status register. - * - */ -#define QSPI_STD_CMD_RDSR 0x05 - -/** - * @brief Byte used to mask status register and retrieve the write-in-progess bit. - * - */ -#define QSPI_MEM_STATUSREG_WIP_Pos 0x01 - -/** - * @brief Default time used in timeout function. - */ -#define QSPI_DEF_WAIT_TIME_US 10 - -/** - * @brief Default number of tries in timeout function. - */ -#define QSPI_DEF_WAIT_ATTEMPTS 100 - -/** - * @brief Control block - driver instance local data. - */ -typedef struct -{ - nrfx_qspi_handler_t handler; /**< Handler. */ - nrfx_drv_state_t state; /**< Driver state. */ - volatile bool interrupt_driven; /**< Information if the current operation is performed and is interrupt-driven. */ - void * p_context; /**< Driver context used in interrupt. */ -} qspi_control_block_t; - -static qspi_control_block_t m_cb; - -static nrfx_err_t qspi_task_perform(nrf_qspi_task_t task) -{ - // Wait for peripheral - if (m_cb.interrupt_driven) - { - return NRFX_ERROR_BUSY; - } - - nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY); - - if (m_cb.handler) - { - m_cb.interrupt_driven = true; - nrf_qspi_int_enable(NRF_QSPI, NRF_QSPI_INT_READY_MASK); - } - - nrf_qspi_task_trigger(NRF_QSPI, task); - - if (m_cb.handler == NULL) - { - while (!nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY)) - {}; - } - return NRFX_SUCCESS; -} - -static bool qspi_pins_configure(nrf_qspi_pins_t const * p_config) -{ - // Check if the user set meaningful values to struct fields. If not, return false. - if ((p_config->sck_pin == NRF_QSPI_PIN_NOT_CONNECTED) || - (p_config->csn_pin == NRF_QSPI_PIN_NOT_CONNECTED) || - (p_config->io0_pin == NRF_QSPI_PIN_NOT_CONNECTED) || - (p_config->io1_pin == NRF_QSPI_PIN_NOT_CONNECTED)) - { - return false; - } - - nrf_qspi_pins_set(NRF_QSPI, p_config); - - return true; -} - -nrfx_err_t nrfx_qspi_init(nrfx_qspi_config_t const * p_config, - nrfx_qspi_handler_t handler, - void * p_context) -{ - NRFX_ASSERT(p_config); - if (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED) - { - return NRFX_ERROR_INVALID_STATE; - } - - if (!qspi_pins_configure(&p_config->pins)) - { - return NRFX_ERROR_INVALID_PARAM; - } - - nrf_qspi_xip_offset_set(NRF_QSPI, p_config->xip_offset); - nrf_qspi_ifconfig0_set(NRF_QSPI, &p_config->prot_if); - nrf_qspi_ifconfig1_set(NRF_QSPI, &p_config->phy_if); - - m_cb.interrupt_driven = false; - m_cb.handler = handler; - m_cb.p_context = p_context; - - /* QSPI interrupt is disabled because the device should be enabled in polling mode (wait for activate - task event ready)*/ - nrf_qspi_int_disable(NRF_QSPI, NRF_QSPI_INT_READY_MASK); - - if (handler) - { - NRFX_IRQ_PRIORITY_SET(QSPI_IRQn, p_config->irq_priority); - NRFX_IRQ_ENABLE(QSPI_IRQn); - } - - m_cb.state = NRFX_DRV_STATE_INITIALIZED; - - nrf_qspi_enable(NRF_QSPI); - - nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY); - nrf_qspi_task_trigger(NRF_QSPI, NRF_QSPI_TASK_ACTIVATE); - - // Waiting for the peripheral to activate - bool result; - NRFX_WAIT_FOR(nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY), - QSPI_DEF_WAIT_ATTEMPTS, - QSPI_DEF_WAIT_TIME_US, - result); - - if (!result) - { - return NRFX_ERROR_TIMEOUT; - } - - return NRFX_SUCCESS; -} - -nrfx_err_t nrfx_qspi_cinstr_xfer(nrf_qspi_cinstr_conf_t const * p_config, - void const * p_tx_buffer, - void * p_rx_buffer) -{ - NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); - - if (m_cb.interrupt_driven) - { - return NRFX_ERROR_BUSY; - } - - nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY); - /* In some cases, only opcode should be sent. To prevent execution, set function code is - * surrounded by an if. - */ - if (p_tx_buffer) - { - nrf_qspi_cinstrdata_set(NRF_QSPI, p_config->length, p_tx_buffer); - } - nrf_qspi_int_disable(NRF_QSPI, NRF_QSPI_INT_READY_MASK); - - nrf_qspi_cinstr_transfer_start(NRF_QSPI, p_config); - - bool result; - NRFX_WAIT_FOR(nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY), - QSPI_DEF_WAIT_ATTEMPTS, - QSPI_DEF_WAIT_TIME_US, - result); - - if (!result) - { - // This timeout should never occur when WIPWAIT is not active, since in this - // case the QSPI peripheral should send the command immediately, without any - // waiting for previous write to complete. - NRFX_ASSERT(p_config->wipwait); - - return NRFX_ERROR_TIMEOUT; - } - nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY); - nrf_qspi_int_enable(NRF_QSPI, NRF_QSPI_INT_READY_MASK); - - if (p_rx_buffer) - { - nrf_qspi_cinstrdata_get(NRF_QSPI, p_config->length, p_rx_buffer); - } - - return NRFX_SUCCESS; -} - -nrfx_err_t nrfx_qspi_cinstr_quick_send(uint8_t opcode, - nrf_qspi_cinstr_len_t length, - void const * p_tx_buffer) -{ - nrf_qspi_cinstr_conf_t config = NRFX_QSPI_DEFAULT_CINSTR(opcode, length); - return nrfx_qspi_cinstr_xfer(&config, p_tx_buffer, NULL); -} - -nrfx_err_t nrfx_qspi_mem_busy_check(void) -{ - nrfx_err_t ret_code; - uint8_t status_value = 0; - - nrf_qspi_cinstr_conf_t const config = - NRFX_QSPI_DEFAULT_CINSTR(QSPI_STD_CMD_RDSR, - NRF_QSPI_CINSTR_LEN_2B); - ret_code = nrfx_qspi_cinstr_xfer(&config, &status_value, &status_value); - - if (ret_code != NRFX_SUCCESS) - { - return ret_code; - } - - if ((status_value & QSPI_MEM_STATUSREG_WIP_Pos) != 0x00) - { - return NRFX_ERROR_BUSY; - } - - return NRFX_SUCCESS; -} - -void nrfx_qspi_uninit(void) -{ - NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); - - nrf_qspi_int_disable(NRF_QSPI, NRF_QSPI_INT_READY_MASK); - - nrf_qspi_disable(NRF_QSPI); - - nrf_qspi_task_trigger(NRF_QSPI, NRF_QSPI_TASK_DEACTIVATE); - - // Workaround for nRF52840 anomaly 122: Current consumption is too high. - *(volatile uint32_t *)0x40029054ul = 1ul; - - NRFX_IRQ_DISABLE(QSPI_IRQn); - - nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY); - - m_cb.state = NRFX_DRV_STATE_UNINITIALIZED; -} - -nrfx_err_t nrfx_qspi_write(void const * p_tx_buffer, - size_t tx_buffer_length, - uint32_t dst_address) -{ - NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); - NRFX_ASSERT(p_tx_buffer != NULL); - - if (!nrfx_is_in_ram(p_tx_buffer)) - { - return NRFX_ERROR_INVALID_ADDR; - } - - nrf_qspi_write_buffer_set(NRF_QSPI, p_tx_buffer, tx_buffer_length, dst_address); - return qspi_task_perform(NRF_QSPI_TASK_WRITESTART); - -} - -nrfx_err_t nrfx_qspi_read(void * p_rx_buffer, - size_t rx_buffer_length, - uint32_t src_address) -{ - NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); - NRFX_ASSERT(p_rx_buffer != NULL); - - if (!nrfx_is_in_ram(p_rx_buffer)) - { - return NRFX_ERROR_INVALID_ADDR; - } - - nrf_qspi_read_buffer_set(NRF_QSPI, p_rx_buffer, rx_buffer_length, src_address); - return qspi_task_perform(NRF_QSPI_TASK_READSTART); -} - -nrfx_err_t nrfx_qspi_erase(nrf_qspi_erase_len_t length, - uint32_t start_address) -{ - NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); - nrf_qspi_erase_ptr_set(NRF_QSPI, start_address, length); - return qspi_task_perform(NRF_QSPI_TASK_ERASESTART); -} - -nrfx_err_t nrfx_qspi_chip_erase(void) -{ - return nrfx_qspi_erase(NRF_QSPI_ERASE_LEN_ALL, 0); -} - -void nrfx_qspi_irq_handler(void) -{ - // Catch Event ready interrupts - if (nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY)) - { - m_cb.interrupt_driven = false; - nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY); - m_cb.handler(NRFX_QSPI_EVENT_DONE, m_cb.p_context); - } -} - -#endif // NRFX_CHECK(NRFX_QSPI_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_rng.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_rng.c deleted file mode 100644 index 66e2beb20b..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_rng.c +++ /dev/null @@ -1,122 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include - -#if NRFX_CHECK(NRFX_RNG_ENABLED) - -#include - -#define NRFX_LOG_MODULE RNG -#include - -/** - * @brief Internal state of RNG driver. - */ -static nrfx_drv_state_t m_rng_state; - -/** - * @brief Pointer to handler calling from interrupt routine. - */ -static nrfx_rng_evt_handler_t m_rng_hndl; - -nrfx_err_t nrfx_rng_init(nrfx_rng_config_t const * p_config, nrfx_rng_evt_handler_t handler) -{ - NRFX_ASSERT(p_config); - NRFX_ASSERT(handler); - if (m_rng_state != NRFX_DRV_STATE_UNINITIALIZED) - { - return NRFX_ERROR_ALREADY_INITIALIZED; - } - - m_rng_hndl = handler; - - if (p_config->error_correction) - { - nrf_rng_error_correction_enable(); - } - nrf_rng_shorts_disable(NRF_RNG_SHORT_VALRDY_STOP_MASK); - NRFX_IRQ_PRIORITY_SET(RNG_IRQn, p_config->interrupt_priority); - NRFX_IRQ_ENABLE(RNG_IRQn); - - m_rng_state = NRFX_DRV_STATE_INITIALIZED; - - return NRFX_SUCCESS; -} - -void nrfx_rng_start(void) -{ - NRFX_ASSERT(m_rng_state == NRFX_DRV_STATE_INITIALIZED); - nrf_rng_event_clear(NRF_RNG_EVENT_VALRDY); - nrf_rng_int_enable(NRF_RNG_INT_VALRDY_MASK); - nrf_rng_task_trigger(NRF_RNG_TASK_START); -} - -void nrfx_rng_stop(void) -{ - NRFX_ASSERT(m_rng_state == NRFX_DRV_STATE_INITIALIZED); - nrf_rng_int_disable(NRF_RNG_INT_VALRDY_MASK); - nrf_rng_task_trigger(NRF_RNG_TASK_STOP); -} - -void nrfx_rng_uninit(void) -{ - NRFX_ASSERT(m_rng_state == NRFX_DRV_STATE_INITIALIZED); - - nrf_rng_int_disable(NRF_RNG_INT_VALRDY_MASK); - nrf_rng_task_trigger(NRF_RNG_TASK_STOP); - NRFX_IRQ_DISABLE(RNG_IRQn); - - m_rng_state = NRFX_DRV_STATE_UNINITIALIZED; - NRFX_LOG_INFO("Uninitialized."); -} - -void nrfx_rng_irq_handler(void) -{ - nrf_rng_event_clear(NRF_RNG_EVENT_VALRDY); - - uint8_t rng_value = nrf_rng_random_value_get(); - - m_rng_hndl(rng_value); - - NRFX_LOG_DEBUG("Event: NRF_RNG_EVENT_VALRDY."); -} - -#endif // NRFX_CHECK(NRFX_RNG_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_rtc.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_rtc.c deleted file mode 100644 index b6094e67b3..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_rtc.c +++ /dev/null @@ -1,348 +0,0 @@ -/** - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include - -#if NRFX_CHECK(NRFX_RTC_ENABLED) - -#if !(NRFX_CHECK(NRFX_RTC0_ENABLED) || NRFX_CHECK(NRFX_RTC1_ENABLED) || \ - NRFX_CHECK(NRFX_RTC2_ENABLED)) -#error "No enabled RTC instances. Check ." -#endif - -#include - -#define NRFX_LOG_MODULE RTC -#include - -#define EVT_TO_STR(event) \ - (event == NRF_RTC_EVENT_TICK ? "NRF_RTC_EVENT_TICK" : \ - (event == NRF_RTC_EVENT_OVERFLOW ? "NRF_RTC_EVENT_OVERFLOW" : \ - (event == NRF_RTC_EVENT_COMPARE_0 ? "NRF_RTC_EVENT_COMPARE_0" : \ - (event == NRF_RTC_EVENT_COMPARE_1 ? "NRF_RTC_EVENT_COMPARE_1" : \ - (event == NRF_RTC_EVENT_COMPARE_2 ? "NRF_RTC_EVENT_COMPARE_2" : \ - (event == NRF_RTC_EVENT_COMPARE_3 ? "NRF_RTC_EVENT_COMPARE_3" : \ - "UNKNOWN EVENT")))))) - - -/**@brief RTC driver instance control block structure. */ -typedef struct -{ - nrfx_drv_state_t state; /**< Instance state. */ - bool reliable; /**< Reliable mode flag. */ - uint8_t tick_latency; /**< Maximum length of interrupt handler in ticks (max 7.7 ms). */ -} nrfx_rtc_cb_t; - -// User callbacks local storage. -static nrfx_rtc_handler_t m_handlers[NRFX_RTC_ENABLED_COUNT]; -static nrfx_rtc_cb_t m_cb[NRFX_RTC_ENABLED_COUNT]; - -nrfx_err_t nrfx_rtc_init(nrfx_rtc_t const * const p_instance, - nrfx_rtc_config_t const * p_config, - nrfx_rtc_handler_t handler) -{ - NRFX_ASSERT(p_config); - NRFX_ASSERT(handler); - nrfx_err_t err_code; - - m_handlers[p_instance->instance_id] = handler; - - if (m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED) - { - err_code = NRFX_ERROR_INVALID_STATE; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - NRFX_IRQ_PRIORITY_SET(p_instance->irq, p_config->interrupt_priority); - NRFX_IRQ_ENABLE(p_instance->irq); - nrf_rtc_prescaler_set(p_instance->p_reg, p_config->prescaler); - m_cb[p_instance->instance_id].reliable = p_config->reliable; - m_cb[p_instance->instance_id].tick_latency = p_config->tick_latency; - m_cb[p_instance->instance_id].state = NRFX_DRV_STATE_INITIALIZED; - - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -void nrfx_rtc_uninit(nrfx_rtc_t const * const p_instance) -{ - uint32_t mask = NRF_RTC_INT_TICK_MASK | - NRF_RTC_INT_OVERFLOW_MASK | - NRF_RTC_INT_COMPARE0_MASK | - NRF_RTC_INT_COMPARE1_MASK | - NRF_RTC_INT_COMPARE2_MASK | - NRF_RTC_INT_COMPARE3_MASK; - NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); - - NRFX_IRQ_DISABLE(p_instance->irq); - - nrf_rtc_task_trigger(p_instance->p_reg, NRF_RTC_TASK_STOP); - nrf_rtc_event_disable(p_instance->p_reg, mask); - nrf_rtc_int_disable(p_instance->p_reg, mask); - - m_cb[p_instance->instance_id].state = NRFX_DRV_STATE_UNINITIALIZED; - NRFX_LOG_INFO("Uninitialized."); -} - -void nrfx_rtc_enable(nrfx_rtc_t const * const p_instance) -{ - NRFX_ASSERT(m_cb[p_instance->instance_id].state == NRFX_DRV_STATE_INITIALIZED); - - nrf_rtc_task_trigger(p_instance->p_reg, NRF_RTC_TASK_START); - m_cb[p_instance->instance_id].state = NRFX_DRV_STATE_POWERED_ON; - NRFX_LOG_INFO("Enabled."); -} - -void nrfx_rtc_disable(nrfx_rtc_t const * const p_instance) -{ - NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); - - nrf_rtc_task_trigger(p_instance->p_reg, NRF_RTC_TASK_STOP); - m_cb[p_instance->instance_id].state = NRFX_DRV_STATE_INITIALIZED; - NRFX_LOG_INFO("Disabled."); -} - -nrfx_err_t nrfx_rtc_cc_disable(nrfx_rtc_t const * const p_instance, uint32_t channel) -{ - NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); - NRFX_ASSERT(channelcc_channel_count); - - nrfx_err_t err_code; - uint32_t int_mask = RTC_CHANNEL_INT_MASK(channel); - nrf_rtc_event_t event = RTC_CHANNEL_EVENT_ADDR(channel); - - nrf_rtc_event_disable(p_instance->p_reg,int_mask); - if (nrf_rtc_int_is_enabled(p_instance->p_reg,int_mask)) - { - nrf_rtc_int_disable(p_instance->p_reg,int_mask); - if (nrf_rtc_event_pending(p_instance->p_reg,event)) - { - nrf_rtc_event_clear(p_instance->p_reg,event); - err_code = NRFX_ERROR_TIMEOUT; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - } - NRFX_LOG_INFO("RTC id: %d, channel disabled: %lu.", p_instance->instance_id, channel); - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -nrfx_err_t nrfx_rtc_cc_set(nrfx_rtc_t const * const p_instance, - uint32_t channel, - uint32_t val, - bool enable_irq) -{ - NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); - NRFX_ASSERT(channelcc_channel_count); - - nrfx_err_t err_code; - uint32_t int_mask = RTC_CHANNEL_INT_MASK(channel); - nrf_rtc_event_t event = RTC_CHANNEL_EVENT_ADDR(channel); - - nrf_rtc_event_disable(p_instance->p_reg, int_mask); - nrf_rtc_int_disable(p_instance->p_reg, int_mask); - - val = RTC_WRAP(val); - if (m_cb[p_instance->instance_id].reliable) - { - nrf_rtc_cc_set(p_instance->p_reg,channel,val); - uint32_t cnt = nrf_rtc_counter_get(p_instance->p_reg); - int32_t diff = cnt - val; - if (cnt < val) - { - diff += RTC_COUNTER_COUNTER_Msk; - } - if (diff < m_cb[p_instance->instance_id].tick_latency) - { - err_code = NRFX_ERROR_TIMEOUT; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - } - else - { - nrf_rtc_cc_set(p_instance->p_reg,channel,val); - } - - if (enable_irq) - { - nrf_rtc_event_clear(p_instance->p_reg,event); - nrf_rtc_int_enable(p_instance->p_reg, int_mask); - } - nrf_rtc_event_enable(p_instance->p_reg,int_mask); - - NRFX_LOG_INFO("RTC id: %d, channel enabled: %lu, compare value: %lu.", - p_instance->instance_id, - channel, - val); - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -void nrfx_rtc_tick_enable(nrfx_rtc_t const * const p_instance, bool enable_irq) -{ - nrf_rtc_event_t event = NRF_RTC_EVENT_TICK; - uint32_t mask = NRF_RTC_INT_TICK_MASK; - - nrf_rtc_event_clear(p_instance->p_reg, event); - nrf_rtc_event_enable(p_instance->p_reg, mask); - if (enable_irq) - { - nrf_rtc_int_enable(p_instance->p_reg, mask); - } - NRFX_LOG_INFO("Tick events enabled."); -} - -void nrfx_rtc_tick_disable(nrfx_rtc_t const * const p_instance) -{ - uint32_t mask = NRF_RTC_INT_TICK_MASK; - - nrf_rtc_event_disable(p_instance->p_reg, mask); - nrf_rtc_int_disable(p_instance->p_reg, mask); - NRFX_LOG_INFO("Tick events disabled."); -} - -void nrfx_rtc_overflow_enable(nrfx_rtc_t const * const p_instance, bool enable_irq) -{ - nrf_rtc_event_t event = NRF_RTC_EVENT_OVERFLOW; - uint32_t mask = NRF_RTC_INT_OVERFLOW_MASK; - - nrf_rtc_event_clear(p_instance->p_reg, event); - nrf_rtc_event_enable(p_instance->p_reg, mask); - if (enable_irq) - { - nrf_rtc_int_enable(p_instance->p_reg, mask); - } -} - -void nrfx_rtc_overflow_disable(nrfx_rtc_t const * const p_instance) -{ - uint32_t mask = NRF_RTC_INT_OVERFLOW_MASK; - nrf_rtc_event_disable(p_instance->p_reg, mask); - nrf_rtc_int_disable(p_instance->p_reg, mask); -} - -uint32_t nrfx_rtc_max_ticks_get(nrfx_rtc_t const * const p_instance) -{ - uint32_t ticks; - if (m_cb[p_instance->instance_id].reliable) - { - ticks = RTC_COUNTER_COUNTER_Msk - m_cb[p_instance->instance_id].tick_latency; - } - else - { - ticks = RTC_COUNTER_COUNTER_Msk; - } - return ticks; -} - -static void irq_handler(NRF_RTC_Type * p_reg, - uint32_t instance_id, - uint32_t channel_count) -{ - uint32_t i; - uint32_t int_mask = (uint32_t)NRF_RTC_INT_COMPARE0_MASK; - nrf_rtc_event_t event = NRF_RTC_EVENT_COMPARE_0; - - for (i = 0; i < channel_count; i++) - { - if (nrf_rtc_int_is_enabled(p_reg,int_mask) && nrf_rtc_event_pending(p_reg,event)) - { - nrf_rtc_event_disable(p_reg,int_mask); - nrf_rtc_int_disable(p_reg,int_mask); - nrf_rtc_event_clear(p_reg,event); - NRFX_LOG_DEBUG("Event: %s, instance id: %lu.", EVT_TO_STR(event), instance_id); - m_handlers[instance_id]((nrfx_rtc_int_type_t)i); - } - int_mask <<= 1; - event = (nrf_rtc_event_t)((uint32_t)event + sizeof(uint32_t)); - } - event = NRF_RTC_EVENT_TICK; - if (nrf_rtc_int_is_enabled(p_reg,NRF_RTC_INT_TICK_MASK) && - nrf_rtc_event_pending(p_reg, event)) - { - nrf_rtc_event_clear(p_reg, event); - NRFX_LOG_DEBUG("Event: %s, instance id: %lu.", EVT_TO_STR(event), instance_id); - m_handlers[instance_id](NRFX_RTC_INT_TICK); - } - - event = NRF_RTC_EVENT_OVERFLOW; - if (nrf_rtc_int_is_enabled(p_reg,NRF_RTC_INT_OVERFLOW_MASK) && - nrf_rtc_event_pending(p_reg, event)) - { - nrf_rtc_event_clear(p_reg,event); - NRFX_LOG_DEBUG("Event: %s, instance id: %lu.", EVT_TO_STR(event), instance_id); - m_handlers[instance_id](NRFX_RTC_INT_OVERFLOW); - } -} - -#if NRFX_CHECK(NRFX_RTC0_ENABLED) -void nrfx_rtc_0_irq_handler(void) -{ - irq_handler(NRF_RTC0, NRFX_RTC0_INST_IDX, NRF_RTC_CC_CHANNEL_COUNT(0)); -} -#endif - -#if NRFX_CHECK(NRFX_RTC1_ENABLED) -void nrfx_rtc_1_irq_handler(void) -{ - irq_handler(NRF_RTC1, NRFX_RTC1_INST_IDX, NRF_RTC_CC_CHANNEL_COUNT(1)); -} -#endif - -#if NRFX_CHECK(NRFX_RTC2_ENABLED) -void nrfx_rtc_2_irq_handler(void) -{ - irq_handler(NRF_RTC2, NRFX_RTC2_INST_IDX, NRF_RTC_CC_CHANNEL_COUNT(2)); -} -#endif - -#endif // NRFX_CHECK(NRFX_RTC_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_saadc.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_saadc.c deleted file mode 100644 index 20e79e9a61..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_saadc.c +++ /dev/null @@ -1,639 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include - -#if NRFX_CHECK(NRFX_SAADC_ENABLED) -#include - -#define NRFX_LOG_MODULE SAADC -#include - -#define EVT_TO_STR(event) \ - (event == NRF_SAADC_EVENT_STARTED ? "NRF_SAADC_EVENT_STARTED" : \ - (event == NRF_SAADC_EVENT_END ? "NRF_SAADC_EVENT_END" : \ - (event == NRF_SAADC_EVENT_DONE ? "NRF_SAADC_EVENT_DONE" : \ - (event == NRF_SAADC_EVENT_RESULTDONE ? "NRF_SAADC_EVENT_RESULTDONE" : \ - (event == NRF_SAADC_EVENT_CALIBRATEDONE ? "NRF_SAADC_EVENT_CALIBRATEDONE" : \ - (event == NRF_SAADC_EVENT_STOPPED ? "NRF_SAADC_EVENT_STOPPED" : \ - "UNKNOWN EVENT")))))) - - -typedef enum -{ - NRF_SAADC_STATE_IDLE = 0, - NRF_SAADC_STATE_BUSY = 1, - NRF_SAADC_STATE_CALIBRATION = 2 -} nrf_saadc_state_t; - - -typedef struct -{ - nrf_saadc_input_t pselp; - nrf_saadc_input_t pseln; -} nrf_saadc_psel_buffer; - -/** @brief SAADC control block.*/ -typedef struct -{ - nrfx_saadc_event_handler_t event_handler; ///< Event handler function pointer. - volatile nrf_saadc_value_t * p_buffer; ///< Sample buffer. - volatile uint16_t buffer_size; ///< Size of the sample buffer. - volatile nrf_saadc_value_t * p_secondary_buffer; ///< Secondary sample buffer. - volatile nrf_saadc_state_t adc_state; ///< State of the SAADC. - uint32_t limits_enabled_flags; ///< Enabled limits flags. - uint16_t secondary_buffer_size; ///< Size of the secondary buffer. - uint16_t buffer_size_left; ///< When low power mode is active indicates how many samples left to convert on current buffer. - nrf_saadc_psel_buffer psel[NRF_SAADC_CHANNEL_COUNT]; ///< Pin configurations of SAADC channels. - nrfx_drv_state_t state; ///< Driver initialization state. - uint8_t active_channels; ///< Number of enabled SAADC channels. - bool low_power_mode; ///< Indicates if low power mode is active. - bool conversions_end; ///< When low power mode is active indicates end of conversions on current buffer. -} nrfx_saadc_cb_t; - -static nrfx_saadc_cb_t m_cb; - -#define LOW_LIMIT_TO_FLAG(channel) ((2 * channel + 1)) -#define HIGH_LIMIT_TO_FLAG(channel) ((2 * channel)) -#define FLAG_IDX_TO_EVENT(idx) ((nrf_saadc_event_t)((uint32_t)NRF_SAADC_EVENT_CH0_LIMITH + \ - 4 * idx)) -#define LIMIT_EVENT_TO_CHANNEL(event) (uint8_t)(((uint32_t)event - \ - (uint32_t)NRF_SAADC_EVENT_CH0_LIMITH) / 8) -#define LIMIT_EVENT_TO_LIMIT_TYPE(event)((((uint32_t)event - (uint32_t)NRF_SAADC_EVENT_CH0_LIMITH) & 4) \ - ? NRF_SAADC_LIMIT_LOW : NRF_SAADC_LIMIT_HIGH) -#define HW_TIMEOUT 10000 - -void nrfx_saadc_irq_handler(void) -{ - if (nrf_saadc_event_check(NRF_SAADC_EVENT_END)) - { - nrf_saadc_event_clear(NRF_SAADC_EVENT_END); - NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRF_SAADC_EVENT_END)); - - if (!m_cb.low_power_mode || m_cb.conversions_end) - { - nrfx_saadc_evt_t evt; - evt.type = NRFX_SAADC_EVT_DONE; - evt.data.done.p_buffer = (nrf_saadc_value_t *)m_cb.p_buffer; - evt.data.done.size = m_cb.buffer_size; - - if (m_cb.p_secondary_buffer == NULL) - { - m_cb.adc_state = NRF_SAADC_STATE_IDLE; - } - else - { - m_cb.buffer_size_left = m_cb.secondary_buffer_size; - m_cb.p_buffer = m_cb.p_secondary_buffer; - m_cb.buffer_size = m_cb.secondary_buffer_size; - m_cb.p_secondary_buffer = NULL; - if (!m_cb.low_power_mode) - { - nrf_saadc_task_trigger(NRF_SAADC_TASK_START); - } - } - m_cb.event_handler(&evt); - m_cb.conversions_end = false; - } - } - if (m_cb.low_power_mode && nrf_saadc_event_check(NRF_SAADC_EVENT_STARTED)) - { - nrf_saadc_event_clear(NRF_SAADC_EVENT_STARTED); - NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRF_SAADC_EVENT_STARTED)); - - if (m_cb.buffer_size_left > m_cb.active_channels) - { - // More samples to convert than for single event. - m_cb.buffer_size_left -= m_cb.active_channels; - nrf_saadc_buffer_init((nrf_saadc_value_t *)&m_cb.p_buffer[m_cb.buffer_size - - m_cb.buffer_size_left], - m_cb.active_channels); - } - else if ((m_cb.buffer_size_left == m_cb.active_channels) && - - (m_cb.p_secondary_buffer != NULL)) - { - // Samples to convert for one event, prepare next buffer. - m_cb.conversions_end = true; - m_cb.buffer_size_left = 0; - nrf_saadc_buffer_init((nrf_saadc_value_t *)m_cb.p_secondary_buffer, - m_cb.active_channels); - } - else if (m_cb.buffer_size_left == m_cb.active_channels) - { - // Samples to convert for one event, but no second buffer. - m_cb.conversions_end = true; - m_cb.buffer_size_left = 0; - } - nrf_saadc_event_clear(NRF_SAADC_EVENT_END); - nrf_saadc_task_trigger(NRF_SAADC_TASK_SAMPLE); - } - if (nrf_saadc_event_check(NRF_SAADC_EVENT_CALIBRATEDONE)) - { - nrf_saadc_event_clear(NRF_SAADC_EVENT_CALIBRATEDONE); - NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRF_SAADC_EVENT_CALIBRATEDONE)); - m_cb.adc_state = NRF_SAADC_STATE_IDLE; - - nrfx_saadc_evt_t evt; - evt.type = NRFX_SAADC_EVT_CALIBRATEDONE; - m_cb.event_handler(&evt); - } - if (nrf_saadc_event_check(NRF_SAADC_EVENT_STOPPED)) - { - nrf_saadc_event_clear(NRF_SAADC_EVENT_STOPPED); - NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRF_SAADC_EVENT_STOPPED)); - m_cb.adc_state = NRF_SAADC_STATE_IDLE; - } - else - { - uint32_t limit_flags = m_cb.limits_enabled_flags; - uint32_t flag_idx; - nrf_saadc_event_t event; - - while (limit_flags) - { - flag_idx = __CLZ(limit_flags); - limit_flags &= ~((1UL << 31) >> flag_idx); - event = FLAG_IDX_TO_EVENT(flag_idx); - if (nrf_saadc_event_check(event)) - { - nrf_saadc_event_clear(event); - nrfx_saadc_evt_t evt; - evt.type = NRFX_SAADC_EVT_LIMIT; - evt.data.limit.channel = LIMIT_EVENT_TO_CHANNEL(event); - evt.data.limit.limit_type = LIMIT_EVENT_TO_LIMIT_TYPE(event); - NRFX_LOG_DEBUG("Event limit, channel: %d, limit type: %d.", - evt.data.limit.channel, - evt.data.limit.limit_type); - m_cb.event_handler(&evt); - } - } - } -} - - -nrfx_err_t nrfx_saadc_init(nrfx_saadc_config_t const * p_config, - nrfx_saadc_event_handler_t event_handler) -{ - NRFX_ASSERT(p_config); - NRFX_ASSERT(event_handler); - nrfx_err_t err_code; - - if (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED) - { - err_code = NRFX_ERROR_INVALID_STATE; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - m_cb.event_handler = event_handler; - nrf_saadc_resolution_set(p_config->resolution); - nrf_saadc_oversample_set(p_config->oversample); - m_cb.low_power_mode = p_config->low_power_mode; - m_cb.state = NRFX_DRV_STATE_INITIALIZED; - m_cb.adc_state = NRF_SAADC_STATE_IDLE; - m_cb.active_channels = 0; - m_cb.limits_enabled_flags = 0; - m_cb.conversions_end = false; - - nrf_saadc_int_disable(NRF_SAADC_INT_ALL); - nrf_saadc_event_clear(NRF_SAADC_EVENT_END); - nrf_saadc_event_clear(NRF_SAADC_EVENT_STARTED); - NRFX_IRQ_PRIORITY_SET(SAADC_IRQn, p_config->interrupt_priority); - NRFX_IRQ_ENABLE(SAADC_IRQn); - nrf_saadc_int_enable(NRF_SAADC_INT_END); - - if (m_cb.low_power_mode) - { - nrf_saadc_int_enable(NRF_SAADC_INT_STARTED); - } - - nrf_saadc_enable(); - - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - - return err_code; -} - - -void nrfx_saadc_uninit(void) -{ - NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); - - nrf_saadc_int_disable(NRF_SAADC_INT_ALL); - NRFX_IRQ_DISABLE(SAADC_IRQn); - nrf_saadc_task_trigger(NRF_SAADC_TASK_STOP); - - // Wait for ADC being stopped. - bool result; - NRFX_WAIT_FOR(nrf_saadc_event_check(NRF_SAADC_EVENT_STOPPED), HW_TIMEOUT, 0, result); - NRFX_ASSERT(result); - - nrf_saadc_disable(); - m_cb.adc_state = NRF_SAADC_STATE_IDLE; - - for (uint32_t channel = 0; channel < NRF_SAADC_CHANNEL_COUNT; ++channel) - { - if (m_cb.psel[channel].pselp != NRF_SAADC_INPUT_DISABLED) - { - nrfx_err_t err_code = nrfx_saadc_channel_uninit(channel); - NRFX_ASSERT(err_code == NRFX_SUCCESS); - } - } - - m_cb.state = NRFX_DRV_STATE_UNINITIALIZED; -} - - -nrfx_err_t nrfx_saadc_channel_init(uint8_t channel, - nrf_saadc_channel_config_t const * const p_config) -{ - NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); - NRFX_ASSERT(channel < NRF_SAADC_CHANNEL_COUNT); - // Oversampling can be used only with one channel. - NRFX_ASSERT((nrf_saadc_oversample_get() == NRF_SAADC_OVERSAMPLE_DISABLED) || - (m_cb.active_channels == 0)); - NRFX_ASSERT((p_config->pin_p <= NRF_SAADC_INPUT_VDD) && - (p_config->pin_p > NRF_SAADC_INPUT_DISABLED)); - NRFX_ASSERT(p_config->pin_n <= NRF_SAADC_INPUT_VDD); - - nrfx_err_t err_code; - - // A channel can only be initialized if the driver is in the idle state. - if (m_cb.adc_state != NRF_SAADC_STATE_IDLE) - { - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - -#ifdef NRF52_PAN_74 - if ((p_config->acq_time == NRF_SAADC_ACQTIME_3US) || - (p_config->acq_time == NRF_SAADC_ACQTIME_5US)) - { - nrf_saadc_disable(); - } -#endif //NRF52_PAN_74 - - if (m_cb.psel[channel].pselp == NRF_SAADC_INPUT_DISABLED) - { - ++m_cb.active_channels; - } - m_cb.psel[channel].pselp = p_config->pin_p; - m_cb.psel[channel].pseln = p_config->pin_n; - nrf_saadc_channel_init(channel, p_config); - nrf_saadc_channel_input_set(channel, p_config->pin_p, p_config->pin_n); - -#ifdef NRF52_PAN_74 - if ((p_config->acq_time == NRF_SAADC_ACQTIME_3US) || - (p_config->acq_time == NRF_SAADC_ACQTIME_5US)) - { - nrf_saadc_enable(); - } -#endif //NRF52_PAN_74 - - NRFX_LOG_INFO("Channel initialized: %d.", channel); - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - - -nrfx_err_t nrfx_saadc_channel_uninit(uint8_t channel) -{ - NRFX_ASSERT(channel < NRF_SAADC_CHANNEL_COUNT); - NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); - - nrfx_err_t err_code; - - // A channel can only be uninitialized if the driver is in the idle state. - if (m_cb.adc_state != NRF_SAADC_STATE_IDLE) - { - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - if (m_cb.psel[channel].pselp != NRF_SAADC_INPUT_DISABLED) - { - --m_cb.active_channels; - } - m_cb.psel[channel].pselp = NRF_SAADC_INPUT_DISABLED; - m_cb.psel[channel].pseln = NRF_SAADC_INPUT_DISABLED; - nrf_saadc_channel_input_set(channel, NRF_SAADC_INPUT_DISABLED, NRF_SAADC_INPUT_DISABLED); - nrfx_saadc_limits_set(channel, NRFX_SAADC_LIMITL_DISABLED, NRFX_SAADC_LIMITH_DISABLED); - NRFX_LOG_INFO("Channel denitialized: %d.", channel); - - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - - -uint32_t nrfx_saadc_sample_task_get(void) -{ - return nrf_saadc_task_address_get( - m_cb.low_power_mode ? NRF_SAADC_TASK_START : NRF_SAADC_TASK_SAMPLE); -} - - -nrfx_err_t nrfx_saadc_sample_convert(uint8_t channel, nrf_saadc_value_t * p_value) -{ - nrfx_err_t err_code; - - if (m_cb.adc_state != NRF_SAADC_STATE_IDLE) - { - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - m_cb.adc_state = NRF_SAADC_STATE_BUSY; - nrf_saadc_int_disable(NRF_SAADC_INT_STARTED | NRF_SAADC_INT_END); - nrf_saadc_buffer_init(p_value, 1); - if (m_cb.active_channels > 1) - { - for (uint32_t i = 0; i < NRF_SAADC_CHANNEL_COUNT; ++i) - { - nrf_saadc_channel_input_set(i, NRF_SAADC_INPUT_DISABLED, NRF_SAADC_INPUT_DISABLED); - } - } - nrf_saadc_channel_input_set(channel, m_cb.psel[channel].pselp, m_cb.psel[channel].pseln); - nrf_saadc_task_trigger(NRF_SAADC_TASK_START); - nrf_saadc_task_trigger(NRF_SAADC_TASK_SAMPLE); - - bool result; - NRFX_WAIT_FOR(nrf_saadc_event_check(NRF_SAADC_EVENT_END), HW_TIMEOUT, 0, result); - NRFX_ASSERT(result); - - nrf_saadc_event_clear(NRF_SAADC_EVENT_STARTED); - nrf_saadc_event_clear(NRF_SAADC_EVENT_END); - - NRFX_LOG_INFO("Conversion value: %d, channel %d.", *p_value, channel); - - if (m_cb.active_channels > 1) - { - for (uint32_t i = 0; i < NRF_SAADC_CHANNEL_COUNT; ++i) - { - nrf_saadc_channel_input_set(i, m_cb.psel[i].pselp, m_cb.psel[i].pseln); - } - } - - if (m_cb.low_power_mode) - { - nrf_saadc_int_enable(NRF_SAADC_INT_STARTED | NRF_SAADC_INT_END); - } - else - { - nrf_saadc_int_enable(NRF_SAADC_INT_END); - } - - m_cb.adc_state = NRF_SAADC_STATE_IDLE; - - err_code = NRFX_SUCCESS; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - - -nrfx_err_t nrfx_saadc_buffer_convert(nrf_saadc_value_t * p_buffer, uint16_t size) -{ - NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); - NRFX_ASSERT((size % m_cb.active_channels) == 0); - nrfx_err_t err_code; - - nrf_saadc_int_disable(NRF_SAADC_INT_END | NRF_SAADC_INT_CALIBRATEDONE); - if (m_cb.adc_state == NRF_SAADC_STATE_CALIBRATION) - { - nrf_saadc_int_enable(NRF_SAADC_INT_END | NRF_SAADC_INT_CALIBRATEDONE); - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - if (m_cb.adc_state == NRF_SAADC_STATE_BUSY) - { - if ( m_cb.p_secondary_buffer) - { - nrf_saadc_int_enable(NRF_SAADC_INT_END); - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - else - { - m_cb.p_secondary_buffer = p_buffer; - m_cb.secondary_buffer_size = size; - if (!m_cb.low_power_mode) - { - while (nrf_saadc_event_check(NRF_SAADC_EVENT_STARTED) == 0); - nrf_saadc_event_clear(NRF_SAADC_EVENT_STARTED); - nrf_saadc_buffer_init(p_buffer, size); - } - nrf_saadc_int_enable(NRF_SAADC_INT_END); - err_code = NRFX_SUCCESS; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - } - nrf_saadc_int_enable(NRF_SAADC_INT_END); - m_cb.adc_state = NRF_SAADC_STATE_BUSY; - - m_cb.p_buffer = p_buffer; - m_cb.buffer_size = size; - m_cb.p_secondary_buffer = NULL; - - NRFX_LOG_INFO("Function: %s, buffer length: %d, active channels: %d.", - __func__, - size, - m_cb.active_channels); - - if (m_cb.low_power_mode) - { - m_cb.buffer_size_left = size; - nrf_saadc_buffer_init(p_buffer, m_cb.active_channels); - } - else - { - nrf_saadc_buffer_init(p_buffer, size); - nrf_saadc_event_clear(NRF_SAADC_EVENT_STARTED); - nrf_saadc_task_trigger(NRF_SAADC_TASK_START); - } - - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - - -nrfx_err_t nrfx_saadc_sample() -{ - NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); - - nrfx_err_t err_code = NRFX_SUCCESS; - if (m_cb.adc_state != NRF_SAADC_STATE_BUSY) - { - err_code = NRFX_ERROR_INVALID_STATE; - } - else if (m_cb.low_power_mode) - { - nrf_saadc_task_trigger(NRF_SAADC_TASK_START); - } - else - { - nrf_saadc_task_trigger(NRF_SAADC_TASK_SAMPLE); - } - - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - - -nrfx_err_t nrfx_saadc_calibrate_offset() -{ - NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); - - nrfx_err_t err_code; - - if (m_cb.adc_state != NRF_SAADC_STATE_IDLE) - { - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - m_cb.adc_state = NRF_SAADC_STATE_CALIBRATION; - - nrf_saadc_event_clear(NRF_SAADC_EVENT_CALIBRATEDONE); - nrf_saadc_int_enable(NRF_SAADC_INT_CALIBRATEDONE); - nrf_saadc_task_trigger(NRF_SAADC_TASK_CALIBRATEOFFSET); - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - - -bool nrfx_saadc_is_busy(void) -{ - return (m_cb.adc_state != NRF_SAADC_STATE_IDLE); -} - - -void nrfx_saadc_abort(void) -{ - if (nrfx_saadc_is_busy()) - { - nrf_saadc_event_clear(NRF_SAADC_EVENT_STOPPED); - nrf_saadc_int_enable(NRF_SAADC_INT_STOPPED); - nrf_saadc_task_trigger(NRF_SAADC_TASK_STOP); - - if (m_cb.adc_state == NRF_SAADC_STATE_CALIBRATION) - { - m_cb.adc_state = NRF_SAADC_STATE_IDLE; - } - else - { - // Wait for ADC being stopped. - bool result; - NRFX_WAIT_FOR((m_cb.adc_state != NRF_SAADC_STATE_IDLE), HW_TIMEOUT, 0, result); - NRFX_ASSERT(result); - } - - nrf_saadc_int_disable(NRF_SAADC_INT_STOPPED); - - m_cb.p_buffer = 0; - m_cb.p_secondary_buffer = 0; - NRFX_LOG_INFO("Conversion aborted."); - } -} - - -void nrfx_saadc_limits_set(uint8_t channel, int16_t limit_low, int16_t limit_high) -{ - NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); - NRFX_ASSERT(m_cb.event_handler); // only non blocking mode supported - NRFX_ASSERT(limit_low >= NRFX_SAADC_LIMITL_DISABLED); - NRFX_ASSERT(limit_high <= NRFX_SAADC_LIMITH_DISABLED); - NRFX_ASSERT(limit_low < limit_high); - nrf_saadc_channel_limits_set(channel, limit_low, limit_high); - - uint32_t int_mask = nrf_saadc_limit_int_get(channel, NRF_SAADC_LIMIT_LOW); - if (limit_low == NRFX_SAADC_LIMITL_DISABLED) - { - m_cb.limits_enabled_flags &= ~(0x80000000 >> LOW_LIMIT_TO_FLAG(channel)); - nrf_saadc_int_disable(int_mask); - } - else - { - m_cb.limits_enabled_flags |= (0x80000000 >> LOW_LIMIT_TO_FLAG(channel)); - nrf_saadc_int_enable(int_mask); - } - - int_mask = nrf_saadc_limit_int_get(channel, NRF_SAADC_LIMIT_HIGH); - if (limit_high == NRFX_SAADC_LIMITH_DISABLED) - { - m_cb.limits_enabled_flags &= ~(0x80000000 >> HIGH_LIMIT_TO_FLAG(channel)); - nrf_saadc_int_disable(int_mask); - } - else - { - m_cb.limits_enabled_flags |= (0x80000000 >> HIGH_LIMIT_TO_FLAG(channel)); - nrf_saadc_int_enable(int_mask); - } -} -#endif // NRFX_CHECK(NRFX_SAADC_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_spi.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_spi.c deleted file mode 100644 index f811760945..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_spi.c +++ /dev/null @@ -1,441 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include - -#if NRFX_CHECK(NRFX_SPI_ENABLED) - -#if !(NRFX_CHECK(NRFX_SPI0_ENABLED) || NRFX_CHECK(NRFX_SPI1_ENABLED) || \ - NRFX_CHECK(NRFX_SPI2_ENABLED)) -#error "No enabled SPI instances. Check ." -#endif - -#include -#include "prs/nrfx_prs.h" -#include - -#define NRFX_LOG_MODULE SPI -#include - -// Control block - driver instance local data. -typedef struct -{ - nrfx_spi_evt_handler_t handler; - void * p_context; - nrfx_spi_evt_t evt; // Keep the struct that is ready for event handler. Less memcpy. - nrfx_drv_state_t state; - volatile bool transfer_in_progress; - - // [no need for 'volatile' attribute for the following members, as they - // are not concurrently used in IRQ handlers and main line code] - uint8_t ss_pin; - uint8_t miso_pin; - uint8_t orc; - size_t bytes_transferred; - - bool abort; -} spi_control_block_t; -static spi_control_block_t m_cb[NRFX_SPI_ENABLED_COUNT]; - - -nrfx_err_t nrfx_spi_init(nrfx_spi_t const * const p_instance, - nrfx_spi_config_t const * p_config, - nrfx_spi_evt_handler_t handler, - void * p_context) -{ - NRFX_ASSERT(p_config); - spi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - nrfx_err_t err_code; - - if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED) - { - err_code = NRFX_ERROR_INVALID_STATE; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - -#if NRFX_CHECK(NRFX_PRS_ENABLED) - static nrfx_irq_handler_t const irq_handlers[NRFX_SPI_ENABLED_COUNT] = { - #if NRFX_CHECK(NRFX_SPI0_ENABLED) - nrfx_spi_0_irq_handler, - #endif - #if NRFX_CHECK(NRFX_SPI1_ENABLED) - nrfx_spi_1_irq_handler, - #endif - #if NRFX_CHECK(NRFX_SPI2_ENABLED) - nrfx_spi_2_irq_handler, - #endif - }; - if (nrfx_prs_acquire(p_instance->p_reg, - irq_handlers[p_instance->drv_inst_idx]) != NRFX_SUCCESS) - { - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } -#endif // NRFX_CHECK(NRFX_PRS_ENABLED) - - p_cb->handler = handler; - p_cb->p_context = p_context; - - uint32_t mosi_pin; - uint32_t miso_pin; - // Configure pins used by the peripheral: - // - SCK - output with initial value corresponding with the SPI mode used: - // 0 - for modes 0 and 1 (CPOL = 0), 1 - for modes 2 and 3 (CPOL = 1); - // according to the reference manual guidelines this pin and its input - // buffer must always be connected for the SPI to work. - if (p_config->mode <= NRF_SPI_MODE_1) - { - nrf_gpio_pin_clear(p_config->sck_pin); - } - else - { - nrf_gpio_pin_set(p_config->sck_pin); - } - nrf_gpio_cfg(p_config->sck_pin, - NRF_GPIO_PIN_DIR_OUTPUT, - NRF_GPIO_PIN_INPUT_CONNECT, - NRF_GPIO_PIN_NOPULL, - NRF_GPIO_PIN_S0S1, - NRF_GPIO_PIN_NOSENSE); - // - MOSI (optional) - output with initial value 0, - if (p_config->mosi_pin != NRFX_SPI_PIN_NOT_USED) - { - mosi_pin = p_config->mosi_pin; - nrf_gpio_pin_clear(mosi_pin); - nrf_gpio_cfg_output(mosi_pin); - } - else - { - mosi_pin = NRF_SPI_PIN_NOT_CONNECTED; - } - // - MISO (optional) - input, - if (p_config->miso_pin != NRFX_SPI_PIN_NOT_USED) - { - miso_pin = p_config->miso_pin; - nrf_gpio_cfg_input(miso_pin, (nrf_gpio_pin_pull_t)NRFX_SPI_MISO_PULL_CFG); - } - else - { - miso_pin = NRF_SPI_PIN_NOT_CONNECTED; - } - m_cb[p_instance->drv_inst_idx].miso_pin = p_config->miso_pin; - // - Slave Select (optional) - output with initial value 1 (inactive). - if (p_config->ss_pin != NRFX_SPI_PIN_NOT_USED) - { - nrf_gpio_pin_set(p_config->ss_pin); - nrf_gpio_cfg_output(p_config->ss_pin); - } - m_cb[p_instance->drv_inst_idx].ss_pin = p_config->ss_pin; - - NRF_SPI_Type * p_spi = p_instance->p_reg; - nrf_spi_pins_set(p_spi, p_config->sck_pin, mosi_pin, miso_pin); - nrf_spi_frequency_set(p_spi, p_config->frequency); - nrf_spi_configure(p_spi, p_config->mode, p_config->bit_order); - - m_cb[p_instance->drv_inst_idx].orc = p_config->orc; - - if (p_cb->handler) - { - nrf_spi_int_enable(p_spi, NRF_SPI_INT_READY_MASK); - } - - nrf_spi_enable(p_spi); - - if (p_cb->handler) - { - NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_instance->p_reg), - p_config->irq_priority); - NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_instance->p_reg)); - } - - p_cb->transfer_in_progress = false; - p_cb->state = NRFX_DRV_STATE_INITIALIZED; - - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -void nrfx_spi_uninit(nrfx_spi_t const * const p_instance) -{ - spi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); - - if (p_cb->handler) - { - NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_instance->p_reg)); - } - - NRF_SPI_Type * p_spi = p_instance->p_reg; - if (p_cb->handler) - { - nrf_spi_int_disable(p_spi, NRF_SPI_ALL_INTS_MASK); - } - - if (p_cb->miso_pin != NRFX_SPI_PIN_NOT_USED) - { - nrf_gpio_cfg_default(p_cb->miso_pin); - } - nrf_spi_disable(p_spi); - -#if NRFX_CHECK(NRFX_PRS_ENABLED) - nrfx_prs_release(p_instance->p_reg); -#endif - - p_cb->state = NRFX_DRV_STATE_UNINITIALIZED; -} - -static void finish_transfer(spi_control_block_t * p_cb) -{ - // If Slave Select signal is used, this is the time to deactivate it. - if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED) - { - nrf_gpio_pin_set(p_cb->ss_pin); - } - - // By clearing this flag before calling the handler we allow subsequent - // transfers to be started directly from the handler function. - p_cb->transfer_in_progress = false; - - p_cb->evt.type = NRFX_SPI_EVENT_DONE; - p_cb->handler(&p_cb->evt, p_cb->p_context); -} - -// This function is called from the IRQ handler or, in blocking mode, directly -// from the 'spi_xfer' function. -// It returns true as long as the transfer should be continued, otherwise (when -// there is nothing more to send/receive) it returns false. -static bool transfer_byte(NRF_SPI_Type * p_spi, spi_control_block_t * p_cb) -{ - // Read the data byte received in this transfer (always, because no further - // READY event can be generated until the current byte is read out from the - // RXD register), and store it in the RX buffer (only when needed). - volatile uint8_t rx_data = nrf_spi_rxd_get(p_spi); - if (p_cb->bytes_transferred < p_cb->evt.xfer_desc.rx_length) - { - p_cb->evt.xfer_desc.p_rx_buffer[p_cb->bytes_transferred] = rx_data; - } - - ++p_cb->bytes_transferred; - - // Check if there are more bytes to send or receive and write proper data - // byte (next one from TX buffer or over-run character) to the TXD register - // when needed. - // NOTE - we've already used 'p_cb->bytes_transferred + 1' bytes from our - // buffers, because we take advantage of double buffering of TXD - // register (so in effect one byte is still being transmitted now); - // see how the transfer is started in the 'spi_xfer' function. - size_t bytes_used = p_cb->bytes_transferred + 1; - - if (p_cb->abort) - { - if (bytes_used < p_cb->evt.xfer_desc.tx_length) - { - p_cb->evt.xfer_desc.tx_length = bytes_used; - } - if (bytes_used < p_cb->evt.xfer_desc.rx_length) - { - p_cb->evt.xfer_desc.rx_length = bytes_used; - } - } - - if (bytes_used < p_cb->evt.xfer_desc.tx_length) - { - nrf_spi_txd_set(p_spi, p_cb->evt.xfer_desc.p_tx_buffer[bytes_used]); - return true; - } - else if (bytes_used < p_cb->evt.xfer_desc.rx_length) - { - nrf_spi_txd_set(p_spi, p_cb->orc); - return true; - } - - return (p_cb->bytes_transferred < p_cb->evt.xfer_desc.tx_length || - p_cb->bytes_transferred < p_cb->evt.xfer_desc.rx_length); -} - -static void spi_xfer(NRF_SPI_Type * p_spi, - spi_control_block_t * p_cb, - nrfx_spi_xfer_desc_t const * p_xfer_desc) -{ - p_cb->bytes_transferred = 0; - nrf_spi_int_disable(p_spi, NRF_SPI_INT_READY_MASK); - - nrf_spi_event_clear(p_spi, NRF_SPI_EVENT_READY); - - // Start the transfer by writing some byte to the TXD register; - // if TX buffer is not empty, take the first byte from this buffer, - // otherwise - use over-run character. - nrf_spi_txd_set(p_spi, - (p_xfer_desc->tx_length > 0 ? p_xfer_desc->p_tx_buffer[0] : p_cb->orc)); - - // TXD register is double buffered, so next byte to be transmitted can - // be written immediately, if needed, i.e. if TX or RX transfer is to - // be more that 1 byte long. Again - if there is something more in TX - // buffer send it, otherwise use over-run character. - if (p_xfer_desc->tx_length > 1) - { - nrf_spi_txd_set(p_spi, p_xfer_desc->p_tx_buffer[1]); - } - else if (p_xfer_desc->rx_length > 1) - { - nrf_spi_txd_set(p_spi, p_cb->orc); - } - - // For blocking mode (user handler not provided) wait here for READY - // events (indicating that the byte from TXD register was transmitted - // and a new incoming byte was moved to the RXD register) and continue - // transaction until all requested bytes are transferred. - // In non-blocking mode - IRQ service routine will do this stuff. - if (p_cb->handler) - { - nrf_spi_int_enable(p_spi, NRF_SPI_INT_READY_MASK); - } - else - { - do { - while (!nrf_spi_event_check(p_spi, NRF_SPI_EVENT_READY)) {} - nrf_spi_event_clear(p_spi, NRF_SPI_EVENT_READY); - NRFX_LOG_DEBUG("SPI: Event: NRF_SPI_EVENT_READY."); - } while (transfer_byte(p_spi, p_cb)); - if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED) - { - nrf_gpio_pin_set(p_cb->ss_pin); - } - } -} - -nrfx_err_t nrfx_spi_xfer(nrfx_spi_t const * const p_instance, - nrfx_spi_xfer_desc_t const * p_xfer_desc, - uint32_t flags) -{ - spi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); - NRFX_ASSERT(p_xfer_desc->p_tx_buffer != NULL || p_xfer_desc->tx_length == 0); - NRFX_ASSERT(p_xfer_desc->p_rx_buffer != NULL || p_xfer_desc->rx_length == 0); - - nrfx_err_t err_code = NRFX_SUCCESS; - - if (p_cb->transfer_in_progress) - { - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - else - { - if (p_cb->handler) - { - p_cb->transfer_in_progress = true; - } - } - - p_cb->evt.xfer_desc = *p_xfer_desc; - p_cb->abort = false; - - if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED) - { - nrf_gpio_pin_clear(p_cb->ss_pin); - } - if (flags) - { - p_cb->transfer_in_progress = false; - err_code = NRFX_ERROR_NOT_SUPPORTED; - } - else - { - spi_xfer(p_instance->p_reg, p_cb, p_xfer_desc); - } - NRFX_LOG_INFO("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -void nrfx_spi_abort(nrfx_spi_t const * p_instance) -{ - spi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); - p_cb->abort = true; -} - -static void irq_handler(NRF_SPI_Type * p_spi, spi_control_block_t * p_cb) -{ - NRFX_ASSERT(p_cb->handler); - - nrf_spi_event_clear(p_spi, NRF_SPI_EVENT_READY); - NRFX_LOG_DEBUG("Event: NRF_SPI_EVENT_READY."); - - if (!transfer_byte(p_spi, p_cb)) - { - finish_transfer(p_cb); - } -} - -#if NRFX_CHECK(NRFX_SPI0_ENABLED) -void nrfx_spi_0_irq_handler(void) -{ - irq_handler(NRF_SPI0, &m_cb[NRFX_SPI0_INST_IDX]); -} -#endif - -#if NRFX_CHECK(NRFX_SPI1_ENABLED) -void nrfx_spi_1_irq_handler(void) -{ - irq_handler(NRF_SPI1, &m_cb[NRFX_SPI1_INST_IDX]); -} -#endif - -#if NRFX_CHECK(NRFX_SPI2_ENABLED) -void nrfx_spi_2_irq_handler(void) -{ - irq_handler(NRF_SPI2, &m_cb[NRFX_SPI2_INST_IDX]); -} -#endif - -#endif // NRFX_CHECK(NRFX_SPI_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_spim.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_spim.c deleted file mode 100644 index 7d7ff4ab68..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_spim.c +++ /dev/null @@ -1,688 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include - -#if NRFX_CHECK(NRFX_SPIM_ENABLED) - -#if !(NRFX_CHECK(NRFX_SPIM0_ENABLED) || NRFX_CHECK(NRFX_SPIM1_ENABLED) || \ - NRFX_CHECK(NRFX_SPIM2_ENABLED) || NRFX_CHECK(NRFX_SPIM3_ENABLED)) -#error "No enabled SPIM instances. Check ." -#endif - -#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) && !NRFX_CHECK(NRFX_SPIM3_ENABLED) -#error "Extended options are available only in SPIM3 on the nRF52840 SoC." -#endif - -#include -#include "prs/nrfx_prs.h" -#include - -#define NRFX_LOG_MODULE SPIM -#include - -#define SPIMX_LENGTH_VALIDATE(peripheral, drv_inst_idx, rx_len, tx_len) \ - (((drv_inst_idx) == NRFX_CONCAT_3(NRFX_, peripheral, _INST_IDX)) && \ - NRFX_EASYDMA_LENGTH_VALIDATE(peripheral, rx_len, tx_len)) - -#if NRFX_CHECK(NRFX_SPIM0_ENABLED) -#define SPIM0_LENGTH_VALIDATE(...) SPIMX_LENGTH_VALIDATE(SPIM0, __VA_ARGS__) -#else -#define SPIM0_LENGTH_VALIDATE(...) 0 -#endif - -#if NRFX_CHECK(NRFX_SPIM1_ENABLED) -#define SPIM1_LENGTH_VALIDATE(...) SPIMX_LENGTH_VALIDATE(SPIM1, __VA_ARGS__) -#else -#define SPIM1_LENGTH_VALIDATE(...) 0 -#endif - -#if NRFX_CHECK(NRFX_SPIM2_ENABLED) -#define SPIM2_LENGTH_VALIDATE(...) SPIMX_LENGTH_VALIDATE(SPIM2, __VA_ARGS__) -#else -#define SPIM2_LENGTH_VALIDATE(...) 0 -#endif - -#if NRFX_CHECK(NRFX_SPIM3_ENABLED) -#define SPIM3_LENGTH_VALIDATE(...) SPIMX_LENGTH_VALIDATE(SPIM3, __VA_ARGS__) -#else -#define SPIM3_LENGTH_VALIDATE(...) 0 -#endif - -#define SPIM_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len) \ - (SPIM0_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len) || \ - SPIM1_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len) || \ - SPIM2_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len) || \ - SPIM3_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len)) - - -// Control block - driver instance local data. -typedef struct -{ - nrfx_spim_evt_handler_t handler; - void * p_context; - nrfx_spim_evt_t evt; // Keep the struct that is ready for event handler. Less memcpy. - nrfx_drv_state_t state; - volatile bool transfer_in_progress; - -#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) - bool use_hw_ss; -#endif - - // [no need for 'volatile' attribute for the following members, as they - // are not concurrently used in IRQ handlers and main line code] - bool ss_active_high; - uint8_t ss_pin; - uint8_t miso_pin; - uint8_t orc; - -#if NRFX_CHECK(NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED) - size_t tx_length; - size_t rx_length; -#endif -} spim_control_block_t; -static spim_control_block_t m_cb[NRFX_SPIM_ENABLED_COUNT]; - -#if NRFX_CHECK(NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED) - -// Workaround for nRF52840 anomaly 198: SPIM3 transmit data might be corrupted. - -static uint32_t m_anomaly_198_preserved_value; - -static void anomaly_198_enable(uint8_t const * p_buffer, size_t buf_len) -{ - m_anomaly_198_preserved_value = *((volatile uint32_t *)0x40000E00); - - if (buf_len == 0) - { - return; - } - uint32_t buffer_end_addr = ((uint32_t)p_buffer) + buf_len; - uint32_t block_addr = ((uint32_t)p_buffer) & ~0x1FFF; - uint32_t block_flag = (1UL << ((block_addr >> 13) & 0xFFFF)); - uint32_t occupied_blocks = 0; - - if (block_addr >= 0x20010000) - { - occupied_blocks = (1UL << 8); - } - else - { - do { - occupied_blocks |= block_flag; - block_flag <<= 1; - block_addr += 0x2000; - } while ((block_addr < buffer_end_addr) && (block_addr < 0x20012000)); - } - - *((volatile uint32_t *)0x40000E00) = occupied_blocks; -} - -static void anomaly_198_disable(void) -{ - *((volatile uint32_t *)0x40000E00) = m_anomaly_198_preserved_value; -} -#endif // NRFX_CHECK(NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED) - -nrfx_err_t nrfx_spim_init(nrfx_spim_t const * const p_instance, - nrfx_spim_config_t const * p_config, - nrfx_spim_evt_handler_t handler, - void * p_context) -{ - NRFX_ASSERT(p_config); - spim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - nrfx_err_t err_code; - - if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED) - { - err_code = NRFX_ERROR_INVALID_STATE; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - -#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) - - // Currently, only SPIM3 in nRF52840 supports the extended features. Other instances must be checked. - if ((p_instance->drv_inst_idx != NRFX_SPIM3_INST_IDX) && - ((p_config->dcx_pin != NRFX_SPIM_PIN_NOT_USED) || - (p_config->frequency == NRF_SPIM_FREQ_16M) || - (p_config->frequency == NRF_SPIM_FREQ_32M) || - (p_config->rx_delay != 0x00) || - (p_config->use_hw_ss))) - { - err_code = NRFX_ERROR_NOT_SUPPORTED; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } -#endif - - NRF_SPIM_Type * p_spim = (NRF_SPIM_Type *)p_instance->p_reg; - -#if NRFX_CHECK(NRFX_PRS_ENABLED) - static nrfx_irq_handler_t const irq_handlers[NRFX_SPIM_ENABLED_COUNT] = { - #if NRFX_CHECK(NRFX_SPIM0_ENABLED) - nrfx_spim_0_irq_handler, - #endif - #if NRFX_CHECK(NRFX_SPIM1_ENABLED) - nrfx_spim_1_irq_handler, - #endif - #if NRFX_CHECK(NRFX_SPIM2_ENABLED) - nrfx_spim_2_irq_handler, - #endif - #if NRFX_CHECK(NRFX_SPIM3_ENABLED) - nrfx_spim_3_irq_handler, - #endif - }; - if (nrfx_prs_acquire(p_instance->p_reg, - irq_handlers[p_instance->drv_inst_idx]) != NRFX_SUCCESS) - { - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } -#endif // NRFX_CHECK(NRFX_PRS_ENABLED) - - p_cb->handler = handler; - p_cb->p_context = p_context; - - uint32_t mosi_pin; - uint32_t miso_pin; - // Configure pins used by the peripheral: - // - SCK - output with initial value corresponding with the SPI mode used: - // 0 - for modes 0 and 1 (CPOL = 0), 1 - for modes 2 and 3 (CPOL = 1); - // according to the reference manual guidelines this pin and its input - // buffer must always be connected for the SPI to work. - if (p_config->mode <= NRF_SPIM_MODE_1) - { - nrf_gpio_pin_clear(p_config->sck_pin); - } - else - { - nrf_gpio_pin_set(p_config->sck_pin); - } - nrf_gpio_cfg(p_config->sck_pin, - NRF_GPIO_PIN_DIR_OUTPUT, - NRF_GPIO_PIN_INPUT_CONNECT, - NRF_GPIO_PIN_NOPULL, - NRF_GPIO_PIN_S0S1, - NRF_GPIO_PIN_NOSENSE); - // - MOSI (optional) - output with initial value 0, - if (p_config->mosi_pin != NRFX_SPIM_PIN_NOT_USED) - { - mosi_pin = p_config->mosi_pin; - nrf_gpio_pin_clear(mosi_pin); - nrf_gpio_cfg_output(mosi_pin); - } - else - { - mosi_pin = NRF_SPIM_PIN_NOT_CONNECTED; - } - // - MISO (optional) - input, - if (p_config->miso_pin != NRFX_SPIM_PIN_NOT_USED) - { - miso_pin = p_config->miso_pin; - nrf_gpio_cfg_input(miso_pin, (nrf_gpio_pin_pull_t)NRFX_SPIM_MISO_PULL_CFG); - } - else - { - miso_pin = NRF_SPIM_PIN_NOT_CONNECTED; - } - m_cb[p_instance->drv_inst_idx].miso_pin = p_config->miso_pin; - // - Slave Select (optional) - output with initial value 1 (inactive). - if (p_config->ss_pin != NRFX_SPIM_PIN_NOT_USED) - { - if (p_config->ss_active_high) - { - nrf_gpio_pin_clear(p_config->ss_pin); - } - else - { - nrf_gpio_pin_set(p_config->ss_pin); - } - nrf_gpio_cfg_output(p_config->ss_pin); -#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) - if (p_config->use_hw_ss) - { - m_cb[p_instance->drv_inst_idx].use_hw_ss = p_config->use_hw_ss; - nrf_spim_csn_configure(p_spim, - p_config->ss_pin, - (p_config->ss_active_high == true ? - NRF_SPIM_CSN_POL_HIGH : NRF_SPIM_CSN_POL_LOW), - p_config->ss_duration); - } -#endif - m_cb[p_instance->drv_inst_idx].ss_pin = p_config->ss_pin; - m_cb[p_instance->drv_inst_idx].ss_active_high = p_config->ss_active_high; - } - -#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) - // - DCX (optional) - output. - if (p_config->dcx_pin != NRFX_SPIM_PIN_NOT_USED) - { - nrf_gpio_pin_set(p_config->dcx_pin); - nrf_gpio_cfg_output(p_config->dcx_pin); - nrf_spim_dcx_pin_set(p_spim, p_config->dcx_pin); - } - - // Change rx delay - nrf_spim_iftiming_set(p_spim, p_config->rx_delay); -#endif - - - nrf_spim_pins_set(p_spim, p_config->sck_pin, mosi_pin, miso_pin); - nrf_spim_frequency_set(p_spim, p_config->frequency); - nrf_spim_configure(p_spim, p_config->mode, p_config->bit_order); - - nrf_spim_orc_set(p_spim, p_config->orc); - - if (p_cb->handler) - { - nrf_spim_int_enable(p_spim, NRF_SPIM_INT_END_MASK); - } - - nrf_spim_enable(p_spim); - - if (p_cb->handler) - { - NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_instance->p_reg), - p_config->irq_priority); - NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_instance->p_reg)); - } - - p_cb->transfer_in_progress = false; - p_cb->state = NRFX_DRV_STATE_INITIALIZED; - - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -void nrfx_spim_uninit(nrfx_spim_t const * const p_instance) -{ - spim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); - - if (p_cb->handler) - { - NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_instance->p_reg)); - } - - NRF_SPIM_Type * p_spim = (NRF_SPIM_Type *)p_instance->p_reg; - if (p_cb->handler) - { - nrf_spim_int_disable(p_spim, NRF_SPIM_ALL_INTS_MASK); - if (p_cb->transfer_in_progress) - { - // Ensure that SPI is not performing any transfer. - nrf_spim_task_trigger(p_spim, NRF_SPIM_TASK_STOP); - while (!nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_STOPPED)) - {} - p_cb->transfer_in_progress = false; - } - } - - if (p_cb->miso_pin != NRFX_SPIM_PIN_NOT_USED) - { - nrf_gpio_cfg_default(p_cb->miso_pin); - } - nrf_spim_disable(p_spim); - -#if NRFX_CHECK(NRFX_PRS_ENABLED) - nrfx_prs_release(p_instance->p_reg); -#endif - - p_cb->state = NRFX_DRV_STATE_UNINITIALIZED; -} - -#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) -nrfx_err_t nrfx_spim_xfer_dcx(nrfx_spim_t const * const p_instance, - nrfx_spim_xfer_desc_t const * p_xfer_desc, - uint32_t flags, - uint8_t cmd_length) -{ - NRFX_ASSERT(cmd_length <= NRF_SPIM_DCX_CNT_ALL_CMD); - nrf_spim_dcx_cnt_set((NRF_SPIM_Type *)p_instance->p_reg, cmd_length); - return nrfx_spim_xfer(p_instance, p_xfer_desc, 0); -} -#endif - -static void finish_transfer(spim_control_block_t * p_cb) -{ - // If Slave Select signal is used, this is the time to deactivate it. - if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED) - { -#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) - if (!p_cb->use_hw_ss) -#endif - { - if (p_cb->ss_active_high) - { - nrf_gpio_pin_clear(p_cb->ss_pin); - } - else - { - nrf_gpio_pin_set(p_cb->ss_pin); - } - } - } - - // By clearing this flag before calling the handler we allow subsequent - // transfers to be started directly from the handler function. - p_cb->transfer_in_progress = false; - - p_cb->evt.type = NRFX_SPIM_EVENT_DONE; - p_cb->handler(&p_cb->evt, p_cb->p_context); -} - -__STATIC_INLINE void spim_int_enable(NRF_SPIM_Type * p_spim, bool enable) -{ - if (!enable) - { - nrf_spim_int_disable(p_spim, NRF_SPIM_INT_END_MASK); - } - else - { - nrf_spim_int_enable(p_spim, NRF_SPIM_INT_END_MASK); - } -} - -__STATIC_INLINE void spim_list_enable_handle(NRF_SPIM_Type * p_spim, uint32_t flags) -{ - if (NRFX_SPIM_FLAG_TX_POSTINC & flags) - { - nrf_spim_tx_list_enable(p_spim); - } - else - { - nrf_spim_tx_list_disable(p_spim); - } - - if (NRFX_SPIM_FLAG_RX_POSTINC & flags) - { - nrf_spim_rx_list_enable(p_spim); - } - else - { - nrf_spim_rx_list_disable(p_spim); - } -} - -static nrfx_err_t spim_xfer(NRF_SPIM_Type * p_spim, - spim_control_block_t * p_cb, - nrfx_spim_xfer_desc_t const * p_xfer_desc, - uint32_t flags) -{ - nrfx_err_t err_code; - // EasyDMA requires that transfer buffers are placed in Data RAM region; - // signal error if they are not. - if ((p_xfer_desc->p_tx_buffer != NULL && !nrfx_is_in_ram(p_xfer_desc->p_tx_buffer)) || - (p_xfer_desc->p_rx_buffer != NULL && !nrfx_is_in_ram(p_xfer_desc->p_rx_buffer))) - { - p_cb->transfer_in_progress = false; - err_code = NRFX_ERROR_INVALID_ADDR; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - -#if NRFX_CHECK(NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED) - p_cb->tx_length = 0; - p_cb->rx_length = 0; -#endif - - nrf_spim_tx_buffer_set(p_spim, p_xfer_desc->p_tx_buffer, p_xfer_desc->tx_length); - nrf_spim_rx_buffer_set(p_spim, p_xfer_desc->p_rx_buffer, p_xfer_desc->rx_length); - -#if NRFX_CHECK(NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED) - if (p_spim == NRF_SPIM3) - { - anomaly_198_enable(p_xfer_desc->p_tx_buffer, p_xfer_desc->tx_length); - } -#endif - - nrf_spim_event_clear(p_spim, NRF_SPIM_EVENT_END); - - spim_list_enable_handle(p_spim, flags); - - if (!(flags & NRFX_SPIM_FLAG_HOLD_XFER)) - { - nrf_spim_task_trigger(p_spim, NRF_SPIM_TASK_START); - } -#if NRFX_CHECK(NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED) - if (flags & NRFX_SPIM_FLAG_HOLD_XFER) - { - nrf_spim_event_clear(p_spim, NRF_SPIM_EVENT_STARTED); - p_cb->tx_length = p_xfer_desc->tx_length; - p_cb->rx_length = p_xfer_desc->rx_length; - nrf_spim_tx_buffer_set(p_spim, p_xfer_desc->p_tx_buffer, 0); - nrf_spim_rx_buffer_set(p_spim, p_xfer_desc->p_rx_buffer, 0); - nrf_spim_int_enable(p_spim, NRF_SPIM_INT_STARTED_MASK); - } -#endif - - if (!p_cb->handler) - { - while (!nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_END)){} - -#if NRFX_CHECK(NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED) - if (p_spim == NRF_SPIM3) - { - anomaly_198_disable(); - } -#endif - if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED) - { -#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) - if (!p_cb->use_hw_ss) -#endif - { - if (p_cb->ss_active_high) - { - nrf_gpio_pin_clear(p_cb->ss_pin); - } - else - { - nrf_gpio_pin_set(p_cb->ss_pin); - } - } - } - } - else - { - spim_int_enable(p_spim, !(flags & NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER)); - } - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -nrfx_err_t nrfx_spim_xfer(nrfx_spim_t const * const p_instance, - nrfx_spim_xfer_desc_t const * p_xfer_desc, - uint32_t flags) -{ - spim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); - NRFX_ASSERT(p_xfer_desc->p_tx_buffer != NULL || p_xfer_desc->tx_length == 0); - NRFX_ASSERT(p_xfer_desc->p_rx_buffer != NULL || p_xfer_desc->rx_length == 0); - NRFX_ASSERT(SPIM_LENGTH_VALIDATE(p_instance->drv_inst_idx, - p_xfer_desc->rx_length, - p_xfer_desc->tx_length)); - - nrfx_err_t err_code = NRFX_SUCCESS; - - if (p_cb->transfer_in_progress) - { - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - else - { - if (p_cb->handler && !(flags & (NRFX_SPIM_FLAG_REPEATED_XFER | - NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER))) - { - p_cb->transfer_in_progress = true; - } - } - - p_cb->evt.xfer_desc = *p_xfer_desc; - - if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED) - { -#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) - if (!p_cb->use_hw_ss) -#endif - { - if (p_cb->ss_active_high) - { - nrf_gpio_pin_set(p_cb->ss_pin); - } - else - { - nrf_gpio_pin_clear(p_cb->ss_pin); - } - } - } - - return spim_xfer(p_instance->p_reg, p_cb, p_xfer_desc, flags); -} - -void nrfx_spim_abort(nrfx_spim_t const * p_instance) -{ - spim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); - - nrf_spim_task_trigger(p_instance->p_reg, NRF_SPIM_TASK_STOP); - while (!nrf_spim_event_check(p_instance->p_reg, NRF_SPIM_EVENT_STOPPED)) - {} - p_cb->transfer_in_progress = false; -} - -uint32_t nrfx_spim_start_task_get(nrfx_spim_t const * p_instance) -{ - NRF_SPIM_Type * p_spim = (NRF_SPIM_Type *)p_instance->p_reg; - return nrf_spim_task_address_get(p_spim, NRF_SPIM_TASK_START); -} - -uint32_t nrfx_spim_end_event_get(nrfx_spim_t const * p_instance) -{ - NRF_SPIM_Type * p_spim = (NRF_SPIM_Type *)p_instance->p_reg; - return nrf_spim_event_address_get(p_spim, NRF_SPIM_EVENT_END); -} - -static void irq_handler(NRF_SPIM_Type * p_spim, spim_control_block_t * p_cb) -{ - -#if NRFX_CHECK(NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED) - if ((nrf_spim_int_enable_check(p_spim, NRF_SPIM_INT_STARTED_MASK)) && - (nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_STARTED)) ) - { - /* Handle first, zero-length, auxiliary transmission. */ - nrf_spim_event_clear(p_spim, NRF_SPIM_EVENT_STARTED); - nrf_spim_event_clear(p_spim, NRF_SPIM_EVENT_END); - - NRFX_ASSERT(p_spim->TXD.MAXCNT == 0); - p_spim->TXD.MAXCNT = p_cb->tx_length; - - NRFX_ASSERT(p_spim->RXD.MAXCNT == 0); - p_spim->RXD.MAXCNT = p_cb->rx_length; - - /* Disable STARTED interrupt, used only in auxiliary transmission. */ - nrf_spim_int_disable(p_spim, NRF_SPIM_INT_STARTED_MASK); - - /* Start the actual, glitch-free transmission. */ - nrf_spim_task_trigger(p_spim, NRF_SPIM_TASK_START); - return; - } -#endif - - if (nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_END)) - { -#if NRFX_CHECK(NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED) - if (p_spim == NRF_SPIM3) - { - anomaly_198_disable(); - } -#endif - nrf_spim_event_clear(p_spim, NRF_SPIM_EVENT_END); - NRFX_ASSERT(p_cb->handler); - NRFX_LOG_DEBUG("Event: NRF_SPIM_EVENT_END."); - finish_transfer(p_cb); - } -} - -#if NRFX_CHECK(NRFX_SPIM0_ENABLED) -void nrfx_spim_0_irq_handler(void) -{ - irq_handler(NRF_SPIM0, &m_cb[NRFX_SPIM0_INST_IDX]); -} -#endif - -#if NRFX_CHECK(NRFX_SPIM1_ENABLED) -void nrfx_spim_1_irq_handler(void) -{ - irq_handler(NRF_SPIM1, &m_cb[NRFX_SPIM1_INST_IDX]); -} -#endif - -#if NRFX_CHECK(NRFX_SPIM2_ENABLED) -void nrfx_spim_2_irq_handler(void) -{ - irq_handler(NRF_SPIM2, &m_cb[NRFX_SPIM2_INST_IDX]); -} -#endif - -#if NRFX_CHECK(NRFX_SPIM3_ENABLED) -void nrfx_spim_3_irq_handler(void) -{ - irq_handler(NRF_SPIM3, &m_cb[NRFX_SPIM3_INST_IDX]); -} -#endif - -#endif // NRFX_CHECK(NRFX_SPIM_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_spis.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_spis.c deleted file mode 100644 index 7470cefb73..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_spis.c +++ /dev/null @@ -1,494 +0,0 @@ -/** - * Copyright (c) 2013 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include - -#if NRFX_CHECK(NRFX_SPIS_ENABLED) - -#if !(NRFX_CHECK(NRFX_SPIS0_ENABLED) || NRFX_CHECK(NRFX_SPIS1_ENABLED) || \ - NRFX_CHECK(NRFX_SPIS2_ENABLED)) -#error "No enabled SPIS instances. Check ." -#endif - -#include -#include "prs/nrfx_prs.h" - -#define NRFX_LOG_MODULE SPIS -#include - -#define EVT_TO_STR(event) \ - (event == NRF_SPIS_EVENT_ACQUIRED ? "NRF_SPIS_EVENT_ACQUIRED" : \ - (event == NRF_SPIS_EVENT_END ? "NRF_SPIS_EVENT_END" : \ - "UNKNOWN ERROR")) - -#define SPISX_LENGTH_VALIDATE(peripheral, drv_inst_idx, rx_len, tx_len) \ - (((drv_inst_idx) == NRFX_CONCAT_3(NRFX_, peripheral, _INST_IDX)) && \ - NRFX_EASYDMA_LENGTH_VALIDATE(peripheral, rx_len, tx_len)) - -#if NRFX_CHECK(NRFX_SPIS0_ENABLED) -#define SPIS0_LENGTH_VALIDATE(...) SPISX_LENGTH_VALIDATE(SPIS0, __VA_ARGS__) -#else -#define SPIS0_LENGTH_VALIDATE(...) 0 -#endif - -#if NRFX_CHECK(NRFX_SPIS1_ENABLED) -#define SPIS1_LENGTH_VALIDATE(...) SPISX_LENGTH_VALIDATE(SPIS1, __VA_ARGS__) -#else -#define SPIS1_LENGTH_VALIDATE(...) 0 -#endif - -#if NRFX_CHECK(NRFX_SPIS2_ENABLED) -#define SPIS2_LENGTH_VALIDATE(...) SPISX_LENGTH_VALIDATE(SPIS2, __VA_ARGS__) -#else -#define SPIS2_LENGTH_VALIDATE(...) 0 -#endif - -#define SPIS_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len) \ - (SPIS0_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len) || \ - SPIS1_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len) || \ - SPIS2_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len)) - - -#if NRFX_CHECK(NRFX_SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED) -#include -#define USE_DMA_ISSUE_WORKAROUND -// This handler is called by the GPIOTE driver when a falling edge is detected -// on the CSN line. There is no need to do anything here. The handling of the -// interrupt itself provides a protection for DMA transfers. -static void csn_event_handler(nrfx_gpiote_pin_t pin, - nrf_gpiote_polarity_t action) -{ -} -#endif - - -/**@brief States of the SPI transaction state machine. */ -typedef enum -{ - SPIS_STATE_INIT, /**< Initialization state. In this state the module waits for a call to @ref spi_slave_buffers_set. */ - SPIS_BUFFER_RESOURCE_REQUESTED, /**< State where the configuration of the memory buffers, which are to be used in SPI transaction, has started. */ - SPIS_BUFFER_RESOURCE_CONFIGURED, /**< State where the configuration of the memory buffers, which are to be used in SPI transaction, has completed. */ - SPIS_XFER_COMPLETED /**< State where SPI transaction has been completed. */ -} nrfx_spis_state_t; - -/**@brief SPIS control block - driver instance local data. */ -typedef struct -{ - volatile uint32_t tx_buffer_size; //!< SPI slave TX buffer size in bytes. - volatile uint32_t rx_buffer_size; //!< SPI slave RX buffer size in bytes. - nrfx_spis_event_handler_t handler; //!< SPI event handler. - volatile const uint8_t * tx_buffer; //!< SPI slave TX buffer. - volatile uint8_t * rx_buffer; //!< SPI slave RX buffer. - nrfx_drv_state_t state; //!< driver initialization state. - volatile nrfx_spis_state_t spi_state; //!< SPI slave state. - void * p_context; //!< Context set on initialization. -} spis_cb_t; - -static spis_cb_t m_cb[NRFX_SPIS_ENABLED_COUNT]; - -nrfx_err_t nrfx_spis_init(nrfx_spis_t const * const p_instance, - nrfx_spis_config_t const * p_config, - nrfx_spis_event_handler_t event_handler, - void * p_context) -{ - NRFX_ASSERT(p_config); - NRFX_ASSERT(event_handler); - spis_cb_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - nrfx_err_t err_code; - - NRF_SPIS_Type * p_spis = p_instance->p_reg; - - if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED) - { - err_code = NRFX_ERROR_INVALID_STATE; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - if ((uint32_t)p_config->mode > (uint32_t)NRF_SPIS_MODE_3) - { - err_code = NRFX_ERROR_INVALID_PARAM; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } -#if NRFX_CHECK(NRFX_PRS_ENABLED) - static nrfx_irq_handler_t const irq_handlers[NRFX_SPIS_ENABLED_COUNT] = { - #if NRFX_CHECK(NRFX_SPIS0_ENABLED) - nrfx_spis_0_irq_handler, - #endif - #if NRFX_CHECK(NRFX_SPIS1_ENABLED) - nrfx_spis_1_irq_handler, - #endif - #if NRFX_CHECK(NRFX_SPIS2_ENABLED) - nrfx_spis_2_irq_handler, - #endif - }; - if (nrfx_prs_acquire(p_spis, - irq_handlers[p_instance->drv_inst_idx]) != NRFX_SUCCESS) - { - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } -#endif // NRFX_CHECK(NRFX_PRS_ENABLED) - - // Configure the SPI pins for input. - uint32_t mosi_pin; - uint32_t miso_pin; - - if (p_config->miso_pin != NRFX_SPIS_PIN_NOT_USED) - { - nrf_gpio_cfg(p_config->miso_pin, - NRF_GPIO_PIN_DIR_INPUT, - NRF_GPIO_PIN_INPUT_CONNECT, - NRF_GPIO_PIN_NOPULL, - p_config->miso_drive, - NRF_GPIO_PIN_NOSENSE); - miso_pin = p_config->miso_pin; - } - else - { - miso_pin = NRF_SPIS_PIN_NOT_CONNECTED; - } - - if (p_config->mosi_pin != NRFX_SPIS_PIN_NOT_USED) - { - nrf_gpio_cfg(p_config->mosi_pin, - NRF_GPIO_PIN_DIR_INPUT, - NRF_GPIO_PIN_INPUT_CONNECT, - NRF_GPIO_PIN_NOPULL, - NRF_GPIO_PIN_S0S1, - NRF_GPIO_PIN_NOSENSE); - mosi_pin = p_config->mosi_pin; - } - else - { - mosi_pin = NRF_SPIS_PIN_NOT_CONNECTED; - } - - nrf_gpio_cfg(p_config->csn_pin, - NRF_GPIO_PIN_DIR_INPUT, - NRF_GPIO_PIN_INPUT_CONNECT, - p_config->csn_pullup, - NRF_GPIO_PIN_S0S1, - NRF_GPIO_PIN_NOSENSE); - - nrf_gpio_cfg(p_config->sck_pin, - NRF_GPIO_PIN_DIR_INPUT, - NRF_GPIO_PIN_INPUT_CONNECT, - NRF_GPIO_PIN_NOPULL, - NRF_GPIO_PIN_S0S1, - NRF_GPIO_PIN_NOSENSE); - - nrf_spis_pins_set(p_spis, p_config->sck_pin, mosi_pin, miso_pin, p_config->csn_pin); - - nrf_spis_rx_buffer_set(p_spis, NULL, 0); - nrf_spis_tx_buffer_set(p_spis, NULL, 0); - - // Configure SPI mode. - nrf_spis_configure(p_spis, p_config->mode, p_config->bit_order); - - // Configure DEF and ORC characters. - nrf_spis_def_set(p_spis, p_config->def); - nrf_spis_orc_set(p_spis, p_config->orc); - - // Clear possible pending events. - nrf_spis_event_clear(p_spis, NRF_SPIS_EVENT_END); - nrf_spis_event_clear(p_spis, NRF_SPIS_EVENT_ACQUIRED); - - // Enable END_ACQUIRE shortcut. - nrf_spis_shorts_enable(p_spis, NRF_SPIS_SHORT_END_ACQUIRE); - - p_cb->spi_state = SPIS_STATE_INIT; - p_cb->handler = event_handler; - p_cb->p_context = p_context; - -#if defined(USE_DMA_ISSUE_WORKAROUND) - // Configure a GPIOTE channel to generate interrupts on each falling edge - // on the CSN line. Handling of these interrupts will make the CPU active, - // and thus will protect the DMA transfers started by SPIS right after it - // is selected for communication. - // [the GPIOTE driver may be already initialized at this point (by this - // driver when another SPIS instance is used, or by an application code), - // so just ignore the returned value] - (void)nrfx_gpiote_init(); - static nrfx_gpiote_in_config_t const csn_gpiote_config = - NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO(true); - nrfx_err_t gpiote_err_code = nrfx_gpiote_in_init(p_config->csn_pin, - &csn_gpiote_config, csn_event_handler); - if (gpiote_err_code != NRFX_SUCCESS) - { - err_code = NRFX_ERROR_INTERNAL; - NRFX_LOG_INFO("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - nrfx_gpiote_in_event_enable(p_config->csn_pin, true); -#endif - - // Enable IRQ. - nrf_spis_int_enable(p_spis, NRF_SPIS_INT_ACQUIRED_MASK | - NRF_SPIS_INT_END_MASK); - NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_instance->p_reg), - p_config->irq_priority); - NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_instance->p_reg)); - - p_cb->state = NRFX_DRV_STATE_INITIALIZED; - - // Enable SPI slave device. - nrf_spis_enable(p_spis); - - NRFX_LOG_INFO("Initialized."); - return NRFX_SUCCESS; -} - - -void nrfx_spis_uninit(nrfx_spis_t const * const p_instance) -{ - spis_cb_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); - - NRF_SPIS_Type * p_spis = p_instance->p_reg; - - #define DISABLE_ALL 0xFFFFFFFF - nrf_spis_disable(p_spis); - NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_instance->p_reg)); - nrf_spis_int_disable(p_spis, DISABLE_ALL); - #undef DISABLE_ALL - -#if NRFX_CHECK(NRFX_PRS_ENABLED) - nrfx_prs_release(p_spis); -#endif - - p_cb->state = NRFX_DRV_STATE_UNINITIALIZED; - NRFX_LOG_INFO("Uninitialized."); -} - - -/**@brief Function for executing the state entry action. */ -static void spis_state_entry_action_execute(NRF_SPIS_Type * p_spis, - spis_cb_t * p_cb) -{ - nrfx_spis_evt_t event; - - switch (p_cb->spi_state) - { - case SPIS_BUFFER_RESOURCE_REQUESTED: - nrf_spis_task_trigger(p_spis, NRF_SPIS_TASK_ACQUIRE); - break; - - case SPIS_BUFFER_RESOURCE_CONFIGURED: - event.evt_type = NRFX_SPIS_BUFFERS_SET_DONE; - event.rx_amount = 0; - event.tx_amount = 0; - - NRFX_ASSERT(p_cb->handler != NULL); - p_cb->handler(&event, p_cb->p_context); - break; - - case SPIS_XFER_COMPLETED: - event.evt_type = NRFX_SPIS_XFER_DONE; - event.rx_amount = nrf_spis_rx_amount_get(p_spis); - event.tx_amount = nrf_spis_tx_amount_get(p_spis); - NRFX_LOG_INFO("Transfer rx_len:%d.", event.rx_amount); - NRFX_LOG_DEBUG("Rx data:"); - NRFX_LOG_HEXDUMP_DEBUG((uint8_t const *)p_cb->rx_buffer, - event.rx_amount * sizeof(p_cb->rx_buffer[0])); - NRFX_ASSERT(p_cb->handler != NULL); - p_cb->handler(&event, p_cb->p_context); - break; - - default: - // No implementation required. - break; - } -} - -/**@brief Function for changing the state of the SPI state machine. - * - * @param[in] p_spis SPIS instance register. - * @param[in] p_cb SPIS instance control block. - * @param[in] new_state State where the state machine transits to. - */ -static void spis_state_change(NRF_SPIS_Type * p_spis, - spis_cb_t * p_cb, - nrfx_spis_state_t new_state) -{ - p_cb->spi_state = new_state; - spis_state_entry_action_execute(p_spis, p_cb); -} - -nrfx_err_t nrfx_spis_buffers_set(nrfx_spis_t const * const p_instance, - uint8_t const * p_tx_buffer, - size_t tx_buffer_length, - uint8_t * p_rx_buffer, - size_t rx_buffer_length) -{ - NRFX_ASSERT(p_tx_buffer != NULL || tx_buffer_length == 0); - NRFX_ASSERT(p_rx_buffer != NULL || rx_buffer_length == 0); - - spis_cb_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - nrfx_err_t err_code; - - if (!SPIS_LENGTH_VALIDATE(p_instance->drv_inst_idx, - rx_buffer_length, - tx_buffer_length)) - { - return NRFX_ERROR_INVALID_LENGTH; - } - - // EasyDMA requires that transfer buffers are placed in Data RAM region; - // signal error if they are not. - if ((p_tx_buffer != NULL && !nrfx_is_in_ram(p_tx_buffer)) || - (p_rx_buffer != NULL && !nrfx_is_in_ram(p_rx_buffer))) - { - err_code = NRFX_ERROR_INVALID_ADDR; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - switch (p_cb->spi_state) - { - case SPIS_STATE_INIT: - case SPIS_XFER_COMPLETED: - case SPIS_BUFFER_RESOURCE_CONFIGURED: - p_cb->tx_buffer = p_tx_buffer; - p_cb->rx_buffer = p_rx_buffer; - p_cb->tx_buffer_size = tx_buffer_length; - p_cb->rx_buffer_size = rx_buffer_length; - err_code = NRFX_SUCCESS; - - spis_state_change(p_instance->p_reg, p_cb, SPIS_BUFFER_RESOURCE_REQUESTED); - break; - - case SPIS_BUFFER_RESOURCE_REQUESTED: - err_code = NRFX_ERROR_INVALID_STATE; - break; - - default: - // @note: execution of this code path would imply internal error in the design. - err_code = NRFX_ERROR_INTERNAL; - break; - } - - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -static void spis_irq_handler(NRF_SPIS_Type * p_spis, spis_cb_t * p_cb) -{ - // @note: as multiple events can be pending for processing, the correct event processing order - // is as follows: - // - SPI semaphore acquired event. - // - SPI transaction complete event. - - // Check for SPI semaphore acquired event. - if (nrf_spis_event_check(p_spis, NRF_SPIS_EVENT_ACQUIRED)) - { - nrf_spis_event_clear(p_spis, NRF_SPIS_EVENT_ACQUIRED); - NRFX_LOG_DEBUG("SPIS: Event: %s.", EVT_TO_STR(NRF_SPIS_EVENT_ACQUIRED)); - - switch (p_cb->spi_state) - { - case SPIS_BUFFER_RESOURCE_REQUESTED: - nrf_spis_tx_buffer_set(p_spis, (uint8_t *)p_cb->tx_buffer, p_cb->tx_buffer_size); - nrf_spis_rx_buffer_set(p_spis, (uint8_t *)p_cb->rx_buffer, p_cb->rx_buffer_size); - - nrf_spis_task_trigger(p_spis, NRF_SPIS_TASK_RELEASE); - - spis_state_change(p_spis, p_cb, SPIS_BUFFER_RESOURCE_CONFIGURED); - break; - - default: - // No implementation required. - break; - } - } - - // Check for SPI transaction complete event. - if (nrf_spis_event_check(p_spis, NRF_SPIS_EVENT_END)) - { - nrf_spis_event_clear(p_spis, NRF_SPIS_EVENT_END); - NRFX_LOG_DEBUG("SPIS: Event: %s.", EVT_TO_STR(NRF_SPIS_EVENT_END)); - - switch (p_cb->spi_state) - { - case SPIS_BUFFER_RESOURCE_CONFIGURED: - spis_state_change(p_spis, p_cb, SPIS_XFER_COMPLETED); - break; - - default: - // No implementation required. - break; - } - } -} - -#if NRFX_CHECK(NRFX_SPIS0_ENABLED) -void nrfx_spis_0_irq_handler(void) -{ - spis_irq_handler(NRF_SPIS0, &m_cb[NRFX_SPIS0_INST_IDX]); -} -#endif - -#if NRFX_CHECK(NRFX_SPIS1_ENABLED) -void nrfx_spis_1_irq_handler(void) -{ - spis_irq_handler(NRF_SPIS1, &m_cb[NRFX_SPIS1_INST_IDX]); -} -#endif - -#if NRFX_CHECK(NRFX_SPIS2_ENABLED) -void nrfx_spis_2_irq_handler(void) -{ - spis_irq_handler(NRF_SPIS2, &m_cb[NRFX_SPIS2_INST_IDX]); -} -#endif - -#endif // NRFX_CHECK(NRFX_SPIS_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_swi.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_swi.c deleted file mode 100644 index 89f5802155..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_swi.c +++ /dev/null @@ -1,412 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include - -#if NRFX_CHECK(NRFX_SWI_ENABLED) - -#include - -#define NRFX_LOG_MODULE SWI -#include - - -// NRFX_SWI_RESERVED_MASK - SWIs reserved for use by external modules. -#if NRFX_CHECK(NRFX_PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED) -#define NRFX_SWI_RESERVED_MASK ((NRFX_SWI_USED) | \ - (1u << NRFX_PWM_NRF52_ANOMALY_109_EGU_INSTANCE)) -#else -#define NRFX_SWI_RESERVED_MASK (NRFX_SWI_USED) -#endif - -// NRFX_SWI_DISABLED_MASK - SWIs excluded from use in . -#if NRFX_CHECK(NRFX_SWI0_DISABLED) -#define NRFX_SWI0_DISABLED_MASK (1u << 0) -#else -#define NRFX_SWI0_DISABLED_MASK 0u -#endif -#if NRFX_CHECK(NRFX_SWI1_DISABLED) -#define NRFX_SWI1_DISABLED_MASK (1u << 1) -#else -#define NRFX_SWI1_DISABLED_MASK 0u -#endif -#if NRFX_CHECK(NRFX_SWI2_DISABLED) -#define NRFX_SWI2_DISABLED_MASK (1u << 2) -#else -#define NRFX_SWI2_DISABLED_MASK 0u -#endif -#if NRFX_CHECK(NRFX_SWI3_DISABLED) -#define NRFX_SWI3_DISABLED_MASK (1u << 3) -#else -#define NRFX_SWI3_DISABLED_MASK 0u -#endif -#if NRFX_CHECK(NRFX_SWI4_DISABLED) -#define NRFX_SWI4_DISABLED_MASK (1u << 4) -#else -#define NRFX_SWI4_DISABLED_MASK 0u -#endif -#if NRFX_CHECK(NRFX_SWI5_DISABLED) -#define NRFX_SWI5_DISABLED_MASK (1u << 5) -#else -#define NRFX_SWI5_DISABLED_MASK 0u -#endif -#define NRFX_SWI_DISABLED_MASK (NRFX_SWI0_DISABLED_MASK | \ - NRFX_SWI1_DISABLED_MASK | \ - NRFX_SWI2_DISABLED_MASK | \ - NRFX_SWI3_DISABLED_MASK | \ - NRFX_SWI4_DISABLED_MASK | \ - NRFX_SWI5_DISABLED_MASK) - -#if (NRFX_SWI_RESERVED_MASK & NRFX_SWI_DISABLED_MASK) -#error "A reserved SWI configured to be disabled. Check and NRFX_SWI_USED." -#endif - -// NRFX_SWI_AVAILABLE_MASK - SWIs available for this module, i.e. present -// in the hardware and neither reserved by external modules nor disabled -// in . -#define NRFX_SWI_PRESENT_MASK ((1u << (SWI_COUNT)) - 1u) -#define NRFX_SWI_AVAILABLE_MASK (NRFX_SWI_PRESENT_MASK & \ - ~(NRFX_SWI_RESERVED_MASK | \ - NRFX_SWI_DISABLED_MASK)) - -#if (NRFX_SWI_AVAILABLE_MASK == 0) -#error "No available SWI instances. Check and NRFX_SWI_USED." -#endif - -#define NRFX_SWI_IS_AVAILABLE(idx) ((NRFX_SWI_AVAILABLE_MASK >> (idx)) & 1u) - -#define NRFX_SWI_FIRST (NRFX_SWI_IS_AVAILABLE(0) ? 0u : \ - (NRFX_SWI_IS_AVAILABLE(1) ? 1u : \ - (NRFX_SWI_IS_AVAILABLE(2) ? 2u : \ - (NRFX_SWI_IS_AVAILABLE(3) ? 3u : \ - (NRFX_SWI_IS_AVAILABLE(4) ? 4u : \ - 5u))))) -#define NRFX_SWI_LAST (NRFX_SWI_IS_AVAILABLE(5) ? 5u : \ - (NRFX_SWI_IS_AVAILABLE(4) ? 4u : \ - (NRFX_SWI_IS_AVAILABLE(3) ? 3u : \ - (NRFX_SWI_IS_AVAILABLE(2) ? 2u : \ - (NRFX_SWI_IS_AVAILABLE(1) ? 1u : \ - 0u))))) - -// NRFX_SWI_EGU_COUNT - number of EGU instances to be used by this module -// (note - if EGU is not present, EGU_COUNT is not defined). -#if NRFX_CHECK(NRFX_EGU_ENABLED) -#define NRFX_SWI_EGU_COUNT EGU_COUNT -#else -#define NRFX_SWI_EGU_COUNT 0 -#endif - -// These flags are needed only for SWIs that have no corresponding EGU unit -// (in EGU such flags are available in hardware). -#if (NRFX_SWI_EGU_COUNT < SWI_COUNT) -static nrfx_swi_flags_t m_swi_flags[SWI_COUNT - NRFX_SWI_EGU_COUNT]; -#endif -static nrfx_swi_handler_t m_swi_handlers[SWI_COUNT]; -static uint8_t m_swi_allocated_mask; - - -static void swi_mark_allocated(nrfx_swi_t swi) -{ - m_swi_allocated_mask |= (1u << swi); -} - -static void swi_mark_unallocated(nrfx_swi_t swi) -{ - m_swi_allocated_mask &= ~(1u << swi); -} - -static bool swi_is_allocated(nrfx_swi_t swi) -{ - return (m_swi_allocated_mask & (1u << swi)); -} - -static bool swi_is_available(nrfx_swi_t swi) -{ - return NRFX_SWI_IS_AVAILABLE(swi); -} - -static IRQn_Type swi_irq_number_get(nrfx_swi_t swi) -{ - return (IRQn_Type)((uint32_t)SWI0_IRQn + (uint32_t)swi); -} - -static void swi_handler_setup(nrfx_swi_t swi, - nrfx_swi_handler_t event_handler, - uint32_t irq_priority) -{ - m_swi_handlers[swi] = event_handler; - -#if NRFX_SWI_EGU_COUNT - if (swi < NRFX_SWI_EGU_COUNT) - { - NRF_EGU_Type * p_egu = nrfx_swi_egu_instance_get(swi); - NRFX_ASSERT(p_egu != NULL); - nrf_egu_int_enable(p_egu, NRF_EGU_INT_ALL); - - if (event_handler == NULL) - { - return; - } - } -#endif - - NRFX_ASSERT(event_handler != NULL); - - NRFX_IRQ_PRIORITY_SET(swi_irq_number_get(swi), irq_priority); - NRFX_IRQ_ENABLE(swi_irq_number_get(swi)); -} - -nrfx_err_t nrfx_swi_alloc(nrfx_swi_t * p_swi, - nrfx_swi_handler_t event_handler, - uint32_t irq_priority) -{ - NRFX_ASSERT(p_swi != NULL); - - nrfx_err_t err_code; - - for (nrfx_swi_t swi = NRFX_SWI_FIRST; swi <= NRFX_SWI_LAST; ++swi) - { - if (swi_is_available(swi)) - { - bool allocated = false; - NRFX_CRITICAL_SECTION_ENTER(); - if (!swi_is_allocated(swi)) - { - swi_mark_allocated(swi); - allocated = true; - } - NRFX_CRITICAL_SECTION_EXIT(); - - if (allocated) - { - swi_handler_setup(swi, event_handler, irq_priority); - - *p_swi = swi; - NRFX_LOG_INFO("SWI channel allocated: %d.", (*p_swi)); - return NRFX_SUCCESS; - } - } - } - - err_code = NRFX_ERROR_NO_MEM; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -bool nrfx_swi_is_allocated(nrfx_swi_t swi) -{ - return swi_is_allocated(swi); -} - -void nrfx_swi_free(nrfx_swi_t * p_swi) -{ - NRFX_ASSERT(p_swi != NULL); - nrfx_swi_t swi = *p_swi; - - NRFX_ASSERT(swi_is_allocated(swi)); - NRFX_IRQ_DISABLE(swi_irq_number_get(swi)); - m_swi_handlers[swi] = NULL; - - swi_mark_unallocated(swi); - *p_swi = NRFX_SWI_UNALLOCATED; -} - -void nrfx_swi_all_free(void) -{ - for (nrfx_swi_t swi = NRFX_SWI_FIRST; swi <= NRFX_SWI_LAST; ++swi) - { - if (swi_is_allocated(swi)) - { - NRFX_IRQ_DISABLE(swi_irq_number_get(swi)); - m_swi_handlers[swi] = NULL; -#if NRFX_SWI_EGU_COUNT - if (swi < NRFX_SWI_EGU_COUNT) - { - nrf_egu_int_disable(nrfx_swi_egu_instance_get(swi), - NRF_EGU_INT_ALL); - } -#endif - } - } - - m_swi_allocated_mask = 0; -} - -void nrfx_swi_trigger(nrfx_swi_t swi, uint8_t flag_number) -{ - NRFX_ASSERT(swi_is_allocated(swi)); - -#if NRFX_SWI_EGU_COUNT - - NRF_EGU_Type * p_egu = nrfx_swi_egu_instance_get(swi); -#if (NRFX_SWI_EGU_COUNT < SWI_COUNT) - if (p_egu == NULL) - { - m_swi_flags[swi - NRFX_SWI_EGU_COUNT] |= (1 << flag_number); - NRFX_IRQ_PENDING_SET(swi_irq_number_get(swi)); - } - else -#endif // (NRFX_SWI_EGU_COUNT < SWI_COUNT) - { - nrf_egu_task_trigger(p_egu, - nrf_egu_task_trigger_get(p_egu, flag_number)); - } - -#else // -> #if !NRFX_SWI_EGU_COUNT - - m_swi_flags[swi - NRFX_SWI_EGU_COUNT] |= (1 << flag_number); - NRFX_IRQ_PENDING_SET(swi_irq_number_get(swi)); - -#endif -} - -#if NRFX_SWI_EGU_COUNT -static void egu_irq_handler(nrfx_swi_t swi, uint8_t egu_channel_count) -{ -#if (NRFX_SWI_FIRST > 0) - NRFX_ASSERT(swi >= NRFX_SWI_FIRST); -#endif - NRFX_ASSERT(swi <= NRFX_SWI_LAST); - nrfx_swi_handler_t handler = m_swi_handlers[swi]; - NRFX_ASSERT(handler != NULL); - - NRF_EGU_Type * p_egu = nrfx_swi_egu_instance_get(swi); - NRFX_ASSERT(p_egu != NULL); - - nrfx_swi_flags_t flags = 0; - for (uint8_t i = 0; i < egu_channel_count; ++i) - { - nrf_egu_event_t egu_event = nrf_egu_event_triggered_get(p_egu, i); - if (nrf_egu_event_check(p_egu, egu_event)) - { - flags |= (1u << i); - nrf_egu_event_clear(p_egu, egu_event); - } - } - - handler(swi, flags); -} -#endif // NRFX_SWI_EGU_COUNT - -#if (NRFX_SWI_EGU_COUNT < SWI_COUNT) -static void swi_irq_handler(nrfx_swi_t swi) -{ -#if (NRFX_SWI_FIRST > 0) - NRFX_ASSERT(swi >= NRFX_SWI_FIRST); -#endif - NRFX_ASSERT(swi <= NRFX_SWI_LAST); - nrfx_swi_handler_t handler = m_swi_handlers[swi]; - NRFX_ASSERT(handler != NULL); - - nrfx_swi_flags_t flags = m_swi_flags[swi - NRFX_SWI_EGU_COUNT]; - m_swi_flags[swi - NRFX_SWI_EGU_COUNT] &= ~flags; - - handler(swi, flags); -} -#endif // (NRFX_SWI_EGU_COUNT < SWI_COUNT) - - -#if NRFX_SWI_IS_AVAILABLE(0) -void nrfx_swi_0_irq_handler(void) -{ -#if (NRFX_SWI_EGU_COUNT > 0) - egu_irq_handler(0, EGU0_CH_NUM); -#else - swi_irq_handler(0); -#endif -} -#endif // NRFX_SWI_IS_AVAILABLE(0) - -#if NRFX_SWI_IS_AVAILABLE(1) -void nrfx_swi_1_irq_handler(void) -{ -#if (NRFX_SWI_EGU_COUNT > 1) - egu_irq_handler(1, EGU1_CH_NUM); -#else - swi_irq_handler(1); -#endif -} -#endif // NRFX_SWI_IS_AVAILABLE(1) - -#if NRFX_SWI_IS_AVAILABLE(2) -void nrfx_swi_2_irq_handler(void) -{ -#if (NRFX_SWI_EGU_COUNT > 2) - egu_irq_handler(2, EGU2_CH_NUM); -#else - swi_irq_handler(2); -#endif -} -#endif // NRFX_SWI_IS_AVAILABLE(2) - -#if NRFX_SWI_IS_AVAILABLE(3) -void nrfx_swi_3_irq_handler(void) -{ -#if (NRFX_SWI_EGU_COUNT > 3) - egu_irq_handler(3, EGU3_CH_NUM); -#else - swi_irq_handler(3); -#endif -} -#endif // NRFX_SWI_IS_AVAILABLE(3) - -#if NRFX_SWI_IS_AVAILABLE(4) -void nrfx_swi_4_irq_handler(void) -{ -#if (NRFX_SWI_EGU_COUNT > 4) - egu_irq_handler(4, EGU4_CH_NUM); -#else - swi_irq_handler(4); -#endif -} -#endif // NRFX_SWI_IS_AVAILABLE(4) - -#if NRFX_SWI_IS_AVAILABLE(5) -void nrfx_swi_5_irq_handler(void) -{ -#if (NRFX_SWI_EGU_COUNT > 5) - egu_irq_handler(5, EGU5_CH_NUM); -#else - swi_irq_handler(5); -#endif -} -#endif // NRFX_SWI_IS_AVAILABLE(5) - -#endif // NRFX_CHECK(NRFX_SWI_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_systick.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_systick.c deleted file mode 100644 index 9261ce6197..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_systick.c +++ /dev/null @@ -1,170 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#include - -#if NRFX_CHECK(NRFX_SYSTICK_ENABLED) -#include - -/** - * @brief Maximum number of ticks to delay - * - * The maximum number of ticks should be much lower than - * Physical maximum count of the SysTick timer. - * It is dictated by the fact that it would be impossible to detect delay - * properly when the timer value warps around the starting point. - */ -#define NRFX_SYSTICK_TICKS_MAX (NRF_SYSTICK_VAL_MASK / 2UL) - -/** - * @brief Number of milliseconds in a second - */ -#define NRFX_SYSTICK_MS (1000UL) - -/** - * @brief Number of microseconds in a second - */ -#define NRFX_SYSTICK_US (1000UL * NRFX_SYSTICK_MS) - -/** - * @brief Number of milliseconds to wait in single loop - * - * Constant used by @ref nrd_drv_systick_delay_ms function - * to split waiting into loops and rest. - * - * It describes the number of milliseconds to wait in single loop. - * - * See @ref nrfx_systick_delay_ms source code for details. - */ -#define NRFX_SYSTICK_MS_STEP (64U) - -/** - * @brief Checks if the given time is in correct range - * - * Function tests given time is not to big for this library. - * Assertion is used for testing. - * - * @param us Time in microseconds to check - */ -#define NRFX_SYSTICK_ASSERT_TIMEOUT(us) \ - NRFX_ASSERT(us <= (NRFX_SYSTICK_TICKS_MAX / ((SystemCoreClock) / NRFX_SYSTICK_US))); - -/** - * @brief Function that converts microseconds to ticks - * - * Function converts from microseconds to CPU ticks. - * - * @param us Number of microseconds - * - * @return Number of ticks - * - * @sa nrfx_systick_ms_tick - */ -static inline uint32_t nrfx_systick_us_tick(uint32_t us) -{ - return us * ((SystemCoreClock) / NRFX_SYSTICK_US); -} - -/** - * @brief Function that converts milliseconds to ticks - * - * Function converts from milliseconds to CPU ticks. - * - * @param us Number of milliseconds - * - * @return Number of ticks - * - * @sa nrfx_systick_us_tick - */ -static inline uint32_t nrfx_systick_ms_tick(uint32_t ms) -{ - return ms * ((SystemCoreClock) / NRFX_SYSTICK_MS); -} - -void nrfx_systick_init(void) -{ - nrf_systick_load_set(NRF_SYSTICK_VAL_MASK); - nrf_systick_csr_set( - NRF_SYSTICK_CSR_CLKSOURCE_CPU | - NRF_SYSTICK_CSR_TICKINT_DISABLE | - NRF_SYSTICK_CSR_ENABLE); -} - -void nrfx_systick_get(nrfx_systick_state_t * p_state) -{ - p_state->time = nrf_systick_val_get(); -} - -bool nrfx_systick_test(nrfx_systick_state_t const * p_state, uint32_t us) -{ - NRFX_SYSTICK_ASSERT_TIMEOUT(us); - - const uint32_t diff = NRF_SYSTICK_VAL_MASK & ((p_state->time) - nrf_systick_val_get()); - return (diff >= nrfx_systick_us_tick(us)); -} - -void nrfx_systick_delay_ticks(uint32_t ticks) -{ - NRFX_ASSERT(ticks <= NRFX_SYSTICK_TICKS_MAX); - - const uint32_t start = nrf_systick_val_get(); - while ((NRF_SYSTICK_VAL_MASK & (start - nrf_systick_val_get())) < ticks) - { - /* Nothing to do */ - } -} - -void nrfx_systick_delay_us(uint32_t us) -{ - NRFX_SYSTICK_ASSERT_TIMEOUT(us); - nrfx_systick_delay_ticks(nrfx_systick_us_tick(us)); -} - -void nrfx_systick_delay_ms(uint32_t ms) -{ - uint32_t n = ms / NRFX_SYSTICK_MS_STEP; - uint32_t r = ms % NRFX_SYSTICK_MS_STEP; - while (0 != (n--)) - { - nrfx_systick_delay_ticks(nrfx_systick_ms_tick(NRFX_SYSTICK_MS_STEP)); - } - nrfx_systick_delay_ticks(nrfx_systick_ms_tick(r)); -} - -#endif // NRFX_CHECK(NRFX_SYSTICK_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_timer.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_timer.c deleted file mode 100644 index c8bd6d23dc..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_timer.c +++ /dev/null @@ -1,330 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include - -#if NRFX_CHECK(NRFX_TIMER_ENABLED) - -#if !(NRFX_CHECK(NRFX_TIMER0_ENABLED) || NRFX_CHECK(NRFX_TIMER1_ENABLED) || \ - NRFX_CHECK(NRFX_TIMER2_ENABLED) || NRFX_CHECK(NRFX_TIMER3_ENABLED) || \ - NRFX_CHECK(NRFX_TIMER4_ENABLED)) -#error "No enabled TIMER instances. Check ." -#endif - -#include - -#define NRFX_LOG_MODULE TIMER -#include - -/**@brief Timer control block. */ -typedef struct -{ - nrfx_timer_event_handler_t handler; - void * context; - nrfx_drv_state_t state; -} timer_control_block_t; - -static timer_control_block_t m_cb[NRFX_TIMER_ENABLED_COUNT]; - -nrfx_err_t nrfx_timer_init(nrfx_timer_t const * const p_instance, - nrfx_timer_config_t const * p_config, - nrfx_timer_event_handler_t timer_event_handler) -{ - timer_control_block_t * p_cb = &m_cb[p_instance->instance_id]; -#ifdef SOFTDEVICE_PRESENT - NRFX_ASSERT(p_instance->p_reg != NRF_TIMER0); -#endif - NRFX_ASSERT(p_config); - NRFX_ASSERT(timer_event_handler); - - nrfx_err_t err_code; - - if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED) - { - err_code = NRFX_ERROR_INVALID_STATE; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - /* Warning 685: Relational operator '<=' always evaluates to 'true'" - * Warning in NRF_TIMER_IS_BIT_WIDTH_VALID macro. Macro validate timers resolution. - * Not necessary in nRF52 based systems. Obligatory in nRF51 based systems. - */ - - /*lint -save -e685 */ - - NRFX_ASSERT(NRF_TIMER_IS_BIT_WIDTH_VALID(p_instance->p_reg, p_config->bit_width)); - - //lint -restore - - p_cb->handler = timer_event_handler; - p_cb->context = p_config->p_context; - - uint8_t i; - for (i = 0; i < p_instance->cc_channel_count; ++i) - { - nrf_timer_event_clear(p_instance->p_reg, - nrf_timer_compare_event_get(i)); - } - - NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_instance->p_reg), - p_config->interrupt_priority); - NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_instance->p_reg)); - - nrf_timer_mode_set(p_instance->p_reg, p_config->mode); - nrf_timer_bit_width_set(p_instance->p_reg, p_config->bit_width); - nrf_timer_frequency_set(p_instance->p_reg, p_config->frequency); - - p_cb->state = NRFX_DRV_STATE_INITIALIZED; - - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -void nrfx_timer_uninit(nrfx_timer_t const * const p_instance) -{ - NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_instance->p_reg)); - - #define DISABLE_ALL UINT32_MAX - nrf_timer_shorts_disable(p_instance->p_reg, DISABLE_ALL); - nrf_timer_int_disable(p_instance->p_reg, DISABLE_ALL); - #undef DISABLE_ALL - - nrfx_timer_disable(p_instance); - - m_cb[p_instance->instance_id].state = NRFX_DRV_STATE_UNINITIALIZED; - NRFX_LOG_INFO("Uninitialized instance: %d.", p_instance->instance_id); -} - -void nrfx_timer_enable(nrfx_timer_t const * const p_instance) -{ - NRFX_ASSERT(m_cb[p_instance->instance_id].state == NRFX_DRV_STATE_INITIALIZED); - nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_START); - m_cb[p_instance->instance_id].state = NRFX_DRV_STATE_POWERED_ON; - NRFX_LOG_INFO("Enabled instance: %d.", p_instance->instance_id); -} - -void nrfx_timer_disable(nrfx_timer_t const * const p_instance) -{ - NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); - nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_SHUTDOWN); - m_cb[p_instance->instance_id].state = NRFX_DRV_STATE_INITIALIZED; - NRFX_LOG_INFO("Disabled instance: %d.", p_instance->instance_id); -} - -bool nrfx_timer_is_enabled(nrfx_timer_t const * const p_instance) -{ - NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); - return (m_cb[p_instance->instance_id].state == NRFX_DRV_STATE_POWERED_ON); -} - -void nrfx_timer_resume(nrfx_timer_t const * const p_instance) -{ - NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); - nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_START); - NRFX_LOG_INFO("Resumed instance: %d.", p_instance->instance_id); -} - -void nrfx_timer_pause(nrfx_timer_t const * const p_instance) -{ - NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); - nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_STOP); - NRFX_LOG_INFO("Paused instance: %d.", p_instance->instance_id); -} - -void nrfx_timer_clear(nrfx_timer_t const * const p_instance) -{ - NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); - nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_CLEAR); -} - -void nrfx_timer_increment(nrfx_timer_t const * const p_instance) -{ - NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); - NRFX_ASSERT(nrf_timer_mode_get(p_instance->p_reg) != NRF_TIMER_MODE_TIMER); - - nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_COUNT); -} - -uint32_t nrfx_timer_capture(nrfx_timer_t const * const p_instance, - nrf_timer_cc_channel_t cc_channel) -{ - NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); - NRFX_ASSERT(cc_channel < p_instance->cc_channel_count); - - nrf_timer_task_trigger(p_instance->p_reg, - nrf_timer_capture_task_get(cc_channel)); - return nrf_timer_cc_read(p_instance->p_reg, cc_channel); -} - -void nrfx_timer_compare(nrfx_timer_t const * const p_instance, - nrf_timer_cc_channel_t cc_channel, - uint32_t cc_value, - bool enable_int) -{ - nrf_timer_int_mask_t timer_int = nrf_timer_compare_int_get(cc_channel); - - if (enable_int) - { - nrf_timer_event_clear(p_instance->p_reg, nrf_timer_compare_event_get(cc_channel)); - nrf_timer_int_enable(p_instance->p_reg, timer_int); - } - else - { - nrf_timer_int_disable(p_instance->p_reg, timer_int); - } - - nrf_timer_cc_write(p_instance->p_reg, cc_channel, cc_value); - NRFX_LOG_INFO("Timer id: %d, capture value set: %lu, channel: %d.", - p_instance->instance_id, - cc_value, - cc_channel); -} - -void nrfx_timer_extended_compare(nrfx_timer_t const * const p_instance, - nrf_timer_cc_channel_t cc_channel, - uint32_t cc_value, - nrf_timer_short_mask_t timer_short_mask, - bool enable_int) -{ - nrf_timer_shorts_disable(p_instance->p_reg, - (TIMER_SHORTS_COMPARE0_STOP_Msk << cc_channel) | - (TIMER_SHORTS_COMPARE0_CLEAR_Msk << cc_channel)); - - nrf_timer_shorts_enable(p_instance->p_reg, timer_short_mask); - - nrfx_timer_compare(p_instance, - cc_channel, - cc_value, - enable_int); - NRFX_LOG_INFO("Timer id: %d, capture value set: %lu, channel: %d.", - p_instance->instance_id, - cc_value, - cc_channel); -} - -void nrfx_timer_compare_int_enable(nrfx_timer_t const * const p_instance, - uint32_t channel) -{ - NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); - NRFX_ASSERT(channel < p_instance->cc_channel_count); - - nrf_timer_event_clear(p_instance->p_reg, - nrf_timer_compare_event_get(channel)); - nrf_timer_int_enable(p_instance->p_reg, - nrf_timer_compare_int_get(channel)); -} - -void nrfx_timer_compare_int_disable(nrfx_timer_t const * const p_instance, - uint32_t channel) -{ - NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); - NRFX_ASSERT(channel < p_instance->cc_channel_count); - - nrf_timer_int_disable(p_instance->p_reg, - nrf_timer_compare_int_get(channel)); -} - -static void irq_handler(NRF_TIMER_Type * p_reg, - timer_control_block_t * p_cb, - uint8_t channel_count) -{ - uint8_t i; - for (i = 0; i < channel_count; ++i) - { - nrf_timer_event_t event = nrf_timer_compare_event_get(i); - nrf_timer_int_mask_t int_mask = nrf_timer_compare_int_get(i); - - if (nrf_timer_event_check(p_reg, event) && - nrf_timer_int_enable_check(p_reg, int_mask)) - { - nrf_timer_event_clear(p_reg, event); - NRFX_LOG_DEBUG("Compare event, channel: %d.", i); - p_cb->handler(event, p_cb->context); - } - } -} - -#if NRFX_CHECK(NRFX_TIMER0_ENABLED) -void nrfx_timer_0_irq_handler(void) -{ - irq_handler(NRF_TIMER0, &m_cb[NRFX_TIMER0_INST_IDX], - NRF_TIMER_CC_CHANNEL_COUNT(0)); -} -#endif - -#if NRFX_CHECK(NRFX_TIMER1_ENABLED) -void nrfx_timer_1_irq_handler(void) -{ - irq_handler(NRF_TIMER1, &m_cb[NRFX_TIMER1_INST_IDX], - NRF_TIMER_CC_CHANNEL_COUNT(1)); -} -#endif - -#if NRFX_CHECK(NRFX_TIMER2_ENABLED) -void nrfx_timer_2_irq_handler(void) -{ - irq_handler(NRF_TIMER2, &m_cb[NRFX_TIMER2_INST_IDX], - NRF_TIMER_CC_CHANNEL_COUNT(2)); -} -#endif - -#if NRFX_CHECK(NRFX_TIMER3_ENABLED) -void nrfx_timer_3_irq_handler(void) -{ - irq_handler(NRF_TIMER3, &m_cb[NRFX_TIMER3_INST_IDX], - NRF_TIMER_CC_CHANNEL_COUNT(3)); -} -#endif - -#if NRFX_CHECK(NRFX_TIMER4_ENABLED) -void nrfx_timer_4_irq_handler(void) -{ - irq_handler(NRF_TIMER4, &m_cb[NRFX_TIMER4_INST_IDX], - NRF_TIMER_CC_CHANNEL_COUNT(4)); -} -#endif - -#endif // NRFX_CHECK(NRFX_TIMER_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_twi.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_twi.c deleted file mode 100644 index 805d1d8403..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_twi.c +++ /dev/null @@ -1,723 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include - -#if NRFX_CHECK(NRFX_TWI_ENABLED) - -#if !(NRFX_CHECK(NRFX_TWI0_ENABLED) || NRFX_CHECK(NRFX_TWI1_ENABLED)) -#error "No enabled TWI instances. Check ." -#endif - -#include -#include -#include "prs/nrfx_prs.h" - -#define NRFX_LOG_MODULE TWI -#include - -#define EVT_TO_STR(event) \ - (event == NRFX_TWI_EVT_DONE ? "EVT_DONE" : \ - (event == NRFX_TWI_EVT_ADDRESS_NACK ? "EVT_ADDRESS_NACK" : \ - (event == NRFX_TWI_EVT_DATA_NACK ? "EVT_DATA_NACK" : \ - "UNKNOWN ERROR"))) - -#define EVT_TO_STR_TWI(event) \ - (event == NRF_TWI_EVENT_STOPPED ? "NRF_TWI_EVENT_STOPPED" : \ - (event == NRF_TWI_EVENT_RXDREADY ? "NRF_TWI_EVENT_RXDREADY" : \ - (event == NRF_TWI_EVENT_TXDSENT ? "NRF_TWI_EVENT_TXDSENT" : \ - (event == NRF_TWI_EVENT_ERROR ? "NRF_TWI_EVENT_ERROR" : \ - (event == NRF_TWI_EVENT_BB ? "NRF_TWI_EVENT_BB" : \ - (event == NRF_TWI_EVENT_SUSPENDED ? "NRF_TWI_EVENT_SUSPENDED" : \ - "UNKNOWN ERROR")))))) - -#define TRANSFER_TO_STR(type) \ - (type == NRFX_TWI_XFER_TX ? "XFER_TX" : \ - (type == NRFX_TWI_XFER_RX ? "XFER_RX" : \ - (type == NRFX_TWI_XFER_TXRX ? "XFER_TXRX" : \ - (type == NRFX_TWI_XFER_TXTX ? "XFER_TXTX" : \ - "UNKNOWN TRANSFER TYPE")))) - -#define TWI_PIN_INIT(_pin) nrf_gpio_cfg((_pin), \ - NRF_GPIO_PIN_DIR_INPUT, \ - NRF_GPIO_PIN_INPUT_CONNECT, \ - NRF_GPIO_PIN_PULLUP, \ - NRF_GPIO_PIN_S0D1, \ - NRF_GPIO_PIN_NOSENSE) - -#define HW_TIMEOUT 10000 - -// Control block - driver instance local data. -typedef struct -{ - nrfx_twi_evt_handler_t handler; - void * p_context; - volatile uint32_t int_mask; - nrfx_twi_xfer_desc_t xfer_desc; - uint32_t flags; - uint8_t * p_curr_buf; - uint8_t curr_length; - bool curr_no_stop; - nrfx_drv_state_t state; - bool error; - volatile bool busy; - bool repeated; - uint8_t bytes_transferred; - bool hold_bus_uninit; -} twi_control_block_t; - -static twi_control_block_t m_cb[NRFX_TWI_ENABLED_COUNT]; - -static nrfx_err_t twi_process_error(uint32_t errorsrc) -{ - nrfx_err_t ret = NRFX_ERROR_INTERNAL; - - if (errorsrc & NRF_TWI_ERROR_OVERRUN) - { - ret = NRFX_ERROR_DRV_TWI_ERR_OVERRUN; - } - - if (errorsrc & NRF_TWI_ERROR_ADDRESS_NACK) - { - ret = NRFX_ERROR_DRV_TWI_ERR_ANACK; - } - - if (errorsrc & NRF_TWI_ERROR_DATA_NACK) - { - ret = NRFX_ERROR_DRV_TWI_ERR_DNACK; - } - - return ret; -} - - - -nrfx_err_t nrfx_twi_init(nrfx_twi_t const * p_instance, - nrfx_twi_config_t const * p_config, - nrfx_twi_evt_handler_t event_handler, - void * p_context) -{ - NRFX_ASSERT(p_config); - NRFX_ASSERT(p_config->scl != p_config->sda); - twi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - nrfx_err_t err_code; - - if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED) - { - err_code = NRFX_ERROR_INVALID_STATE; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - -#if NRFX_CHECK(NRFX_PRS_ENABLED) - static nrfx_irq_handler_t const irq_handlers[NRFX_TWI_ENABLED_COUNT] = { - #if NRFX_CHECK(NRFX_TWI0_ENABLED) - nrfx_twi_0_irq_handler, - #endif - #if NRFX_CHECK(NRFX_TWI1_ENABLED) - nrfx_twi_1_irq_handler, - #endif - }; - if (nrfx_prs_acquire(p_instance->p_twi, - irq_handlers[p_instance->drv_inst_idx]) != NRFX_SUCCESS) - { - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } -#endif // NRFX_CHECK(NRFX_PRS_ENABLED) - - p_cb->handler = event_handler; - p_cb->p_context = p_context; - p_cb->int_mask = 0; - p_cb->repeated = false; - p_cb->busy = false; - p_cb->hold_bus_uninit = p_config->hold_bus_uninit; - - /* To secure correct signal levels on the pins used by the TWI - master when the system is in OFF mode, and when the TWI master is - disabled, these pins must be configured in the GPIO peripheral. - */ - TWI_PIN_INIT(p_config->scl); - TWI_PIN_INIT(p_config->sda); - - NRF_TWI_Type * p_twi = p_instance->p_twi; - nrf_twi_pins_set(p_twi, p_config->scl, p_config->sda); - nrf_twi_frequency_set(p_twi, - (nrf_twi_frequency_t)p_config->frequency); - - if (p_cb->handler) - { - NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_instance->p_twi), - p_config->interrupt_priority); - NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_instance->p_twi)); - } - - p_cb->state = NRFX_DRV_STATE_INITIALIZED; - - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -void nrfx_twi_uninit(nrfx_twi_t const * p_instance) -{ - twi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); - - if (p_cb->handler) - { - NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_instance->p_twi)); - } - nrfx_twi_disable(p_instance); - -#if NRFX_CHECK(NRFX_PRS_ENABLED) - nrfx_prs_release(p_instance->p_twi); -#endif - - if (!p_cb->hold_bus_uninit) - { - nrf_gpio_cfg_default(p_instance->p_twi->PSELSCL); - nrf_gpio_cfg_default(p_instance->p_twi->PSELSDA); - } - - p_cb->state = NRFX_DRV_STATE_UNINITIALIZED; - NRFX_LOG_INFO("Instance uninitialized: %d.", p_instance->drv_inst_idx); -} - -void nrfx_twi_enable(nrfx_twi_t const * p_instance) -{ - twi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - NRFX_ASSERT(p_cb->state == NRFX_DRV_STATE_INITIALIZED); - - NRF_TWI_Type * p_twi = p_instance->p_twi; - nrf_twi_enable(p_twi); - - p_cb->state = NRFX_DRV_STATE_POWERED_ON; - NRFX_LOG_INFO("Instance enabled: %d.", p_instance->drv_inst_idx); -} - -void nrfx_twi_disable(nrfx_twi_t const * p_instance) -{ - twi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); - - NRF_TWI_Type * p_twi = p_instance->p_twi; - nrf_twi_int_disable(p_twi, NRF_TWI_ALL_INTS_MASK); - nrf_twi_shorts_disable(p_twi, NRF_TWI_ALL_SHORTS_MASK); - nrf_twi_disable(p_twi); - - p_cb->state = NRFX_DRV_STATE_INITIALIZED; - NRFX_LOG_INFO("Instance disabled: %d.", p_instance->drv_inst_idx); -} - -static bool twi_send_byte(NRF_TWI_Type * p_twi, - uint8_t const * p_data, - uint8_t length, - uint8_t * p_bytes_transferred, - bool no_stop) -{ - if (*p_bytes_transferred < length) - { - nrf_twi_txd_set(p_twi, p_data[*p_bytes_transferred]); - ++(*p_bytes_transferred); - } - else - { - if (no_stop) - { - nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_SUSPEND); - return false; - } - else - { - nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STOP); - } - } - return true; -} - -static void twi_receive_byte(NRF_TWI_Type * p_twi, - uint8_t * p_data, - uint8_t length, - uint8_t * p_bytes_transferred) -{ - if (*p_bytes_transferred < length) - { - p_data[*p_bytes_transferred] = nrf_twi_rxd_get(p_twi); - - ++(*p_bytes_transferred); - - if (*p_bytes_transferred == length - 1) - { - nrf_twi_shorts_set(p_twi, NRF_TWI_SHORT_BB_STOP_MASK); - } - else if (*p_bytes_transferred == length) - { - return; - } - - nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_RESUME); - } -} - -static bool twi_transfer(NRF_TWI_Type * p_twi, - bool * p_error, - uint8_t * p_bytes_transferred, - uint8_t * p_data, - uint8_t length, - bool no_stop) -{ - bool do_stop_check = ((*p_error) || ((*p_bytes_transferred) == length)); - - if (*p_error) - { - nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_ERROR); - nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_TXDSENT); - nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_RXDREADY); - } - else if (nrf_twi_event_check(p_twi, NRF_TWI_EVENT_ERROR)) - { - nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_ERROR); - NRFX_LOG_DEBUG("TWI: Event: %s.", EVT_TO_STR_TWI(NRF_TWI_EVENT_ERROR)); - nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STOP); - *p_error = true; - } - else - { - if (nrf_twi_event_check(p_twi, NRF_TWI_EVENT_TXDSENT)) - { - nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_TXDSENT); - NRFX_LOG_DEBUG("TWI: Event: %s.", EVT_TO_STR_TWI(NRF_TWI_EVENT_TXDSENT)); - if (nrf_twi_event_check(p_twi, NRF_TWI_EVENT_ERROR)) - { - nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_ERROR); - NRFX_LOG_DEBUG("TWI: Event: %s.", EVT_TO_STR_TWI(NRF_TWI_EVENT_ERROR)); - nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STOP); - *p_error = true; - } - else - { - if (!twi_send_byte(p_twi, p_data, length, p_bytes_transferred, no_stop)) - { - return false; - } - } - } - else if (nrf_twi_event_check(p_twi, NRF_TWI_EVENT_RXDREADY)) - { - nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_RXDREADY); - NRFX_LOG_DEBUG("TWI: Event: %s.", EVT_TO_STR_TWI(NRF_TWI_EVENT_RXDREADY)); - if (nrf_twi_event_check(p_twi, NRF_TWI_EVENT_ERROR)) - { - NRFX_LOG_DEBUG("TWI: Event: %s.", EVT_TO_STR_TWI(NRF_TWI_EVENT_ERROR)); - nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_ERROR); - nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STOP); - *p_error = true; - } - else - { - twi_receive_byte(p_twi, p_data, length, p_bytes_transferred); - } - } - } - - if (do_stop_check && nrf_twi_event_check(p_twi, NRF_TWI_EVENT_STOPPED)) - { - nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_STOPPED); - NRFX_LOG_DEBUG("TWI: Event: %s.", EVT_TO_STR_TWI(NRF_TWI_EVENT_STOPPED)); - return false; - } - - return true; -} - -static nrfx_err_t twi_tx_start_transfer(twi_control_block_t * p_cb, - NRF_TWI_Type * p_twi, - uint8_t const * p_data, - uint8_t length, - bool no_stop) -{ - nrfx_err_t ret_code = NRFX_SUCCESS; - volatile int32_t hw_timeout; - - hw_timeout = HW_TIMEOUT; - - nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_STOPPED); - nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_ERROR); - nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_TXDSENT); - nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_RXDREADY); - nrf_twi_shorts_set(p_twi, 0); - - p_cb->bytes_transferred = 0; - p_cb->error = false; - - // In case TWI is suspended resume its operation. - nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_RESUME); - nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STARTTX); - - (void)twi_send_byte(p_twi, p_data, length, &p_cb->bytes_transferred, no_stop); - - if (p_cb->handler) - { - p_cb->int_mask = NRF_TWI_INT_STOPPED_MASK | - NRF_TWI_INT_ERROR_MASK | - NRF_TWI_INT_TXDSENT_MASK | - NRF_TWI_INT_RXDREADY_MASK; - nrf_twi_int_enable(p_twi, p_cb->int_mask); - } - else - { - while ((hw_timeout > 0) && - twi_transfer(p_twi, - &p_cb->error, - &p_cb->bytes_transferred, - (uint8_t *)p_data, - length, - no_stop)) - { - hw_timeout--; - } - - if (p_cb->error) - { - uint32_t errorsrc = nrf_twi_errorsrc_get_and_clear(p_twi); - - if (errorsrc) - { - ret_code = twi_process_error(errorsrc); - } - } - - if (hw_timeout <= 0) - { - nrf_twi_disable(p_twi); - nrf_twi_enable(p_twi); - ret_code = NRFX_ERROR_INTERNAL; - } - - } - return ret_code; -} - -static nrfx_err_t twi_rx_start_transfer(twi_control_block_t * p_cb, - NRF_TWI_Type * p_twi, - uint8_t const * p_data, - uint8_t length) -{ - nrfx_err_t ret_code = NRFX_SUCCESS; - volatile int32_t hw_timeout; - - hw_timeout = HW_TIMEOUT; - - nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_STOPPED); - nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_ERROR); - nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_TXDSENT); - nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_RXDREADY); - - p_cb->bytes_transferred = 0; - p_cb->error = false; - - if (length == 1) - { - nrf_twi_shorts_set(p_twi, NRF_TWI_SHORT_BB_STOP_MASK); - } - else - { - nrf_twi_shorts_set(p_twi, NRF_TWI_SHORT_BB_SUSPEND_MASK); - } - // In case TWI is suspended resume its operation. - nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_RESUME); - nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STARTRX); - - if (p_cb->handler) - { - p_cb->int_mask = NRF_TWI_INT_STOPPED_MASK | - NRF_TWI_INT_ERROR_MASK | - NRF_TWI_INT_TXDSENT_MASK | - NRF_TWI_INT_RXDREADY_MASK; - nrf_twi_int_enable(p_twi, p_cb->int_mask); - } - else - { - while ((hw_timeout > 0) && - twi_transfer(p_twi, - &p_cb->error, - &p_cb->bytes_transferred, - (uint8_t*)p_data, - length, - false)) - { - hw_timeout--; - } - - if (p_cb->error) - { - uint32_t errorsrc = nrf_twi_errorsrc_get_and_clear(p_twi); - - if (errorsrc) - { - ret_code = twi_process_error(errorsrc); - } - } - if (hw_timeout <= 0) - { - nrf_twi_disable(p_twi); - nrf_twi_enable(p_twi); - ret_code = NRFX_ERROR_INTERNAL; - } - } - return ret_code; -} - -__STATIC_INLINE nrfx_err_t twi_xfer(twi_control_block_t * p_cb, - NRF_TWI_Type * p_twi, - nrfx_twi_xfer_desc_t const * p_xfer_desc, - uint32_t flags) -{ - - nrfx_err_t err_code = NRFX_SUCCESS; - - /* Block TWI interrupts to ensure that function is not interrupted by TWI interrupt. */ - nrf_twi_int_disable(p_twi, NRF_TWI_ALL_INTS_MASK); - - if (p_cb->busy) - { - nrf_twi_int_enable(p_twi, p_cb->int_mask); - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - else - { - p_cb->busy = (NRFX_TWI_FLAG_NO_XFER_EVT_HANDLER & flags) ? false : true; - } - - p_cb->flags = flags; - p_cb->xfer_desc = *p_xfer_desc; - p_cb->curr_length = p_xfer_desc->primary_length; - p_cb->p_curr_buf = p_xfer_desc->p_primary_buf; - nrf_twi_address_set(p_twi, p_xfer_desc->address); - - if (p_xfer_desc->type != NRFX_TWI_XFER_RX) - { - p_cb->curr_no_stop = ((p_xfer_desc->type == NRFX_TWI_XFER_TX) && - !(flags & NRFX_TWI_FLAG_TX_NO_STOP)) ? false : true; - - err_code = twi_tx_start_transfer(p_cb, - p_twi, - p_xfer_desc->p_primary_buf, - p_xfer_desc->primary_length, - p_cb->curr_no_stop); - } - else - { - p_cb->curr_no_stop = false; - - err_code = twi_rx_start_transfer(p_cb, - p_twi, - p_xfer_desc->p_primary_buf, - p_xfer_desc->primary_length); - } - if (p_cb->handler == NULL) - { - p_cb->busy = false; - } - return err_code; -} - -bool nrfx_twi_is_busy(nrfx_twi_t const * p_instance) -{ - twi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - return p_cb->busy; -} - -nrfx_err_t nrfx_twi_xfer(nrfx_twi_t const * p_instance, - nrfx_twi_xfer_desc_t const * p_xfer_desc, - uint32_t flags) -{ - - nrfx_err_t err_code = NRFX_SUCCESS; - twi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - - // TXRX and TXTX transfers are supported only in non-blocking mode. - NRFX_ASSERT( !((p_cb->handler == NULL) && (p_xfer_desc->type == NRFX_TWI_XFER_TXRX))); - NRFX_ASSERT( !((p_cb->handler == NULL) && (p_xfer_desc->type == NRFX_TWI_XFER_TXTX))); - - NRFX_LOG_INFO("Transfer type: %s.", TRANSFER_TO_STR(p_xfer_desc->type)); - NRFX_LOG_INFO("Transfer buffers length: primary: %d, secondary: %d.", - p_xfer_desc->primary_length, - p_xfer_desc->secondary_length); - NRFX_LOG_DEBUG("Primary buffer data:"); - NRFX_LOG_HEXDUMP_DEBUG(p_xfer_desc->p_primary_buf, - p_xfer_desc->primary_length * sizeof(p_xfer_desc->p_primary_buf[0])); - NRFX_LOG_DEBUG("Secondary buffer data:"); - NRFX_LOG_HEXDUMP_DEBUG(p_xfer_desc->p_secondary_buf, - p_xfer_desc->secondary_length * sizeof(p_xfer_desc->p_secondary_buf[0])); - - err_code = twi_xfer(p_cb, (NRF_TWI_Type *)p_instance->p_twi, p_xfer_desc, flags); - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -nrfx_err_t nrfx_twi_tx(nrfx_twi_t const * p_instance, - uint8_t address, - uint8_t const * p_data, - size_t length, - bool no_stop) -{ - nrfx_twi_xfer_desc_t xfer = NRFX_TWI_XFER_DESC_TX(address, (uint8_t*)p_data, length); - - return nrfx_twi_xfer(p_instance, &xfer, no_stop ? NRFX_TWI_FLAG_TX_NO_STOP : 0); -} - -nrfx_err_t nrfx_twi_rx(nrfx_twi_t const * p_instance, - uint8_t address, - uint8_t * p_data, - size_t length) -{ - nrfx_twi_xfer_desc_t xfer = NRFX_TWI_XFER_DESC_RX(address, p_data, length); - return nrfx_twi_xfer(p_instance, &xfer, 0); -} - -size_t nrfx_twi_data_count_get(nrfx_twi_t const * const p_instance) -{ - return m_cb[p_instance->drv_inst_idx].bytes_transferred; -} - -uint32_t nrfx_twi_stopped_event_get(nrfx_twi_t const * p_instance) -{ - return (uint32_t)nrf_twi_event_address_get(p_instance->p_twi, NRF_TWI_EVENT_STOPPED); -} - -static void twi_irq_handler(NRF_TWI_Type * p_twi, twi_control_block_t * p_cb) -{ - NRFX_ASSERT(p_cb->handler); - - if (twi_transfer(p_twi, - &p_cb->error, - &p_cb->bytes_transferred, - p_cb->p_curr_buf, - p_cb->curr_length, - p_cb->curr_no_stop )) - { - return; - } - - if (!p_cb->error && - ((p_cb->xfer_desc.type == NRFX_TWI_XFER_TXRX) || - (p_cb->xfer_desc.type == NRFX_TWI_XFER_TXTX)) && - p_cb->p_curr_buf == p_cb->xfer_desc.p_primary_buf) - { - p_cb->p_curr_buf = p_cb->xfer_desc.p_secondary_buf; - p_cb->curr_length = p_cb->xfer_desc.secondary_length; - p_cb->curr_no_stop = (p_cb->flags & NRFX_TWI_FLAG_TX_NO_STOP); - - if (p_cb->xfer_desc.type == NRFX_TWI_XFER_TXTX) - { - (void)twi_tx_start_transfer(p_cb, - p_twi, - p_cb->p_curr_buf, - p_cb->curr_length, - p_cb->curr_no_stop); - } - else - { - (void)twi_rx_start_transfer(p_cb, p_twi, p_cb->p_curr_buf, p_cb->curr_length); - } - } - else - { - nrfx_twi_evt_t event; - event.xfer_desc = p_cb->xfer_desc; - - if (p_cb->error) - { - uint32_t errorsrc = nrf_twi_errorsrc_get_and_clear(p_twi); - if (errorsrc & NRF_TWI_ERROR_ADDRESS_NACK) - { - event.type = NRFX_TWI_EVT_ADDRESS_NACK; - NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRFX_TWI_EVT_ADDRESS_NACK)); - } - else if (errorsrc & NRF_TWI_ERROR_DATA_NACK) - { - event.type = NRFX_TWI_EVT_DATA_NACK; - NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRFX_TWI_EVT_DATA_NACK)); - } - } - else - { - event.type = NRFX_TWI_EVT_DONE; - NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRFX_TWI_EVT_DONE)); - } - - p_cb->busy = false; - - if (!(NRFX_TWI_FLAG_NO_XFER_EVT_HANDLER & p_cb->flags)) - { - p_cb->handler(&event, p_cb->p_context); - } - } - -} - -#if NRFX_CHECK(NRFX_TWI0_ENABLED) -void nrfx_twi_0_irq_handler(void) -{ - twi_irq_handler(NRF_TWI0, &m_cb[NRFX_TWI0_INST_IDX]); -} -#endif - -#if NRFX_CHECK(NRFX_TWI1_ENABLED) -void nrfx_twi_1_irq_handler(void) -{ - twi_irq_handler(NRF_TWI1, &m_cb[NRFX_TWI1_INST_IDX]); -} -#endif - -#endif // NRFX_CHECK(NRFX_TWI_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_twim.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_twim.c deleted file mode 100644 index c767394eae..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_twim.c +++ /dev/null @@ -1,664 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include - -#if NRFX_CHECK(NRFX_TWIM_ENABLED) - -#if !(NRFX_CHECK(NRFX_TWIM0_ENABLED) || NRFX_CHECK(NRFX_TWIM1_ENABLED)) -#error "No enabled TWIM instances. Check ." -#endif - -#include -#include -#include "prs/nrfx_prs.h" - -#define NRFX_LOG_MODULE TWIM -#include - -#define EVT_TO_STR(event) \ - (event == NRFX_TWIM_EVT_DONE ? "EVT_DONE" : \ - (event == NRFX_TWIM_EVT_ADDRESS_NACK ? "EVT_ADDRESS_NACK" : \ - (event == NRFX_TWIM_EVT_DATA_NACK ? "EVT_DATA_NACK" : \ - "UNKNOWN ERROR"))) - -#define EVT_TO_STR_TWIM(event) \ - (event == NRF_TWIM_EVENT_STOPPED ? "NRF_TWIM_EVENT_STOPPED" : \ - (event == NRF_TWIM_EVENT_ERROR ? "NRF_TWIM_EVENT_ERROR" : \ - (event == NRF_TWIM_EVENT_SUSPENDED ? "NRF_TWIM_EVENT_SUSPENDED" : \ - (event == NRF_TWIM_EVENT_RXSTARTED ? "NRF_TWIM_EVENT_RXSTARTED" : \ - (event == NRF_TWIM_EVENT_TXSTARTED ? "NRF_TWIM_EVENT_TXSTARTED" : \ - (event == NRF_TWIM_EVENT_LASTRX ? "NRF_TWIM_EVENT_LASTRX" : \ - (event == NRF_TWIM_EVENT_LASTTX ? "NRF_TWIM_EVENT_LASTTX" : \ - "UNKNOWN ERROR"))))))) - -#define TRANSFER_TO_STR(type) \ - (type == NRFX_TWIM_XFER_TX ? "XFER_TX" : \ - (type == NRFX_TWIM_XFER_RX ? "XFER_RX" : \ - (type == NRFX_TWIM_XFER_TXRX ? "XFER_TXRX" : \ - (type == NRFX_TWIM_XFER_TXTX ? "XFER_TXTX" : \ - "UNKNOWN TRANSFER TYPE")))) - -#define TWIM_PIN_INIT(_pin) nrf_gpio_cfg((_pin), \ - NRF_GPIO_PIN_DIR_INPUT, \ - NRF_GPIO_PIN_INPUT_CONNECT, \ - NRF_GPIO_PIN_PULLUP, \ - NRF_GPIO_PIN_S0D1, \ - NRF_GPIO_PIN_NOSENSE) - -#define TWIMX_LENGTH_VALIDATE(peripheral, drv_inst_idx, len1, len2) \ - (((drv_inst_idx) == NRFX_CONCAT_3(NRFX_, peripheral, _INST_IDX)) && \ - NRFX_EASYDMA_LENGTH_VALIDATE(peripheral, len1, len2)) - -#if NRFX_CHECK(NRFX_TWIM0_ENABLED) -#define TWIM0_LENGTH_VALIDATE(...) TWIMX_LENGTH_VALIDATE(TWIM0, __VA_ARGS__) -#else -#define TWIM0_LENGTH_VALIDATE(...) 0 -#endif - -#if NRFX_CHECK(NRFX_TWIM1_ENABLED) -#define TWIM1_LENGTH_VALIDATE(...) TWIMX_LENGTH_VALIDATE(TWIM1, __VA_ARGS__) -#else -#define TWIM1_LENGTH_VALIDATE(...) 0 -#endif - -#define TWIM_LENGTH_VALIDATE(drv_inst_idx, len1, len2) \ - (TWIM0_LENGTH_VALIDATE(drv_inst_idx, len1, len2) || \ - TWIM1_LENGTH_VALIDATE(drv_inst_idx, len1, len2)) - -// Control block - driver instance local data. -typedef struct -{ - nrfx_twim_evt_handler_t handler; - void * p_context; - volatile uint32_t int_mask; - nrfx_twim_xfer_desc_t xfer_desc; - uint32_t flags; - uint8_t * p_curr_buf; - size_t curr_length; - bool curr_no_stop; - nrfx_drv_state_t state; - bool error; - volatile bool busy; - bool repeated; - uint8_t bytes_transferred; - bool hold_bus_uninit; -#if NRFX_CHECK(NRFX_TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED) - nrf_twim_frequency_t bus_frequency; -#endif -} twim_control_block_t; - -static twim_control_block_t m_cb[NRFX_TWIM_ENABLED_COUNT]; - -static nrfx_err_t twi_process_error(uint32_t errorsrc) -{ - nrfx_err_t ret = NRFX_ERROR_INTERNAL; - - if (errorsrc & NRF_TWIM_ERROR_ADDRESS_NACK) - { - ret = NRFX_ERROR_DRV_TWI_ERR_ANACK; - } - - if (errorsrc & NRF_TWIM_ERROR_DATA_NACK) - { - ret = NRFX_ERROR_DRV_TWI_ERR_DNACK; - } - - return ret; -} - -nrfx_err_t nrfx_twim_init(nrfx_twim_t const * p_instance, - nrfx_twim_config_t const * p_config, - nrfx_twim_evt_handler_t event_handler, - void * p_context) -{ - NRFX_ASSERT(p_config); - NRFX_ASSERT(p_config->scl != p_config->sda); - twim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - nrfx_err_t err_code; - - if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED) - { - err_code = NRFX_ERROR_INVALID_STATE; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - -#if NRFX_CHECK(NRFX_PRS_ENABLED) - static nrfx_irq_handler_t const irq_handlers[NRFX_TWIM_ENABLED_COUNT] = { - #if NRFX_CHECK(NRFX_TWIM0_ENABLED) - nrfx_twim_0_irq_handler, - #endif - #if NRFX_CHECK(NRFX_TWIM1_ENABLED) - nrfx_twim_1_irq_handler, - #endif - }; - if (nrfx_prs_acquire(p_instance->p_twim, - irq_handlers[p_instance->drv_inst_idx]) != NRFX_SUCCESS) - { - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } -#endif // NRFX_CHECK(NRFX_PRS_ENABLED) - - p_cb->handler = event_handler; - p_cb->p_context = p_context; - p_cb->int_mask = 0; - p_cb->repeated = false; - p_cb->busy = false; - p_cb->hold_bus_uninit = p_config->hold_bus_uninit; -#if NRFX_CHECK(NRFX_TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED) - p_cb->bus_frequency = (nrf_twim_frequency_t)p_config->frequency; -#endif - - /* To secure correct signal levels on the pins used by the TWI - master when the system is in OFF mode, and when the TWI master is - disabled, these pins must be configured in the GPIO peripheral. - */ - TWIM_PIN_INIT(p_config->scl); - TWIM_PIN_INIT(p_config->sda); - - NRF_TWIM_Type * p_twim = p_instance->p_twim; - nrf_twim_pins_set(p_twim, p_config->scl, p_config->sda); - nrf_twim_frequency_set(p_twim, - (nrf_twim_frequency_t)p_config->frequency); - - if (p_cb->handler) - { - NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_instance->p_twim), - p_config->interrupt_priority); - NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_instance->p_twim)); - } - - p_cb->state = NRFX_DRV_STATE_INITIALIZED; - - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -void nrfx_twim_uninit(nrfx_twim_t const * p_instance) -{ - twim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); - - if (p_cb->handler) - { - NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_instance->p_twim)); - } - nrfx_twim_disable(p_instance); - -#if NRFX_CHECK(NRFX_PRS_ENABLED) - nrfx_prs_release(p_instance->p_twim); -#endif - - if (!p_cb->hold_bus_uninit) - { - nrf_gpio_cfg_default(p_instance->p_twim->PSEL.SCL); - nrf_gpio_cfg_default(p_instance->p_twim->PSEL.SDA); - } - - p_cb->state = NRFX_DRV_STATE_UNINITIALIZED; - NRFX_LOG_INFO("Instance uninitialized: %d.", p_instance->drv_inst_idx); -} - -void nrfx_twim_enable(nrfx_twim_t const * p_instance) -{ - twim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - NRFX_ASSERT(p_cb->state == NRFX_DRV_STATE_INITIALIZED); - - nrf_twim_enable(p_instance->p_twim); - - p_cb->state = NRFX_DRV_STATE_POWERED_ON; - NRFX_LOG_INFO("Instance enabled: %d.", p_instance->drv_inst_idx); -} - -void nrfx_twim_disable(nrfx_twim_t const * p_instance) -{ - twim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); - - NRF_TWIM_Type * p_twim = p_instance->p_twim; - p_cb->int_mask = 0; - nrf_twim_int_disable(p_twim, NRF_TWIM_ALL_INTS_MASK); - nrf_twim_shorts_disable(p_twim, NRF_TWIM_ALL_SHORTS_MASK); - nrf_twim_disable(p_twim); - - p_cb->state = NRFX_DRV_STATE_INITIALIZED; - NRFX_LOG_INFO("Instance disabled: %d.", p_instance->drv_inst_idx); -} - - -bool nrfx_twim_is_busy(nrfx_twim_t const * p_instance) -{ - twim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - return p_cb->busy; -} - - -__STATIC_INLINE void twim_list_enable_handle(NRF_TWIM_Type * p_twim, uint32_t flags) -{ - if (NRFX_TWIM_FLAG_TX_POSTINC & flags) - { - nrf_twim_tx_list_enable(p_twim); - } - else - { - nrf_twim_tx_list_disable(p_twim); - } - - if (NRFX_TWIM_FLAG_RX_POSTINC & flags) - { - nrf_twim_rx_list_enable(p_twim); - } - else - { - nrf_twim_rx_list_disable(p_twim); - } -} -__STATIC_INLINE nrfx_err_t twim_xfer(twim_control_block_t * p_cb, - NRF_TWIM_Type * p_twim, - nrfx_twim_xfer_desc_t const * p_xfer_desc, - uint32_t flags) -{ - nrfx_err_t err_code = NRFX_SUCCESS; - nrf_twim_task_t start_task = NRF_TWIM_TASK_STARTTX; - nrf_twim_event_t evt_to_wait = NRF_TWIM_EVENT_STOPPED; - - if (!nrfx_is_in_ram(p_xfer_desc->p_primary_buf)) - { - err_code = NRFX_ERROR_INVALID_ADDR; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - /* Block TWI interrupts to ensure that function is not interrupted by TWI interrupt. */ - nrf_twim_int_disable(p_twim, NRF_TWIM_ALL_INTS_MASK); - if (p_cb->busy) - { - nrf_twim_int_enable(p_twim, p_cb->int_mask); - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - else - { - p_cb->busy = ((NRFX_TWIM_FLAG_NO_XFER_EVT_HANDLER & flags) || - (NRFX_TWIM_FLAG_REPEATED_XFER & flags)) ? false: true; - } - - p_cb->xfer_desc = *p_xfer_desc; - p_cb->repeated = (flags & NRFX_TWIM_FLAG_REPEATED_XFER) ? true : false; - nrf_twim_address_set(p_twim, p_xfer_desc->address); - - nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_STOPPED); - nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_ERROR); - - twim_list_enable_handle(p_twim, flags); - switch (p_xfer_desc->type) - { - case NRFX_TWIM_XFER_TXTX: - NRFX_ASSERT(!(flags & NRFX_TWIM_FLAG_REPEATED_XFER)); - NRFX_ASSERT(!(flags & NRFX_TWIM_FLAG_HOLD_XFER)); - NRFX_ASSERT(!(flags & NRFX_TWIM_FLAG_NO_XFER_EVT_HANDLER)); - if (!nrfx_is_in_ram(p_xfer_desc->p_secondary_buf)) - { - err_code = NRFX_ERROR_INVALID_ADDR; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - nrf_twim_shorts_set(p_twim, NRF_TWIM_SHORT_LASTTX_SUSPEND_MASK); - nrf_twim_tx_buffer_set(p_twim, p_xfer_desc->p_primary_buf, p_xfer_desc->primary_length); - nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_TXSTARTED); - nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_LASTTX); - nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_SUSPENDED); - nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME); - nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_STARTTX); - while (!nrf_twim_event_check(p_twim, NRF_TWIM_EVENT_TXSTARTED)) - {} - NRFX_LOG_DEBUG("TWIM: Event: %s.", EVT_TO_STR_TWIM(NRF_TWIM_EVENT_TXSTARTED)); - nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_TXSTARTED); - nrf_twim_tx_buffer_set(p_twim, p_xfer_desc->p_secondary_buf, p_xfer_desc->secondary_length); - p_cb->int_mask = NRF_TWIM_INT_SUSPENDED_MASK | NRF_TWIM_INT_ERROR_MASK; - break; - case NRFX_TWIM_XFER_TXRX: - nrf_twim_tx_buffer_set(p_twim, p_xfer_desc->p_primary_buf, p_xfer_desc->primary_length); - if (!nrfx_is_in_ram(p_xfer_desc->p_secondary_buf)) - { - err_code = NRFX_ERROR_INVALID_ADDR; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - nrf_twim_rx_buffer_set(p_twim, p_xfer_desc->p_secondary_buf, p_xfer_desc->secondary_length); - nrf_twim_shorts_set(p_twim, NRF_TWIM_SHORT_LASTTX_STARTRX_MASK | - NRF_TWIM_SHORT_LASTRX_STOP_MASK); - p_cb->int_mask = NRF_TWIM_INT_STOPPED_MASK | NRF_TWIM_INT_ERROR_MASK; - break; - case NRFX_TWIM_XFER_TX: - nrf_twim_tx_buffer_set(p_twim, p_xfer_desc->p_primary_buf, p_xfer_desc->primary_length); - if (NRFX_TWIM_FLAG_TX_NO_STOP & flags) - { - nrf_twim_shorts_set(p_twim, NRF_TWIM_SHORT_LASTTX_SUSPEND_MASK); - p_cb->int_mask = NRF_TWIM_INT_SUSPENDED_MASK | NRF_TWIM_INT_ERROR_MASK; - nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_SUSPENDED); - evt_to_wait = NRF_TWIM_EVENT_SUSPENDED; - } - else - { - nrf_twim_shorts_set(p_twim, NRF_TWIM_SHORT_LASTTX_STOP_MASK); - p_cb->int_mask = NRF_TWIM_INT_STOPPED_MASK | NRF_TWIM_INT_ERROR_MASK; - } - nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME); - break; - case NRFX_TWIM_XFER_RX: - nrf_twim_rx_buffer_set(p_twim, p_xfer_desc->p_primary_buf, p_xfer_desc->primary_length); - nrf_twim_shorts_set(p_twim, NRF_TWIM_SHORT_LASTRX_STOP_MASK); - p_cb->int_mask = NRF_TWIM_INT_STOPPED_MASK | NRF_TWIM_INT_ERROR_MASK; - start_task = NRF_TWIM_TASK_STARTRX; - nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME); - break; - default: - err_code = NRFX_ERROR_INVALID_PARAM; - break; - } - - if (!(flags & NRFX_TWIM_FLAG_HOLD_XFER) && (p_xfer_desc->type != NRFX_TWIM_XFER_TXTX)) - { - nrf_twim_task_trigger(p_twim, start_task); - } - - if (p_cb->handler) - { - if (flags & NRFX_TWIM_FLAG_NO_XFER_EVT_HANDLER) - { - p_cb->int_mask = NRF_TWIM_INT_ERROR_MASK; - } - nrf_twim_int_enable(p_twim, p_cb->int_mask); - -#if NRFX_CHECK(NRFX_TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED) - if ((flags & NRFX_TWIM_FLAG_HOLD_XFER) && ((p_xfer_desc->type == NRFX_TWIM_XFER_TX) || - (p_xfer_desc->type == NRFX_TWIM_XFER_TXRX))) - { - p_cb->flags = flags; - twim_list_enable_handle(p_twim, 0); - p_twim->FREQUENCY = 0; - nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_TXSTARTED); - nrf_twim_int_enable(p_twim, NRF_TWIM_INT_TXSTARTED_MASK); - } -#endif - } - else - { - while (!nrf_twim_event_check(p_twim, evt_to_wait)) - { - if (nrf_twim_event_check(p_twim, NRF_TWIM_EVENT_ERROR)) - { - NRFX_LOG_DEBUG("TWIM: Event: %s.", EVT_TO_STR_TWIM(NRF_TWIM_EVENT_ERROR)); - nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_ERROR); - nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME); - nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_STOP); - evt_to_wait = NRF_TWIM_EVENT_STOPPED; - } - } - - uint32_t errorsrc = nrf_twim_errorsrc_get_and_clear(p_twim); - - p_cb->busy = false; - - if (errorsrc) - { - err_code = twi_process_error(errorsrc); - } - } - return err_code; -} - - -nrfx_err_t nrfx_twim_xfer(nrfx_twim_t const * p_instance, - nrfx_twim_xfer_desc_t const * p_xfer_desc, - uint32_t flags) -{ - NRFX_ASSERT(TWIM_LENGTH_VALIDATE(p_instance->drv_inst_idx, - p_xfer_desc->primary_length, - p_xfer_desc->secondary_length)); - - nrfx_err_t err_code = NRFX_SUCCESS; - twim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - - // TXRX and TXTX transfers are supported only in non-blocking mode. - NRFX_ASSERT( !((p_cb->handler == NULL) && (p_xfer_desc->type == NRFX_TWIM_XFER_TXRX))); - NRFX_ASSERT( !((p_cb->handler == NULL) && (p_xfer_desc->type == NRFX_TWIM_XFER_TXTX))); - - NRFX_LOG_INFO("Transfer type: %s.", TRANSFER_TO_STR(p_xfer_desc->type)); - NRFX_LOG_INFO("Transfer buffers length: primary: %d, secondary: %d.", - p_xfer_desc->primary_length, - p_xfer_desc->secondary_length); - NRFX_LOG_DEBUG("Primary buffer data:"); - NRFX_LOG_HEXDUMP_DEBUG(p_xfer_desc->p_primary_buf, - p_xfer_desc->primary_length * sizeof(p_xfer_desc->p_primary_buf[0])); - NRFX_LOG_DEBUG("Secondary buffer data:"); - NRFX_LOG_HEXDUMP_DEBUG(p_xfer_desc->p_secondary_buf, - p_xfer_desc->secondary_length * sizeof(p_xfer_desc->p_secondary_buf[0])); - - err_code = twim_xfer(p_cb, (NRF_TWIM_Type *)p_instance->p_twim, p_xfer_desc, flags); - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -nrfx_err_t nrfx_twim_tx(nrfx_twim_t const * p_instance, - uint8_t address, - uint8_t const * p_data, - size_t length, - bool no_stop) -{ - nrfx_twim_xfer_desc_t xfer = NRFX_TWIM_XFER_DESC_TX(address, (uint8_t*)p_data, length); - - return nrfx_twim_xfer(p_instance, &xfer, no_stop ? NRFX_TWIM_FLAG_TX_NO_STOP : 0); -} - -nrfx_err_t nrfx_twim_rx(nrfx_twim_t const * p_instance, - uint8_t address, - uint8_t * p_data, - size_t length) -{ - nrfx_twim_xfer_desc_t xfer = NRFX_TWIM_XFER_DESC_RX(address, p_data, length); - return nrfx_twim_xfer(p_instance, &xfer, 0); -} - -uint32_t nrfx_twim_start_task_get(nrfx_twim_t const * p_instance, - nrfx_twim_xfer_type_t xfer_type) -{ - return (uint32_t)nrf_twim_task_address_get(p_instance->p_twim, - (xfer_type != NRFX_TWIM_XFER_RX) ? NRF_TWIM_TASK_STARTTX : NRF_TWIM_TASK_STARTRX); -} - -uint32_t nrfx_twim_stopped_event_get(nrfx_twim_t const * p_instance) -{ - return (uint32_t)nrf_twim_event_address_get(p_instance->p_twim, NRF_TWIM_EVENT_STOPPED); -} - -static void twim_irq_handler(NRF_TWIM_Type * p_twim, twim_control_block_t * p_cb) -{ - -#if NRFX_CHECK(NRFX_TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED) - /* Handle only workaround case. Can be used without TWIM handler in IRQs. */ - if (nrf_twim_event_check(p_twim, NRF_TWIM_EVENT_TXSTARTED)) - { - nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_TXSTARTED); - nrf_twim_int_disable(p_twim, NRF_TWIM_INT_TXSTARTED_MASK); - if (p_twim->FREQUENCY == 0) - { - // Set enable to zero to reset TWIM internal state. - nrf_twim_disable(p_twim); - nrf_twim_enable(p_twim); - - // Set proper frequency. - nrf_twim_frequency_set(p_twim, p_cb->bus_frequency); - twim_list_enable_handle(p_twim, p_cb->flags); - - // Start proper transmission. - nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_STARTTX); - return; - } - } -#endif - - NRFX_ASSERT(p_cb->handler); - - if (nrf_twim_event_check(p_twim, NRF_TWIM_EVENT_ERROR)) - { - nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_ERROR); - NRFX_LOG_DEBUG("TWIM: Event: %s.", EVT_TO_STR_TWIM(NRF_TWIM_EVENT_ERROR)); - if (!nrf_twim_event_check(p_twim, NRF_TWIM_EVENT_STOPPED)) - { - nrf_twim_int_disable(p_twim, p_cb->int_mask); - p_cb->int_mask = NRF_TWIM_INT_STOPPED_MASK; - nrf_twim_int_enable(p_twim, p_cb->int_mask); - - nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME); - nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_STOP); - return; - } - } - - nrfx_twim_evt_t event; - - if (nrf_twim_event_check(p_twim, NRF_TWIM_EVENT_STOPPED)) - { - NRFX_LOG_DEBUG("TWIM: Event: %s.", EVT_TO_STR_TWIM(NRF_TWIM_EVENT_STOPPED)); - nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_STOPPED); - event.xfer_desc = p_cb->xfer_desc; - if (p_cb->error) - { - - event.xfer_desc.primary_length = (p_cb->xfer_desc.type == NRFX_TWIM_XFER_RX) ? - nrf_twim_rxd_amount_get(p_twim) : nrf_twim_txd_amount_get(p_twim); - event.xfer_desc.secondary_length = (p_cb->xfer_desc.type == NRFX_TWIM_XFER_TXRX) ? - nrf_twim_rxd_amount_get(p_twim) : nrf_twim_txd_amount_get(p_twim); - - } - nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_LASTTX); - nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_LASTRX); - if (!p_cb->repeated || p_cb->error) - { - nrf_twim_shorts_set(p_twim, 0); - p_cb->int_mask = 0; - nrf_twim_int_disable(p_twim, NRF_TWIM_ALL_INTS_MASK); - } - } - else - { - nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_SUSPENDED); - NRFX_LOG_DEBUG("TWIM: Event: %s.", EVT_TO_STR_TWIM(NRF_TWIM_EVENT_SUSPENDED)); - if (p_cb->xfer_desc.type == NRFX_TWIM_XFER_TX) - { - event.xfer_desc = p_cb->xfer_desc; - if (!p_cb->repeated) - { - nrf_twim_shorts_set(p_twim, 0); - p_cb->int_mask = 0; - nrf_twim_int_disable(p_twim, NRF_TWIM_ALL_INTS_MASK); - } - } - else - { - nrf_twim_shorts_set(p_twim, NRF_TWIM_SHORT_LASTTX_STOP_MASK); - p_cb->int_mask = NRF_TWIM_INT_STOPPED_MASK | NRF_TWIM_INT_ERROR_MASK; - nrf_twim_int_disable(p_twim, NRF_TWIM_ALL_INTS_MASK); - nrf_twim_int_enable(p_twim, p_cb->int_mask); - nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_STARTTX); - nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME); - return; - } - } - - uint32_t errorsrc = nrf_twim_errorsrc_get_and_clear(p_twim); - if (errorsrc & NRF_TWIM_ERROR_ADDRESS_NACK) - { - event.type = NRFX_TWIM_EVT_ADDRESS_NACK; - NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRFX_TWIM_EVT_ADDRESS_NACK)); - } - else if (errorsrc & NRF_TWIM_ERROR_DATA_NACK) - { - event.type = NRFX_TWIM_EVT_DATA_NACK; - NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRFX_TWIM_EVT_DATA_NACK)); - } - else - { - event.type = NRFX_TWIM_EVT_DONE; - NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRFX_TWIM_EVT_DONE)); - } - - if (!p_cb->repeated) - { - p_cb->busy = false; - } - p_cb->handler(&event, p_cb->p_context); -} - -#if NRFX_CHECK(NRFX_TWIM0_ENABLED) -void nrfx_twim_0_irq_handler(void) -{ - twim_irq_handler(NRF_TWIM0, &m_cb[NRFX_TWIM0_INST_IDX]); -} -#endif - -#if NRFX_CHECK(NRFX_TWIM1_ENABLED) -void nrfx_twim_1_irq_handler(void) -{ - twim_irq_handler(NRF_TWIM1, &m_cb[NRFX_TWIM1_INST_IDX]); -} -#endif - -#endif // NRFX_CHECK(NRFX_TWIM_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_twis.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_twis.c deleted file mode 100644 index e139410c55..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_twis.c +++ /dev/null @@ -1,834 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include - -#if NRFX_CHECK(NRFX_TWIS_ENABLED) - -#if !(NRFX_CHECK(NRFX_TWIS0_ENABLED) || NRFX_CHECK(NRFX_TWIS1_ENABLED)) -#error "No enabled TWIS instances. Check ." -#endif - -#include -#include "prs/nrfx_prs.h" - -#define NRFX_LOG_MODULE TWIS -#include - -#define EVT_TO_STR(event) \ - (event == NRF_TWIS_EVENT_STOPPED ? "NRF_TWIS_EVENT_STOPPED" : \ - (event == NRF_TWIS_EVENT_ERROR ? "NRF_TWIS_EVENT_ERROR" : \ - (event == NRF_TWIS_EVENT_RXSTARTED ? "NRF_TWIS_EVENT_RXSTARTED" : \ - (event == NRF_TWIS_EVENT_TXSTARTED ? "NRF_TWIS_EVENT_TXSTARTED" : \ - (event == NRF_TWIS_EVENT_WRITE ? "NRF_TWIS_EVENT_WRITE" : \ - (event == NRF_TWIS_EVENT_READ ? "NRF_TWIS_EVENT_READ" : \ - "UNKNOWN EVENT")))))) - - -/** - * @brief Actual state of internal state machine - * - * Current substate of powered on state. - */ -typedef enum -{ - NRFX_TWIS_SUBSTATE_IDLE, ///< No ongoing transmission - NRFX_TWIS_SUBSTATE_READ_WAITING, ///< Read request received, waiting for data - NRFX_TWIS_SUBSTATE_READ_PENDING, ///< Reading is actually pending (data sending) - NRFX_TWIS_SUBSTATE_WRITE_WAITING, ///< Write request received, waiting for data buffer - NRFX_TWIS_SUBSTATE_WRITE_PENDING, ///< Writing is actually pending (data receiving) -} nrfx_twis_substate_t; - -// Control block - driver instance local data. -typedef struct -{ - nrfx_twis_event_handler_t ev_handler; - // Internal copy of hardware errors flags merged with specific internal - // driver errors flags. - // This value can be changed in the interrupt and cleared in the main program. - // Always use Atomic load-store when updating this value in main loop. - volatile uint32_t error; - nrfx_drv_state_t state; - volatile nrfx_twis_substate_t substate; - - volatile bool semaphore; -} twis_control_block_t; -static twis_control_block_t m_cb[NRFX_TWIS_ENABLED_COUNT]; - -/** - * @brief Used interrupts mask - * - * Mask for all interrupts used by this library - */ -static const uint32_t m_used_ints_mask = NRF_TWIS_INT_STOPPED_MASK | - NRF_TWIS_INT_ERROR_MASK | - NRF_TWIS_INT_RXSTARTED_MASK | - NRF_TWIS_INT_TXSTARTED_MASK | - NRF_TWIS_INT_WRITE_MASK | - NRF_TWIS_INT_READ_MASK; - -/** - * @brief Clear all events - * - * Function clears all actually pending events - */ -static void nrfx_twis_clear_all_events(NRF_TWIS_Type * const p_reg) -{ - /* Clear all events */ - nrf_twis_event_clear(p_reg, NRF_TWIS_EVENT_STOPPED); - nrf_twis_event_clear(p_reg, NRF_TWIS_EVENT_ERROR); - nrf_twis_event_clear(p_reg, NRF_TWIS_EVENT_RXSTARTED); - nrf_twis_event_clear(p_reg, NRF_TWIS_EVENT_TXSTARTED); - nrf_twis_event_clear(p_reg, NRF_TWIS_EVENT_WRITE); - nrf_twis_event_clear(p_reg, NRF_TWIS_EVENT_READ); -} - -/** - * @brief Reset all the registers to known state - * - * This function clears all registers that requires it to known state. - * TWIS is left disabled after this function. - * All events are cleared. - * @param[out] p_reg TWIS to reset register address - */ -static inline void nrfx_twis_swreset(NRF_TWIS_Type * p_reg) -{ - /* Disable TWIS */ - nrf_twis_disable(p_reg); - - /* Disconnect pins */ - nrf_twis_pins_set(p_reg, ~0U, ~0U); - - /* Disable interrupt global for the instance */ - NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_reg)); - - /* Disable interrupts */ - nrf_twis_int_disable(p_reg, ~0U); -} - -/** - * @brief Configure pin - * - * Function configures selected for work as SDA or SCL. - * @param pin Pin number to configure - */ -static inline void nrfx_twis_config_pin(uint32_t pin, nrf_gpio_pin_pull_t pull) -{ - nrf_gpio_cfg(pin, - NRF_GPIO_PIN_DIR_INPUT, - NRF_GPIO_PIN_INPUT_DISCONNECT, - pull, - NRF_GPIO_PIN_S0D1, - NRF_GPIO_PIN_NOSENSE); -} - -/** - * @brief Auxiliary function for getting event state on right bit possition - * - * This function calls @ref nrf_twis_event_get function but the the result - * is shifted to match INTEN register scheme. - * - * @param[in,out] p_reg TWIS to read event from - * @param ev Event code - * - * @return Selected event state shifted by @ref nrfx_event_to_bitpos - * - * @sa nrf_twis_event_get - * @sa nrfx_event_to_bitpos - */ -static inline uint32_t nrfx_twis_event_bit_get(NRF_TWIS_Type * p_reg, - nrf_twis_event_t ev) -{ - return (uint32_t)nrf_twis_event_get_and_clear(p_reg, ev) << nrfx_event_to_bitpos(ev); -} - -/** - * @brief Auxiliary function for checking event bit inside given flags value - * - * Function used here to check presence of the event inside given flags value. - * It transforms given event to bit possition and then checks if in given variable it is cleared. - * - * @param flags Flags to test - * @param ev Event code - * - * @retval true Flag for selected event is set - * @retval false Flag for selected event is cleared - */ -static inline bool nrfx_twis_check_bit(uint32_t flags, - nrf_twis_event_t ev) -{ - return 0 != (flags & (1U << nrfx_event_to_bitpos(ev))); -} - -/** - * @brief Auxiliary function for clearing event bit in given flags value - * - * Function used to clear selected event bit. - * - * @param flags Flags to process - * @param ev Event code to clear - * - * @return Value @em flags with cleared event bit that matches given @em ev - */ -static inline uint32_t nrfx_twis_clear_bit(uint32_t flags, - nrf_twis_event_t ev) -{ - return flags & ~(1U << nrfx_event_to_bitpos(ev)); -} - -static void call_event_handler(twis_control_block_t const * p_cb, - nrfx_twis_evt_t const * p_evt) -{ - nrfx_twis_event_handler_t handler = p_cb->ev_handler; - if (handler != NULL) - { - handler(p_evt); - } -} - -/** - * @brief Auxiliary function for error processing - * - * Function called when in current substate the event apears and it cannot be processed. - * It should be called also on ERROR event. - * If given @em error parameter has zero value the @ref NRFX_TWIS_ERROR_UNEXPECTED_EVENT - * would be set. - * - * @param p_cb Pointer to the driver instance control block. - * @param evt What error event raport to event handler - * @param error Error flags - */ -static inline void nrfx_twis_process_error(twis_control_block_t * p_cb, - nrfx_twis_evt_type_t evt, - uint32_t error) -{ - if (0 == error) - { - error = NRFX_TWIS_ERROR_UNEXPECTED_EVENT; - } - nrfx_twis_evt_t evdata; - evdata.type = evt; - evdata.data.error = error; - - p_cb->error |= error; - - call_event_handler(p_cb, &evdata); -} - -static void nrfx_twis_state_machine(NRF_TWIS_Type * p_reg, - twis_control_block_t * p_cb) -{ - if (!NRFX_TWIS_NO_SYNC_MODE) - { - /* Exclude parallel processing of this function */ - if (p_cb->semaphore) - { - return; - } - p_cb->semaphore = 1; - } - - /* Event data structure to be passed into event handler */ - nrfx_twis_evt_t evdata; - /* Current substate copy */ - nrfx_twis_substate_t substate = p_cb->substate; - /* Event flags */ - uint32_t ev = 0; - - /* Get all events */ - ev |= nrfx_twis_event_bit_get(p_reg, NRF_TWIS_EVENT_STOPPED); - ev |= nrfx_twis_event_bit_get(p_reg, NRF_TWIS_EVENT_ERROR); - ev |= nrfx_twis_event_bit_get(p_reg, NRF_TWIS_EVENT_RXSTARTED); - ev |= nrfx_twis_event_bit_get(p_reg, NRF_TWIS_EVENT_TXSTARTED); - ev |= nrfx_twis_event_bit_get(p_reg, NRF_TWIS_EVENT_WRITE); - ev |= nrfx_twis_event_bit_get(p_reg, NRF_TWIS_EVENT_READ); - - /* State machine */ - while (0 != ev) - { - switch (substate) - { - case NRFX_TWIS_SUBSTATE_IDLE: - if (nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_STOPPED)) - { - /* Stopped event is always allowed in IDLE state - just ignore */ - ev = nrfx_twis_clear_bit(ev, NRF_TWIS_EVENT_STOPPED); - } - else if (nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_READ)) - { - evdata.type = NRFX_TWIS_EVT_READ_REQ; - if (nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_TXSTARTED)) - { - substate = NRFX_TWIS_SUBSTATE_READ_PENDING; - evdata.data.buf_req = false; - } - else - { - substate = NRFX_TWIS_SUBSTATE_READ_WAITING; - evdata.data.buf_req = true; - } - call_event_handler(p_cb, &evdata); - ev = nrfx_twis_clear_bit(ev, NRF_TWIS_EVENT_READ); - ev = nrfx_twis_clear_bit(ev, NRF_TWIS_EVENT_TXSTARTED); - ev = nrfx_twis_clear_bit(ev, NRF_TWIS_EVENT_WRITE); - ev = nrfx_twis_clear_bit(ev, NRF_TWIS_EVENT_RXSTARTED); - } - else if (nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_WRITE)) - { - evdata.type = NRFX_TWIS_EVT_WRITE_REQ; - if (nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_RXSTARTED)) - { - substate = NRFX_TWIS_SUBSTATE_WRITE_PENDING; - evdata.data.buf_req = false; - } - else - { - substate = NRFX_TWIS_SUBSTATE_WRITE_WAITING; - evdata.data.buf_req = true; - } - call_event_handler(p_cb, &evdata); - ev = nrfx_twis_clear_bit(ev, NRF_TWIS_EVENT_READ); - ev = nrfx_twis_clear_bit(ev, NRF_TWIS_EVENT_TXSTARTED); - ev = nrfx_twis_clear_bit(ev, NRF_TWIS_EVENT_WRITE); - ev = nrfx_twis_clear_bit(ev, NRF_TWIS_EVENT_RXSTARTED); - } - else - { - nrfx_twis_process_error(p_cb, - NRFX_TWIS_EVT_GENERAL_ERROR, - nrf_twis_error_source_get_and_clear(p_reg)); - ev = 0; - } - break; - case NRFX_TWIS_SUBSTATE_READ_WAITING: - if (nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_TXSTARTED) || - nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_WRITE) || - nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_READ) || - nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_STOPPED)) - { - substate = NRFX_TWIS_SUBSTATE_READ_PENDING; - /* Any other bits requires further processing in PENDING substate */ - ev = nrfx_twis_clear_bit(ev, NRF_TWIS_EVENT_TXSTARTED); - } - else - { - nrfx_twis_process_error(p_cb, - NRFX_TWIS_EVT_READ_ERROR, - nrf_twis_error_source_get_and_clear(p_reg)); - substate = NRFX_TWIS_SUBSTATE_IDLE; - ev = 0; - } - break; - case NRFX_TWIS_SUBSTATE_READ_PENDING: - if (nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_WRITE) || - nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_READ) || - nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_STOPPED)) - { - evdata.type = NRFX_TWIS_EVT_READ_DONE; - evdata.data.tx_amount = nrf_twis_tx_amount_get(p_reg); - NRFX_LOG_INFO("Transfer tx_len:%d", evdata.data.tx_amount); - NRFX_LOG_DEBUG("Tx data:"); - NRFX_LOG_HEXDUMP_DEBUG((uint8_t const *)p_reg->TXD.PTR, - evdata.data.tx_amount * sizeof(uint8_t)); - call_event_handler(p_cb, &evdata); - /* Go to idle and repeat the state machine if READ or WRITE events detected. - * This time READ or WRITE would be started */ - substate = NRFX_TWIS_SUBSTATE_IDLE; - ev = nrfx_twis_clear_bit(ev, NRF_TWIS_EVENT_STOPPED); - } - else - { - nrfx_twis_process_error(p_cb, - NRFX_TWIS_EVT_READ_ERROR, - nrf_twis_error_source_get_and_clear(p_reg)); - substate = NRFX_TWIS_SUBSTATE_IDLE; - ev = 0; - } - break; - case NRFX_TWIS_SUBSTATE_WRITE_WAITING: - if (nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_RXSTARTED) || - nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_WRITE) || - nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_READ) || - nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_STOPPED)) - { - substate = NRFX_TWIS_SUBSTATE_WRITE_PENDING; - /* Any other bits requires further processing in PENDING substate */ - ev = nrfx_twis_clear_bit(ev, NRF_TWIS_EVENT_RXSTARTED); - } - else - { - nrfx_twis_process_error(p_cb, - NRFX_TWIS_EVT_WRITE_ERROR, - nrf_twis_error_source_get_and_clear(p_reg)); - substate = NRFX_TWIS_SUBSTATE_IDLE; - ev = 0; - } - break; - case NRFX_TWIS_SUBSTATE_WRITE_PENDING: - if (nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_WRITE) || - nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_READ) || - nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_STOPPED)) - { - evdata.type = NRFX_TWIS_EVT_WRITE_DONE; - evdata.data.rx_amount = nrf_twis_rx_amount_get(p_reg); - call_event_handler(p_cb, &evdata); - /* Go to idle and repeat the state machine if READ or WRITE events detected. - * This time READ or WRITE would be started */ - substate = NRFX_TWIS_SUBSTATE_IDLE; - ev = nrfx_twis_clear_bit(ev, NRF_TWIS_EVENT_STOPPED); - } - else - { - nrfx_twis_process_error(p_cb, - NRFX_TWIS_EVT_WRITE_ERROR, - nrf_twis_error_source_get_and_clear(p_reg)); - substate = NRFX_TWIS_SUBSTATE_IDLE; - ev = 0; - } - break; - default: - substate = NRFX_TWIS_SUBSTATE_IDLE; - /* Do not clear any events and repeat the machine */ - break; - } - } - - p_cb->substate = substate; - if (!NRFX_TWIS_NO_SYNC_MODE) - { - p_cb->semaphore = 0; - } -} - - -static inline void nrfx_twis_preprocess_status(nrfx_twis_t const * p_instance) -{ - if (!NRFX_TWIS_NO_SYNC_MODE) - { - NRF_TWIS_Type * p_reg = p_instance->p_reg; - twis_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - if (NULL == p_cb->ev_handler) - { - nrfx_twis_state_machine(p_reg, p_cb); - } - } -} - - -/* ------------------------------------------------------------------------- - * Implementation of interface functions - * - */ - - -nrfx_err_t nrfx_twis_init(nrfx_twis_t const * p_instance, - nrfx_twis_config_t const * p_config, - nrfx_twis_event_handler_t event_handler) -{ - NRFX_ASSERT(p_config); - NRFX_ASSERT(p_config->scl != p_config->sda); - nrfx_err_t err_code; - - NRF_TWIS_Type * p_reg = p_instance->p_reg; - twis_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - - if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED) - { - err_code = NRFX_ERROR_INVALID_STATE; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - -#if NRFX_CHECK(NRFX_PRS_ENABLED) - static nrfx_irq_handler_t const irq_handlers[NRFX_TWIS_ENABLED_COUNT] = { - #if NRFX_CHECK(NRFX_TWIS0_ENABLED) - nrfx_twis_0_irq_handler, - #endif - #if NRFX_CHECK(NRFX_TWIS1_ENABLED) - nrfx_twis_1_irq_handler, - #endif - }; - if (nrfx_prs_acquire(p_reg, - irq_handlers[p_instance->drv_inst_idx]) != NRFX_SUCCESS) - { - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } -#endif // NRFX_CHECK(NRFX_PRS_ENABLED) - - if (!NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY) - { - nrfx_twis_swreset(p_reg); - } - - nrfx_twis_config_pin(p_config->scl, p_config->scl_pull); - nrfx_twis_config_pin(p_config->sda, p_config->sda_pull); - - nrf_twis_config_addr_mask_t addr_mask = (nrf_twis_config_addr_mask_t)0; - if (0 == (p_config->addr[0] | p_config->addr[1])) - { - addr_mask = NRF_TWIS_CONFIG_ADDRESS0_MASK; - } - else - { - if (0 != p_config->addr[0]) - { - addr_mask |= NRF_TWIS_CONFIG_ADDRESS0_MASK; - } - if (0 != p_config->addr[1]) - { - addr_mask |= NRF_TWIS_CONFIG_ADDRESS1_MASK; - } - } - - /* Peripheral interrupt configure - * (note - interrupts still needs to be configured in INTEN register. - * This is done in enable function) */ - NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_reg), - p_config->interrupt_priority); - NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_reg)); - - /* Configure */ - nrf_twis_pins_set (p_reg, p_config->scl, p_config->sda); - nrf_twis_address_set (p_reg, 0, p_config->addr[0]); - nrf_twis_address_set (p_reg, 1, p_config->addr[1]); - nrf_twis_config_address_set(p_reg, addr_mask); - - /* Clear semaphore */ - if (!NRFX_TWIS_NO_SYNC_MODE) - { - p_cb->semaphore = 0; - } - /* Set internal instance variables */ - p_cb->substate = NRFX_TWIS_SUBSTATE_IDLE; - p_cb->ev_handler = event_handler; - p_cb->state = NRFX_DRV_STATE_INITIALIZED; - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - - -void nrfx_twis_uninit(nrfx_twis_t const * p_instance) -{ - NRF_TWIS_Type * p_reg = p_instance->p_reg; - twis_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); - - TWIS_PSEL_Type psel = p_reg->PSEL; - - nrfx_twis_swreset(p_reg); - - /* Clear pins state if */ - if (!(TWIS_PSEL_SCL_CONNECT_Msk & psel.SCL)) - { - nrf_gpio_cfg_default(psel.SCL); - } - if (!(TWIS_PSEL_SDA_CONNECT_Msk & psel.SDA)) - { - nrf_gpio_cfg_default(psel.SDA); - } - -#if NRFX_CHECK(NRFX_PRS_ENABLED) - nrfx_prs_release(p_reg); -#endif - - /* Clear variables */ - p_cb->ev_handler = NULL; - p_cb->state = NRFX_DRV_STATE_UNINITIALIZED; -} - - -void nrfx_twis_enable(nrfx_twis_t const * p_instance) -{ - NRF_TWIS_Type * p_reg = p_instance->p_reg; - twis_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - NRFX_ASSERT(p_cb->state == NRFX_DRV_STATE_INITIALIZED); - - nrfx_twis_clear_all_events(p_reg); - - /* Enable interrupts */ - if (NULL != p_cb->ev_handler) - { - nrf_twis_int_enable(p_reg, m_used_ints_mask); - } - - nrf_twis_enable(p_reg); - p_cb->error = 0; - p_cb->state = NRFX_DRV_STATE_POWERED_ON; - p_cb->substate = NRFX_TWIS_SUBSTATE_IDLE; -} - - -void nrfx_twis_disable(nrfx_twis_t const * p_instance) -{ - NRF_TWIS_Type * p_reg = p_instance->p_reg; - twis_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); - - nrf_twis_int_disable(p_reg, m_used_ints_mask); - - nrf_twis_disable(p_reg); - p_cb->state = NRFX_DRV_STATE_INITIALIZED; -} - -/* ARM recommends not using the LDREX and STREX instructions in C code. - * This is because the compiler might generate loads and stores between - * LDREX and STREX, potentially clearing the exclusive monitor set by LDREX. - * This recommendation also applies to the byte, halfword, and doubleword - * variants LDREXB, STREXB, LDREXH, STREXH, LDREXD, and STREXD. - * - * This is the reason for the function below to be implemented in assembly. - */ -//lint -save -e578 -#if defined (__CC_ARM ) -static __ASM uint32_t nrfx_twis_error_get_and_clear_internal(uint32_t volatile * perror) -{ - mov r3, r0 - mov r1, #0 -nrfx_twis_error_get_and_clear_internal_try - ldrex r0, [r3] - strex r2, r1, [r3] - cmp r2, r1 /* did this succeed? */ - bne nrfx_twis_error_get_and_clear_internal_try /* no - try again */ - bx lr -} -#elif defined ( __GNUC__ ) -static uint32_t nrfx_twis_error_get_and_clear_internal(uint32_t volatile * perror) -{ - uint32_t ret; - uint32_t temp; - __ASM volatile( - " .syntax unified \n" - "nrfx_twis_error_get_and_clear_internal_try: \n" - " ldrex %[ret], [%[perror]] \n" - " strex %[temp], %[zero], [%[perror]] \n" - " cmp %[temp], %[zero] \n" - " bne nrfx_twis_error_get_and_clear_internal_try \n" - : /* Output */ - [ret]"=&l"(ret), - [temp]"=&l"(temp) - : /* Input */ - [zero]"l"(0), - [perror]"l"(perror) - ); - (void)temp; - return ret; -} -#elif defined ( __ICCARM__ ) -static uint32_t nrfx_twis_error_get_and_clear_internal(uint32_t volatile * perror) -{ - uint32_t ret; - uint32_t temp; - __ASM volatile( - "1: \n" - " ldrex %[ret], [%[perror]] \n" - " strex %[temp], %[zero], [%[perror]] \n" - " cmp %[temp], %[zero] \n" - " bne.n 1b \n" - : /* Output */ - [ret]"=&l"(ret), - [temp]"=&l"(temp) - : /* Input */ - [zero]"l"(0), - [perror]"l"(perror) - ); - (void)temp; - return ret; -} -#else - #error Unknown compiler -#endif -//lint -restore - -uint32_t nrfx_twis_error_get_and_clear(nrfx_twis_t const * p_instance) -{ - nrfx_twis_preprocess_status(p_instance); - /* Make sure that access to error member is atomic - * so there is no bit that is cleared if it is not copied to local variable already. */ - twis_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - return nrfx_twis_error_get_and_clear_internal(&p_cb->error); -} - - -nrfx_err_t nrfx_twis_tx_prepare(nrfx_twis_t const * p_instance, - void const * p_buf, - size_t size) -{ - nrfx_err_t err_code; - twis_control_block_t const * p_cb = &m_cb[p_instance->drv_inst_idx]; - - /* Check power state*/ - if (p_cb->state != NRFX_DRV_STATE_POWERED_ON) - { - err_code = NRFX_ERROR_INVALID_STATE; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - /* Check data address */ - if (!nrfx_is_in_ram(p_buf)) - { - err_code = NRFX_ERROR_INVALID_ADDR; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - /* Check data size */ - if ((size & TWIS_TXD_MAXCNT_MAXCNT_Msk) != size) - { - err_code = NRFX_ERROR_INVALID_LENGTH; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - nrf_twis_tx_prepare(p_instance->p_reg, - (uint8_t const *)p_buf, - (nrf_twis_amount_t)size); - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - - -nrfx_err_t nrfx_twis_rx_prepare(nrfx_twis_t const * p_instance, - void * p_buf, - size_t size) -{ - nrfx_err_t err_code; - twis_control_block_t const * p_cb = &m_cb[p_instance->drv_inst_idx]; - - /* Check power state*/ - if (p_cb->state != NRFX_DRV_STATE_POWERED_ON) - { - err_code = NRFX_ERROR_INVALID_STATE; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - /* Check data address */ - if (!nrfx_is_in_ram(p_buf)) - { - err_code = NRFX_ERROR_INVALID_ADDR; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - /* Check data size */ - if ((size & TWIS_RXD_MAXCNT_MAXCNT_Msk) != size) - { - err_code = NRFX_ERROR_INVALID_LENGTH; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - nrf_twis_rx_prepare(p_instance->p_reg, - (uint8_t *)p_buf, - (nrf_twis_amount_t)size); - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - - -bool nrfx_twis_is_busy(nrfx_twis_t const * p_instance) -{ - nrfx_twis_preprocess_status(p_instance); - twis_control_block_t const * p_cb = &m_cb[p_instance->drv_inst_idx]; - return NRFX_TWIS_SUBSTATE_IDLE != p_cb->substate; -} - -bool nrfx_twis_is_waiting_tx_buff(nrfx_twis_t const * p_instance) -{ - nrfx_twis_preprocess_status(p_instance); - twis_control_block_t const * p_cb = &m_cb[p_instance->drv_inst_idx]; - return NRFX_TWIS_SUBSTATE_READ_WAITING == p_cb->substate; -} - -bool nrfx_twis_is_waiting_rx_buff(nrfx_twis_t const * p_instance) -{ - nrfx_twis_preprocess_status(p_instance); - twis_control_block_t const * p_cb = &m_cb[p_instance->drv_inst_idx]; - return NRFX_TWIS_SUBSTATE_WRITE_WAITING == p_cb->substate; -} - -bool nrfx_twis_is_pending_tx(nrfx_twis_t const * p_instance) -{ - nrfx_twis_preprocess_status(p_instance); - twis_control_block_t const * p_cb = &m_cb[p_instance->drv_inst_idx]; - return NRFX_TWIS_SUBSTATE_READ_PENDING == p_cb->substate; -} - -bool nrfx_twis_is_pending_rx(nrfx_twis_t const * p_instance) -{ - nrfx_twis_preprocess_status(p_instance); - twis_control_block_t const * p_cb = &m_cb[p_instance->drv_inst_idx]; - return NRFX_TWIS_SUBSTATE_WRITE_PENDING == p_cb->substate; -} - - -#if NRFX_CHECK(NRFX_TWIS0_ENABLED) -void nrfx_twis_0_irq_handler(void) -{ - nrfx_twis_state_machine(NRF_TWIS0, &m_cb[NRFX_TWIS0_INST_IDX]); -} -#endif - -#if NRFX_CHECK(NRFX_TWIS1_ENABLED) -void nrfx_twis_1_irq_handler(void) -{ - nrfx_twis_state_machine(NRF_TWIS1, &m_cb[NRFX_TWIS1_INST_IDX]); -} -#endif - -#endif // NRFX_CHECK(NRFX_TWIS_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_uart.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_uart.c deleted file mode 100644 index 87caf36855..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_uart.c +++ /dev/null @@ -1,649 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include - -#if NRFX_CHECK(NRFX_UART_ENABLED) - -#if !NRFX_CHECK(NRFX_UART0_ENABLED) -#error "No enabled UART instances. Check ." -#endif - -#include -#include "prs/nrfx_prs.h" -#include - -#define NRFX_LOG_MODULE UART -#include - -#define EVT_TO_STR(event) \ - (event == NRF_UART_EVENT_ERROR ? "NRF_UART_EVENT_ERROR" : \ - "UNKNOWN EVENT") - - -#define TX_COUNTER_ABORT_REQ_VALUE UINT32_MAX - -typedef struct -{ - void * p_context; - nrfx_uart_event_handler_t handler; - uint8_t const * p_tx_buffer; - uint8_t * p_rx_buffer; - uint8_t * p_rx_secondary_buffer; - size_t tx_buffer_length; - size_t rx_buffer_length; - size_t rx_secondary_buffer_length; - volatile size_t tx_counter; - volatile size_t rx_counter; - volatile bool tx_abort; - bool rx_enabled; - nrfx_drv_state_t state; -} uart_control_block_t; -static uart_control_block_t m_cb[NRFX_UART_ENABLED_COUNT]; - -static void apply_config(nrfx_uart_t const * p_instance, - nrfx_uart_config_t const * p_config) -{ - if (p_config->pseltxd != NRF_UART_PSEL_DISCONNECTED) - { - nrf_gpio_pin_set(p_config->pseltxd); - nrf_gpio_cfg_output(p_config->pseltxd); - } - if (p_config->pselrxd != NRF_UART_PSEL_DISCONNECTED) - { - nrf_gpio_cfg_input(p_config->pselrxd, NRF_GPIO_PIN_NOPULL); - } - - nrf_uart_baudrate_set(p_instance->p_reg, p_config->baudrate); - nrf_uart_configure(p_instance->p_reg, p_config->parity, p_config->hwfc); - nrf_uart_txrx_pins_set(p_instance->p_reg, p_config->pseltxd, p_config->pselrxd); - if (p_config->hwfc == NRF_UART_HWFC_ENABLED) - { - if (p_config->pselcts != NRF_UART_PSEL_DISCONNECTED) - { - nrf_gpio_cfg_input(p_config->pselcts, NRF_GPIO_PIN_NOPULL); - } - if (p_config->pselrts != NRF_UART_PSEL_DISCONNECTED) - { - nrf_gpio_pin_set(p_config->pselrts); - nrf_gpio_cfg_output(p_config->pselrts); - } - nrf_uart_hwfc_pins_set(p_instance->p_reg, p_config->pselrts, p_config->pselcts); - } -} - -static void interrupts_enable(nrfx_uart_t const * p_instance, - uint8_t interrupt_priority) -{ - nrf_uart_event_clear(p_instance->p_reg, NRF_UART_EVENT_TXDRDY); - nrf_uart_event_clear(p_instance->p_reg, NRF_UART_EVENT_RXTO); - nrf_uart_int_enable(p_instance->p_reg, NRF_UART_INT_MASK_TXDRDY | - NRF_UART_INT_MASK_RXTO); - NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number((void *)p_instance->p_reg), - interrupt_priority); - NRFX_IRQ_ENABLE(nrfx_get_irq_number((void *)p_instance->p_reg)); -} - -static void interrupts_disable(nrfx_uart_t const * p_instance) -{ - nrf_uart_int_disable(p_instance->p_reg, NRF_UART_INT_MASK_RXDRDY | - NRF_UART_INT_MASK_TXDRDY | - NRF_UART_INT_MASK_ERROR | - NRF_UART_INT_MASK_RXTO); - NRFX_IRQ_DISABLE(nrfx_get_irq_number((void *)p_instance->p_reg)); -} - -static void pins_to_default(nrfx_uart_t const * p_instance) -{ - /* Reset pins to default states */ - uint32_t txd; - uint32_t rxd; - uint32_t rts; - uint32_t cts; - - txd = nrf_uart_tx_pin_get(p_instance->p_reg); - rxd = nrf_uart_rx_pin_get(p_instance->p_reg); - rts = nrf_uart_rts_pin_get(p_instance->p_reg); - cts = nrf_uart_cts_pin_get(p_instance->p_reg); - nrf_uart_txrx_pins_disconnect(p_instance->p_reg); - nrf_uart_hwfc_pins_disconnect(p_instance->p_reg); - - if (txd != NRF_UART_PSEL_DISCONNECTED) - { - nrf_gpio_cfg_default(txd); - } - if (rxd != NRF_UART_PSEL_DISCONNECTED) - { - nrf_gpio_cfg_default(rxd); - } - if (cts != NRF_UART_PSEL_DISCONNECTED) - { - nrf_gpio_cfg_default(cts); - } - if (rts != NRF_UART_PSEL_DISCONNECTED) - { - nrf_gpio_cfg_default(rts); - } -} - -nrfx_err_t nrfx_uart_init(nrfx_uart_t const * p_instance, - nrfx_uart_config_t const * p_config, - nrfx_uart_event_handler_t event_handler) -{ - NRFX_ASSERT(p_config); - uart_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - nrfx_err_t err_code = NRFX_SUCCESS; - - if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED) - { - err_code = NRFX_ERROR_INVALID_STATE; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - -#if NRFX_CHECK(NRFX_PRS_ENABLED) - static nrfx_irq_handler_t const irq_handlers[NRFX_UART_ENABLED_COUNT] = { - #if NRFX_CHECK(NRFX_UART0_ENABLED) - nrfx_uart_0_irq_handler, - #endif - }; - if (nrfx_prs_acquire(p_instance->p_reg, - irq_handlers[p_instance->drv_inst_idx]) != NRFX_SUCCESS) - { - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } -#endif // NRFX_CHECK(NRFX_PRS_ENABLED) - - apply_config(p_instance, p_config); - - p_cb->handler = event_handler; - p_cb->p_context = p_config->p_context; - - if (p_cb->handler) - { - interrupts_enable(p_instance, p_config->interrupt_priority); - } - - nrf_uart_enable(p_instance->p_reg); - p_cb->rx_buffer_length = 0; - p_cb->rx_secondary_buffer_length = 0; - p_cb->rx_enabled = false; - p_cb->tx_buffer_length = 0; - p_cb->state = NRFX_DRV_STATE_INITIALIZED; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -void nrfx_uart_uninit(nrfx_uart_t const * p_instance) -{ - uart_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - - nrf_uart_disable(p_instance->p_reg); - - if (p_cb->handler) - { - interrupts_disable(p_instance); - } - - pins_to_default(p_instance); - -#if NRFX_CHECK(NRFX_PRS_ENABLED) - nrfx_prs_release(p_instance->p_reg); -#endif - - p_cb->state = NRFX_DRV_STATE_UNINITIALIZED; - p_cb->handler = NULL; - NRFX_LOG_INFO("Instance uninitialized: %d.", p_instance->drv_inst_idx); -} - -static void tx_byte(NRF_UART_Type * p_uart, uart_control_block_t * p_cb) -{ - nrf_uart_event_clear(p_uart, NRF_UART_EVENT_TXDRDY); - uint8_t txd = p_cb->p_tx_buffer[p_cb->tx_counter]; - p_cb->tx_counter++; - nrf_uart_txd_set(p_uart, txd); -} - -static bool tx_blocking(NRF_UART_Type * p_uart, uart_control_block_t * p_cb) -{ - while (p_cb->tx_counter < p_cb->tx_buffer_length) - { - // Wait until the transmitter is ready to accept a new byte. - // Exit immediately if the transfer has been aborted. - while (!nrf_uart_event_check(p_uart, NRF_UART_EVENT_TXDRDY)) - { - if (p_cb->tx_abort) - { - return false; - } - } - - tx_byte(p_uart, p_cb); - } - - return true; -} - -nrfx_err_t nrfx_uart_tx(nrfx_uart_t const * p_instance, - uint8_t const * p_data, - size_t length) -{ - uart_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - NRFX_ASSERT(p_cb->state == NRFX_DRV_STATE_INITIALIZED); - NRFX_ASSERT(p_data); - NRFX_ASSERT(length > 0); - - nrfx_err_t err_code; - - if (nrfx_uart_tx_in_progress(p_instance)) - { - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - p_cb->tx_buffer_length = length; - p_cb->p_tx_buffer = p_data; - p_cb->tx_counter = 0; - p_cb->tx_abort = false; - - NRFX_LOG_INFO("Transfer tx_len: %d.", p_cb->tx_buffer_length); - NRFX_LOG_DEBUG("Tx data:"); - NRFX_LOG_HEXDUMP_DEBUG(p_cb->p_tx_buffer, - p_cb->tx_buffer_length * sizeof(p_cb->p_tx_buffer[0])); - - err_code = NRFX_SUCCESS; - - nrf_uart_event_clear(p_instance->p_reg, NRF_UART_EVENT_TXDRDY); - nrf_uart_task_trigger(p_instance->p_reg, NRF_UART_TASK_STARTTX); - - tx_byte(p_instance->p_reg, p_cb); - - if (p_cb->handler == NULL) - { - if (!tx_blocking(p_instance->p_reg, p_cb)) - { - // The transfer has been aborted. - err_code = NRFX_ERROR_FORBIDDEN; - } - else - { - // Wait until the last byte is completely transmitted. - while (!nrf_uart_event_check(p_instance->p_reg, NRF_UART_EVENT_TXDRDY)) - {} - nrf_uart_task_trigger(p_instance->p_reg, NRF_UART_TASK_STOPTX); - } - p_cb->tx_buffer_length = 0; - } - - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -bool nrfx_uart_tx_in_progress(nrfx_uart_t const * p_instance) -{ - return (m_cb[p_instance->drv_inst_idx].tx_buffer_length != 0); -} - -static void rx_enable(nrfx_uart_t const * p_instance) -{ - nrf_uart_event_clear(p_instance->p_reg, NRF_UART_EVENT_ERROR); - nrf_uart_event_clear(p_instance->p_reg, NRF_UART_EVENT_RXDRDY); - nrf_uart_task_trigger(p_instance->p_reg, NRF_UART_TASK_STARTRX); -} - -static void rx_byte(NRF_UART_Type * p_uart, uart_control_block_t * p_cb) -{ - if (!p_cb->rx_buffer_length) - { - nrf_uart_event_clear(p_uart, NRF_UART_EVENT_RXDRDY); - // Byte received when buffer is not set - data lost. - (void) nrf_uart_rxd_get(p_uart); - return; - } - nrf_uart_event_clear(p_uart, NRF_UART_EVENT_RXDRDY); - p_cb->p_rx_buffer[p_cb->rx_counter] = nrf_uart_rxd_get(p_uart); - p_cb->rx_counter++; -} - -nrfx_err_t nrfx_uart_rx(nrfx_uart_t const * p_instance, - uint8_t * p_data, - size_t length) -{ - uart_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - - NRFX_ASSERT(m_cb[p_instance->drv_inst_idx].state == NRFX_DRV_STATE_INITIALIZED); - NRFX_ASSERT(p_data); - NRFX_ASSERT(length > 0); - - nrfx_err_t err_code; - - bool second_buffer = false; - - if (p_cb->handler) - { - nrf_uart_int_disable(p_instance->p_reg, NRF_UART_INT_MASK_RXDRDY | - NRF_UART_INT_MASK_ERROR); - } - if (p_cb->rx_buffer_length != 0) - { - if (p_cb->rx_secondary_buffer_length != 0) - { - if (p_cb->handler) - { - nrf_uart_int_enable(p_instance->p_reg, NRF_UART_INT_MASK_RXDRDY | - NRF_UART_INT_MASK_ERROR); - } - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - second_buffer = true; - } - - if (!second_buffer) - { - p_cb->rx_buffer_length = length; - p_cb->p_rx_buffer = p_data; - p_cb->rx_counter = 0; - p_cb->rx_secondary_buffer_length = 0; - } - else - { - p_cb->p_rx_secondary_buffer = p_data; - p_cb->rx_secondary_buffer_length = length; - } - - NRFX_LOG_INFO("Transfer rx_len: %d.", length); - - if ((!p_cb->rx_enabled) && (!second_buffer)) - { - rx_enable(p_instance); - } - - if (p_cb->handler == NULL) - { - nrf_uart_event_clear(p_instance->p_reg, NRF_UART_EVENT_RXTO); - - bool rxrdy; - bool rxto; - bool error; - do - { - do - { - error = nrf_uart_event_check(p_instance->p_reg, NRF_UART_EVENT_ERROR); - rxrdy = nrf_uart_event_check(p_instance->p_reg, NRF_UART_EVENT_RXDRDY); - rxto = nrf_uart_event_check(p_instance->p_reg, NRF_UART_EVENT_RXTO); - } while ((!rxrdy) && (!rxto) && (!error)); - - if (error || rxto) - { - break; - } - rx_byte(p_instance->p_reg, p_cb); - } while (p_cb->rx_buffer_length > p_cb->rx_counter); - - p_cb->rx_buffer_length = 0; - if (error) - { - err_code = NRFX_ERROR_INTERNAL; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - if (rxto) - { - err_code = NRFX_ERROR_FORBIDDEN; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - if (p_cb->rx_enabled) - { - nrf_uart_task_trigger(p_instance->p_reg, NRF_UART_TASK_STARTRX); - } - else - { - // Skip stopping RX if driver is forced to be enabled. - nrf_uart_task_trigger(p_instance->p_reg, NRF_UART_TASK_STOPRX); - } - } - else - { - nrf_uart_int_enable(p_instance->p_reg, NRF_UART_INT_MASK_RXDRDY | - NRF_UART_INT_MASK_ERROR); - } - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -bool nrfx_uart_rx_ready(nrfx_uart_t const * p_instance) -{ - return nrf_uart_event_check(p_instance->p_reg, NRF_UART_EVENT_RXDRDY); -} - -void nrfx_uart_rx_enable(nrfx_uart_t const * p_instance) -{ - if (!m_cb[p_instance->drv_inst_idx].rx_enabled) - { - rx_enable(p_instance); - m_cb[p_instance->drv_inst_idx].rx_enabled = true; - } -} - -void nrfx_uart_rx_disable(nrfx_uart_t const * p_instance) -{ - nrf_uart_task_trigger(p_instance->p_reg, NRF_UART_TASK_STOPRX); - m_cb[p_instance->drv_inst_idx].rx_enabled = false; -} - -uint32_t nrfx_uart_errorsrc_get(nrfx_uart_t const * p_instance) -{ - nrf_uart_event_clear(p_instance->p_reg, NRF_UART_EVENT_ERROR); - return nrf_uart_errorsrc_get_and_clear(p_instance->p_reg); -} - -static void rx_done_event(uart_control_block_t * p_cb, - size_t bytes, - uint8_t * p_data) -{ - nrfx_uart_event_t event; - - event.type = NRFX_UART_EVT_RX_DONE; - event.data.rxtx.bytes = bytes; - event.data.rxtx.p_data = p_data; - - p_cb->handler(&event, p_cb->p_context); -} - -static void tx_done_event(uart_control_block_t * p_cb, - size_t bytes) -{ - nrfx_uart_event_t event; - - event.type = NRFX_UART_EVT_TX_DONE; - event.data.rxtx.bytes = bytes; - event.data.rxtx.p_data = (uint8_t *)p_cb->p_tx_buffer; - - p_cb->tx_buffer_length = 0; - - p_cb->handler(&event, p_cb->p_context); -} - -void nrfx_uart_tx_abort(nrfx_uart_t const * p_instance) -{ - uart_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - - p_cb->tx_abort = true; - nrf_uart_task_trigger(p_instance->p_reg, NRF_UART_TASK_STOPTX); - if (p_cb->handler) - { - tx_done_event(p_cb, p_cb->tx_counter); - } - - NRFX_LOG_INFO("TX transaction aborted."); -} - -void nrfx_uart_rx_abort(nrfx_uart_t const * p_instance) -{ - nrf_uart_int_disable(p_instance->p_reg, NRF_UART_INT_MASK_RXDRDY | - NRF_UART_INT_MASK_ERROR); - nrf_uart_task_trigger(p_instance->p_reg, NRF_UART_TASK_STOPRX); - - NRFX_LOG_INFO("RX transaction aborted."); -} - -static void uart_irq_handler(NRF_UART_Type * p_uart, - uart_control_block_t * p_cb) -{ - if (nrf_uart_int_enable_check(p_uart, NRF_UART_INT_MASK_ERROR) && - nrf_uart_event_check(p_uart, NRF_UART_EVENT_ERROR)) - { - nrfx_uart_event_t event; - nrf_uart_event_clear(p_uart, NRF_UART_EVENT_ERROR); - NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRF_UART_EVENT_ERROR)); - nrf_uart_int_disable(p_uart, NRF_UART_INT_MASK_RXDRDY | - NRF_UART_INT_MASK_ERROR); - if (!p_cb->rx_enabled) - { - nrf_uart_task_trigger(p_uart, NRF_UART_TASK_STOPRX); - } - event.type = NRFX_UART_EVT_ERROR; - event.data.error.error_mask = nrf_uart_errorsrc_get_and_clear(p_uart); - event.data.error.rxtx.bytes = p_cb->rx_buffer_length; - event.data.error.rxtx.p_data = p_cb->p_rx_buffer; - - // Abort transfer. - p_cb->rx_buffer_length = 0; - p_cb->rx_secondary_buffer_length = 0; - - p_cb->handler(&event,p_cb->p_context); - } - else if (nrf_uart_int_enable_check(p_uart, NRF_UART_INT_MASK_RXDRDY) && - nrf_uart_event_check(p_uart, NRF_UART_EVENT_RXDRDY)) - { - rx_byte(p_uart, p_cb); - if (p_cb->rx_buffer_length == p_cb->rx_counter) - { - if (p_cb->rx_secondary_buffer_length) - { - uint8_t * p_data = p_cb->p_rx_buffer; - size_t rx_counter = p_cb->rx_counter; - - // Switch to secondary buffer. - p_cb->rx_buffer_length = p_cb->rx_secondary_buffer_length; - p_cb->p_rx_buffer = p_cb->p_rx_secondary_buffer; - p_cb->rx_secondary_buffer_length = 0; - p_cb->rx_counter = 0; - rx_done_event(p_cb, rx_counter, p_data); - } - else - { - if (!p_cb->rx_enabled) - { - nrf_uart_task_trigger(p_uart, NRF_UART_TASK_STOPRX); - } - nrf_uart_int_disable(p_uart, NRF_UART_INT_MASK_RXDRDY | - NRF_UART_INT_MASK_ERROR); - p_cb->rx_buffer_length = 0; - rx_done_event(p_cb, p_cb->rx_counter, p_cb->p_rx_buffer); - } - } - } - - if (nrf_uart_event_check(p_uart, NRF_UART_EVENT_TXDRDY)) - { - if (p_cb->tx_counter < p_cb->tx_buffer_length && - !p_cb->tx_abort) - { - tx_byte(p_uart, p_cb); - } - else - { - nrf_uart_event_clear(p_uart, NRF_UART_EVENT_TXDRDY); - if (p_cb->tx_buffer_length) - { - tx_done_event(p_cb, p_cb->tx_buffer_length); - } - } - } - - if (nrf_uart_event_check(p_uart, NRF_UART_EVENT_RXTO)) - { - nrf_uart_event_clear(p_uart, NRF_UART_EVENT_RXTO); - - // RXTO event may be triggered as a result of abort call. In th - if (p_cb->rx_enabled) - { - nrf_uart_task_trigger(p_uart, NRF_UART_TASK_STARTRX); - } - if (p_cb->rx_buffer_length) - { - p_cb->rx_buffer_length = 0; - rx_done_event(p_cb, p_cb->rx_counter, p_cb->p_rx_buffer); - } - } -} - -//#if NRFX_CHECK(NRFX_UART0_ENABLED) -//void nrfx_uart_0_irq_handler(void) -//{ -// uart_irq_handler(NRF_UART0, &m_cb[NRFX_UART0_INST_IDX]); -//} -//#endif - -#endif // NRFX_CHECK(NRFX_UART_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_uarte.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_uarte.c deleted file mode 100644 index 6d87354a9a..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_uarte.c +++ /dev/null @@ -1,583 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include - -#if NRFX_CHECK(NRFX_UARTE_ENABLED) - -#if !(NRFX_CHECK(NRFX_UARTE0_ENABLED) || NRFX_CHECK(NRFX_UARTE1_ENABLED)) -#error "No enabled UARTE instances. Check ." -#endif - -#include -#include "prs/nrfx_prs.h" -#include - -#define NRFX_LOG_MODULE UARTE -#include - -#define EVT_TO_STR(event) \ - (event == NRF_UARTE_EVENT_ERROR ? "NRF_UARTE_EVENT_ERROR" : \ - "UNKNOWN EVENT") - -#define UARTEX_LENGTH_VALIDATE(peripheral, drv_inst_idx, len1, len2) \ - (((drv_inst_idx) == NRFX_CONCAT_3(NRFX_, peripheral, _INST_IDX)) && \ - NRFX_EASYDMA_LENGTH_VALIDATE(peripheral, len1, len2)) - -#if NRFX_CHECK(NRFX_UARTE0_ENABLED) -#define UARTE0_LENGTH_VALIDATE(...) UARTEX_LENGTH_VALIDATE(UARTE0, __VA_ARGS__) -#else -#define UARTE0_LENGTH_VALIDATE(...) 0 -#endif - -#if NRFX_CHECK(NRFX_UARTE1_ENABLED) -#define UARTE1_LENGTH_VALIDATE(...) UARTEX_LENGTH_VALIDATE(UARTE1, __VA_ARGS__) -#else -#define UARTE1_LENGTH_VALIDATE(...) 0 -#endif - -#define UARTE_LENGTH_VALIDATE(drv_inst_idx, length) \ - (UARTE0_LENGTH_VALIDATE(drv_inst_idx, length, 0) || \ - UARTE1_LENGTH_VALIDATE(drv_inst_idx, length, 0)) - - -typedef struct -{ - void * p_context; - nrfx_uarte_event_handler_t handler; - uint8_t const * p_tx_buffer; - uint8_t * p_rx_buffer; - uint8_t * p_rx_secondary_buffer; - size_t tx_buffer_length; - size_t rx_buffer_length; - size_t rx_secondary_buffer_length; - nrfx_drv_state_t state; -} uarte_control_block_t; -static uarte_control_block_t m_cb[NRFX_UARTE_ENABLED_COUNT]; - -static void apply_config(nrfx_uarte_t const * p_instance, - nrfx_uarte_config_t const * p_config) -{ - if (p_config->pseltxd != NRF_UARTE_PSEL_DISCONNECTED) - { - nrf_gpio_pin_set(p_config->pseltxd); - nrf_gpio_cfg_output(p_config->pseltxd); - } - if (p_config->pselrxd != NRF_UARTE_PSEL_DISCONNECTED) - { - nrf_gpio_cfg_input(p_config->pselrxd, NRF_GPIO_PIN_NOPULL); - } - - nrf_uarte_baudrate_set(p_instance->p_reg, p_config->baudrate); - nrf_uarte_configure(p_instance->p_reg, p_config->parity, p_config->hwfc); - nrf_uarte_txrx_pins_set(p_instance->p_reg, p_config->pseltxd, p_config->pselrxd); - if (p_config->hwfc == NRF_UARTE_HWFC_ENABLED) - { - if (p_config->pselcts != NRF_UARTE_PSEL_DISCONNECTED) - { - nrf_gpio_cfg_input(p_config->pselcts, NRF_GPIO_PIN_NOPULL); - } - if (p_config->pselrts != NRF_UARTE_PSEL_DISCONNECTED) - { - nrf_gpio_pin_set(p_config->pselrts); - nrf_gpio_cfg_output(p_config->pselrts); - } - nrf_uarte_hwfc_pins_set(p_instance->p_reg, p_config->pselrts, p_config->pselcts); - } -} - -static void interrupts_enable(nrfx_uarte_t const * p_instance, - uint8_t interrupt_priority) -{ - nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_ENDRX); - nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_ENDTX); - nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_ERROR); - nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_RXTO); - nrf_uarte_int_enable(p_instance->p_reg, NRF_UARTE_INT_ENDRX_MASK | - NRF_UARTE_INT_ENDTX_MASK | - NRF_UARTE_INT_ERROR_MASK | - NRF_UARTE_INT_RXTO_MASK); - NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number((void *)p_instance->p_reg), - interrupt_priority); - NRFX_IRQ_ENABLE(nrfx_get_irq_number((void *)p_instance->p_reg)); -} - -static void interrupts_disable(nrfx_uarte_t const * p_instance) -{ - nrf_uarte_int_disable(p_instance->p_reg, NRF_UARTE_INT_ENDRX_MASK | - NRF_UARTE_INT_ENDTX_MASK | - NRF_UARTE_INT_ERROR_MASK | - NRF_UARTE_INT_RXTO_MASK); - NRFX_IRQ_DISABLE(nrfx_get_irq_number((void *)p_instance->p_reg)); -} - -static void pins_to_default(nrfx_uarte_t const * p_instance) -{ - /* Reset pins to default states */ - uint32_t txd; - uint32_t rxd; - uint32_t rts; - uint32_t cts; - - txd = nrf_uarte_tx_pin_get(p_instance->p_reg); - rxd = nrf_uarte_rx_pin_get(p_instance->p_reg); - rts = nrf_uarte_rts_pin_get(p_instance->p_reg); - cts = nrf_uarte_cts_pin_get(p_instance->p_reg); - nrf_uarte_txrx_pins_disconnect(p_instance->p_reg); - nrf_uarte_hwfc_pins_disconnect(p_instance->p_reg); - - if (txd != NRF_UARTE_PSEL_DISCONNECTED) - { - nrf_gpio_cfg_default(txd); - } - if (rxd != NRF_UARTE_PSEL_DISCONNECTED) - { - nrf_gpio_cfg_default(rxd); - } - if (cts != NRF_UARTE_PSEL_DISCONNECTED) - { - nrf_gpio_cfg_default(cts); - } - if (rts != NRF_UARTE_PSEL_DISCONNECTED) - { - nrf_gpio_cfg_default(rts); - } -} - -nrfx_err_t nrfx_uarte_init(nrfx_uarte_t const * p_instance, - nrfx_uarte_config_t const * p_config, - nrfx_uarte_event_handler_t event_handler) -{ - NRFX_ASSERT(p_config); - uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - nrfx_err_t err_code = NRFX_SUCCESS; - - if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED) - { - err_code = NRFX_ERROR_INVALID_STATE; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - -#if NRFX_CHECK(NRFX_PRS_ENABLED) - static nrfx_irq_handler_t const irq_handlers[NRFX_UARTE_ENABLED_COUNT] = { - #if NRFX_CHECK(NRFX_UARTE0_ENABLED) - nrfx_uarte_0_irq_handler, - #endif - #if NRFX_CHECK(NRFX_UARTE1_ENABLED) - nrfx_uarte_1_irq_handler, - #endif - }; - if (nrfx_prs_acquire(p_instance->p_reg, - irq_handlers[p_instance->drv_inst_idx]) != NRFX_SUCCESS) - { - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } -#endif // NRFX_CHECK(NRFX_PRS_ENABLED) - - apply_config(p_instance, p_config); - - p_cb->handler = event_handler; - p_cb->p_context = p_config->p_context; - - if (p_cb->handler) - { - interrupts_enable(p_instance, p_config->interrupt_priority); - } - - nrf_uarte_enable(p_instance->p_reg); - p_cb->rx_buffer_length = 0; - p_cb->rx_secondary_buffer_length = 0; - p_cb->tx_buffer_length = 0; - p_cb->state = NRFX_DRV_STATE_INITIALIZED; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -void nrfx_uarte_uninit(nrfx_uarte_t const * p_instance) -{ - uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - - nrf_uarte_disable(p_instance->p_reg); - - if (p_cb->handler) - { - interrupts_disable(p_instance); - } - - pins_to_default(p_instance); - -#if NRFX_CHECK(NRFX_PRS_ENABLED) - nrfx_prs_release(p_instance->p_reg); -#endif - - p_cb->state = NRFX_DRV_STATE_UNINITIALIZED; - p_cb->handler = NULL; - NRFX_LOG_INFO("Instance uninitialized: %d.", p_instance->drv_inst_idx); -} - -nrfx_err_t nrfx_uarte_tx(nrfx_uarte_t const * p_instance, - uint8_t const * p_data, - size_t length) -{ - uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - NRFX_ASSERT(p_cb->state == NRFX_DRV_STATE_INITIALIZED); - NRFX_ASSERT(p_data); - NRFX_ASSERT(length > 0); - NRFX_ASSERT(UARTE_LENGTH_VALIDATE(p_instance->drv_inst_idx, length)); - - nrfx_err_t err_code; - - // EasyDMA requires that transfer buffers are placed in DataRAM, - // signal error if the are not. - if (!nrfx_is_in_ram(p_data)) - { - err_code = NRFX_ERROR_INVALID_ADDR; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - if (nrfx_uarte_tx_in_progress(p_instance)) - { - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - p_cb->tx_buffer_length = length; - p_cb->p_tx_buffer = p_data; - - NRFX_LOG_INFO("Transfer tx_len: %d.", p_cb->tx_buffer_length); - NRFX_LOG_DEBUG("Tx data:"); - NRFX_LOG_HEXDUMP_DEBUG(p_cb->p_tx_buffer, - p_cb->tx_buffer_length * sizeof(p_cb->p_tx_buffer[0])); - - err_code = NRFX_SUCCESS; - - nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_ENDTX); - nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_TXSTOPPED); - nrf_uarte_tx_buffer_set(p_instance->p_reg, p_cb->p_tx_buffer, p_cb->tx_buffer_length); - nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STARTTX); - - if (p_cb->handler == NULL) - { - bool endtx; - bool txstopped; - do - { - endtx = nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_ENDTX); - txstopped = nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_TXSTOPPED); - } - while ((!endtx) && (!txstopped)); - - if (txstopped) - { - err_code = NRFX_ERROR_FORBIDDEN; - } - p_cb->tx_buffer_length = 0; - } - - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -bool nrfx_uarte_tx_in_progress(nrfx_uarte_t const * p_instance) -{ - return (m_cb[p_instance->drv_inst_idx].tx_buffer_length != 0); -} - -nrfx_err_t nrfx_uarte_rx(nrfx_uarte_t const * p_instance, - uint8_t * p_data, - size_t length) -{ - uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - - NRFX_ASSERT(m_cb[p_instance->drv_inst_idx].state == NRFX_DRV_STATE_INITIALIZED); - NRFX_ASSERT(p_data); - NRFX_ASSERT(length > 0); - NRFX_ASSERT(UARTE_LENGTH_VALIDATE(p_instance->drv_inst_idx, length)); - - nrfx_err_t err_code; - - // EasyDMA requires that transfer buffers are placed in DataRAM, - // signal error if the are not. - if (!nrfx_is_in_ram(p_data)) - { - err_code = NRFX_ERROR_INVALID_ADDR; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - bool second_buffer = false; - - if (p_cb->handler) - { - nrf_uarte_int_disable(p_instance->p_reg, NRF_UARTE_INT_ERROR_MASK | - NRF_UARTE_INT_ENDRX_MASK); - } - if (p_cb->rx_buffer_length != 0) - { - if (p_cb->rx_secondary_buffer_length != 0) - { - if (p_cb->handler) - { - nrf_uarte_int_enable(p_instance->p_reg, NRF_UARTE_INT_ERROR_MASK | - NRF_UARTE_INT_ENDRX_MASK); - } - err_code = NRFX_ERROR_BUSY; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - second_buffer = true; - } - - if (!second_buffer) - { - p_cb->rx_buffer_length = length; - p_cb->p_rx_buffer = p_data; - p_cb->rx_secondary_buffer_length = 0; - } - else - { - p_cb->p_rx_secondary_buffer = p_data; - p_cb->rx_secondary_buffer_length = length; - } - - NRFX_LOG_INFO("Transfer rx_len: %d.", length); - - err_code = NRFX_SUCCESS; - - nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_ENDRX); - nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_RXTO); - nrf_uarte_rx_buffer_set(p_instance->p_reg, p_data, length); - if (!second_buffer) - { - nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STARTRX); - } - else - { - nrf_uarte_shorts_enable(p_instance->p_reg, NRF_UARTE_SHORT_ENDRX_STARTRX); - } - - if (m_cb[p_instance->drv_inst_idx].handler == NULL) - { - bool endrx; - bool rxto; - bool error; - do { - endrx = nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_ENDRX); - rxto = nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_RXTO); - error = nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_ERROR); - } while ((!endrx) && (!rxto) && (!error)); - - m_cb[p_instance->drv_inst_idx].rx_buffer_length = 0; - - if (error) - { - err_code = NRFX_ERROR_INTERNAL; - } - - if (rxto) - { - err_code = NRFX_ERROR_FORBIDDEN; - } - } - else - { - nrf_uarte_int_enable(p_instance->p_reg, NRF_UARTE_INT_ERROR_MASK | - NRF_UARTE_INT_ENDRX_MASK); - } - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -bool nrfx_uarte_rx_ready(nrfx_uarte_t const * p_instance) -{ - return nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_ENDRX); -} - -uint32_t nrfx_uarte_errorsrc_get(nrfx_uarte_t const * p_instance) -{ - nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_ERROR); - return nrf_uarte_errorsrc_get_and_clear(p_instance->p_reg); -} - -static void rx_done_event(uarte_control_block_t * p_cb, - size_t bytes, - uint8_t * p_data) -{ - nrfx_uarte_event_t event; - - event.type = NRFX_UARTE_EVT_RX_DONE; - event.data.rxtx.bytes = bytes; - event.data.rxtx.p_data = p_data; - - p_cb->handler(&event, p_cb->p_context); -} - -static void tx_done_event(uarte_control_block_t * p_cb, - size_t bytes) -{ - nrfx_uarte_event_t event; - - event.type = NRFX_UARTE_EVT_TX_DONE; - event.data.rxtx.bytes = bytes; - event.data.rxtx.p_data = (uint8_t *)p_cb->p_tx_buffer; - - p_cb->tx_buffer_length = 0; - - p_cb->handler(&event, p_cb->p_context); -} - -void nrfx_uarte_tx_abort(nrfx_uarte_t const * p_instance) -{ - uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - - nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_TXSTOPPED); - nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STOPTX); - if (p_cb->handler == NULL) - { - while (!nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_TXSTOPPED)) - {} - } - NRFX_LOG_INFO("TX transaction aborted."); -} - -void nrfx_uarte_rx_abort(nrfx_uarte_t const * p_instance) -{ - nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STOPRX); - NRFX_LOG_INFO("RX transaction aborted."); -} - -static void uarte_irq_handler(NRF_UARTE_Type * p_uarte, - uarte_control_block_t * p_cb) -{ - if (nrf_uarte_event_check(p_uarte, NRF_UARTE_EVENT_ERROR)) - { - nrfx_uarte_event_t event; - - nrf_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_ERROR); - - event.type = NRFX_UARTE_EVT_ERROR; - event.data.error.error_mask = nrf_uarte_errorsrc_get_and_clear(p_uarte); - event.data.error.rxtx.bytes = nrf_uarte_rx_amount_get(p_uarte); - event.data.error.rxtx.p_data = p_cb->p_rx_buffer; - - // Abort transfer. - p_cb->rx_buffer_length = 0; - p_cb->rx_secondary_buffer_length = 0; - - p_cb->handler(&event, p_cb->p_context); - } - else if (nrf_uarte_event_check(p_uarte, NRF_UARTE_EVENT_ENDRX)) - { - nrf_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_ENDRX); - size_t amount = nrf_uarte_rx_amount_get(p_uarte); - // If the transfer was stopped before completion, amount of transfered bytes - // will not be equal to the buffer length. Interrupted transfer is ignored. - if (amount == p_cb->rx_buffer_length) - { - if (p_cb->rx_secondary_buffer_length) - { - uint8_t * p_data = p_cb->p_rx_buffer; - nrf_uarte_shorts_disable(p_uarte, NRF_UARTE_SHORT_ENDRX_STARTRX); - p_cb->rx_buffer_length = p_cb->rx_secondary_buffer_length; - p_cb->p_rx_buffer = p_cb->p_rx_secondary_buffer; - p_cb->rx_secondary_buffer_length = 0; - rx_done_event(p_cb, amount, p_data); - } - else - { - p_cb->rx_buffer_length = 0; - rx_done_event(p_cb, amount, p_cb->p_rx_buffer); - } - } - } - - if (nrf_uarte_event_check(p_uarte, NRF_UARTE_EVENT_RXTO)) - { - nrf_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_RXTO); - if (p_cb->rx_buffer_length) - { - p_cb->rx_buffer_length = 0; - rx_done_event(p_cb, nrf_uarte_rx_amount_get(p_uarte), p_cb->p_rx_buffer); - } - } - - if (nrf_uarte_event_check(p_uarte, NRF_UARTE_EVENT_ENDTX)) - { - nrf_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_ENDTX); - if (p_cb->tx_buffer_length) - { - tx_done_event(p_cb, nrf_uarte_tx_amount_get(p_uarte)); - } - } -} - -#if NRFX_CHECK(NRFX_UARTE0_ENABLED) -void nrfx_uarte_0_irq_handler(void) -{ - uarte_irq_handler(NRF_UARTE0, &m_cb[NRFX_UARTE0_INST_IDX]); -} -#endif - -#if NRFX_CHECK(NRFX_UARTE1_ENABLED) -void nrfx_uarte_1_irq_handler(void) -{ - uarte_irq_handler(NRF_UARTE1, &m_cb[NRFX_UARTE1_INST_IDX]); -} -#endif - -#endif // NRFX_CHECK(NRFX_UARTE_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_wdt.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_wdt.c deleted file mode 100644 index 33e80c84ae..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/nrfx_wdt.c +++ /dev/null @@ -1,153 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include - -#if NRFX_CHECK(NRFX_WDT_ENABLED) -#include - -#define NRFX_LOG_MODULE WDT -#include - - -/**@brief WDT event handler. */ -static nrfx_wdt_event_handler_t m_wdt_event_handler; - -/**@brief WDT state. */ -static nrfx_drv_state_t m_state; - -/**@brief WDT alloc table. */ -static uint32_t m_alloc_index; - -/**@brief WDT interrupt handler. */ -void nrfx_wdt_irq_handler(void) -{ - if (nrf_wdt_int_enable_check(NRF_WDT_INT_TIMEOUT_MASK) == true) - { - nrf_wdt_event_clear(NRF_WDT_EVENT_TIMEOUT); - m_wdt_event_handler(); - } -} - - -nrfx_err_t nrfx_wdt_init(nrfx_wdt_config_t const * p_config, - nrfx_wdt_event_handler_t wdt_event_handler) -{ - NRFX_ASSERT(p_config); - NRFX_ASSERT(wdt_event_handler != NULL); - nrfx_err_t err_code; - m_wdt_event_handler = wdt_event_handler; - - if (m_state == NRFX_DRV_STATE_UNINITIALIZED) - { - m_state = NRFX_DRV_STATE_INITIALIZED; - } - else - { - err_code = NRFX_ERROR_INVALID_STATE; - NRFX_LOG_WARNING("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - nrf_wdt_behaviour_set(p_config->behaviour); - - nrf_wdt_reload_value_set((p_config->reload_value * 32768) / 1000); - - NRFX_IRQ_PRIORITY_SET(WDT_IRQn, p_config->interrupt_priority); - NRFX_IRQ_ENABLE(WDT_IRQn); - - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - - -void nrfx_wdt_enable(void) -{ - NRFX_ASSERT(m_alloc_index != 0); - NRFX_ASSERT(m_state == NRFX_DRV_STATE_INITIALIZED); - nrf_wdt_int_enable(NRF_WDT_INT_TIMEOUT_MASK); - nrf_wdt_task_trigger(NRF_WDT_TASK_START); - m_state = NRFX_DRV_STATE_POWERED_ON; - NRFX_LOG_INFO("Enabled."); -} - - -void nrfx_wdt_feed(void) -{ - NRFX_ASSERT(m_state == NRFX_DRV_STATE_POWERED_ON); - for (uint32_t i = 0; i < m_alloc_index; i++) - { - nrf_wdt_reload_request_set((nrf_wdt_rr_register_t)(NRF_WDT_RR0 + i)); - } -} - -nrfx_err_t nrfx_wdt_channel_alloc(nrfx_wdt_channel_id * p_channel_id) -{ - nrfx_err_t result; - NRFX_ASSERT(p_channel_id); - NRFX_ASSERT(m_state == NRFX_DRV_STATE_INITIALIZED); - - NRFX_CRITICAL_SECTION_ENTER(); - if (m_alloc_index < NRF_WDT_CHANNEL_NUMBER) - { - *p_channel_id = (nrfx_wdt_channel_id)(NRF_WDT_RR0 + m_alloc_index); - m_alloc_index++; - nrf_wdt_reload_request_enable(*p_channel_id); - result = NRFX_SUCCESS; - } - else - { - result = NRFX_ERROR_NO_MEM; - } - NRFX_CRITICAL_SECTION_EXIT(); - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(result)); - return result; -} - -void nrfx_wdt_channel_feed(nrfx_wdt_channel_id channel_id) -{ - NRFX_ASSERT(m_state == NRFX_DRV_STATE_POWERED_ON); - nrf_wdt_reload_request_set(channel_id); -} - -#endif // NRFX_CHECK(NRFX_WDT_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/prs/nrfx_prs.c b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/prs/nrfx_prs.c deleted file mode 100644 index 4993993af2..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/prs/nrfx_prs.c +++ /dev/null @@ -1,166 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include - -#if NRFX_CHECK(NRFX_PRS_ENABLED) -#include "nrfx_prs.h" - -#define NRFX_LOG_MODULE PRS -#include - -#define LOG_FUNCTION_EXIT(level, ret_code) \ - NRFX_LOG_##level("Function: %s, error code: %s.", \ - __func__, \ - NRFX_LOG_ERROR_STRING_GET(ret_code)) - - -typedef struct { - nrfx_irq_handler_t handler; - bool acquired; -} prs_box_t; - -#define PRS_BOX_DEFINE(n) \ - static prs_box_t m_prs_box_##n = { .handler = NULL, .acquired = false }; \ - void nrfx_prs_box_##n##_irq_handler(void) \ - { \ - NRFX_ASSERT(m_prs_box_##n.handler); \ - m_prs_box_##n.handler(); \ - } - -#if defined(NRFX_PRS_BOX_0_ADDR) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED) -PRS_BOX_DEFINE(0) -#endif -#if defined(NRFX_PRS_BOX_1_ADDR) && NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED) -PRS_BOX_DEFINE(1) -#endif -#if defined(NRFX_PRS_BOX_2_ADDR) && NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED) -PRS_BOX_DEFINE(2) -#endif -#if defined(NRFX_PRS_BOX_3_ADDR) && NRFX_CHECK(NRFX_PRS_BOX_3_ENABLED) -PRS_BOX_DEFINE(3) -#endif -#if defined(NRFX_PRS_BOX_4_ADDR) && NRFX_CHECK(NRFX_PRS_BOX_4_ENABLED) -PRS_BOX_DEFINE(4) -#endif - - -static prs_box_t * prs_box_get(void const * p_base_addr) -{ -#if !defined(IS_PRS_BOX) -#define IS_PRS_BOX(n, p_base_addr) ((p_base_addr) == NRFX_PRS_BOX_##n##_ADDR) -#endif - -#if defined(NRFX_PRS_BOX_0_ADDR) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED) - if (IS_PRS_BOX(0, p_base_addr)) { return &m_prs_box_0; } - else -#endif -#if defined(NRFX_PRS_BOX_1_ADDR) && NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED) - if (IS_PRS_BOX(1, p_base_addr)) { return &m_prs_box_1; } - else -#endif -#if defined(NRFX_PRS_BOX_2_ADDR) && NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED) - if (IS_PRS_BOX(2, p_base_addr)) { return &m_prs_box_2; } - else -#endif -#if defined(NRFX_PRS_BOX_3_ADDR) && NRFX_CHECK(NRFX_PRS_BOX_3_ENABLED) - if (IS_PRS_BOX(3, p_base_addr)) { return &m_prs_box_3; } - else -#endif -#if defined(NRFX_PRS_BOX_4_ADDR) && NRFX_CHECK(NRFX_PRS_BOX_4_ENABLED) - if (IS_PRS_BOX(4, p_base_addr)) { return &m_prs_box_4; } - else -#endif - { - return NULL; - } -} - -nrfx_err_t nrfx_prs_acquire(void const * p_base_addr, - nrfx_irq_handler_t irq_handler) -{ - NRFX_ASSERT(p_base_addr); - - nrfx_err_t ret_code; - - prs_box_t * p_box = prs_box_get(p_base_addr); - if (p_box != NULL) - { - bool busy = false; - - NRFX_CRITICAL_SECTION_ENTER(); - if (p_box->acquired) - { - busy = true; - } - else - { - p_box->handler = irq_handler; - p_box->acquired = true; - } - NRFX_CRITICAL_SECTION_EXIT(); - - if (busy) - { - ret_code = NRFX_ERROR_BUSY; - LOG_FUNCTION_EXIT(WARNING, ret_code); - return ret_code; - } - } - - ret_code = NRFX_SUCCESS; - LOG_FUNCTION_EXIT(INFO, ret_code); - return ret_code; -} - -void nrfx_prs_release(void const * p_base_addr) -{ - NRFX_ASSERT(p_base_addr); - - prs_box_t * p_box = prs_box_get(p_base_addr); - if (p_box != NULL) - { - p_box->handler = NULL; - p_box->acquired = false; - } -} - - -#endif // NRFX_CHECK(NRFX_PRS_ENABLED) diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/prs/nrfx_prs.h b/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/prs/nrfx_prs.h deleted file mode 100644 index 7c9c540f8b..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/drivers/src/prs/nrfx_prs.h +++ /dev/null @@ -1,140 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_PRS_H__ -#define NRFX_PRS_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_prs Peripheral Resource Sharing (PRS) - * @{ - * @ingroup nrfx - * - * @brief Peripheral Resource Sharing interface (PRS). - */ - -#if defined(NRF51) - // SPI0, TWI0 - #define NRFX_PRS_BOX_0_ADDR NRF_SPI0 - // SPI1, SPIS1, TWI1 - #define NRFX_PRS_BOX_1_ADDR NRF_SPI1 -#elif defined(NRF52810_XXAA) - // TWIM0, TWIS0 - #define NRFX_PRS_BOX_0_ADDR NRF_TWIM0 - // SPIM0, SPIS0 - #define NRFX_PRS_BOX_1_ADDR NRF_SPIM0 -#elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB) - // SPIM0, SPIS0, TWIM0, TWIS0, SPI0, TWI0 - #define NRFX_PRS_BOX_0_ADDR NRF_SPIM0 - // SPIM1, SPIS1, TWIM1, TWIS1, SPI1, TWI1 - #define NRFX_PRS_BOX_1_ADDR NRF_SPIM1 - // SPIM2, SPIS2, SPI2 - #define NRFX_PRS_BOX_2_ADDR NRF_SPIM2 - // COMP, LPCOMP - #define NRFX_PRS_BOX_3_ADDR NRF_COMP - // UARTE0, UART0 - #define NRFX_PRS_BOX_4_ADDR NRF_UARTE0 -#elif defined(NRF52840_XXAA) - // SPIM0, SPIS0, TWIM0, TWIS0, SPI0, TWI0 - #define NRFX_PRS_BOX_0_ADDR NRF_SPIM0 - // SPIM1, SPIS1, TWIM1, TWIS1, SPI1, TWI1 - #define NRFX_PRS_BOX_1_ADDR NRF_SPIM1 - // SPIM2, SPIS2, SPI2 - #define NRFX_PRS_BOX_2_ADDR NRF_SPIM2 - // COMP, LPCOMP - #define NRFX_PRS_BOX_3_ADDR NRF_COMP - // UARTE0, UART0 - #define NRFX_PRS_BOX_4_ADDR NRF_UARTE0 -#else - #error "Unknown device." -#endif - -/** - * @brief Function for acquiring shared peripheral resources associated with - * the specified peripheral. - * - * Certain resources and registers are shared among peripherals that have - * the same ID (for example: SPI0, SPIM0, SPIS0, TWI0, TWIM0, and TWIS0 in - * nRF52832). Only one of them can be utilized at a given time. This function - * reserves proper resources to be used by the specified peripheral. - * If NRFX_PRS_ENABLED is set to a non-zero value, IRQ handlers for peripherals - * that are sharing resources with others are implemented by the @ref nrfx_prs - * module instead of individual drivers. The drivers must then specify their - * interrupt handling routines and register them by using this function. - * - * @param[in] p_base_addr Requested peripheral base pointer. - * @param[in] irq_handler Interrupt handler to register. - * - * @retval NRFX_SUCCESS If resources were acquired successfully or the - * specified peripheral is not handled by the PRS - * subsystem and there is no need to acquire resources - * for it. - * @retval NRFX_ERROR_BUSY If resources were already acquired. - */ -nrfx_err_t nrfx_prs_acquire(void const * p_base_addr, - nrfx_irq_handler_t irq_handler); - -/** - * @brief Function for releasing shared resources reserved previously by - * @ref nrfx_prs_acquire() for the specified peripheral. - * - * @param[in] p_base_addr Released peripheral base pointer. - */ -void nrfx_prs_release(void const * p_base_addr); - - -void nrfx_prs_box_0_irq_handler(void); -void nrfx_prs_box_1_irq_handler(void); -void nrfx_prs_box_2_irq_handler(void); -void nrfx_prs_box_3_irq_handler(void); -void nrfx_prs_box_4_irq_handler(void); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_PRS_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_adc.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_adc.h deleted file mode 100644 index 75b0e0931c..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_adc.h +++ /dev/null @@ -1,348 +0,0 @@ -/** - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_ADC_H_ -#define NRF_ADC_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_adc_hal ADC HAL - * @{ - * @ingroup nrf_adc - * @brief Hardware access layer for managing the Analog-to-Digital Converter (ADC) - * peripheral. - */ - -/** @brief ADC interrupts. */ -typedef enum -{ - NRF_ADC_INT_END_MASK = ADC_INTENSET_END_Msk, /**< ADC interrupt on END event. */ -} nrf_adc_int_mask_t; - -/** @brief Resolution of the analog-to-digital converter. */ -typedef enum -{ - NRF_ADC_CONFIG_RES_8BIT = ADC_CONFIG_RES_8bit, /**< 8-bit resolution. */ - NRF_ADC_CONFIG_RES_9BIT = ADC_CONFIG_RES_9bit, /**< 9-bit resolution. */ - NRF_ADC_CONFIG_RES_10BIT = ADC_CONFIG_RES_10bit, /**< 10-bit resolution. */ -} nrf_adc_config_resolution_t; - - -/** @brief Scaling factor of the analog-to-digital conversion. */ -typedef enum -{ - NRF_ADC_CONFIG_SCALING_INPUT_FULL_SCALE = ADC_CONFIG_INPSEL_AnalogInputNoPrescaling, /**< Full scale input. */ - NRF_ADC_CONFIG_SCALING_INPUT_TWO_THIRDS = ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling, /**< 2/3 scale input. */ - NRF_ADC_CONFIG_SCALING_INPUT_ONE_THIRD = ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling, /**< 1/3 scale input. */ - NRF_ADC_CONFIG_SCALING_SUPPLY_TWO_THIRDS = ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling, /**< 2/3 of supply. */ - NRF_ADC_CONFIG_SCALING_SUPPLY_ONE_THIRD = ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling /**< 1/3 of supply. */ -} nrf_adc_config_scaling_t; - - -/** - * @brief External reference selection of the analog-to-digital converter. - */ -typedef enum -{ - NRF_ADC_CONFIG_EXTREFSEL_NONE = ADC_CONFIG_EXTREFSEL_None, /**< Analog reference inputs disabled. */ - NRF_ADC_CONFIG_EXTREFSEL_AREF0 = ADC_CONFIG_EXTREFSEL_AnalogReference0, /**< AREF0 as analog reference. */ - NRF_ADC_CONFIG_EXTREFSEL_AREF1 = ADC_CONFIG_EXTREFSEL_AnalogReference1 /**< AREF1 as analog reference. */ -} nrf_adc_config_extref_t; - -/** - * @brief Reference selection of the analog-to-digital converter. - */ -typedef enum -{ - NRF_ADC_CONFIG_REF_VBG = ADC_CONFIG_REFSEL_VBG, /**< 1.2 V reference. */ - NRF_ADC_CONFIG_REF_SUPPLY_ONE_HALF = ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling, /**< 1/2 of power supply. */ - NRF_ADC_CONFIG_REF_SUPPLY_ONE_THIRD = ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling, /**< 1/3 of power supply. */ - NRF_ADC_CONFIG_REF_EXT = ADC_CONFIG_REFSEL_External /**< External reference. See @ref nrf_adc_config_extref_t for further configuration.*/ -} nrf_adc_config_reference_t; - -/** @brief Input selection of the analog-to-digital converter. */ -typedef enum -{ - NRF_ADC_CONFIG_INPUT_DISABLED = ADC_CONFIG_PSEL_Disabled, /**< No input selected. */ - NRF_ADC_CONFIG_INPUT_0 = ADC_CONFIG_PSEL_AnalogInput0, /**< Input 0. */ - NRF_ADC_CONFIG_INPUT_1 = ADC_CONFIG_PSEL_AnalogInput1, /**< Input 1. */ - NRF_ADC_CONFIG_INPUT_2 = ADC_CONFIG_PSEL_AnalogInput2, /**< Input 2. */ - NRF_ADC_CONFIG_INPUT_3 = ADC_CONFIG_PSEL_AnalogInput3, /**< Input 3. */ - NRF_ADC_CONFIG_INPUT_4 = ADC_CONFIG_PSEL_AnalogInput4, /**< Input 4. */ - NRF_ADC_CONFIG_INPUT_5 = ADC_CONFIG_PSEL_AnalogInput5, /**< Input 5. */ - NRF_ADC_CONFIG_INPUT_6 = ADC_CONFIG_PSEL_AnalogInput6, /**< Input 6. */ - NRF_ADC_CONFIG_INPUT_7 = ADC_CONFIG_PSEL_AnalogInput7, /**< Input 7. */ -} nrf_adc_config_input_t; - -/** @brief Analog-to-digital converter tasks. */ -typedef enum -{ - /*lint -save -e30*/ - NRF_ADC_TASK_START = offsetof(NRF_ADC_Type, TASKS_START), /**< ADC start sampling task. */ - NRF_ADC_TASK_STOP = offsetof(NRF_ADC_Type, TASKS_STOP) /**< ADC stop sampling task. */ - /*lint -restore*/ -} nrf_adc_task_t; - -/** @brief Analog-to-digital converter events. */ -typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ -{ - /*lint -save -e30*/ - NRF_ADC_EVENT_END = offsetof(NRF_ADC_Type, EVENTS_END) /**< End of a conversion event. */ - /*lint -restore*/ -} nrf_adc_event_t; - -/**@brief Analog-to-digital converter configuration. */ -typedef struct -{ - nrf_adc_config_resolution_t resolution; /**< ADC resolution. */ - nrf_adc_config_scaling_t scaling; /**< ADC scaling factor. */ - nrf_adc_config_reference_t reference; /**< ADC reference. */ - nrf_adc_config_input_t input; /**< ADC input selection. */ - nrf_adc_config_extref_t extref; /**< ADC external reference selection. */ -} nrf_adc_config_t; - -/**@brief Analog-to-digital value type. */ -typedef uint16_t nrf_adc_value_t; - -/** - * @brief Function for activating a specific ADC task. - * - * @param[in] task Task to activate. - */ -__STATIC_INLINE void nrf_adc_task_trigger(nrf_adc_task_t task); - -/** - * @brief Function for getting the address of an ADC task register. - * - * @param[in] task ADC task. - * - * @return Address of the specified ADC task. - */ -__STATIC_INLINE uint32_t nrf_adc_task_address_get(nrf_adc_task_t task); - -/** - * @brief Function for checking the state of an ADC event. - * - * @param[in] event Event to check. - * - * @retval true If the event is set. - * @retval false If the event is not set. - */ -__STATIC_INLINE bool nrf_adc_event_check(nrf_adc_event_t event); - -/** - * @brief Function for clearing an ADC event. - * - * @param[in] event Event to clear. - */ -__STATIC_INLINE void nrf_adc_event_clear(nrf_adc_event_t event); - -/** - * @brief Function for getting the address of a specific ADC event register. - * - * @param[in] adc_event ADC event. - * - * @return Address of the specified ADC event. - */ -__STATIC_INLINE uint32_t nrf_adc_event_address_get(nrf_adc_event_t adc_event); - -/** - * @brief Function for enabling the specified interrupts. - * - * @param[in] int_mask Interrupts to enable. - */ -__STATIC_INLINE void nrf_adc_int_enable(uint32_t int_mask); - -/** - * @brief Function for disabling the specified interrupts. - * - * @param[in] int_mask Interrupts to disable. - */ -__STATIC_INLINE void nrf_adc_int_disable(uint32_t int_mask); - -/** - * @brief Function for retrieving the state of the specified ADC interrupts. - * - * @param[in] int_mask Interrupts to check. - * - * @retval true If all specified interrupts are enabled. - * @retval false If at least one of the given interrupts is not enabled. - */ -__STATIC_INLINE bool nrf_adc_int_enable_check(uint32_t int_mask); - -/** - * @brief Function for checking whether the ADC is busy. - * - * This function checks whether the ADC converter is busy with a conversion. - * - * @retval true If the ADC is busy. - * @retval false If the ADC is not busy. - */ -__STATIC_INLINE bool nrf_adc_busy_check(void); - -/** - * @brief Function for enabling the ADC. - * - */ -__STATIC_INLINE void nrf_adc_enable(void); - -/** - * @brief Function for disabling the ADC. - * - */ -__STATIC_INLINE void nrf_adc_disable(void); - -/** - * @brief Function for checking if the ADC is enabled. - * - * @retval true If the ADC is enabled. - * @retval false If the ADC is not enabled. - */ -__STATIC_INLINE bool nrf_adc_enable_check(void); - -/** - * @brief Function for retrieving the ADC conversion result. - * - * This function retrieves and returns the last analog-to-digital conversion result. - * - * @return Last conversion result. - */ -__STATIC_INLINE nrf_adc_value_t nrf_adc_result_get(void); - -/** - * @brief Function for initializing the ADC. - * - * This function writes data to ADC's CONFIG register. After the configuration, - * the ADC is in DISABLE state and must be enabled before using it. - * - * @param[in] p_config Configuration parameters. - */ -__STATIC_INLINE void nrf_adc_init(nrf_adc_config_t const * p_config); - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -__STATIC_INLINE void nrf_adc_task_trigger(nrf_adc_task_t task) -{ - *((volatile uint32_t *)((uint8_t *)NRF_ADC + (uint32_t)task)) = 0x1UL; -} - -__STATIC_INLINE uint32_t nrf_adc_task_address_get(nrf_adc_task_t adc_task) -{ - return (uint32_t)((uint8_t *)NRF_ADC + (uint32_t)adc_task); -} - -__STATIC_INLINE bool nrf_adc_event_check(nrf_adc_event_t event) -{ - return (bool)*(volatile uint32_t *)((uint8_t *)NRF_ADC + (uint32_t)event); -} - -__STATIC_INLINE void nrf_adc_event_clear(nrf_adc_event_t event) -{ - *((volatile uint32_t *)((uint8_t *)NRF_ADC + (uint32_t)event)) = 0x0UL; -} - -__STATIC_INLINE uint32_t nrf_adc_event_address_get(nrf_adc_event_t adc_event) -{ - return (uint32_t)((uint8_t *)NRF_ADC + (uint32_t)adc_event); -} - -__STATIC_INLINE void nrf_adc_int_enable(uint32_t int_mask) -{ - NRF_ADC->INTENSET = int_mask; -} - -__STATIC_INLINE void nrf_adc_int_disable(uint32_t int_mask) -{ - NRF_ADC->INTENCLR = int_mask; -} - -__STATIC_INLINE bool nrf_adc_int_enable_check(uint32_t int_mask) -{ - return (bool)(NRF_ADC->INTENSET & int_mask); -} - -__STATIC_INLINE bool nrf_adc_busy_check(void) -{ - return ((NRF_ADC->BUSY & ADC_BUSY_BUSY_Msk) == (ADC_BUSY_BUSY_Busy << ADC_BUSY_BUSY_Pos)); -} - -__STATIC_INLINE void nrf_adc_enable(void) -{ - NRF_ADC->ENABLE = (ADC_ENABLE_ENABLE_Enabled << ADC_ENABLE_ENABLE_Pos); -} - -__STATIC_INLINE void nrf_adc_disable(void) -{ - NRF_ADC->ENABLE = (ADC_ENABLE_ENABLE_Disabled << ADC_ENABLE_ENABLE_Pos); -} - -__STATIC_INLINE bool nrf_adc_enable_check(void) -{ - return (NRF_ADC->ENABLE == (ADC_ENABLE_ENABLE_Enabled << ADC_ENABLE_ENABLE_Pos)); -} - -__STATIC_INLINE nrf_adc_value_t nrf_adc_result_get(void) -{ - return (nrf_adc_value_t)NRF_ADC->RESULT; -} - -__STATIC_INLINE void nrf_adc_init(nrf_adc_config_t const * p_config) -{ - NRF_ADC->CONFIG = - ((p_config->resolution << ADC_CONFIG_RES_Pos) & ADC_CONFIG_RES_Msk) - |((p_config->scaling << ADC_CONFIG_INPSEL_Pos) & ADC_CONFIG_INPSEL_Msk) - |((p_config->reference << ADC_CONFIG_REFSEL_Pos) & ADC_CONFIG_REFSEL_Msk) - |((p_config->input << ADC_CONFIG_PSEL_Pos) & ADC_CONFIG_PSEL_Msk) - |((p_config->extref << ADC_CONFIG_EXTREFSEL_Pos) & ADC_CONFIG_EXTREFSEL_Msk); -} - -#endif // SUPPRESS_INLINE_IMPLEMENTATION -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* NRF_ADC_H_ */ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_clock.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_clock.h deleted file mode 100644 index f1281393e0..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_clock.h +++ /dev/null @@ -1,400 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_CLOCK_H__ -#define NRF_CLOCK_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_clock_hal Clock HAL - * @{ - * @ingroup nrf_clock - * @brief Hardware access layer for managing the CLOCK peripheral. - * - * This code can be used to managing low-frequency clock (LFCLK) and the high-frequency clock - * (HFCLK) settings. - */ - -#define NRF_CLOCK_TASK_TRIGGER (1UL) -#define NRF_CLOCK_EVENT_CLEAR (0UL) - -/** - * @brief Low-frequency clock sources. - * @details Used by LFCLKSRC, LFCLKSTAT, and LFCLKSRCCOPY registers. - */ -typedef enum -{ - NRF_CLOCK_LFCLK_RC = CLOCK_LFCLKSRC_SRC_RC, /**< Internal 32 kHz RC oscillator. */ - NRF_CLOCK_LFCLK_Xtal = CLOCK_LFCLKSRC_SRC_Xtal, /**< External 32 kHz crystal. */ - NRF_CLOCK_LFCLK_Synth = CLOCK_LFCLKSRC_SRC_Synth /**< Internal 32 kHz synthesizer from HFCLK system clock. */ -} nrf_clock_lfclk_t; - -/** - * @brief High-frequency clock sources. - */ -typedef enum -{ - NRF_CLOCK_HFCLK_LOW_ACCURACY = CLOCK_HFCLKSTAT_SRC_RC, /**< Internal 16 MHz RC oscillator. */ - NRF_CLOCK_HFCLK_HIGH_ACCURACY = CLOCK_HFCLKSTAT_SRC_Xtal /**< External 16 MHz/32 MHz crystal oscillator. */ -} nrf_clock_hfclk_t; - -/** - * @brief Trigger status of task LFCLKSTART/HFCLKSTART. - * @details Used by LFCLKRUN and HFCLKRUN registers. - */ -typedef enum -{ - NRF_CLOCK_START_TASK_NOT_TRIGGERED = CLOCK_LFCLKRUN_STATUS_NotTriggered, /**< Task LFCLKSTART/HFCLKSTART has not been triggered. */ - NRF_CLOCK_START_TASK_TRIGGERED = CLOCK_LFCLKRUN_STATUS_Triggered /**< Task LFCLKSTART/HFCLKSTART has been triggered. */ -} nrf_clock_start_task_status_t; - -/** - * @brief Interrupts. - */ -typedef enum -{ - NRF_CLOCK_INT_HF_STARTED_MASK = CLOCK_INTENSET_HFCLKSTARTED_Msk, /**< Interrupt on HFCLKSTARTED event. */ - NRF_CLOCK_INT_LF_STARTED_MASK = CLOCK_INTENSET_LFCLKSTARTED_Msk, /**< Interrupt on LFCLKSTARTED event. */ - NRF_CLOCK_INT_DONE_MASK = CLOCK_INTENSET_DONE_Msk, /**< Interrupt on DONE event. */ - NRF_CLOCK_INT_CTTO_MASK = CLOCK_INTENSET_CTTO_Msk /**< Interrupt on CTTO event. */ -} nrf_clock_int_mask_t; - -/** - * @brief Tasks. - * - * @details The NRF_CLOCK_TASK_LFCLKSTOP task cannot be set when the low-frequency clock is not running. - * The NRF_CLOCK_TASK_HFCLKSTOP task cannot be set when the high-frequency clock is not running. - */ -typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ -{ - NRF_CLOCK_TASK_HFCLKSTART = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTART), /**< Start HFCLK clock source.*/ - NRF_CLOCK_TASK_HFCLKSTOP = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTOP), /**< Stop HFCLK clock source.*/ - NRF_CLOCK_TASK_LFCLKSTART = offsetof(NRF_CLOCK_Type, TASKS_LFCLKSTART), /**< Start LFCLK clock source.*/ - NRF_CLOCK_TASK_LFCLKSTOP = offsetof(NRF_CLOCK_Type, TASKS_LFCLKSTOP), /**< Stop LFCLK clock source.*/ - NRF_CLOCK_TASK_CAL = offsetof(NRF_CLOCK_Type, TASKS_CAL), /**< Start calibration of LFCLK RC oscillator.*/ - NRF_CLOCK_TASK_CTSTART = offsetof(NRF_CLOCK_Type, TASKS_CTSTART), /**< Start calibration timer.*/ - NRF_CLOCK_TASK_CTSTOP = offsetof(NRF_CLOCK_Type, TASKS_CTSTOP) /**< Stop calibration timer.*/ -} nrf_clock_task_t; /*lint -restore */ - -/** - * @brief Events. - */ -typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ -{ - NRF_CLOCK_EVENT_HFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_HFCLKSTARTED), /**< HFCLK oscillator started.*/ - NRF_CLOCK_EVENT_LFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_LFCLKSTARTED), /**< LFCLK oscillator started.*/ - NRF_CLOCK_EVENT_DONE = offsetof(NRF_CLOCK_Type, EVENTS_DONE), /**< Calibration of LFCLK RC oscillator completed.*/ - NRF_CLOCK_EVENT_CTTO = offsetof(NRF_CLOCK_Type, EVENTS_CTTO) /**< Calibration timer time-out.*/ -} nrf_clock_event_t; /*lint -restore */ - -/** - * @brief Function for enabling a specific interrupt. - * - * @param[in] int_mask Interrupt. - */ -__STATIC_INLINE void nrf_clock_int_enable(uint32_t int_mask); - -/** - * @brief Function for disabling a specific interrupt. - * - * @param[in] int_mask Interrupt. - */ -__STATIC_INLINE void nrf_clock_int_disable(uint32_t int_mask); - -/** - * @brief Function for retrieving the state of a specific interrupt. - * - * @param[in] int_mask Interrupt. - * - * @retval true If the interrupt is enabled. - * @retval false If the interrupt is not enabled. - */ -__STATIC_INLINE bool nrf_clock_int_enable_check(nrf_clock_int_mask_t int_mask); - -/** - * @brief Function for retrieving the address of a specific task. - * @details This function can be used by the PPI module. - * - * @param[in] task Task. - * - * @return Address of the requested task register. - */ -__STATIC_INLINE uint32_t nrf_clock_task_address_get(nrf_clock_task_t task); - -/** - * @brief Function for setting a specific task. - * - * @param[in] task Task. - */ -__STATIC_INLINE void nrf_clock_task_trigger(nrf_clock_task_t task); - -/** - * @brief Function for retrieving the address of a specific event. - * @details This function can be used by the PPI module. - * - * @param[in] event Event. - * - * @return Address of the requested event register. - */ -__STATIC_INLINE uint32_t nrf_clock_event_address_get(nrf_clock_event_t event); - -/** - * @brief Function for clearing a specific event. - * - * @param[in] event Event. - */ -__STATIC_INLINE void nrf_clock_event_clear(nrf_clock_event_t event); - -/** - * @brief Function for retrieving the state of a specific event. - * - * @param[in] event Event. - * - * @retval true If the event is set. - * @retval false If the event is not set. - */ -__STATIC_INLINE bool nrf_clock_event_check(nrf_clock_event_t event); - -/** - * @brief Function for changing the low-frequency clock source. - * @details This function cannot be called when the low-frequency clock is running. - * - * @param[in] source New low-frequency clock source. - * - */ -__STATIC_INLINE void nrf_clock_lf_src_set(nrf_clock_lfclk_t source); - -/** - * @brief Function for retrieving the selected source for the low-frequency clock. - * - * @retval NRF_CLOCK_LFCLK_RC If the internal 32 kHz RC oscillator is the selected source for the low-frequency clock. - * @retval NRF_CLOCK_LFCLK_Xtal If an external 32 kHz crystal oscillator is the selected source for the low-frequency clock. - * @retval NRF_CLOCK_LFCLK_Synth If the internal 32 kHz synthesizer from the HFCLK is the selected source for the low-frequency clock. - */ -__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(void); - -/** - * @brief Function for retrieving the active source of the low-frequency clock. - * - * @retval NRF_CLOCK_LFCLK_RC If the internal 32 kHz RC oscillator is the active source of the low-frequency clock. - * @retval NRF_CLOCK_LFCLK_Xtal If an external 32 kHz crystal oscillator is the active source of the low-frequency clock. - * @retval NRF_CLOCK_LFCLK_Synth If the internal 32 kHz synthesizer from the HFCLK is the active source of the low-frequency clock. - */ -__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(void); - -/** - * @brief Function for retrieving the clock source for the LFCLK clock when the task LKCLKSTART is triggered. - * - * @retval NRF_CLOCK_LFCLK_RC If the internal 32 kHz RC oscillator is running and generating the LFCLK clock. - * @retval NRF_CLOCK_LFCLK_Xtal If an external 32 kHz crystal oscillator is running and generating the LFCLK clock. - * @retval NRF_CLOCK_LFCLK_Synth If the internal 32 kHz synthesizer from the HFCLK is running and generating the LFCLK clock. - */ -__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(void); - -/** - * @brief Function for retrieving the state of the LFCLK clock. - * - * @retval false If the LFCLK clock is not running. - * @retval true If the LFCLK clock is running. - */ -__STATIC_INLINE bool nrf_clock_lf_is_running(void); - -/** - * @brief Function for retrieving the trigger status of the task LFCLKSTART. - * - * @retval NRF_CLOCK_START_TASK_NOT_TRIGGERED If the task LFCLKSTART has not been triggered. - * @retval NRF_CLOCK_START_TASK_TRIGGERED If the task LFCLKSTART has been triggered. - */ -__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_lf_start_task_status_get(void); - -/** - * @brief Function for retrieving the active source of the high-frequency clock. - * - * @retval NRF_CLOCK_HFCLK_LOW_ACCURACY If the internal 16 MHz RC oscillator is the active source of the high-frequency clock. - * @retval NRF_CLOCK_HFCLK_HIGH_ACCURACY If an external 16 MHz/32 MHz crystal oscillator is the active source of the high-frequency clock. - */ -__STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hf_src_get(void); - -/** - * @brief Function for retrieving the state of the HFCLK clock. - * - * @param[in] clk_src Clock source to be checked. - * - * @retval false If the HFCLK clock is not running. - * @retval true If the HFCLK clock is running. - */ -__STATIC_INLINE bool nrf_clock_hf_is_running(nrf_clock_hfclk_t clk_src); - -/** - * @brief Function for retrieving the trigger status of the task HFCLKSTART. - * - * @retval NRF_CLOCK_START_TASK_NOT_TRIGGERED If the task HFCLKSTART has not been triggered. - * @retval NRF_CLOCK_START_TASK_TRIGGERED If the task HFCLKSTART has been triggered. - */ -__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_hf_start_task_status_get(void); - -/** - * @brief Function for changing the calibration timer interval. - * - * @param[in] interval New calibration timer interval in 0.25 s resolution (range: 0.25 seconds to 31.75 seconds). - */ -__STATIC_INLINE void nrf_clock_cal_timer_timeout_set(uint32_t interval); - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -__STATIC_INLINE void nrf_clock_int_enable(uint32_t int_mask) -{ - NRF_CLOCK->INTENSET = int_mask; -} - -__STATIC_INLINE void nrf_clock_int_disable(uint32_t int_mask) -{ - NRF_CLOCK->INTENCLR = int_mask; -} - -__STATIC_INLINE bool nrf_clock_int_enable_check(nrf_clock_int_mask_t int_mask) -{ - return (bool)(NRF_CLOCK->INTENCLR & int_mask); -} - -__STATIC_INLINE uint32_t nrf_clock_task_address_get(nrf_clock_task_t task) -{ - return ((uint32_t )NRF_CLOCK + task); -} - -__STATIC_INLINE void nrf_clock_task_trigger(nrf_clock_task_t task) -{ - *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + task)) = NRF_CLOCK_TASK_TRIGGER; -} - -__STATIC_INLINE uint32_t nrf_clock_event_address_get(nrf_clock_event_t event) -{ - return ((uint32_t)NRF_CLOCK + event); -} - -__STATIC_INLINE void nrf_clock_event_clear(nrf_clock_event_t event) -{ - *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + event)) = NRF_CLOCK_EVENT_CLEAR; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + event)); - (void)dummy; -#endif -} - -__STATIC_INLINE bool nrf_clock_event_check(nrf_clock_event_t event) -{ - return (bool)*((volatile uint32_t *)((uint8_t *)NRF_CLOCK + event)); -} - -__STATIC_INLINE void nrf_clock_lf_src_set(nrf_clock_lfclk_t source) -{ - NRF_CLOCK->LFCLKSRC = - (uint32_t)((source << CLOCK_LFCLKSRC_SRC_Pos) & CLOCK_LFCLKSRC_SRC_Msk); -} - -__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(void) -{ - return (nrf_clock_lfclk_t)((NRF_CLOCK->LFCLKSRC & - CLOCK_LFCLKSRC_SRC_Msk) >> CLOCK_LFCLKSRC_SRC_Pos); -} - -__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(void) -{ - return (nrf_clock_lfclk_t)((NRF_CLOCK->LFCLKSTAT & - CLOCK_LFCLKSTAT_SRC_Msk) >> CLOCK_LFCLKSTAT_SRC_Pos); -} - -__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(void) -{ - return (nrf_clock_lfclk_t)((NRF_CLOCK->LFCLKSRCCOPY & - CLOCK_LFCLKSRCCOPY_SRC_Msk) >> CLOCK_LFCLKSRCCOPY_SRC_Pos); -} - -__STATIC_INLINE bool nrf_clock_lf_is_running(void) -{ - return ((NRF_CLOCK->LFCLKSTAT & - CLOCK_LFCLKSTAT_STATE_Msk) >> CLOCK_LFCLKSTAT_STATE_Pos); -} - -__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_lf_start_task_status_get(void) -{ - return (nrf_clock_start_task_status_t)((NRF_CLOCK->LFCLKRUN & - CLOCK_LFCLKRUN_STATUS_Msk) >> - CLOCK_LFCLKRUN_STATUS_Pos); -} - -__STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hf_src_get(void) -{ - return (nrf_clock_hfclk_t)((NRF_CLOCK->HFCLKSTAT & - CLOCK_HFCLKSTAT_SRC_Msk) >> CLOCK_HFCLKSTAT_SRC_Pos); -} - -__STATIC_INLINE bool nrf_clock_hf_is_running(nrf_clock_hfclk_t clk_src) -{ - return (NRF_CLOCK->HFCLKSTAT & (CLOCK_HFCLKSTAT_STATE_Msk | CLOCK_HFCLKSTAT_SRC_Msk)) == - (CLOCK_HFCLKSTAT_STATE_Msk | (clk_src << CLOCK_HFCLKSTAT_SRC_Pos)); -} - -__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_hf_start_task_status_get(void) -{ - return (nrf_clock_start_task_status_t)((NRF_CLOCK->HFCLKRUN & - CLOCK_HFCLKRUN_STATUS_Msk) >> - CLOCK_HFCLKRUN_STATUS_Pos); -} - -__STATIC_INLINE void nrf_clock_cal_timer_timeout_set(uint32_t interval) -{ - NRF_CLOCK->CTIV = ((interval << CLOCK_CTIV_CTIV_Pos) & CLOCK_CTIV_CTIV_Msk); -} - -#endif // SUPPRESS_INLINE_IMPLEMENTATION - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_CLOCK_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_comp.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_comp.h deleted file mode 100644 index d236d2b5fc..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_comp.h +++ /dev/null @@ -1,509 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_COMP_H_ -#define NRF_COMP_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_comp_hal COMP HAL - * @{ - * @ingroup nrf_comp - * @brief Hardware access layer for managing the Comparator (COMP) peripheral. - */ - -/** - * @enum nrf_comp_input_t - * @brief COMP analog pin selection. - */ -typedef enum -{ - NRF_COMP_INPUT_0 = COMP_PSEL_PSEL_AnalogInput0, /*!< AIN0 selected as analog input. */ - NRF_COMP_INPUT_1 = COMP_PSEL_PSEL_AnalogInput1, /*!< AIN1 selected as analog input. */ - NRF_COMP_INPUT_2 = COMP_PSEL_PSEL_AnalogInput2, /*!< AIN2 selected as analog input. */ - NRF_COMP_INPUT_3 = COMP_PSEL_PSEL_AnalogInput3, /*!< AIN3 selected as analog input. */ - NRF_COMP_INPUT_4 = COMP_PSEL_PSEL_AnalogInput4, /*!< AIN4 selected as analog input. */ - NRF_COMP_INPUT_5 = COMP_PSEL_PSEL_AnalogInput5, /*!< AIN5 selected as analog input. */ - NRF_COMP_INPUT_6 = COMP_PSEL_PSEL_AnalogInput6, /*!< AIN6 selected as analog input. */ -#if defined (COMP_PSEL_PSEL_AnalogInput7) || defined (__NRFX_DOXYGEN__) - NRF_COMP_INPUT_7 = COMP_PSEL_PSEL_AnalogInput7, /*!< AIN7 selected as analog input. */ -#endif -#if defined (COMP_PSEL_PSEL_VddDiv2) || defined (__NRFX_DOXYGEN__) - NRF_COMP_VDD_DIV2 = COMP_PSEL_PSEL_VddDiv2, /*!< VDD/2 selected as analog input. */ -#endif -}nrf_comp_input_t; - -/** - * @enum nrf_comp_ref_t - * @brief COMP reference selection. - */ -typedef enum -{ - NRF_COMP_REF_Int1V2 = COMP_REFSEL_REFSEL_Int1V2, /*!< VREF = internal 1.2 V reference (VDD >= 1.7 V). */ - NRF_COMP_REF_Int1V8 = COMP_REFSEL_REFSEL_Int1V8, /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V). */ - NRF_COMP_REF_Int2V4 = COMP_REFSEL_REFSEL_Int2V4, /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V). */ - NRF_COMP_REF_VDD = COMP_REFSEL_REFSEL_VDD, /*!< VREF = VDD. */ - NRF_COMP_REF_ARef = COMP_REFSEL_REFSEL_ARef /*!< VREF = AREF (VDD >= VREF >= AREFMIN). */ -}nrf_comp_ref_t; - -/** - * @enum nrf_comp_ext_ref_t - * @brief COMP external analog reference selection. - */ -typedef enum -{ - NRF_COMP_EXT_REF_0 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference0, /*!< Use AIN0 as external analog reference. */ - NRF_COMP_EXT_REF_1 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 /*!< Use AIN1 as external analog reference. */ -}nrf_comp_ext_ref_t; - -/** - * @brief COMP THDOWN and THUP values that are used to calculate the threshold voltages VDOWN and VUP. - */ -typedef struct -{ - uint8_t th_down; /*!< THDOWN value. */ - uint8_t th_up; /*!< THUP value. */ -}nrf_comp_th_t; - -/** - * @enum nrf_comp_main_mode_t - * @brief COMP main operation mode. - */ -typedef enum -{ - NRF_COMP_MAIN_MODE_SE = COMP_MODE_MAIN_SE, /*!< Single ended mode. */ - NRF_COMP_MAIN_MODE_Diff = COMP_MODE_MAIN_Diff /*!< Differential mode. */ -}nrf_comp_main_mode_t; - -/** - * @enum nrf_comp_sp_mode_t - * @brief COMP speed and power mode. - */ -typedef enum -{ - NRF_COMP_SP_MODE_Low = COMP_MODE_SP_Low, /*!< Low power mode. */ - NRF_COMP_SP_MODE_Normal = COMP_MODE_SP_Normal, /*!< Normal mode. */ - NRF_COMP_SP_MODE_High = COMP_MODE_SP_High /*!< High speed mode. */ -}nrf_comp_sp_mode_t; - -/** - * @enum nrf_comp_hyst_t - * @brief COMP comparator hysteresis. - */ -typedef enum -{ - NRF_COMP_HYST_NoHyst = COMP_HYST_HYST_NoHyst, /*!< Comparator hysteresis disabled. */ - NRF_COMP_HYST_50mV = COMP_HYST_HYST_Hyst50mV /*!< Comparator hysteresis enabled. */ -}nrf_comp_hyst_t; - -#if defined (COMP_ISOURCE_ISOURCE_Msk) || defined (__NRFX_DOXYGEN__) -/** - * @brief COMP current source selection on analog input. - */ -typedef enum -{ - NRF_COMP_ISOURCE_Off = COMP_ISOURCE_ISOURCE_Off, /*!< Current source disabled. */ - NRF_COMP_ISOURCE_Ien2uA5 = COMP_ISOURCE_ISOURCE_Ien2mA5, /*!< Current source enabled (+/- 2.5 uA). */ - NRF_COMP_ISOURCE_Ien5uA = COMP_ISOURCE_ISOURCE_Ien5mA, /*!< Current source enabled (+/- 5 uA). */ - NRF_COMP_ISOURCE_Ien10uA = COMP_ISOURCE_ISOURCE_Ien10mA /*!< Current source enabled (+/- 10 uA). */ -}nrf_isource_t; -#endif - -/** - * @enum nrf_comp_task_t - * @brief COMP tasks. - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_COMP_TASK_START = offsetof(NRF_COMP_Type, TASKS_START), /*!< COMP start sampling task. */ - NRF_COMP_TASK_STOP = offsetof(NRF_COMP_Type, TASKS_STOP), /*!< COMP stop sampling task. */ - NRF_COMP_TASK_SAMPLE = offsetof(NRF_COMP_Type, TASKS_SAMPLE) /*!< Sample comparator value. */ - /*lint -restore*/ -}nrf_comp_task_t; - -/** - * @enum nrf_comp_event_t - * @brief COMP events. - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_COMP_EVENT_READY = offsetof(NRF_COMP_Type, EVENTS_READY), /*!< COMP is ready and output is valid. */ - NRF_COMP_EVENT_DOWN = offsetof(NRF_COMP_Type, EVENTS_DOWN), /*!< Input voltage crossed the threshold going down. */ - NRF_COMP_EVENT_UP = offsetof(NRF_COMP_Type, EVENTS_UP), /*!< Input voltage crossed the threshold going up. */ - NRF_COMP_EVENT_CROSS = offsetof(NRF_COMP_Type, EVENTS_CROSS) /*!< Input voltage crossed the threshold in any direction. */ - /*lint -restore*/ -}nrf_comp_event_t; - -/** - * @brief COMP reference configuration. - */ -typedef struct -{ - nrf_comp_ref_t reference; /*!< COMP reference selection. */ - nrf_comp_ext_ref_t external; /*!< COMP external analog reference selection. */ -}nrf_comp_ref_conf_t; - - -/** - * @brief Function for enabling the COMP peripheral. - */ -__STATIC_INLINE void nrf_comp_enable(void); - - -/** - * @brief Function for disabling the COMP peripheral. - */ - -__STATIC_INLINE void nrf_comp_disable(void); - -/** - * @brief Function for checking if the COMP peripheral is enabled. - * - * @retval true If the COMP peripheral is enabled. - * @retval false If the COMP peripheral is not enabled. - */ -__STATIC_INLINE bool nrf_comp_enable_check(void); - -/** - * @brief Function for setting the reference source. - * - * @param[in] reference COMP reference selection. - */ -__STATIC_INLINE void nrf_comp_ref_set(nrf_comp_ref_t reference); - - -/** - * @brief Function for setting the external analog reference source. - * - * @param[in] ext_ref COMP external analog reference selection. - */ -__STATIC_INLINE void nrf_comp_ext_ref_set(nrf_comp_ext_ref_t ext_ref); - - -/** - * @brief Function for setting threshold voltages. - * - * @param[in] threshold COMP VDOWN and VUP thresholds. - */ -__STATIC_INLINE void nrf_comp_th_set(nrf_comp_th_t threshold); - - -/** - * @brief Function for setting the main mode. - * - * @param[in] main_mode COMP main operation mode. - */ -__STATIC_INLINE void nrf_comp_main_mode_set(nrf_comp_main_mode_t main_mode); - - -/** - * @brief Function for setting the speed mode. - * - * @param[in] speed_mode COMP speed and power mode. - */ -__STATIC_INLINE void nrf_comp_speed_mode_set(nrf_comp_sp_mode_t speed_mode); - - -/** - * @brief Function for setting the hysteresis. - * - * @param[in] hyst COMP comparator hysteresis. - */ -__STATIC_INLINE void nrf_comp_hysteresis_set(nrf_comp_hyst_t hyst); - - -#if defined (COMP_ISOURCE_ISOURCE_Msk) || defined (__NRFX_DOXYGEN__) -/** - * @brief Function for setting the current source on the analog input. - * - * @param[in] isource COMP current source selection on analog input. - */ -__STATIC_INLINE void nrf_comp_isource_set(nrf_isource_t isource); -#endif - - -/** - * @brief Function for selecting the active input of the COMP. - * - * @param[in] input Input to be selected. - */ -__STATIC_INLINE void nrf_comp_input_select(nrf_comp_input_t input); - - -/** - * @brief Function for getting the last COMP compare result. - * - * @return The last compare result. If 0, then VIN+ < VIN-. If 1, then VIN+ > VIN-. - * - * @note If VIN+ == VIN-, the return value depends on the previous result. - */ -__STATIC_INLINE uint32_t nrf_comp_result_get(void); - - -/** - * @brief Function for enabling interrupts from COMP. - * - * @param[in] comp_int_mask Mask of interrupts to be enabled. - * - * @sa nrf_comp_int_enable_check() - */ -__STATIC_INLINE void nrf_comp_int_enable(uint32_t comp_int_mask); - -/** - * @brief Function for disabling interrupts from COMP. - * - * @param[in] comp_int_mask Mask of interrupts to be disabled. - * - * @sa nrf_comp_int_enable_check() - */ -__STATIC_INLINE void nrf_comp_int_disable(uint32_t comp_int_mask); - - -/** - * @brief Function for getting the enabled interrupts of COMP. - * - * @param[in] comp_int_mask Mask of interrupts to be checked. - * - * @retval true If any interrupts of the specified mask are enabled. - */ -__STATIC_INLINE bool nrf_comp_int_enable_check(uint32_t comp_int_mask); - - - -/** - * @brief Function for getting the address of a specific COMP task register. - * - * @param[in] comp_task COMP task. - * - * @return Address of the specified COMP task. - */ -__STATIC_INLINE uint32_t * nrf_comp_task_address_get(nrf_comp_task_t comp_task); - - -/** - * @brief Function for getting the address of a specific COMP event register. - * - * @param[in] comp_event COMP event. - * - * @return Address of the specified COMP event. - */ -__STATIC_INLINE uint32_t * nrf_comp_event_address_get(nrf_comp_event_t comp_event); - - -/** - * @brief Function for setting COMP shorts. - * - * @param[in] comp_short_mask COMP shorts by mask. - * - */ -__STATIC_INLINE void nrf_comp_shorts_enable(uint32_t comp_short_mask); - - -/** - * @brief Function for clearing COMP shorts by mask. - * - * @param[in] comp_short_mask COMP shorts to be cleared. - * - */ -__STATIC_INLINE void nrf_comp_shorts_disable(uint32_t comp_short_mask); - - -/** - * @brief Function for setting a specific COMP task. - * - * @param[in] comp_task COMP task to be set. - * - */ -__STATIC_INLINE void nrf_comp_task_trigger(nrf_comp_task_t comp_task); - - -/** - * @brief Function for clearing a specific COMP event. - * - * @param[in] comp_event COMP event to be cleared. - * - */ -__STATIC_INLINE void nrf_comp_event_clear(nrf_comp_event_t comp_event); - - -/** - * @brief Function for getting the state of a specific COMP event. - * - * @retval true If the specified COMP event is active. - * - */ -__STATIC_INLINE bool nrf_comp_event_check(nrf_comp_event_t comp_event); - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -__STATIC_INLINE void nrf_comp_enable(void) -{ - NRF_COMP->ENABLE = (COMP_ENABLE_ENABLE_Enabled << COMP_ENABLE_ENABLE_Pos); -} - -__STATIC_INLINE void nrf_comp_disable(void) -{ - NRF_COMP->ENABLE = (COMP_ENABLE_ENABLE_Disabled << COMP_ENABLE_ENABLE_Pos); -} - -__STATIC_INLINE bool nrf_comp_enable_check(void) -{ - return ((NRF_COMP->ENABLE) & COMP_ENABLE_ENABLE_Enabled); -} - -__STATIC_INLINE void nrf_comp_ref_set(nrf_comp_ref_t reference) -{ - NRF_COMP->REFSEL = (reference << COMP_REFSEL_REFSEL_Pos); -} - -__STATIC_INLINE void nrf_comp_ext_ref_set(nrf_comp_ext_ref_t ext_ref) -{ - NRF_COMP->EXTREFSEL = (ext_ref << COMP_EXTREFSEL_EXTREFSEL_Pos); -} - -__STATIC_INLINE void nrf_comp_th_set(nrf_comp_th_t threshold) -{ - NRF_COMP->TH = - ((threshold.th_down << COMP_TH_THDOWN_Pos) & COMP_TH_THDOWN_Msk) | - ((threshold.th_up << COMP_TH_THUP_Pos) & COMP_TH_THUP_Msk); -} - -__STATIC_INLINE void nrf_comp_main_mode_set(nrf_comp_main_mode_t main_mode) -{ - NRF_COMP->MODE |= (main_mode << COMP_MODE_MAIN_Pos); -} - -__STATIC_INLINE void nrf_comp_speed_mode_set(nrf_comp_sp_mode_t speed_mode) -{ - NRF_COMP->MODE |= (speed_mode << COMP_MODE_SP_Pos); -} - -__STATIC_INLINE void nrf_comp_hysteresis_set(nrf_comp_hyst_t hyst) -{ - NRF_COMP->HYST = (hyst << COMP_HYST_HYST_Pos) & COMP_HYST_HYST_Msk; -} - -#if defined (COMP_ISOURCE_ISOURCE_Msk) -__STATIC_INLINE void nrf_comp_isource_set(nrf_isource_t isource) -{ - NRF_COMP->ISOURCE = (isource << COMP_ISOURCE_ISOURCE_Pos) & COMP_ISOURCE_ISOURCE_Msk; -} -#endif - -__STATIC_INLINE void nrf_comp_input_select(nrf_comp_input_t input) -{ - NRF_COMP->PSEL = ((uint32_t)input << COMP_PSEL_PSEL_Pos); -} - -__STATIC_INLINE uint32_t nrf_comp_result_get(void) -{ - return (uint32_t)NRF_COMP->RESULT; -} - -__STATIC_INLINE void nrf_comp_int_enable(uint32_t comp_int_mask) -{ - NRF_COMP->INTENSET = comp_int_mask; -} - -__STATIC_INLINE void nrf_comp_int_disable(uint32_t comp_int_mask) -{ - NRF_COMP->INTENCLR = comp_int_mask; -} - -__STATIC_INLINE bool nrf_comp_int_enable_check(uint32_t comp_int_mask) -{ - return (NRF_COMP->INTENSET & comp_int_mask); // when read this register will return the value of INTEN. -} - -__STATIC_INLINE uint32_t * nrf_comp_task_address_get(nrf_comp_task_t comp_task) -{ - return (uint32_t *)((uint8_t *)NRF_COMP + (uint32_t)comp_task); -} - -__STATIC_INLINE uint32_t * nrf_comp_event_address_get(nrf_comp_event_t comp_event) -{ - return (uint32_t *)((uint8_t *)NRF_COMP + (uint32_t)comp_event); -} - -__STATIC_INLINE void nrf_comp_shorts_enable(uint32_t comp_short_mask) -{ - NRF_COMP->SHORTS |= comp_short_mask; -} - -__STATIC_INLINE void nrf_comp_shorts_disable(uint32_t comp_short_mask) -{ - NRF_COMP->SHORTS &= ~comp_short_mask; -} - -__STATIC_INLINE void nrf_comp_task_trigger(nrf_comp_task_t comp_task) -{ - *( (volatile uint32_t *)( (uint8_t *)NRF_COMP + comp_task) ) = 1; -} - -__STATIC_INLINE void nrf_comp_event_clear(nrf_comp_event_t comp_event) -{ - *( (volatile uint32_t *)( (uint8_t *)NRF_COMP + (uint32_t)comp_event) ) = 0; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_COMP + (uint32_t)comp_event)); - (void)dummy; -#endif -} - -__STATIC_INLINE bool nrf_comp_event_check(nrf_comp_event_t comp_event) -{ - return (bool) (*(volatile uint32_t *)( (uint8_t *)NRF_COMP + comp_event)); -} - -#endif // SUPPRESS_INLINE_IMPLEMENTATION - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_COMP_H_ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_ecb.c b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_ecb.c deleted file mode 100644 index 1680bc0422..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_ecb.c +++ /dev/null @@ -1,93 +0,0 @@ -/** - * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -//lint -e438 - -#include -#include "nrf_ecb.h" -#include - -static uint8_t ecb_data[48]; ///< ECB data structure for RNG peripheral to access. -static uint8_t* ecb_key; ///< Key: Starts at ecb_data -static uint8_t* ecb_cleartext; ///< Cleartext: Starts at ecb_data + 16 bytes. -static uint8_t* ecb_ciphertext; ///< Ciphertext: Starts at ecb_data + 32 bytes. - -bool nrf_ecb_init(void) -{ - ecb_key = ecb_data; - ecb_cleartext = ecb_data + 16; - ecb_ciphertext = ecb_data + 32; - - NRF_ECB->ECBDATAPTR = (uint32_t)ecb_data; - return true; -} - - -bool nrf_ecb_crypt(uint8_t * dest_buf, const uint8_t * src_buf) -{ - uint32_t counter = 0x1000000; - if (src_buf != ecb_cleartext) - { - memcpy(ecb_cleartext,src_buf,16); - } - NRF_ECB->EVENTS_ENDECB = 0; - NRF_ECB->TASKS_STARTECB = 1; - while (NRF_ECB->EVENTS_ENDECB == 0) - { - counter--; - if (counter == 0) - { - return false; - } - } - NRF_ECB->EVENTS_ENDECB = 0; - if (dest_buf != ecb_ciphertext) - { - memcpy(dest_buf,ecb_ciphertext,16); - } - return true; -} - -void nrf_ecb_set_key(const uint8_t * key) -{ - memcpy(ecb_key,key,16); -} - - diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_ecb.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_ecb.h deleted file mode 100644 index bb8a103dc5..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_ecb.h +++ /dev/null @@ -1,97 +0,0 @@ -/** - * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_ECB_H__ -#define NRF_ECB_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_ecb_hal AES ECB encryption HAL - * @{ - * @ingroup nrf_ecb - * @brief Driver for the AES Electronic Code Book (ECB) peripheral. - * - * To encrypt data, the peripheral must first be powered on - * using @ref nrf_ecb_init. Next, the key must be set using @ref nrf_ecb_set_key. - */ - -/** - * @brief Function for initializing and powering on the ECB peripheral. - * - * This function allocates memory for the ECBDATAPTR. - * @retval true If initialization was successful. - * @retval false If powering on failed. - */ -bool nrf_ecb_init(void); - -/** - * @brief Function for encrypting 16-byte data using current key. - * - * This function avoids unnecessary copying of data if the parameters point to the - * correct locations in the ECB data structure. - * - * @param dst Result of encryption, 16 bytes will be written. - * @param src Source with 16-byte data to be encrypted. - * - * @retval true If the encryption operation completed. - * @retval false If the encryption operation did not complete. - */ -bool nrf_ecb_crypt(uint8_t * dst, const uint8_t * src); - -/** - * @brief Function for setting the key to be used for encryption. - * - * @param key Pointer to the key. 16 bytes will be read. - */ -void nrf_ecb_set_key(const uint8_t * key); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_ECB_H__ - diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_egu.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_egu.h deleted file mode 100644 index 49a3717de3..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_egu.h +++ /dev/null @@ -1,389 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_EGU_H__ -#define NRF_EGU_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** -* @defgroup nrf_egu_hal EGU HAL -* @{ -* @ingroup nrf_swi_egu -* @brief Hardware access layer for managing the Event Generator Unit (EGU) peripheral. -*/ - -/** - * @enum nrf_egu_task_t - * @brief EGU tasks. - */ -typedef enum -{ - /*lint -save -e30 -esym(628,__INTADDR__)*/ - NRF_EGU_TASK_TRIGGER0 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[0]), /**< Trigger 0 for triggering the corresponding TRIGGERED[0] event. */ - NRF_EGU_TASK_TRIGGER1 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[1]), /**< Trigger 1 for triggering the corresponding TRIGGERED[1] event. */ - NRF_EGU_TASK_TRIGGER2 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[2]), /**< Trigger 2 for triggering the corresponding TRIGGERED[2] event. */ - NRF_EGU_TASK_TRIGGER3 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[3]), /**< Trigger 3 for triggering the corresponding TRIGGERED[3] event. */ - NRF_EGU_TASK_TRIGGER4 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[4]), /**< Trigger 4 for triggering the corresponding TRIGGERED[4] event. */ - NRF_EGU_TASK_TRIGGER5 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[5]), /**< Trigger 5 for triggering the corresponding TRIGGERED[5] event. */ - NRF_EGU_TASK_TRIGGER6 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[6]), /**< Trigger 6 for triggering the corresponding TRIGGERED[6] event. */ - NRF_EGU_TASK_TRIGGER7 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[7]), /**< Trigger 7 for triggering the corresponding TRIGGERED[7] event. */ - NRF_EGU_TASK_TRIGGER8 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[8]), /**< Trigger 8 for triggering the corresponding TRIGGERED[8] event. */ - NRF_EGU_TASK_TRIGGER9 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[9]), /**< Trigger 9 for triggering the corresponding TRIGGERED[9] event. */ - NRF_EGU_TASK_TRIGGER10 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[10]), /**< Trigger 10 for triggering the corresponding TRIGGERED[10] event. */ - NRF_EGU_TASK_TRIGGER11 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[11]), /**< Trigger 11 for triggering the corresponding TRIGGERED[11] event. */ - NRF_EGU_TASK_TRIGGER12 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[12]), /**< Trigger 12 for triggering the corresponding TRIGGERED[12] event. */ - NRF_EGU_TASK_TRIGGER13 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[13]), /**< Trigger 13 for triggering the corresponding TRIGGERED[13] event. */ - NRF_EGU_TASK_TRIGGER14 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[14]), /**< Trigger 14 for triggering the corresponding TRIGGERED[14] event. */ - NRF_EGU_TASK_TRIGGER15 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[15]) /**< Trigger 15 for triggering the corresponding TRIGGERED[15] event. */ - /*lint -restore*/ -} nrf_egu_task_t; - - -/** - * @enum nrf_egu_event_t - * @brief EGU events. - */ -typedef enum -{ - /*lint -save -e30 -esym(628,__INTADDR__)*/ - NRF_EGU_EVENT_TRIGGERED0 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[0]), /**< Event number 0 generated by triggering the corresponding TRIGGER[0] task. */ - NRF_EGU_EVENT_TRIGGERED1 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[1]), /**< Event number 1 generated by triggering the corresponding TRIGGER[1] task. */ - NRF_EGU_EVENT_TRIGGERED2 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[2]), /**< Event number 2 generated by triggering the corresponding TRIGGER[2] task. */ - NRF_EGU_EVENT_TRIGGERED3 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[3]), /**< Event number 3 generated by triggering the corresponding TRIGGER[3] task. */ - NRF_EGU_EVENT_TRIGGERED4 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[4]), /**< Event number 4 generated by triggering the corresponding TRIGGER[4] task. */ - NRF_EGU_EVENT_TRIGGERED5 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[5]), /**< Event number 5 generated by triggering the corresponding TRIGGER[5] task. */ - NRF_EGU_EVENT_TRIGGERED6 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[6]), /**< Event number 6 generated by triggering the corresponding TRIGGER[6] task. */ - NRF_EGU_EVENT_TRIGGERED7 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[7]), /**< Event number 7 generated by triggering the corresponding TRIGGER[7] task. */ - NRF_EGU_EVENT_TRIGGERED8 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[8]), /**< Event number 8 generated by triggering the corresponding TRIGGER[8] task. */ - NRF_EGU_EVENT_TRIGGERED9 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[9]), /**< Event number 9 generated by triggering the corresponding TRIGGER[9] task. */ - NRF_EGU_EVENT_TRIGGERED10 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[10]), /**< Event number 10 generated by triggering the corresponding TRIGGER[10] task. */ - NRF_EGU_EVENT_TRIGGERED11 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[11]), /**< Event number 11 generated by triggering the corresponding TRIGGER[11] task. */ - NRF_EGU_EVENT_TRIGGERED12 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[12]), /**< Event number 12 generated by triggering the corresponding TRIGGER[12] task. */ - NRF_EGU_EVENT_TRIGGERED13 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[13]), /**< Event number 13 generated by triggering the corresponding TRIGGER[13] task. */ - NRF_EGU_EVENT_TRIGGERED14 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[14]), /**< Event number 14 generated by triggering the corresponding TRIGGER[14] task. */ - NRF_EGU_EVENT_TRIGGERED15 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[15]) /**< Event number 15 generated by triggering the corresponding TRIGGER[15] task. */ - /*lint -restore*/ -} nrf_egu_event_t; - - -/** - * @enum nrf_egu_int_mask_t - * @brief EGU interrupts. - */ -typedef enum -{ - NRF_EGU_INT_TRIGGERED0 = EGU_INTENSET_TRIGGERED0_Msk, /**< Interrupt on EVENTS_TRIGGERED[0] event. */ - NRF_EGU_INT_TRIGGERED1 = EGU_INTENSET_TRIGGERED1_Msk, /**< Interrupt on EVENTS_TRIGGERED[1] event. */ - NRF_EGU_INT_TRIGGERED2 = EGU_INTENSET_TRIGGERED2_Msk, /**< Interrupt on EVENTS_TRIGGERED[2] event. */ - NRF_EGU_INT_TRIGGERED3 = EGU_INTENSET_TRIGGERED3_Msk, /**< Interrupt on EVENTS_TRIGGERED[3] event. */ - NRF_EGU_INT_TRIGGERED4 = EGU_INTENSET_TRIGGERED4_Msk, /**< Interrupt on EVENTS_TRIGGERED[4] event. */ - NRF_EGU_INT_TRIGGERED5 = EGU_INTENSET_TRIGGERED5_Msk, /**< Interrupt on EVENTS_TRIGGERED[5] event. */ - NRF_EGU_INT_TRIGGERED6 = EGU_INTENSET_TRIGGERED6_Msk, /**< Interrupt on EVENTS_TRIGGERED[6] event. */ - NRF_EGU_INT_TRIGGERED7 = EGU_INTENSET_TRIGGERED7_Msk, /**< Interrupt on EVENTS_TRIGGERED[7] event. */ - NRF_EGU_INT_TRIGGERED8 = EGU_INTENSET_TRIGGERED8_Msk, /**< Interrupt on EVENTS_TRIGGERED[8] event. */ - NRF_EGU_INT_TRIGGERED9 = EGU_INTENSET_TRIGGERED9_Msk, /**< Interrupt on EVENTS_TRIGGERED[9] event. */ - NRF_EGU_INT_TRIGGERED10 = EGU_INTENSET_TRIGGERED10_Msk, /**< Interrupt on EVENTS_TRIGGERED[10] event. */ - NRF_EGU_INT_TRIGGERED11 = EGU_INTENSET_TRIGGERED11_Msk, /**< Interrupt on EVENTS_TRIGGERED[11] event. */ - NRF_EGU_INT_TRIGGERED12 = EGU_INTENSET_TRIGGERED12_Msk, /**< Interrupt on EVENTS_TRIGGERED[12] event. */ - NRF_EGU_INT_TRIGGERED13 = EGU_INTENSET_TRIGGERED13_Msk, /**< Interrupt on EVENTS_TRIGGERED[13] event. */ - NRF_EGU_INT_TRIGGERED14 = EGU_INTENSET_TRIGGERED14_Msk, /**< Interrupt on EVENTS_TRIGGERED[14] event. */ - NRF_EGU_INT_TRIGGERED15 = EGU_INTENSET_TRIGGERED15_Msk, /**< Interrupt on EVENTS_TRIGGERED[15] event. */ - NRF_EGU_INT_ALL = 0xFFFFuL -} nrf_egu_int_mask_t; - -/**@brief Function for getting max channel number of given EGU. - * - * @param NRF_EGUx EGU instance. - * - * @returns number of available channels. - */ -__STATIC_INLINE uint32_t nrf_egu_channel_count(NRF_EGU_Type * NRF_EGUx); - -/** - * @brief Function for triggering a specific EGU task. - * - * @param NRF_EGUx EGU instance. - * @param egu_task EGU task. - */ -__STATIC_INLINE void nrf_egu_task_trigger(NRF_EGU_Type * NRF_EGUx, nrf_egu_task_t egu_task); - -/** - * @brief Function for returning the address of a specific EGU task register. - * - * @param NRF_EGUx EGU instance. - * @param egu_task EGU task. - */ -__STATIC_INLINE uint32_t * nrf_egu_task_address_get(NRF_EGU_Type * NRF_EGUx, - nrf_egu_task_t egu_task); - -/** - * @brief Function for returning the address of a specific EGU TRIGGER task register. - * - * @param NRF_EGUx EGU instance. - * @param channel Channel number. - */ -__STATIC_INLINE uint32_t * nrf_egu_task_trigger_address_get(NRF_EGU_Type * NRF_EGUx, - uint8_t channel); - -/** - * @brief Function for returning the specific EGU TRIGGER task. - * - * @param NRF_EGUx EGU instance. - * @param channel Channel number. - */ -__STATIC_INLINE nrf_egu_task_t nrf_egu_task_trigger_get(NRF_EGU_Type * NRF_EGUx, uint8_t channel); - -/** - * @brief Function for returning the state of a specific EGU event. - * - * @param NRF_EGUx EGU instance. - * @param egu_event EGU event to check. - */ -__STATIC_INLINE bool nrf_egu_event_check(NRF_EGU_Type * NRF_EGUx, - nrf_egu_event_t egu_event); - -/** - * @brief Function for clearing a specific EGU event. - * - * @param NRF_EGUx EGU instance. - * @param egu_event EGU event to clear. - */ -__STATIC_INLINE void nrf_egu_event_clear(NRF_EGU_Type * NRF_EGUx, - nrf_egu_event_t egu_event); - -/** - * @brief Function for returning the address of a specific EGU event register. - * - * @param NRF_EGUx EGU instance. - * @param egu_event EGU event. - */ -__STATIC_INLINE uint32_t * nrf_egu_event_address_get(NRF_EGU_Type * NRF_EGUx, - nrf_egu_event_t egu_event); - -/** - * @brief Function for returning the address of a specific EGU TRIGGERED event register. - * - * @param NRF_EGUx EGU instance. - * @param channel Channel number. - */ -__STATIC_INLINE uint32_t * nrf_egu_event_triggered_address_get(NRF_EGU_Type * NRF_EGUx, - uint8_t channel); - -/** - * @brief Function for returning the specific EGU TRIGGERED event. - * - * @param NRF_EGUx EGU instance. - * @param channel Channel number. - */ -__STATIC_INLINE nrf_egu_event_t nrf_egu_event_triggered_get(NRF_EGU_Type * NRF_EGUx, - uint8_t channel); - -/** - * @brief Function for enabling one or more specific EGU interrupts. - * - * @param NRF_EGUx EGU instance. - * @param egu_int_mask Interrupts to enable. - */ -__STATIC_INLINE void nrf_egu_int_enable(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask); - -/** - * @brief Function for retrieving the state of one or more EGU interrupts. - * - * @param NRF_EGUx EGU instance. - * @param egu_int_mask Interrupts to check. - * - * @retval true If all of the specified interrupts are enabled. - * @retval false If at least one of the specified interrupts is disabled. - */ -__STATIC_INLINE bool nrf_egu_int_enable_check(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask); - -/** - * @brief Function for disabling one or more specific EGU interrupts. - * - * @param NRF_EGUx EGU instance. - * @param egu_int_mask Interrupts to disable. - */ -__STATIC_INLINE void nrf_egu_int_disable(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask); - -/** - * @brief Function for retrieving one or more specific EGU interrupts. - * - * @param NRF_EGUx EGU instance. - * @param channel Channel number. - * - * @returns EGU interrupt mask. - */ -__STATIC_INLINE nrf_egu_int_mask_t nrf_egu_int_get(NRF_EGU_Type * NRF_EGUx, uint8_t channel); - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -__STATIC_INLINE uint32_t nrf_egu_channel_count(NRF_EGU_Type * NRF_EGUx) -{ - if (NRF_EGUx == NRF_EGU0){ - return EGU0_CH_NUM; - } - if (NRF_EGUx == NRF_EGU1){ - return EGU1_CH_NUM; - } -#if EGU_COUNT > 2 - if (NRF_EGUx == NRF_EGU2){ - return EGU2_CH_NUM; - } - if (NRF_EGUx == NRF_EGU3){ - return EGU3_CH_NUM; - } - if (NRF_EGUx == NRF_EGU4){ - return EGU4_CH_NUM; - } - if (NRF_EGUx == NRF_EGU5){ - return EGU5_CH_NUM; - } -#endif - return 0; -} - -__STATIC_INLINE void nrf_egu_task_trigger(NRF_EGU_Type * NRF_EGUx, nrf_egu_task_t egu_task) -{ - NRFX_ASSERT(NRF_EGUx); - *((volatile uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_task)) = 0x1UL; -} - -__STATIC_INLINE uint32_t * nrf_egu_task_address_get(NRF_EGU_Type * NRF_EGUx, - nrf_egu_task_t egu_task) -{ - NRFX_ASSERT(NRF_EGUx); - return (uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_task); -} - -__STATIC_INLINE uint32_t * nrf_egu_task_trigger_address_get(NRF_EGU_Type * NRF_EGUx, - uint8_t channel) -{ - NRFX_ASSERT(NRF_EGUx); - NRFX_ASSERT(channel < nrf_egu_channel_count(NRF_EGUx)); - return (uint32_t*)&NRF_EGUx->TASKS_TRIGGER[channel]; -} - -__STATIC_INLINE nrf_egu_task_t nrf_egu_task_trigger_get(NRF_EGU_Type * NRF_EGUx, uint8_t channel) -{ - NRFX_ASSERT(NRF_EGUx); - NRFX_ASSERT(channel < nrf_egu_channel_count(NRF_EGUx)); - return (nrf_egu_task_t)((uint32_t) NRF_EGU_TASK_TRIGGER0 + (channel * sizeof(uint32_t))); -} - -__STATIC_INLINE bool nrf_egu_event_check(NRF_EGU_Type * NRF_EGUx, - nrf_egu_event_t egu_event) -{ - NRFX_ASSERT(NRF_EGUx); - return (bool)*(volatile uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_event); -} - -__STATIC_INLINE void nrf_egu_event_clear(NRF_EGU_Type * NRF_EGUx, - nrf_egu_event_t egu_event) -{ - NRFX_ASSERT(NRF_EGUx); - *((volatile uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_event)); - (void)dummy; -#endif -} - -__STATIC_INLINE uint32_t * nrf_egu_event_address_get(NRF_EGU_Type * NRF_EGUx, - nrf_egu_event_t egu_event) -{ - NRFX_ASSERT(NRF_EGUx); - return (uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_event); -} - -__STATIC_INLINE uint32_t * nrf_egu_event_triggered_address_get(NRF_EGU_Type * NRF_EGUx, - uint8_t channel) -{ - NRFX_ASSERT(NRF_EGUx); - NRFX_ASSERT(channel < nrf_egu_channel_count(NRF_EGUx)); - return (uint32_t*)&NRF_EGUx->EVENTS_TRIGGERED[channel]; -} - -__STATIC_INLINE nrf_egu_event_t nrf_egu_event_triggered_get(NRF_EGU_Type * NRF_EGUx, - uint8_t channel) -{ - NRFX_ASSERT(NRF_EGUx); - NRFX_ASSERT(channel < nrf_egu_channel_count(NRF_EGUx)); - return (nrf_egu_event_t)((uint32_t) NRF_EGU_EVENT_TRIGGERED0 + (channel * sizeof(uint32_t))); -} - -__STATIC_INLINE void nrf_egu_int_enable(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask) -{ - NRFX_ASSERT(NRF_EGUx); - NRF_EGUx->INTENSET = egu_int_mask; -} - -__STATIC_INLINE bool nrf_egu_int_enable_check(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask) -{ - NRFX_ASSERT(NRF_EGUx); - return (bool)(NRF_EGUx->INTENSET & egu_int_mask); -} - -__STATIC_INLINE void nrf_egu_int_disable(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask) -{ - NRFX_ASSERT(NRF_EGUx); - NRF_EGUx->INTENCLR = egu_int_mask; -} - -__STATIC_INLINE nrf_egu_int_mask_t nrf_egu_int_get(NRF_EGU_Type * NRF_EGUx, uint8_t channel) -{ - NRFX_ASSERT(NRF_EGUx); - NRFX_ASSERT(channel < nrf_egu_channel_count(NRF_EGUx)); - return (nrf_egu_int_mask_t)((uint32_t) (EGU_INTENSET_TRIGGERED0_Msk << channel)); -} - -#endif // SUPPRESS_INLINE_IMPLEMENTATION - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_gpio.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_gpio.h deleted file mode 100644 index 77c32545a0..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_gpio.h +++ /dev/null @@ -1,785 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_GPIO_H__ -#define NRF_GPIO_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_gpio_hal GPIO HAL - * @{ - * @ingroup nrf_gpio - * @brief Hardware access layer for managing the GPIO peripheral. - */ - -#if (GPIO_COUNT == 1) -#define NUMBER_OF_PINS (P0_PIN_NUM) -#define GPIO_REG_LIST {NRF_GPIO} -#elif (GPIO_COUNT == 2) -#define NUMBER_OF_PINS (P0_PIN_NUM + P1_PIN_NUM) -#define GPIO_REG_LIST {NRF_P0, NRF_P1} -#else -#error "Not supported." -#endif - - -/** - * @brief Macro for mapping port and pin numbers to values understandable for nrf_gpio functions. - */ -#define NRF_GPIO_PIN_MAP(port, pin) (((port) << 5) | ((pin) & 0x1F)) - -/** - * @brief Pin direction definitions. - */ -typedef enum -{ - NRF_GPIO_PIN_DIR_INPUT = GPIO_PIN_CNF_DIR_Input, ///< Input. - NRF_GPIO_PIN_DIR_OUTPUT = GPIO_PIN_CNF_DIR_Output ///< Output. -} nrf_gpio_pin_dir_t; - -/** - * @brief Connection of input buffer. - */ -typedef enum -{ - NRF_GPIO_PIN_INPUT_CONNECT = GPIO_PIN_CNF_INPUT_Connect, ///< Connect input buffer. - NRF_GPIO_PIN_INPUT_DISCONNECT = GPIO_PIN_CNF_INPUT_Disconnect ///< Disconnect input buffer. -} nrf_gpio_pin_input_t; - -/** - * @brief Enumerator used for selecting the pin to be pulled down or up at the time of pin configuration. - */ -typedef enum -{ - NRF_GPIO_PIN_NOPULL = GPIO_PIN_CNF_PULL_Disabled, ///< Pin pull-up resistor disabled. - NRF_GPIO_PIN_PULLDOWN = GPIO_PIN_CNF_PULL_Pulldown, ///< Pin pull-down resistor enabled. - NRF_GPIO_PIN_PULLUP = GPIO_PIN_CNF_PULL_Pullup, ///< Pin pull-up resistor enabled. -} nrf_gpio_pin_pull_t; - -/** - * @brief Enumerator used for selecting output drive mode. - */ -typedef enum -{ - NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE_S0S1, ///< !< Standard '0', standard '1'. - NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE_H0S1, ///< !< High-drive '0', standard '1'. - NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE_S0H1, ///< !< Standard '0', high-drive '1'. - NRF_GPIO_PIN_H0H1 = GPIO_PIN_CNF_DRIVE_H0H1, ///< !< High drive '0', high-drive '1'. - NRF_GPIO_PIN_D0S1 = GPIO_PIN_CNF_DRIVE_D0S1, ///< !< Disconnect '0' standard '1'. - NRF_GPIO_PIN_D0H1 = GPIO_PIN_CNF_DRIVE_D0H1, ///< !< Disconnect '0', high-drive '1'. - NRF_GPIO_PIN_S0D1 = GPIO_PIN_CNF_DRIVE_S0D1, ///< !< Standard '0', disconnect '1'. - NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE_H0D1, ///< !< High-drive '0', disconnect '1'. -} nrf_gpio_pin_drive_t; - -/** - * @brief Enumerator used for selecting the pin to sense high or low level on the pin input. - */ -typedef enum -{ - NRF_GPIO_PIN_NOSENSE = GPIO_PIN_CNF_SENSE_Disabled, ///< Pin sense level disabled. - NRF_GPIO_PIN_SENSE_LOW = GPIO_PIN_CNF_SENSE_Low, ///< Pin sense low level. - NRF_GPIO_PIN_SENSE_HIGH = GPIO_PIN_CNF_SENSE_High, ///< Pin sense high level. -} nrf_gpio_pin_sense_t; - -/** - * @brief Function for configuring the GPIO pin range as output pins with normal drive strength. - * This function can be used to configure pin range as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases). - * - * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30). - * - * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30). - * - * @note For configuring only one pin as output, use @ref nrf_gpio_cfg_output. - * Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output. - */ -__STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end); - -/** - * @brief Function for configuring the GPIO pin range as input pins with given initial value set, hiding inner details. - * This function can be used to configure pin range as simple input. - * - * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30). - * - * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30). - * - * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high). - * - * @note For configuring only one pin as input, use @ref nrf_gpio_cfg_input. - * Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable. - */ -__STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start, - uint32_t pin_range_end, - nrf_gpio_pin_pull_t pull_config); - -/** - * @brief Pin configuration function. - * - * The main pin configuration function. - * This function allows to set any aspect in PIN_CNF register. - * @param pin_number Specifies the pin number. - * @param dir Pin direction. - * @param input Connect or disconnect the input buffer. - * @param pull Pull configuration. - * @param drive Drive configuration. - * @param sense Pin sensing mechanism. - */ -__STATIC_INLINE void nrf_gpio_cfg( - uint32_t pin_number, - nrf_gpio_pin_dir_t dir, - nrf_gpio_pin_input_t input, - nrf_gpio_pin_pull_t pull, - nrf_gpio_pin_drive_t drive, - nrf_gpio_pin_sense_t sense); - -/** - * @brief Function for configuring the given GPIO pin number as output, hiding inner details. - * This function can be used to configure a pin as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases). - * - * @param pin_number Specifies the pin number. - * - * @note Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output. - */ -__STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number); - -/** - * @brief Function for configuring the given GPIO pin number as input, hiding inner details. - * This function can be used to configure a pin as simple input. - * - * @param pin_number Specifies the pin number. - * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high). - * - * @note Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable. - */ -__STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config); - -/** - * @brief Function for resetting pin configuration to its default state. - * - * @param pin_number Specifies the pin number. - */ -__STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number); - -/** - * @brief Function for configuring the given GPIO pin number as a watcher. Only input is connected. - * - * @param pin_number Specifies the pin number. - * - */ -__STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number); - -/** - * @brief Function for disconnecting input for the given GPIO. - * - * @param pin_number Specifies the pin number. - * - */ -__STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number); - -/** - * @brief Function for configuring the given GPIO pin number as input, hiding inner details. - * This function can be used to configure pin range as simple input. - * Sense capability on the pin is configurable and input is connected to buffer so that the GPIO->IN register is readable. - * - * @param pin_number Specifies the pin number. - * @param pull_config State of the pin pull resistor (no pull, pulled down, or pulled high). - * @param sense_config Sense level of the pin (no sense, sense low, or sense high). - */ -__STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number, - nrf_gpio_pin_pull_t pull_config, - nrf_gpio_pin_sense_t sense_config); - -/** - * @brief Function for configuring sense level for the given GPIO. - * - * @param pin_number Specifies the pin number. - * @param sense_config Sense configuration. - * - */ -__STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config); - -/** - * @brief Function for setting the direction for a GPIO pin. - * - * @param pin_number Specifies the pin number for which to set the direction. - * - * @param direction Specifies the direction. - */ -__STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction); - -/** - * @brief Function for setting a GPIO pin. - * - * Note that the pin must be configured as an output for this function to have any effect. - * - * @param pin_number Specifies the pin number to set. - */ -__STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number); - -/** - * @brief Function for clearing a GPIO pin. - * - * Note that the pin must be configured as an output for this - * function to have any effect. - * - * @param pin_number Specifies the pin number to clear. - */ -__STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number); - -/** - * @brief Function for toggling a GPIO pin. - * - * Note that the pin must be configured as an output for this - * function to have any effect. - * - * @param pin_number Specifies the pin number to toggle. - */ -__STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number); - -/** - * @brief Function for writing a value to a GPIO pin. - * - * Note that the pin must be configured as an output for this - * function to have any effect. - * - * @param pin_number Specifies the pin number to write. - * - * @param value Specifies the value to be written to the pin. - * @arg 0 Clears the pin. - * @arg >=1 Sets the pin. - */ -__STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value); - -/** - * @brief Function for reading the input level of a GPIO pin. - * - * Note that the pin must have input connected for the value - * returned from this function to be valid. - * - * @param pin_number Specifies the pin number to read. - * - * @return 0 if the pin input level is low. Positive value if the pin is high. - */ -__STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number); - -/** - * @brief Function for reading the output level of a GPIO pin. - * - * @param pin_number Specifies the pin number to read. - * - * @return 0 if the pin output level is low. Positive value if pin output is high. - */ -__STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number); - -/** - * @brief Function for reading the sense configuration of a GPIO pin. - * - * @param pin_number Specifies the pin number to read. - * - * @retval Sense configuration. - */ -__STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number); - -/** - * @brief Function for setting output direction on selected pins on a given port. - * - * @param p_reg Pointer to the peripheral registers structure. - * @param out_mask Mask specifying the pins to set as output. - * - */ -__STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask); - -/** - * @brief Function for setting input direction on selected pins on a given port. - * - * @param p_reg Pointer to the peripheral registers structure. - * @param in_mask Mask specifying the pins to set as input. - * - */ -__STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask); - -/** - * @brief Function for writing the direction configuration of GPIO pins in a given port. - * - * @param p_reg Pointer to the peripheral registers structure. - * @param dir_mask Mask specifying the direction of pins. Bit set means that the given pin is configured as output. - * - */ -__STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t dir_mask); - -/** - * @brief Function for reading the direction configuration of a GPIO port. - * - * @param p_reg Pointer to the peripheral registers structure. - * - * @retval Pin configuration of the current direction settings. Bit set means that the given pin is configured as output. - */ -__STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg); - -/** - * @brief Function for reading the input signals of GPIO pins on a given port. - * - * @param p_reg Pointer to the peripheral registers structure. - * - * @retval Port input values. - */ -__STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg); - -/** - * @brief Function for reading the output signals of GPIO pins of a given port. - * - * @param p_reg Pointer to the peripheral registers structure. - * - * @retval Port output values. - */ -__STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg); - -/** - * @brief Function for writing the GPIO pins output on a given port. - * - * @param p_reg Pointer to the peripheral registers structure. - * @param value Output port mask. - * - */ -__STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value); - -/** - * @brief Function for setting high level on selected GPIO pins of a given port. - * - * @param p_reg Pointer to the peripheral registers structure. - * @param set_mask Mask with pins to set as logical high level. - * - */ -__STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask); - -/** - * @brief Function for setting low level on selected GPIO pins of a given port. - * - * @param p_reg Pointer to the peripheral registers structure. - * @param clr_mask Mask with pins to set as logical low level. - * - */ -__STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask); - -/** - * @brief Function for reading pins state of multiple consecutive ports. - * - * @param start_port Index of the first port to read. - * @param length Number of ports to read. - * @param p_masks Pointer to output array where port states will be stored. - */ -__STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port, uint32_t length, uint32_t * p_masks); - -#if defined(GPIO_DETECTMODE_DETECTMODE_LDETECT) || defined(__NRF_DOXYGEN__) -/** - * @brief Function for reading latch state of multiple consecutive ports. - * - * @param start_port Index of the first port to read. - * @param length Number of ports to read. - * @param p_masks Pointer to output array where latch states will be stored. - */ -__STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port, uint32_t length, - uint32_t * p_masks); - -/** - * @brief Function for reading latch state of single pin. - * - * @param pin_number Pin number. - * @return 0 if latch is not set. Positive value otherwise. - * - */ -__STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number); - -/** - * @brief Function for clearing latch state of a single pin. - * - * @param pin_number Pin number. - * - */ -__STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number); -#endif - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -/** - * @brief Function for extracting port and relative pin number from absolute pin number. - * - * @param[inout] Pointer to absolute pin number which is overriden by relative to port pin number. - * - * @return Pointer to port register set. - * - */ -__STATIC_INLINE NRF_GPIO_Type * nrf_gpio_pin_port_decode(uint32_t * p_pin) -{ - NRFX_ASSERT(*p_pin < NUMBER_OF_PINS); -#if (GPIO_COUNT == 1) - // The oldest definition case - return NRF_GPIO; -#else - if (*p_pin < P0_PIN_NUM) - { - return NRF_P0; - } - else - { - *p_pin = *p_pin & (P0_PIN_NUM - 1); - return NRF_P1; - } -#endif -} - - -__STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end) -{ - /*lint -e{845} // A zero has been given as right argument to operator '|'" */ - for (; pin_range_start <= pin_range_end; pin_range_start++) - { - nrf_gpio_cfg_output(pin_range_start); - } -} - - -__STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start, - uint32_t pin_range_end, - nrf_gpio_pin_pull_t pull_config) -{ - /*lint -e{845} // A zero has been given as right argument to operator '|'" */ - for (; pin_range_start <= pin_range_end; pin_range_start++) - { - nrf_gpio_cfg_input(pin_range_start, pull_config); - } -} - - -__STATIC_INLINE void nrf_gpio_cfg( - uint32_t pin_number, - nrf_gpio_pin_dir_t dir, - nrf_gpio_pin_input_t input, - nrf_gpio_pin_pull_t pull, - nrf_gpio_pin_drive_t drive, - nrf_gpio_pin_sense_t sense) -{ - NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); - - reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos) - | ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos) - | ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos) - | ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) - | ((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos); -} - - -__STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number) -{ - nrf_gpio_cfg( - pin_number, - NRF_GPIO_PIN_DIR_OUTPUT, - NRF_GPIO_PIN_INPUT_DISCONNECT, - NRF_GPIO_PIN_NOPULL, - NRF_GPIO_PIN_S0S1, - NRF_GPIO_PIN_NOSENSE); -} - - -__STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config) -{ - nrf_gpio_cfg( - pin_number, - NRF_GPIO_PIN_DIR_INPUT, - NRF_GPIO_PIN_INPUT_CONNECT, - pull_config, - NRF_GPIO_PIN_S0S1, - NRF_GPIO_PIN_NOSENSE); -} - - -__STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number) -{ - nrf_gpio_cfg( - pin_number, - NRF_GPIO_PIN_DIR_INPUT, - NRF_GPIO_PIN_INPUT_DISCONNECT, - NRF_GPIO_PIN_NOPULL, - NRF_GPIO_PIN_S0S1, - NRF_GPIO_PIN_NOSENSE); -} - - -__STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number) -{ - NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); - /*lint -e{845} // A zero has been given as right argument to operator '|'" */ - uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk; - - reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos); -} - - -__STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number) -{ - NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); - /*lint -e{845} // A zero has been given as right argument to operator '|'" */ - uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk; - - reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos); -} - - -__STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number, - nrf_gpio_pin_pull_t pull_config, - nrf_gpio_pin_sense_t sense_config) -{ - nrf_gpio_cfg( - pin_number, - NRF_GPIO_PIN_DIR_INPUT, - NRF_GPIO_PIN_INPUT_CONNECT, - pull_config, - NRF_GPIO_PIN_S0S1, - sense_config); -} - - -__STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config) -{ - NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); - - /*lint -e{845} // A zero has been given as right argument to operator '|'" */ - reg->PIN_CNF[pin_number] &= ~GPIO_PIN_CNF_SENSE_Msk; - reg->PIN_CNF[pin_number] |= (sense_config << GPIO_PIN_CNF_SENSE_Pos); -} - - -__STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction) -{ - if (direction == NRF_GPIO_PIN_DIR_INPUT) - { - nrf_gpio_cfg( - pin_number, - NRF_GPIO_PIN_DIR_INPUT, - NRF_GPIO_PIN_INPUT_CONNECT, - NRF_GPIO_PIN_NOPULL, - NRF_GPIO_PIN_S0S1, - NRF_GPIO_PIN_NOSENSE); - } - else - { - NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); - reg->DIRSET = (1UL << pin_number); - } -} - - -__STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number) -{ - NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); - - nrf_gpio_port_out_set(reg, 1UL << pin_number); -} - - -__STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number) -{ - NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); - - nrf_gpio_port_out_clear(reg, 1UL << pin_number); -} - - -__STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number) -{ - NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); - uint32_t pins_state = reg->OUT; - - reg->OUTSET = (~pins_state & (1UL << pin_number)); - reg->OUTCLR = (pins_state & (1UL << pin_number)); -} - - -__STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value) -{ - if (value == 0) - { - nrf_gpio_pin_clear(pin_number); - } - else - { - nrf_gpio_pin_set(pin_number); - } -} - - -__STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number) -{ - NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); - - return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL); -} - - -__STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number) -{ - NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); - - return ((nrf_gpio_port_out_read(reg) >> pin_number) & 1UL); -} - - -__STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number) -{ - NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); - - return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] & - GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos); -} - - -__STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask) -{ - p_reg->DIRSET = out_mask; -} - - -__STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask) -{ - p_reg->DIRCLR = in_mask; -} - - -__STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t value) -{ - p_reg->DIR = value; -} - - -__STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg) -{ - return p_reg->DIR; -} - - -__STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg) -{ - return p_reg->IN; -} - - -__STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg) -{ - return p_reg->OUT; -} - - -__STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value) -{ - p_reg->OUT = value; -} - - -__STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask) -{ - p_reg->OUTSET = set_mask; -} - - -__STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask) -{ - p_reg->OUTCLR = clr_mask; -} - - -__STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port, uint32_t length, uint32_t * p_masks) -{ - NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST; - - NRFX_ASSERT(start_port + length <= GPIO_COUNT); - uint32_t i; - - for (i = start_port; i < (start_port + length); i++) - { - *p_masks = nrf_gpio_port_in_read(gpio_regs[i]); - p_masks++; - } -} - - -#ifdef GPIO_DETECTMODE_DETECTMODE_LDETECT -__STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port, uint32_t length, uint32_t * p_masks) -{ - NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST; - uint32_t i; - - for (i = start_port; i < (start_port + length); i++) - { - *p_masks = gpio_regs[i]->LATCH; - p_masks++; - } -} - - -__STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number) -{ - NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); - - return (reg->LATCH & (1 << pin_number)) ? 1 : 0; -} - - -__STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number) -{ - NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); - - reg->LATCH = (1 << pin_number); -} - - -#endif -#endif // SUPPRESS_INLINE_IMPLEMENTATION - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_GPIO_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_gpiote.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_gpiote.h deleted file mode 100644 index 8997048870..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_gpiote.h +++ /dev/null @@ -1,428 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_GPIOTE_H__ -#define NRF_GPIOTE_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** -* @defgroup nrf_gpiote_hal GPIOTE HAL -* @{ -* @ingroup nrf_gpiote -* @brief Hardware access layer for managing the GPIOTE peripheral. -*/ - -#ifdef GPIOTE_CONFIG_PORT_Msk -#define GPIOTE_CONFIG_PORT_PIN_Msk (GPIOTE_CONFIG_PORT_Msk | GPIOTE_CONFIG_PSEL_Msk) -#else -#define GPIOTE_CONFIG_PORT_PIN_Msk GPIOTE_CONFIG_PSEL_Msk -#endif - - /** - * @enum nrf_gpiote_polarity_t - * @brief Polarity for the GPIOTE channel. - */ -typedef enum -{ - NRF_GPIOTE_POLARITY_LOTOHI = GPIOTE_CONFIG_POLARITY_LoToHi, ///< Low to high. - NRF_GPIOTE_POLARITY_HITOLO = GPIOTE_CONFIG_POLARITY_HiToLo, ///< High to low. - NRF_GPIOTE_POLARITY_TOGGLE = GPIOTE_CONFIG_POLARITY_Toggle ///< Toggle. -} nrf_gpiote_polarity_t; - - - /** - * @enum nrf_gpiote_outinit_t - * @brief Initial output value for the GPIOTE channel. - */ -typedef enum -{ - NRF_GPIOTE_INITIAL_VALUE_LOW = GPIOTE_CONFIG_OUTINIT_Low, ///< Low to high. - NRF_GPIOTE_INITIAL_VALUE_HIGH = GPIOTE_CONFIG_OUTINIT_High ///< High to low. -} nrf_gpiote_outinit_t; - -/** - * @brief Tasks. - */ -typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ -{ - NRF_GPIOTE_TASKS_OUT_0 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[0]), /**< Out task 0.*/ - NRF_GPIOTE_TASKS_OUT_1 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[1]), /**< Out task 1.*/ - NRF_GPIOTE_TASKS_OUT_2 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[2]), /**< Out task 2.*/ - NRF_GPIOTE_TASKS_OUT_3 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[3]), /**< Out task 3.*/ -#if (GPIOTE_CH_NUM > 4) || defined(__NRFX_DOXYGEN__) - NRF_GPIOTE_TASKS_OUT_4 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[4]), /**< Out task 4.*/ - NRF_GPIOTE_TASKS_OUT_5 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[5]), /**< Out task 5.*/ - NRF_GPIOTE_TASKS_OUT_6 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[6]), /**< Out task 6.*/ - NRF_GPIOTE_TASKS_OUT_7 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[7]), /**< Out task 7.*/ -#endif -#if defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__NRFX_DOXYGEN__) - NRF_GPIOTE_TASKS_SET_0 = offsetof(NRF_GPIOTE_Type, TASKS_SET[0]), /**< Set task 0.*/ - NRF_GPIOTE_TASKS_SET_1 = offsetof(NRF_GPIOTE_Type, TASKS_SET[1]), /**< Set task 1.*/ - NRF_GPIOTE_TASKS_SET_2 = offsetof(NRF_GPIOTE_Type, TASKS_SET[2]), /**< Set task 2.*/ - NRF_GPIOTE_TASKS_SET_3 = offsetof(NRF_GPIOTE_Type, TASKS_SET[3]), /**< Set task 3.*/ - NRF_GPIOTE_TASKS_SET_4 = offsetof(NRF_GPIOTE_Type, TASKS_SET[4]), /**< Set task 4.*/ - NRF_GPIOTE_TASKS_SET_5 = offsetof(NRF_GPIOTE_Type, TASKS_SET[5]), /**< Set task 5.*/ - NRF_GPIOTE_TASKS_SET_6 = offsetof(NRF_GPIOTE_Type, TASKS_SET[6]), /**< Set task 6.*/ - NRF_GPIOTE_TASKS_SET_7 = offsetof(NRF_GPIOTE_Type, TASKS_SET[7]), /**< Set task 7.*/ -#endif -#if defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__) - NRF_GPIOTE_TASKS_CLR_0 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[0]), /**< Clear task 0.*/ - NRF_GPIOTE_TASKS_CLR_1 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[1]), /**< Clear task 1.*/ - NRF_GPIOTE_TASKS_CLR_2 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[2]), /**< Clear task 2.*/ - NRF_GPIOTE_TASKS_CLR_3 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[3]), /**< Clear task 3.*/ - NRF_GPIOTE_TASKS_CLR_4 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[4]), /**< Clear task 4.*/ - NRF_GPIOTE_TASKS_CLR_5 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[5]), /**< Clear task 5.*/ - NRF_GPIOTE_TASKS_CLR_6 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[6]), /**< Clear task 6.*/ - NRF_GPIOTE_TASKS_CLR_7 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[7]), /**< Clear task 7.*/ -#endif - /*lint -restore*/ -} nrf_gpiote_tasks_t; - -/** - * @brief Events. - */ -typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ -{ - NRF_GPIOTE_EVENTS_IN_0 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[0]), /**< In event 0.*/ - NRF_GPIOTE_EVENTS_IN_1 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[1]), /**< In event 1.*/ - NRF_GPIOTE_EVENTS_IN_2 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[2]), /**< In event 2.*/ - NRF_GPIOTE_EVENTS_IN_3 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[3]), /**< In event 3.*/ -#if (GPIOTE_CH_NUM > 4) || defined(__NRFX_DOXYGEN__) - NRF_GPIOTE_EVENTS_IN_4 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[4]), /**< In event 4.*/ - NRF_GPIOTE_EVENTS_IN_5 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[5]), /**< In event 5.*/ - NRF_GPIOTE_EVENTS_IN_6 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[6]), /**< In event 6.*/ - NRF_GPIOTE_EVENTS_IN_7 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[7]), /**< In event 7.*/ -#endif - NRF_GPIOTE_EVENTS_PORT = offsetof(NRF_GPIOTE_Type, EVENTS_PORT), /**< Port event.*/ - /*lint -restore*/ -} nrf_gpiote_events_t; - -/** - * @enum nrf_gpiote_int_t - * @brief GPIOTE interrupts. - */ -typedef enum -{ - NRF_GPIOTE_INT_IN0_MASK = GPIOTE_INTENSET_IN0_Msk, /**< GPIOTE interrupt from IN0. */ - NRF_GPIOTE_INT_IN1_MASK = GPIOTE_INTENSET_IN1_Msk, /**< GPIOTE interrupt from IN1. */ - NRF_GPIOTE_INT_IN2_MASK = GPIOTE_INTENSET_IN2_Msk, /**< GPIOTE interrupt from IN2. */ - NRF_GPIOTE_INT_IN3_MASK = GPIOTE_INTENSET_IN3_Msk, /**< GPIOTE interrupt from IN3. */ -#if (GPIOTE_CH_NUM > 4) || defined(__NRFX_DOXYGEN__) - NRF_GPIOTE_INT_IN4_MASK = GPIOTE_INTENSET_IN4_Msk, /**< GPIOTE interrupt from IN4. */ - NRF_GPIOTE_INT_IN5_MASK = GPIOTE_INTENSET_IN5_Msk, /**< GPIOTE interrupt from IN5. */ - NRF_GPIOTE_INT_IN6_MASK = GPIOTE_INTENSET_IN6_Msk, /**< GPIOTE interrupt from IN6. */ - NRF_GPIOTE_INT_IN7_MASK = GPIOTE_INTENSET_IN7_Msk, /**< GPIOTE interrupt from IN7. */ -#endif - NRF_GPIOTE_INT_PORT_MASK = (int)GPIOTE_INTENSET_PORT_Msk, /**< GPIOTE interrupt from PORT event. */ -} nrf_gpiote_int_t; - -#define NRF_GPIOTE_INT_IN_MASK (NRF_GPIOTE_INT_IN0_MASK | NRF_GPIOTE_INT_IN1_MASK |\ - NRF_GPIOTE_INT_IN2_MASK | NRF_GPIOTE_INT_IN3_MASK) -#if (GPIOTE_CH_NUM > 4) -#undef NRF_GPIOTE_INT_IN_MASK -#define NRF_GPIOTE_INT_IN_MASK (NRF_GPIOTE_INT_IN0_MASK | NRF_GPIOTE_INT_IN1_MASK |\ - NRF_GPIOTE_INT_IN2_MASK | NRF_GPIOTE_INT_IN3_MASK |\ - NRF_GPIOTE_INT_IN4_MASK | NRF_GPIOTE_INT_IN5_MASK |\ - NRF_GPIOTE_INT_IN6_MASK | NRF_GPIOTE_INT_IN7_MASK) -#endif - -/** - * @brief Function for activating a specific GPIOTE task. - * - * @param[in] task Task. - */ -__STATIC_INLINE void nrf_gpiote_task_set(nrf_gpiote_tasks_t task); - -/** - * @brief Function for getting the address of a specific GPIOTE task. - * - * @param[in] task Task. - * - * @returns Address. - */ -__STATIC_INLINE uint32_t nrf_gpiote_task_addr_get(nrf_gpiote_tasks_t task); - -/** - * @brief Function for getting the state of a specific GPIOTE event. - * - * @param[in] event Event. - */ -__STATIC_INLINE bool nrf_gpiote_event_is_set(nrf_gpiote_events_t event); - -/** - * @brief Function for clearing a specific GPIOTE event. - * - * @param[in] event Event. - */ -__STATIC_INLINE void nrf_gpiote_event_clear(nrf_gpiote_events_t event); - -/** - * @brief Function for getting the address of a specific GPIOTE event. - * - * @param[in] event Event. - * - * @return Address - */ -__STATIC_INLINE uint32_t nrf_gpiote_event_addr_get(nrf_gpiote_events_t event); - -/**@brief Function for enabling interrupts. - * - * @param[in] mask Interrupt mask to be enabled. - */ -__STATIC_INLINE void nrf_gpiote_int_enable(uint32_t mask); - -/**@brief Function for disabling interrupts. - * - * @param[in] mask Interrupt mask to be disabled. - */ -__STATIC_INLINE void nrf_gpiote_int_disable(uint32_t mask); - -/**@brief Function for checking if interrupts are enabled. - * - * @param[in] mask Mask of interrupt flags to check. - * - * @return Mask with enabled interrupts. - */ -__STATIC_INLINE uint32_t nrf_gpiote_int_is_enabled(uint32_t mask); - -/**@brief Function for enabling a GPIOTE event. - * - * @param[in] idx Task-Event index. - */ -__STATIC_INLINE void nrf_gpiote_event_enable(uint32_t idx); - -/**@brief Function for disabling a GPIOTE event. - * - * @param[in] idx Task-Event index. - */ -__STATIC_INLINE void nrf_gpiote_event_disable(uint32_t idx); - -/**@brief Function for configuring a GPIOTE event. - * - * @param[in] idx Task-Event index. - * @param[in] pin Pin associated with event. - * @param[in] polarity Transition that should generate an event. - */ -__STATIC_INLINE void nrf_gpiote_event_configure(uint32_t idx, uint32_t pin, - nrf_gpiote_polarity_t polarity); - -/**@brief Function for getting the pin associated with a GPIOTE event. - * - * @param[in] idx Task-Event index. - * - * @return Pin number. - */ -__STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(uint32_t idx); - -/**@brief Function for getting the polarity associated with a GPIOTE event. - * - * @param[in] idx Task-Event index. - * - * @return Polarity. - */ -__STATIC_INLINE nrf_gpiote_polarity_t nrf_gpiote_event_polarity_get(uint32_t idx); - -/**@brief Function for enabling a GPIOTE task. - * - * @param[in] idx Task-Event index. - */ -__STATIC_INLINE void nrf_gpiote_task_enable(uint32_t idx); - -/**@brief Function for disabling a GPIOTE task. - * - * @param[in] idx Task-Event index. - */ -__STATIC_INLINE void nrf_gpiote_task_disable(uint32_t idx); - -/**@brief Function for configuring a GPIOTE task. - * @note Function is not configuring mode field so task is disabled after this function is called. - * - * @param[in] idx Task-Event index. - * @param[in] pin Pin associated with event. - * @param[in] polarity Transition that should generate an event. - * @param[in] init_val Initial value of the pin. - */ -__STATIC_INLINE void nrf_gpiote_task_configure(uint32_t idx, uint32_t pin, - nrf_gpiote_polarity_t polarity, - nrf_gpiote_outinit_t init_val); - -/**@brief Function for forcing a specific state on the pin connected to GPIOTE. - * - * @param[in] idx Task-Event index. - * @param[in] init_val Pin state. - */ -__STATIC_INLINE void nrf_gpiote_task_force(uint32_t idx, nrf_gpiote_outinit_t init_val); - -/**@brief Function for resetting a GPIOTE task event configuration to the default state. - * - * @param[in] idx Task-Event index. - */ -__STATIC_INLINE void nrf_gpiote_te_default(uint32_t idx); - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION -__STATIC_INLINE void nrf_gpiote_task_set(nrf_gpiote_tasks_t task) -{ - *(__IO uint32_t *)((uint32_t)NRF_GPIOTE + task) = 0x1UL; -} - -__STATIC_INLINE uint32_t nrf_gpiote_task_addr_get(nrf_gpiote_tasks_t task) -{ - return ((uint32_t)NRF_GPIOTE + task); -} - -__STATIC_INLINE bool nrf_gpiote_event_is_set(nrf_gpiote_events_t event) -{ - return (*(uint32_t *)nrf_gpiote_event_addr_get(event) == 0x1UL) ? true : false; -} - -__STATIC_INLINE void nrf_gpiote_event_clear(nrf_gpiote_events_t event) -{ - *(uint32_t *)nrf_gpiote_event_addr_get(event) = 0; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)nrf_gpiote_event_addr_get(event)); - (void)dummy; -#endif -} - -__STATIC_INLINE uint32_t nrf_gpiote_event_addr_get(nrf_gpiote_events_t event) -{ - return ((uint32_t)NRF_GPIOTE + event); -} - -__STATIC_INLINE void nrf_gpiote_int_enable(uint32_t mask) -{ - NRF_GPIOTE->INTENSET = mask; -} - -__STATIC_INLINE void nrf_gpiote_int_disable(uint32_t mask) -{ - NRF_GPIOTE->INTENCLR = mask; -} - -__STATIC_INLINE uint32_t nrf_gpiote_int_is_enabled(uint32_t mask) -{ - return (NRF_GPIOTE->INTENSET & mask); -} - -__STATIC_INLINE void nrf_gpiote_event_enable(uint32_t idx) -{ - NRF_GPIOTE->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event; -} - -__STATIC_INLINE void nrf_gpiote_event_disable(uint32_t idx) -{ - NRF_GPIOTE->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Event; -} - -__STATIC_INLINE void nrf_gpiote_event_configure(uint32_t idx, uint32_t pin, nrf_gpiote_polarity_t polarity) -{ - NRF_GPIOTE->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk); - NRF_GPIOTE->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) | - ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk); -} - -__STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(uint32_t idx) -{ - return ((NRF_GPIOTE->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos); -} - -__STATIC_INLINE nrf_gpiote_polarity_t nrf_gpiote_event_polarity_get(uint32_t idx) -{ - return (nrf_gpiote_polarity_t)((NRF_GPIOTE->CONFIG[idx] & GPIOTE_CONFIG_POLARITY_Msk) >> GPIOTE_CONFIG_POLARITY_Pos); -} - -__STATIC_INLINE void nrf_gpiote_task_enable(uint32_t idx) -{ - uint32_t final_config = NRF_GPIOTE->CONFIG[idx] | GPIOTE_CONFIG_MODE_Task; -#ifdef NRF51 - /* Workaround for the OUTINIT PAN. When nrf_gpiote_task_config() is called a glitch happens - on the GPIO if the GPIO in question is already assigned to GPIOTE and the pin is in the - correct state in GPIOTE but not in the OUT register. */ - /* Configure channel to not existing, not connected to the pin, and configure as a tasks that will set it to proper level */ - NRF_GPIOTE->CONFIG[idx] = final_config | (((31) << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk); - __NOP(); - __NOP(); - __NOP(); -#endif - NRF_GPIOTE->CONFIG[idx] = final_config; -} - -__STATIC_INLINE void nrf_gpiote_task_disable(uint32_t idx) -{ - NRF_GPIOTE->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Task; -} - -__STATIC_INLINE void nrf_gpiote_task_configure(uint32_t idx, uint32_t pin, - nrf_gpiote_polarity_t polarity, - nrf_gpiote_outinit_t init_val) -{ - NRF_GPIOTE->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | - GPIOTE_CONFIG_POLARITY_Msk | - GPIOTE_CONFIG_OUTINIT_Msk); - - NRF_GPIOTE->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) | - ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) | - ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk); -} - -__STATIC_INLINE void nrf_gpiote_task_force(uint32_t idx, nrf_gpiote_outinit_t init_val) -{ - NRF_GPIOTE->CONFIG[idx] = (NRF_GPIOTE->CONFIG[idx] & ~GPIOTE_CONFIG_OUTINIT_Msk) - | ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk); -} - -__STATIC_INLINE void nrf_gpiote_te_default(uint32_t idx) -{ - NRF_GPIOTE->CONFIG[idx] = 0; -} -#endif //SUPPRESS_INLINE_IMPLEMENTATION - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_i2s.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_i2s.h deleted file mode 100644 index 9b48f08f95..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_i2s.h +++ /dev/null @@ -1,557 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_I2S_H__ -#define NRF_I2S_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_i2s_hal I2S HAL - * @{ - * @ingroup nrf_i2s - * @brief Hardware access layer for managing the Inter-IC Sound (I2S) peripheral. - */ - -/** - * @brief This value can be provided as a parameter for the @ref nrf_i2s_pins_set - * function call to specify that a given I2S signal (SDOUT, SDIN, or MCK) - * shall not be connected to a physical pin. - */ -#define NRF_I2S_PIN_NOT_CONNECTED 0xFFFFFFFF - - -/** - * @brief I2S tasks. - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_I2S_TASK_START = offsetof(NRF_I2S_Type, TASKS_START), ///< Starts continuous I2S transfer. Also starts the MCK generator if this is enabled. - NRF_I2S_TASK_STOP = offsetof(NRF_I2S_Type, TASKS_STOP) ///< Stops I2S transfer. Also stops the MCK generator. - /*lint -restore*/ -} nrf_i2s_task_t; - -/** - * @brief I2S events. - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_I2S_EVENT_RXPTRUPD = offsetof(NRF_I2S_Type, EVENTS_RXPTRUPD), ///< The RXD.PTR register has been copied to internal double-buffers. - NRF_I2S_EVENT_TXPTRUPD = offsetof(NRF_I2S_Type, EVENTS_TXPTRUPD), ///< The TXD.PTR register has been copied to internal double-buffers. - NRF_I2S_EVENT_STOPPED = offsetof(NRF_I2S_Type, EVENTS_STOPPED) ///< I2S transfer stopped. - /*lint -restore*/ -} nrf_i2s_event_t; - -/** - * @brief I2S interrupts. - */ -typedef enum -{ - NRF_I2S_INT_RXPTRUPD_MASK = I2S_INTENSET_RXPTRUPD_Msk, ///< Interrupt on RXPTRUPD event. - NRF_I2S_INT_TXPTRUPD_MASK = I2S_INTENSET_TXPTRUPD_Msk, ///< Interrupt on TXPTRUPD event. - NRF_I2S_INT_STOPPED_MASK = I2S_INTENSET_STOPPED_Msk ///< Interrupt on STOPPED event. -} nrf_i2s_int_mask_t; - -/** - * @brief I2S modes of operation. - */ -typedef enum -{ - NRF_I2S_MODE_MASTER = I2S_CONFIG_MODE_MODE_Master, ///< Master mode. - NRF_I2S_MODE_SLAVE = I2S_CONFIG_MODE_MODE_Slave ///< Slave mode. -} nrf_i2s_mode_t; - -/** - * @brief I2S master clock generator settings. - */ -typedef enum -{ - NRF_I2S_MCK_DISABLED = 0, ///< MCK disabled. - // [conversion to 'int' needed to prevent compilers from complaining - // that the provided value (0x80000000UL) is out of range of "int"] - NRF_I2S_MCK_32MDIV2 = (int)I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2, ///< 32 MHz / 2 = 16.0 MHz. - NRF_I2S_MCK_32MDIV3 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3, ///< 32 MHz / 3 = 10.6666667 MHz. - NRF_I2S_MCK_32MDIV4 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4, ///< 32 MHz / 4 = 8.0 MHz. - NRF_I2S_MCK_32MDIV5 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5, ///< 32 MHz / 5 = 6.4 MHz. - NRF_I2S_MCK_32MDIV6 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6, ///< 32 MHz / 6 = 5.3333333 MHz. - NRF_I2S_MCK_32MDIV8 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8, ///< 32 MHz / 8 = 4.0 MHz. - NRF_I2S_MCK_32MDIV10 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10, ///< 32 MHz / 10 = 3.2 MHz. - NRF_I2S_MCK_32MDIV11 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11, ///< 32 MHz / 11 = 2.9090909 MHz. - NRF_I2S_MCK_32MDIV15 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15, ///< 32 MHz / 15 = 2.1333333 MHz. - NRF_I2S_MCK_32MDIV16 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16, ///< 32 MHz / 16 = 2.0 MHz. - NRF_I2S_MCK_32MDIV21 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21, ///< 32 MHz / 21 = 1.5238095 MHz. - NRF_I2S_MCK_32MDIV23 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23, ///< 32 MHz / 23 = 1.3913043 MHz. - NRF_I2S_MCK_32MDIV31 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31, ///< 32 MHz / 31 = 1.0322581 MHz. - NRF_I2S_MCK_32MDIV42 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42, ///< 32 MHz / 42 = 0.7619048 MHz. - NRF_I2S_MCK_32MDIV63 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63, ///< 32 MHz / 63 = 0.5079365 MHz. - NRF_I2S_MCK_32MDIV125 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 ///< 32 MHz / 125 = 0.256 MHz. -} nrf_i2s_mck_t; - -/** - * @brief I2S MCK/LRCK ratios. - */ -typedef enum -{ - NRF_I2S_RATIO_32X = I2S_CONFIG_RATIO_RATIO_32X, ///< LRCK = MCK / 32. - NRF_I2S_RATIO_48X = I2S_CONFIG_RATIO_RATIO_48X, ///< LRCK = MCK / 48. - NRF_I2S_RATIO_64X = I2S_CONFIG_RATIO_RATIO_64X, ///< LRCK = MCK / 64. - NRF_I2S_RATIO_96X = I2S_CONFIG_RATIO_RATIO_96X, ///< LRCK = MCK / 96. - NRF_I2S_RATIO_128X = I2S_CONFIG_RATIO_RATIO_128X, ///< LRCK = MCK / 128. - NRF_I2S_RATIO_192X = I2S_CONFIG_RATIO_RATIO_192X, ///< LRCK = MCK / 192. - NRF_I2S_RATIO_256X = I2S_CONFIG_RATIO_RATIO_256X, ///< LRCK = MCK / 256. - NRF_I2S_RATIO_384X = I2S_CONFIG_RATIO_RATIO_384X, ///< LRCK = MCK / 384. - NRF_I2S_RATIO_512X = I2S_CONFIG_RATIO_RATIO_512X ///< LRCK = MCK / 512. -} nrf_i2s_ratio_t; - -/** - * @brief I2S sample widths. - */ -typedef enum -{ - NRF_I2S_SWIDTH_8BIT = I2S_CONFIG_SWIDTH_SWIDTH_8Bit, ///< 8 bit. - NRF_I2S_SWIDTH_16BIT = I2S_CONFIG_SWIDTH_SWIDTH_16Bit, ///< 16 bit. - NRF_I2S_SWIDTH_24BIT = I2S_CONFIG_SWIDTH_SWIDTH_24Bit ///< 24 bit. -} nrf_i2s_swidth_t; - -/** - * @brief I2S alignments of sample within a frame. - */ -typedef enum -{ - NRF_I2S_ALIGN_LEFT = I2S_CONFIG_ALIGN_ALIGN_Left, ///< Left-aligned. - NRF_I2S_ALIGN_RIGHT = I2S_CONFIG_ALIGN_ALIGN_Right ///< Right-aligned. -} nrf_i2s_align_t; - -/** - * @brief I2S frame formats. - */ -typedef enum -{ - NRF_I2S_FORMAT_I2S = I2S_CONFIG_FORMAT_FORMAT_I2S, ///< Original I2S format. - NRF_I2S_FORMAT_ALIGNED = I2S_CONFIG_FORMAT_FORMAT_Aligned ///< Alternate (left- or right-aligned) format. -} nrf_i2s_format_t; - -/** - * @brief I2S enabled channels. - */ -typedef enum -{ - NRF_I2S_CHANNELS_STEREO = I2S_CONFIG_CHANNELS_CHANNELS_Stereo, ///< Stereo. - NRF_I2S_CHANNELS_LEFT = I2S_CONFIG_CHANNELS_CHANNELS_Left, ///< Left only. - NRF_I2S_CHANNELS_RIGHT = I2S_CONFIG_CHANNELS_CHANNELS_Right ///< Right only. -} nrf_i2s_channels_t; - - -/** - * @brief Function for activating a specific I2S task. - * - * @param[in] p_i2s I2S instance. - * @param[in] task Task to activate. - */ -__STATIC_INLINE void nrf_i2s_task_trigger(NRF_I2S_Type * p_i2s, - nrf_i2s_task_t task); - -/** - * @brief Function for getting the address of a specific I2S task register. - * - * @param[in] p_i2s I2S instance. - * @param[in] task Requested task. - * - * @return Address of the specified task register. - */ -__STATIC_INLINE uint32_t nrf_i2s_task_address_get(NRF_I2S_Type const * p_i2s, - nrf_i2s_task_t task); - -/** - * @brief Function for clearing a specific I2S event. - * - * @param[in] p_i2s I2S instance. - * @param[in] event Event to clear. - */ -__STATIC_INLINE void nrf_i2s_event_clear(NRF_I2S_Type * p_i2s, - nrf_i2s_event_t event); - -/** - * @brief Function for checking the state of a specific I2S event. - * - * @param[in] p_i2s I2S instance. - * @param[in] event Event to check. - * - * @retval true If the event is set. - * @retval false If the event is not set. - */ -__STATIC_INLINE bool nrf_i2s_event_check(NRF_I2S_Type const * p_i2s, - nrf_i2s_event_t event); - -/** - * @brief Function for getting the address of a specific I2S event register. - * - * @param[in] p_i2s I2S instance. - * @param[in] event Requested event. - * - * @return Address of the specified event register. - */ -__STATIC_INLINE uint32_t nrf_i2s_event_address_get(NRF_I2S_Type const * p_i2s, - nrf_i2s_event_t event); - -/** - * @brief Function for enabling specified interrupts. - * - * @param[in] p_i2s I2S instance. - * @param[in] mask Interrupts to enable. - */ -__STATIC_INLINE void nrf_i2s_int_enable(NRF_I2S_Type * p_i2s, uint32_t mask); - -/** - * @brief Function for disabling specified interrupts. - * - * @param[in] p_i2s I2S instance. - * @param[in] mask Interrupts to disable. - */ -__STATIC_INLINE void nrf_i2s_int_disable(NRF_I2S_Type * p_i2s, uint32_t mask); - -/** - * @brief Function for retrieving the state of a given interrupt. - * - * @param[in] p_i2s I2S instance. - * @param[in] i2s_int Interrupt to check. - * - * @retval true If the interrupt is enabled. - * @retval false If the interrupt is not enabled. - */ -__STATIC_INLINE bool nrf_i2s_int_enable_check(NRF_I2S_Type const * p_i2s, - nrf_i2s_int_mask_t i2s_int); - -/** - * @brief Function for enabling the I2S peripheral. - * - * @param[in] p_i2s I2S instance. - */ -__STATIC_INLINE void nrf_i2s_enable(NRF_I2S_Type * p_i2s); - -/** - * @brief Function for disabling the I2S peripheral. - * - * @param[in] p_i2s I2S instance. - */ -__STATIC_INLINE void nrf_i2s_disable(NRF_I2S_Type * p_i2s); - -/** - * @brief Function for configuring I2S pins. - * - * Usage of the SDOUT, SDIN, and MCK signals is optional. - * If a given signal is not needed, pass the @ref NRF_I2S_PIN_NOT_CONNECTED - * value instead of its pin number. - * - * @param[in] p_i2s I2S instance. - * @param[in] sck_pin SCK pin number. - * @param[in] lrck_pin LRCK pin number. - * @param[in] mck_pin MCK pin number. - * @param[in] sdout_pin SDOUT pin number. - * @param[in] sdin_pin SDIN pin number. - */ -__STATIC_INLINE void nrf_i2s_pins_set(NRF_I2S_Type * p_i2s, - uint32_t sck_pin, - uint32_t lrck_pin, - uint32_t mck_pin, - uint32_t sdout_pin, - uint32_t sdin_pin); - -/** - * @brief Function for setting the I2S peripheral configuration. - * - * @param[in] p_i2s I2S instance. - * @param[in] mode Mode of operation (master or slave). - * @param[in] format I2S frame format. - * @param[in] alignment Alignment of sample within a frame. - * @param[in] sample_width Sample width. - * @param[in] channels Enabled channels. - * @param[in] mck_setup Master clock generator setup. - * @param[in] ratio MCK/LRCK ratio. - * - * @retval true If the configuration has been set successfully. - * @retval false If the requested configuration is not allowed. - */ -__STATIC_INLINE bool nrf_i2s_configure(NRF_I2S_Type * p_i2s, - nrf_i2s_mode_t mode, - nrf_i2s_format_t format, - nrf_i2s_align_t alignment, - nrf_i2s_swidth_t sample_width, - nrf_i2s_channels_t channels, - nrf_i2s_mck_t mck_setup, - nrf_i2s_ratio_t ratio); - -/** - * @brief Function for setting up the I2S transfer. - * - * This function sets up the RX and TX buffers and enables reception and/or - * transmission accordingly. If the transfer in a given direction is not - * required, pass NULL instead of the pointer to the corresponding buffer. - * - * @param[in] p_i2s I2S instance. - * @param[in] size Size of the buffers (in 32-bit words). - * @param[in] p_rx_buffer Pointer to the receive buffer. - * Pass NULL to disable reception. - * @param[in] p_tx_buffer Pointer to the transmit buffer. - * Pass NULL to disable transmission. - */ -__STATIC_INLINE void nrf_i2s_transfer_set(NRF_I2S_Type * p_i2s, - uint16_t size, - uint32_t * p_rx_buffer, - uint32_t const * p_tx_buffer); - -/** - * @brief Function for setting the pointer to the receive buffer. - * - * @note The size of the buffer can be set only by calling - * @ref nrf_i2s_transfer_set. - * - * @param[in] p_i2s I2S instance. - * @param[in] p_buffer Pointer to the receive buffer. - */ -__STATIC_INLINE void nrf_i2s_rx_buffer_set(NRF_I2S_Type * p_i2s, - uint32_t * p_buffer); - -/** - * @brief Function for getting the pointer to the receive buffer. - * - * @param[in] p_i2s I2S instance. - * - * @return Pointer to the receive buffer. - */ -__STATIC_INLINE uint32_t * nrf_i2s_rx_buffer_get(NRF_I2S_Type const * p_i2s); - -/** - * @brief Function for setting the pointer to the transmit buffer. - * - * @note The size of the buffer can be set only by calling - * @ref nrf_i2s_transfer_set. - * - * @param[in] p_i2s I2S instance. - * @param[in] p_buffer Pointer to the transmit buffer. - */ -__STATIC_INLINE void nrf_i2s_tx_buffer_set(NRF_I2S_Type * p_i2s, - uint32_t const * p_buffer); - -/** - * @brief Function for getting the pointer to the transmit buffer. - * - * @param[in] p_i2s I2S instance. - * - * @return Pointer to the transmit buffer. - */ -__STATIC_INLINE uint32_t * nrf_i2s_tx_buffer_get(NRF_I2S_Type const * p_i2s); - - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -__STATIC_INLINE void nrf_i2s_task_trigger(NRF_I2S_Type * p_i2s, - nrf_i2s_task_t task) -{ - *((volatile uint32_t *)((uint8_t *)p_i2s + (uint32_t)task)) = 0x1UL; -} - -__STATIC_INLINE uint32_t nrf_i2s_task_address_get(NRF_I2S_Type const * p_i2s, - nrf_i2s_task_t task) -{ - return ((uint32_t)p_i2s + (uint32_t)task); -} - -__STATIC_INLINE void nrf_i2s_event_clear(NRF_I2S_Type * p_i2s, - nrf_i2s_event_t event) -{ - *((volatile uint32_t *)((uint8_t *)p_i2s + (uint32_t)event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_i2s + (uint32_t)event)); - (void)dummy; -#endif -} - -__STATIC_INLINE bool nrf_i2s_event_check(NRF_I2S_Type const * p_i2s, - nrf_i2s_event_t event) -{ - return (bool)*(volatile uint32_t *)((uint8_t *)p_i2s + (uint32_t)event); -} - -__STATIC_INLINE uint32_t nrf_i2s_event_address_get(NRF_I2S_Type const * p_i2s, - nrf_i2s_event_t event) -{ - return ((uint32_t)p_i2s + (uint32_t)event); -} - -__STATIC_INLINE void nrf_i2s_int_enable(NRF_I2S_Type * p_i2s, uint32_t mask) -{ - p_i2s->INTENSET = mask; -} - -__STATIC_INLINE void nrf_i2s_int_disable(NRF_I2S_Type * p_i2s, uint32_t mask) -{ - p_i2s->INTENCLR = mask; -} - -__STATIC_INLINE bool nrf_i2s_int_enable_check(NRF_I2S_Type const * p_i2s, - nrf_i2s_int_mask_t i2s_int) -{ - return (bool)(p_i2s->INTENSET & i2s_int); -} - -__STATIC_INLINE void nrf_i2s_enable(NRF_I2S_Type * p_i2s) -{ - p_i2s->ENABLE = (I2S_ENABLE_ENABLE_Enabled << I2S_ENABLE_ENABLE_Pos); -} - -__STATIC_INLINE void nrf_i2s_disable(NRF_I2S_Type * p_i2s) -{ - p_i2s->ENABLE = (I2S_ENABLE_ENABLE_Disabled << I2S_ENABLE_ENABLE_Pos); -} - -__STATIC_INLINE void nrf_i2s_pins_set(NRF_I2S_Type * p_i2s, - uint32_t sck_pin, - uint32_t lrck_pin, - uint32_t mck_pin, - uint32_t sdout_pin, - uint32_t sdin_pin) -{ - p_i2s->PSEL.SCK = sck_pin; - p_i2s->PSEL.LRCK = lrck_pin; - p_i2s->PSEL.MCK = mck_pin; - p_i2s->PSEL.SDOUT = sdout_pin; - p_i2s->PSEL.SDIN = sdin_pin; -} - -__STATIC_INLINE bool nrf_i2s_configure(NRF_I2S_Type * p_i2s, - nrf_i2s_mode_t mode, - nrf_i2s_format_t format, - nrf_i2s_align_t alignment, - nrf_i2s_swidth_t sample_width, - nrf_i2s_channels_t channels, - nrf_i2s_mck_t mck_setup, - nrf_i2s_ratio_t ratio) -{ - if (mode == NRF_I2S_MODE_MASTER) - { - // The MCK/LRCK ratio shall be a multiple of 2 * sample width. - if (((sample_width == NRF_I2S_SWIDTH_16BIT) && - (ratio == NRF_I2S_RATIO_48X)) - || - ((sample_width == NRF_I2S_SWIDTH_24BIT) && - ((ratio == NRF_I2S_RATIO_32X) || - (ratio == NRF_I2S_RATIO_64X) || - (ratio == NRF_I2S_RATIO_128X) || - (ratio == NRF_I2S_RATIO_256X) || - (ratio == NRF_I2S_RATIO_512X)))) - { - return false; - } - } - - p_i2s->CONFIG.MODE = mode; - p_i2s->CONFIG.FORMAT = format; - p_i2s->CONFIG.ALIGN = alignment; - p_i2s->CONFIG.SWIDTH = sample_width; - p_i2s->CONFIG.CHANNELS = channels; - p_i2s->CONFIG.RATIO = ratio; - - if (mck_setup == NRF_I2S_MCK_DISABLED) - { - p_i2s->CONFIG.MCKEN = - (I2S_CONFIG_MCKEN_MCKEN_Disabled << I2S_CONFIG_MCKEN_MCKEN_Pos); - } - else - { - p_i2s->CONFIG.MCKFREQ = mck_setup; - p_i2s->CONFIG.MCKEN = - (I2S_CONFIG_MCKEN_MCKEN_Enabled << I2S_CONFIG_MCKEN_MCKEN_Pos); - } - - return true; -} - -__STATIC_INLINE void nrf_i2s_transfer_set(NRF_I2S_Type * p_i2s, - uint16_t size, - uint32_t * p_buffer_rx, - uint32_t const * p_buffer_tx) -{ - p_i2s->RXTXD.MAXCNT = size; - - nrf_i2s_rx_buffer_set(p_i2s, p_buffer_rx); - p_i2s->CONFIG.RXEN = (p_buffer_rx != NULL) ? 1 : 0; - - nrf_i2s_tx_buffer_set(p_i2s, p_buffer_tx); - p_i2s->CONFIG.TXEN = (p_buffer_tx != NULL) ? 1 : 0; -} - -__STATIC_INLINE void nrf_i2s_rx_buffer_set(NRF_I2S_Type * p_i2s, - uint32_t * p_buffer) -{ - p_i2s->RXD.PTR = (uint32_t)p_buffer; -} - -__STATIC_INLINE uint32_t * nrf_i2s_rx_buffer_get(NRF_I2S_Type const * p_i2s) -{ - return (uint32_t *)(p_i2s->RXD.PTR); -} - -__STATIC_INLINE void nrf_i2s_tx_buffer_set(NRF_I2S_Type * p_i2s, - uint32_t const * p_buffer) -{ - p_i2s->TXD.PTR = (uint32_t)p_buffer; -} - -__STATIC_INLINE uint32_t * nrf_i2s_tx_buffer_get(NRF_I2S_Type const * p_i2s) -{ - return (uint32_t *)(p_i2s->TXD.PTR); -} - -#endif // SUPPRESS_INLINE_IMPLEMENTATION - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_I2S_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_lpcomp.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_lpcomp.h deleted file mode 100644 index da687fac3e..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_lpcomp.h +++ /dev/null @@ -1,412 +0,0 @@ -/** - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_LPCOMP_H_ -#define NRF_LPCOMP_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_lpcomp_hal LPCOMP HAL - * @{ - * @ingroup nrf_lpcomp - * @brief Hardware access layer for managing the Low Power Comparator (LPCOMP) peripheral. - */ - -/** - * @enum nrf_lpcomp_ref_t - * @brief LPCOMP reference selection. - */ -typedef enum -{ -#if (LPCOMP_REFSEL_RESOLUTION == 8) || defined(__NRFX_DOXYGEN__) - NRF_LPCOMP_REF_SUPPLY_1_8 = LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling, /**< Use supply with a 1/8 prescaler as reference. */ - NRF_LPCOMP_REF_SUPPLY_2_8 = LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling, /**< Use supply with a 2/8 prescaler as reference. */ - NRF_LPCOMP_REF_SUPPLY_3_8 = LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling, /**< Use supply with a 3/8 prescaler as reference. */ - NRF_LPCOMP_REF_SUPPLY_4_8 = LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling, /**< Use supply with a 4/8 prescaler as reference. */ - NRF_LPCOMP_REF_SUPPLY_5_8 = LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling, /**< Use supply with a 5/8 prescaler as reference. */ - NRF_LPCOMP_REF_SUPPLY_6_8 = LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling, /**< Use supply with a 6/8 prescaler as reference. */ - NRF_LPCOMP_REF_SUPPLY_7_8 = LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling, /**< Use supply with a 7/8 prescaler as reference. */ -#elif (LPCOMP_REFSEL_RESOLUTION == 16) || defined(__NRFX_DOXYGEN__) - NRF_LPCOMP_REF_SUPPLY_1_8 = LPCOMP_REFSEL_REFSEL_Ref1_8Vdd, /**< Use supply with a 1/8 prescaler as reference. */ - NRF_LPCOMP_REF_SUPPLY_2_8 = LPCOMP_REFSEL_REFSEL_Ref2_8Vdd, /**< Use supply with a 2/8 prescaler as reference. */ - NRF_LPCOMP_REF_SUPPLY_3_8 = LPCOMP_REFSEL_REFSEL_Ref3_8Vdd, /**< Use supply with a 3/8 prescaler as reference. */ - NRF_LPCOMP_REF_SUPPLY_4_8 = LPCOMP_REFSEL_REFSEL_Ref4_8Vdd, /**< Use supply with a 4/8 prescaler as reference. */ - NRF_LPCOMP_REF_SUPPLY_5_8 = LPCOMP_REFSEL_REFSEL_Ref5_8Vdd, /**< Use supply with a 5/8 prescaler as reference. */ - NRF_LPCOMP_REF_SUPPLY_6_8 = LPCOMP_REFSEL_REFSEL_Ref6_8Vdd, /**< Use supply with a 6/8 prescaler as reference. */ - NRF_LPCOMP_REF_SUPPLY_7_8 = LPCOMP_REFSEL_REFSEL_Ref7_8Vdd, /**< Use supply with a 7/8 prescaler as reference. */ - NRF_LPCOMP_REF_SUPPLY_1_16 = LPCOMP_REFSEL_REFSEL_Ref1_16Vdd, /**< Use supply with a 1/16 prescaler as reference. */ - NRF_LPCOMP_REF_SUPPLY_3_16 = LPCOMP_REFSEL_REFSEL_Ref3_16Vdd, /**< Use supply with a 3/16 prescaler as reference. */ - NRF_LPCOMP_REF_SUPPLY_5_16 = LPCOMP_REFSEL_REFSEL_Ref5_16Vdd, /**< Use supply with a 5/16 prescaler as reference. */ - NRF_LPCOMP_REF_SUPPLY_7_16 = LPCOMP_REFSEL_REFSEL_Ref7_16Vdd, /**< Use supply with a 7/16 prescaler as reference. */ - NRF_LPCOMP_REF_SUPPLY_9_16 = LPCOMP_REFSEL_REFSEL_Ref9_16Vdd, /**< Use supply with a 9/16 prescaler as reference. */ - NRF_LPCOMP_REF_SUPPLY_11_16 = LPCOMP_REFSEL_REFSEL_Ref11_16Vdd, /**< Use supply with a 11/16 prescaler as reference. */ - NRF_LPCOMP_REF_SUPPLY_13_16 = LPCOMP_REFSEL_REFSEL_Ref13_16Vdd, /**< Use supply with a 13/16 prescaler as reference. */ - NRF_LPCOMP_REF_SUPPLY_15_16 = LPCOMP_REFSEL_REFSEL_Ref15_16Vdd, /**< Use supply with a 15/16 prescaler as reference. */ -#endif - NRF_LPCOMP_REF_EXT_REF0 = LPCOMP_REFSEL_REFSEL_ARef | - (LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 << 16), /**< External reference 0. */ - NRF_LPCOMP_CONFIG_REF_EXT_REF1 = LPCOMP_REFSEL_REFSEL_ARef | - (LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 << 16), /**< External reference 1. */ -} nrf_lpcomp_ref_t; - -/** - * @enum nrf_lpcomp_input_t - * @brief LPCOMP input selection. - */ -typedef enum -{ - NRF_LPCOMP_INPUT_0 = LPCOMP_PSEL_PSEL_AnalogInput0, /**< Input 0. */ - NRF_LPCOMP_INPUT_1 = LPCOMP_PSEL_PSEL_AnalogInput1, /**< Input 1. */ - NRF_LPCOMP_INPUT_2 = LPCOMP_PSEL_PSEL_AnalogInput2, /**< Input 2. */ - NRF_LPCOMP_INPUT_3 = LPCOMP_PSEL_PSEL_AnalogInput3, /**< Input 3. */ - NRF_LPCOMP_INPUT_4 = LPCOMP_PSEL_PSEL_AnalogInput4, /**< Input 4. */ - NRF_LPCOMP_INPUT_5 = LPCOMP_PSEL_PSEL_AnalogInput5, /**< Input 5. */ - NRF_LPCOMP_INPUT_6 = LPCOMP_PSEL_PSEL_AnalogInput6, /**< Input 6. */ - NRF_LPCOMP_INPUT_7 = LPCOMP_PSEL_PSEL_AnalogInput7 /**< Input 7. */ -} nrf_lpcomp_input_t; - -/** - * @enum nrf_lpcomp_detect_t - * @brief LPCOMP detection type selection. - */ -typedef enum -{ - NRF_LPCOMP_DETECT_CROSS = LPCOMP_ANADETECT_ANADETECT_Cross, /**< Generate ANADETEC on crossing, both upwards and downwards crossing. */ - NRF_LPCOMP_DETECT_UP = LPCOMP_ANADETECT_ANADETECT_Up, /**< Generate ANADETEC on upwards crossing only. */ - NRF_LPCOMP_DETECT_DOWN = LPCOMP_ANADETECT_ANADETECT_Down /**< Generate ANADETEC on downwards crossing only. */ -} nrf_lpcomp_detect_t; - -/** - * @enum nrf_lpcomp_task_t - * @brief LPCOMP tasks. - */ -typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ -{ - NRF_LPCOMP_TASK_START = offsetof(NRF_LPCOMP_Type, TASKS_START), /**< LPCOMP start sampling task. */ - NRF_LPCOMP_TASK_STOP = offsetof(NRF_LPCOMP_Type, TASKS_STOP), /**< LPCOMP stop sampling task. */ - NRF_LPCOMP_TASK_SAMPLE = offsetof(NRF_LPCOMP_Type, TASKS_SAMPLE) /**< Sample comparator value. */ -} nrf_lpcomp_task_t; /*lint -restore*/ - - -/** - * @enum nrf_lpcomp_event_t - * @brief LPCOMP events. - */ -typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ -{ - NRF_LPCOMP_EVENT_READY = offsetof(NRF_LPCOMP_Type, EVENTS_READY), /**< LPCOMP is ready and output is valid. */ - NRF_LPCOMP_EVENT_DOWN = offsetof(NRF_LPCOMP_Type, EVENTS_DOWN), /**< Input voltage crossed the threshold going down. */ - NRF_LPCOMP_EVENT_UP = offsetof(NRF_LPCOMP_Type, EVENTS_UP), /**< Input voltage crossed the threshold going up. */ - NRF_LPCOMP_EVENT_CROSS = offsetof(NRF_LPCOMP_Type, EVENTS_CROSS) /**< Input voltage crossed the threshold in any direction. */ -} nrf_lpcomp_event_t; /*lint -restore*/ - -/** - * @enum nrf_lpcomp_short_mask_t - * @brief LPCOMP shorts masks. - */ -typedef enum -{ - NRF_LPCOMP_SHORT_CROSS_STOP_MASK = LPCOMP_SHORTS_CROSS_STOP_Msk, /*!< Short between CROSS event and STOP task. */ - NRF_LPCOMP_SHORT_UP_STOP_MASK = LPCOMP_SHORTS_UP_STOP_Msk, /*!< Short between UP event and STOP task. */ - NRF_LPCOMP_SHORT_DOWN_STOP_MASK = LPCOMP_SHORTS_DOWN_STOP_Msk, /*!< Short between DOWN event and STOP task. */ - NRF_LPCOMP_SHORT_READY_STOP_MASK = LPCOMP_SHORTS_READY_STOP_Msk, /*!< Short between READY event and STOP task. */ - NRF_LPCOMP_SHORT_READY_SAMPLE_MASK = LPCOMP_SHORTS_READY_SAMPLE_Msk /*!< Short between READY event and SAMPLE task. */ -} nrf_lpcomp_short_mask_t; - -#ifdef LPCOMP_FEATURE_HYST_PRESENT -/** - * @enum nrf_lpcomp_hysteresis_t - * @brief LPCOMP hysteresis. - */ -typedef enum -{ - NRF_LPCOMP_HYST_NOHYST = LPCOMP_HYST_HYST_NoHyst, /**< Comparator hysteresis disabled. */ - NRF_LPCOMP_HYST_50mV = LPCOMP_HYST_HYST_Hyst50mV /**< Comparator hysteresis enabled (typ. 50 mV). */ -}nrf_lpcomp_hysteresis_t; -#endif // LPCOMP_FEATURE_HYST_PRESENT - -/** @brief LPCOMP configuration. */ -typedef struct -{ - nrf_lpcomp_ref_t reference; /**< LPCOMP reference. */ - nrf_lpcomp_detect_t detection; /**< LPCOMP detection type. */ -#ifdef LPCOMP_FEATURE_HYST_PRESENT - nrf_lpcomp_hysteresis_t hyst; /**< LPCOMP hysteresis. */ -#endif // LPCOMP_FEATURE_HYST_PRESENT -} nrf_lpcomp_config_t; - -/** Default LPCOMP configuration. */ -#define NRF_LPCOMP_CONFIG_DEFAULT { NRF_LPCOMP_REF_SUPPLY_FOUR_EIGHT, NRF_LPCOMP_DETECT_DOWN } - -/** - * @brief Function for configuring LPCOMP. - * - * This function powers on LPCOMP and configures it. LPCOMP is in DISABLE state after configuration, - * so it must be enabled before using it. All shorts are inactive, events are cleared, and LPCOMP is stopped. - * - * @param[in] p_config Configuration. - */ -__STATIC_INLINE void nrf_lpcomp_configure(const nrf_lpcomp_config_t * p_config) -{ - NRF_LPCOMP->TASKS_STOP = 1; - NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos; - NRF_LPCOMP->REFSEL = - (p_config->reference << LPCOMP_REFSEL_REFSEL_Pos) & LPCOMP_REFSEL_REFSEL_Msk; - - //If external source is choosen extract analog reference index. - if ((p_config->reference & LPCOMP_REFSEL_REFSEL_ARef)==LPCOMP_REFSEL_REFSEL_ARef) - { - uint32_t extref = p_config->reference >> 16; - NRF_LPCOMP->EXTREFSEL = (extref << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) & LPCOMP_EXTREFSEL_EXTREFSEL_Msk; - } - - NRF_LPCOMP->ANADETECT = - (p_config->detection << LPCOMP_ANADETECT_ANADETECT_Pos) & LPCOMP_ANADETECT_ANADETECT_Msk; -#ifdef LPCOMP_FEATURE_HYST_PRESENT - NRF_LPCOMP->HYST = ((p_config->hyst) << LPCOMP_HYST_HYST_Pos) & LPCOMP_HYST_HYST_Msk; -#endif //LPCOMP_FEATURE_HYST_PRESENT - NRF_LPCOMP->SHORTS = 0; - NRF_LPCOMP->INTENCLR = LPCOMP_INTENCLR_CROSS_Msk | LPCOMP_INTENCLR_UP_Msk | - LPCOMP_INTENCLR_DOWN_Msk | LPCOMP_INTENCLR_READY_Msk; -} - - -/** - * @brief Function for selecting the LPCOMP input. - * - * This function selects the active input of LPCOMP. - * - * @param[in] input Input to be selected. - */ -__STATIC_INLINE void nrf_lpcomp_input_select(nrf_lpcomp_input_t input) -{ - uint32_t lpcomp_enable_state = NRF_LPCOMP->ENABLE; - - NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos; - NRF_LPCOMP->PSEL = - ((uint32_t)input << LPCOMP_PSEL_PSEL_Pos) | (NRF_LPCOMP->PSEL & ~LPCOMP_PSEL_PSEL_Msk); - NRF_LPCOMP->ENABLE = lpcomp_enable_state; -} - - -/** - * @brief Function for enabling the Low Power Comparator. - * - * This function enables LPCOMP. - * - */ -__STATIC_INLINE void nrf_lpcomp_enable(void) -{ - NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Enabled << LPCOMP_ENABLE_ENABLE_Pos; - NRF_LPCOMP->EVENTS_READY = 0; - NRF_LPCOMP->EVENTS_DOWN = 0; - NRF_LPCOMP->EVENTS_UP = 0; - NRF_LPCOMP->EVENTS_CROSS = 0; -} - - -/** - * @brief Function for disabling the Low Power Comparator. - * - * This function disables LPCOMP. - * - */ -__STATIC_INLINE void nrf_lpcomp_disable(void) -{ - NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos; -} - - -/** - * @brief Function for getting the last LPCOMP compare result. - * - * @return The last compare result. If 0 then VIN+ < VIN-, if 1 then the opposite. - */ -__STATIC_INLINE uint32_t nrf_lpcomp_result_get(void) -{ - return (uint32_t)NRF_LPCOMP->RESULT; -} - - -/** - * @brief Function for enabling interrupts from LPCOMP. - * - * @param[in] lpcomp_int_mask Mask of interrupts to be enabled. - * - * @sa nrf_lpcomp_int_disable() - * @sa nrf_lpcomp_int_enable_check() - */ -__STATIC_INLINE void nrf_lpcomp_int_enable(uint32_t lpcomp_int_mask) -{ - NRF_LPCOMP->INTENSET = lpcomp_int_mask; -} - - -/** - * @brief Function for disabling interrupts from LPCOMP. - * - * @param[in] lpcomp_int_mask Mask of interrupts to be disabled. - * - * @sa nrf_lpcomp_int_enable() - * @sa nrf_lpcomp_int_enable_check() - */ -__STATIC_INLINE void nrf_lpcomp_int_disable(uint32_t lpcomp_int_mask) -{ - NRF_LPCOMP->INTENCLR = lpcomp_int_mask; -} - - -/** - * @brief Function for getting the enabled interrupts of LPCOMP. - * - * @param[in] lpcomp_int_mask Mask of interrupts to be checked. - * - * @retval true If any of interrupts of the specified mask are enabled. - * - * @sa nrf_lpcomp_int_enable() - * @sa nrf_lpcomp_int_disable() - */ -__STATIC_INLINE bool nrf_lpcomp_int_enable_check(uint32_t lpcomp_int_mask) -{ - return (NRF_LPCOMP->INTENSET & lpcomp_int_mask); // when read this register will return the value of INTEN. -} - - -/** - * @brief Function for getting the address of a specific LPCOMP task register. - * - * @param[in] lpcomp_task LPCOMP task. - * - * @return The address of the specified LPCOMP task. - */ -__STATIC_INLINE uint32_t * nrf_lpcomp_task_address_get(nrf_lpcomp_task_t lpcomp_task) -{ - return (uint32_t *)((uint8_t *)NRF_LPCOMP + lpcomp_task); -} - - -/** - * @brief Function for getting the address of a specific LPCOMP event register. - * - * @param[in] lpcomp_event LPCOMP event. - * - * @return The address of the specified LPCOMP event. - */ -__STATIC_INLINE uint32_t * nrf_lpcomp_event_address_get(nrf_lpcomp_event_t lpcomp_event) -{ - return (uint32_t *)((uint8_t *)NRF_LPCOMP + lpcomp_event); -} - - -/** - * @brief Function for setting LPCOMP shorts. - * - * @param[in] lpcomp_short_mask LPCOMP shorts by mask. - * - */ -__STATIC_INLINE void nrf_lpcomp_shorts_enable(uint32_t lpcomp_short_mask) -{ - NRF_LPCOMP->SHORTS |= lpcomp_short_mask; -} - - -/** - * @brief Function for clearing LPCOMP shorts by mask. - * - * @param[in] lpcomp_short_mask LPCOMP shorts to be cleared. - * - */ -__STATIC_INLINE void nrf_lpcomp_shorts_disable(uint32_t lpcomp_short_mask) -{ - NRF_LPCOMP->SHORTS &= ~lpcomp_short_mask; -} - - -/** - * @brief Function for setting a specific LPCOMP task. - * - * @param[in] lpcomp_task LPCOMP task to be set. - * - */ -__STATIC_INLINE void nrf_lpcomp_task_trigger(nrf_lpcomp_task_t lpcomp_task) -{ - *( (volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + lpcomp_task) ) = 1; -} - - -/** - * @brief Function for clearing a specific LPCOMP event. - * - * @param[in] lpcomp_event LPCOMP event to be cleared. - * - */ -__STATIC_INLINE void nrf_lpcomp_event_clear(nrf_lpcomp_event_t lpcomp_event) -{ - *( (volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + lpcomp_event) ) = 0; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_LPCOMP + lpcomp_event)); - (void)dummy; -#endif -} - - -/** - * @brief Function for getting the state of a specific LPCOMP event. - * - * @retval true If the specified LPCOMP event is active. - * - */ -__STATIC_INLINE bool nrf_lpcomp_event_check(nrf_lpcomp_event_t lpcomp_event) -{ - return (bool) (*(volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + lpcomp_event)); -} - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* NRF_LPCOMP_H_ */ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_nvmc.c b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_nvmc.c deleted file mode 100644 index 2d35370ad9..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_nvmc.c +++ /dev/null @@ -1,133 +0,0 @@ -/** - * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -/** - *@file - *@brief NMVC driver implementation - */ - -#include -#include "nrf_nvmc.h" - -static inline void wait_for_flash_ready(void) -{ - while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {;} -} - -void nrf_nvmc_page_erase(uint32_t address) -{ - // Enable erase. - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Een; - __ISB(); - __DSB(); - - // Erase the page - NRF_NVMC->ERASEPAGE = address; - wait_for_flash_ready(); - - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren; - __ISB(); - __DSB(); -} - - -void nrf_nvmc_write_byte(uint32_t address, uint8_t value) -{ - uint32_t byte_shift = address & (uint32_t)0x03; - uint32_t address32 = address & ~byte_shift; // Address to the word this byte is in. - uint32_t value32 = (*(uint32_t*)address32 & ~((uint32_t)0xFF << (byte_shift << (uint32_t)3))); - value32 = value32 + ((uint32_t)value << (byte_shift << 3)); - - // Enable write. - NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos); - __ISB(); - __DSB(); - - *(uint32_t*)address32 = value32; - wait_for_flash_ready(); - - NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos); - __ISB(); - __DSB(); -} - -void nrf_nvmc_write_word(uint32_t address, uint32_t value) -{ - // Enable write. - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen; - __ISB(); - __DSB(); - - *(uint32_t*)address = value; - wait_for_flash_ready(); - - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren; - __ISB(); - __DSB(); -} - -void nrf_nvmc_write_bytes(uint32_t address, const uint8_t * src, uint32_t num_bytes) -{ - uint32_t i; - for (i = 0; i < num_bytes; i++) - { - nrf_nvmc_write_byte(address + i,src[i]); - } -} - -void nrf_nvmc_write_words(uint32_t address, const uint32_t * src, uint32_t num_words) -{ - uint32_t i; - - // Enable write. - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen; - __ISB(); - __DSB(); - - for (i = 0; i < num_words; i++) - { - ((uint32_t*)address)[i] = src[i]; - wait_for_flash_ready(); - } - - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren; - __ISB(); - __DSB(); -} - diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_nvmc.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_nvmc.h deleted file mode 100644 index 743f590a22..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_nvmc.h +++ /dev/null @@ -1,119 +0,0 @@ -/** - * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_NVMC_H__ -#define NRF_NVMC_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - - -/** - * @defgroup nrf_nvmc_hal NVMC HAL - * @{ - * @ingroup nrf_nvmc - * @brief Hardware access layer for managing the Non-Volatile Memory Controller (NVMC) peripheral. - * - * This driver allows writing to the non-volatile memory (NVM) regions - * of the chip. In order to write to NVM the controller must be powered - * on and the relevant page must be erased. - * - */ - - -/** - * @brief Erase a page in flash. This is required before writing to any - * address in the page. - * - * @param address Start address of the page. - */ -void nrf_nvmc_page_erase(uint32_t address); - - -/** - * @brief Write a single byte to flash. - * - * The function reads the word containing the byte, and then - * rewrites the entire word. - * - * @param address Address to write to. - * @param value Value to write. - */ -void nrf_nvmc_write_byte(uint32_t address , uint8_t value); - - -/** - * @brief Write a 32-bit word to flash. - * @param address Address to write to. - * @param value Value to write. - */ -void nrf_nvmc_write_word(uint32_t address, uint32_t value); - - -/** - * @brief Write consecutive bytes to flash. - * - * @param address Address to write to. - * @param src Pointer to data to copy from. - * @param num_bytes Number of bytes in src to write. - */ -void nrf_nvmc_write_bytes(uint32_t address, const uint8_t * src, uint32_t num_bytes); - - -/** - * @brief Write consecutive words to flash. - * - * @param address Address to write to. - * @param src Pointer to data to copy from. - * @param num_words Number of words in src to write. - */ -void nrf_nvmc_write_words(uint32_t address, const uint32_t * src, uint32_t num_words); - - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_NVMC_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_pdm.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_pdm.h deleted file mode 100644 index 7de7f50204..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_pdm.h +++ /dev/null @@ -1,387 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef NRF_PDM_H_ -#define NRF_PDM_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_pdm_hal PDM HAL - * @{ - * @ingroup nrf_pdm - * @brief Hardware access layer for managing the Pulse Density Modulation (PDM) peripheral. - */ - -#define NRF_PDM_GAIN_MINIMUM 0x00 -#define NRF_PDM_GAIN_DEFAULT 0x28 -#define NRF_PDM_GAIN_MAXIMUM 0x50 - -typedef uint8_t nrf_pdm_gain_t; - - -/** - * @brief PDM tasks. - */ -typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ -{ - NRF_PDM_TASK_START = offsetof(NRF_PDM_Type, TASKS_START), ///< Starts continuous PDM transfer. - NRF_PDM_TASK_STOP = offsetof(NRF_PDM_Type, TASKS_STOP) ///< Stops PDM transfer. -} nrf_pdm_task_t; - - -/** - * @brief PDM events. - */ -typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ -{ - NRF_PDM_EVENT_STARTED = offsetof(NRF_PDM_Type, EVENTS_STARTED), ///< PDM transfer has started. - NRF_PDM_EVENT_STOPPED = offsetof(NRF_PDM_Type, EVENTS_STOPPED), ///< PDM transfer has finished. - NRF_PDM_EVENT_END = offsetof(NRF_PDM_Type, EVENTS_END) ///< The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM. -} nrf_pdm_event_t; - - -/** - * @brief PDM interrupt masks. - */ -typedef enum -{ - NRF_PDM_INT_STARTED = PDM_INTENSET_STARTED_Msk, ///< Interrupt on EVENTS_STARTED event. - NRF_PDM_INT_STOPPED = PDM_INTENSET_STOPPED_Msk, ///< Interrupt on EVENTS_STOPPED event. - NRF_PDM_INT_END = PDM_INTENSET_END_Msk ///< Interrupt on EVENTS_END event. -} nrf_pdm_int_mask_t; - -/** - * @brief PDM clock frequency. - */ -typedef enum -{ - NRF_PDM_FREQ_1000K = PDM_PDMCLKCTRL_FREQ_1000K, ///< PDM_CLK = 1.000 MHz. - NRF_PDM_FREQ_1032K = PDM_PDMCLKCTRL_FREQ_Default, ///< PDM_CLK = 1.032 MHz. - NRF_PDM_FREQ_1067K = PDM_PDMCLKCTRL_FREQ_1067K ///< PDM_CLK = 1.067 MHz. -} nrf_pdm_freq_t; - - -/** - * @brief PDM operation mode. - */ -typedef enum -{ - NRF_PDM_MODE_STEREO = PDM_MODE_OPERATION_Stereo, ///< Sample and store one pair (Left + Right) of 16-bit samples per RAM word. - NRF_PDM_MODE_MONO = PDM_MODE_OPERATION_Mono ///< Sample and store two successive Left samples (16 bit each) per RAM word. -} nrf_pdm_mode_t; - - -/** - * @brief PDM sampling mode. - */ -typedef enum -{ - NRF_PDM_EDGE_LEFTFALLING = PDM_MODE_EDGE_LeftFalling, ///< Left (or mono) is sampled on falling edge of PDM_CLK. - NRF_PDM_EDGE_LEFTRISING = PDM_MODE_EDGE_LeftRising ///< Left (or mono) is sampled on rising edge of PDM_CLK. -} nrf_pdm_edge_t; - - -/** - * @brief Function for triggering a PDM task. - * - * @param[in] pdm_task PDM task. - */ -__STATIC_INLINE void nrf_pdm_task_trigger(nrf_pdm_task_t pdm_task) -{ - *((volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_task)) = 0x1UL; -} - - -/** - * @brief Function for getting the address of a PDM task register. - * - * @param[in] pdm_task PDM task. - * - * @return Address of the specified PDM task. - */ -__STATIC_INLINE uint32_t nrf_pdm_task_address_get(nrf_pdm_task_t pdm_task) -{ - return (uint32_t)((uint8_t *)NRF_PDM + (uint32_t)pdm_task); -} - - -/** - * @brief Function for getting the state of a PDM event. - * - * @param[in] pdm_event PDM event. - * - * @return State of the specified PDM event. - */ -__STATIC_INLINE bool nrf_pdm_event_check(nrf_pdm_event_t pdm_event) -{ - return (bool)*(volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event); -} - - -/** - * @brief Function for clearing a PDM event. - * - * @param[in] pdm_event PDM event. - */ -__STATIC_INLINE void nrf_pdm_event_clear(nrf_pdm_event_t pdm_event) -{ - *((volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event)); - (void)dummy; -#endif -} - - -/** - * @brief Function for getting the address of a PDM event register. - * - * @param[in] pdm_event PDM event. - * - * @return Address of the specified PDM event. - */ -__STATIC_INLINE volatile uint32_t * nrf_pdm_event_address_get(nrf_pdm_event_t pdm_event) -{ - return (volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event); -} - - -/** - * @brief Function for enabling PDM interrupts. - * - * @param[in] pdm_int_mask Interrupts to enable. - */ -__STATIC_INLINE void nrf_pdm_int_enable(uint32_t pdm_int_mask) -{ - NRF_PDM->INTENSET = pdm_int_mask; -} - - -/** - * @brief Function for retrieving the state of PDM interrupts. - * - * @param[in] pdm_int_mask Interrupts to check. - * - * @retval true If all specified interrupts are enabled. - * @retval false If at least one of the given interrupts is not enabled. - */ -__STATIC_INLINE bool nrf_pdm_int_enable_check(uint32_t pdm_int_mask) -{ - return (bool)(NRF_PDM->INTENSET & pdm_int_mask); -} - - -/** - * @brief Function for disabling interrupts. - * - * @param pdm_int_mask Interrupts to disable. - */ -__STATIC_INLINE void nrf_pdm_int_disable(uint32_t pdm_int_mask) -{ - NRF_PDM->INTENCLR = pdm_int_mask; -} - - -/** - * @brief Function for enabling the PDM peripheral. - * - * The PDM peripheral must be enabled before use. - */ -__STATIC_INLINE void nrf_pdm_enable(void) -{ - NRF_PDM->ENABLE = (PDM_ENABLE_ENABLE_Enabled << PDM_ENABLE_ENABLE_Pos); -} - - -/** - * @brief Function for disabling the PDM peripheral. - */ -__STATIC_INLINE void nrf_pdm_disable(void) -{ - NRF_PDM->ENABLE = (PDM_ENABLE_ENABLE_Disabled << PDM_ENABLE_ENABLE_Pos); -} - - -/** - * @brief Function for checking if the PDM peripheral is enabled. - * - * @retval true If the PDM peripheral is enabled. - * @retval false If the PDM peripheral is not enabled. - */ -__STATIC_INLINE bool nrf_pdm_enable_check(void) -{ - return (NRF_PDM->ENABLE == (PDM_ENABLE_ENABLE_Enabled << PDM_ENABLE_ENABLE_Pos)); -} - - -/** - * @brief Function for setting the PDM operation mode. - * - * @param[in] pdm_mode PDM operation mode. - * @param[in] pdm_edge PDM sampling mode. - */ -__STATIC_INLINE void nrf_pdm_mode_set(nrf_pdm_mode_t pdm_mode, nrf_pdm_edge_t pdm_edge) -{ - NRF_PDM->MODE = ((pdm_mode << PDM_MODE_OPERATION_Pos) & PDM_MODE_OPERATION_Msk) - | ((pdm_edge << PDM_MODE_EDGE_Pos) & PDM_MODE_EDGE_Msk); -} - - -/** - * @brief Function for getting the PDM operation mode. - * - * @param[out] p_pdm_mode PDM operation mode. - * @param[out] p_pdm_edge PDM sampling mode. - */ -__STATIC_INLINE void nrf_pdm_mode_get(nrf_pdm_mode_t * p_pdm_mode, nrf_pdm_edge_t * p_pdm_edge) -{ - uint32_t mode = NRF_PDM->MODE; - *p_pdm_mode = (nrf_pdm_mode_t)((mode & PDM_MODE_OPERATION_Msk ) >> PDM_MODE_OPERATION_Pos); - *p_pdm_edge = (nrf_pdm_edge_t)((mode & PDM_MODE_EDGE_Msk ) >> PDM_MODE_EDGE_Pos); -} - - -/** - * @brief Function for setting the PDM clock frequency. - * - * @param[in] pdm_freq PDM clock frequency. - */ -__STATIC_INLINE void nrf_pdm_clock_set(nrf_pdm_freq_t pdm_freq) -{ - NRF_PDM->PDMCLKCTRL = ((pdm_freq << PDM_PDMCLKCTRL_FREQ_Pos) & PDM_PDMCLKCTRL_FREQ_Msk); -} - - -/** - * @brief Function for getting the PDM clock frequency. - */ -__STATIC_INLINE nrf_pdm_freq_t nrf_pdm_clock_get(void) -{ - return (nrf_pdm_freq_t) ((NRF_PDM->PDMCLKCTRL << PDM_PDMCLKCTRL_FREQ_Pos) & PDM_PDMCLKCTRL_FREQ_Msk); -} - - -/** - * @brief Function for setting up the PDM pins. - * - * @param[in] psel_clk CLK pin number. - * @param[in] psel_din DIN pin number. - */ -__STATIC_INLINE void nrf_pdm_psel_connect(uint32_t psel_clk, uint32_t psel_din) -{ - NRF_PDM->PSEL.CLK = psel_clk; - NRF_PDM->PSEL.DIN = psel_din; -} - -/** - * @brief Function for disconnecting the PDM pins. - */ -__STATIC_INLINE void nrf_pdm_psel_disconnect() -{ - NRF_PDM->PSEL.CLK = ((PDM_PSEL_CLK_CONNECT_Disconnected << PDM_PSEL_CLK_CONNECT_Pos) - & PDM_PSEL_CLK_CONNECT_Msk); - NRF_PDM->PSEL.DIN = ((PDM_PSEL_DIN_CONNECT_Disconnected << PDM_PSEL_DIN_CONNECT_Pos) - & PDM_PSEL_DIN_CONNECT_Msk); -} - - -/** - * @brief Function for setting the PDM gain. - * - * @param[in] gain_l Left channel gain. - * @param[in] gain_r Right channel gain. - */ -__STATIC_INLINE void nrf_pdm_gain_set(nrf_pdm_gain_t gain_l, nrf_pdm_gain_t gain_r) -{ - NRF_PDM->GAINL = gain_l; - NRF_PDM->GAINR = gain_r; -} - - -/** - * @brief Function for getting the PDM gain. - * - * @param[out] p_gain_l Left channel gain. - * @param[out] p_gain_r Right channel gain. - */ -__STATIC_INLINE void nrf_pdm_gain_get(nrf_pdm_gain_t * p_gain_l, nrf_pdm_gain_t * p_gain_r) -{ - *p_gain_l = NRF_PDM->GAINL; - *p_gain_r = NRF_PDM->GAINR; -} - - -/** - * @brief Function for setting the PDM sample buffer. - * - * @param[in] p_buffer Pointer to the RAM address where samples should be written with EasyDMA. - * @param[in] num Number of samples to allocate memory for in EasyDMA mode. - * - * The amount of allocated RAM depends on the operation mode. - * - For stereo mode: N 32-bit words. - * - For mono mode: Ceil(N/2) 32-bit words. - */ -__STATIC_INLINE void nrf_pdm_buffer_set(uint32_t * p_buffer, uint32_t num) -{ - NRF_PDM->SAMPLE.PTR = (uint32_t)p_buffer; - NRF_PDM->SAMPLE.MAXCNT = num; -} - -/** - * @brief Function for getting the current PDM sample buffer address. - * - * @return Pointer to the current sample buffer. - */ -__STATIC_INLINE uint32_t * nrf_pdm_buffer_get() -{ - return (uint32_t *)NRF_PDM->SAMPLE.PTR; -} - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* NRF_PDM_H_ */ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_power.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_power.h deleted file mode 100644 index a0d82b2291..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_power.h +++ /dev/null @@ -1,1057 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_POWER_H__ -#define NRF_POWER_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_power_hal POWER HAL - * @{ - * @ingroup nrf_power - * @brief Hardware access layer for managing the POWER peripheral. - */ - -#if defined(POWER_RAMSTATUS_RAMBLOCK0_Msk) -#define NRF_POWER_HAS_RAMSTATUS 1 -#else -#define NRF_POWER_HAS_RAMSTATUS 0 -#endif - -/** - * @name The implemented functionality - * @{ - * - * Macros that defines functionality that is implemented into POWER peripheral. - */ -#if defined(POWER_INTENSET_SLEEPENTER_Msk) || defined(__NRFX_DOXYGEN__) -/** - * @brief The fact that sleep events are present - * - * In some MCUs there is possibility to process sleep entering and exiting - * events. - */ -#define NRF_POWER_HAS_SLEEPEVT 1 -#else -#define NRF_POWER_HAS_SLEEPEVT 0 -#endif - -#if defined(POWER_RAM_POWER_S0POWER_Msk) || defined(__NRFX_DOXYGEN__) -/** - * @brief The fact that RAMPOWER registers are present - * - * After nRF51, new way to manage RAM power was implemented. - * Special registers, one for every RAM block that makes it possible to - * power ON or OFF RAM segments and turn ON and OFF RAM retention in system OFF - * state. - */ -#define NRF_POWER_HAS_RAMPOWER_REGS 1 -#else -#define NRF_POWER_HAS_RAMPOWER_REGS 0 -#endif - -#if defined(POWER_POFCON_THRESHOLDVDDH_Msk) || defined(__NRFX_DOXYGEN__) -/** - * @brief Auxiliary definition to mark the fact that VDDH is present - * - * This definition can be used in a code to decide if the part with VDDH - * related settings should be implemented. - */ -#define NRF_POWER_HAS_VDDH 1 -#else -#define NRF_POWER_HAS_VDDH 0 -#endif - -#if defined(POWER_USBREGSTATUS_VBUSDETECT_Msk) || defined(__NRFX_DOXYGEN__) -/** - * @brief The fact that power module manages USB regulator - * - * In devices that have USB, power peripheral manages also connection - * detection and USB power regulator, that converts 5 V to 3.3 V - * used by USBD peripheral. - */ -#define NRF_POWER_HAS_USBREG 1 -#else -#define NRF_POWER_HAS_USBREG 0 -#endif -/** @} */ - -/* ------------------------------------------------------------------------------------------------ - * Begin of automatically generated part - * ------------------------------------------------------------------------------------------------ - */ - -/** - * @brief POWER tasks - */ -typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ -{ - NRF_POWER_TASK_CONSTLAT = offsetof(NRF_POWER_Type, TASKS_CONSTLAT), /**< Enable constant latency mode */ - NRF_POWER_TASK_LOWPWR = offsetof(NRF_POWER_Type, TASKS_LOWPWR ), /**< Enable low power mode (variable latency) */ -}nrf_power_task_t; /*lint -restore */ - -/** - * @brief POWER events - */ -typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ -{ - NRF_POWER_EVENT_POFWARN = offsetof(NRF_POWER_Type, EVENTS_POFWARN ), /**< Power failure warning */ -#if NRF_POWER_HAS_SLEEPEVT - NRF_POWER_EVENT_SLEEPENTER = offsetof(NRF_POWER_Type, EVENTS_SLEEPENTER ), /**< CPU entered WFI/WFE sleep */ - NRF_POWER_EVENT_SLEEPEXIT = offsetof(NRF_POWER_Type, EVENTS_SLEEPEXIT ), /**< CPU exited WFI/WFE sleep */ -#endif -#if NRF_POWER_HAS_USBREG - NRF_POWER_EVENT_USBDETECTED = offsetof(NRF_POWER_Type, EVENTS_USBDETECTED), /**< Voltage supply detected on VBUS */ - NRF_POWER_EVENT_USBREMOVED = offsetof(NRF_POWER_Type, EVENTS_USBREMOVED ), /**< Voltage supply removed from VBUS */ - NRF_POWER_EVENT_USBPWRRDY = offsetof(NRF_POWER_Type, EVENTS_USBPWRRDY ), /**< USB 3.3 V supply ready */ -#endif -}nrf_power_event_t; /*lint -restore */ - -/** - * @brief POWER interrupts - */ -typedef enum -{ - NRF_POWER_INT_POFWARN_MASK = POWER_INTENSET_POFWARN_Msk , /**< Write '1' to Enable interrupt for POFWARN event */ -#if NRF_POWER_HAS_SLEEPEVT - NRF_POWER_INT_SLEEPENTER_MASK = POWER_INTENSET_SLEEPENTER_Msk , /**< Write '1' to Enable interrupt for SLEEPENTER event */ - NRF_POWER_INT_SLEEPEXIT_MASK = POWER_INTENSET_SLEEPEXIT_Msk , /**< Write '1' to Enable interrupt for SLEEPEXIT event */ -#endif -#if NRF_POWER_HAS_USBREG - NRF_POWER_INT_USBDETECTED_MASK = POWER_INTENSET_USBDETECTED_Msk, /**< Write '1' to Enable interrupt for USBDETECTED event */ - NRF_POWER_INT_USBREMOVED_MASK = POWER_INTENSET_USBREMOVED_Msk , /**< Write '1' to Enable interrupt for USBREMOVED event */ - NRF_POWER_INT_USBPWRRDY_MASK = POWER_INTENSET_USBPWRRDY_Msk , /**< Write '1' to Enable interrupt for USBPWRRDY event */ -#endif -}nrf_power_int_mask_t; - -/** - * @brief Function for activating a specific POWER task. - * - * @param task Task. - */ -__STATIC_INLINE void nrf_power_task_trigger(nrf_power_task_t task); - -/** - * @brief Function for returning the address of a specific POWER task register. - * - * @param task Task. - * - * @return Task address. - */ -__STATIC_INLINE uint32_t nrf_power_task_address_get(nrf_power_task_t task); - -/** - * @brief Function for clearing a specific event. - * - * @param event Event. - */ -__STATIC_INLINE void nrf_power_event_clear(nrf_power_event_t event); - -/** - * @brief Function for returning the state of a specific event. - * - * @param event Event. - * - * @retval true If the event is set. - * @retval false If the event is not set. - */ -__STATIC_INLINE bool nrf_power_event_check(nrf_power_event_t event); - -/** - * @brief Function for getting and clearing the state of specific event - * - * This function checks the state of the event and clears it. - * - * @param event Event. - * - * @retval true If the event was set. - * @retval false If the event was not set. - */ -__STATIC_INLINE bool nrf_power_event_get_and_clear(nrf_power_event_t event); - -/** - * @brief Function for returning the address of a specific POWER event register. - * - * @param event Event. - * - * @return Address. - */ -__STATIC_INLINE uint32_t nrf_power_event_address_get(nrf_power_event_t event); - -/** - * @brief Function for enabling selected interrupts. - * - * @param int_mask Interrupts mask. - */ -__STATIC_INLINE void nrf_power_int_enable(uint32_t int_mask); - -/** - * @brief Function for retrieving the state of selected interrupts. - * - * @param int_mask Interrupts mask. - * - * @retval true If any of selected interrupts is enabled. - * @retval false If none of selected interrupts is enabled. - */ -__STATIC_INLINE bool nrf_power_int_enable_check(uint32_t int_mask); - -/** - * @brief Function for retrieving the information about enabled interrupts. - * - * @return The flags of enabled interrupts. - */ -__STATIC_INLINE uint32_t nrf_power_int_enable_get(void); - -/** - * @brief Function for disabling selected interrupts. - * - * @param int_mask Interrupts mask. - */ -__STATIC_INLINE void nrf_power_int_disable(uint32_t int_mask); - - -/** @} */ /* End of nrf_power_hal */ - - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -/* ------------------------------------------------------------------------------------------------ - * Internal functions - */ - -/** - * @internal - * @brief Internal function for getting task/event register address - * - * @oaram offset Offset of the register from the instance beginning - * - * @attention offset has to be modulo 4 value. In other case we can get hardware fault. - * @return Pointer to the register - */ -__STATIC_INLINE volatile uint32_t * nrf_power_regptr_get(uint32_t offset) -{ - return (volatile uint32_t *)(((uint8_t *)NRF_POWER) + (uint32_t)offset); -} - -/** - * @internal - * @brief Internal function for getting task/event register address - constant version - * - * @oaram offset Offset of the register from the instance beginning - * - * @attention offset has to be modulo 4 value. In other case we can get hardware fault. - * @return Pointer to the register - */ -__STATIC_INLINE volatile const uint32_t * nrf_power_regptr_get_c( - uint32_t offset) -{ - return (volatile const uint32_t *)(((uint8_t *)NRF_POWER) + - (uint32_t)offset); -} - -/* ------------------------------------------------------------------------------------------------ - * Interface functions definitions - */ - -void nrf_power_task_trigger(nrf_power_task_t task) -{ - *(nrf_power_regptr_get((uint32_t)task)) = 1UL; -} - -uint32_t nrf_power_task_address_get(nrf_power_task_t task) -{ - return (uint32_t)nrf_power_regptr_get_c((uint32_t)task); -} - -void nrf_power_event_clear(nrf_power_event_t event) -{ - *(nrf_power_regptr_get((uint32_t)event)) = 0UL; -} - -bool nrf_power_event_check(nrf_power_event_t event) -{ - return (bool)*nrf_power_regptr_get_c((uint32_t)event); -} - -bool nrf_power_event_get_and_clear(nrf_power_event_t event) -{ - bool ret = nrf_power_event_check(event); - if (ret) - { - nrf_power_event_clear(event); - } - return ret; -} - -uint32_t nrf_power_event_address_get(nrf_power_event_t event) -{ - return (uint32_t)nrf_power_regptr_get_c((uint32_t)event); -} - -void nrf_power_int_enable(uint32_t int_mask) -{ - NRF_POWER->INTENSET = int_mask; -} - -bool nrf_power_int_enable_check(uint32_t int_mask) -{ - return !!(NRF_POWER->INTENSET & int_mask); -} - -uint32_t nrf_power_int_enable_get(void) -{ - return NRF_POWER->INTENSET; -} - -void nrf_power_int_disable(uint32_t int_mask) -{ - NRF_POWER->INTENCLR = int_mask; -} - -#endif /* SUPPRESS_INLINE_IMPLEMENTATION */ - -/* ------------------------------------------------------------------------------------------------ - * End of automatically generated part - * ------------------------------------------------------------------------------------------------ - */ -/** - * @ingroup nrf_power_hal - * @{ - */ - -/** - * @brief Reset reason - */ -typedef enum -{ - NRF_POWER_RESETREAS_RESETPIN_MASK = POWER_RESETREAS_RESETPIN_Msk, /*!< Bit mask of RESETPIN field. *///!< NRF_POWER_RESETREAS_RESETPIN_MASK - NRF_POWER_RESETREAS_DOG_MASK = POWER_RESETREAS_DOG_Msk , /*!< Bit mask of DOG field. */ //!< NRF_POWER_RESETREAS_DOG_MASK - NRF_POWER_RESETREAS_SREQ_MASK = POWER_RESETREAS_SREQ_Msk , /*!< Bit mask of SREQ field. */ //!< NRF_POWER_RESETREAS_SREQ_MASK - NRF_POWER_RESETREAS_LOCKUP_MASK = POWER_RESETREAS_LOCKUP_Msk , /*!< Bit mask of LOCKUP field. */ //!< NRF_POWER_RESETREAS_LOCKUP_MASK - NRF_POWER_RESETREAS_OFF_MASK = POWER_RESETREAS_OFF_Msk , /*!< Bit mask of OFF field. */ //!< NRF_POWER_RESETREAS_OFF_MASK -#if defined(POWER_RESETREAS_LPCOMP_Msk) || defined(__NRFX_DOXYGEN__) - NRF_POWER_RESETREAS_LPCOMP_MASK = POWER_RESETREAS_LPCOMP_Msk , /*!< Bit mask of LPCOMP field. */ //!< NRF_POWER_RESETREAS_LPCOMP_MASK -#endif - NRF_POWER_RESETREAS_DIF_MASK = POWER_RESETREAS_DIF_Msk , /*!< Bit mask of DIF field. */ //!< NRF_POWER_RESETREAS_DIF_MASK -#if defined(POWER_RESETREAS_NFC_Msk) || defined(__NRFX_DOXYGEN__) - NRF_POWER_RESETREAS_NFC_MASK = POWER_RESETREAS_NFC_Msk , /*!< Bit mask of NFC field. */ -#endif -#if defined(POWER_RESETREAS_VBUS_Msk) || defined(__NRFX_DOXYGEN__) - NRF_POWER_RESETREAS_VBUS_MASK = POWER_RESETREAS_VBUS_Msk , /*!< Bit mask of VBUS field. */ -#endif -}nrf_power_resetreas_mask_t; - -#if NRF_POWER_HAS_USBREG -/** - * @brief USBREGSTATUS register bit masks - * - * @sa nrf_power_usbregstatus_get - */ -typedef enum -{ - NRF_POWER_USBREGSTATUS_VBUSDETECT_MASK = POWER_USBREGSTATUS_VBUSDETECT_Msk, /**< USB detected or removed */ - NRF_POWER_USBREGSTATUS_OUTPUTRDY_MASK = POWER_USBREGSTATUS_OUTPUTRDY_Msk /**< USB 3.3 V supply ready */ -}nrf_power_usbregstatus_mask_t; -#endif - -#if NRF_POWER_HAS_RAMSTATUS -/** - * @brief RAM blocks numbers - * - * @sa nrf_power_ramblock_mask_t - * @note - * Ram blocks has to been used in nrf51. - * In new CPU ram is divided into segments and this functionality is depreciated. - * For the newer MCU see the PS for mapping between internal RAM and RAM blocks, - * because this mapping is not 1:1, and functions related to old style blocks - * should not be used. - */ -typedef enum -{ - NRF_POWER_RAMBLOCK0 = POWER_RAMSTATUS_RAMBLOCK0_Pos, - NRF_POWER_RAMBLOCK1 = POWER_RAMSTATUS_RAMBLOCK1_Pos, - NRF_POWER_RAMBLOCK2 = POWER_RAMSTATUS_RAMBLOCK2_Pos, - NRF_POWER_RAMBLOCK3 = POWER_RAMSTATUS_RAMBLOCK3_Pos -}nrf_power_ramblock_t; - -/** - * @brief RAM blocks masks - * - * @sa nrf_power_ramblock_t - */ -typedef enum -{ - NRF_POWER_RAMBLOCK0_MASK = POWER_RAMSTATUS_RAMBLOCK0_Msk, - NRF_POWER_RAMBLOCK1_MASK = POWER_RAMSTATUS_RAMBLOCK1_Msk, - NRF_POWER_RAMBLOCK2_MASK = POWER_RAMSTATUS_RAMBLOCK2_Msk, - NRF_POWER_RAMBLOCK3_MASK = POWER_RAMSTATUS_RAMBLOCK3_Msk -}nrf_power_ramblock_mask_t; -#endif // NRF_POWER_HAS_RAMSTATUS - -/** - * @brief RAM power state position of the bits - * - * @sa nrf_power_onoffram_mask_t - */ -typedef enum -{ - NRF_POWER_ONRAM0, /**< Keep RAM block 0 on or off in system ON Mode */ - NRF_POWER_OFFRAM0, /**< Keep retention on RAM block 0 when RAM block is switched off */ - NRF_POWER_ONRAM1, /**< Keep RAM block 1 on or off in system ON Mode */ - NRF_POWER_OFFRAM1, /**< Keep retention on RAM block 1 when RAM block is switched off */ - NRF_POWER_ONRAM2, /**< Keep RAM block 2 on or off in system ON Mode */ - NRF_POWER_OFFRAM2, /**< Keep retention on RAM block 2 when RAM block is switched off */ - NRF_POWER_ONRAM3, /**< Keep RAM block 3 on or off in system ON Mode */ - NRF_POWER_OFFRAM3, /**< Keep retention on RAM block 3 when RAM block is switched off */ -}nrf_power_onoffram_t; - -/** - * @brief RAM power state bit masks - * - * @sa nrf_power_onoffram_t - */ -typedef enum -{ - NRF_POWER_ONRAM0_MASK = 1U << NRF_POWER_ONRAM0, /**< Keep RAM block 0 on or off in system ON Mode */ - NRF_POWER_OFFRAM0_MASK = 1U << NRF_POWER_OFFRAM0, /**< Keep retention on RAM block 0 when RAM block is switched off */ - NRF_POWER_ONRAM1_MASK = 1U << NRF_POWER_ONRAM1, /**< Keep RAM block 1 on or off in system ON Mode */ - NRF_POWER_OFFRAM1_MASK = 1U << NRF_POWER_OFFRAM1, /**< Keep retention on RAM block 1 when RAM block is switched off */ - NRF_POWER_ONRAM2_MASK = 1U << NRF_POWER_ONRAM2, /**< Keep RAM block 2 on or off in system ON Mode */ - NRF_POWER_OFFRAM2_MASK = 1U << NRF_POWER_OFFRAM2, /**< Keep retention on RAM block 2 when RAM block is switched off */ - NRF_POWER_ONRAM3_MASK = 1U << NRF_POWER_ONRAM3, /**< Keep RAM block 3 on or off in system ON Mode */ - NRF_POWER_OFFRAM3_MASK = 1U << NRF_POWER_OFFRAM3, /**< Keep retention on RAM block 3 when RAM block is switched off */ -}nrf_power_onoffram_mask_t; - -/** - * @brief Power failure comparator thresholds - */ -typedef enum -{ - NRF_POWER_POFTHR_V21 = POWER_POFCON_THRESHOLD_V21, /**< Set threshold to 2.1 V */ - NRF_POWER_POFTHR_V23 = POWER_POFCON_THRESHOLD_V23, /**< Set threshold to 2.3 V */ - NRF_POWER_POFTHR_V25 = POWER_POFCON_THRESHOLD_V25, /**< Set threshold to 2.5 V */ - NRF_POWER_POFTHR_V27 = POWER_POFCON_THRESHOLD_V27, /**< Set threshold to 2.7 V */ -#if defined(POWER_POFCON_THRESHOLD_V17) || defined(__NRFX_DOXYGEN__) - NRF_POWER_POFTHR_V17 = POWER_POFCON_THRESHOLD_V17, /**< Set threshold to 1.7 V */ - NRF_POWER_POFTHR_V18 = POWER_POFCON_THRESHOLD_V18, /**< Set threshold to 1.8 V */ - NRF_POWER_POFTHR_V19 = POWER_POFCON_THRESHOLD_V19, /**< Set threshold to 1.9 V */ - NRF_POWER_POFTHR_V20 = POWER_POFCON_THRESHOLD_V20, /**< Set threshold to 2.0 V */ - NRF_POWER_POFTHR_V22 = POWER_POFCON_THRESHOLD_V22, /**< Set threshold to 2.2 V */ - NRF_POWER_POFTHR_V24 = POWER_POFCON_THRESHOLD_V24, /**< Set threshold to 2.4 V */ - NRF_POWER_POFTHR_V26 = POWER_POFCON_THRESHOLD_V26, /**< Set threshold to 2.6 V */ - NRF_POWER_POFTHR_V28 = POWER_POFCON_THRESHOLD_V28, /**< Set threshold to 2.8 V */ -#endif -}nrf_power_pof_thr_t; - -#if NRF_POWER_HAS_VDDH -/** - * @brief Power failure comparator thresholds for VDDH - */ -typedef enum -{ - NRF_POWER_POFTHRVDDH_V27 = POWER_POFCON_THRESHOLDVDDH_V27, /**< Set threshold to 2.7 V */ - NRF_POWER_POFTHRVDDH_V28 = POWER_POFCON_THRESHOLDVDDH_V28, /**< Set threshold to 2.8 V */ - NRF_POWER_POFTHRVDDH_V29 = POWER_POFCON_THRESHOLDVDDH_V29, /**< Set threshold to 2.9 V */ - NRF_POWER_POFTHRVDDH_V30 = POWER_POFCON_THRESHOLDVDDH_V30, /**< Set threshold to 3.0 V */ - NRF_POWER_POFTHRVDDH_V31 = POWER_POFCON_THRESHOLDVDDH_V31, /**< Set threshold to 3.1 V */ - NRF_POWER_POFTHRVDDH_V32 = POWER_POFCON_THRESHOLDVDDH_V32, /**< Set threshold to 3.2 V */ - NRF_POWER_POFTHRVDDH_V33 = POWER_POFCON_THRESHOLDVDDH_V33, /**< Set threshold to 3.3 V */ - NRF_POWER_POFTHRVDDH_V34 = POWER_POFCON_THRESHOLDVDDH_V34, /**< Set threshold to 3.4 V */ - NRF_POWER_POFTHRVDDH_V35 = POWER_POFCON_THRESHOLDVDDH_V35, /**< Set threshold to 3.5 V */ - NRF_POWER_POFTHRVDDH_V36 = POWER_POFCON_THRESHOLDVDDH_V36, /**< Set threshold to 3.6 V */ - NRF_POWER_POFTHRVDDH_V37 = POWER_POFCON_THRESHOLDVDDH_V37, /**< Set threshold to 3.7 V */ - NRF_POWER_POFTHRVDDH_V38 = POWER_POFCON_THRESHOLDVDDH_V38, /**< Set threshold to 3.8 V */ - NRF_POWER_POFTHRVDDH_V39 = POWER_POFCON_THRESHOLDVDDH_V39, /**< Set threshold to 3.9 V */ - NRF_POWER_POFTHRVDDH_V40 = POWER_POFCON_THRESHOLDVDDH_V40, /**< Set threshold to 4.0 V */ - NRF_POWER_POFTHRVDDH_V41 = POWER_POFCON_THRESHOLDVDDH_V41, /**< Set threshold to 4.1 V */ - NRF_POWER_POFTHRVDDH_V42 = POWER_POFCON_THRESHOLDVDDH_V42, /**< Set threshold to 4.2 V */ -}nrf_power_pof_thrvddh_t; - -/** - * @brief Main regulator status - */ -typedef enum -{ - NRF_POWER_MAINREGSTATUS_NORMAL = POWER_MAINREGSTATUS_MAINREGSTATUS_Normal, /**< Normal voltage mode. Voltage supplied on VDD. */ - NRF_POWER_MAINREGSTATUS_HIGH = POWER_MAINREGSTATUS_MAINREGSTATUS_High /**< High voltage mode. Voltage supplied on VDDH. */ -}nrf_power_mainregstatus_t; - -#endif /* NRF_POWER_HAS_VDDH */ - -#if NRF_POWER_HAS_RAMPOWER_REGS -/** - * @brief Bit positions for RAMPOWER register - * - * All possible bits described, even if they are not used in selected MCU. - */ -typedef enum -{ - /** Keep RAM section S0 ON in System ON mode */ - NRF_POWER_RAMPOWER_S0POWER = POWER_RAM_POWER_S0POWER_Pos, - NRF_POWER_RAMPOWER_S1POWER, /**< Keep RAM section S1 ON in System ON mode */ - NRF_POWER_RAMPOWER_S2POWER, /**< Keep RAM section S2 ON in System ON mode */ - NRF_POWER_RAMPOWER_S3POWER, /**< Keep RAM section S3 ON in System ON mode */ - NRF_POWER_RAMPOWER_S4POWER, /**< Keep RAM section S4 ON in System ON mode */ - NRF_POWER_RAMPOWER_S5POWER, /**< Keep RAM section S5 ON in System ON mode */ - NRF_POWER_RAMPOWER_S6POWER, /**< Keep RAM section S6 ON in System ON mode */ - NRF_POWER_RAMPOWER_S7POWER, /**< Keep RAM section S7 ON in System ON mode */ - NRF_POWER_RAMPOWER_S8POWER, /**< Keep RAM section S8 ON in System ON mode */ - NRF_POWER_RAMPOWER_S9POWER, /**< Keep RAM section S9 ON in System ON mode */ - NRF_POWER_RAMPOWER_S10POWER, /**< Keep RAM section S10 ON in System ON mode */ - NRF_POWER_RAMPOWER_S11POWER, /**< Keep RAM section S11 ON in System ON mode */ - NRF_POWER_RAMPOWER_S12POWER, /**< Keep RAM section S12 ON in System ON mode */ - NRF_POWER_RAMPOWER_S13POWER, /**< Keep RAM section S13 ON in System ON mode */ - NRF_POWER_RAMPOWER_S14POWER, /**< Keep RAM section S14 ON in System ON mode */ - NRF_POWER_RAMPOWER_S15POWER, /**< Keep RAM section S15 ON in System ON mode */ - - /** Keep section retention in OFF mode when section is OFF */ - NRF_POWER_RAMPOWER_S0RETENTION = POWER_RAM_POWER_S0RETENTION_Pos, - NRF_POWER_RAMPOWER_S1RETENTION, /**< Keep section retention in OFF mode when section is OFF */ - NRF_POWER_RAMPOWER_S2RETENTION, /**< Keep section retention in OFF mode when section is OFF */ - NRF_POWER_RAMPOWER_S3RETENTION, /**< Keep section retention in OFF mode when section is OFF */ - NRF_POWER_RAMPOWER_S4RETENTION, /**< Keep section retention in OFF mode when section is OFF */ - NRF_POWER_RAMPOWER_S5RETENTION, /**< Keep section retention in OFF mode when section is OFF */ - NRF_POWER_RAMPOWER_S6RETENTION, /**< Keep section retention in OFF mode when section is OFF */ - NRF_POWER_RAMPOWER_S7RETENTION, /**< Keep section retention in OFF mode when section is OFF */ - NRF_POWER_RAMPOWER_S8RETENTION, /**< Keep section retention in OFF mode when section is OFF */ - NRF_POWER_RAMPOWER_S9RETENTION, /**< Keep section retention in OFF mode when section is OFF */ - NRF_POWER_RAMPOWER_S10RETENTION, /**< Keep section retention in OFF mode when section is OFF */ - NRF_POWER_RAMPOWER_S11RETENTION, /**< Keep section retention in OFF mode when section is OFF */ - NRF_POWER_RAMPOWER_S12RETENTION, /**< Keep section retention in OFF mode when section is OFF */ - NRF_POWER_RAMPOWER_S13RETENTION, /**< Keep section retention in OFF mode when section is OFF */ - NRF_POWER_RAMPOWER_S14RETENTION, /**< Keep section retention in OFF mode when section is OFF */ - NRF_POWER_RAMPOWER_S15RETENTION, /**< Keep section retention in OFF mode when section is OFF */ -}nrf_power_rampower_t; - -#if defined ( __CC_ARM ) -#pragma push -#pragma diag_suppress 66 -#endif -/** - * @brief Bit masks for RAMPOWER register - * - * All possible bits described, even if they are not used in selected MCU. - */ -typedef enum -{ - NRF_POWER_RAMPOWER_S0POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S0POWER , - NRF_POWER_RAMPOWER_S1POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S1POWER , - NRF_POWER_RAMPOWER_S2POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S2POWER , - NRF_POWER_RAMPOWER_S3POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S3POWER , - NRF_POWER_RAMPOWER_S4POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S4POWER , - NRF_POWER_RAMPOWER_S5POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S5POWER , - NRF_POWER_RAMPOWER_S7POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S7POWER , - NRF_POWER_RAMPOWER_S8POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S8POWER , - NRF_POWER_RAMPOWER_S9POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S9POWER , - NRF_POWER_RAMPOWER_S10POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S10POWER, - NRF_POWER_RAMPOWER_S11POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S11POWER, - NRF_POWER_RAMPOWER_S12POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S12POWER, - NRF_POWER_RAMPOWER_S13POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S13POWER, - NRF_POWER_RAMPOWER_S14POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S14POWER, - NRF_POWER_RAMPOWER_S15POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S15POWER, - - NRF_POWER_RAMPOWER_S0RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S0RETENTION , - NRF_POWER_RAMPOWER_S1RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S1RETENTION , - NRF_POWER_RAMPOWER_S2RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S2RETENTION , - NRF_POWER_RAMPOWER_S3RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S3RETENTION , - NRF_POWER_RAMPOWER_S4RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S4RETENTION , - NRF_POWER_RAMPOWER_S5RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S5RETENTION , - NRF_POWER_RAMPOWER_S7RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S7RETENTION , - NRF_POWER_RAMPOWER_S8RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S8RETENTION , - NRF_POWER_RAMPOWER_S9RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S9RETENTION , - NRF_POWER_RAMPOWER_S10RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S10RETENTION, - NRF_POWER_RAMPOWER_S11RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S11RETENTION, - NRF_POWER_RAMPOWER_S12RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S12RETENTION, - NRF_POWER_RAMPOWER_S13RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S13RETENTION, - NRF_POWER_RAMPOWER_S14RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S14RETENTION, - NRF_POWER_RAMPOWER_S15RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S15RETENTION, -}nrf_power_rampower_mask_t; -#if defined ( __CC_ARM ) -#pragma pop -#endif -#endif /* NRF_POWER_HAS_RAMPOWER_REGS */ - - -/** - * @brief Get reset reason mask - * - * Function returns the reset reason. - * Unless cleared, the RESETREAS register is cumulative. - * A field is cleared by writing '1' to it (see @ref nrf_power_resetreas_clear). - * If none of the reset sources are flagged, - * this indicates that the chip was reset from the on-chip reset generator, - * which indicates a power-on-reset or a brown out reset. - * - * @return The mask of reset reasons constructed with @ref nrf_power_resetreas_mask_t. - */ -__STATIC_INLINE uint32_t nrf_power_resetreas_get(void); - -/** - * @brief Clear selected reset reason field - * - * Function clears selected reset reason fields. - * - * @param[in] mask The mask constructed from @ref nrf_power_resetreas_mask_t enumerator values. - * @sa nrf_power_resetreas_get - */ -__STATIC_INLINE void nrf_power_resetreas_clear(uint32_t mask); - -#if NRF_POWER_HAS_RAMSTATUS -/** - * @brief Get RAMSTATUS register - * - * Returns the masks of RAM blocks that are powered ON. - * - * @return Value with bits sets according to masks in @ref nrf_power_ramblock_mask_t. - */ -__STATIC_INLINE uint32_t nrf_power_ramstatus_get(void); -#endif // NRF_POWER_HAS_RAMSTATUS - -/** - * @brief Go to system OFF - * - * This function puts the CPU into system off mode. - * The only way to wake up the CPU is by reset. - * - * @note This function never returns. - */ -__STATIC_INLINE void nrf_power_system_off(void); - -/** - * @brief Set power failure comparator configuration - * - * Sets power failure comparator threshold and enable/disable flag. - * - * @param enabled Set to true if power failure comparator should be enabled. - * @param thr Set the voltage threshold value. - * - * @note - * If VDDH settings is present in the device, this function would - * clear it settings (set to the lowest voltage). - * Use @ref nrf_power_pofcon_vddh_set function to set new value. - */ -__STATIC_INLINE void nrf_power_pofcon_set(bool enabled, nrf_power_pof_thr_t thr); - -/** - * @brief Get power failure comparator configuration - * - * Get power failure comparator threshold and enable bit. - * - * @param[out] p_enabled Function would set this boolean variable to true - * if power failure comparator is enabled. - * The pointer can be NULL if we do not need this information. - * @return Threshold setting for power failure comparator - */ -__STATIC_INLINE nrf_power_pof_thr_t nrf_power_pofcon_get(bool * p_enabled); - -#if NRF_POWER_HAS_VDDH -/** - * @brief Set VDDH power failure comparator threshold - * - * @param thr Threshold to be set - */ -__STATIC_INLINE void nrf_power_pofcon_vddh_set(nrf_power_pof_thrvddh_t thr); - -/** - * @brief Get VDDH power failure comparator threshold - * - * @return VDDH threshold currently configured - */ -__STATIC_INLINE nrf_power_pof_thrvddh_t nrf_power_pofcon_vddh_get(void); -#endif - -/** - * @brief Set general purpose retention register - * - * @param val Value to be set in the register - */ -__STATIC_INLINE void nrf_power_gpregret_set(uint8_t val); - -/** - * @brief Get general purpose retention register - * - * @return The value from the register - */ -__STATIC_INLINE uint8_t nrf_power_gpregret_get(void); - -#if defined(POWER_GPREGRET2_GPREGRET_Msk) || defined(__NRFX_DOXYGEN__) -/** - * @brief Set general purpose retention register 2 - * - * @param val Value to be set in the register - * @note This register is not available in nrf51 MCU family - */ -__STATIC_INLINE void nrf_power_gpregret2_set(uint8_t val); - -/** - * @brief Get general purpose retention register 2 - * - * @return The value from the register - * @note This register is not available in all MCUs. - */ -__STATIC_INLINE uint8_t nrf_power_gpregret2_get(void); -#endif - -/** - * @brief Enable or disable DCDC converter - * - * @param enable Set true to enable or false to disable DCDC converter. - * - * @note - * If the device consist of high voltage power input (VDDH) this setting - * would relate to the converter on low voltage side (1.3 V output). - */ -__STATIC_INLINE void nrf_power_dcdcen_set(bool enable); - -/** - * @brief Get the state of DCDC converter - * - * @retval true Converter is enabled - * @retval false Converter is disabled - * - * @note - * If the device consist of high voltage power input (VDDH) this setting - * would relate to the converter on low voltage side (1.3 V output). - */ -__STATIC_INLINE bool nrf_power_dcdcen_get(void); - -#if NRF_POWER_HAS_RAMPOWER_REGS -/** - * @brief Turn ON sections in selected RAM block. - * - * This function turns ON sections in block and also block retention. - * - * @sa nrf_power_rampower_mask_t - * @sa nrf_power_rampower_mask_off - * - * @param block RAM block index. - * @param section_mask Mask of the sections created by merging - * @ref nrf_power_rampower_mask_t flags. - */ -__STATIC_INLINE void nrf_power_rampower_mask_on(uint8_t block, uint32_t section_mask); - -/** - * @brief Turn ON sections in selected RAM block. - * - * This function turns OFF sections in block and also block retention. - * - * @sa nrf_power_rampower_mask_t - * @sa nrf_power_rampower_mask_off - * - * @param block RAM block index. - * @param section_mask Mask of the sections created by merging - * @ref nrf_power_rampower_mask_t flags. - */ -__STATIC_INLINE void nrf_power_rampower_mask_off(uint8_t block, uint32_t section_mask); - -/** - * @brief Get the mask of ON and retention sections in selected RAM block. - * - * @param block RAM block index. - * @return Mask of sections state composed from @ref nrf_power_rampower_mask_t flags. - */ -__STATIC_INLINE uint32_t nrf_power_rampower_mask_get(uint8_t block); -#endif /* NRF_POWER_HAS_RAMPOWER_REGS */ - -#if NRF_POWER_HAS_VDDH -/** - * @brief Enable of disable DCDC converter on VDDH - * - * @param enable Set true to enable or false to disable DCDC converter. - */ -__STATIC_INLINE void nrf_power_dcdcen_vddh_set(bool enable); - -/** - * @brief Get the state of DCDC converter on VDDH - * - * @retval true Converter is enabled - * @retval false Converter is disabled - */ -__STATIC_INLINE bool nrf_power_dcdcen_vddh_get(void); - -/** - * @brief Get main supply status - * - * @return Current main supply status - */ -__STATIC_INLINE nrf_power_mainregstatus_t nrf_power_mainregstatus_get(void); -#endif /* NRF_POWER_HAS_VDDH */ - -#if NRF_POWER_HAS_USBREG -/** - * - * @return Get the whole USBREGSTATUS register - * - * @return The USBREGSTATUS register value. - * Use @ref nrf_power_usbregstatus_mask_t values for bit masking. - * - * @sa nrf_power_usbregstatus_vbusdet_get - * @sa nrf_power_usbregstatus_outrdy_get - */ -__STATIC_INLINE uint32_t nrf_power_usbregstatus_get(void); - -/** - * @brief VBUS input detection status - * - * USBDETECTED and USBREMOVED events are derived from this information - * - * @retval false VBUS voltage below valid threshold - * @retval true VBUS voltage above valid threshold - * - * @sa nrf_power_usbregstatus_get - */ -__STATIC_INLINE bool nrf_power_usbregstatus_vbusdet_get(void); - -/** - * @brief USB supply output settling time elapsed - * - * @retval false USBREG output settling time not elapsed - * @retval true USBREG output settling time elapsed - * (same information as USBPWRRDY event) - * - * @sa nrf_power_usbregstatus_get - */ -__STATIC_INLINE bool nrf_power_usbregstatus_outrdy_get(void); -#endif /* NRF_POWER_HAS_USBREG */ - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -__STATIC_INLINE uint32_t nrf_power_resetreas_get(void) -{ - return NRF_POWER->RESETREAS; -} - -__STATIC_INLINE void nrf_power_resetreas_clear(uint32_t mask) -{ - NRF_POWER->RESETREAS = mask; -} - -#if NRF_POWER_HAS_RAMSTATUS -__STATIC_INLINE uint32_t nrf_power_ramstatus_get(void) -{ - return NRF_POWER->RAMSTATUS; -} -#endif // NRF_POWER_HAS_RAMSTATUS - -__STATIC_INLINE void nrf_power_system_off(void) -{ - NRF_POWER->SYSTEMOFF = POWER_SYSTEMOFF_SYSTEMOFF_Enter; - __DSB(); - - /* Solution for simulated System OFF in debug mode */ - while (true) - { - __WFE(); - } -} - -__STATIC_INLINE void nrf_power_pofcon_set(bool enabled, nrf_power_pof_thr_t thr) -{ - NRFX_ASSERT(thr == (thr & (POWER_POFCON_THRESHOLD_Msk >> POWER_POFCON_THRESHOLD_Pos))); -#if NRF_POWER_HAS_VDDH - uint32_t pofcon = NRF_POWER->POFCON; - pofcon &= ~(POWER_POFCON_THRESHOLD_Msk | POWER_POFCON_POF_Msk); - pofcon |= -#else /* NRF_POWER_HAS_VDDH */ - NRF_POWER->POFCON = -#endif - (((uint32_t)thr) << POWER_POFCON_THRESHOLD_Pos) | - (enabled ? - (POWER_POFCON_POF_Enabled << POWER_POFCON_POF_Pos) - : - (POWER_POFCON_POF_Disabled << POWER_POFCON_POF_Pos)); -#if NRF_POWER_HAS_VDDH - NRF_POWER->POFCON = pofcon; -#endif -} - -__STATIC_INLINE nrf_power_pof_thr_t nrf_power_pofcon_get(bool * p_enabled) -{ - uint32_t pofcon = NRF_POWER->POFCON; - if (NULL != p_enabled) - { - (*p_enabled) = ((pofcon & POWER_POFCON_POF_Msk) >> POWER_POFCON_POF_Pos) - == POWER_POFCON_POF_Enabled; - } - return (nrf_power_pof_thr_t)((pofcon & POWER_POFCON_THRESHOLD_Msk) >> - POWER_POFCON_THRESHOLD_Pos); -} - -#if NRF_POWER_HAS_VDDH -__STATIC_INLINE void nrf_power_pofcon_vddh_set(nrf_power_pof_thrvddh_t thr) -{ - NRFX_ASSERT(thr == (thr & (POWER_POFCON_THRESHOLDVDDH_Msk >> POWER_POFCON_THRESHOLDVDDH_Pos))); - uint32_t pofcon = NRF_POWER->POFCON; - pofcon &= ~POWER_POFCON_THRESHOLDVDDH_Msk; - pofcon |= (((uint32_t)thr) << POWER_POFCON_THRESHOLDVDDH_Pos); - NRF_POWER->POFCON = pofcon; -} - -__STATIC_INLINE nrf_power_pof_thrvddh_t nrf_power_pofcon_vddh_get(void) -{ - return (nrf_power_pof_thrvddh_t)((NRF_POWER->POFCON & - POWER_POFCON_THRESHOLDVDDH_Msk) >> POWER_POFCON_THRESHOLDVDDH_Pos); -} -#endif /* NRF_POWER_HAS_VDDH */ - -__STATIC_INLINE void nrf_power_gpregret_set(uint8_t val) -{ - NRF_POWER->GPREGRET = val; -} - -__STATIC_INLINE uint8_t nrf_power_gpregret_get(void) -{ - return NRF_POWER->GPREGRET; -} - -#if defined(POWER_GPREGRET2_GPREGRET_Msk) || defined(__NRFX_DOXYGEN__) -void nrf_power_gpregret2_set(uint8_t val) -{ - NRF_POWER->GPREGRET2 = val; -} - -__STATIC_INLINE uint8_t nrf_power_gpregret2_get(void) -{ - return NRF_POWER->GPREGRET2; -} -#endif - -__STATIC_INLINE void nrf_power_dcdcen_set(bool enable) -{ -#if NRF_POWER_HAS_VDDH - NRF_POWER->DCDCEN = (enable ? - POWER_DCDCEN_DCDCEN_Enabled : POWER_DCDCEN_DCDCEN_Disabled) << - POWER_DCDCEN_DCDCEN_Pos; -#else - NRF_POWER->DCDCEN = (enable ? - POWER_DCDCEN_DCDCEN_Enabled : POWER_DCDCEN_DCDCEN_Disabled) << - POWER_DCDCEN_DCDCEN_Pos; -#endif -} - -__STATIC_INLINE bool nrf_power_dcdcen_get(void) -{ -#if NRF_POWER_HAS_VDDH - return (NRF_POWER->DCDCEN & POWER_DCDCEN_DCDCEN_Msk) - == - (POWER_DCDCEN_DCDCEN_Enabled << POWER_DCDCEN_DCDCEN_Pos); -#else - return (NRF_POWER->DCDCEN & POWER_DCDCEN_DCDCEN_Msk) - == - (POWER_DCDCEN_DCDCEN_Enabled << POWER_DCDCEN_DCDCEN_Pos); -#endif -} - -#if NRF_POWER_HAS_RAMPOWER_REGS -__STATIC_INLINE void nrf_power_rampower_mask_on(uint8_t block, uint32_t section_mask) -{ - NRFX_ASSERT(block < ARRAY_SIZE(NRF_POWER->RAM)); - NRF_POWER->RAM[block].POWERSET = section_mask; -} - -__STATIC_INLINE void nrf_power_rampower_mask_off(uint8_t block, uint32_t section_mask) -{ - NRFX_ASSERT(block < ARRAY_SIZE(NRF_POWER->RAM)); - NRF_POWER->RAM[block].POWERCLR = section_mask; -} - -__STATIC_INLINE uint32_t nrf_power_rampower_mask_get(uint8_t block) -{ - NRFX_ASSERT(block < ARRAY_SIZE(NRF_POWER->RAM)); - return NRF_POWER->RAM[block].POWER; -} -#endif /* NRF_POWER_HAS_RAMPOWER_REGS */ - -#if NRF_POWER_HAS_VDDH -__STATIC_INLINE void nrf_power_dcdcen_vddh_set(bool enable) -{ - NRF_POWER->DCDCEN0 = (enable ? - POWER_DCDCEN0_DCDCEN_Enabled : POWER_DCDCEN0_DCDCEN_Disabled) << - POWER_DCDCEN0_DCDCEN_Pos; -} - -bool nrf_power_dcdcen_vddh_get(void) -{ - return (NRF_POWER->DCDCEN0 & POWER_DCDCEN0_DCDCEN_Msk) - == - (POWER_DCDCEN0_DCDCEN_Enabled << POWER_DCDCEN0_DCDCEN_Pos); -} - -nrf_power_mainregstatus_t nrf_power_mainregstatus_get(void) -{ - return (nrf_power_mainregstatus_t)(((NRF_POWER->MAINREGSTATUS) & - POWER_MAINREGSTATUS_MAINREGSTATUS_Msk) >> - POWER_MAINREGSTATUS_MAINREGSTATUS_Pos); -} -#endif /* NRF_POWER_HAS_VDDH */ - -#if NRF_POWER_HAS_USBREG -__STATIC_INLINE uint32_t nrf_power_usbregstatus_get(void) -{ - return NRF_POWER->USBREGSTATUS; -} - -__STATIC_INLINE bool nrf_power_usbregstatus_vbusdet_get(void) -{ - return (nrf_power_usbregstatus_get() & - NRF_POWER_USBREGSTATUS_VBUSDETECT_MASK) != 0; -} - -__STATIC_INLINE bool nrf_power_usbregstatus_outrdy_get(void) -{ - return (nrf_power_usbregstatus_get() & - NRF_POWER_USBREGSTATUS_OUTPUTRDY_MASK) != 0; -} -#endif /* NRF_POWER_HAS_USBREG */ - -#endif /* SUPPRESS_INLINE_IMPLEMENTATION */ - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* NRF_POWER_H__ */ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_ppi.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_ppi.h deleted file mode 100644 index 2be876a589..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_ppi.h +++ /dev/null @@ -1,481 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_PPI_H__ -#define NRF_PPI_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_ppi_hal PPI HAL - * @{ - * @ingroup nrf_ppi - * @brief Hardware access layer for managing the Programmable Peripheral Interconnect (PPI) - * channels. - */ - -#define NRF_PPI_TASK_SET (1UL) - -/** - * @enum nrf_ppi_channel_t - * @brief PPI channels. - */ -typedef enum -{ - NRF_PPI_CHANNEL0 = PPI_CHEN_CH0_Pos, /**< Channel 0. */ - NRF_PPI_CHANNEL1 = PPI_CHEN_CH1_Pos, /**< Channel 1. */ - NRF_PPI_CHANNEL2 = PPI_CHEN_CH2_Pos, /**< Channel 2. */ - NRF_PPI_CHANNEL3 = PPI_CHEN_CH3_Pos, /**< Channel 3. */ - NRF_PPI_CHANNEL4 = PPI_CHEN_CH4_Pos, /**< Channel 4. */ - NRF_PPI_CHANNEL5 = PPI_CHEN_CH5_Pos, /**< Channel 5. */ - NRF_PPI_CHANNEL6 = PPI_CHEN_CH6_Pos, /**< Channel 6. */ - NRF_PPI_CHANNEL7 = PPI_CHEN_CH7_Pos, /**< Channel 7. */ - NRF_PPI_CHANNEL8 = PPI_CHEN_CH8_Pos, /**< Channel 8. */ - NRF_PPI_CHANNEL9 = PPI_CHEN_CH9_Pos, /**< Channel 9. */ - NRF_PPI_CHANNEL10 = PPI_CHEN_CH10_Pos, /**< Channel 10. */ - NRF_PPI_CHANNEL11 = PPI_CHEN_CH11_Pos, /**< Channel 11. */ - NRF_PPI_CHANNEL12 = PPI_CHEN_CH12_Pos, /**< Channel 12. */ - NRF_PPI_CHANNEL13 = PPI_CHEN_CH13_Pos, /**< Channel 13. */ - NRF_PPI_CHANNEL14 = PPI_CHEN_CH14_Pos, /**< Channel 14. */ - NRF_PPI_CHANNEL15 = PPI_CHEN_CH15_Pos, /**< Channel 15. */ -#if (PPI_CH_NUM > 16) || defined(__NRFX_DOXYGEN__) - NRF_PPI_CHANNEL16 = PPI_CHEN_CH16_Pos, /**< Channel 16. */ - NRF_PPI_CHANNEL17 = PPI_CHEN_CH17_Pos, /**< Channel 17. */ - NRF_PPI_CHANNEL18 = PPI_CHEN_CH18_Pos, /**< Channel 18. */ - NRF_PPI_CHANNEL19 = PPI_CHEN_CH19_Pos, /**< Channel 19. */ -#endif - NRF_PPI_CHANNEL20 = PPI_CHEN_CH20_Pos, /**< Channel 20. */ - NRF_PPI_CHANNEL21 = PPI_CHEN_CH21_Pos, /**< Channel 21. */ - NRF_PPI_CHANNEL22 = PPI_CHEN_CH22_Pos, /**< Channel 22. */ - NRF_PPI_CHANNEL23 = PPI_CHEN_CH23_Pos, /**< Channel 23. */ - NRF_PPI_CHANNEL24 = PPI_CHEN_CH24_Pos, /**< Channel 24. */ - NRF_PPI_CHANNEL25 = PPI_CHEN_CH25_Pos, /**< Channel 25. */ - NRF_PPI_CHANNEL26 = PPI_CHEN_CH26_Pos, /**< Channel 26. */ - NRF_PPI_CHANNEL27 = PPI_CHEN_CH27_Pos, /**< Channel 27. */ - NRF_PPI_CHANNEL28 = PPI_CHEN_CH28_Pos, /**< Channel 28. */ - NRF_PPI_CHANNEL29 = PPI_CHEN_CH29_Pos, /**< Channel 29. */ - NRF_PPI_CHANNEL30 = PPI_CHEN_CH30_Pos, /**< Channel 30. */ - NRF_PPI_CHANNEL31 = PPI_CHEN_CH31_Pos /**< Channel 31. */ -} nrf_ppi_channel_t; - -/** - * @enum nrf_ppi_channel_group_t - * @brief PPI channel groups. - */ -typedef enum -{ - NRF_PPI_CHANNEL_GROUP0 = 0, /**< Channel group 0. */ - NRF_PPI_CHANNEL_GROUP1 = 1, /**< Channel group 1. */ - NRF_PPI_CHANNEL_GROUP2 = 2, /**< Channel group 2. */ - NRF_PPI_CHANNEL_GROUP3 = 3, /**< Channel group 3. */ -#if (PPI_GROUP_NUM > 4) || defined(__NRFX_DOXYGEN__) - NRF_PPI_CHANNEL_GROUP4 = 4, /**< Channel group 4. */ - NRF_PPI_CHANNEL_GROUP5 = 5 /**< Channel group 5. */ -#endif -} nrf_ppi_channel_group_t; - -/** - * @enum nrf_ppi_channel_include_t - * @brief Definition of which PPI channels belong to a group. - */ -typedef enum -{ - NRF_PPI_CHANNEL_EXCLUDE = PPI_CHG_CH0_Excluded, /**< Channel excluded from a group. */ - NRF_PPI_CHANNEL_INCLUDE = PPI_CHG_CH0_Included /**< Channel included in a group. */ -} nrf_ppi_channel_include_t; - -/** - * @enum nrf_ppi_channel_enable_t - * @brief Definition if a PPI channel is enabled. - */ -typedef enum -{ - NRF_PPI_CHANNEL_DISABLED = PPI_CHEN_CH0_Disabled, /**< Channel disabled. */ - NRF_PPI_CHANNEL_ENABLED = PPI_CHEN_CH0_Enabled /**< Channel enabled. */ -} nrf_ppi_channel_enable_t; - -/** - * @enum nrf_ppi_task_t - * @brief PPI tasks. - */ -typedef enum -{ - /*lint -save -e30 -esym(628,__INTADDR__)*/ - NRF_PPI_TASK_CHG0_EN = offsetof(NRF_PPI_Type, TASKS_CHG[0].EN), /**< Task for enabling channel group 0 */ - NRF_PPI_TASK_CHG0_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[0].DIS), /**< Task for disabling channel group 0 */ - NRF_PPI_TASK_CHG1_EN = offsetof(NRF_PPI_Type, TASKS_CHG[1].EN), /**< Task for enabling channel group 1 */ - NRF_PPI_TASK_CHG1_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[1].DIS), /**< Task for disabling channel group 1 */ - NRF_PPI_TASK_CHG2_EN = offsetof(NRF_PPI_Type, TASKS_CHG[2].EN), /**< Task for enabling channel group 2 */ - NRF_PPI_TASK_CHG2_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[2].DIS), /**< Task for disabling channel group 2 */ - NRF_PPI_TASK_CHG3_EN = offsetof(NRF_PPI_Type, TASKS_CHG[3].EN), /**< Task for enabling channel group 3 */ - NRF_PPI_TASK_CHG3_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[3].DIS), /**< Task for disabling channel group 3 */ -#if (PPI_GROUP_NUM > 4) || defined(__NRFX_DOXYGEN__) - NRF_PPI_TASK_CHG4_EN = offsetof(NRF_PPI_Type, TASKS_CHG[4].EN), /**< Task for enabling channel group 4 */ - NRF_PPI_TASK_CHG4_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[4].DIS), /**< Task for disabling channel group 4 */ - NRF_PPI_TASK_CHG5_EN = offsetof(NRF_PPI_Type, TASKS_CHG[5].EN), /**< Task for enabling channel group 5 */ - NRF_PPI_TASK_CHG5_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[5].DIS) /**< Task for disabling channel group 5 */ -#endif - /*lint -restore*/ -} nrf_ppi_task_t; - -/** - * @brief Function for enabling a given PPI channel. - * - * @details This function enables only one channel. - * - * @param[in] channel Channel to enable. - * - * */ -__STATIC_INLINE void nrf_ppi_channel_enable(nrf_ppi_channel_t channel); - -/** - * @brief Function for disabling a given PPI channel. - * - * @details This function disables only one channel. - * - * @param[in] channel Channel to disable. - */ -__STATIC_INLINE void nrf_ppi_channel_disable(nrf_ppi_channel_t channel); - -/** - * @brief Function for checking if a given PPI channel is enabled. - * - * @details This function checks only one channel. - * - * @param[in] channel Channel to check. - * - * @retval NRF_PPI_CHANNEL_ENABLED If the channel is enabled. - * @retval NRF_PPI_CHANNEL_DISABLED If the channel is not enabled. - * - */ -__STATIC_INLINE nrf_ppi_channel_enable_t nrf_ppi_channel_enable_get(nrf_ppi_channel_t channel); - -/** - * @brief Function for disabling all PPI channels. - */ -__STATIC_INLINE void nrf_ppi_channel_disable_all(void); - -/** - * @brief Function for disabling multiple PPI channels. - * - * @param[in] mask Channel mask. - */ -__STATIC_INLINE void nrf_ppi_channels_disable(uint32_t mask); - -/** - * @brief Function for setting up event and task endpoints for a given PPI channel. - * - * @param[in] eep Event register address. - * - * @param[in] tep Task register address. - * - * @param[in] channel Channel to which the given endpoints are assigned. - */ -__STATIC_INLINE void nrf_ppi_channel_endpoint_setup(nrf_ppi_channel_t channel, - uint32_t eep, - uint32_t tep); - -#if defined(PPI_FEATURE_FORKS_PRESENT) || defined(__NRFX_DOXYGEN__) -/** - * @brief Function for setting up task endpoint for a given PPI fork. - * - * @param[in] fork_tep Task register address. - * - * @param[in] channel Channel to which the given fork endpoint is assigned. - */ -__STATIC_INLINE void nrf_ppi_fork_endpoint_setup(nrf_ppi_channel_t channel, - uint32_t fork_tep); - -/** - * @brief Function for setting up event and task endpoints for a given PPI channel and fork. - * - * @param[in] eep Event register address. - * - * @param[in] tep Task register address. - * - * @param[in] fork_tep Fork task register address (register value). - * - * @param[in] channel Channel to which the given endpoints are assigned. - */ -__STATIC_INLINE void nrf_ppi_channel_and_fork_endpoint_setup(nrf_ppi_channel_t channel, - uint32_t eep, - uint32_t tep, - uint32_t fork_tep); -#endif - -/** - * @brief Function for including a PPI channel in a channel group. - * - * @details This function adds only one channel to the group. - * - * @param[in] channel Channel to be included in the group. - * - * @param[in] channel_group Channel group. - * - */ -__STATIC_INLINE void nrf_ppi_channel_include_in_group(nrf_ppi_channel_t channel, - nrf_ppi_channel_group_t channel_group); - -/** - * @brief Function for including multiple PPI channels in a channel group. - * - * @details This function adds all specified channels to the group. - * - * @param[in] channel_mask Channels to be included in the group. - * - * @param[in] channel_group Channel group. - * - */ -__STATIC_INLINE void nrf_ppi_channels_include_in_group(uint32_t channel_mask, - nrf_ppi_channel_group_t channel_group); - -/** - * @brief Function for removing a PPI channel from a channel group. - * - * @details This function removes only one channel from the group. - * - * @param[in] channel Channel to be removed from the group. - * - * @param[in] channel_group Channel group. - */ -__STATIC_INLINE void nrf_ppi_channel_remove_from_group(nrf_ppi_channel_t channel, - nrf_ppi_channel_group_t channel_group); - -/** - * @brief Function for removing multiple PPI channels from a channel group. - * - * @details This function removes all specified channels from the group. - * - * @param[in] channel_mask Channels to be removed from the group. - * - * @param[in] channel_group Channel group. - */ -__STATIC_INLINE void nrf_ppi_channels_remove_from_group(uint32_t channel_mask, - nrf_ppi_channel_group_t channel_group); - -/** - * @brief Function for removing all PPI channels from a channel group. - * - * @param[in] group Channel group. - * - */ -__STATIC_INLINE void nrf_ppi_channel_group_clear(nrf_ppi_channel_group_t group); - -/** - * @brief Function for enabling a channel group. - * - * @param[in] group Channel group. - * - */ -__STATIC_INLINE void nrf_ppi_group_enable(nrf_ppi_channel_group_t group); - -/** - * @brief Function for disabling a channel group. - * - * @param[in] group Channel group. - * - */ -__STATIC_INLINE void nrf_ppi_group_disable(nrf_ppi_channel_group_t group); - -/** - * @brief Function for setting a PPI task. - * - * @param[in] ppi_task PPI task to set. - */ -__STATIC_INLINE void nrf_ppi_task_trigger(nrf_ppi_task_t ppi_task); - -/** - * @brief Function for returning the address of a specific PPI task register. - * - * @param[in] ppi_task PPI task. - */ -__STATIC_INLINE uint32_t * nrf_ppi_task_address_get(nrf_ppi_task_t ppi_task); - -/** - * @brief Function for returning the PPI enable task address of a specific group. - * - * @param[in] group PPI group. - */ -__STATIC_INLINE uint32_t * nrf_ppi_task_group_enable_address_get(nrf_ppi_channel_group_t group); - -/** - * @brief Function for returning the PPI disable task address of a specific group. - * - * @param[in] group PPI group. - */ -__STATIC_INLINE uint32_t * nrf_ppi_task_group_disable_address_get(nrf_ppi_channel_group_t group); - - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -__STATIC_INLINE void nrf_ppi_channel_enable(nrf_ppi_channel_t channel) -{ - NRF_PPI->CHENSET = PPI_CHENSET_CH0_Set << ((uint32_t) channel); -} - -__STATIC_INLINE void nrf_ppi_channel_disable(nrf_ppi_channel_t channel) -{ - NRF_PPI->CHENCLR = PPI_CHENCLR_CH0_Clear << ((uint32_t) channel); -} - -__STATIC_INLINE nrf_ppi_channel_enable_t nrf_ppi_channel_enable_get(nrf_ppi_channel_t channel) -{ - if (NRF_PPI->CHEN & (PPI_CHEN_CH0_Msk << ((uint32_t) channel))) - { - return NRF_PPI_CHANNEL_ENABLED; - } - else - { - return NRF_PPI_CHANNEL_DISABLED; - } -} - -__STATIC_INLINE void nrf_ppi_channel_disable_all(void) -{ - NRF_PPI->CHENCLR = ((uint32_t)0xFFFFFFFFuL); -} - -__STATIC_INLINE void nrf_ppi_channels_disable(uint32_t mask) -{ - NRF_PPI->CHENCLR = mask; -} - -__STATIC_INLINE void nrf_ppi_channel_endpoint_setup(nrf_ppi_channel_t channel, - uint32_t eep, - uint32_t tep) -{ - NRF_PPI->CH[(uint32_t) channel].EEP = eep; - NRF_PPI->CH[(uint32_t) channel].TEP = tep; -} - -#if defined(PPI_FEATURE_FORKS_PRESENT) - -__STATIC_INLINE void nrf_ppi_fork_endpoint_setup(nrf_ppi_channel_t channel, - uint32_t fork_tep) -{ - NRF_PPI->FORK[(uint32_t) channel].TEP = fork_tep; -} - -__STATIC_INLINE void nrf_ppi_channel_and_fork_endpoint_setup(nrf_ppi_channel_t channel, - uint32_t eep, - uint32_t tep, - uint32_t fork_tep) -{ - nrf_ppi_channel_endpoint_setup(channel, eep, tep); - nrf_ppi_fork_endpoint_setup(channel, fork_tep); -} -#endif - -__STATIC_INLINE void nrf_ppi_channel_include_in_group(nrf_ppi_channel_t channel, - nrf_ppi_channel_group_t channel_group) -{ - NRF_PPI->CHG[(uint32_t) channel_group] = - NRF_PPI->CHG[(uint32_t) channel_group] | (PPI_CHG_CH0_Included << ((uint32_t) channel)); -} - -__STATIC_INLINE void nrf_ppi_channels_include_in_group(uint32_t channel_mask, - nrf_ppi_channel_group_t channel_group) -{ - NRF_PPI->CHG[(uint32_t) channel_group] = - NRF_PPI->CHG[(uint32_t) channel_group] | (channel_mask); -} - -__STATIC_INLINE void nrf_ppi_channel_remove_from_group(nrf_ppi_channel_t channel, - nrf_ppi_channel_group_t channel_group) -{ - NRF_PPI->CHG[(uint32_t) channel_group] = - NRF_PPI->CHG[(uint32_t) channel_group] & ~(PPI_CHG_CH0_Included << ((uint32_t) channel)); -} - -__STATIC_INLINE void nrf_ppi_channels_remove_from_group(uint32_t channel_mask, - nrf_ppi_channel_group_t channel_group) -{ - NRF_PPI->CHG[(uint32_t) channel_group] = - NRF_PPI->CHG[(uint32_t) channel_group] & ~(channel_mask); -} - -__STATIC_INLINE void nrf_ppi_channel_group_clear(nrf_ppi_channel_group_t group) -{ - NRF_PPI->CHG[(uint32_t) group] = 0; -} - -__STATIC_INLINE void nrf_ppi_group_enable(nrf_ppi_channel_group_t group) -{ - NRF_PPI->TASKS_CHG[(uint32_t) group].EN = NRF_PPI_TASK_SET; -} - -__STATIC_INLINE void nrf_ppi_group_disable(nrf_ppi_channel_group_t group) -{ - NRF_PPI->TASKS_CHG[(uint32_t) group].DIS = NRF_PPI_TASK_SET; -} - -__STATIC_INLINE void nrf_ppi_task_trigger(nrf_ppi_task_t ppi_task) -{ - *((volatile uint32_t *) ((uint8_t *) NRF_PPI_BASE + (uint32_t) ppi_task)) = NRF_PPI_TASK_SET; -} - -__STATIC_INLINE uint32_t * nrf_ppi_task_address_get(nrf_ppi_task_t ppi_task) -{ - return (uint32_t *) ((uint8_t *) NRF_PPI_BASE + (uint32_t) ppi_task); -} - -__STATIC_INLINE uint32_t * nrf_ppi_task_group_enable_address_get(nrf_ppi_channel_group_t group) -{ - return (uint32_t *) &NRF_PPI->TASKS_CHG[(uint32_t) group].EN; -} - -__STATIC_INLINE uint32_t * nrf_ppi_task_group_disable_address_get(nrf_ppi_channel_group_t group) -{ - return (uint32_t *) &NRF_PPI->TASKS_CHG[(uint32_t) group].DIS; -} - -#endif // SUPPRESS_INLINE_IMPLEMENTATION - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_PPI_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_pwm.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_pwm.h deleted file mode 100644 index 8bbe591d87..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_pwm.h +++ /dev/null @@ -1,694 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_PWM_H__ -#define NRF_PWM_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_pwm_hal PWM HAL - * @{ - * @ingroup nrf_pwm - * @brief Hardware access layer for managing the Pulse Width Modulation (PWM) peripheral. - */ - -/** - * @brief This value can be provided as a parameter for the @ref nrf_pwm_pins_set - * function call to specify that a given output channel shall not be - * connected to a physical pin. - */ -#define NRF_PWM_PIN_NOT_CONNECTED 0xFFFFFFFF - -/** - * @brief Number of channels in each Pointer to the peripheral registers structure. - */ -#define NRF_PWM_CHANNEL_COUNT 4 - - -/** - * @brief PWM tasks. - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_PWM_TASK_STOP = offsetof(NRF_PWM_Type, TASKS_STOP), ///< Stops PWM pulse generation on all channels at the end of the current PWM period, and stops the sequence playback. - NRF_PWM_TASK_SEQSTART0 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[0]), ///< Starts playback of sequence 0. - NRF_PWM_TASK_SEQSTART1 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[1]), ///< Starts playback of sequence 1. - NRF_PWM_TASK_NEXTSTEP = offsetof(NRF_PWM_Type, TASKS_NEXTSTEP) ///< Steps by one value in the current sequence if the decoder is set to @ref NRF_PWM_STEP_TRIGGERED mode. - /*lint -restore*/ -} nrf_pwm_task_t; - -/** - * @brief PWM events. - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_PWM_EVENT_STOPPED = offsetof(NRF_PWM_Type, EVENTS_STOPPED), ///< Response to STOP task, emitted when PWM pulses are no longer generated. - NRF_PWM_EVENT_SEQSTARTED0 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[0]), ///< First PWM period started on sequence 0. - NRF_PWM_EVENT_SEQSTARTED1 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[1]), ///< First PWM period started on sequence 1. - NRF_PWM_EVENT_SEQEND0 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[0]), ///< Emitted at the end of every sequence 0 when its last value has been read from RAM. - NRF_PWM_EVENT_SEQEND1 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[1]), ///< Emitted at the end of every sequence 1 when its last value has been read from RAM. - NRF_PWM_EVENT_PWMPERIODEND = offsetof(NRF_PWM_Type, EVENTS_PWMPERIODEND), ///< Emitted at the end of each PWM period. - NRF_PWM_EVENT_LOOPSDONE = offsetof(NRF_PWM_Type, EVENTS_LOOPSDONE) ///< Concatenated sequences have been played the requested number of times. - /*lint -restore*/ -} nrf_pwm_event_t; - -/** - * @brief PWM interrupts. - */ -typedef enum -{ - NRF_PWM_INT_STOPPED_MASK = PWM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event. - NRF_PWM_INT_SEQSTARTED0_MASK = PWM_INTENSET_SEQSTARTED0_Msk, ///< Interrupt on SEQSTARTED[0] event. - NRF_PWM_INT_SEQSTARTED1_MASK = PWM_INTENSET_SEQSTARTED1_Msk, ///< Interrupt on SEQSTARTED[1] event. - NRF_PWM_INT_SEQEND0_MASK = PWM_INTENSET_SEQEND0_Msk, ///< Interrupt on SEQEND[0] event. - NRF_PWM_INT_SEQEND1_MASK = PWM_INTENSET_SEQEND1_Msk, ///< Interrupt on SEQEND[1] event. - NRF_PWM_INT_PWMPERIODEND_MASK = PWM_INTENSET_PWMPERIODEND_Msk, ///< Interrupt on PWMPERIODEND event. - NRF_PWM_INT_LOOPSDONE_MASK = PWM_INTENSET_LOOPSDONE_Msk ///< Interrupt on LOOPSDONE event. -} nrf_pwm_int_mask_t; - -/** - * @brief PWM shortcuts. - */ -typedef enum -{ - NRF_PWM_SHORT_SEQEND0_STOP_MASK = PWM_SHORTS_SEQEND0_STOP_Msk, ///< Shortcut between SEQEND[0] event and STOP task. - NRF_PWM_SHORT_SEQEND1_STOP_MASK = PWM_SHORTS_SEQEND1_STOP_Msk, ///< Shortcut between SEQEND[1] event and STOP task. - NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[0] task. - NRF_PWM_SHORT_LOOPSDONE_SEQSTART1_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[1] task. - NRF_PWM_SHORT_LOOPSDONE_STOP_MASK = PWM_SHORTS_LOOPSDONE_STOP_Msk ///< Shortcut between LOOPSDONE event and STOP task. -} nrf_pwm_short_mask_t; - -/** - * @brief PWM modes of operation. - */ -typedef enum -{ - NRF_PWM_MODE_UP = PWM_MODE_UPDOWN_Up, ///< Up counter (edge-aligned PWM duty cycle). - NRF_PWM_MODE_UP_AND_DOWN = PWM_MODE_UPDOWN_UpAndDown, ///< Up and down counter (center-aligned PWM duty cycle). -} nrf_pwm_mode_t; - -/** - * @brief PWM base clock frequencies. - */ -typedef enum -{ - NRF_PWM_CLK_16MHz = PWM_PRESCALER_PRESCALER_DIV_1, ///< 16 MHz / 1 = 16 MHz. - NRF_PWM_CLK_8MHz = PWM_PRESCALER_PRESCALER_DIV_2, ///< 16 MHz / 2 = 8 MHz. - NRF_PWM_CLK_4MHz = PWM_PRESCALER_PRESCALER_DIV_4, ///< 16 MHz / 4 = 4 MHz. - NRF_PWM_CLK_2MHz = PWM_PRESCALER_PRESCALER_DIV_8, ///< 16 MHz / 8 = 2 MHz. - NRF_PWM_CLK_1MHz = PWM_PRESCALER_PRESCALER_DIV_16, ///< 16 MHz / 16 = 1 MHz. - NRF_PWM_CLK_500kHz = PWM_PRESCALER_PRESCALER_DIV_32, ///< 16 MHz / 32 = 500 kHz. - NRF_PWM_CLK_250kHz = PWM_PRESCALER_PRESCALER_DIV_64, ///< 16 MHz / 64 = 250 kHz. - NRF_PWM_CLK_125kHz = PWM_PRESCALER_PRESCALER_DIV_128 ///< 16 MHz / 128 = 125 kHz. -} nrf_pwm_clk_t; - -/** - * @brief PWM decoder load modes. - * - * The selected mode determines how the sequence data is read from RAM and - * spread to the compare registers. - */ -typedef enum -{ - NRF_PWM_LOAD_COMMON = PWM_DECODER_LOAD_Common, ///< 1st half word (16-bit) used in all PWM channels (0-3). - NRF_PWM_LOAD_GROUPED = PWM_DECODER_LOAD_Grouped, ///< 1st half word (16-bit) used in channels 0 and 1; 2nd word in channels 2 and 3. - NRF_PWM_LOAD_INDIVIDUAL = PWM_DECODER_LOAD_Individual, ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; 3rd in channel 2; 4th in channel 3. - NRF_PWM_LOAD_WAVE_FORM = PWM_DECODER_LOAD_WaveForm ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; ... ; 4th as the top value for the pulse generator counter. -} nrf_pwm_dec_load_t; - -/** - * @brief PWM decoder next step modes. - * - * The selected mode determines when the next value from the active sequence - * is loaded. - */ -typedef enum -{ - NRF_PWM_STEP_AUTO = PWM_DECODER_MODE_RefreshCount, ///< Automatically after the current value is played and repeated the requested number of times. - NRF_PWM_STEP_TRIGGERED = PWM_DECODER_MODE_NextStep ///< When the @ref NRF_PWM_TASK_NEXTSTEP task is triggered. -} nrf_pwm_dec_step_t; - - -/** - * @brief Type used for defining duty cycle values for a sequence - * loaded in @ref NRF_PWM_LOAD_COMMON mode. - */ -typedef uint16_t nrf_pwm_values_common_t; - -/** - * @brief Structure for defining duty cycle values for a sequence - * loaded in @ref NRF_PWM_LOAD_GROUPED mode. - */ -typedef struct { - uint16_t group_0; ///< Duty cycle value for group 0 (channels 0 and 1). - uint16_t group_1; ///< Duty cycle value for group 1 (channels 2 and 3). -} nrf_pwm_values_grouped_t; - -/** - * @brief Structure for defining duty cycle values for a sequence - * loaded in @ref NRF_PWM_LOAD_INDIVIDUAL mode. - */ -typedef struct -{ - uint16_t channel_0; ///< Duty cycle value for channel 0. - uint16_t channel_1; ///< Duty cycle value for channel 1. - uint16_t channel_2; ///< Duty cycle value for channel 2. - uint16_t channel_3; ///< Duty cycle value for channel 3. -} nrf_pwm_values_individual_t; - -/** - * @brief Structure for defining duty cycle values for a sequence - * loaded in @ref NRF_PWM_LOAD_WAVE_FORM mode. - */ -typedef struct { - uint16_t channel_0; ///< Duty cycle value for channel 0. - uint16_t channel_1; ///< Duty cycle value for channel 1. - uint16_t channel_2; ///< Duty cycle value for channel 2. - uint16_t counter_top; ///< Top value for the pulse generator counter. -} nrf_pwm_values_wave_form_t; - -/** - * @brief Union grouping pointers to arrays of duty cycle values applicable to - * various loading modes. - */ -typedef union { - nrf_pwm_values_common_t const * p_common; ///< Pointer to be used in @ref NRF_PWM_LOAD_COMMON mode. - nrf_pwm_values_grouped_t const * p_grouped; ///< Pointer to be used in @ref NRF_PWM_LOAD_GROUPED mode. - nrf_pwm_values_individual_t const * p_individual; ///< Pointer to be used in @ref NRF_PWM_LOAD_INDIVIDUAL mode. - nrf_pwm_values_wave_form_t const * p_wave_form; ///< Pointer to be used in @ref NRF_PWM_LOAD_WAVE_FORM mode. - uint16_t const * p_raw; ///< Pointer providing raw access to the values. -} nrf_pwm_values_t; - -/** - * @brief Structure for defining a sequence of PWM duty cycles. - * - * When the sequence is set (by a call to @ref nrf_pwm_sequence_set), the - * provided duty cycle values are not copied. The @p values pointer is stored - * in the peripheral's internal register, and the values are loaded from RAM - * during the sequence playback. Therefore, you must ensure that the values - * do not change before and during the sequence playback (for example, - * the values cannot be placed in a local variable that is allocated on stack). - * If the sequence is played in a loop and the values should be updated - * before the next iteration, it is safe to modify them when the corresponding - * event signaling the end of sequence occurs (@ref NRF_PWM_EVENT_SEQEND0 - * or @ref NRF_PWM_EVENT_SEQEND1, respectively). - * - * @note The @p repeats and @p end_delay values (which are written to the - * SEQ[n].REFRESH and SEQ[n].ENDDELAY registers in the peripheral, - * respectively) are ignored at the end of a complex sequence - * playback, indicated by the LOOPSDONE event. - * See the @linkProductSpecification52 for more information. - */ -typedef struct -{ - nrf_pwm_values_t values; ///< Pointer to an array with duty cycle values. This array must be in Data RAM. - /**< This field is defined as an union of pointers - * to provide a convenient way to define duty - * cycle values in various loading modes - * (see @ref nrf_pwm_dec_load_t). - * In each value, the most significant bit (15) - * determines the polarity of the output and the - * others (14-0) compose the 15-bit value to be - * compared with the pulse generator counter. */ - uint16_t length; ///< Number of 16-bit values in the array pointed by @p values. - uint32_t repeats; ///< Number of times that each duty cycle should be repeated (after being played once). Ignored in @ref NRF_PWM_STEP_TRIGGERED mode. - uint32_t end_delay; ///< Additional time (in PWM periods) that the last duty cycle is to be kept after the sequence is played. Ignored in @ref NRF_PWM_STEP_TRIGGERED mode. -} nrf_pwm_sequence_t; - -/** - * @brief Helper macro for calculating the number of 16-bit values in specified - * array of duty cycle values. - */ -#define NRF_PWM_VALUES_LENGTH(array) (sizeof(array) / sizeof(uint16_t)) - - -/** - * @brief Function for activating a specific PWM task. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] task Task to activate. - */ -__STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_reg, - nrf_pwm_task_t task); - -/** - * @brief Function for getting the address of a specific PWM task register. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] task Requested task. - * - * @return Address of the specified task register. - */ -__STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg, - nrf_pwm_task_t task); - -/** - * @brief Function for clearing a specific PWM event. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] event Event to clear. - */ -__STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg, - nrf_pwm_event_t event); - -/** - * @brief Function for checking the state of a specific PWM event. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] event Event to check. - * - * @retval true If the event is set. - * @retval false If the event is not set. - */ -__STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_reg, - nrf_pwm_event_t event); - -/** - * @brief Function for getting the address of a specific PWM event register. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] event Requested event. - * - * @return Address of the specified event register. - */ -__STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg, - nrf_pwm_event_t event); - -/** - * @brief Function for enabling specified shortcuts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] pwm_shorts_mask Shortcuts to enable. - */ -__STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg, - uint32_t pwm_shorts_mask); - -/** - * @brief Function for disabling specified shortcuts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] pwm_shorts_mask Shortcuts to disable. - */ -__STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg, - uint32_t pwm_shorts_mask); - -/** - * @brief Function for setting the configuration of PWM shortcuts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] pwm_shorts_mask Shortcuts configuration to set. - */ -__STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_reg, - uint32_t pwm_shorts_mask); - -/** - * @brief Function for enabling specified interrupts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] pwm_int_mask Interrupts to enable. - */ -__STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_reg, - uint32_t pwm_int_mask); - -/** - * @brief Function for disabling specified interrupts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] pwm_int_mask Interrupts to disable. - */ -__STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_reg, - uint32_t pwm_int_mask); - -/** - * @brief Function for setting the configuration of PWM interrupts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] pwm_int_mask Interrupts configuration to set. - */ -__STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_reg, - uint32_t pwm_int_mask); - -/** - * @brief Function for retrieving the state of a given interrupt. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] pwm_int Interrupt to check. - * - * @retval true If the interrupt is enabled. - * @retval false If the interrupt is not enabled. - */ -__STATIC_INLINE bool nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg, - nrf_pwm_int_mask_t pwm_int); - -/** - * @brief Function for enabling the PWM peripheral. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_reg); - -/** - * @brief Function for disabling the PWM peripheral. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_reg); - -/** - * @brief Function for assigning pins to PWM output channels. - * - * Usage of all PWM output channels is optional. If a given channel is not - * needed, pass the @ref NRF_PWM_PIN_NOT_CONNECTED value instead of its pin - * number. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] out_pins Array with pin numbers for individual PWM output channels. - */ -__STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_reg, - uint32_t out_pins[NRF_PWM_CHANNEL_COUNT]); - -/** - * @brief Function for configuring the PWM peripheral. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] base_clock Base clock frequency. - * @param[in] mode Operating mode of the pulse generator counter. - * @param[in] top_value Value up to which the pulse generator counter counts. - */ -__STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_reg, - nrf_pwm_clk_t base_clock, - nrf_pwm_mode_t mode, - uint16_t top_value); - -/** - * @brief Function for defining a sequence of PWM duty cycles. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] seq_id Identifier of the sequence (0 or 1). - * @param[in] p_seq Pointer to the sequence definition. - */ -__STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg, - uint8_t seq_id, - nrf_pwm_sequence_t const * p_seq); - -/** - * @brief Function for modifying the pointer to the duty cycle values - * in the specified sequence. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] seq_id Identifier of the sequence (0 or 1). - * @param[in] p_values Pointer to an array with duty cycle values. - */ -__STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg, - uint8_t seq_id, - uint16_t const * p_values); - -/** - * @brief Function for modifying the total number of duty cycle values - * in the specified sequence. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] seq_id Identifier of the sequence (0 or 1). - * @param[in] length Number of duty cycle values. - */ -__STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg, - uint8_t seq_id, - uint16_t length); - -/** - * @brief Function for modifying the additional number of PWM periods spent - * on each duty cycle value in the specified sequence. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] seq_id Identifier of the sequence (0 or 1). - * @param[in] refresh Number of additional PWM periods for each duty cycle value. - */ -__STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg, - uint8_t seq_id, - uint32_t refresh); - -/** - * @brief Function for modifying the additional time added after the sequence - * is played. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] seq_id Identifier of the sequence (0 or 1). - * @param[in] end_delay Number of PWM periods added at the end of the sequence. - */ -__STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg, - uint8_t seq_id, - uint32_t end_delay); - -/** - * @brief Function for setting the mode of loading sequence data from RAM - * and advancing the sequence. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] dec_load Mode of loading sequence data from RAM. - * @param[in] dec_step Mode of advancing the active sequence. - */ -__STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_reg, - nrf_pwm_dec_load_t dec_load, - nrf_pwm_dec_step_t dec_step); - -/** - * @brief Function for setting the number of times the sequence playback - * should be performed. - * - * This function applies to two-sequence playback (concatenated sequence 0 and 1). - * A single sequence can be played back only once. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] loop_count Number of times to perform the sequence playback. - */ -__STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_reg, - uint16_t loop_count); - - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -__STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_reg, - nrf_pwm_task_t task) -{ - *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; -} - -__STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg, - nrf_pwm_task_t task) -{ - return ((uint32_t)p_reg + (uint32_t)task); -} - -__STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg, - nrf_pwm_event_t event) -{ - *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif -} - -__STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_reg, - nrf_pwm_event_t event) -{ - return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event); -} - -__STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg, - nrf_pwm_event_t event) -{ - return ((uint32_t)p_reg + (uint32_t)event); -} - -__STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg, - uint32_t pwm_shorts_mask) -{ - p_reg->SHORTS |= pwm_shorts_mask; -} - -__STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg, - uint32_t pwm_shorts_mask) -{ - p_reg->SHORTS &= ~(pwm_shorts_mask); -} - -__STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_reg, - uint32_t pwm_shorts_mask) -{ - p_reg->SHORTS = pwm_shorts_mask; -} - -__STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_reg, - uint32_t pwm_int_mask) -{ - p_reg->INTENSET = pwm_int_mask; -} - -__STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_reg, - uint32_t pwm_int_mask) -{ - p_reg->INTENCLR = pwm_int_mask; -} - -__STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_reg, - uint32_t pwm_int_mask) -{ - p_reg->INTEN = pwm_int_mask; -} - -__STATIC_INLINE bool nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg, - nrf_pwm_int_mask_t pwm_int) -{ - return (bool)(p_reg->INTENSET & pwm_int); -} - -__STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_reg) -{ - p_reg->ENABLE = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos); -} - -__STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_reg) -{ - p_reg->ENABLE = (PWM_ENABLE_ENABLE_Disabled << PWM_ENABLE_ENABLE_Pos); -} - -__STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_reg, - uint32_t out_pins[NRF_PWM_CHANNEL_COUNT]) -{ - uint8_t i; - for (i = 0; i < NRF_PWM_CHANNEL_COUNT; ++i) - { - p_reg->PSEL.OUT[i] = out_pins[i]; - } -} - -__STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_reg, - nrf_pwm_clk_t base_clock, - nrf_pwm_mode_t mode, - uint16_t top_value) -{ - NRFX_ASSERT(top_value <= PWM_COUNTERTOP_COUNTERTOP_Msk); - - p_reg->PRESCALER = base_clock; - p_reg->MODE = mode; - p_reg->COUNTERTOP = top_value; -} - -__STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg, - uint8_t seq_id, - nrf_pwm_sequence_t const * p_seq) -{ - NRFX_ASSERT(p_seq != NULL); - - nrf_pwm_seq_ptr_set( p_reg, seq_id, p_seq->values.p_raw); - nrf_pwm_seq_cnt_set( p_reg, seq_id, p_seq->length); - nrf_pwm_seq_refresh_set( p_reg, seq_id, p_seq->repeats); - nrf_pwm_seq_end_delay_set(p_reg, seq_id, p_seq->end_delay); -} - -__STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg, - uint8_t seq_id, - uint16_t const * p_values) -{ - NRFX_ASSERT(seq_id <= 1); - NRFX_ASSERT(p_values != NULL); - p_reg->SEQ[seq_id].PTR = (uint32_t)p_values; -} - -__STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg, - uint8_t seq_id, - uint16_t length) -{ - NRFX_ASSERT(seq_id <= 1); - NRFX_ASSERT(length != 0); - NRFX_ASSERT(length <= PWM_SEQ_CNT_CNT_Msk); - p_reg->SEQ[seq_id].CNT = length; -} - -__STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg, - uint8_t seq_id, - uint32_t refresh) -{ - NRFX_ASSERT(seq_id <= 1); - NRFX_ASSERT(refresh <= PWM_SEQ_REFRESH_CNT_Msk); - p_reg->SEQ[seq_id].REFRESH = refresh; -} - -__STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg, - uint8_t seq_id, - uint32_t end_delay) -{ - NRFX_ASSERT(seq_id <= 1); - NRFX_ASSERT(end_delay <= PWM_SEQ_ENDDELAY_CNT_Msk); - p_reg->SEQ[seq_id].ENDDELAY = end_delay; -} - -__STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_reg, - nrf_pwm_dec_load_t dec_load, - nrf_pwm_dec_step_t dec_step) -{ - p_reg->DECODER = ((uint32_t)dec_load << PWM_DECODER_LOAD_Pos) | - ((uint32_t)dec_step << PWM_DECODER_MODE_Pos); -} - -__STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_reg, - uint16_t loop_count) -{ - p_reg->LOOP = loop_count; -} - -#endif // SUPPRESS_INLINE_IMPLEMENTATION - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_PWM_H__ - diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_qdec.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_qdec.h deleted file mode 100644 index 4eb125570f..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_qdec.h +++ /dev/null @@ -1,495 +0,0 @@ -/** - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef NRF_QDEC_H__ -#define NRF_QDEC_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_qdec_hal QDEC HAL - * @{ - * @ingroup nrf_qdec - * @brief Hardware access layer for managing the Quadrature Decoder (QDEC) peripheral. - */ - -/** - * @enum nrf_qdec_task_t - * @brief QDEC tasks. - */ -typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ -{ - NRF_QDEC_TASK_START = offsetof(NRF_QDEC_Type, TASKS_START), /**< Starting the quadrature decoder. */ - NRF_QDEC_TASK_STOP = offsetof(NRF_QDEC_Type, TASKS_STOP), /**< Stopping the quadrature decoder. */ - NRF_QDEC_TASK_READCLRACC = offsetof(NRF_QDEC_Type, TASKS_READCLRACC) /**< Reading and clearing ACC and ACCDBL registers. */ -} nrf_qdec_task_t; - -/** - * @enum nrf_qdec_event_t - * @brief QDEC events. - */ -typedef enum -{ - NRF_QDEC_EVENT_SAMPLERDY = offsetof(NRF_QDEC_Type, EVENTS_SAMPLERDY), /**< Event generated for every new sample. */ - NRF_QDEC_EVENT_REPORTRDY = offsetof(NRF_QDEC_Type, EVENTS_REPORTRDY), /**< Event generated for every new report. */ - NRF_QDEC_EVENT_ACCOF = offsetof(NRF_QDEC_Type, EVENTS_ACCOF) /**< Event generated for every accumulator overflow. */ -} nrf_qdec_event_t; /*lint -restore */ - -/** - * @enum nrf_qdec_short_mask_t - * @brief QDEC shortcuts. - */ -typedef enum -{ - NRF_QDEC_SHORT_REPORTRDY_READCLRACC_MASK = QDEC_SHORTS_REPORTRDY_READCLRACC_Msk, /**< Shortcut between REPORTRDY event and READCLRACC task. */ - NRF_QDEC_SHORT_SAMPLERDY_STOP_MASK = QDEC_SHORTS_SAMPLERDY_STOP_Msk /**< Shortcut between SAMPLERDY event and STOP task. */ -} nrf_qdec_short_mask_t; - -/** - * @enum nrf_qdec_int_mask_t - * @brief QDEC interrupts. - */ -typedef enum -{ - NRF_QDEC_INT_SAMPLERDY_MASK = QDEC_INTENSET_SAMPLERDY_Msk, /**< Mask for enabling or disabling an interrupt on SAMPLERDY event. */ - NRF_QDEC_INT_REPORTRDY_MASK = QDEC_INTENSET_REPORTRDY_Msk, /**< Mask for enabling or disabling an interrupt on REPORTRDY event. */ - NRF_QDEC_INT_ACCOF_MASK = QDEC_INTENSET_ACCOF_Msk /**< Mask for enabling or disabling an interrupt on ACCOF event. */ -} nrf_qdec_int_mask_t; - -/** - * @enum nrf_qdec_enable_t - * @brief States of the enable bit. - */ -typedef enum -{ - NRF_QDEC_DISABLE = QDEC_ENABLE_ENABLE_Disabled, /**< Mask for disabling the QDEC periperal. When disabled, the QDEC decoder pins are not active. */ - NRF_QDEC_ENABLE = QDEC_ENABLE_ENABLE_Enabled /**< Mask for enabling the QDEC periperal. When enabled, the QDEC pins are active. */ -} nrf_qdec_enable_t; - - -/** - * @enum nrf_qdec_dbfen_t - * @brief States of the debounce filter enable bit. - */ -typedef enum -{ - NRF_QDEC_DBFEN_DISABLE = QDEC_DBFEN_DBFEN_Disabled, /**< Mask for disabling the debounce filter. */ - NRF_QDEC_DBFEN_ENABLE = QDEC_DBFEN_DBFEN_Enabled /**< Mask for enabling the debounce filter. */ -} nrf_qdec_dbfen_t; - -/** - * @enum nrf_qdec_ledpol_t - * @brief Active LED polarity. - */ -typedef enum -{ - NRF_QDEC_LEPOL_ACTIVE_LOW = QDEC_LEDPOL_LEDPOL_ActiveLow, /**< QDEC LED active on output pin low. */ - NRF_QDEC_LEPOL_ACTIVE_HIGH = QDEC_LEDPOL_LEDPOL_ActiveHigh /**< QDEC LED active on output pin high. */ -} nrf_qdec_ledpol_t; - - -/** - * @enum nrf_qdec_sampleper_t - * @brief Available sampling periods. - */ -typedef enum -{ - NRF_QDEC_SAMPLEPER_128us = QDEC_SAMPLEPER_SAMPLEPER_128us, /**< QDEC sampling period 128 microseconds. */ - NRF_QDEC_SAMPLEPER_256us = QDEC_SAMPLEPER_SAMPLEPER_256us, /**< QDEC sampling period 256 microseconds. */ - NRF_QDEC_SAMPLEPER_512us = QDEC_SAMPLEPER_SAMPLEPER_512us, /**< QDEC sampling period 512 microseconds. */ - NRF_QDEC_SAMPLEPER_1024us = QDEC_SAMPLEPER_SAMPLEPER_1024us, /**< QDEC sampling period 1024 microseconds. */ - NRF_QDEC_SAMPLEPER_2048us = QDEC_SAMPLEPER_SAMPLEPER_2048us, /**< QDEC sampling period 2048 microseconds. */ - NRF_QDEC_SAMPLEPER_4096us = QDEC_SAMPLEPER_SAMPLEPER_4096us, /**< QDEC sampling period 4096 microseconds. */ - NRF_QDEC_SAMPLEPER_8192us = QDEC_SAMPLEPER_SAMPLEPER_8192us, /**< QDEC sampling period 8192 microseconds. */ - NRF_QDEC_SAMPLEPER_16384us = QDEC_SAMPLEPER_SAMPLEPER_16384us /**< QDEC sampling period 16384 microseconds. */ -} nrf_qdec_sampleper_t; - -/** - * @enum nrf_qdec_reportper_t - * @brief Available report periods. - */ -typedef enum -{ - NRF_QDEC_REPORTPER_10 = QDEC_REPORTPER_REPORTPER_10Smpl, /**< QDEC report period 10 samples. */ - NRF_QDEC_REPORTPER_40 = QDEC_REPORTPER_REPORTPER_40Smpl, /**< QDEC report period 40 samples. */ - NRF_QDEC_REPORTPER_80 = QDEC_REPORTPER_REPORTPER_80Smpl, /**< QDEC report period 80 samples. */ - NRF_QDEC_REPORTPER_120 = QDEC_REPORTPER_REPORTPER_120Smpl, /**< QDEC report period 120 samples. */ - NRF_QDEC_REPORTPER_160 = QDEC_REPORTPER_REPORTPER_160Smpl, /**< QDEC report period 160 samples. */ - NRF_QDEC_REPORTPER_200 = QDEC_REPORTPER_REPORTPER_200Smpl, /**< QDEC report period 200 samples. */ - NRF_QDEC_REPORTPER_240 = QDEC_REPORTPER_REPORTPER_240Smpl, /**< QDEC report period 240 samples. */ - NRF_QDEC_REPORTPER_280 = QDEC_REPORTPER_REPORTPER_280Smpl, /**< QDEC report period 280 samples. */ - NRF_QDEC_REPORTPER_DISABLED /**< QDEC reporting disabled. */ -} nrf_qdec_reportper_t; - -/** - * @brief Function for enabling QDEC. - */ -__STATIC_INLINE void nrf_qdec_enable(void) -{ - NRF_QDEC->ENABLE = NRF_QDEC_ENABLE; -} - - -/** - * @brief Function for disabling QDEC. - */ -__STATIC_INLINE void nrf_qdec_disable(void) -{ - NRF_QDEC->ENABLE = NRF_QDEC_DISABLE; -} - - -/** - * @brief Function for returning the enable state of QDEC. - * @return State of the register. - */ -__STATIC_INLINE uint32_t nrf_qdec_enable_get(void) -{ - return NRF_QDEC->ENABLE; -} - - -/** - * @brief Function for enabling QDEC interrupts by mask. - * @param[in] qdec_int_mask Sources of the interrupts to enable. - */ -__STATIC_INLINE void nrf_qdec_int_enable(uint32_t qdec_int_mask) -{ - NRF_QDEC->INTENSET = qdec_int_mask; // writing 0 has no effect -} - - -/** - * @brief Function for disabling QDEC interrupts by mask. - * @param[in] qdec_int_mask Sources of the interrupts to disable. - * - */ -__STATIC_INLINE void nrf_qdec_int_disable(uint32_t qdec_int_mask) -{ - NRF_QDEC->INTENCLR = qdec_int_mask; // writing 0 has no effect -} - - -/** - * @brief Function for getting the enabled interrupts of the QDEC. - */ -__STATIC_INLINE uint32_t nrf_qdec_int_enable_check(nrf_qdec_int_mask_t qdec_int_mask) -{ - return NRF_QDEC->INTENSET & qdec_int_mask; // when read this register will return the value of INTEN. -} - - -/** - * @brief Function for enabling the debouncing filter of the QED. - */ -__STATIC_INLINE void nrf_qdec_dbfen_enable(void) -{ - NRF_QDEC->DBFEN = NRF_QDEC_DBFEN_ENABLE; -} - - -/** - * @brief Function for disabling the debouncing filter of the QED. - */ -__STATIC_INLINE void nrf_qdec_dbfen_disable(void) -{ - NRF_QDEC->DBFEN = NRF_QDEC_DBFEN_DISABLE; -} - - -/** - * @brief Function for getting the state of the QDEC's debouncing filter. - * @retval NRF_QDEC_DBFEN_DISABLE If the debouncing filter is disabled. - * @retval NRF_QDEC_DBFEN_ENABLE If the debouncing filter is enabled. - */ -__STATIC_INLINE uint32_t nrf_qdec_dbfen_get(void) -{ - return NRF_QDEC->DBFEN; -} - - -/** - * @brief Function for assigning QDEC pins. - * @param[in] psela Pin number. - * @param[in] pselb Pin number. - * @param[in] pselled Pin number. - */ -__STATIC_INLINE void nrf_qdec_pio_assign( uint32_t psela, uint32_t pselb, uint32_t pselled) -{ - NRF_QDEC->PSELA = psela; - NRF_QDEC->PSELB = pselb; - NRF_QDEC->PSELLED = pselled; - -} - -/** - * @brief Function for setting a specific QDEC task. - * @param[in] qdec_task QDEC task to be set. - */ -__STATIC_INLINE void nrf_qdec_task_trigger(nrf_qdec_task_t qdec_task) -{ - *( (volatile uint32_t *)( (uint8_t *)NRF_QDEC + qdec_task) ) = 1; -} - - -/** - * @brief Function for retrieving the address of a QDEC task register. - * @param[in] qdec_task QDEC task. - */ -__STATIC_INLINE uint32_t * nrf_qdec_task_address_get(nrf_qdec_task_t qdec_task) -{ - return (uint32_t *)( (uint8_t *)NRF_QDEC + qdec_task); -} - - -/** - * @brief Function for clearing a specific QDEC event. - * @param[in] qdec_event QDEC event to clear. - */ -__STATIC_INLINE void nrf_qdec_event_clear(nrf_qdec_event_t qdec_event) -{ - *( (volatile uint32_t *)( (uint8_t *)NRF_QDEC + qdec_event) ) = 0; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_QDEC + qdec_event)); - (void)dummy; -#endif -} - - -/** - * @brief Function for retrieving the state of a specific QDEC event. - * @return State of the QDEC event. - */ -__STATIC_INLINE uint32_t nrf_qdec_event_check(nrf_qdec_event_t qdec_event) -{ - return *(volatile uint32_t *)( (uint8_t *)NRF_QDEC + qdec_event); -} - - -/** - * @brief Function for retrieving the address of a specific QDEC event register. - * @param[in] qdec_event QDEC event. - * @return Address of the specified QDEC event. - */ -__STATIC_INLINE uint32_t * nrf_qdec_event_address_get(nrf_qdec_event_t qdec_event) -{ - return (uint32_t *)( (uint8_t *)NRF_QDEC + qdec_event); -} - - -/** - * @brief Function for setting QDEC shortcuts. - * @param[in] qdec_short_mask QDEC shortcut by mask. - */ -__STATIC_INLINE void nrf_qdec_shorts_enable(uint32_t qdec_short_mask) -{ - NRF_QDEC->SHORTS |= qdec_short_mask; -} - - -/** - * @brief Function for clearing shortcuts of the QDEC by mask. - * @param[in] qdec_short_mask QDEC shortcute to be cleared. - */ -__STATIC_INLINE void nrf_qdec_shorts_disable(uint32_t qdec_short_mask) -{ - NRF_QDEC->SHORTS &= ~qdec_short_mask; -} - - -/** - * @brief Function for retrieving the value of QDEC's SAMPLEPER register. - * @return Value of the SAMPLEPER register. - */ -__STATIC_INLINE int32_t nrf_qdec_sampleper_reg_get(void) -{ - return NRF_QDEC->SAMPLEPER; -} - - -/** - * @brief Function for converting the value of QDEC's SAMPLE PERIOD to microseconds. - * @retval sampling period in microseconds. - */ -__STATIC_INLINE uint32_t nrf_qdec_sampleper_to_value(uint32_t sampleper) -{ - return (1 << (7 + sampleper)); -} - -/** - * @brief Function for setting the value of QDEC's SAMPLEPER register. - * @param[in] sample_per Sampling period. - */ -__STATIC_INLINE void nrf_qdec_sampleper_set(nrf_qdec_sampleper_t sample_per) -{ - NRF_QDEC->SAMPLEPER = sample_per; -} - - -/** - * @brief Function for retrieving the value of QDEC's SAMPLE register. - * @return Value of the SAMPLE register. - */ -__STATIC_INLINE int32_t nrf_qdec_sample_get(void) -{ - return NRF_QDEC->SAMPLE; -} - - -/** - * @brief Function for retrieving the value of QDEC's ACC register. - * @return Value of the ACC register. - */ -__STATIC_INLINE int32_t nrf_qdec_acc_get(void) -{ - return NRF_QDEC->ACC; -} - - -/** - * @brief Function for retrieving the value of QDEC's ACCREAD register. - * @return Value of the ACCREAD register. - */ -__STATIC_INLINE int32_t nrf_qdec_accread_get(void) -{ - return NRF_QDEC->ACCREAD; -} - - -/** - * @brief Function for retrieving the value of QDEC's ACCDBL register. - * @return Value of the ACCDBL register. - */ -__STATIC_INLINE uint32_t nrf_qdec_accdbl_get(void) -{ - return NRF_QDEC->ACCDBL; -} - - -/** - * @brief Function for retrieving the value of QDEC's ACCDBLREAD register. - * @return Value of the ACCDBLREAD register. - */ -__STATIC_INLINE uint32_t nrf_qdec_accdblread_get(void) -{ - return NRF_QDEC->ACCDBLREAD; -} - - -/** - * @brief Function for setting how long the LED is switched on before sampling. - * @param[in] time_us Time (in microseconds) how long the LED is switched on before sampling. - */ -__STATIC_INLINE void nrf_qdec_ledpre_set(uint32_t time_us) -{ - NRF_QDEC->LEDPRE = time_us; -} - - -/** - * @brief Function for retrieving how long the LED is switched on before sampling. - * @retval time_us Time (in microseconds) how long the LED is switched on before sampling. - */ -__STATIC_INLINE uint32_t nrf_qdec_ledpre_get(void) -{ - return NRF_QDEC->LEDPRE; -} - - -/** - * @brief Function for setting the report period (in samples). - * @param[in] reportper Number of samples. - */ -__STATIC_INLINE void nrf_qdec_reportper_set(nrf_qdec_reportper_t reportper) -{ - NRF_QDEC->REPORTPER = reportper; -} - - -/** - * @brief Function for retrieving the report period. - * @retval reportper Number of samples as encoded in the register. - */ -__STATIC_INLINE uint32_t nrf_qdec_reportper_reg_get(void) -{ - return NRF_QDEC->REPORTPER; -} - - -/** - * @brief Function for retrieving the value of QDEC's SAMPLEPER register. - * @param [in] reportper Reportper to be converted to amount of samples per report. - - */ -__STATIC_INLINE uint32_t nrf_qdec_reportper_to_value(uint32_t reportper) -{ - return (reportper == NRF_QDEC_REPORTPER_10) ? 10 : reportper * 40; -} - - -/** - * @brief Function for setting the active level for the LED. - * @param[in] pol Active level for the LED. - */ -__STATIC_INLINE void nrf_qdec_ledpol_set(nrf_qdec_ledpol_t pol) -{ - NRF_QDEC->LEDPOL = pol; -} - - -/** - * @brief Function for retrieving the active level for the LED. - * @return Active level for the LED. - */ -__STATIC_INLINE uint32_t nrf_qdec_ledpol_get(void) -{ - return NRF_QDEC->LEDPOL; -} - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_qspi.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_qspi.h deleted file mode 100644 index f3679ec3c2..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_qspi.h +++ /dev/null @@ -1,778 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_QSPI_H__ -#define NRF_QSPI_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_qspi_hal QSPI HAL - * @{ - * @ingroup nrf_qspi - * @brief Hardware access layer for managing the QSPI peripheral. - */ - -/** - * @brief This value can be used as a parameter for the @ref nrf_qspi_pins_set - * function to specify that a given QSPI signal (SCK, CSN, IO0, IO1, IO2, or IO3) - * will not be connected to a physical pin. - */ -#define NRF_QSPI_PIN_NOT_CONNECTED 0xFF - -/** - * @brief Macro for setting proper values to pin registers. - */ - -#define NRF_QSPI_PIN_VAL(pin) (pin) == NRF_QSPI_PIN_NOT_CONNECTED ? 0xFFFFFFFF : (pin) - -/** - * @brief QSPI tasks. - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_QSPI_TASK_ACTIVATE = offsetof(NRF_QSPI_Type, TASKS_ACTIVATE), /**< Activate the QSPI interface. */ - NRF_QSPI_TASK_READSTART = offsetof(NRF_QSPI_Type, TASKS_READSTART), /**< Start transfer from external flash memory to internal RAM. */ - NRF_QSPI_TASK_WRITESTART = offsetof(NRF_QSPI_Type, TASKS_WRITESTART), /**< Start transfer from internal RAM to external flash memory. */ - NRF_QSPI_TASK_ERASESTART = offsetof(NRF_QSPI_Type, TASKS_ERASESTART), /**< Start external flash memory erase operation. */ - NRF_QSPI_TASK_DEACTIVATE = offsetof(NRF_QSPI_Type, TASKS_DEACTIVATE), /**< Deactivate the QSPI interface. */ - /*lint -restore*/ -} nrf_qspi_task_t; - -/** - * @brief QSPI events. - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_QSPI_EVENT_READY = offsetof(NRF_QSPI_Type, EVENTS_READY) /**< QSPI peripheral is ready after it executes any task. */ - /*lint -restore*/ -} nrf_qspi_event_t; - -/** - * @brief QSPI interrupts. - */ -typedef enum -{ - NRF_QSPI_INT_READY_MASK = QSPI_INTENSET_READY_Msk /**< Interrupt on READY event. */ -} nrf_qspi_int_mask_t; - -/** - * @brief QSPI frequency divider values. - */ -typedef enum -{ - NRF_QSPI_FREQ_32MDIV1, /**< 32.0 MHz. */ - NRF_QSPI_FREQ_32MDIV2, /**< 16.0 MHz. */ - NRF_QSPI_FREQ_32MDIV3, /**< 10.6 MHz. */ - NRF_QSPI_FREQ_32MDIV4, /**< 8.00 MHz. */ - NRF_QSPI_FREQ_32MDIV5, /**< 6.40 MHz. */ - NRF_QSPI_FREQ_32MDIV6, /**< 5.33 MHz. */ - NRF_QSPI_FREQ_32MDIV7, /**< 4.57 MHz. */ - NRF_QSPI_FREQ_32MDIV8, /**< 4.00 MHz. */ - NRF_QSPI_FREQ_32MDIV9, /**< 3.55 MHz. */ - NRF_QSPI_FREQ_32MDIV10, /**< 3.20 MHz. */ - NRF_QSPI_FREQ_32MDIV11, /**< 2.90 MHz. */ - NRF_QSPI_FREQ_32MDIV12, /**< 2.66 MHz. */ - NRF_QSPI_FREQ_32MDIV13, /**< 2.46 MHz. */ - NRF_QSPI_FREQ_32MDIV14, /**< 2.29 MHz. */ - NRF_QSPI_FREQ_32MDIV15, /**< 2.13 MHz. */ - NRF_QSPI_FREQ_32MDIV16, /**< 2.00 MHz. */ -} nrf_qspi_frequency_t; - -/** - * @brief Interface configuration for a read operation. - */ -typedef enum -{ - NRF_QSPI_READOC_FASTREAD = QSPI_IFCONFIG0_READOC_FASTREAD, /**< Single data line SPI. FAST_READ (opcode 0x0B). */ - NRF_QSPI_READOC_READ2O = QSPI_IFCONFIG0_READOC_READ2O, /**< Dual data line SPI. READ2O (opcode 0x3B). */ - NRF_QSPI_READOC_READ2IO = QSPI_IFCONFIG0_READOC_READ2IO, /**< Dual data line SPI. READ2IO (opcode 0xBB). */ - NRF_QSPI_READOC_READ4O = QSPI_IFCONFIG0_READOC_READ4O, /**< Quad data line SPI. READ4O (opcode 0x6B). */ - NRF_QSPI_READOC_READ4IO = QSPI_IFCONFIG0_READOC_READ4IO /**< Quad data line SPI. READ4IO (opcode 0xEB). */ -} nrf_qspi_readoc_t; - -/** - * @brief Interface configuration for a write operation. - */ -typedef enum -{ - NRF_QSPI_WRITEOC_PP = QSPI_IFCONFIG0_WRITEOC_PP, /**< Single data line SPI. PP (opcode 0x02). */ - NRF_QSPI_WRITEOC_PP2O = QSPI_IFCONFIG0_WRITEOC_PP2O, /**< Dual data line SPI. PP2O (opcode 0xA2). */ - NRF_QSPI_WRITEOC_PP4O = QSPI_IFCONFIG0_WRITEOC_PP4O, /**< Quad data line SPI. PP4O (opcode 0x32). */ - NRF_QSPI_WRITEOC_PP4IO = QSPI_IFCONFIG0_WRITEOC_PP4IO, /**< Quad data line SPI. READ4O (opcode 0x38). */ -} nrf_qspi_writeoc_t; - -/** - * @brief Interface configuration for addressing mode. - */ -typedef enum -{ - NRF_QSPI_ADDRMODE_24BIT = QSPI_IFCONFIG0_ADDRMODE_24BIT, /**< 24-bit addressing. */ - NRF_QSPI_ADDRMODE_32BIT = QSPI_IFCONFIG0_ADDRMODE_32BIT /**< 32-bit addressing. */ -} nrf_qspi_addrmode_t; - -/** - * @brief QSPI SPI mode. Polarization and phase configuration. - */ -typedef enum -{ - NRF_QSPI_MODE_0 = QSPI_IFCONFIG1_SPIMODE_MODE0, /**< Mode 0 (CPOL=0, CPHA=0). */ - NRF_QSPI_MODE_1 = QSPI_IFCONFIG1_SPIMODE_MODE3 /**< Mode 1 (CPOL=1, CPHA=1). */ -} nrf_qspi_spi_mode_t; - -/** - * @brief Addressing configuration mode. - */ -typedef enum -{ - NRF_QSPI_ADDRCONF_MODE_NOINSTR = QSPI_ADDRCONF_MODE_NoInstr, /**< Do not send any instruction. */ - NRF_QSPI_ADDRCONF_MODE_OPCODE = QSPI_ADDRCONF_MODE_Opcode, /**< Send opcode. */ - NRF_QSPI_ADDRCONF_MODE_OPBYTE0 = QSPI_ADDRCONF_MODE_OpByte0, /**< Send opcode, byte0. */ - NRF_QSPI_ADDRCONF_MODE_ALL = QSPI_ADDRCONF_MODE_All /**< Send opcode, byte0, byte1. */ -} nrf_qspi_addrconfig_mode_t; - -/** - * @brief Erasing data length. - */ -typedef enum -{ - NRF_QSPI_ERASE_LEN_4KB = QSPI_ERASE_LEN_LEN_4KB, /**< Erase 4 kB block (flash command 0x20). */ - NRF_QSPI_ERASE_LEN_64KB = QSPI_ERASE_LEN_LEN_64KB, /**< Erase 64 kB block (flash command 0xD8). */ - NRF_QSPI_ERASE_LEN_ALL = QSPI_ERASE_LEN_LEN_All /**< Erase all (flash command 0xC7). */ -} nrf_qspi_erase_len_t; - -/** - * @brief Custom instruction length. - */ -typedef enum -{ - NRF_QSPI_CINSTR_LEN_1B = QSPI_CINSTRCONF_LENGTH_1B, /**< Send opcode only. */ - NRF_QSPI_CINSTR_LEN_2B = QSPI_CINSTRCONF_LENGTH_2B, /**< Send opcode, CINSTRDAT0.BYTE0. */ - NRF_QSPI_CINSTR_LEN_3B = QSPI_CINSTRCONF_LENGTH_3B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE1. */ - NRF_QSPI_CINSTR_LEN_4B = QSPI_CINSTRCONF_LENGTH_4B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE2. */ - NRF_QSPI_CINSTR_LEN_5B = QSPI_CINSTRCONF_LENGTH_5B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE3. */ - NRF_QSPI_CINSTR_LEN_6B = QSPI_CINSTRCONF_LENGTH_6B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE4. */ - NRF_QSPI_CINSTR_LEN_7B = QSPI_CINSTRCONF_LENGTH_7B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE5. */ - NRF_QSPI_CINSTR_LEN_8B = QSPI_CINSTRCONF_LENGTH_8B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE6. */ - NRF_QSPI_CINSTR_LEN_9B = QSPI_CINSTRCONF_LENGTH_9B /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE7. */ -} nrf_qspi_cinstr_len_t; - -/** - * @brief Pins configuration. - */ -typedef struct -{ - uint8_t sck_pin; /**< SCK pin number. */ - uint8_t csn_pin; /**< Chip select pin number. */ - uint8_t io0_pin; /**< IO0/MOSI pin number. */ - uint8_t io1_pin; /**< IO1/MISO pin number. */ - uint8_t io2_pin; /**< IO2 pin number (optional). - * Set to @ref NRF_QSPI_PIN_NOT_CONNECTED if this signal is not needed. - */ - uint8_t io3_pin; /**< IO3 pin number (optional). - * Set to @ref NRF_QSPI_PIN_NOT_CONNECTED if this signal is not needed. - */ -} nrf_qspi_pins_t; - -/** - * @brief Custom instruction configuration. - */ -typedef struct -{ - uint8_t opcode; /**< Opcode used in custom instruction transmission. */ - nrf_qspi_cinstr_len_t length; /**< Length of the custom instruction data. */ - bool io2_level; /**< I/O line level during transmission. */ - bool io3_level; /**< I/O line level during transmission. */ - bool wipwait; /**< Wait if a Wait in Progress bit is set in the memory status byte. */ - bool wren; /**< Send write enable before instruction. */ -} nrf_qspi_cinstr_conf_t; - -/** - * @brief Addressing mode register configuration. See @ref nrf_qspi_addrconfig_set - */ -typedef struct -{ - uint8_t opcode; /**< Opcode used to enter proper addressing mode. */ - uint8_t byte0; /**< Byte following the opcode. */ - uint8_t byte1; /**< Byte following byte0. */ - nrf_qspi_addrconfig_mode_t mode; /**< Extended addresing mode. */ - bool wipwait; /**< Enable/disable waiting for complete operation execution. */ - bool wren; /**< Send write enable before instruction. */ -} nrf_qspi_addrconfig_conf_t; - -/** - * @brief Structure with QSPI protocol interface configuration. - */ -typedef struct -{ - nrf_qspi_readoc_t readoc; /**< Read operation code. */ - nrf_qspi_writeoc_t writeoc; /**< Write operation code. */ - nrf_qspi_addrmode_t addrmode; /**< Addresing mode (24-bit or 32-bit). */ - bool dpmconfig; /**< Enable the Deep Power-down Mode (DPM) feature. */ -} nrf_qspi_prot_conf_t; - -/** - * @brief QSPI physical interface configuration. - */ -typedef struct -{ - uint8_t sck_delay; /**< tSHSL, tWHSL, and tSHWL in number of 16 MHz periods (62.5ns). */ - bool dpmen; /**< Enable the DPM feature. */ - nrf_qspi_spi_mode_t spi_mode; /**< SPI phase and polarization. */ - nrf_qspi_frequency_t sck_freq; /**< SCK frequency given as enum @ref nrf_qspi_frequency_t. */ -} nrf_qspi_phy_conf_t; - -/** - * @brief Function for activating a specific QSPI task. - * - * @param[in] p_reg Pointer to the peripheral register structure. - * @param[in] task Task to activate. - */ -__STATIC_INLINE void nrf_qspi_task_trigger(NRF_QSPI_Type * p_reg, nrf_qspi_task_t task); - -/** - * @brief Function for getting the address of a specific QSPI task register. - * - * @param[in] p_reg Pointer to the peripheral register structure. - * @param[in] task Requested task. - * - * @return Address of the specified task register. - */ -__STATIC_INLINE uint32_t nrf_qspi_task_address_get(NRF_QSPI_Type const * p_reg, - nrf_qspi_task_t task); - -/** - * @brief Function for clearing a specific QSPI event. - * - * @param[in] p_reg Pointer to the peripheral register structure. - * @param[in] qspi_event Event to clear. - */ -__STATIC_INLINE void nrf_qspi_event_clear(NRF_QSPI_Type * p_reg, nrf_qspi_event_t qspi_event); - -/** - * @brief Function for checking the state of a specific SPI event. - * - * @param[in] p_reg Pointer to the peripheral register structure. - * @param[in] qspi_event Event to check. - * - * @retval true If the event is set. - * @retval false If the event is not set. - */ -__STATIC_INLINE bool nrf_qspi_event_check(NRF_QSPI_Type const * p_reg, nrf_qspi_event_t qspi_event); - -/** - * @brief Function for getting the address of a specific QSPI event register. - * - * @param[in] p_reg Pointer to the peripheral register structure. - * @param[in] qspi_event Requested event. - * - * @return Address of the specified event register. - */ -__STATIC_INLINE uint32_t * nrf_qspi_event_address_get(NRF_QSPI_Type const * p_reg, - nrf_qspi_event_t qspi_event); - -/** - * @brief Function for enabling specified interrupts. - * - * @param[in] p_reg Pointer to the peripheral register structure. - * @param[in] qspi_int_mask Interrupts to enable. - */ -__STATIC_INLINE void nrf_qspi_int_enable(NRF_QSPI_Type * p_reg, uint32_t qspi_int_mask); - -/** - * @brief Function for disabling specified interrupts. - * - * @param[in] p_reg Pointer to the peripheral register structure. - * @param[in] qspi_int_mask Interrupts to disable. - */ -__STATIC_INLINE void nrf_qspi_int_disable(NRF_QSPI_Type * p_reg, uint32_t qspi_int_mask); - -/** - * @brief Function for retrieving the state of a given interrupt. - * - * @param[in] p_reg Pointer to the peripheral register structure. - * @param[in] qspi_int Interrupt to check. - * - * @retval true If the interrupt is enabled. - * @retval false If the interrupt is not enabled. - */ -__STATIC_INLINE bool nrf_qspi_int_enable_check(NRF_QSPI_Type const * p_reg, - nrf_qspi_int_mask_t qspi_int); - -/** - * @brief Function for enabling the QSPI peripheral. - * - * @param[in] p_reg Pointer to the peripheral register structure. - */ -__STATIC_INLINE void nrf_qspi_enable(NRF_QSPI_Type * p_reg); - -/** - * @brief Function for disabling the QSPI peripheral. - * - * @param[in] p_reg Pointer to the peripheral register structure. - */ -__STATIC_INLINE void nrf_qspi_disable(NRF_QSPI_Type * p_reg); - -/** - * @brief Function for configuring QSPI pins. - * - * If a given signal is not needed, pass the @ref NRF_QSPI_PIN_NOT_CONNECTED - * value instead of its pin number. - * - * @param[in] p_reg Pointer to the peripheral register structure. - * @param[in] p_pins Pointer to the pins configuration structure. See @ref nrf_qspi_pins_t. - */ -__STATIC_INLINE void nrf_qspi_pins_set(NRF_QSPI_Type * p_reg, - const nrf_qspi_pins_t * p_pins); - -/** - * @brief Function for setting the QSPI XIPOFFSET register. - * - * @param[in] p_reg Pointer to the peripheral register structure. - * @param[in] xip_offset Address offset in the external memory for Execute in Place operation. - */ -__STATIC_INLINE void nrf_qspi_xip_offset_set(NRF_QSPI_Type * p_reg, - uint32_t xip_offset); - -/** - * @brief Function for setting the QSPI IFCONFIG0 register. - * - * @param[in] p_reg Pointer to the peripheral register structure. - * @param[in] p_config Pointer to the QSPI protocol interface configuration structure. See @ref nrf_qspi_prot_conf_t. - */ -__STATIC_INLINE void nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg, - const nrf_qspi_prot_conf_t * p_config); - -/** - * @brief Function for setting the QSPI IFCONFIG1 register. - * - * @param[in] p_reg Pointer to the peripheral register structure. - * @param[in] p_config Pointer to the QSPI physical interface configuration structure. See @ref nrf_qspi_phy_conf_t. - */ -__STATIC_INLINE void nrf_qspi_ifconfig1_set(NRF_QSPI_Type * p_reg, - const nrf_qspi_phy_conf_t * p_config); - -/** - * @brief Function for setting the QSPI ADDRCONF register. - * - * Function must be executed before sending task NRF_QSPI_TASK_ACTIVATE. Data stored in the structure - * is sent during the start of the peripheral. Remember that the reset instruction can set - * addressing mode to default in the memory device. If memory reset is necessary before configuring - * the addressing mode, use custom instruction feature instead of this function. - * Case with reset: Enable the peripheral without setting ADDRCONF register, send reset instructions - * using a custom instruction feature (reset enable and then reset), set proper addressing mode - * using the custom instruction feature. - * - * @param[in] p_reg Pointer to the peripheral register structure. - * @param[in] p_config Pointer to the addressing mode configuration structure. See @ref nrf_qspi_addrconfig_conf_t. -*/ -__STATIC_INLINE void nrf_qspi_addrconfig_set(NRF_QSPI_Type * p_reg, - const nrf_qspi_addrconfig_conf_t * p_config); - -/** - * @brief Function for setting write data into the peripheral register (without starting the process). - * - * @param[in] p_reg Pointer to the peripheral register structure. - * @param[in] p_buffer Pointer to the writing buffer. - * @param[in] length Lenght of the writing data. - * @param[in] dest_addr Address in memory to write to. - */ -__STATIC_INLINE void nrf_qspi_write_buffer_set(NRF_QSPI_Type * p_reg, - void const * p_buffer, - uint32_t length, - uint32_t dest_addr); - -/** - * @brief Function for setting read data into the peripheral register (without starting the process). - * - * @param[in] p_reg Pointer to the peripheral register structure. - * @param[out] p_buffer Pointer to the reading buffer. - * @param[in] length Length of the read data. - * @param[in] src_addr Address in memory to read from. - */ -__STATIC_INLINE void nrf_qspi_read_buffer_set(NRF_QSPI_Type * p_reg, - void * p_buffer, - uint32_t length, - uint32_t src_addr); - -/** - * @brief Function for setting erase data into the peripheral register (without starting the process). - * - * @param[in] p_reg Pointer to the peripheral register structure. - * @param[in] erase_addr Start address to erase. Address must have padding set to 4 bytes. - * @param[in] len Size of erasing area. - */ -__STATIC_INLINE void nrf_qspi_erase_ptr_set(NRF_QSPI_Type * p_reg, - uint32_t erase_addr, - nrf_qspi_erase_len_t len); - -/** - * @brief Function for getting the peripheral status register. - * - * @param[in] p_reg Pointer to the peripheral register structure. - * - * @return Peripheral status register. - */ -__STATIC_INLINE uint32_t nrf_qspi_status_reg_get(NRF_QSPI_Type const * p_reg); - -/** - * @brief Function for getting the device status register stored in the peripheral status register. - * - * @param[in] p_reg Pointer to the peripheral register structure. - * - * @return Device status register (lower byte). - */ -__STATIC_INLINE uint8_t nrf_qspi_sreg_get(NRF_QSPI_Type const * p_reg); - -/** - * @brief Function for checking if the peripheral is busy or not. - * - * @param[in] p_reg Pointer to the peripheral register structure. - * - * @retval true If QSPI is busy. - * @retval false If QSPI is ready. - */ -__STATIC_INLINE bool nrf_qspi_busy_check(NRF_QSPI_Type const * p_reg); - -/** - * @brief Function for setting registers sending with custom instruction transmission. - * - * This function can be ommited when using NRF_QSPI_CINSTR_LEN_1B as the length argument - * (sending only opcode without data). - * - * @param[in] p_reg Pointer to the peripheral register structure. - * @param[in] length Length of the custom instruction data. - * @param[in] p_tx_data Pointer to the data to send with the custom instruction. - */ -__STATIC_INLINE void nrf_qspi_cinstrdata_set(NRF_QSPI_Type * p_reg, - nrf_qspi_cinstr_len_t length, - void const * p_tx_data); - -/** - * @brief Function for getting data from register after custom instruction transmission. - * @param[in] p_reg Pointer to the peripheral register structure. - * @param[in] length Length of the custom instruction data. - * @param[in] p_rx_data Pointer to the reading buffer. - */ -__STATIC_INLINE void nrf_qspi_cinstrdata_get(NRF_QSPI_Type const * p_reg, - nrf_qspi_cinstr_len_t length, - void * p_rx_data); - -/** - * @brief Function for sending custom instruction to external memory. - * - * @param[in] p_reg Pointer to the peripheral register structure. - * @param[in] p_config Pointer to the custom instruction configuration structure. See @ref nrf_qspi_cinstr_conf_t. - */ - -__STATIC_INLINE void nrf_qspi_cinstr_transfer_start(NRF_QSPI_Type * p_reg, - const nrf_qspi_cinstr_conf_t * p_config); - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -__STATIC_INLINE void nrf_qspi_task_trigger(NRF_QSPI_Type * p_reg, nrf_qspi_task_t task) -{ - *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; -} - -__STATIC_INLINE uint32_t nrf_qspi_task_address_get(NRF_QSPI_Type const * p_reg, - nrf_qspi_task_t task) -{ - return ((uint32_t)p_reg + (uint32_t)task); -} - -__STATIC_INLINE void nrf_qspi_event_clear(NRF_QSPI_Type * p_reg, nrf_qspi_event_t qspi_event) -{ - *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)qspi_event)) = 0x0UL; -} - -__STATIC_INLINE bool nrf_qspi_event_check(NRF_QSPI_Type const * p_reg, nrf_qspi_event_t qspi_event) -{ - return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)qspi_event); -} - -__STATIC_INLINE uint32_t * nrf_qspi_event_address_get(NRF_QSPI_Type const * p_reg, - nrf_qspi_event_t qspi_event) -{ - return (uint32_t *)((uint8_t *)p_reg + (uint32_t)qspi_event); -} - -__STATIC_INLINE void nrf_qspi_int_enable(NRF_QSPI_Type * p_reg, uint32_t qspi_int_mask) -{ - p_reg->INTENSET = qspi_int_mask; -} - -__STATIC_INLINE void nrf_qspi_int_disable(NRF_QSPI_Type * p_reg, uint32_t qspi_int_mask) -{ - p_reg->INTENCLR = qspi_int_mask; -} - -__STATIC_INLINE bool nrf_qspi_int_enable_check(NRF_QSPI_Type const * p_reg, - nrf_qspi_int_mask_t qspi_int) -{ - return (bool)(p_reg->INTENSET & qspi_int); -} - -__STATIC_INLINE void nrf_qspi_enable(NRF_QSPI_Type * p_reg) -{ - p_reg->ENABLE = (QSPI_ENABLE_ENABLE_Enabled << QSPI_ENABLE_ENABLE_Pos); -} - -__STATIC_INLINE void nrf_qspi_disable(NRF_QSPI_Type * p_reg) -{ - p_reg->ENABLE = (QSPI_ENABLE_ENABLE_Disabled << QSPI_ENABLE_ENABLE_Pos); -} - -__STATIC_INLINE void nrf_qspi_pins_set(NRF_QSPI_Type * p_reg, const nrf_qspi_pins_t * p_pins) -{ - p_reg->PSEL.SCK = NRF_QSPI_PIN_VAL(p_pins->sck_pin); - p_reg->PSEL.CSN = NRF_QSPI_PIN_VAL(p_pins->csn_pin); - p_reg->PSEL.IO0 = NRF_QSPI_PIN_VAL(p_pins->io0_pin); - p_reg->PSEL.IO1 = NRF_QSPI_PIN_VAL(p_pins->io1_pin); - p_reg->PSEL.IO2 = NRF_QSPI_PIN_VAL(p_pins->io2_pin); - p_reg->PSEL.IO3 = NRF_QSPI_PIN_VAL(p_pins->io3_pin); -} - -__STATIC_INLINE void nrf_qspi_xip_offset_set(NRF_QSPI_Type * p_reg, - uint32_t xip_offset) -{ - p_reg->XIPOFFSET = xip_offset; -} - -__STATIC_INLINE void nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg, - const nrf_qspi_prot_conf_t * p_config) -{ - uint32_t config = p_config->readoc; - config |= ((uint32_t)p_config->writeoc) << QSPI_IFCONFIG0_WRITEOC_Pos; - config |= ((uint32_t)p_config->addrmode) << QSPI_IFCONFIG0_ADDRMODE_Pos; - config |= (p_config->dpmconfig ? 1U : 0U ) << QSPI_IFCONFIG0_DPMENABLE_Pos; - - p_reg->IFCONFIG0 = config; -} - -__STATIC_INLINE void nrf_qspi_ifconfig1_set(NRF_QSPI_Type * p_reg, - const nrf_qspi_phy_conf_t * p_config) -{ - // IFCONFIG1 mask for reserved fields in the register. - uint32_t config = p_reg->IFCONFIG1 & 0x00FFFF00; - config |= p_config->sck_delay; - config |= (p_config->dpmen ? 1U : 0U) << QSPI_IFCONFIG1_DPMEN_Pos; - config |= ((uint32_t)(p_config->spi_mode)) << QSPI_IFCONFIG1_SPIMODE_Pos; - config |= ((uint32_t)(p_config->sck_freq)) << QSPI_IFCONFIG1_SCKFREQ_Pos; - - p_reg->IFCONFIG1 = config; -} - -__STATIC_INLINE void nrf_qspi_addrconfig_set(NRF_QSPI_Type * p_reg, - const nrf_qspi_addrconfig_conf_t * p_config) -{ - uint32_t config = p_config->opcode; - config |= ((uint32_t)p_config->byte0) << QSPI_ADDRCONF_BYTE0_Pos; - config |= ((uint32_t)p_config->byte1) << QSPI_ADDRCONF_BYTE1_Pos; - config |= ((uint32_t)(p_config->mode)) << QSPI_ADDRCONF_MODE_Pos; - config |= (p_config->wipwait ? 1U : 0U) << QSPI_ADDRCONF_WIPWAIT_Pos; - config |= (p_config->wren ? 1U : 0U) << QSPI_ADDRCONF_WREN_Pos; - - p_reg->ADDRCONF = config; -} - -__STATIC_INLINE void nrf_qspi_write_buffer_set(NRF_QSPI_Type * p_reg, - void const * p_buffer, - uint32_t length, - uint32_t dest_addr) -{ - p_reg->WRITE.DST = dest_addr; - p_reg->WRITE.SRC = (uint32_t) p_buffer; - p_reg->WRITE.CNT = length; -} - -__STATIC_INLINE void nrf_qspi_read_buffer_set(NRF_QSPI_Type * p_reg, - void * p_buffer, - uint32_t length, - uint32_t src_addr) -{ - p_reg->READ.SRC = src_addr; - p_reg->READ.DST = (uint32_t) p_buffer; - p_reg->READ.CNT = length; -} - -__STATIC_INLINE void nrf_qspi_erase_ptr_set(NRF_QSPI_Type * p_reg, - uint32_t erase_addr, - nrf_qspi_erase_len_t len) -{ - p_reg->ERASE.PTR = erase_addr; - p_reg->ERASE.LEN = len; -} - -__STATIC_INLINE uint32_t nrf_qspi_status_reg_get(NRF_QSPI_Type const * p_reg) -{ - return p_reg->STATUS; -} - -__STATIC_INLINE uint8_t nrf_qspi_sreg_get(NRF_QSPI_Type const * p_reg) -{ - return (uint8_t)(p_reg->STATUS & QSPI_STATUS_SREG_Msk) >> QSPI_STATUS_SREG_Pos; -} - -__STATIC_INLINE bool nrf_qspi_busy_check(NRF_QSPI_Type const * p_reg) -{ - return ((p_reg->STATUS & QSPI_STATUS_READY_Msk) >> - QSPI_STATUS_READY_Pos) == QSPI_STATUS_READY_BUSY; -} - -__STATIC_INLINE void nrf_qspi_cinstrdata_set(NRF_QSPI_Type * p_reg, - nrf_qspi_cinstr_len_t length, - void const * p_tx_data) -{ - uint32_t reg = 0; - uint8_t const *p_tx_data_8 = (uint8_t const *) p_tx_data; - - // Load custom instruction. - switch (length) - { - case NRF_QSPI_CINSTR_LEN_9B: - reg |= ((uint32_t)p_tx_data_8[7]) << QSPI_CINSTRDAT1_BYTE7_Pos; - /* fall-through */ - case NRF_QSPI_CINSTR_LEN_8B: - reg |= ((uint32_t)p_tx_data_8[6]) << QSPI_CINSTRDAT1_BYTE6_Pos; - /* fall-through */ - case NRF_QSPI_CINSTR_LEN_7B: - reg |= ((uint32_t)p_tx_data_8[5]) << QSPI_CINSTRDAT1_BYTE5_Pos; - /* fall-through */ - case NRF_QSPI_CINSTR_LEN_6B: - reg |= ((uint32_t)p_tx_data_8[4]); - p_reg->CINSTRDAT1 = reg; - reg = 0; - /* fall-through */ - case NRF_QSPI_CINSTR_LEN_5B: - reg |= ((uint32_t)p_tx_data_8[3]) << QSPI_CINSTRDAT0_BYTE3_Pos; - /* fall-through */ - case NRF_QSPI_CINSTR_LEN_4B: - reg |= ((uint32_t)p_tx_data_8[2]) << QSPI_CINSTRDAT0_BYTE2_Pos; - /* fall-through */ - case NRF_QSPI_CINSTR_LEN_3B: - reg |= ((uint32_t)p_tx_data_8[1]) << QSPI_CINSTRDAT0_BYTE1_Pos; - /* fall-through */ - case NRF_QSPI_CINSTR_LEN_2B: - reg |= ((uint32_t)p_tx_data_8[0]); - p_reg->CINSTRDAT0 = reg; - /* fall-through */ - case NRF_QSPI_CINSTR_LEN_1B: - /* Send only opcode. Case to avoid compiler warnings. */ - break; - default: - break; - } -} - -__STATIC_INLINE void nrf_qspi_cinstrdata_get(NRF_QSPI_Type const * p_reg, - nrf_qspi_cinstr_len_t length, - void * p_rx_data) -{ - uint8_t *p_rx_data_8 = (uint8_t *) p_rx_data; - - uint32_t reg = p_reg->CINSTRDAT1; - switch (length) - { - case NRF_QSPI_CINSTR_LEN_9B: - p_rx_data_8[7] = (uint8_t)(reg >> QSPI_CINSTRDAT1_BYTE7_Pos); - /* fall-through */ - case NRF_QSPI_CINSTR_LEN_8B: - p_rx_data_8[6] = (uint8_t)(reg >> QSPI_CINSTRDAT1_BYTE6_Pos); - /* fall-through */ - case NRF_QSPI_CINSTR_LEN_7B: - p_rx_data_8[5] = (uint8_t)(reg >> QSPI_CINSTRDAT1_BYTE5_Pos); - /* fall-through */ - case NRF_QSPI_CINSTR_LEN_6B: - p_rx_data_8[4] = (uint8_t)(reg); - /* fall-through */ - default: - break; - } - - reg = p_reg->CINSTRDAT0; - switch (length) - { - case NRF_QSPI_CINSTR_LEN_5B: - p_rx_data_8[3] = (uint8_t)(reg >> QSPI_CINSTRDAT0_BYTE3_Pos); - /* fall-through */ - case NRF_QSPI_CINSTR_LEN_4B: - p_rx_data_8[2] = (uint8_t)(reg >> QSPI_CINSTRDAT0_BYTE2_Pos); - /* fall-through */ - case NRF_QSPI_CINSTR_LEN_3B: - p_rx_data_8[1] = (uint8_t)(reg >> QSPI_CINSTRDAT0_BYTE1_Pos); - /* fall-through */ - case NRF_QSPI_CINSTR_LEN_2B: - p_rx_data_8[0] = (uint8_t)(reg); - /* fall-through */ - case NRF_QSPI_CINSTR_LEN_1B: - /* Send only opcode. Case to avoid compiler warnings. */ - break; - default: - break; - } -} - -__STATIC_INLINE void nrf_qspi_cinstr_transfer_start(NRF_QSPI_Type * p_reg, - const nrf_qspi_cinstr_conf_t * p_config) -{ - p_reg->CINSTRCONF = (((uint32_t)p_config->opcode << QSPI_CINSTRCONF_OPCODE_Pos) | - ((uint32_t)p_config->length << QSPI_CINSTRCONF_LENGTH_Pos) | - ((uint32_t)p_config->io2_level << QSPI_CINSTRCONF_LIO2_Pos) | - ((uint32_t)p_config->io3_level << QSPI_CINSTRCONF_LIO3_Pos) | - ((uint32_t)p_config->wipwait << QSPI_CINSTRCONF_WIPWAIT_Pos) | - ((uint32_t)p_config->wren << QSPI_CINSTRCONF_WREN_Pos)); -} - -#endif // SUPPRESS_INLINE_IMPLEMENTATION - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_QSPI_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_rng.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_rng.h deleted file mode 100644 index 8aa5ae10f7..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_rng.h +++ /dev/null @@ -1,274 +0,0 @@ -/** - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_RNG_H__ -#define NRF_RNG_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_rng_hal RNG HAL - * @{ - * @ingroup nrf_rng - * @brief Hardware access layer for managing the Random Number Generator (RNG) peripheral. - */ - -#define NRF_RNG_TASK_SET (1UL) -#define NRF_RNG_EVENT_CLEAR (0UL) -/** - * @enum nrf_rng_task_t - * @brief RNG tasks. - */ -typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ -{ - NRF_RNG_TASK_START = offsetof(NRF_RNG_Type, TASKS_START), /**< Start the random number generator. */ - NRF_RNG_TASK_STOP = offsetof(NRF_RNG_Type, TASKS_STOP) /**< Stop the random number generator. */ -} nrf_rng_task_t; /*lint -restore */ - -/** - * @enum nrf_rng_event_t - * @brief RNG events. - */ -typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ -{ - NRF_RNG_EVENT_VALRDY = offsetof(NRF_RNG_Type, EVENTS_VALRDY) /**< New random number generated event. */ -} nrf_rng_event_t; /*lint -restore */ - -/** - * @enum nrf_rng_int_mask_t - * @brief RNG interrupts. - */ -typedef enum -{ - NRF_RNG_INT_VALRDY_MASK = RNG_INTENSET_VALRDY_Msk /**< Mask for enabling or disabling an interrupt on VALRDY event. */ -} nrf_rng_int_mask_t; - -/** - * @enum nrf_rng_short_mask_t - * @brief Types of RNG shortcuts. - */ -typedef enum -{ - NRF_RNG_SHORT_VALRDY_STOP_MASK = RNG_SHORTS_VALRDY_STOP_Msk /**< Mask for setting shortcut between EVENT_VALRDY and TASK_STOP. */ -} nrf_rng_short_mask_t; - -/** - * @brief Function for enabling interrupts. - * - * @param[in] rng_int_mask Mask of interrupts. - */ -__STATIC_INLINE void nrf_rng_int_enable(uint32_t rng_int_mask); - -/** - * @brief Function for disabling interrupts. - * - * @param[in] rng_int_mask Mask of interrupts. - */ -__STATIC_INLINE void nrf_rng_int_disable(uint32_t rng_int_mask); - -/** - * @brief Function for getting the state of a specific interrupt. - * - * @param[in] rng_int_mask Interrupt. - * - * @retval true If the interrupt is not enabled. - * @retval false If the interrupt is enabled. - */ -__STATIC_INLINE bool nrf_rng_int_get(nrf_rng_int_mask_t rng_int_mask); - -/** - * @brief Function for getting the address of a specific task. - * - * This function can be used by the PPI module. - * - * @param[in] rng_task Task. - */ -__STATIC_INLINE uint32_t * nrf_rng_task_address_get(nrf_rng_task_t rng_task); - -/** - * @brief Function for setting a specific task. - * - * @param[in] rng_task Task. - */ -__STATIC_INLINE void nrf_rng_task_trigger(nrf_rng_task_t rng_task); - -/** - * @brief Function for getting address of a specific event. - * - * This function can be used by the PPI module. - * - * @param[in] rng_event Event. - */ -__STATIC_INLINE uint32_t * nrf_rng_event_address_get(nrf_rng_event_t rng_event); - -/** - * @brief Function for clearing a specific event. - * - * @param[in] rng_event Event. - */ -__STATIC_INLINE void nrf_rng_event_clear(nrf_rng_event_t rng_event); - -/** - * @brief Function for getting the state of a specific event. - * - * @param[in] rng_event Event. - * - * @retval true If the event is not set. - * @retval false If the event is set. - */ -__STATIC_INLINE bool nrf_rng_event_get(nrf_rng_event_t rng_event); - -/** - * @brief Function for setting shortcuts. - * - * @param[in] rng_short_mask Mask of shortcuts. - * - */ -__STATIC_INLINE void nrf_rng_shorts_enable(uint32_t rng_short_mask); - -/** - * @brief Function for clearing shortcuts. - * - * @param[in] rng_short_mask Mask of shortcuts. - * - */ -__STATIC_INLINE void nrf_rng_shorts_disable(uint32_t rng_short_mask); - -/** - * @brief Function for getting the previously generated random value. - * - * @return Previously generated random value. - */ -__STATIC_INLINE uint8_t nrf_rng_random_value_get(void); - -/** - * @brief Function for enabling digital error correction. - */ -__STATIC_INLINE void nrf_rng_error_correction_enable(void); - -/** - * @brief Function for disabling digital error correction. - */ -__STATIC_INLINE void nrf_rng_error_correction_disable(void); - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -__STATIC_INLINE void nrf_rng_int_enable(uint32_t rng_int_mask) -{ - NRF_RNG->INTENSET = rng_int_mask; -} - -__STATIC_INLINE void nrf_rng_int_disable(uint32_t rng_int_mask) -{ - NRF_RNG->INTENCLR = rng_int_mask; -} - -__STATIC_INLINE bool nrf_rng_int_get(nrf_rng_int_mask_t rng_int_mask) -{ - return (bool)(NRF_RNG->INTENCLR & rng_int_mask); -} - -__STATIC_INLINE uint32_t * nrf_rng_task_address_get(nrf_rng_task_t rng_task) -{ - return (uint32_t *)((uint8_t *)NRF_RNG + rng_task); -} - -__STATIC_INLINE void nrf_rng_task_trigger(nrf_rng_task_t rng_task) -{ - *((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_task)) = NRF_RNG_TASK_SET; -} - -__STATIC_INLINE uint32_t * nrf_rng_event_address_get(nrf_rng_event_t rng_event) -{ - return (uint32_t *)((uint8_t *)NRF_RNG + rng_event); -} - -__STATIC_INLINE void nrf_rng_event_clear(nrf_rng_event_t rng_event) -{ - *((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_event)) = NRF_RNG_EVENT_CLEAR; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_event)); - (void)dummy; -#endif -} - -__STATIC_INLINE bool nrf_rng_event_get(nrf_rng_event_t rng_event) -{ - return (bool) * ((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_event)); -} - -__STATIC_INLINE void nrf_rng_shorts_enable(uint32_t rng_short_mask) -{ - NRF_RNG->SHORTS |= rng_short_mask; -} - -__STATIC_INLINE void nrf_rng_shorts_disable(uint32_t rng_short_mask) -{ - NRF_RNG->SHORTS &= ~rng_short_mask; -} - -__STATIC_INLINE uint8_t nrf_rng_random_value_get(void) -{ - return (uint8_t)(NRF_RNG->VALUE & RNG_VALUE_VALUE_Msk); -} - -__STATIC_INLINE void nrf_rng_error_correction_enable(void) -{ - NRF_RNG->CONFIG |= RNG_CONFIG_DERCEN_Msk; -} - -__STATIC_INLINE void nrf_rng_error_correction_disable(void) -{ - NRF_RNG->CONFIG &= ~RNG_CONFIG_DERCEN_Msk; -} - -#endif - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* NRF_RNG_H__ */ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_rtc.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_rtc.h deleted file mode 100644 index 3de2fad53e..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_rtc.h +++ /dev/null @@ -1,330 +0,0 @@ -/** - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_RTC_H -#define NRF_RTC_H - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_rtc_hal RTC HAL - * @{ - * @ingroup nrf_rtc - * @brief Hardware access layer for managing the Real Time Counter (RTC) peripheral. - */ - -/** - * @brief Macro for getting the number of compare channels available - * in a given RTC instance. - */ - -#define NRF_RTC_CC_CHANNEL_COUNT(id) NRFX_CONCAT_3(RTC, id, _CC_NUM) - -#define RTC_INPUT_FREQ 32768 /**< Input frequency of the RTC instance. */ - -/** - * @brief Macro for converting expected frequency to prescaler setting. - */ -#define RTC_FREQ_TO_PRESCALER(FREQ) (uint16_t)(((RTC_INPUT_FREQ) / (FREQ)) - 1) - -/**< Macro for wrapping values to RTC capacity. */ -#define RTC_WRAP(val) ((val) & RTC_COUNTER_COUNTER_Msk) - -#define RTC_CHANNEL_INT_MASK(ch) ((uint32_t)(NRF_RTC_INT_COMPARE0_MASK) << (ch)) -#define RTC_CHANNEL_EVENT_ADDR(ch) (nrf_rtc_event_t)((NRF_RTC_EVENT_COMPARE_0) + (ch) * sizeof(uint32_t)) -/** - * @enum nrf_rtc_task_t - * @brief RTC tasks. - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_RTC_TASK_START = offsetof(NRF_RTC_Type,TASKS_START), /**< Start. */ - NRF_RTC_TASK_STOP = offsetof(NRF_RTC_Type,TASKS_STOP), /**< Stop. */ - NRF_RTC_TASK_CLEAR = offsetof(NRF_RTC_Type,TASKS_CLEAR), /**< Clear. */ - NRF_RTC_TASK_TRIGGER_OVERFLOW = offsetof(NRF_RTC_Type,TASKS_TRIGOVRFLW),/**< Trigger overflow. */ - /*lint -restore*/ -} nrf_rtc_task_t; - -/** - * @enum nrf_rtc_event_t - * @brief RTC events. - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_RTC_EVENT_TICK = offsetof(NRF_RTC_Type,EVENTS_TICK), /**< Tick event. */ - NRF_RTC_EVENT_OVERFLOW = offsetof(NRF_RTC_Type,EVENTS_OVRFLW), /**< Overflow event. */ - NRF_RTC_EVENT_COMPARE_0 = offsetof(NRF_RTC_Type,EVENTS_COMPARE[0]), /**< Compare 0 event. */ - NRF_RTC_EVENT_COMPARE_1 = offsetof(NRF_RTC_Type,EVENTS_COMPARE[1]), /**< Compare 1 event. */ - NRF_RTC_EVENT_COMPARE_2 = offsetof(NRF_RTC_Type,EVENTS_COMPARE[2]), /**< Compare 2 event. */ - NRF_RTC_EVENT_COMPARE_3 = offsetof(NRF_RTC_Type,EVENTS_COMPARE[3]) /**< Compare 3 event. */ - /*lint -restore*/ -} nrf_rtc_event_t; - -/** - * @enum nrf_rtc_int_t - * @brief RTC interrupts. - */ -typedef enum -{ - NRF_RTC_INT_TICK_MASK = RTC_INTENSET_TICK_Msk, /**< RTC interrupt from tick event. */ - NRF_RTC_INT_OVERFLOW_MASK = RTC_INTENSET_OVRFLW_Msk, /**< RTC interrupt from overflow event. */ - NRF_RTC_INT_COMPARE0_MASK = RTC_INTENSET_COMPARE0_Msk, /**< RTC interrupt from compare event on channel 0. */ - NRF_RTC_INT_COMPARE1_MASK = RTC_INTENSET_COMPARE1_Msk, /**< RTC interrupt from compare event on channel 1. */ - NRF_RTC_INT_COMPARE2_MASK = RTC_INTENSET_COMPARE2_Msk, /**< RTC interrupt from compare event on channel 2. */ - NRF_RTC_INT_COMPARE3_MASK = RTC_INTENSET_COMPARE3_Msk /**< RTC interrupt from compare event on channel 3. */ -} nrf_rtc_int_t; - -/**@brief Function for setting a compare value for a channel. - * - * @param[in] p_rtc Pointer to the peripheral registers structure. - * @param[in] ch Channel. - * @param[in] cc_val Compare value to set. - */ -__STATIC_INLINE void nrf_rtc_cc_set(NRF_RTC_Type * p_rtc, uint32_t ch, uint32_t cc_val); - -/**@brief Function for returning the compare value for a channel. - * - * @param[in] p_rtc Pointer to the peripheral registers structure. - * @param[in] ch Channel. - * - * @return COMPARE[ch] value. - */ -__STATIC_INLINE uint32_t nrf_rtc_cc_get(NRF_RTC_Type * p_rtc, uint32_t ch); - -/**@brief Function for enabling interrupts. - * - * @param[in] p_rtc Pointer to the peripheral registers structure. - * @param[in] mask Interrupt mask to be enabled. - */ -__STATIC_INLINE void nrf_rtc_int_enable(NRF_RTC_Type * p_rtc, uint32_t mask); - -/**@brief Function for disabling interrupts. - * - * @param[in] p_rtc Pointer to the peripheral registers structure. - * @param[in] mask Interrupt mask to be disabled. - */ -__STATIC_INLINE void nrf_rtc_int_disable(NRF_RTC_Type * p_rtc, uint32_t mask); - -/**@brief Function for checking if interrupts are enabled. - * - * @param[in] p_rtc Pointer to the peripheral registers structure. - * @param[in] mask Mask of interrupt flags to check. - * - * @return Mask with enabled interrupts. - */ -__STATIC_INLINE uint32_t nrf_rtc_int_is_enabled(NRF_RTC_Type * p_rtc, uint32_t mask); - -/**@brief Function for returning the status of currently enabled interrupts. - * - * @param[in] p_rtc Pointer to the peripheral registers structure. - * - * @return Value in INTEN register. - */ -__STATIC_INLINE uint32_t nrf_rtc_int_get(NRF_RTC_Type * p_rtc); - -/**@brief Function for checking if an event is pending. - * - * @param[in] p_rtc Pointer to the peripheral registers structure. - * @param[in] event Address of the event. - * - * @return Mask of pending events. - */ -__STATIC_INLINE uint32_t nrf_rtc_event_pending(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event); - -/**@brief Function for clearing an event. - * - * @param[in] p_rtc Pointer to the peripheral registers structure. - * @param[in] event Event to clear. - */ -__STATIC_INLINE void nrf_rtc_event_clear(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event); - -/**@brief Function for returning a counter value. - * - * @param[in] p_rtc Pointer to the peripheral registers structure. - * - * @return Counter value. - */ -__STATIC_INLINE uint32_t nrf_rtc_counter_get(NRF_RTC_Type * p_rtc); - -/**@brief Function for setting a prescaler value. - * - * @param[in] p_rtc Pointer to the peripheral registers structure. - * @param[in] val Value to set the prescaler to. - */ -__STATIC_INLINE void nrf_rtc_prescaler_set(NRF_RTC_Type * p_rtc, uint32_t val); - -/**@brief Function for returning the address of an event. - * - * @param[in] p_rtc Pointer to the peripheral registers structure. - * @param[in] event Requested event. - * - * @return Address of the requested event register. - */ -__STATIC_INLINE uint32_t nrf_rtc_event_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event); - -/**@brief Function for returning the address of a task. - * - * @param[in] p_rtc Pointer to the peripheral registers structure. - * @param[in] task Requested task. - * - * @return Address of the requested task register. - */ -__STATIC_INLINE uint32_t nrf_rtc_task_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task); - -/**@brief Function for starting a task. - * - * @param[in] p_rtc Pointer to the peripheral registers structure. - * @param[in] task Requested task. - */ -__STATIC_INLINE void nrf_rtc_task_trigger(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task); - -/**@brief Function for enabling events. - * - * @param[in] p_rtc Pointer to the peripheral registers structure. - * @param[in] mask Mask of event flags to enable. - */ -__STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_rtc, uint32_t mask); - -/**@brief Function for disabling an event. - * - * @param[in] p_rtc Pointer to the peripheral registers structure. - * @param[in] event Requested event. - */ -__STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_rtc, uint32_t event); - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -__STATIC_INLINE void nrf_rtc_cc_set(NRF_RTC_Type * p_rtc, uint32_t ch, uint32_t cc_val) -{ - p_rtc->CC[ch] = cc_val; -} - -__STATIC_INLINE uint32_t nrf_rtc_cc_get(NRF_RTC_Type * p_rtc, uint32_t ch) -{ - return p_rtc->CC[ch]; -} - -__STATIC_INLINE void nrf_rtc_int_enable(NRF_RTC_Type * p_rtc, uint32_t mask) -{ - p_rtc->INTENSET = mask; -} - -__STATIC_INLINE void nrf_rtc_int_disable(NRF_RTC_Type * p_rtc, uint32_t mask) -{ - p_rtc->INTENCLR = mask; -} - -__STATIC_INLINE uint32_t nrf_rtc_int_is_enabled(NRF_RTC_Type * p_rtc, uint32_t mask) -{ - return (p_rtc->INTENSET & mask); -} - -__STATIC_INLINE uint32_t nrf_rtc_int_get(NRF_RTC_Type * p_rtc) -{ - return p_rtc->INTENSET; -} - -__STATIC_INLINE uint32_t nrf_rtc_event_pending(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event) -{ - return *(volatile uint32_t *)((uint8_t *)p_rtc + (uint32_t)event); -} - -__STATIC_INLINE void nrf_rtc_event_clear(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event) -{ - *((volatile uint32_t *)((uint8_t *)p_rtc + (uint32_t)event)) = 0; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_rtc + (uint32_t)event)); - (void)dummy; -#endif -} - -__STATIC_INLINE uint32_t nrf_rtc_counter_get(NRF_RTC_Type * p_rtc) -{ - return p_rtc->COUNTER; -} - -__STATIC_INLINE void nrf_rtc_prescaler_set(NRF_RTC_Type * p_rtc, uint32_t val) -{ - NRFX_ASSERT(val <= (RTC_PRESCALER_PRESCALER_Msk >> RTC_PRESCALER_PRESCALER_Pos)); - p_rtc->PRESCALER = val; -} -__STATIC_INLINE uint32_t rtc_prescaler_get(NRF_RTC_Type * p_rtc) -{ - return p_rtc->PRESCALER; -} - -__STATIC_INLINE uint32_t nrf_rtc_event_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event) -{ - return (uint32_t)p_rtc + event; -} - -__STATIC_INLINE uint32_t nrf_rtc_task_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task) -{ - return (uint32_t)p_rtc + task; -} - -__STATIC_INLINE void nrf_rtc_task_trigger(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task) -{ - *(__IO uint32_t *)((uint32_t)p_rtc + task) = 1; -} - -__STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_rtc, uint32_t mask) -{ - p_rtc->EVTENSET = mask; -} -__STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_rtc, uint32_t mask) -{ - p_rtc->EVTENCLR = mask; -} -#endif - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* NRF_RTC_H */ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_saadc.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_saadc.h deleted file mode 100644 index e9115d2db3..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_saadc.h +++ /dev/null @@ -1,615 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_SAADC_H_ -#define NRF_SAADC_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_saadc_hal SAADC HAL - * @{ - * @ingroup nrf_saadc - * @brief Hardware access layer for managing the SAADC peripheral. - */ - -#define NRF_SAADC_CHANNEL_COUNT 8 - -/** - * @brief Resolution of the analog-to-digital converter. - */ -typedef enum -{ - NRF_SAADC_RESOLUTION_8BIT = SAADC_RESOLUTION_VAL_8bit, ///< 8 bit resolution. - NRF_SAADC_RESOLUTION_10BIT = SAADC_RESOLUTION_VAL_10bit, ///< 10 bit resolution. - NRF_SAADC_RESOLUTION_12BIT = SAADC_RESOLUTION_VAL_12bit, ///< 12 bit resolution. - NRF_SAADC_RESOLUTION_14BIT = SAADC_RESOLUTION_VAL_14bit ///< 14 bit resolution. -} nrf_saadc_resolution_t; - - -/** - * @brief Input selection for the analog-to-digital converter. - */ -typedef enum -{ - NRF_SAADC_INPUT_DISABLED = SAADC_CH_PSELP_PSELP_NC, ///< Not connected. - NRF_SAADC_INPUT_AIN0 = SAADC_CH_PSELP_PSELP_AnalogInput0, ///< Analog input 0 (AIN0). - NRF_SAADC_INPUT_AIN1 = SAADC_CH_PSELP_PSELP_AnalogInput1, ///< Analog input 1 (AIN1). - NRF_SAADC_INPUT_AIN2 = SAADC_CH_PSELP_PSELP_AnalogInput2, ///< Analog input 2 (AIN2). - NRF_SAADC_INPUT_AIN3 = SAADC_CH_PSELP_PSELP_AnalogInput3, ///< Analog input 3 (AIN3). - NRF_SAADC_INPUT_AIN4 = SAADC_CH_PSELP_PSELP_AnalogInput4, ///< Analog input 4 (AIN4). - NRF_SAADC_INPUT_AIN5 = SAADC_CH_PSELP_PSELP_AnalogInput5, ///< Analog input 5 (AIN5). - NRF_SAADC_INPUT_AIN6 = SAADC_CH_PSELP_PSELP_AnalogInput6, ///< Analog input 6 (AIN6). - NRF_SAADC_INPUT_AIN7 = SAADC_CH_PSELP_PSELP_AnalogInput7, ///< Analog input 7 (AIN7). - NRF_SAADC_INPUT_VDD = SAADC_CH_PSELP_PSELP_VDD ///< VDD as input. -} nrf_saadc_input_t; - - -/** - * @brief Analog-to-digital converter oversampling mode. - */ -typedef enum -{ - NRF_SAADC_OVERSAMPLE_DISABLED = SAADC_OVERSAMPLE_OVERSAMPLE_Bypass, ///< No oversampling. - NRF_SAADC_OVERSAMPLE_2X = SAADC_OVERSAMPLE_OVERSAMPLE_Over2x, ///< Oversample 2x. - NRF_SAADC_OVERSAMPLE_4X = SAADC_OVERSAMPLE_OVERSAMPLE_Over4x, ///< Oversample 4x. - NRF_SAADC_OVERSAMPLE_8X = SAADC_OVERSAMPLE_OVERSAMPLE_Over8x, ///< Oversample 8x. - NRF_SAADC_OVERSAMPLE_16X = SAADC_OVERSAMPLE_OVERSAMPLE_Over16x, ///< Oversample 16x. - NRF_SAADC_OVERSAMPLE_32X = SAADC_OVERSAMPLE_OVERSAMPLE_Over32x, ///< Oversample 32x. - NRF_SAADC_OVERSAMPLE_64X = SAADC_OVERSAMPLE_OVERSAMPLE_Over64x, ///< Oversample 64x. - NRF_SAADC_OVERSAMPLE_128X = SAADC_OVERSAMPLE_OVERSAMPLE_Over128x, ///< Oversample 128x. - NRF_SAADC_OVERSAMPLE_256X = SAADC_OVERSAMPLE_OVERSAMPLE_Over256x ///< Oversample 256x. -} nrf_saadc_oversample_t; - - -/** - * @brief Analog-to-digital converter channel resistor control. - */ -typedef enum -{ - NRF_SAADC_RESISTOR_DISABLED = SAADC_CH_CONFIG_RESP_Bypass, ///< Bypass resistor ladder. - NRF_SAADC_RESISTOR_PULLDOWN = SAADC_CH_CONFIG_RESP_Pulldown, ///< Pull-down to GND. - NRF_SAADC_RESISTOR_PULLUP = SAADC_CH_CONFIG_RESP_Pullup, ///< Pull-up to VDD. - NRF_SAADC_RESISTOR_VDD1_2 = SAADC_CH_CONFIG_RESP_VDD1_2 ///< Set input at VDD/2. -} nrf_saadc_resistor_t; - - -/** - * @brief Gain factor of the analog-to-digital converter input. - */ -typedef enum -{ - NRF_SAADC_GAIN1_6 = SAADC_CH_CONFIG_GAIN_Gain1_6, ///< Gain factor 1/6. - NRF_SAADC_GAIN1_5 = SAADC_CH_CONFIG_GAIN_Gain1_5, ///< Gain factor 1/5. - NRF_SAADC_GAIN1_4 = SAADC_CH_CONFIG_GAIN_Gain1_4, ///< Gain factor 1/4. - NRF_SAADC_GAIN1_3 = SAADC_CH_CONFIG_GAIN_Gain1_3, ///< Gain factor 1/3. - NRF_SAADC_GAIN1_2 = SAADC_CH_CONFIG_GAIN_Gain1_2, ///< Gain factor 1/2. - NRF_SAADC_GAIN1 = SAADC_CH_CONFIG_GAIN_Gain1, ///< Gain factor 1. - NRF_SAADC_GAIN2 = SAADC_CH_CONFIG_GAIN_Gain2, ///< Gain factor 2. - NRF_SAADC_GAIN4 = SAADC_CH_CONFIG_GAIN_Gain4, ///< Gain factor 4. -} nrf_saadc_gain_t; - - -/** - * @brief Reference selection for the analog-to-digital converter. - */ -typedef enum -{ - NRF_SAADC_REFERENCE_INTERNAL = SAADC_CH_CONFIG_REFSEL_Internal, ///< Internal reference (0.6 V). - NRF_SAADC_REFERENCE_VDD4 = SAADC_CH_CONFIG_REFSEL_VDD1_4 ///< VDD/4 as reference. -} nrf_saadc_reference_t; - - -/** - * @brief Analog-to-digital converter acquisition time. - */ -typedef enum -{ - NRF_SAADC_ACQTIME_3US = SAADC_CH_CONFIG_TACQ_3us, ///< 3 us. - NRF_SAADC_ACQTIME_5US = SAADC_CH_CONFIG_TACQ_5us, ///< 5 us. - NRF_SAADC_ACQTIME_10US = SAADC_CH_CONFIG_TACQ_10us, ///< 10 us. - NRF_SAADC_ACQTIME_15US = SAADC_CH_CONFIG_TACQ_15us, ///< 15 us. - NRF_SAADC_ACQTIME_20US = SAADC_CH_CONFIG_TACQ_20us, ///< 20 us. - NRF_SAADC_ACQTIME_40US = SAADC_CH_CONFIG_TACQ_40us ///< 40 us. -} nrf_saadc_acqtime_t; - - -/** - * @brief Analog-to-digital converter channel mode. - */ -typedef enum -{ - NRF_SAADC_MODE_SINGLE_ENDED = SAADC_CH_CONFIG_MODE_SE, ///< Single ended, PSELN will be ignored, negative input to ADC shorted to GND. - NRF_SAADC_MODE_DIFFERENTIAL = SAADC_CH_CONFIG_MODE_Diff ///< Differential mode. -} nrf_saadc_mode_t; - - -/** - * @brief Analog-to-digital converter channel burst mode. - */ -typedef enum -{ - NRF_SAADC_BURST_DISABLED = SAADC_CH_CONFIG_BURST_Disabled, ///< Burst mode is disabled (normal operation). - NRF_SAADC_BURST_ENABLED = SAADC_CH_CONFIG_BURST_Enabled ///< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. -} nrf_saadc_burst_t; - - -/** - * @brief Analog-to-digital converter tasks. - */ -typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ -{ - NRF_SAADC_TASK_START = offsetof(NRF_SAADC_Type, TASKS_START), ///< Start the ADC and prepare the result buffer in RAM. - NRF_SAADC_TASK_SAMPLE = offsetof(NRF_SAADC_Type, TASKS_SAMPLE), ///< Take one ADC sample. If scan is enabled, all channels are sampled. - NRF_SAADC_TASK_STOP = offsetof(NRF_SAADC_Type, TASKS_STOP), ///< Stop the ADC and terminate any on-going conversion. - NRF_SAADC_TASK_CALIBRATEOFFSET = offsetof(NRF_SAADC_Type, TASKS_CALIBRATEOFFSET), ///< Starts offset auto-calibration. -} nrf_saadc_task_t; - - -/** - * @brief Analog-to-digital converter events. - */ -typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ -{ - NRF_SAADC_EVENT_STARTED = offsetof(NRF_SAADC_Type, EVENTS_STARTED), ///< The ADC has started. - NRF_SAADC_EVENT_END = offsetof(NRF_SAADC_Type, EVENTS_END), ///< The ADC has filled up the result buffer. - NRF_SAADC_EVENT_DONE = offsetof(NRF_SAADC_Type, EVENTS_DONE), ///< A conversion task has been completed. - NRF_SAADC_EVENT_RESULTDONE = offsetof(NRF_SAADC_Type, EVENTS_RESULTDONE), ///< A result is ready to get transferred to RAM. - NRF_SAADC_EVENT_CALIBRATEDONE = offsetof(NRF_SAADC_Type, EVENTS_CALIBRATEDONE), ///< Calibration is complete. - NRF_SAADC_EVENT_STOPPED = offsetof(NRF_SAADC_Type, EVENTS_STOPPED), ///< The ADC has stopped. - NRF_SAADC_EVENT_CH0_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[0].LIMITH), ///< Last result is equal or above CH[0].LIMIT.HIGH. - NRF_SAADC_EVENT_CH0_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[0].LIMITL), ///< Last result is equal or below CH[0].LIMIT.LOW. - NRF_SAADC_EVENT_CH1_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[1].LIMITH), ///< Last result is equal or above CH[1].LIMIT.HIGH. - NRF_SAADC_EVENT_CH1_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[1].LIMITL), ///< Last result is equal or below CH[1].LIMIT.LOW. - NRF_SAADC_EVENT_CH2_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[2].LIMITH), ///< Last result is equal or above CH[2].LIMIT.HIGH. - NRF_SAADC_EVENT_CH2_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[2].LIMITL), ///< Last result is equal or below CH[2].LIMIT.LOW. - NRF_SAADC_EVENT_CH3_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[3].LIMITH), ///< Last result is equal or above CH[3].LIMIT.HIGH. - NRF_SAADC_EVENT_CH3_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[3].LIMITL), ///< Last result is equal or below CH[3].LIMIT.LOW. - NRF_SAADC_EVENT_CH4_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[4].LIMITH), ///< Last result is equal or above CH[4].LIMIT.HIGH. - NRF_SAADC_EVENT_CH4_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[4].LIMITL), ///< Last result is equal or below CH[4].LIMIT.LOW. - NRF_SAADC_EVENT_CH5_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[5].LIMITH), ///< Last result is equal or above CH[5].LIMIT.HIGH. - NRF_SAADC_EVENT_CH5_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[5].LIMITL), ///< Last result is equal or below CH[5].LIMIT.LOW. - NRF_SAADC_EVENT_CH6_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[6].LIMITH), ///< Last result is equal or above CH[6].LIMIT.HIGH. - NRF_SAADC_EVENT_CH6_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[6].LIMITL), ///< Last result is equal or below CH[6].LIMIT.LOW. - NRF_SAADC_EVENT_CH7_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[7].LIMITH), ///< Last result is equal or above CH[7].LIMIT.HIGH. - NRF_SAADC_EVENT_CH7_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[7].LIMITL) ///< Last result is equal or below CH[7].LIMIT.LOW. -} nrf_saadc_event_t; - - -/** - * @brief Analog-to-digital converter interrupt masks. - */ -typedef enum -{ - NRF_SAADC_INT_STARTED = SAADC_INTENSET_STARTED_Msk, ///< Interrupt on EVENTS_STARTED event. - NRF_SAADC_INT_END = SAADC_INTENSET_END_Msk, ///< Interrupt on EVENTS_END event. - NRF_SAADC_INT_DONE = SAADC_INTENSET_DONE_Msk, ///< Interrupt on EVENTS_DONE event. - NRF_SAADC_INT_RESULTDONE = SAADC_INTENSET_RESULTDONE_Msk, ///< Interrupt on EVENTS_RESULTDONE event. - NRF_SAADC_INT_CALIBRATEDONE = SAADC_INTENSET_CALIBRATEDONE_Msk, ///< Interrupt on EVENTS_CALIBRATEDONE event. - NRF_SAADC_INT_STOPPED = SAADC_INTENSET_STOPPED_Msk, ///< Interrupt on EVENTS_STOPPED event. - NRF_SAADC_INT_CH0LIMITH = SAADC_INTENSET_CH0LIMITH_Msk, ///< Interrupt on EVENTS_CH[0].LIMITH event. - NRF_SAADC_INT_CH0LIMITL = SAADC_INTENSET_CH0LIMITL_Msk, ///< Interrupt on EVENTS_CH[0].LIMITL event. - NRF_SAADC_INT_CH1LIMITH = SAADC_INTENSET_CH1LIMITH_Msk, ///< Interrupt on EVENTS_CH[1].LIMITH event. - NRF_SAADC_INT_CH1LIMITL = SAADC_INTENSET_CH1LIMITL_Msk, ///< Interrupt on EVENTS_CH[1].LIMITL event. - NRF_SAADC_INT_CH2LIMITH = SAADC_INTENSET_CH2LIMITH_Msk, ///< Interrupt on EVENTS_CH[2].LIMITH event. - NRF_SAADC_INT_CH2LIMITL = SAADC_INTENSET_CH2LIMITL_Msk, ///< Interrupt on EVENTS_CH[2].LIMITL event. - NRF_SAADC_INT_CH3LIMITH = SAADC_INTENSET_CH3LIMITH_Msk, ///< Interrupt on EVENTS_CH[3].LIMITH event. - NRF_SAADC_INT_CH3LIMITL = SAADC_INTENSET_CH3LIMITL_Msk, ///< Interrupt on EVENTS_CH[3].LIMITL event. - NRF_SAADC_INT_CH4LIMITH = SAADC_INTENSET_CH4LIMITH_Msk, ///< Interrupt on EVENTS_CH[4].LIMITH event. - NRF_SAADC_INT_CH4LIMITL = SAADC_INTENSET_CH4LIMITL_Msk, ///< Interrupt on EVENTS_CH[4].LIMITL event. - NRF_SAADC_INT_CH5LIMITH = SAADC_INTENSET_CH5LIMITH_Msk, ///< Interrupt on EVENTS_CH[5].LIMITH event. - NRF_SAADC_INT_CH5LIMITL = SAADC_INTENSET_CH5LIMITL_Msk, ///< Interrupt on EVENTS_CH[5].LIMITL event. - NRF_SAADC_INT_CH6LIMITH = SAADC_INTENSET_CH6LIMITH_Msk, ///< Interrupt on EVENTS_CH[6].LIMITH event. - NRF_SAADC_INT_CH6LIMITL = SAADC_INTENSET_CH6LIMITL_Msk, ///< Interrupt on EVENTS_CH[6].LIMITL event. - NRF_SAADC_INT_CH7LIMITH = SAADC_INTENSET_CH7LIMITH_Msk, ///< Interrupt on EVENTS_CH[7].LIMITH event. - NRF_SAADC_INT_CH7LIMITL = SAADC_INTENSET_CH7LIMITL_Msk, ///< Interrupt on EVENTS_CH[7].LIMITL event. - NRF_SAADC_INT_ALL = 0x7FFFFFFFUL ///< Mask of all interrupts. -} nrf_saadc_int_mask_t; - - -/** - * @brief Analog-to-digital converter value limit type. - */ -typedef enum -{ - NRF_SAADC_LIMIT_LOW = 0, - NRF_SAADC_LIMIT_HIGH = 1 -} nrf_saadc_limit_t; - - -typedef int16_t nrf_saadc_value_t; ///< Type of a single ADC conversion result. - - -/** - * @brief Analog-to-digital converter configuration structure. - */ -typedef struct -{ - nrf_saadc_resolution_t resolution; - nrf_saadc_oversample_t oversample; - nrf_saadc_value_t * buffer; - uint32_t buffer_size; -} nrf_saadc_config_t; - - -/** - * @brief Analog-to-digital converter channel configuration structure. - */ -typedef struct -{ - nrf_saadc_resistor_t resistor_p; - nrf_saadc_resistor_t resistor_n; - nrf_saadc_gain_t gain; - nrf_saadc_reference_t reference; - nrf_saadc_acqtime_t acq_time; - nrf_saadc_mode_t mode; - nrf_saadc_burst_t burst; - nrf_saadc_input_t pin_p; - nrf_saadc_input_t pin_n; -} nrf_saadc_channel_config_t; - - -/** - * @brief Function for triggering a specific SAADC task. - * - * @param[in] saadc_task SAADC task. - */ -__STATIC_INLINE void nrf_saadc_task_trigger(nrf_saadc_task_t saadc_task) -{ - *((volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_task)) = 0x1UL; -} - - -/** - * @brief Function for getting the address of a specific SAADC task register. - * - * @param[in] saadc_task SAADC task. - * - * @return Address of the specified SAADC task. - */ -__STATIC_INLINE uint32_t nrf_saadc_task_address_get(nrf_saadc_task_t saadc_task) -{ - return (uint32_t)((uint8_t *)NRF_SAADC + (uint32_t)saadc_task); -} - - -/** - * @brief Function for getting the state of a specific SAADC event. - * - * @param[in] saadc_event SAADC event. - * - * @return State of the specified SAADC event. - */ -__STATIC_INLINE bool nrf_saadc_event_check(nrf_saadc_event_t saadc_event) -{ - return (bool)*(volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_event); -} - - -/** - * @brief Function for clearing the specific SAADC event. - * - * @param[in] saadc_event SAADC event. - */ -__STATIC_INLINE void nrf_saadc_event_clear(nrf_saadc_event_t saadc_event) -{ - *((volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_event)); - (void)dummy; -#endif -} - - -/** - * @brief Function for getting the address of a specific SAADC event register. - * - * @param[in] saadc_event SAADC event. - * - * @return Address of the specified SAADC event. - */ -__STATIC_INLINE uint32_t nrf_saadc_event_address_get(nrf_saadc_event_t saadc_event) -{ - return (uint32_t )((uint8_t *)NRF_SAADC + (uint32_t)saadc_event); -} - - -/** - * @brief Function for getting the address of a specific SAADC limit event register. - * - * @param[in] channel Channel number. - * @param[in] limit_type Low limit or high limit. - * - * @return Address of the specified SAADC limit event. - */ -__STATIC_INLINE volatile uint32_t * nrf_saadc_event_limit_address_get(uint8_t channel, nrf_saadc_limit_t limit_type) -{ - NRFX_ASSERT(channel < NRF_SAADC_CHANNEL_COUNT); - if (limit_type == NRF_SAADC_LIMIT_HIGH) - { - return &NRF_SAADC->EVENTS_CH[channel].LIMITH; - } - else - { - return &NRF_SAADC->EVENTS_CH[channel].LIMITL; - } -} - - -/** - * @brief Function for getting the SAADC channel monitoring limit events. - * - * @param[in] channel Channel number. - * @param[in] limit_type Low limit or high limit. - */ -__STATIC_INLINE nrf_saadc_event_t nrf_saadc_event_limit_get(uint8_t channel, nrf_saadc_limit_t limit_type) -{ - if (limit_type == NRF_SAADC_LIMIT_HIGH) - { - return (nrf_saadc_event_t)( (uint32_t) NRF_SAADC_EVENT_CH0_LIMITH + - (uint32_t) (NRF_SAADC_EVENT_CH1_LIMITH - NRF_SAADC_EVENT_CH0_LIMITH) - * (uint32_t) channel ); - } - else - { - return (nrf_saadc_event_t)( (uint32_t) NRF_SAADC_EVENT_CH0_LIMITL + - (uint32_t) (NRF_SAADC_EVENT_CH1_LIMITL - NRF_SAADC_EVENT_CH0_LIMITL) - * (uint32_t) channel ); - } -} - - -/** - * @brief Function for configuring the input pins for a specific SAADC channel. - * - * @param[in] channel Channel number. - * @param[in] pselp Positive input. - * @param[in] pseln Negative input. Set to NRF_SAADC_INPUT_DISABLED in single ended mode. - */ -__STATIC_INLINE void nrf_saadc_channel_input_set(uint8_t channel, - nrf_saadc_input_t pselp, - nrf_saadc_input_t pseln) -{ - NRF_SAADC->CH[channel].PSELN = pseln; - NRF_SAADC->CH[channel].PSELP = pselp; -} - - -/** - * @brief Function for setting the SAADC channel monitoring limits. - * - * @param[in] channel Channel number. - * @param[in] low Low limit. - * @param[in] high High limit. - */ -__STATIC_INLINE void nrf_saadc_channel_limits_set(uint8_t channel, int16_t low, int16_t high) -{ - NRF_SAADC->CH[channel].LIMIT = ( - (((uint32_t) low << SAADC_CH_LIMIT_LOW_Pos) & SAADC_CH_LIMIT_LOW_Msk) - | (((uint32_t) high << SAADC_CH_LIMIT_HIGH_Pos) & SAADC_CH_LIMIT_HIGH_Msk)); -} - - -/** - * @brief Function for enabling specified SAADC interrupts. - * - * @param[in] saadc_int_mask Interrupt(s) to enable. - */ -__STATIC_INLINE void nrf_saadc_int_enable(uint32_t saadc_int_mask) -{ - NRF_SAADC->INTENSET = saadc_int_mask; -} - - -/** - * @brief Function for retrieving the state of specified SAADC interrupts. - * - * @param[in] saadc_int_mask Interrupt(s) to check. - * - * @retval true If all specified interrupts are enabled. - * @retval false If at least one of the given interrupts is not enabled. - */ -__STATIC_INLINE bool nrf_saadc_int_enable_check(uint32_t saadc_int_mask) -{ - return (bool)(NRF_SAADC->INTENSET & saadc_int_mask); -} - - -/** - * @brief Function for disabling specified interrupts. - * - * @param saadc_int_mask Interrupt(s) to disable. - */ -__STATIC_INLINE void nrf_saadc_int_disable(uint32_t saadc_int_mask) -{ - NRF_SAADC->INTENCLR = saadc_int_mask; -} - - -/** - * @brief Function for generating masks for SAADC channel limit interrupts. - * - * @param[in] channel SAADC channel number. - * @param[in] limit_type Limit type. - * - * @returns Interrupt mask. - */ -__STATIC_INLINE uint32_t nrf_saadc_limit_int_get(uint8_t channel, nrf_saadc_limit_t limit_type) -{ - NRFX_ASSERT(channel < NRF_SAADC_CHANNEL_COUNT); - uint32_t mask = (limit_type == NRF_SAADC_LIMIT_LOW) ? NRF_SAADC_INT_CH0LIMITL : NRF_SAADC_INT_CH0LIMITH; - return mask << (channel * 2); -} - - -/** - * @brief Function for checking whether the SAADC is busy. - * - * This function checks whether the analog-to-digital converter is busy with a conversion. - * - * @retval true If the SAADC is busy. - * @retval false If the SAADC is not busy. - */ -__STATIC_INLINE bool nrf_saadc_busy_check(void) -{ - //return ((NRF_SAADC->STATUS & SAADC_STATUS_STATUS_Msk) == SAADC_STATUS_STATUS_Msk); - //simplified for performance - return NRF_SAADC->STATUS; -} - - -/** - * @brief Function for enabling the SAADC. - * - * The analog-to-digital converter must be enabled before use. - */ -__STATIC_INLINE void nrf_saadc_enable(void) -{ - NRF_SAADC->ENABLE = (SAADC_ENABLE_ENABLE_Enabled << SAADC_ENABLE_ENABLE_Pos); -} - - -/** - * @brief Function for disabling the SAADC. - */ -__STATIC_INLINE void nrf_saadc_disable(void) -{ - NRF_SAADC->ENABLE = (SAADC_ENABLE_ENABLE_Disabled << SAADC_ENABLE_ENABLE_Pos); -} - - -/** - * @brief Function for checking if the SAADC is enabled. - * - * @retval true If the SAADC is enabled. - * @retval false If the SAADC is not enabled. - */ -__STATIC_INLINE bool nrf_saadc_enable_check(void) -{ - //simplified for performance - return NRF_SAADC->ENABLE; -} - - -/** - * @brief Function for initializing the SAADC result buffer. - * - * @param[in] buffer Pointer to the result buffer. - * @param[in] num Size of buffer in words. - */ -__STATIC_INLINE void nrf_saadc_buffer_init(nrf_saadc_value_t * buffer, uint32_t num) -{ - NRF_SAADC->RESULT.PTR = (uint32_t)buffer; - NRF_SAADC->RESULT.MAXCNT = num; -} - -/** - * @brief Function for getting the number of buffer words transferred since last START operation. - * - * @returns Number of words transferred. - */ -__STATIC_INLINE uint16_t nrf_saadc_amount_get(void) -{ - return NRF_SAADC->RESULT.AMOUNT; -} - - -/** - * @brief Function for setting the SAADC sample resolution. - * - * @param[in] resolution Bit resolution. - */ -__STATIC_INLINE void nrf_saadc_resolution_set(nrf_saadc_resolution_t resolution) -{ - NRF_SAADC->RESOLUTION = resolution; -} - - -/** - * @brief Function for configuring the oversampling feature. - * - * @param[in] oversample Oversampling mode. - */ -__STATIC_INLINE void nrf_saadc_oversample_set(nrf_saadc_oversample_t oversample) -{ - NRF_SAADC->OVERSAMPLE = oversample; -} - -/** - * @brief Function for getting the oversampling feature configuration. - * - * @return Oversampling configuration. - */ -__STATIC_INLINE nrf_saadc_oversample_t nrf_saadc_oversample_get(void) -{ - return (nrf_saadc_oversample_t)NRF_SAADC->OVERSAMPLE; -} - -/** - * @brief Function for initializing the SAADC channel. - * - * @param[in] channel Channel number. - * @param[in] config Pointer to the channel configuration structure. - */ -__STATIC_INLINE void nrf_saadc_channel_init(uint8_t channel, - nrf_saadc_channel_config_t const * const config) -{ - NRF_SAADC->CH[channel].CONFIG = - ((config->resistor_p << SAADC_CH_CONFIG_RESP_Pos) & SAADC_CH_CONFIG_RESP_Msk) - | ((config->resistor_n << SAADC_CH_CONFIG_RESN_Pos) & SAADC_CH_CONFIG_RESN_Msk) - | ((config->gain << SAADC_CH_CONFIG_GAIN_Pos) & SAADC_CH_CONFIG_GAIN_Msk) - | ((config->reference << SAADC_CH_CONFIG_REFSEL_Pos) & SAADC_CH_CONFIG_REFSEL_Msk) - | ((config->acq_time << SAADC_CH_CONFIG_TACQ_Pos) & SAADC_CH_CONFIG_TACQ_Msk) - | ((config->mode << SAADC_CH_CONFIG_MODE_Pos) & SAADC_CH_CONFIG_MODE_Msk) - | ((config->burst << SAADC_CH_CONFIG_BURST_Pos) & SAADC_CH_CONFIG_BURST_Msk); - nrf_saadc_channel_input_set(channel, config->pin_p, config->pin_n); -} - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* NRF_SAADC_H_ */ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_spi.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_spi.h deleted file mode 100644 index 5455e59ab2..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_spi.h +++ /dev/null @@ -1,369 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_SPI_H__ -#define NRF_SPI_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_spi_hal SPI HAL - * @{ - * @ingroup nrf_spi - * @brief Hardware access layer for managing the SPI peripheral. - */ - -/** - * @brief This value can be used as a parameter for the @ref nrf_spi_pins_set - * function to specify that a given SPI signal (SCK, MOSI, or MISO) - * shall not be connected to a physical pin. - */ -#define NRF_SPI_PIN_NOT_CONNECTED 0xFFFFFFFF - - -/** - * @brief SPI events. - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_SPI_EVENT_READY = offsetof(NRF_SPI_Type, EVENTS_READY) ///< TXD byte sent and RXD byte received. - /*lint -restore*/ -} nrf_spi_event_t; - -/** - * @brief SPI interrupts. - */ -typedef enum -{ - NRF_SPI_INT_READY_MASK = SPI_INTENSET_READY_Msk, ///< Interrupt on READY event. - NRF_SPI_ALL_INTS_MASK = SPI_INTENSET_READY_Msk ///< All SPI interrupts. -} nrf_spi_int_mask_t; - -/** - * @brief SPI data rates. - */ -typedef enum -{ - NRF_SPI_FREQ_125K = SPI_FREQUENCY_FREQUENCY_K125, ///< 125 kbps. - NRF_SPI_FREQ_250K = SPI_FREQUENCY_FREQUENCY_K250, ///< 250 kbps. - NRF_SPI_FREQ_500K = SPI_FREQUENCY_FREQUENCY_K500, ///< 500 kbps. - NRF_SPI_FREQ_1M = SPI_FREQUENCY_FREQUENCY_M1, ///< 1 Mbps. - NRF_SPI_FREQ_2M = SPI_FREQUENCY_FREQUENCY_M2, ///< 2 Mbps. - NRF_SPI_FREQ_4M = SPI_FREQUENCY_FREQUENCY_M4, ///< 4 Mbps. - // [conversion to 'int' needed to prevent compilers from complaining - // that the provided value (0x80000000UL) is out of range of "int"] - NRF_SPI_FREQ_8M = (int)SPI_FREQUENCY_FREQUENCY_M8 ///< 8 Mbps. -} nrf_spi_frequency_t; - -/** - * @brief SPI modes. - */ -typedef enum -{ - NRF_SPI_MODE_0, ///< SCK active high, sample on leading edge of clock. - NRF_SPI_MODE_1, ///< SCK active high, sample on trailing edge of clock. - NRF_SPI_MODE_2, ///< SCK active low, sample on leading edge of clock. - NRF_SPI_MODE_3 ///< SCK active low, sample on trailing edge of clock. -} nrf_spi_mode_t; - -/** - * @brief SPI bit orders. - */ -typedef enum -{ - NRF_SPI_BIT_ORDER_MSB_FIRST = SPI_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first. - NRF_SPI_BIT_ORDER_LSB_FIRST = SPI_CONFIG_ORDER_LsbFirst ///< Least significant bit shifted out first. -} nrf_spi_bit_order_t; - - -/** - * @brief Function for clearing a specific SPI event. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spi_event Event to clear. - */ -__STATIC_INLINE void nrf_spi_event_clear(NRF_SPI_Type * p_reg, - nrf_spi_event_t spi_event); - -/** - * @brief Function for checking the state of a specific SPI event. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spi_event Event to check. - * - * @retval true If the event is set. - * @retval false If the event is not set. - */ -__STATIC_INLINE bool nrf_spi_event_check(NRF_SPI_Type * p_reg, - nrf_spi_event_t spi_event); - -/** - * @brief Function for getting the address of a specific SPI event register. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spi_event Requested event. - * - * @return Address of the specified event register. - */ -__STATIC_INLINE uint32_t * nrf_spi_event_address_get(NRF_SPI_Type * p_reg, - nrf_spi_event_t spi_event); - -/** - * @brief Function for enabling specified interrupts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spi_int_mask Interrupts to enable. - */ -__STATIC_INLINE void nrf_spi_int_enable(NRF_SPI_Type * p_reg, - uint32_t spi_int_mask); - -/** - * @brief Function for disabling specified interrupts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spi_int_mask Interrupts to disable. - */ -__STATIC_INLINE void nrf_spi_int_disable(NRF_SPI_Type * p_reg, - uint32_t spi_int_mask); - -/** - * @brief Function for retrieving the state of a given interrupt. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spi_int Interrupt to check. - * - * @retval true If the interrupt is enabled. - * @retval false If the interrupt is not enabled. - */ -__STATIC_INLINE bool nrf_spi_int_enable_check(NRF_SPI_Type * p_reg, - nrf_spi_int_mask_t spi_int); - -/** - * @brief Function for enabling the SPI peripheral. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_spi_enable(NRF_SPI_Type * p_reg); - -/** - * @brief Function for disabling the SPI peripheral. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_spi_disable(NRF_SPI_Type * p_reg); - -/** - * @brief Function for configuring SPI pins. - * - * If a given signal is not needed, pass the @ref NRF_SPI_PIN_NOT_CONNECTED - * value instead of its pin number. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] sck_pin SCK pin number. - * @param[in] mosi_pin MOSI pin number. - * @param[in] miso_pin MISO pin number. - */ -__STATIC_INLINE void nrf_spi_pins_set(NRF_SPI_Type * p_reg, - uint32_t sck_pin, - uint32_t mosi_pin, - uint32_t miso_pin); - -/** - * @brief Function for writing data to the SPI transmitter register. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] data TX data to send. - */ -__STATIC_INLINE void nrf_spi_txd_set(NRF_SPI_Type * p_reg, uint8_t data); - -/** - * @brief Function for reading data from the SPI receiver register. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * - * @return RX data received. - */ -__STATIC_INLINE uint8_t nrf_spi_rxd_get(NRF_SPI_Type * p_reg); - -/** - * @brief Function for setting the SPI master data rate. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] frequency SPI frequency. - */ -__STATIC_INLINE void nrf_spi_frequency_set(NRF_SPI_Type * p_reg, - nrf_spi_frequency_t frequency); - -/** - * @brief Function for setting the SPI configuration. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spi_mode SPI mode. - * @param[in] spi_bit_order SPI bit order. - */ -__STATIC_INLINE void nrf_spi_configure(NRF_SPI_Type * p_reg, - nrf_spi_mode_t spi_mode, - nrf_spi_bit_order_t spi_bit_order); - - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -__STATIC_INLINE void nrf_spi_event_clear(NRF_SPI_Type * p_reg, - nrf_spi_event_t spi_event) -{ - *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spi_event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spi_event)); - (void)dummy; -#endif -} - -__STATIC_INLINE bool nrf_spi_event_check(NRF_SPI_Type * p_reg, - nrf_spi_event_t spi_event) -{ - return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spi_event); -} - -__STATIC_INLINE uint32_t * nrf_spi_event_address_get(NRF_SPI_Type * p_reg, - nrf_spi_event_t spi_event) -{ - return (uint32_t *)((uint8_t *)p_reg + (uint32_t)spi_event); -} - -__STATIC_INLINE void nrf_spi_int_enable(NRF_SPI_Type * p_reg, - uint32_t spi_int_mask) -{ - p_reg->INTENSET = spi_int_mask; -} - -__STATIC_INLINE void nrf_spi_int_disable(NRF_SPI_Type * p_reg, - uint32_t spi_int_mask) -{ - p_reg->INTENCLR = spi_int_mask; -} - -__STATIC_INLINE bool nrf_spi_int_enable_check(NRF_SPI_Type * p_reg, - nrf_spi_int_mask_t spi_int) -{ - return (bool)(p_reg->INTENSET & spi_int); -} - -__STATIC_INLINE void nrf_spi_enable(NRF_SPI_Type * p_reg) -{ - p_reg->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos); -} - -__STATIC_INLINE void nrf_spi_disable(NRF_SPI_Type * p_reg) -{ - p_reg->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos); -} - -__STATIC_INLINE void nrf_spi_pins_set(NRF_SPI_Type * p_reg, - uint32_t sck_pin, - uint32_t mosi_pin, - uint32_t miso_pin) -{ - p_reg->PSELSCK = sck_pin; - p_reg->PSELMOSI = mosi_pin; - p_reg->PSELMISO = miso_pin; -} - -__STATIC_INLINE void nrf_spi_txd_set(NRF_SPI_Type * p_reg, uint8_t data) -{ - p_reg->TXD = data; -} - -__STATIC_INLINE uint8_t nrf_spi_rxd_get(NRF_SPI_Type * p_reg) -{ - return p_reg->RXD; -} - -__STATIC_INLINE void nrf_spi_frequency_set(NRF_SPI_Type * p_reg, - nrf_spi_frequency_t frequency) -{ - p_reg->FREQUENCY = frequency; -} - -__STATIC_INLINE void nrf_spi_configure(NRF_SPI_Type * p_reg, - nrf_spi_mode_t spi_mode, - nrf_spi_bit_order_t spi_bit_order) -{ - uint32_t config = (spi_bit_order == NRF_SPI_BIT_ORDER_MSB_FIRST ? - SPI_CONFIG_ORDER_MsbFirst : SPI_CONFIG_ORDER_LsbFirst); - switch (spi_mode) - { - default: - case NRF_SPI_MODE_0: - config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos) | - (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos); - break; - - case NRF_SPI_MODE_1: - config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos) | - (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos); - break; - - case NRF_SPI_MODE_2: - config |= (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos) | - (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos); - break; - - case NRF_SPI_MODE_3: - config |= (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos) | - (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos); - break; - } - p_reg->CONFIG = config; -} - -#endif // SUPPRESS_INLINE_IMPLEMENTATION - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_SPI_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_spim.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_spim.h deleted file mode 100644 index fcef27cab5..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_spim.h +++ /dev/null @@ -1,736 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_SPIM_H__ -#define NRF_SPIM_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_spim_hal SPIM HAL - * @{ - * @ingroup nrf_spim - * @brief Hardware access layer for managing the SPIM peripheral. - */ - -/** - * @brief This value can be used as a parameter for the @ref nrf_spim_pins_set - * function to specify that a given SPI signal (SCK, MOSI, or MISO) - * shall not be connected to a physical pin. - */ -#define NRF_SPIM_PIN_NOT_CONNECTED 0xFFFFFFFF - -#if defined(SPIM_DCXCNT_DCXCNT_Msk) || defined(__NRFX_DOXYGEN__) -/** - * @brief This value specified in the DCX line configuration causes this line - * to be set low during whole transmission (all transmitted bytes are - * marked as command bytes). Any lower value causes the DCX line to be - * switched from low to high after this number of bytes is transmitted - * (all remaining bytes are marked as data bytes). - */ -#define NRF_SPIM_DCX_CNT_ALL_CMD 0xF -#endif - -#define NRF_SPIM_HW_CSN_PRESENT \ - (NRFX_CHECK(SPIM0_FEATURE_HARDWARE_CSN_PRESENT) || \ - NRFX_CHECK(SPIM1_FEATURE_HARDWARE_CSN_PRESENT) || \ - NRFX_CHECK(SPIM2_FEATURE_HARDWARE_CSN_PRESENT) || \ - NRFX_CHECK(SPIM3_FEATURE_HARDWARE_CSN_PRESENT)) - -/** - * @brief SPIM tasks. - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_SPIM_TASK_START = offsetof(NRF_SPIM_Type, TASKS_START), ///< Start SPI transaction. - NRF_SPIM_TASK_STOP = offsetof(NRF_SPIM_Type, TASKS_STOP), ///< Stop SPI transaction. - NRF_SPIM_TASK_SUSPEND = offsetof(NRF_SPIM_Type, TASKS_SUSPEND), ///< Suspend SPI transaction. - NRF_SPIM_TASK_RESUME = offsetof(NRF_SPIM_Type, TASKS_RESUME) ///< Resume SPI transaction. - /*lint -restore*/ -} nrf_spim_task_t; - -/** - * @brief SPIM events. - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_SPIM_EVENT_STOPPED = offsetof(NRF_SPIM_Type, EVENTS_STOPPED), ///< SPI transaction has stopped. - NRF_SPIM_EVENT_ENDRX = offsetof(NRF_SPIM_Type, EVENTS_ENDRX), ///< End of RXD buffer reached. - NRF_SPIM_EVENT_END = offsetof(NRF_SPIM_Type, EVENTS_END), ///< End of RXD buffer and TXD buffer reached. - NRF_SPIM_EVENT_ENDTX = offsetof(NRF_SPIM_Type, EVENTS_ENDTX), ///< End of TXD buffer reached. - NRF_SPIM_EVENT_STARTED = offsetof(NRF_SPIM_Type, EVENTS_STARTED) ///< Transaction started. - /*lint -restore*/ -} nrf_spim_event_t; - -/** - * @brief SPIM shortcuts. - */ -typedef enum -{ - NRF_SPIM_SHORT_END_START_MASK = SPIM_SHORTS_END_START_Msk, ///< Shortcut between END event and START task. - NRF_SPIM_ALL_SHORTS_MASK = SPIM_SHORTS_END_START_Msk ///< All SPIM shortcuts. -} nrf_spim_short_mask_t; - -/** - * @brief SPIM interrupts. - */ -typedef enum -{ - NRF_SPIM_INT_STOPPED_MASK = SPIM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event. - NRF_SPIM_INT_ENDRX_MASK = SPIM_INTENSET_ENDRX_Msk, ///< Interrupt on ENDRX event. - NRF_SPIM_INT_END_MASK = SPIM_INTENSET_END_Msk, ///< Interrupt on END event. - NRF_SPIM_INT_ENDTX_MASK = SPIM_INTENSET_ENDTX_Msk, ///< Interrupt on ENDTX event. - NRF_SPIM_INT_STARTED_MASK = SPIM_INTENSET_STARTED_Msk, ///< Interrupt on STARTED event. - NRF_SPIM_ALL_INTS_MASK = SPIM_INTENSET_STOPPED_Msk | - SPIM_INTENSET_ENDRX_Msk | - SPIM_INTENSET_END_Msk | - SPIM_INTENSET_ENDTX_Msk | - SPIM_INTENSET_STARTED_Msk ///< All SPIM interrupts. -} nrf_spim_int_mask_t; - -/** - * @brief SPI master data rates. - */ -typedef enum -{ - NRF_SPIM_FREQ_125K = SPIM_FREQUENCY_FREQUENCY_K125, ///< 125 kbps. - NRF_SPIM_FREQ_250K = SPIM_FREQUENCY_FREQUENCY_K250, ///< 250 kbps. - NRF_SPIM_FREQ_500K = SPIM_FREQUENCY_FREQUENCY_K500, ///< 500 kbps. - NRF_SPIM_FREQ_1M = SPIM_FREQUENCY_FREQUENCY_M1, ///< 1 Mbps. - NRF_SPIM_FREQ_2M = SPIM_FREQUENCY_FREQUENCY_M2, ///< 2 Mbps. - NRF_SPIM_FREQ_4M = SPIM_FREQUENCY_FREQUENCY_M4, ///< 4 Mbps. - // [conversion to 'int' needed to prevent compilers from complaining - // that the provided value (0x80000000UL) is out of range of "int"] - NRF_SPIM_FREQ_8M = (int)SPIM_FREQUENCY_FREQUENCY_M8, ///< 8 Mbps. -#if defined(SPIM_FREQUENCY_FREQUENCY_M16) || defined(__NRFX_DOXYGEN__) - NRF_SPIM_FREQ_16M = SPIM_FREQUENCY_FREQUENCY_M16, ///< 16 Mbps. -#endif -#if defined(SPIM_FREQUENCY_FREQUENCY_M32) || defined(__NRFX_DOXYGEN__) - NRF_SPIM_FREQ_32M = SPIM_FREQUENCY_FREQUENCY_M32 ///< 32 Mbps. -#endif -} nrf_spim_frequency_t; - -/** - * @brief SPI modes. - */ -typedef enum -{ - NRF_SPIM_MODE_0, ///< SCK active high, sample on leading edge of clock. - NRF_SPIM_MODE_1, ///< SCK active high, sample on trailing edge of clock. - NRF_SPIM_MODE_2, ///< SCK active low, sample on leading edge of clock. - NRF_SPIM_MODE_3 ///< SCK active low, sample on trailing edge of clock. -} nrf_spim_mode_t; - -/** - * @brief SPI bit orders. - */ -typedef enum -{ - NRF_SPIM_BIT_ORDER_MSB_FIRST = SPIM_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first. - NRF_SPIM_BIT_ORDER_LSB_FIRST = SPIM_CONFIG_ORDER_LsbFirst ///< Least significant bit shifted out first. -} nrf_spim_bit_order_t; - -#if (NRF_SPIM_HW_CSN_PRESENT) || defined(__NRFX_DOXYGEN__) -/** - * @brief SPI CSN pin polarity. - */ -typedef enum -{ - NRF_SPIM_CSN_POL_LOW = SPIM_CSNPOL_CSNPOL_LOW, ///< Active low (idle state high). - NRF_SPIM_CSN_POL_HIGH = SPIM_CSNPOL_CSNPOL_HIGH ///< Active high (idle state low). -} nrf_spim_csn_pol_t; -#endif // (NRF_SPIM_HW_CSN_PRESENT) || defined(__NRFX_DOXYGEN__) - -/** - * @brief Function for activating a specific SPIM task. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spim_task Task to activate. - */ -__STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_reg, - nrf_spim_task_t spim_task); - -/** - * @brief Function for getting the address of a specific SPIM task register. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spim_task Requested task. - * - * @return Address of the specified task register. - */ -__STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type * p_reg, - nrf_spim_task_t spim_task); - -/** - * @brief Function for clearing a specific SPIM event. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spim_event Event to clear. - */ -__STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_reg, - nrf_spim_event_t spim_event); - -/** - * @brief Function for checking the state of a specific SPIM event. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spim_event Event to check. - * - * @retval true If the event is set. - * @retval false If the event is not set. - */ -__STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type * p_reg, - nrf_spim_event_t spim_event); - -/** - * @brief Function for getting the address of a specific SPIM event register. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spim_event Requested event. - * - * @return Address of the specified event register. - */ -__STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type * p_reg, - nrf_spim_event_t spim_event); -/** - * @brief Function for enabling specified shortcuts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spim_shorts_mask Shortcuts to enable. - */ -__STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_reg, - uint32_t spim_shorts_mask); - -/** - * @brief Function for disabling specified shortcuts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spim_shorts_mask Shortcuts to disable. - */ -__STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_reg, - uint32_t spim_shorts_mask); - -/** - * @brief Function for getting shorts setting. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type * p_reg); - -/** - * @brief Function for enabling specified interrupts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spim_int_mask Interrupts to enable. - */ -__STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_reg, - uint32_t spim_int_mask); - -/** - * @brief Function for disabling specified interrupts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spim_int_mask Interrupts to disable. - */ -__STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_reg, - uint32_t spim_int_mask); - -/** - * @brief Function for retrieving the state of a given interrupt. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spim_int Interrupt to check. - * - * @retval true If the interrupt is enabled. - * @retval false If the interrupt is not enabled. - */ -__STATIC_INLINE bool nrf_spim_int_enable_check(NRF_SPIM_Type * p_reg, - nrf_spim_int_mask_t spim_int); - -/** - * @brief Function for enabling the SPIM peripheral. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_spim_enable(NRF_SPIM_Type * p_reg); - -/** - * @brief Function for disabling the SPIM peripheral. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_reg); - -/** - * @brief Function for configuring SPIM pins. - * - * If a given signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED - * value instead of its pin number. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] sck_pin SCK pin number. - * @param[in] mosi_pin MOSI pin number. - * @param[in] miso_pin MISO pin number. - */ -__STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg, - uint32_t sck_pin, - uint32_t mosi_pin, - uint32_t miso_pin); - -#if (NRF_SPIM_HW_CSN_PRESENT) || defined(__NRFX_DOXYGEN__) -/** - * @brief Function for configuring the SPIM hardware CSN pin. - * - * If this signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED - * value instead of its pin number. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] pin CSN pin number. - * @param[in] polarity CSN pin polarity. - * @param[in] duration Minimum duration between the edge of CSN and the edge of SCK - * and minimum duration of CSN must stay unselected between transactions. - * The value is specified in number of 64 MHz clock cycles (15.625 ns). - */ -__STATIC_INLINE void nrf_spim_csn_configure(NRF_SPIM_Type * p_reg, - uint32_t pin, - nrf_spim_csn_pol_t polarity, - uint32_t duration); -#endif // (NRF_SPIM_HW_CSN_PRESENT) || defined(__NRFX_DOXYGEN__) - -#if defined(SPIM_PSELDCX_CONNECT_Msk) || defined(__NRFX_DOXYGEN__) -/** - * @brief Function for configuring the SPIM DCX pin. - * - * If this signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED - * value instead of its pin number. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] dcx_pin DCX pin number. - */ -__STATIC_INLINE void nrf_spim_dcx_pin_set(NRF_SPIM_Type * p_reg, - uint32_t dcx_pin); - -/** - * @brief Function for configuring the number of command bytes. - * - * Maximum value available for dividing the transmitted bytes into command - * bytes and data bytes is @ref NRF_SPIM_DCX_CNT_ALL_CMD - 1. - * The @ref NRF_SPIM_DCX_CNT_ALL_CMD value passed as the @c count parameter - * causes all transmitted bytes to be marked as command bytes. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] count Number of command bytes preceding the data bytes. - */ -__STATIC_INLINE void nrf_spim_dcx_cnt_set(NRF_SPIM_Type * p_reg, - uint32_t count); -#endif // defined(SPIM_PSELDCX_CONNECT_Msk) || defined(__NRFX_DOXYGEN__) - -#if defined(SPIM_IFTIMING_RXDELAY_RXDELAY_Msk) || defined(__NRFX_DOXYGEN__) -/** - * @brief Function for configuring the extended SPIM interface. - * @param p_reg Pointer to the peripheral registers structure. - * @param rxdelay Sample delay for input serial data on MISO, - * specified in 64 MHz clock cycles (15.625 ns) from the sampling edge of SCK. - */ -__STATIC_INLINE void nrf_spim_iftiming_set(NRF_SPIM_Type * p_reg, - uint32_t rxdelay); -#endif // defined(SPIM_IFTIMING_RXDELAY_RXDELAY_Msk) || defined(__NRFX_DOXYGEN__) - -#if defined(SPIM_STALLSTAT_RX_Msk) || defined(__NRFX_DOXYGEN__) -/** - * @brief Function for clearing stall status for RX EasyDMA RAM accesses. - * - * @param p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_spim_stallstat_rx_clear(NRF_SPIM_Type * p_reg); - -/** - * @brief Function for getting stall status for RX EasyDMA RAM accesses. - * - * @param p_reg Pointer to the peripheral registers structure. - * - * @return Stall status of RX EasyDMA RAM accesses. - */ -__STATIC_INLINE bool nrf_spim_stallstat_rx_get(NRF_SPIM_Type * p_reg); -#endif // defined(SPIM_STALLSTAT_RX_Msk) || defined(__NRFX_DOXYGEN__) - -#if defined(SPIM_STALLSTAT_TX_Msk) || defined(__NRFX_DOXYGEN__) -/** - * @brief Function for clearing stall status for TX EasyDMA RAM accesses. - * - * @param p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_spim_stallstat_tx_clear(NRF_SPIM_Type * p_reg); - -/** - * @brief Function for getting stall status for TX EasyDMA RAM accesses. - * - * @param p_reg Pointer to the peripheral registers structure. - * - * @return Stall status of TX EasyDMA RAM accesses. - */ -__STATIC_INLINE bool nrf_spim_stallstat_tx_get(NRF_SPIM_Type * p_reg); -#endif // defined(SPIM_STALLSTAT_TX_Msk) || defined(__NRFX_DOXYGEN__) - -/** - * @brief Function for setting the SPI master data rate. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] frequency SPI frequency. - */ -__STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg, - nrf_spim_frequency_t frequency); - -/** - * @brief Function for setting the transmit buffer. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] p_buffer Pointer to the buffer with data to send. - * @param[in] length Maximum number of data bytes to transmit. - */ -__STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg, - uint8_t const * p_buffer, - size_t length); - -/** - * @brief Function for setting the receive buffer. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] p_buffer Pointer to the buffer for received data. - * @param[in] length Maximum number of data bytes to receive. - */ -__STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg, - uint8_t * p_buffer, - size_t length); - -/** - * @brief Function for setting the SPI configuration. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spi_mode SPI mode. - * @param[in] spi_bit_order SPI bit order. - */ -__STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_reg, - nrf_spim_mode_t spi_mode, - nrf_spim_bit_order_t spi_bit_order); - -/** - * @brief Function for setting the over-read character. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] orc Over-read character that is clocked out in case of - * an over-read of the TXD buffer. - */ -__STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_reg, - uint8_t orc); - -/** - * @brief Function for enabling the TX list feature. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg); - -/** - * @brief Function for disabling the TX list feature. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_reg); - -/** - * @brief Function for enabling the RX list feature. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg); - -/** - * @brief Function for disabling the RX list feature. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg); - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -__STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_reg, - nrf_spim_task_t spim_task) -{ - *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_task)) = 0x1UL; -} - -__STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type * p_reg, - nrf_spim_task_t spim_task) -{ - return (uint32_t)((uint8_t *)p_reg + (uint32_t)spim_task); -} - -__STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_reg, - nrf_spim_event_t spim_event) -{ - *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_event)); - (void)dummy; -#endif -} - -__STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type * p_reg, - nrf_spim_event_t spim_event) -{ - return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_event); -} - -__STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type * p_reg, - nrf_spim_event_t spim_event) -{ - return (uint32_t)((uint8_t *)p_reg + (uint32_t)spim_event); -} - -__STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_reg, - uint32_t spim_shorts_mask) -{ - p_reg->SHORTS |= spim_shorts_mask; -} - -__STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_reg, - uint32_t spim_shorts_mask) -{ - p_reg->SHORTS &= ~(spim_shorts_mask); -} - -__STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type * p_reg) -{ - return p_reg->SHORTS; -} - -__STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_reg, - uint32_t spim_int_mask) -{ - p_reg->INTENSET = spim_int_mask; -} - -__STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_reg, - uint32_t spim_int_mask) -{ - p_reg->INTENCLR = spim_int_mask; -} - -__STATIC_INLINE bool nrf_spim_int_enable_check(NRF_SPIM_Type * p_reg, - nrf_spim_int_mask_t spim_int) -{ - return (bool)(p_reg->INTENSET & spim_int); -} - -__STATIC_INLINE void nrf_spim_enable(NRF_SPIM_Type * p_reg) -{ - p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos); -} - -__STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_reg) -{ - p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos); -} - -__STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg, - uint32_t sck_pin, - uint32_t mosi_pin, - uint32_t miso_pin) -{ - p_reg->PSEL.SCK = sck_pin; - p_reg->PSEL.MOSI = mosi_pin; - p_reg->PSEL.MISO = miso_pin; -} - -#if (NRF_SPIM_HW_CSN_PRESENT) -__STATIC_INLINE void nrf_spim_csn_configure(NRF_SPIM_Type * p_reg, - uint32_t pin, - nrf_spim_csn_pol_t polarity, - uint32_t duration) -{ - p_reg->PSEL.CSN = pin; - p_reg->CSNPOL = polarity; - p_reg->IFTIMING.CSNDUR = duration; -} -#endif // defined(NRF_SPIM_HW_CSN_PRESENT) - -#if defined(SPIM_PSELDCX_CONNECT_Msk) -__STATIC_INLINE void nrf_spim_dcx_pin_set(NRF_SPIM_Type * p_reg, - uint32_t dcx_pin) -{ - p_reg->PSELDCX = dcx_pin; -} - -__STATIC_INLINE void nrf_spim_dcx_cnt_set(NRF_SPIM_Type * p_reg, - uint32_t dcx_cnt) -{ - p_reg->DCXCNT = dcx_cnt; -} -#endif // defined(SPIM_PSELDCX_CONNECT_Msk) - -#if defined(SPIM_IFTIMING_RXDELAY_RXDELAY_Msk) -__STATIC_INLINE void nrf_spim_iftiming_set(NRF_SPIM_Type * p_reg, - uint32_t rxdelay) -{ - p_reg->IFTIMING.RXDELAY = rxdelay; -} -#endif // defined(SPIM_IFTIMING_RXDELAY_RXDELAY_Msk) - -#if defined(SPIM_STALLSTAT_RX_Msk) -__STATIC_INLINE void nrf_spim_stallstat_rx_clear(NRF_SPIM_Type * p_reg) -{ - p_reg->STALLSTAT &= ~(SPIM_STALLSTAT_RX_Msk); -} - -__STATIC_INLINE bool nrf_spim_stallstat_rx_get(NRF_SPIM_Type * p_reg) -{ - return (p_reg->STALLSTAT & SPIM_STALLSTAT_RX_Msk) != 0; -} -#endif // defined(SPIM_STALLSTAT_RX_Msk) - -#if defined(SPIM_STALLSTAT_TX_Msk) -__STATIC_INLINE void nrf_spim_stallstat_tx_clear(NRF_SPIM_Type * p_reg) -{ - p_reg->STALLSTAT &= ~(SPIM_STALLSTAT_TX_Msk); -} - -__STATIC_INLINE bool nrf_spim_stallstat_tx_get(NRF_SPIM_Type * p_reg) -{ - return (p_reg->STALLSTAT & SPIM_STALLSTAT_TX_Msk) != 0; -} -#endif // defined(SPIM_STALLSTAT_TX_Msk) - -__STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg, - nrf_spim_frequency_t frequency) -{ - p_reg->FREQUENCY = frequency; -} - -__STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg, - uint8_t const * p_buffer, - size_t length) -{ - p_reg->TXD.PTR = (uint32_t)p_buffer; - p_reg->TXD.MAXCNT = length; -} - -__STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg, - uint8_t * p_buffer, - size_t length) -{ - p_reg->RXD.PTR = (uint32_t)p_buffer; - p_reg->RXD.MAXCNT = length; -} - -__STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_reg, - nrf_spim_mode_t spi_mode, - nrf_spim_bit_order_t spi_bit_order) -{ - uint32_t config = (spi_bit_order == NRF_SPIM_BIT_ORDER_MSB_FIRST ? - SPIM_CONFIG_ORDER_MsbFirst : SPIM_CONFIG_ORDER_LsbFirst); - switch (spi_mode) - { - default: - case NRF_SPIM_MODE_0: - config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) | - (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos); - break; - - case NRF_SPIM_MODE_1: - config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) | - (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos); - break; - - case NRF_SPIM_MODE_2: - config |= (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) | - (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos); - break; - - case NRF_SPIM_MODE_3: - config |= (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) | - (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos); - break; - } - p_reg->CONFIG = config; -} - -__STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_reg, - uint8_t orc) -{ - p_reg->ORC = orc; -} - - -__STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg) -{ - p_reg->TXD.LIST = 1; -} - -__STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_reg) -{ - p_reg->TXD.LIST = 0; -} - -__STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg) -{ - p_reg->RXD.LIST = 1; -} - -__STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg) -{ - p_reg->RXD.LIST = 0; -} - -#endif // SUPPRESS_INLINE_IMPLEMENTATION - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_SPIM_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_spis.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_spis.h deleted file mode 100644 index 506c485a38..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_spis.h +++ /dev/null @@ -1,571 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_SPIS_H__ -#define NRF_SPIS_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_spis_hal SPIS HAL - * @{ - * @ingroup nrf_spis - * @brief Hardware access layer for managing the SPIS peripheral. - */ - -/** - * @brief This value can be used as a parameter for the @ref nrf_spis_pins_set - * function to specify that a given SPI signal (SCK, MOSI, or MISO) - * shall not be connected to a physical pin. - */ -#define NRF_SPIS_PIN_NOT_CONNECTED 0xFFFFFFFF - - -/** - * @brief SPIS tasks. - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_SPIS_TASK_ACQUIRE = offsetof(NRF_SPIS_Type, TASKS_ACQUIRE), ///< Acquire SPI semaphore. - NRF_SPIS_TASK_RELEASE = offsetof(NRF_SPIS_Type, TASKS_RELEASE), ///< Release SPI semaphore, enabling the SPI slave to acquire it. - /*lint -restore*/ -} nrf_spis_task_t; - -/** - * @brief SPIS events. - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_SPIS_EVENT_END = offsetof(NRF_SPIS_Type, EVENTS_END), ///< Granted transaction completed. - NRF_SPIS_EVENT_ACQUIRED = offsetof(NRF_SPIS_Type, EVENTS_ACQUIRED) ///< Semaphore acquired. - /*lint -restore*/ -} nrf_spis_event_t; - -/** - * @brief SPIS shortcuts. - */ -typedef enum -{ - NRF_SPIS_SHORT_END_ACQUIRE = SPIS_SHORTS_END_ACQUIRE_Msk ///< Shortcut between END event and ACQUIRE task. -} nrf_spis_short_mask_t; - -/** - * @brief SPIS interrupts. - */ -typedef enum -{ - NRF_SPIS_INT_END_MASK = SPIS_INTENSET_END_Msk, ///< Interrupt on END event. - NRF_SPIS_INT_ACQUIRED_MASK = SPIS_INTENSET_ACQUIRED_Msk ///< Interrupt on ACQUIRED event. -} nrf_spis_int_mask_t; - -/** - * @brief SPI modes. - */ -typedef enum -{ - NRF_SPIS_MODE_0, ///< SCK active high, sample on leading edge of clock. - NRF_SPIS_MODE_1, ///< SCK active high, sample on trailing edge of clock. - NRF_SPIS_MODE_2, ///< SCK active low, sample on leading edge of clock. - NRF_SPIS_MODE_3 ///< SCK active low, sample on trailing edge of clock. -} nrf_spis_mode_t; - -/** - * @brief SPI bit orders. - */ -typedef enum -{ - NRF_SPIS_BIT_ORDER_MSB_FIRST = SPIS_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first. - NRF_SPIS_BIT_ORDER_LSB_FIRST = SPIS_CONFIG_ORDER_LsbFirst ///< Least significant bit shifted out first. -} nrf_spis_bit_order_t; - -/** - * @brief SPI semaphore status. - */ -typedef enum -{ - NRF_SPIS_SEMSTAT_FREE = 0, ///< Semaphore is free. - NRF_SPIS_SEMSTAT_CPU = 1, ///< Semaphore is assigned to the CPU. - NRF_SPIS_SEMSTAT_SPIS = 2, ///< Semaphore is assigned to the SPI slave. - NRF_SPIS_SEMSTAT_CPUPENDING = 3 ///< Semaphore is assigned to the SPI, but a handover to the CPU is pending. -} nrf_spis_semstat_t; - -/** - * @brief SPIS status. - */ -typedef enum -{ - NRF_SPIS_STATUS_OVERREAD = SPIS_STATUS_OVERREAD_Msk, ///< TX buffer over-read detected and prevented. - NRF_SPIS_STATUS_OVERFLOW = SPIS_STATUS_OVERFLOW_Msk ///< RX buffer overflow detected and prevented. -} nrf_spis_status_mask_t; - -/** - * @brief Function for activating a specific SPIS task. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spis_task Task to activate. - */ -__STATIC_INLINE void nrf_spis_task_trigger(NRF_SPIS_Type * p_reg, - nrf_spis_task_t spis_task); - -/** - * @brief Function for getting the address of a specific SPIS task register. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spis_task Requested task. - * - * @return Address of the specified task register. - */ -__STATIC_INLINE uint32_t nrf_spis_task_address_get(NRF_SPIS_Type const * p_reg, - nrf_spis_task_t spis_task); - -/** - * @brief Function for clearing a specific SPIS event. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spis_event Event to clear. - */ -__STATIC_INLINE void nrf_spis_event_clear(NRF_SPIS_Type * p_reg, - nrf_spis_event_t spis_event); - -/** - * @brief Function for checking the state of a specific SPIS event. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spis_event Event to check. - * - * @retval true If the event is set. - * @retval false If the event is not set. - */ -__STATIC_INLINE bool nrf_spis_event_check(NRF_SPIS_Type const * p_reg, - nrf_spis_event_t spis_event); - -/** - * @brief Function for getting the address of a specific SPIS event register. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spis_event Requested event. - * - * @return Address of the specified event register. - */ -__STATIC_INLINE uint32_t nrf_spis_event_address_get(NRF_SPIS_Type const * p_reg, - nrf_spis_event_t spis_event); - -/** - * @brief Function for enabling specified shortcuts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spis_shorts_mask Shortcuts to enable. - */ -__STATIC_INLINE void nrf_spis_shorts_enable(NRF_SPIS_Type * p_reg, - uint32_t spis_shorts_mask); - -/** - * @brief Function for disabling specified shortcuts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spis_shorts_mask Shortcuts to disable. - */ -__STATIC_INLINE void nrf_spis_shorts_disable(NRF_SPIS_Type * p_reg, - uint32_t spis_shorts_mask); - -/** - * @brief Function for enabling specified interrupts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spis_int_mask Interrupts to enable. - */ -__STATIC_INLINE void nrf_spis_int_enable(NRF_SPIS_Type * p_reg, - uint32_t spis_int_mask); - -/** - * @brief Function for disabling specified interrupts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spis_int_mask Interrupts to disable. - */ -__STATIC_INLINE void nrf_spis_int_disable(NRF_SPIS_Type * p_reg, - uint32_t spis_int_mask); - -/** - * @brief Function for retrieving the state of a given interrupt. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spis_int Interrupt to check. - * - * @retval true If the interrupt is enabled. - * @retval false If the interrupt is not enabled. - */ -__STATIC_INLINE bool nrf_spis_int_enable_check(NRF_SPIS_Type const * p_reg, - nrf_spis_int_mask_t spis_int); - -/** - * @brief Function for enabling the SPIS peripheral. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_spis_enable(NRF_SPIS_Type * p_reg); - -/** - * @brief Function for disabling the SPIS peripheral. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_spis_disable(NRF_SPIS_Type * p_reg); - -/** - * @brief Function for retrieving the SPIS semaphore status. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * - * @returns Current semaphore status. - */ -__STATIC_INLINE nrf_spis_semstat_t nrf_spis_semaphore_status_get(NRF_SPIS_Type * p_reg); - -/** - * @brief Function for retrieving the SPIS status. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * - * @returns Current SPIS status. - */ -__STATIC_INLINE nrf_spis_status_mask_t nrf_spis_status_get(NRF_SPIS_Type * p_reg); - -/** - * @brief Function for configuring SPIS pins. - * - * If a given signal is not needed, pass the @ref NRF_SPIS_PIN_NOT_CONNECTED - * value instead of its pin number. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] sck_pin SCK pin number. - * @param[in] mosi_pin MOSI pin number. - * @param[in] miso_pin MISO pin number. - * @param[in] csn_pin CSN pin number. - */ -__STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_reg, - uint32_t sck_pin, - uint32_t mosi_pin, - uint32_t miso_pin, - uint32_t csn_pin); - -/** - * @brief Function for setting the transmit buffer. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] p_buffer Pointer to the buffer that contains the data to send. - * @param[in] length Maximum number of data bytes to transmit. - */ -__STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_reg, - uint8_t const * p_buffer, - size_t length); - -/** - * @brief Function for setting the receive buffer. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] p_buffer Pointer to the buffer for received data. - * @param[in] length Maximum number of data bytes to receive. - */ -__STATIC_INLINE void nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_reg, - uint8_t * p_buffer, - size_t length); - -/** - * @brief Function for getting the number of bytes transmitted - * in the last granted transaction. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * - * @returns Number of bytes transmitted. - */ -__STATIC_INLINE size_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_reg); - -/** - * @brief Function for getting the number of bytes received - * in the last granted transaction. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * - * @returns Number of bytes received. - */ -__STATIC_INLINE size_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_reg); - -/** - * @brief Function for setting the SPI configuration. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] spi_mode SPI mode. - * @param[in] spi_bit_order SPI bit order. - */ -__STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_reg, - nrf_spis_mode_t spi_mode, - nrf_spis_bit_order_t spi_bit_order); - -/** - * @brief Function for setting the default character. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] def Default character that is clocked out in case of - * an overflow of the RXD buffer. - */ -__STATIC_INLINE void nrf_spis_def_set(NRF_SPIS_Type * p_reg, - uint8_t def); - -/** - * @brief Function for setting the over-read character. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] orc Over-read character that is clocked out in case of - * an over-read of the TXD buffer. - */ -__STATIC_INLINE void nrf_spis_orc_set(NRF_SPIS_Type * p_reg, - uint8_t orc); - - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -__STATIC_INLINE void nrf_spis_task_trigger(NRF_SPIS_Type * p_reg, - nrf_spis_task_t spis_task) -{ - *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spis_task)) = 0x1UL; -} - -__STATIC_INLINE uint32_t nrf_spis_task_address_get(NRF_SPIS_Type const * p_reg, - nrf_spis_task_t spis_task) -{ - return (uint32_t)p_reg + (uint32_t)spis_task; -} - -__STATIC_INLINE void nrf_spis_event_clear(NRF_SPIS_Type * p_reg, - nrf_spis_event_t spis_event) -{ - *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spis_event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spis_event)); - (void)dummy; -#endif -} - -__STATIC_INLINE bool nrf_spis_event_check(NRF_SPIS_Type const * p_reg, - nrf_spis_event_t spis_event) -{ - return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spis_event); -} - -__STATIC_INLINE uint32_t nrf_spis_event_address_get(NRF_SPIS_Type const * p_reg, - nrf_spis_event_t spis_event) -{ - return (uint32_t)p_reg + (uint32_t)spis_event; -} - -__STATIC_INLINE void nrf_spis_shorts_enable(NRF_SPIS_Type * p_reg, - uint32_t spis_shorts_mask) -{ - p_reg->SHORTS |= spis_shorts_mask; -} - -__STATIC_INLINE void nrf_spis_shorts_disable(NRF_SPIS_Type * p_reg, - uint32_t spis_shorts_mask) -{ - p_reg->SHORTS &= ~(spis_shorts_mask); -} - -__STATIC_INLINE void nrf_spis_int_enable(NRF_SPIS_Type * p_reg, - uint32_t spis_int_mask) -{ - p_reg->INTENSET = spis_int_mask; -} - -__STATIC_INLINE void nrf_spis_int_disable(NRF_SPIS_Type * p_reg, - uint32_t spis_int_mask) -{ - p_reg->INTENCLR = spis_int_mask; -} - -__STATIC_INLINE bool nrf_spis_int_enable_check(NRF_SPIS_Type const * p_reg, - nrf_spis_int_mask_t spis_int) -{ - return (bool)(p_reg->INTENSET & spis_int); -} - -__STATIC_INLINE void nrf_spis_enable(NRF_SPIS_Type * p_reg) -{ - p_reg->ENABLE = (SPIS_ENABLE_ENABLE_Enabled << SPIS_ENABLE_ENABLE_Pos); -} - -__STATIC_INLINE void nrf_spis_disable(NRF_SPIS_Type * p_reg) -{ - p_reg->ENABLE = (SPIS_ENABLE_ENABLE_Disabled << SPIS_ENABLE_ENABLE_Pos); -} - -__STATIC_INLINE nrf_spis_semstat_t nrf_spis_semaphore_status_get(NRF_SPIS_Type * p_reg) -{ - return (nrf_spis_semstat_t) ((p_reg->SEMSTAT & SPIS_SEMSTAT_SEMSTAT_Msk) - >> SPIS_SEMSTAT_SEMSTAT_Pos); -} - -__STATIC_INLINE nrf_spis_status_mask_t nrf_spis_status_get(NRF_SPIS_Type * p_reg) -{ - return (nrf_spis_status_mask_t) p_reg->STATUS; -} - -__STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_reg, - uint32_t sck_pin, - uint32_t mosi_pin, - uint32_t miso_pin, - uint32_t csn_pin) -{ -#if defined (NRF51) - p_reg->PSELSCK = sck_pin; - p_reg->PSELMOSI = mosi_pin; - p_reg->PSELMISO = miso_pin; - p_reg->PSELCSN = csn_pin; -#else - p_reg->PSEL.SCK = sck_pin; - p_reg->PSEL.MOSI = mosi_pin; - p_reg->PSEL.MISO = miso_pin; - p_reg->PSEL.CSN = csn_pin; -#endif -} - -__STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_reg, - uint8_t const * p_buffer, - size_t length) -{ -#if defined (NRF51) - p_reg->TXDPTR = (uint32_t)p_buffer; - p_reg->MAXTX = length; -#else - p_reg->TXD.PTR = (uint32_t)p_buffer; - p_reg->TXD.MAXCNT = length; -#endif -} - -__STATIC_INLINE void nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_reg, - uint8_t * p_buffer, - size_t length) -{ -#if defined (NRF51) - p_reg->RXDPTR = (uint32_t)p_buffer; - p_reg->MAXRX = length; -#else - p_reg->RXD.PTR = (uint32_t)p_buffer; - p_reg->RXD.MAXCNT = length; -#endif -} - -__STATIC_INLINE size_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_reg) -{ -#if defined (NRF51) - return p_reg->AMOUNTTX; -#else - return p_reg->TXD.AMOUNT; -#endif -} - -__STATIC_INLINE size_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_reg) -{ -#if defined (NRF51) - return p_reg->AMOUNTRX; -#else - return p_reg->RXD.AMOUNT; -#endif -} - -__STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_reg, - nrf_spis_mode_t spi_mode, - nrf_spis_bit_order_t spi_bit_order) -{ - uint32_t config = (spi_bit_order == NRF_SPIS_BIT_ORDER_MSB_FIRST ? - SPIS_CONFIG_ORDER_MsbFirst : SPIS_CONFIG_ORDER_LsbFirst); - - switch (spi_mode) - { - default: - case NRF_SPIS_MODE_0: - config |= (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) | - (SPIS_CONFIG_CPHA_Leading << SPIS_CONFIG_CPHA_Pos); - break; - - case NRF_SPIS_MODE_1: - config |= (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) | - (SPIS_CONFIG_CPHA_Trailing << SPIS_CONFIG_CPHA_Pos); - break; - - case NRF_SPIS_MODE_2: - config |= (SPIS_CONFIG_CPOL_ActiveLow << SPIS_CONFIG_CPOL_Pos) | - (SPIS_CONFIG_CPHA_Leading << SPIS_CONFIG_CPHA_Pos); - break; - - case NRF_SPIS_MODE_3: - config |= (SPIS_CONFIG_CPOL_ActiveLow << SPIS_CONFIG_CPOL_Pos) | - (SPIS_CONFIG_CPHA_Trailing << SPIS_CONFIG_CPHA_Pos); - break; - } - p_reg->CONFIG = config; -} - -__STATIC_INLINE void nrf_spis_orc_set(NRF_SPIS_Type * p_reg, - uint8_t orc) -{ - p_reg->ORC = orc; -} - -__STATIC_INLINE void nrf_spis_def_set(NRF_SPIS_Type * p_reg, - uint8_t def) -{ - p_reg->DEF = def; -} - -#endif // SUPPRESS_INLINE_IMPLEMENTATION - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_SPIS_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_systick.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_systick.h deleted file mode 100644 index 57932fdfc2..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_systick.h +++ /dev/null @@ -1,190 +0,0 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_SYSTICK_H__ -#define NRF_SYSTICK_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_systick_hal SYSTICK HAL - * @{ - * @ingroup nrf_systick - * @brief Hardware access layer for managing the SYSTICK peripheral. - * - * SYSTICK is ARM peripheral, not Nordic design. - * It means that it has no Nordic-typical interface with Tasks and Events. - * - * Its usage is limited here to implement simple delays. - * Also keep in mind that this timer would be stopped when CPU is sleeping - * (WFE/WFI instruction is successfully executed). - */ - -/** - * @brief Mask of usable bits in the SysTick value - */ -#define NRF_SYSTICK_VAL_MASK SysTick_VAL_CURRENT_Msk - -/** - * @brief Flags used by SysTick configuration. - * - * @sa nrf_systick_csr_set - * @sa nrf_systick_csr_get - */ -typedef enum { - NRF_SYSTICK_CSR_COUNTFLAG_MASK = SysTick_CTRL_COUNTFLAG_Msk, /**< Status flag: Returns 1 if timer counted to 0 since the last read of this register. */ - - NRF_SYSTICK_CSR_CLKSOURCE_MASK = SysTick_CTRL_CLKSOURCE_Msk, /**< Configuration bit: Select the SysTick clock source. */ - NRF_SYSTICK_CSR_CLKSOURCE_REF = 0U << SysTick_CTRL_CLKSOURCE_Pos, /**< Configuration value: Select reference clock. */ - NRF_SYSTICK_CSR_CLKSOURCE_CPU = 1U << SysTick_CTRL_CLKSOURCE_Pos, /**< Configuration value: Select CPU clock. */ - - NRF_SYSTICK_CSR_TICKINT_MASK = SysTick_CTRL_TICKINT_Msk, /**< Configuration bit: Enables SysTick exception request. */ - NRF_SYSTICK_CSR_TICKINT_ENABLE = 1U << SysTick_CTRL_TICKINT_Pos, /**< Configuration value: Counting down to zero does not assert the SysTick exception request. */ - NRF_SYSTICK_CSR_TICKINT_DISABLE = 0U << SysTick_CTRL_TICKINT_Pos, /**< Configuration value: Counting down to zero to asserts the SysTick exception request. */ - - NRF_SYSTICK_CSR_ENABLE_MASK = SysTick_CTRL_ENABLE_Msk, /**< Configuration bit: Enable the SysTick timer. */ - NRF_SYSTICK_CSR_ENABLE = 1U << SysTick_CTRL_ENABLE_Pos, /**< Configuration value: Counter enabled. */ - NRF_SYSTICK_CSR_DISABLE = 0U << SysTick_CTRL_ENABLE_Pos /**< Configuration value: Counter disabled. */ -} nrf_systick_csr_flags_t; - -/** - * @brief Get Configuration and Status Register - * - * @return Values composed by @ref nrf_systick_csr_flags_t. - * @note The @ref NRF_SYSTICK_CSR_COUNTFLAG_MASK value is cleared when CSR register is read. - */ -__STATIC_INLINE uint32_t nrf_systick_csr_get(void); - -/** - * @brief Set Configuration and Status Register - * - * @param[in] val The value composed from @ref nrf_systick_csr_flags_t. - */ -__STATIC_INLINE void nrf_systick_csr_set(uint32_t val); - -/** - * @brief Get the current reload value. - * - * @return The reload register value. - */ -__STATIC_INLINE uint32_t nrf_systick_load_get(void); - -/** - * @brief Configure the reload value. - * - * @param[in] val The value to set in the reload register. - */ -__STATIC_INLINE void nrf_systick_load_set(uint32_t val); - -/** - * @brief Read the SysTick current value - * - * @return The current SysTick value - * @sa NRF_SYSTICK_VAL_MASK - */ -__STATIC_INLINE uint32_t nrf_systick_val_get(void); - -/** - * @brief Clear the SysTick current value - * - * @note The SysTick does not allow setting current value. - * Any write to VAL register would clear the timer. - */ -__STATIC_INLINE void nrf_systick_val_clear(void); - -/** - * @brief Read the calibration register - * - * @return The calibration register value - */ -__STATIC_INLINE uint32_t nrf_systick_calib_get(void); - - - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -__STATIC_INLINE uint32_t nrf_systick_csr_get(void) -{ - return SysTick->CTRL; -} - -__STATIC_INLINE void nrf_systick_csr_set(uint32_t val) -{ - SysTick->CTRL = val; -} - -__STATIC_INLINE uint32_t nrf_systick_load_get(void) -{ - return SysTick->LOAD; -} - -__STATIC_INLINE void nrf_systick_load_set(uint32_t val) -{ - SysTick->LOAD = val; -} - -__STATIC_INLINE uint32_t nrf_systick_val_get(void) -{ - return SysTick->VAL; -} - -__STATIC_INLINE void nrf_systick_val_clear(void) -{ - SysTick->VAL = 0; -} - -__STATIC_INLINE uint32_t nrf_systick_calib_get(void) -{ - return SysTick->CALIB; -} - -#endif /* SUPPRESS_INLINE_IMPLEMENTATION */ - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* NRF_SYSTICK_H__ */ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_temp.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_temp.h deleted file mode 100644 index 51fa6078a1..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_temp.h +++ /dev/null @@ -1,88 +0,0 @@ -/** - * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_TEMP_H__ -#define NRF_TEMP_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** -* @defgroup nrf_temp_hal TEMP HAL -* @{ -* @ingroup nrf_temp temperature_example -* @brief Temperature module init and read functions. -*/ - -#define MASK_SIGN (0x00000200UL) -#define MASK_SIGN_EXTENSION (0xFFFFFC00UL) - -/** - * @brief Function for preparing the temp module for temperature measurement. - * - * This function initializes the TEMP module and writes to the hidden configuration register. - */ -static __INLINE void nrf_temp_init(void) -{ - /**@note Workaround for PAN_028 rev2.0A anomaly 31 - TEMP: Temperature offset value has to be manually loaded to the TEMP module */ - *(uint32_t *) 0x4000C504 = 0; -} - -/** - * @brief Function for reading temperature measurement. - * - * The function reads the 10 bit 2's complement value and transforms it to a 32 bit 2's complement value. - */ -static __INLINE int32_t nrf_temp_read(void) -{ - /**@note Workaround for PAN_028 rev2.0A anomaly 28 - TEMP: Negative measured values are not represented correctly */ - return ((NRF_TEMP->TEMP & MASK_SIGN) != 0) ? (int32_t)(NRF_TEMP->TEMP | MASK_SIGN_EXTENSION) : (NRF_TEMP->TEMP); -} - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_timer.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_timer.h deleted file mode 100644 index 8e0030e952..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_timer.h +++ /dev/null @@ -1,634 +0,0 @@ -/** - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_TIMER_H__ -#define NRF_TIMER_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_timer_hal TIMER HAL - * @{ - * @ingroup nrf_timer - * @brief Hardware access layer for managing the TIMER peripheral. - */ - -/** - * @brief Macro for validating the correctness of the BIT_WIDTH setting. - */ - -#define TIMER_MAX_SIZE(id) NRFX_CONCAT_3(TIMER, id, _MAX_SIZE) - -#define TIMER_BIT_WIDTH_MAX(id, bit_width) \ - (TIMER_MAX_SIZE(id) == 8 ? (bit_width == NRF_TIMER_BIT_WIDTH_8) : \ - (TIMER_MAX_SIZE(id) == 16 ? (bit_width == NRF_TIMER_BIT_WIDTH_8) || \ - (bit_width == NRF_TIMER_BIT_WIDTH_16) : \ - (TIMER_MAX_SIZE(id) == 24 ? (bit_width == NRF_TIMER_BIT_WIDTH_8) || \ - (bit_width == NRF_TIMER_BIT_WIDTH_16) || \ - (bit_width == NRF_TIMER_BIT_WIDTH_24) : \ - (TIMER_MAX_SIZE(id) == 32 ? (bit_width == NRF_TIMER_BIT_WIDTH_8) || \ - (bit_width == NRF_TIMER_BIT_WIDTH_16) || \ - (bit_width == NRF_TIMER_BIT_WIDTH_24) || \ - (bit_width == NRF_TIMER_BIT_WIDTH_32) : \ - false)))) - -#if TIMER_COUNT > 3 -#define NRF_TIMER_IS_BIT_WIDTH_VALID(p_reg, bit_width) ( \ - ((p_reg == NRF_TIMER0) && (TIMER_BIT_WIDTH_MAX(0, bit_width))) \ - || ((p_reg == NRF_TIMER1) && (TIMER_BIT_WIDTH_MAX(1, bit_width))) \ - || ((p_reg == NRF_TIMER2) && (TIMER_BIT_WIDTH_MAX(2, bit_width))) \ - || ((p_reg == NRF_TIMER3) && (TIMER_BIT_WIDTH_MAX(3, bit_width))) \ - || ((p_reg == NRF_TIMER4) && (TIMER_BIT_WIDTH_MAX(4, bit_width))) ) - -#else -#define NRF_TIMER_IS_BIT_WIDTH_VALID(p_reg, bit_width) ( \ - ((p_reg == NRF_TIMER0) && TIMER_BIT_WIDTH_MAX(0, bit_width)) \ - || ((p_reg == NRF_TIMER1) && TIMER_BIT_WIDTH_MAX(1, bit_width)) \ - || ((p_reg == NRF_TIMER2) && TIMER_BIT_WIDTH_MAX(2, bit_width)) ) - -#endif - -/** - * @brief Macro for getting the number of capture/compare channels available - * in a given timer instance. - */ -#define NRF_TIMER_CC_CHANNEL_COUNT(id) NRFX_CONCAT_3(TIMER, id, _CC_NUM) - -/** - * @brief Timer tasks. - */ -typedef enum -{ - /*lint -save -e30 -esym(628,__INTADDR__)*/ - NRF_TIMER_TASK_START = offsetof(NRF_TIMER_Type, TASKS_START), ///< Task for starting the timer. - NRF_TIMER_TASK_STOP = offsetof(NRF_TIMER_Type, TASKS_STOP), ///< Task for stopping the timer. - NRF_TIMER_TASK_COUNT = offsetof(NRF_TIMER_Type, TASKS_COUNT), ///< Task for incrementing the timer (in counter mode). - NRF_TIMER_TASK_CLEAR = offsetof(NRF_TIMER_Type, TASKS_CLEAR), ///< Task for resetting the timer value. - NRF_TIMER_TASK_SHUTDOWN = offsetof(NRF_TIMER_Type, TASKS_SHUTDOWN), ///< Task for powering off the timer. - NRF_TIMER_TASK_CAPTURE0 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[0]), ///< Task for capturing the timer value on channel 0. - NRF_TIMER_TASK_CAPTURE1 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[1]), ///< Task for capturing the timer value on channel 1. - NRF_TIMER_TASK_CAPTURE2 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[2]), ///< Task for capturing the timer value on channel 2. - NRF_TIMER_TASK_CAPTURE3 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[3]), ///< Task for capturing the timer value on channel 3. -#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__) - NRF_TIMER_TASK_CAPTURE4 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[4]), ///< Task for capturing the timer value on channel 4. -#endif -#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__) - NRF_TIMER_TASK_CAPTURE5 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[5]), ///< Task for capturing the timer value on channel 5. -#endif - /*lint -restore*/ -} nrf_timer_task_t; - -/** - * @brief Timer events. - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_TIMER_EVENT_COMPARE0 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[0]), ///< Event from compare channel 0. - NRF_TIMER_EVENT_COMPARE1 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[1]), ///< Event from compare channel 1. - NRF_TIMER_EVENT_COMPARE2 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[2]), ///< Event from compare channel 2. - NRF_TIMER_EVENT_COMPARE3 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[3]), ///< Event from compare channel 3. -#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__) - NRF_TIMER_EVENT_COMPARE4 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[4]), ///< Event from compare channel 4. -#endif -#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__) - NRF_TIMER_EVENT_COMPARE5 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[5]), ///< Event from compare channel 5. -#endif - /*lint -restore*/ -} nrf_timer_event_t; - -/** - * @brief Types of timer shortcuts. - */ -typedef enum -{ - NRF_TIMER_SHORT_COMPARE0_STOP_MASK = TIMER_SHORTS_COMPARE0_STOP_Msk, ///< Shortcut for stopping the timer based on compare 0. - NRF_TIMER_SHORT_COMPARE1_STOP_MASK = TIMER_SHORTS_COMPARE1_STOP_Msk, ///< Shortcut for stopping the timer based on compare 1. - NRF_TIMER_SHORT_COMPARE2_STOP_MASK = TIMER_SHORTS_COMPARE2_STOP_Msk, ///< Shortcut for stopping the timer based on compare 2. - NRF_TIMER_SHORT_COMPARE3_STOP_MASK = TIMER_SHORTS_COMPARE3_STOP_Msk, ///< Shortcut for stopping the timer based on compare 3. -#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__) - NRF_TIMER_SHORT_COMPARE4_STOP_MASK = TIMER_SHORTS_COMPARE4_STOP_Msk, ///< Shortcut for stopping the timer based on compare 4. -#endif -#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__) - NRF_TIMER_SHORT_COMPARE5_STOP_MASK = TIMER_SHORTS_COMPARE5_STOP_Msk, ///< Shortcut for stopping the timer based on compare 5. -#endif - NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK = TIMER_SHORTS_COMPARE0_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 0. - NRF_TIMER_SHORT_COMPARE1_CLEAR_MASK = TIMER_SHORTS_COMPARE1_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 1. - NRF_TIMER_SHORT_COMPARE2_CLEAR_MASK = TIMER_SHORTS_COMPARE2_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 2. - NRF_TIMER_SHORT_COMPARE3_CLEAR_MASK = TIMER_SHORTS_COMPARE3_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 3. -#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__) - NRF_TIMER_SHORT_COMPARE4_CLEAR_MASK = TIMER_SHORTS_COMPARE4_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 4. -#endif -#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__) - NRF_TIMER_SHORT_COMPARE5_CLEAR_MASK = TIMER_SHORTS_COMPARE5_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 5. -#endif -} nrf_timer_short_mask_t; - -/** - * @brief Timer modes. - */ -typedef enum -{ - NRF_TIMER_MODE_TIMER = TIMER_MODE_MODE_Timer, ///< Timer mode: timer. - NRF_TIMER_MODE_COUNTER = TIMER_MODE_MODE_Counter, ///< Timer mode: counter. -#if defined(TIMER_MODE_MODE_LowPowerCounter) || defined(__NRFX_DOXYGEN__) - NRF_TIMER_MODE_LOW_POWER_COUNTER = TIMER_MODE_MODE_LowPowerCounter, ///< Timer mode: low-power counter. -#endif -} nrf_timer_mode_t; - -/** - * @brief Timer bit width. - */ -typedef enum -{ - NRF_TIMER_BIT_WIDTH_8 = TIMER_BITMODE_BITMODE_08Bit, ///< Timer bit width 8 bit. - NRF_TIMER_BIT_WIDTH_16 = TIMER_BITMODE_BITMODE_16Bit, ///< Timer bit width 16 bit. - NRF_TIMER_BIT_WIDTH_24 = TIMER_BITMODE_BITMODE_24Bit, ///< Timer bit width 24 bit. - NRF_TIMER_BIT_WIDTH_32 = TIMER_BITMODE_BITMODE_32Bit ///< Timer bit width 32 bit. -} nrf_timer_bit_width_t; - -/** - * @brief Timer prescalers. - */ -typedef enum -{ - NRF_TIMER_FREQ_16MHz = 0, ///< Timer frequency 16 MHz. - NRF_TIMER_FREQ_8MHz, ///< Timer frequency 8 MHz. - NRF_TIMER_FREQ_4MHz, ///< Timer frequency 4 MHz. - NRF_TIMER_FREQ_2MHz, ///< Timer frequency 2 MHz. - NRF_TIMER_FREQ_1MHz, ///< Timer frequency 1 MHz. - NRF_TIMER_FREQ_500kHz, ///< Timer frequency 500 kHz. - NRF_TIMER_FREQ_250kHz, ///< Timer frequency 250 kHz. - NRF_TIMER_FREQ_125kHz, ///< Timer frequency 125 kHz. - NRF_TIMER_FREQ_62500Hz, ///< Timer frequency 62500 Hz. - NRF_TIMER_FREQ_31250Hz ///< Timer frequency 31250 Hz. -} nrf_timer_frequency_t; - -/** - * @brief Timer capture/compare channels. - */ -typedef enum -{ - NRF_TIMER_CC_CHANNEL0 = 0, ///< Timer capture/compare channel 0. - NRF_TIMER_CC_CHANNEL1, ///< Timer capture/compare channel 1. - NRF_TIMER_CC_CHANNEL2, ///< Timer capture/compare channel 2. - NRF_TIMER_CC_CHANNEL3, ///< Timer capture/compare channel 3. -#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__) - NRF_TIMER_CC_CHANNEL4, ///< Timer capture/compare channel 4. -#endif -#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__) - NRF_TIMER_CC_CHANNEL5, ///< Timer capture/compare channel 5. -#endif -} nrf_timer_cc_channel_t; - -/** - * @brief Timer interrupts. - */ -typedef enum -{ - NRF_TIMER_INT_COMPARE0_MASK = TIMER_INTENSET_COMPARE0_Msk, ///< Timer interrupt from compare event on channel 0. - NRF_TIMER_INT_COMPARE1_MASK = TIMER_INTENSET_COMPARE1_Msk, ///< Timer interrupt from compare event on channel 1. - NRF_TIMER_INT_COMPARE2_MASK = TIMER_INTENSET_COMPARE2_Msk, ///< Timer interrupt from compare event on channel 2. - NRF_TIMER_INT_COMPARE3_MASK = TIMER_INTENSET_COMPARE3_Msk, ///< Timer interrupt from compare event on channel 3. -#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__) - NRF_TIMER_INT_COMPARE4_MASK = TIMER_INTENSET_COMPARE4_Msk, ///< Timer interrupt from compare event on channel 4. -#endif -#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__) - NRF_TIMER_INT_COMPARE5_MASK = TIMER_INTENSET_COMPARE5_Msk, ///< Timer interrupt from compare event on channel 5. -#endif -} nrf_timer_int_mask_t; - - -/** - * @brief Function for activating a specific timer task. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] task Task to activate. - */ -__STATIC_INLINE void nrf_timer_task_trigger(NRF_TIMER_Type * p_reg, - nrf_timer_task_t task); - -/** - * @brief Function for getting the address of a specific timer task register. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] task Requested task. - * - * @return Address of the specified task register. - */ -__STATIC_INLINE uint32_t * nrf_timer_task_address_get(NRF_TIMER_Type * p_reg, - nrf_timer_task_t task); - -/** - * @brief Function for clearing a specific timer event. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] event Event to clear. - */ -__STATIC_INLINE void nrf_timer_event_clear(NRF_TIMER_Type * p_reg, - nrf_timer_event_t event); - -/** - * @brief Function for checking the state of a specific timer event. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] event Event to check. - * - * @retval true If the event is set. - * @retval false If the event is not set. - */ -__STATIC_INLINE bool nrf_timer_event_check(NRF_TIMER_Type * p_reg, - nrf_timer_event_t event); - -/** - * @brief Function for getting the address of a specific timer event register. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] event Requested event. - * - * @return Address of the specified event register. - */ -__STATIC_INLINE uint32_t * nrf_timer_event_address_get(NRF_TIMER_Type * p_reg, - nrf_timer_event_t event); - -/** - * @brief Function for enabling specified shortcuts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] timer_shorts_mask Shortcuts to enable. - */ -__STATIC_INLINE void nrf_timer_shorts_enable(NRF_TIMER_Type * p_reg, - uint32_t timer_shorts_mask); - -/** - * @brief Function for disabling specified shortcuts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] timer_shorts_mask Shortcuts to disable. - */ -__STATIC_INLINE void nrf_timer_shorts_disable(NRF_TIMER_Type * p_reg, - uint32_t timer_shorts_mask); - -/** - * @brief Function for enabling specified interrupts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] timer_int_mask Interrupts to enable. - */ -__STATIC_INLINE void nrf_timer_int_enable(NRF_TIMER_Type * p_reg, - uint32_t timer_int_mask); - -/** - * @brief Function for disabling specified interrupts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] timer_int_mask Interrupts to disable. - */ -__STATIC_INLINE void nrf_timer_int_disable(NRF_TIMER_Type * p_reg, - uint32_t timer_int_mask); - -/** - * @brief Function for retrieving the state of a given interrupt. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] timer_int Interrupt to check. - * - * @retval true If the interrupt is enabled. - * @retval false If the interrupt is not enabled. - */ -__STATIC_INLINE bool nrf_timer_int_enable_check(NRF_TIMER_Type * p_reg, - uint32_t timer_int); - -/** - * @brief Function for setting the timer mode. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] mode Timer mode. - */ -__STATIC_INLINE void nrf_timer_mode_set(NRF_TIMER_Type * p_reg, - nrf_timer_mode_t mode); - -/** - * @brief Function for retrieving the timer mode. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * - * @return Timer mode. - */ -__STATIC_INLINE nrf_timer_mode_t nrf_timer_mode_get(NRF_TIMER_Type * p_reg); - -/** - * @brief Function for setting the timer bit width. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] bit_width Timer bit width. - */ -__STATIC_INLINE void nrf_timer_bit_width_set(NRF_TIMER_Type * p_reg, - nrf_timer_bit_width_t bit_width); - -/** - * @brief Function for retrieving the timer bit width. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * - * @return Timer bit width. - */ -__STATIC_INLINE nrf_timer_bit_width_t nrf_timer_bit_width_get(NRF_TIMER_Type * p_reg); - -/** - * @brief Function for setting the timer frequency. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] frequency Timer frequency. - */ -__STATIC_INLINE void nrf_timer_frequency_set(NRF_TIMER_Type * p_reg, - nrf_timer_frequency_t frequency); - -/** - * @brief Function for retrieving the timer frequency. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * - * @return Timer frequency. - */ -__STATIC_INLINE nrf_timer_frequency_t nrf_timer_frequency_get(NRF_TIMER_Type * p_reg); - -/** - * @brief Function for writing the capture/compare register for a specified channel. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] cc_channel Requested capture/compare channel. - * @param[in] cc_value Value to write to the capture/compare register. - */ -__STATIC_INLINE void nrf_timer_cc_write(NRF_TIMER_Type * p_reg, - nrf_timer_cc_channel_t cc_channel, - uint32_t cc_value); - -/** - * @brief Function for retrieving the capture/compare value for a specified channel. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] cc_channel Requested capture/compare channel. - * - * @return Value from the requested capture/compare register. - */ -__STATIC_INLINE uint32_t nrf_timer_cc_read(NRF_TIMER_Type * p_reg, - nrf_timer_cc_channel_t cc_channel); - -/** - * @brief Function for getting a specific timer capture task. - * - * @param[in] channel Capture channel. - * - * @return Capture task. - */ -__STATIC_INLINE nrf_timer_task_t nrf_timer_capture_task_get(uint32_t channel); - -/** - * @brief Function for getting a specific timer compare event. - * - * @param[in] channel Compare channel. - * - * @return Compare event. - */ -__STATIC_INLINE nrf_timer_event_t nrf_timer_compare_event_get(uint32_t channel); - -/** - * @brief Function for getting a specific timer compare interrupt. - * - * @param[in] channel Compare channel. - * - * @return Compare interrupt. - */ -__STATIC_INLINE nrf_timer_int_mask_t nrf_timer_compare_int_get(uint32_t channel); - -/** - * @brief Function for calculating the number of timer ticks for a given time - * (in microseconds) and timer frequency. - * - * @param[in] time_us Time in microseconds. - * @param[in] frequency Timer frequency. - * - * @return Number of timer ticks. - */ -__STATIC_INLINE uint32_t nrf_timer_us_to_ticks(uint32_t time_us, - nrf_timer_frequency_t frequency); - -/** - * @brief Function for calculating the number of timer ticks for a given time - * (in milliseconds) and timer frequency. - * - * @param[in] time_ms Time in milliseconds. - * @param[in] frequency Timer frequency. - * - * @return Number of timer ticks. - */ -__STATIC_INLINE uint32_t nrf_timer_ms_to_ticks(uint32_t time_ms, - nrf_timer_frequency_t frequency); - - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -__STATIC_INLINE void nrf_timer_task_trigger(NRF_TIMER_Type * p_reg, - nrf_timer_task_t task) -{ - *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; -} - -__STATIC_INLINE uint32_t * nrf_timer_task_address_get(NRF_TIMER_Type * p_reg, - nrf_timer_task_t task) -{ - return (uint32_t *)((uint8_t *)p_reg + (uint32_t)task); -} - -__STATIC_INLINE void nrf_timer_event_clear(NRF_TIMER_Type * p_reg, - nrf_timer_event_t event) -{ - *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif -} - -__STATIC_INLINE bool nrf_timer_event_check(NRF_TIMER_Type * p_reg, - nrf_timer_event_t event) -{ - return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event); -} - -__STATIC_INLINE uint32_t * nrf_timer_event_address_get(NRF_TIMER_Type * p_reg, - nrf_timer_event_t event) -{ - return (uint32_t *)((uint8_t *)p_reg + (uint32_t)event); -} - -__STATIC_INLINE void nrf_timer_shorts_enable(NRF_TIMER_Type * p_reg, - uint32_t timer_shorts_mask) -{ - p_reg->SHORTS |= timer_shorts_mask; -} - -__STATIC_INLINE void nrf_timer_shorts_disable(NRF_TIMER_Type * p_reg, - uint32_t timer_shorts_mask) -{ - p_reg->SHORTS &= ~(timer_shorts_mask); -} - -__STATIC_INLINE void nrf_timer_int_enable(NRF_TIMER_Type * p_reg, - uint32_t timer_int_mask) -{ - p_reg->INTENSET = timer_int_mask; -} - -__STATIC_INLINE void nrf_timer_int_disable(NRF_TIMER_Type * p_reg, - uint32_t timer_int_mask) -{ - p_reg->INTENCLR = timer_int_mask; -} - -__STATIC_INLINE bool nrf_timer_int_enable_check(NRF_TIMER_Type * p_reg, - uint32_t timer_int) -{ - return (bool)(p_reg->INTENSET & timer_int); -} - -__STATIC_INLINE void nrf_timer_mode_set(NRF_TIMER_Type * p_reg, - nrf_timer_mode_t mode) -{ - p_reg->MODE = (p_reg->MODE & ~TIMER_MODE_MODE_Msk) | - ((mode << TIMER_MODE_MODE_Pos) & TIMER_MODE_MODE_Msk); -} - -__STATIC_INLINE nrf_timer_mode_t nrf_timer_mode_get(NRF_TIMER_Type * p_reg) -{ - return (nrf_timer_mode_t)(p_reg->MODE); -} - -__STATIC_INLINE void nrf_timer_bit_width_set(NRF_TIMER_Type * p_reg, - nrf_timer_bit_width_t bit_width) -{ - p_reg->BITMODE = (p_reg->BITMODE & ~TIMER_BITMODE_BITMODE_Msk) | - ((bit_width << TIMER_BITMODE_BITMODE_Pos) & - TIMER_BITMODE_BITMODE_Msk); -} - -__STATIC_INLINE nrf_timer_bit_width_t nrf_timer_bit_width_get(NRF_TIMER_Type * p_reg) -{ - return (nrf_timer_bit_width_t)(p_reg->BITMODE); -} - -__STATIC_INLINE void nrf_timer_frequency_set(NRF_TIMER_Type * p_reg, - nrf_timer_frequency_t frequency) -{ - p_reg->PRESCALER = (p_reg->PRESCALER & ~TIMER_PRESCALER_PRESCALER_Msk) | - ((frequency << TIMER_PRESCALER_PRESCALER_Pos) & - TIMER_PRESCALER_PRESCALER_Msk); -} - -__STATIC_INLINE nrf_timer_frequency_t nrf_timer_frequency_get(NRF_TIMER_Type * p_reg) -{ - return (nrf_timer_frequency_t)(p_reg->PRESCALER); -} - -__STATIC_INLINE void nrf_timer_cc_write(NRF_TIMER_Type * p_reg, - nrf_timer_cc_channel_t cc_channel, - uint32_t cc_value) -{ - p_reg->CC[cc_channel] = cc_value; -} - -__STATIC_INLINE uint32_t nrf_timer_cc_read(NRF_TIMER_Type * p_reg, - nrf_timer_cc_channel_t cc_channel) -{ - return (uint32_t)p_reg->CC[cc_channel]; -} - -__STATIC_INLINE nrf_timer_task_t nrf_timer_capture_task_get(uint32_t channel) -{ - return (nrf_timer_task_t) - ((uint32_t)NRF_TIMER_TASK_CAPTURE0 + (channel * sizeof(uint32_t))); -} - -__STATIC_INLINE nrf_timer_event_t nrf_timer_compare_event_get(uint32_t channel) -{ - return (nrf_timer_event_t) - ((uint32_t)NRF_TIMER_EVENT_COMPARE0 + (channel * sizeof(uint32_t))); -} - -__STATIC_INLINE nrf_timer_int_mask_t nrf_timer_compare_int_get(uint32_t channel) -{ - return (nrf_timer_int_mask_t) - ((uint32_t)NRF_TIMER_INT_COMPARE0_MASK << channel); -} - -__STATIC_INLINE uint32_t nrf_timer_us_to_ticks(uint32_t time_us, - nrf_timer_frequency_t frequency) -{ - // The "frequency" parameter here is actually the prescaler value, and the - // timer runs at the following frequency: f = 16 MHz / 2^prescaler. - uint32_t prescaler = (uint32_t)frequency; - NRFX_ASSERT(time_us <= (UINT32_MAX / 16UL)); - return ((time_us * 16UL) >> prescaler); -} - -__STATIC_INLINE uint32_t nrf_timer_ms_to_ticks(uint32_t time_ms, - nrf_timer_frequency_t frequency) -{ - // The "frequency" parameter here is actually the prescaler value, and the - // timer runs at the following frequency: f = 16000 kHz / 2^prescaler. - uint32_t prescaler = (uint32_t)frequency; - NRFX_ASSERT(time_ms <= (UINT32_MAX / 16000UL)); - return ((time_ms * 16000UL) >> prescaler); -} - -#endif // SUPPRESS_INLINE_IMPLEMENTATION - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_TIMER_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_twi.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_twi.h deleted file mode 100644 index f8df53f7b3..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_twi.h +++ /dev/null @@ -1,451 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_TWI_H__ -#define NRF_TWI_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_twi_hal TWI HAL - * @{ - * @ingroup nrf_twi - * @brief Hardware access layer for managing the TWI peripheral. - */ - -/** - * @brief TWI tasks. - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_TWI_TASK_STARTRX = offsetof(NRF_TWI_Type, TASKS_STARTRX), ///< Start TWI receive sequence. - NRF_TWI_TASK_STARTTX = offsetof(NRF_TWI_Type, TASKS_STARTTX), ///< Start TWI transmit sequence. - NRF_TWI_TASK_STOP = offsetof(NRF_TWI_Type, TASKS_STOP), ///< Stop TWI transaction. - NRF_TWI_TASK_SUSPEND = offsetof(NRF_TWI_Type, TASKS_SUSPEND), ///< Suspend TWI transaction. - NRF_TWI_TASK_RESUME = offsetof(NRF_TWI_Type, TASKS_RESUME) ///< Resume TWI transaction. - /*lint -restore*/ -} nrf_twi_task_t; - -/** - * @brief TWI events. - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_TWI_EVENT_STOPPED = offsetof(NRF_TWI_Type, EVENTS_STOPPED), ///< TWI stopped. - NRF_TWI_EVENT_RXDREADY = offsetof(NRF_TWI_Type, EVENTS_RXDREADY), ///< TWI RXD byte received. - NRF_TWI_EVENT_TXDSENT = offsetof(NRF_TWI_Type, EVENTS_TXDSENT), ///< TWI TXD byte sent. - NRF_TWI_EVENT_ERROR = offsetof(NRF_TWI_Type, EVENTS_ERROR), ///< TWI error. - NRF_TWI_EVENT_BB = offsetof(NRF_TWI_Type, EVENTS_BB), ///< TWI byte boundary, generated before each byte that is sent or received. - NRF_TWI_EVENT_SUSPENDED = offsetof(NRF_TWI_Type, EVENTS_SUSPENDED) ///< TWI entered the suspended state. - /*lint -restore*/ -} nrf_twi_event_t; - -/** - * @brief TWI shortcuts. - */ -typedef enum -{ - NRF_TWI_SHORT_BB_SUSPEND_MASK = TWI_SHORTS_BB_SUSPEND_Msk, ///< Shortcut between BB event and SUSPEND task. - NRF_TWI_SHORT_BB_STOP_MASK = TWI_SHORTS_BB_STOP_Msk, ///< Shortcut between BB event and STOP task. - NRF_TWI_ALL_SHORTS_MASK = TWI_SHORTS_BB_SUSPEND_Msk | - TWI_SHORTS_BB_STOP_Msk ///< All TWI shortcuts. -} nrf_twi_short_mask_t; - -/** - * @brief TWI interrupts. - */ -typedef enum -{ - NRF_TWI_INT_STOPPED_MASK = TWI_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event. - NRF_TWI_INT_RXDREADY_MASK = TWI_INTENSET_RXDREADY_Msk, ///< Interrupt on RXDREADY event. - NRF_TWI_INT_TXDSENT_MASK = TWI_INTENSET_TXDSENT_Msk, ///< Interrupt on TXDSENT event. - NRF_TWI_INT_ERROR_MASK = TWI_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event. - NRF_TWI_INT_BB_MASK = TWI_INTENSET_BB_Msk, ///< Interrupt on BB event. - NRF_TWI_INT_SUSPENDED_MASK = TWI_INTENSET_SUSPENDED_Msk, ///< Interrupt on SUSPENDED event. - NRF_TWI_ALL_INTS_MASK = TWI_INTENSET_STOPPED_Msk | - TWI_INTENSET_RXDREADY_Msk | - TWI_INTENSET_TXDSENT_Msk | - TWI_INTENSET_ERROR_Msk | - TWI_INTENSET_BB_Msk | - TWI_INTENSET_SUSPENDED_Msk ///< All TWI interrupts. -} nrf_twi_int_mask_t; - -/** - * @brief TWI error source. - */ -typedef enum -{ - NRF_TWI_ERROR_ADDRESS_NACK = TWI_ERRORSRC_ANACK_Msk, ///< NACK received after sending the address. - NRF_TWI_ERROR_DATA_NACK = TWI_ERRORSRC_DNACK_Msk, ///< NACK received after sending a data byte. - NRF_TWI_ERROR_OVERRUN = TWI_ERRORSRC_OVERRUN_Msk ///< Overrun error. - /**< A new byte was received before the previous byte was read - * from the RXD register (previous data is lost). */ -} nrf_twi_error_t; - -/** - * @brief TWI master clock frequency. - */ -typedef enum -{ - NRF_TWI_FREQ_100K = TWI_FREQUENCY_FREQUENCY_K100, ///< 100 kbps. - NRF_TWI_FREQ_250K = TWI_FREQUENCY_FREQUENCY_K250, ///< 250 kbps. - NRF_TWI_FREQ_400K = TWI_FREQUENCY_FREQUENCY_K400 ///< 400 kbps. -} nrf_twi_frequency_t; - - -/** - * @brief Function for activating a specific TWI task. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] task Task to activate. - */ -__STATIC_INLINE void nrf_twi_task_trigger(NRF_TWI_Type * p_reg, - nrf_twi_task_t task); - -/** - * @brief Function for getting the address of a specific TWI task register. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] task Requested task. - * - * @return Address of the specified task register. - */ -__STATIC_INLINE uint32_t * nrf_twi_task_address_get(NRF_TWI_Type * p_reg, - nrf_twi_task_t task); - -/** - * @brief Function for clearing a specific TWI event. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] event Event to clear. - */ -__STATIC_INLINE void nrf_twi_event_clear(NRF_TWI_Type * p_reg, - nrf_twi_event_t event); - -/** - * @brief Function for checking the state of a specific event. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] event Event to check. - * - * @retval true If the event is set. - * @retval false If the event is not set. - */ -__STATIC_INLINE bool nrf_twi_event_check(NRF_TWI_Type * p_reg, - nrf_twi_event_t event); - -/** - * @brief Function for getting the address of a specific TWI event register. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] event Requested event. - * - * @return Address of the specified event register. - */ -__STATIC_INLINE uint32_t * nrf_twi_event_address_get(NRF_TWI_Type * p_reg, - nrf_twi_event_t event); - -/** - * @brief Function for enabling specified shortcuts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] shorts_mask Shortcuts to enable. - */ -__STATIC_INLINE void nrf_twi_shorts_enable(NRF_TWI_Type * p_reg, - uint32_t shorts_mask); - -/** - * @brief Function for disabling specified shortcuts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] shorts_mask Shortcuts to disable. - */ -__STATIC_INLINE void nrf_twi_shorts_disable(NRF_TWI_Type * p_reg, - uint32_t shorts_mask); - -/** - * @brief Function for enabling specified interrupts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] int_mask Interrupts to enable. - */ -__STATIC_INLINE void nrf_twi_int_enable(NRF_TWI_Type * p_reg, - uint32_t int_mask); - -/** - * @brief Function for disabling specified interrupts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] int_mask Interrupts to disable. - */ -__STATIC_INLINE void nrf_twi_int_disable(NRF_TWI_Type * p_reg, - uint32_t int_mask); - -/** - * @brief Function for retrieving the state of a given interrupt. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] int_mask Interrupt to check. - * - * @retval true If the interrupt is enabled. - * @retval false If the interrupt is not enabled. - */ -__STATIC_INLINE bool nrf_twi_int_enable_check(NRF_TWI_Type * p_reg, - nrf_twi_int_mask_t int_mask); - -/** - * @brief Function for enabling the TWI peripheral. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_twi_enable(NRF_TWI_Type * p_reg); - -/** - * @brief Function for disabling the TWI peripheral. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_twi_disable(NRF_TWI_Type * p_reg); - -/** - * @brief Function for configuring TWI pins. - * - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] scl_pin SCL pin number. - * @param[in] sda_pin SDA pin number. - */ -__STATIC_INLINE void nrf_twi_pins_set(NRF_TWI_Type * p_reg, - uint32_t scl_pin, - uint32_t sda_pin); - -/** - * @brief Function for setting the TWI master clock frequency. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] frequency TWI frequency. - */ -__STATIC_INLINE void nrf_twi_frequency_set(NRF_TWI_Type * p_reg, - nrf_twi_frequency_t frequency); - -/** - * @brief Function for checking the TWI error source. - * - * The error flags are cleared after reading. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * - * @return Mask with error source flags. - */ -__STATIC_INLINE uint32_t nrf_twi_errorsrc_get_and_clear(NRF_TWI_Type * p_reg); - -/** - * @brief Function for setting the address to be used in TWI transfers. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] address Address to be used in transfers. - */ -__STATIC_INLINE void nrf_twi_address_set(NRF_TWI_Type * p_reg, uint8_t address); - -/** - * @brief Function for reading data received by TWI. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * - * @return Received data. - */ -__STATIC_INLINE uint8_t nrf_twi_rxd_get(NRF_TWI_Type * p_reg); - -/** - * @brief Function for writing data to be transmitted by TWI. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] data Data to be transmitted. - */ -__STATIC_INLINE void nrf_twi_txd_set(NRF_TWI_Type * p_reg, uint8_t data); - -__STATIC_INLINE void nrf_twi_shorts_set(NRF_TWI_Type * p_reg, - uint32_t shorts_mask); - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -__STATIC_INLINE void nrf_twi_task_trigger(NRF_TWI_Type * p_reg, - nrf_twi_task_t task) -{ - *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; -} - -__STATIC_INLINE uint32_t * nrf_twi_task_address_get(NRF_TWI_Type * p_reg, - nrf_twi_task_t task) -{ - return (uint32_t *)((uint8_t *)p_reg + (uint32_t)task); -} - -__STATIC_INLINE void nrf_twi_event_clear(NRF_TWI_Type * p_reg, - nrf_twi_event_t event) -{ - *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif -} - -__STATIC_INLINE bool nrf_twi_event_check(NRF_TWI_Type * p_reg, - nrf_twi_event_t event) -{ - return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event); -} - -__STATIC_INLINE uint32_t * nrf_twi_event_address_get(NRF_TWI_Type * p_reg, - nrf_twi_event_t event) -{ - return (uint32_t *)((uint8_t *)p_reg + (uint32_t)event); -} - -__STATIC_INLINE void nrf_twi_shorts_enable(NRF_TWI_Type * p_reg, - uint32_t shorts_mask) -{ - p_reg->SHORTS |= shorts_mask; -} - -__STATIC_INLINE void nrf_twi_shorts_disable(NRF_TWI_Type * p_reg, - uint32_t shorts_mask) -{ - p_reg->SHORTS &= ~(shorts_mask); -} - -__STATIC_INLINE void nrf_twi_int_enable(NRF_TWI_Type * p_reg, - uint32_t int_mask) -{ - p_reg->INTENSET = int_mask; -} - -__STATIC_INLINE void nrf_twi_int_disable(NRF_TWI_Type * p_reg, - uint32_t int_mask) -{ - p_reg->INTENCLR = int_mask; -} - -__STATIC_INLINE bool nrf_twi_int_enable_check(NRF_TWI_Type * p_reg, - nrf_twi_int_mask_t int_mask) -{ - return (bool)(p_reg->INTENSET & int_mask); -} - -__STATIC_INLINE void nrf_twi_enable(NRF_TWI_Type * p_reg) -{ - p_reg->ENABLE = (TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos); -} - -__STATIC_INLINE void nrf_twi_disable(NRF_TWI_Type * p_reg) -{ - p_reg->ENABLE = (TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos); -} - -__STATIC_INLINE void nrf_twi_pins_set(NRF_TWI_Type * p_reg, - uint32_t scl_pin, - uint32_t sda_pin) -{ -#if defined(TWI_PSEL_SCL_CONNECT_Pos) - p_reg->PSEL.SCL = scl_pin; -#else - p_reg->PSELSCL = scl_pin; -#endif - -#if defined(TWI_PSEL_SDA_CONNECT_Pos) - p_reg->PSEL.SDA = sda_pin; -#else - p_reg->PSELSDA = sda_pin; -#endif -} - -__STATIC_INLINE void nrf_twi_frequency_set(NRF_TWI_Type * p_reg, - nrf_twi_frequency_t frequency) -{ - p_reg->FREQUENCY = frequency; -} - -__STATIC_INLINE uint32_t nrf_twi_errorsrc_get_and_clear(NRF_TWI_Type * p_reg) -{ - uint32_t error_source = p_reg->ERRORSRC; - - // [error flags are cleared by writing '1' on their position] - p_reg->ERRORSRC = error_source; - - return error_source; -} - -__STATIC_INLINE void nrf_twi_address_set(NRF_TWI_Type * p_reg, uint8_t address) -{ - p_reg->ADDRESS = address; -} - -__STATIC_INLINE uint8_t nrf_twi_rxd_get(NRF_TWI_Type * p_reg) -{ - return (uint8_t)p_reg->RXD; -} - -__STATIC_INLINE void nrf_twi_txd_set(NRF_TWI_Type * p_reg, uint8_t data) -{ - p_reg->TXD = data; -} - -__STATIC_INLINE void nrf_twi_shorts_set(NRF_TWI_Type * p_reg, - uint32_t shorts_mask) -{ - p_reg->SHORTS = shorts_mask; -} - -#endif // SUPPRESS_INLINE_IMPLEMENTATION - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_TWI_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_twim.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_twim.h deleted file mode 100644 index 515bee43d9..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_twim.h +++ /dev/null @@ -1,522 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_TWIM_H__ -#define NRF_TWIM_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_twim_hal TWIM HAL - * @{ - * @ingroup nrf_twim - * @brief Hardware access layer for managing the TWIM peripheral. - */ - -/** - * @brief TWIM tasks. - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_TWIM_TASK_STARTRX = offsetof(NRF_TWIM_Type, TASKS_STARTRX), ///< Start TWI receive sequence. - NRF_TWIM_TASK_STARTTX = offsetof(NRF_TWIM_Type, TASKS_STARTTX), ///< Start TWI transmit sequence. - NRF_TWIM_TASK_STOP = offsetof(NRF_TWIM_Type, TASKS_STOP), ///< Stop TWI transaction. - NRF_TWIM_TASK_SUSPEND = offsetof(NRF_TWIM_Type, TASKS_SUSPEND), ///< Suspend TWI transaction. - NRF_TWIM_TASK_RESUME = offsetof(NRF_TWIM_Type, TASKS_RESUME) ///< Resume TWI transaction. - /*lint -restore*/ -} nrf_twim_task_t; - -/** - * @brief TWIM events. - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_TWIM_EVENT_STOPPED = offsetof(NRF_TWIM_Type, EVENTS_STOPPED), ///< TWI stopped. - NRF_TWIM_EVENT_ERROR = offsetof(NRF_TWIM_Type, EVENTS_ERROR), ///< TWI error. - NRF_TWIM_EVENT_SUSPENDED = 0x148, ///< TWI suspended. - NRF_TWIM_EVENT_RXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_RXSTARTED), ///< Receive sequence started. - NRF_TWIM_EVENT_TXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_TXSTARTED), ///< Transmit sequence started. - NRF_TWIM_EVENT_LASTRX = offsetof(NRF_TWIM_Type, EVENTS_LASTRX), ///< Byte boundary, starting to receive the last byte. - NRF_TWIM_EVENT_LASTTX = offsetof(NRF_TWIM_Type, EVENTS_LASTTX) ///< Byte boundary, starting to transmit the last byte. - /*lint -restore*/ -} nrf_twim_event_t; - -/** - * @brief TWIM shortcuts. - */ -typedef enum -{ - NRF_TWIM_SHORT_LASTTX_STARTRX_MASK = TWIM_SHORTS_LASTTX_STARTRX_Msk, ///< Shortcut between LASTTX event and STARTRX task. - NRF_TWIM_SHORT_LASTTX_SUSPEND_MASK = TWIM_SHORTS_LASTTX_SUSPEND_Msk, ///< Shortcut between LASTTX event and SUSPEND task. - NRF_TWIM_SHORT_LASTTX_STOP_MASK = TWIM_SHORTS_LASTTX_STOP_Msk, ///< Shortcut between LASTTX event and STOP task. - NRF_TWIM_SHORT_LASTRX_STARTTX_MASK = TWIM_SHORTS_LASTRX_STARTTX_Msk, ///< Shortcut between LASTRX event and STARTTX task. - NRF_TWIM_SHORT_LASTRX_STOP_MASK = TWIM_SHORTS_LASTRX_STOP_Msk, ///< Shortcut between LASTRX event and STOP task. - NRF_TWIM_ALL_SHORTS_MASK = TWIM_SHORTS_LASTTX_STARTRX_Msk | - TWIM_SHORTS_LASTTX_SUSPEND_Msk | - TWIM_SHORTS_LASTTX_STOP_Msk | - TWIM_SHORTS_LASTRX_STARTTX_Msk | - TWIM_SHORTS_LASTRX_STOP_Msk ///< All TWIM shortcuts. -} nrf_twim_short_mask_t; - -/** - * @brief TWIM interrupts. - */ -typedef enum -{ - NRF_TWIM_INT_STOPPED_MASK = TWIM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event. - NRF_TWIM_INT_ERROR_MASK = TWIM_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event. - NRF_TWIM_INT_SUSPENDED_MASK = TWIM_INTENSET_SUSPENDED_Msk, ///< Interrupt on SUSPENDED event. - NRF_TWIM_INT_RXSTARTED_MASK = TWIM_INTENSET_RXSTARTED_Msk, ///< Interrupt on RXSTARTED event. - NRF_TWIM_INT_TXSTARTED_MASK = TWIM_INTENSET_TXSTARTED_Msk, ///< Interrupt on TXSTARTED event. - NRF_TWIM_INT_LASTRX_MASK = TWIM_INTENSET_LASTRX_Msk, ///< Interrupt on LASTRX event. - NRF_TWIM_INT_LASTTX_MASK = TWIM_INTENSET_LASTTX_Msk, ///< Interrupt on LASTTX event. - NRF_TWIM_ALL_INTS_MASK = TWIM_INTENSET_STOPPED_Msk | - TWIM_INTENSET_ERROR_Msk | - TWIM_INTENSET_SUSPENDED_Msk | - TWIM_INTENSET_RXSTARTED_Msk | - TWIM_INTENSET_TXSTARTED_Msk | - TWIM_INTENSET_LASTRX_Msk | - TWIM_INTENSET_LASTTX_Msk ///< Interrupt on LASTTX event. -} nrf_twim_int_mask_t; - -/** - * @brief TWIM master clock frequency. - */ -typedef enum -{ - NRF_TWIM_FREQ_100K = TWIM_FREQUENCY_FREQUENCY_K100, ///< 100 kbps. - NRF_TWIM_FREQ_250K = TWIM_FREQUENCY_FREQUENCY_K250, ///< 250 kbps. - NRF_TWIM_FREQ_400K = TWIM_FREQUENCY_FREQUENCY_K400 ///< 400 kbps. -} nrf_twim_frequency_t; - -/** - * @brief TWIM error source. - */ -typedef enum -{ - NRF_TWIM_ERROR_ADDRESS_NACK = TWIM_ERRORSRC_ANACK_Msk, ///< NACK received after sending the address. - NRF_TWIM_ERROR_DATA_NACK = TWIM_ERRORSRC_DNACK_Msk ///< NACK received after sending a data byte. -} nrf_twim_error_t; - - -/** - * @brief Function for activating a specific TWIM task. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] task Task to activate. - */ -__STATIC_INLINE void nrf_twim_task_trigger(NRF_TWIM_Type * p_reg, - nrf_twim_task_t task); - -/** - * @brief Function for getting the address of a specific TWIM task register. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] task Requested task. - * - * @return Address of the specified task register. - */ -__STATIC_INLINE uint32_t * nrf_twim_task_address_get(NRF_TWIM_Type * p_reg, - nrf_twim_task_t task); - -/** - * @brief Function for clearing a specific TWIM event. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] event Event to clear. - */ -__STATIC_INLINE void nrf_twim_event_clear(NRF_TWIM_Type * p_reg, - nrf_twim_event_t event); - -/** - * @brief Function for checking the state of a specific TWIM event. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] event Event to check. - * - * @retval true If the event is set. - * @retval false If the event is not set. - */ -__STATIC_INLINE bool nrf_twim_event_check(NRF_TWIM_Type * p_reg, - nrf_twim_event_t event); - -/** - * @brief Function for getting the address of a specific TWIM event register. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] event Requested event. - * - * @return Address of the specified event register. - */ -__STATIC_INLINE uint32_t * nrf_twim_event_address_get(NRF_TWIM_Type * p_reg, - nrf_twim_event_t event); - -/** - * @brief Function for enabling specified shortcuts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] shorts_mask Shortcuts to enable. - */ -__STATIC_INLINE void nrf_twim_shorts_enable(NRF_TWIM_Type * p_reg, - uint32_t shorts_mask); - -/** - * @brief Function for disabling specified shortcuts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] shorts_mask Shortcuts to disable. - */ -__STATIC_INLINE void nrf_twim_shorts_disable(NRF_TWIM_Type * p_reg, - uint32_t shorts_mask); - -/** - * @brief Function for enabling specified interrupts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] int_mask Interrupts to enable. - */ -__STATIC_INLINE void nrf_twim_int_enable(NRF_TWIM_Type * p_reg, - uint32_t int_mask); - -/** - * @brief Function for disabling specified interrupts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] int_mask Interrupts to disable. - */ -__STATIC_INLINE void nrf_twim_int_disable(NRF_TWIM_Type * p_reg, - uint32_t int_mask); - -/** - * @brief Function for checking the state of a given interrupt. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] int_mask Interrupt to check. - * - * @retval true If the interrupt is enabled. - * @retval false If the interrupt is not enabled. - */ -__STATIC_INLINE bool nrf_twim_int_enable_check(NRF_TWIM_Type * p_reg, - nrf_twim_int_mask_t int_mask); - -/** - * @brief Function for enabling the TWIM peripheral. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_twim_enable(NRF_TWIM_Type * p_reg); - -/** - * @brief Function for disabling the TWIM peripheral. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_twim_disable(NRF_TWIM_Type * p_reg); - -/** - * @brief Function for configuring TWI pins. - * - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] scl_pin SCL pin number. - * @param[in] sda_pin SDA pin number. - */ -__STATIC_INLINE void nrf_twim_pins_set(NRF_TWIM_Type * p_reg, - uint32_t scl_pin, - uint32_t sda_pin); - -/** - * @brief Function for setting the TWI master clock frequency. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] frequency TWI frequency. - */ -__STATIC_INLINE void nrf_twim_frequency_set(NRF_TWIM_Type * p_reg, - nrf_twim_frequency_t frequency); - -/** - * @brief Function for checking the TWI error source. - * - * The error flags are cleared after reading. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * - * @return Mask with error source flags. - */ -__STATIC_INLINE uint32_t nrf_twim_errorsrc_get_and_clear(NRF_TWIM_Type * p_reg); - -/** - * @brief Function for setting the address to be used in TWI transfers. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] address Address to be used in transfers. - */ -__STATIC_INLINE void nrf_twim_address_set(NRF_TWIM_Type * p_reg, - uint8_t address); - -/** - * @brief Function for setting the transmit buffer. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] p_buffer Pointer to the buffer with data to send. - * @param[in] length Maximum number of data bytes to transmit. - */ -__STATIC_INLINE void nrf_twim_tx_buffer_set(NRF_TWIM_Type * p_reg, - uint8_t const * p_buffer, - size_t length); - -/** - * @brief Function for setting the receive buffer. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] p_buffer Pointer to the buffer for received data. - * @param[in] length Maximum number of data bytes to receive. - */ -__STATIC_INLINE void nrf_twim_rx_buffer_set(NRF_TWIM_Type * p_reg, - uint8_t * p_buffer, - size_t length); - -__STATIC_INLINE void nrf_twim_shorts_set(NRF_TWIM_Type * p_reg, - uint32_t shorts_mask); - -__STATIC_INLINE size_t nrf_twim_txd_amount_get(NRF_TWIM_Type * p_reg); - -__STATIC_INLINE size_t nrf_twim_rxd_amount_get(NRF_TWIM_Type * p_reg); - -/** - * @brief Function for enabling the TX list feature. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_twim_tx_list_enable(NRF_TWIM_Type * p_reg); - -/** - * @brief Function for disabling the TX list feature. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_twim_tx_list_disable(NRF_TWIM_Type * p_reg); - -/** - * @brief Function for enabling the RX list feature. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_twim_rx_list_enable(NRF_TWIM_Type * p_reg); - -/** - * @brief Function for disabling the RX list feature. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_twim_rx_list_disable(NRF_TWIM_Type * p_reg); - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -__STATIC_INLINE void nrf_twim_task_trigger(NRF_TWIM_Type * p_reg, - nrf_twim_task_t task) -{ - *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; -} - -__STATIC_INLINE uint32_t * nrf_twim_task_address_get(NRF_TWIM_Type * p_reg, - nrf_twim_task_t task) -{ - return (uint32_t *)((uint8_t *)p_reg + (uint32_t)task); -} - -__STATIC_INLINE void nrf_twim_event_clear(NRF_TWIM_Type * p_reg, - nrf_twim_event_t event) -{ - *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif -} - -__STATIC_INLINE bool nrf_twim_event_check(NRF_TWIM_Type * p_reg, - nrf_twim_event_t event) -{ - return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event); -} - -__STATIC_INLINE uint32_t * nrf_twim_event_address_get(NRF_TWIM_Type * p_reg, - nrf_twim_event_t event) -{ - return (uint32_t *)((uint8_t *)p_reg + (uint32_t)event); -} - -__STATIC_INLINE void nrf_twim_shorts_enable(NRF_TWIM_Type * p_reg, - uint32_t shorts_mask) -{ - p_reg->SHORTS |= shorts_mask; -} - -__STATIC_INLINE void nrf_twim_shorts_disable(NRF_TWIM_Type * p_reg, - uint32_t shorts_mask) -{ - p_reg->SHORTS &= ~(shorts_mask); -} - -__STATIC_INLINE void nrf_twim_int_enable(NRF_TWIM_Type * p_reg, - uint32_t int_mask) -{ - p_reg->INTENSET = int_mask; -} - -__STATIC_INLINE void nrf_twim_int_disable(NRF_TWIM_Type * p_reg, - uint32_t int_mask) -{ - p_reg->INTENCLR = int_mask; -} - -__STATIC_INLINE bool nrf_twim_int_enable_check(NRF_TWIM_Type * p_reg, - nrf_twim_int_mask_t int_mask) -{ - return (bool)(p_reg->INTENSET & int_mask); -} - -__STATIC_INLINE void nrf_twim_enable(NRF_TWIM_Type * p_reg) -{ - p_reg->ENABLE = (TWIM_ENABLE_ENABLE_Enabled << TWIM_ENABLE_ENABLE_Pos); -} - -__STATIC_INLINE void nrf_twim_disable(NRF_TWIM_Type * p_reg) -{ - p_reg->ENABLE = (TWIM_ENABLE_ENABLE_Disabled << TWIM_ENABLE_ENABLE_Pos); -} - -__STATIC_INLINE void nrf_twim_pins_set(NRF_TWIM_Type * p_reg, - uint32_t scl_pin, - uint32_t sda_pin) -{ - p_reg->PSEL.SCL = scl_pin; - p_reg->PSEL.SDA = sda_pin; -} - -__STATIC_INLINE void nrf_twim_frequency_set(NRF_TWIM_Type * p_reg, - nrf_twim_frequency_t frequency) -{ - p_reg->FREQUENCY = frequency; -} - -__STATIC_INLINE uint32_t nrf_twim_errorsrc_get_and_clear(NRF_TWIM_Type * p_reg) -{ - uint32_t error_source = p_reg->ERRORSRC; - - // [error flags are cleared by writing '1' on their position] - p_reg->ERRORSRC = error_source; - - return error_source; -} - -__STATIC_INLINE void nrf_twim_address_set(NRF_TWIM_Type * p_reg, - uint8_t address) -{ - p_reg->ADDRESS = address; -} - -__STATIC_INLINE void nrf_twim_tx_buffer_set(NRF_TWIM_Type * p_reg, - uint8_t const * p_buffer, - size_t length) -{ - p_reg->TXD.PTR = (uint32_t)p_buffer; - p_reg->TXD.MAXCNT = length; -} - -__STATIC_INLINE void nrf_twim_rx_buffer_set(NRF_TWIM_Type * p_reg, - uint8_t * p_buffer, - size_t length) -{ - p_reg->RXD.PTR = (uint32_t)p_buffer; - p_reg->RXD.MAXCNT = length; -} - -__STATIC_INLINE void nrf_twim_shorts_set(NRF_TWIM_Type * p_reg, - uint32_t shorts_mask) -{ - p_reg->SHORTS = shorts_mask; -} - -__STATIC_INLINE size_t nrf_twim_txd_amount_get(NRF_TWIM_Type * p_reg) -{ - return p_reg->TXD.AMOUNT; -} - -__STATIC_INLINE size_t nrf_twim_rxd_amount_get(NRF_TWIM_Type * p_reg) -{ - return p_reg->RXD.AMOUNT; -} - -__STATIC_INLINE void nrf_twim_tx_list_enable(NRF_TWIM_Type * p_reg) -{ - p_reg->TXD.LIST = 1; -} - -__STATIC_INLINE void nrf_twim_tx_list_disable(NRF_TWIM_Type * p_reg) -{ - p_reg->TXD.LIST = 0; -} - -__STATIC_INLINE void nrf_twim_rx_list_enable(NRF_TWIM_Type * p_reg) -{ - p_reg->RXD.LIST = 1; -} - -__STATIC_INLINE void nrf_twim_rx_list_disable(NRF_TWIM_Type * p_reg) -{ - p_reg->RXD.LIST = 0; -} -#endif // SUPPRESS_INLINE_IMPLEMENTATION - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_TWIM_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_twis.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_twis.h deleted file mode 100644 index ccbf173e8d..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_twis.h +++ /dev/null @@ -1,702 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_TWIS_H__ -#define NRF_TWIS_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_twis_hal TWIS HAL - * @{ - * @ingroup nrf_twis - * @brief Hardware access layer for managing the Two Wire Interface Slave with EasyDMA - * (TWIS) peripheral. - */ - -/** - * @brief TWIS tasks - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_TWIS_TASK_STOP = offsetof(NRF_TWIS_Type, TASKS_STOP), /**< Stop TWIS transaction */ - NRF_TWIS_TASK_SUSPEND = offsetof(NRF_TWIS_Type, TASKS_SUSPEND), /**< Suspend TWIS transaction */ - NRF_TWIS_TASK_RESUME = offsetof(NRF_TWIS_Type, TASKS_RESUME), /**< Resume TWIS transaction */ - NRF_TWIS_TASK_PREPARERX = offsetof(NRF_TWIS_Type, TASKS_PREPARERX), /**< Prepare the TWIS slave to respond to a write command */ - NRF_TWIS_TASK_PREPARETX = offsetof(NRF_TWIS_Type, TASKS_PREPARETX) /**< Prepare the TWIS slave to respond to a read command */ - /*lint -restore*/ -} nrf_twis_task_t; - -/** - * @brief TWIS events - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_TWIS_EVENT_STOPPED = offsetof(NRF_TWIS_Type, EVENTS_STOPPED), /**< TWIS stopped */ - NRF_TWIS_EVENT_ERROR = offsetof(NRF_TWIS_Type, EVENTS_ERROR), /**< TWIS error */ - NRF_TWIS_EVENT_RXSTARTED = offsetof(NRF_TWIS_Type, EVENTS_RXSTARTED), /**< Receive sequence started */ - NRF_TWIS_EVENT_TXSTARTED = offsetof(NRF_TWIS_Type, EVENTS_TXSTARTED), /**< Transmit sequence started */ - NRF_TWIS_EVENT_WRITE = offsetof(NRF_TWIS_Type, EVENTS_WRITE), /**< Write command received */ - NRF_TWIS_EVENT_READ = offsetof(NRF_TWIS_Type, EVENTS_READ) /**< Read command received */ - /*lint -restore*/ -} nrf_twis_event_t; - -/** - * @brief TWIS shortcuts - */ -typedef enum -{ - NRF_TWIS_SHORT_WRITE_SUSPEND_MASK = TWIS_SHORTS_WRITE_SUSPEND_Msk, /**< Shortcut between WRITE event and SUSPEND task */ - NRF_TWIS_SHORT_READ_SUSPEND_MASK = TWIS_SHORTS_READ_SUSPEND_Msk, /**< Shortcut between READ event and SUSPEND task */ -} nrf_twis_short_mask_t; - -/** - * @brief TWIS interrupts - */ -typedef enum -{ - NRF_TWIS_INT_STOPPED_MASK = TWIS_INTEN_STOPPED_Msk, /**< Interrupt on STOPPED event */ - NRF_TWIS_INT_ERROR_MASK = TWIS_INTEN_ERROR_Msk, /**< Interrupt on ERROR event */ - NRF_TWIS_INT_RXSTARTED_MASK = TWIS_INTEN_RXSTARTED_Msk, /**< Interrupt on RXSTARTED event */ - NRF_TWIS_INT_TXSTARTED_MASK = TWIS_INTEN_TXSTARTED_Msk, /**< Interrupt on TXSTARTED event */ - NRF_TWIS_INT_WRITE_MASK = TWIS_INTEN_WRITE_Msk, /**< Interrupt on WRITE event */ - NRF_TWIS_INT_READ_MASK = TWIS_INTEN_READ_Msk, /**< Interrupt on READ event */ -} nrf_twis_int_mask_t; - -/** - * @brief TWIS error source - */ -typedef enum -{ - NRF_TWIS_ERROR_OVERFLOW = TWIS_ERRORSRC_OVERFLOW_Msk, /**< RX buffer overflow detected, and prevented */ - NRF_TWIS_ERROR_DATA_NACK = TWIS_ERRORSRC_DNACK_Msk, /**< NACK sent after receiving a data byte */ - NRF_TWIS_ERROR_OVERREAD = TWIS_ERRORSRC_OVERREAD_Msk /**< TX buffer over-read detected, and prevented */ -} nrf_twis_error_t; - -/** - * @brief TWIS address matching configuration - */ -typedef enum -{ - NRF_TWIS_CONFIG_ADDRESS0_MASK = TWIS_CONFIG_ADDRESS0_Msk, /**< Enable or disable address matching on ADDRESS[0] */ - NRF_TWIS_CONFIG_ADDRESS1_MASK = TWIS_CONFIG_ADDRESS1_Msk, /**< Enable or disable address matching on ADDRESS[1] */ - NRF_TWIS_CONFIG_ADDRESS01_MASK = TWIS_CONFIG_ADDRESS0_Msk | TWIS_CONFIG_ADDRESS1_Msk /**< Enable both address matching */ -} nrf_twis_config_addr_mask_t; - -/** - * @brief Variable type to hold amount of data for EasyDMA - * - * Variable of the minimum size that can hold the amount of data to transfer. - * - * @note - * Defined to make it simple to change if EasyDMA would be updated to support more data in - * the future devices to. - */ -typedef uint8_t nrf_twis_amount_t; - -/** - * @brief Smallest variable type to hold TWI address - * - * Variable of the minimum size that can hold single TWI address. - * - * @note - * Defined to make it simple to change if new TWI would support for example - * 10 bit addressing mode. - */ -typedef uint8_t nrf_twis_address_t; - - -/** - * @brief Function for activating a specific TWIS task. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param task Task. - */ -__STATIC_INLINE void nrf_twis_task_trigger(NRF_TWIS_Type * const p_reg, nrf_twis_task_t task); - -/** - * @brief Function for returning the address of a specific TWIS task register. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param task Task. - * - * @return Task address. - */ -__STATIC_INLINE uint32_t nrf_twis_task_address_get( - NRF_TWIS_Type const * const p_reg, - nrf_twis_task_t task); - -/** - * @brief Function for clearing a specific event. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param event Event. - */ -__STATIC_INLINE void nrf_twis_event_clear( - NRF_TWIS_Type * const p_reg, - nrf_twis_event_t event); -/** - * @brief Function for returning the state of a specific event. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param event Event. - * - * @retval true If the event is set. - * @retval false If the event is not set. - */ -__STATIC_INLINE bool nrf_twis_event_check( - NRF_TWIS_Type const * const p_reg, - nrf_twis_event_t event); - - -/** - * @brief Function for getting and clearing the state of specific event - * - * This function checks the state of the event and clears it. - * @param[in,out] p_reg Pointer to the peripheral registers structure. - * @param event Event. - * - * @retval true If the event was set. - * @retval false If the event was not set. - */ -__STATIC_INLINE bool nrf_twis_event_get_and_clear( - NRF_TWIS_Type * const p_reg, - nrf_twis_event_t event); - - -/** - * @brief Function for returning the address of a specific TWIS event register. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param event Event. - * - * @return Address. - */ -__STATIC_INLINE uint32_t nrf_twis_event_address_get( - NRF_TWIS_Type const * const p_reg, - nrf_twis_event_t event); - -/** - * @brief Function for setting a shortcut. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param short_mask Shortcuts mask. - */ -__STATIC_INLINE void nrf_twis_shorts_enable(NRF_TWIS_Type * const p_reg, uint32_t short_mask); - -/** - * @brief Function for clearing shortcuts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param short_mask Shortcuts mask. - */ -__STATIC_INLINE void nrf_twis_shorts_disable(NRF_TWIS_Type * const p_reg, uint32_t short_mask); - -/** - * @brief Get the shorts mask - * - * Function returns shorts register. - * @param[in] p_reg Pointer to the peripheral registers structure. - * @return Flags of currently enabled shortcuts - */ -__STATIC_INLINE uint32_t nrf_twis_shorts_get(NRF_TWIS_Type * const p_reg); - -/** - * @brief Function for enabling selected interrupts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param int_mask Interrupts mask. - */ -__STATIC_INLINE void nrf_twis_int_enable(NRF_TWIS_Type * const p_reg, uint32_t int_mask); - -/** - * @brief Function for retrieving the state of selected interrupts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param int_mask Interrupts mask. - * - * @retval true If any of selected interrupts is enabled. - * @retval false If none of selected interrupts is enabled. - */ -__STATIC_INLINE bool nrf_twis_int_enable_check(NRF_TWIS_Type const * const p_reg, uint32_t int_mask); - -/** - * @brief Function for disabling selected interrupts. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param int_mask Interrupts mask. - */ -__STATIC_INLINE void nrf_twis_int_disable(NRF_TWIS_Type * const p_reg, uint32_t int_mask); - -/** - * @brief Function for retrieving and clearing the TWIS error source. - * - * @attention Error sources are cleared after read. - * @param[in] p_reg Pointer to the peripheral registers structure. - * @return Error source mask with values from @ref nrf_twis_error_t. - */ -__STATIC_INLINE uint32_t nrf_twis_error_source_get_and_clear(NRF_TWIS_Type * const p_reg); - -/** - * @brief Get information which of addresses matched - * - * Function returns index in the address table - * that points to the address that already matched. - * @param[in] p_reg Pointer to the peripheral registers structure. - * @return Index of matched address - */ -__STATIC_INLINE uint_fast8_t nrf_twis_match_get(NRF_TWIS_Type const * p_reg); - -/** - * @brief Function for enabling TWIS. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_twis_enable(NRF_TWIS_Type * const p_reg); - -/** - * @brief Function for disabling TWIS. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_twis_disable(NRF_TWIS_Type * const p_reg); - -/** - * @brief Function for configuring TWIS pins. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param scl SCL pin number. - * @param sda SDA pin number. - */ -__STATIC_INLINE void nrf_twis_pins_set(NRF_TWIS_Type * const p_reg, uint32_t scl, uint32_t sda); - -/** - * @brief Function for setting the receive buffer. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param p_buf Pointer to the buffer for received data. - * @param length Maximum number of data bytes to receive. - */ -__STATIC_INLINE void nrf_twis_rx_buffer_set( - NRF_TWIS_Type * const p_reg, - uint8_t * p_buf, - nrf_twis_amount_t length); - -/** - * @brief Function that prepares TWIS for receiving - * - * This function sets receive buffer and then sets NRF_TWIS_TASK_PREPARERX task. - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param p_buf Pointer to the buffer for received data. - * @param length Maximum number of data bytes to receive. - */ -__STATIC_INLINE void nrf_twis_rx_prepare( - NRF_TWIS_Type * const p_reg, - uint8_t * p_buf, - nrf_twis_amount_t length); - -/** - * @brief Function for getting number of bytes received in the last transaction. - * - * @param[in] p_reg TWIS instance. - * @return Amount of bytes received. - * */ -__STATIC_INLINE nrf_twis_amount_t nrf_twis_rx_amount_get(NRF_TWIS_Type const * const p_reg); - -/** - * @brief Function for setting the transmit buffer. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param p_buf Pointer to the buffer with data to send. - * @param length Maximum number of data bytes to transmit. - */ -__STATIC_INLINE void nrf_twis_tx_buffer_set( - NRF_TWIS_Type * const p_reg, - uint8_t const * p_buf, - nrf_twis_amount_t length); - -/** - * @brief Function that prepares TWIS for transmitting - * - * This function sets transmit buffer and then sets NRF_TWIS_TASK_PREPARETX task. - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param p_buf Pointer to the buffer with data to send. - * @param length Maximum number of data bytes to transmit. - */ -__STATIC_INLINE void nrf_twis_tx_prepare( - NRF_TWIS_Type * const p_reg, - uint8_t const * p_buf, - nrf_twis_amount_t length); - -/** - * @brief Function for getting number of bytes transmitted in the last transaction. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @return Amount of bytes transmitted. - */ -__STATIC_INLINE nrf_twis_amount_t nrf_twis_tx_amount_get(NRF_TWIS_Type const * const p_reg); - -/** - * @brief Function for setting slave address - * - * Function sets the selected address for this TWI interface. - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param n Index of address to set - * @param addr Addres to set - * @sa nrf_twis_config_address_set - * @sa nrf_twis_config_address_get - */ -__STATIC_INLINE void nrf_twis_address_set( - NRF_TWIS_Type * const p_reg, - uint_fast8_t n, - nrf_twis_address_t addr); - -/** - * @brief Function for retrieving configured slave address - * - * Function gets the selected address for this TWI interface. - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param n Index of address to get - */ -__STATIC_INLINE nrf_twis_address_t nrf_twis_address_get( - NRF_TWIS_Type const * const p_reg, - uint_fast8_t n); - -/** - * @brief Function for setting the device address configuration. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param addr_mask Mask of address indexes of what device should answer to. - * - * @sa nrf_twis_address_set - */ -__STATIC_INLINE void nrf_twis_config_address_set( - NRF_TWIS_Type * const p_reg, - nrf_twis_config_addr_mask_t addr_mask); - -/** - * @brief Function for retrieving the device address configuration. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * - * @return Mask of address indexes of what device should answer to. - */ -__STATIC_INLINE nrf_twis_config_addr_mask_t nrf_twis_config_address_get( - NRF_TWIS_Type const * const p_reg); - -/** - * @brief Function for setting the over-read character. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] orc Over-read character. Character clocked out in case of - * over-read of the TXD buffer. - */ -__STATIC_INLINE void nrf_twis_orc_set( - NRF_TWIS_Type * const p_reg, - uint8_t orc); - -/** - * @brief Function for setting the over-read character. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * - * @return Over-read character configured for selected instance. - */ -__STATIC_INLINE uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * const p_reg); - - -/** @} */ /* End of nrf_twis_hal */ - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -/* ------------------------------------------------------------------------------------------------ - * Internal functions - */ - -/** - * @internal - * @brief Internal function for getting task/event register address - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @oaram offset Offset of the register from the instance beginning - * - * @attention offset has to be modulo 4 value. In other case we can get hardware fault. - * @return Pointer to the register - */ -__STATIC_INLINE volatile uint32_t* nrf_twis_getRegPtr(NRF_TWIS_Type * const p_reg, uint32_t offset) -{ - return (volatile uint32_t*)((uint8_t *)p_reg + (uint32_t)offset); -} - -/** - * @internal - * @brief Internal function for getting task/event register address - constant version - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @oaram offset Offset of the register from the instance beginning - * - * @attention offset has to be modulo 4 value. In other case we can get hardware fault. - * @return Pointer to the register - */ -__STATIC_INLINE volatile const uint32_t* nrf_twis_getRegPtr_c(NRF_TWIS_Type const * const p_reg, uint32_t offset) -{ - return (volatile const uint32_t*)((uint8_t *)p_reg + (uint32_t)offset); -} - - -/* ------------------------------------------------------------------------------------------------ - * Interface functions definitions - */ - - -void nrf_twis_task_trigger(NRF_TWIS_Type * const p_reg, nrf_twis_task_t task) -{ - *(nrf_twis_getRegPtr(p_reg, (uint32_t)task)) = 1UL; -} - -uint32_t nrf_twis_task_address_get( - NRF_TWIS_Type const * const p_reg, - nrf_twis_task_t task) -{ - return (uint32_t)nrf_twis_getRegPtr_c(p_reg, (uint32_t)task); -} - -void nrf_twis_event_clear( - NRF_TWIS_Type * const p_reg, - nrf_twis_event_t event) -{ - *(nrf_twis_getRegPtr(p_reg, (uint32_t)event)) = 0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif -} - -bool nrf_twis_event_check( - NRF_TWIS_Type const * const p_reg, - nrf_twis_event_t event) -{ - return (bool)*nrf_twis_getRegPtr_c(p_reg, (uint32_t)event); -} - -bool nrf_twis_event_get_and_clear( - NRF_TWIS_Type * const p_reg, - nrf_twis_event_t event) -{ - bool ret = nrf_twis_event_check(p_reg, event); - if (ret) - { - nrf_twis_event_clear(p_reg, event); - } - return ret; -} - -uint32_t nrf_twis_event_address_get( - NRF_TWIS_Type const * const p_reg, - nrf_twis_event_t event) -{ - return (uint32_t)nrf_twis_getRegPtr_c(p_reg, (uint32_t)event); -} - -void nrf_twis_shorts_enable(NRF_TWIS_Type * const p_reg, uint32_t short_mask) -{ - p_reg->SHORTS |= short_mask; -} - -void nrf_twis_shorts_disable(NRF_TWIS_Type * const p_reg, uint32_t short_mask) -{ - if (~0U == short_mask) - { - /* Optimized version for "disable all" */ - p_reg->SHORTS = 0; - } - else - { - p_reg->SHORTS &= ~short_mask; - } -} - -uint32_t nrf_twis_shorts_get(NRF_TWIS_Type * const p_reg) -{ - return p_reg->SHORTS; -} - -void nrf_twis_int_enable(NRF_TWIS_Type * const p_reg, uint32_t int_mask) -{ - p_reg->INTENSET = int_mask; -} - -bool nrf_twis_int_enable_check(NRF_TWIS_Type const * const p_reg, uint32_t int_mask) -{ - return (bool)(p_reg->INTENSET & int_mask); -} - -void nrf_twis_int_disable(NRF_TWIS_Type * const p_reg, uint32_t int_mask) -{ - p_reg->INTENCLR = int_mask; -} - -uint32_t nrf_twis_error_source_get_and_clear(NRF_TWIS_Type * const p_reg) -{ - uint32_t ret = p_reg->ERRORSRC; - p_reg->ERRORSRC = ret; - return ret; -} - -uint_fast8_t nrf_twis_match_get(NRF_TWIS_Type const * p_reg) -{ - return (uint_fast8_t)p_reg->MATCH; -} - -void nrf_twis_enable(NRF_TWIS_Type * const p_reg) -{ - p_reg->ENABLE = (TWIS_ENABLE_ENABLE_Enabled << TWIS_ENABLE_ENABLE_Pos); -} - -void nrf_twis_disable(NRF_TWIS_Type * const p_reg) -{ - p_reg->ENABLE = (TWIS_ENABLE_ENABLE_Disabled << TWIS_ENABLE_ENABLE_Pos); -} - -void nrf_twis_pins_set(NRF_TWIS_Type * const p_reg, uint32_t scl, uint32_t sda) -{ - p_reg->PSEL.SCL = scl; - p_reg->PSEL.SDA = sda; -} - -void nrf_twis_rx_buffer_set( - NRF_TWIS_Type * const p_reg, - uint8_t * p_buf, - nrf_twis_amount_t length) -{ - p_reg->RXD.PTR = (uint32_t)p_buf; - p_reg->RXD.MAXCNT = length; -} - -__STATIC_INLINE void nrf_twis_rx_prepare( - NRF_TWIS_Type * const p_reg, - uint8_t * p_buf, - nrf_twis_amount_t length) -{ - nrf_twis_rx_buffer_set(p_reg, p_buf, length); - nrf_twis_task_trigger(p_reg, NRF_TWIS_TASK_PREPARERX); -} - -nrf_twis_amount_t nrf_twis_rx_amount_get(NRF_TWIS_Type const * const p_reg) -{ - return (nrf_twis_amount_t)p_reg->RXD.AMOUNT; -} - -void nrf_twis_tx_buffer_set( - NRF_TWIS_Type * const p_reg, - uint8_t const * p_buf, - nrf_twis_amount_t length) -{ - p_reg->TXD.PTR = (uint32_t)p_buf; - p_reg->TXD.MAXCNT = length; -} - -__STATIC_INLINE void nrf_twis_tx_prepare( - NRF_TWIS_Type * const p_reg, - uint8_t const * p_buf, - nrf_twis_amount_t length) -{ - nrf_twis_tx_buffer_set(p_reg, p_buf, length); - nrf_twis_task_trigger(p_reg, NRF_TWIS_TASK_PREPARETX); -} - -nrf_twis_amount_t nrf_twis_tx_amount_get(NRF_TWIS_Type const * const p_reg) -{ - return (nrf_twis_amount_t)p_reg->TXD.AMOUNT; -} - -void nrf_twis_address_set( - NRF_TWIS_Type * const p_reg, - uint_fast8_t n, - nrf_twis_address_t addr) -{ - p_reg->ADDRESS[n] = addr; -} - -nrf_twis_address_t nrf_twis_address_get( - NRF_TWIS_Type const * const p_reg, - uint_fast8_t n) -{ - return (nrf_twis_address_t)p_reg->ADDRESS[n]; -} -void nrf_twis_config_address_set( - NRF_TWIS_Type * const p_reg, - nrf_twis_config_addr_mask_t addr_mask) -{ - /* This is the only configuration in TWIS - just write it without masking */ - p_reg->CONFIG = addr_mask; -} - -nrf_twis_config_addr_mask_t nrf_twis_config_address_get(NRF_TWIS_Type const * const p_reg) -{ - return (nrf_twis_config_addr_mask_t)(p_reg->CONFIG & TWIS_ADDRESS_ADDRESS_Msk); -} - -void nrf_twis_orc_set( - NRF_TWIS_Type * const p_reg, - uint8_t orc) -{ - p_reg->ORC = orc; -} - -uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * const p_reg) -{ - return (uint8_t)p_reg->ORC; -} - -#endif /* SUPPRESS_INLINE_IMPLEMENTATION */ - - -#ifdef __cplusplus -} -#endif - -#endif /* NRF_TWIS_H__ */ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_uart.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_uart.h deleted file mode 100644 index 776a4605db..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_uart.h +++ /dev/null @@ -1,526 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_UART_H__ -#define NRF_UART_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_uart_hal UART HAL - * @{ - * @ingroup nrf_uart - * @brief Hardware access layer for managing the UART peripheral. - */ - -#define NRF_UART_PSEL_DISCONNECTED 0xFFFFFFFF - -/** - * @enum nrf_uart_task_t - * @brief UART tasks. - */ -typedef enum -{ - /*lint -save -e30 -esym(628,__INTADDR__)*/ - NRF_UART_TASK_STARTRX = offsetof(NRF_UART_Type, TASKS_STARTRX), /**< Task for starting reception. */ - NRF_UART_TASK_STOPRX = offsetof(NRF_UART_Type, TASKS_STOPRX), /**< Task for stopping reception. */ - NRF_UART_TASK_STARTTX = offsetof(NRF_UART_Type, TASKS_STARTTX), /**< Task for starting transmission. */ - NRF_UART_TASK_STOPTX = offsetof(NRF_UART_Type, TASKS_STOPTX), /**< Task for stopping transmission. */ - NRF_UART_TASK_SUSPEND = offsetof(NRF_UART_Type, TASKS_SUSPEND), /**< Task for suspending UART. */ - /*lint -restore*/ -} nrf_uart_task_t; - -/** - * @enum nrf_uart_event_t - * @brief UART events. - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_UART_EVENT_CTS = offsetof(NRF_UART_Type, EVENTS_CTS), /**< Event from CTS line activation. */ - NRF_UART_EVENT_NCTS = offsetof(NRF_UART_Type, EVENTS_NCTS), /**< Event from CTS line deactivation. */ - NRF_UART_EVENT_RXDRDY = offsetof(NRF_UART_Type, EVENTS_RXDRDY),/**< Event from data ready in RXD. */ - NRF_UART_EVENT_TXDRDY = offsetof(NRF_UART_Type, EVENTS_TXDRDY),/**< Event from data sent from TXD. */ - NRF_UART_EVENT_ERROR = offsetof(NRF_UART_Type, EVENTS_ERROR), /**< Event from error detection. */ - NRF_UART_EVENT_RXTO = offsetof(NRF_UART_Type, EVENTS_RXTO) /**< Event from receiver timeout. */ - /*lint -restore*/ -} nrf_uart_event_t; - -/** - * @enum nrf_uart_int_mask_t - * @brief UART interrupts. - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_UART_INT_MASK_CTS = UART_INTENCLR_CTS_Msk, /**< CTS line activation interrupt. */ - NRF_UART_INT_MASK_NCTS = UART_INTENCLR_NCTS_Msk, /**< CTS line deactivation interrupt. */ - NRF_UART_INT_MASK_RXDRDY = UART_INTENCLR_RXDRDY_Msk, /**< Data ready in RXD interrupt. */ - NRF_UART_INT_MASK_TXDRDY = UART_INTENCLR_TXDRDY_Msk, /**< Data sent from TXD interrupt. */ - NRF_UART_INT_MASK_ERROR = UART_INTENCLR_ERROR_Msk, /**< Error detection interrupt. */ - NRF_UART_INT_MASK_RXTO = UART_INTENCLR_RXTO_Msk /**< Receiver timeout interrupt. */ - /*lint -restore*/ -} nrf_uart_int_mask_t; - -/** - * @enum nrf_uart_baudrate_t - * @brief Baudrates supported by UART. - */ -typedef enum -{ - NRF_UART_BAUDRATE_1200 = UART_BAUDRATE_BAUDRATE_Baud1200, /**< 1200 baud. */ - NRF_UART_BAUDRATE_2400 = UART_BAUDRATE_BAUDRATE_Baud2400, /**< 2400 baud. */ - NRF_UART_BAUDRATE_4800 = UART_BAUDRATE_BAUDRATE_Baud4800, /**< 4800 baud. */ - NRF_UART_BAUDRATE_9600 = UART_BAUDRATE_BAUDRATE_Baud9600, /**< 9600 baud. */ - NRF_UART_BAUDRATE_14400 = UART_BAUDRATE_BAUDRATE_Baud14400, /**< 14400 baud. */ - NRF_UART_BAUDRATE_19200 = UART_BAUDRATE_BAUDRATE_Baud19200, /**< 19200 baud. */ - NRF_UART_BAUDRATE_28800 = UART_BAUDRATE_BAUDRATE_Baud28800, /**< 28800 baud. */ - NRF_UART_BAUDRATE_31250 = UART_BAUDRATE_BAUDRATE_Baud31250, /**< 31250 baud. */ - NRF_UART_BAUDRATE_38400 = UART_BAUDRATE_BAUDRATE_Baud38400, /**< 38400 baud. */ - NRF_UART_BAUDRATE_56000 = UART_BAUDRATE_BAUDRATE_Baud56000, /**< 56000 baud. */ - NRF_UART_BAUDRATE_57600 = UART_BAUDRATE_BAUDRATE_Baud57600, /**< 57600 baud. */ - NRF_UART_BAUDRATE_76800 = UART_BAUDRATE_BAUDRATE_Baud76800, /**< 76800 baud. */ - NRF_UART_BAUDRATE_115200 = UART_BAUDRATE_BAUDRATE_Baud115200, /**< 115200 baud. */ - NRF_UART_BAUDRATE_230400 = UART_BAUDRATE_BAUDRATE_Baud230400, /**< 230400 baud. */ - NRF_UART_BAUDRATE_250000 = UART_BAUDRATE_BAUDRATE_Baud250000, /**< 250000 baud. */ - NRF_UART_BAUDRATE_460800 = UART_BAUDRATE_BAUDRATE_Baud460800, /**< 460800 baud. */ - NRF_UART_BAUDRATE_921600 = UART_BAUDRATE_BAUDRATE_Baud921600, /**< 921600 baud. */ - NRF_UART_BAUDRATE_1000000 = UART_BAUDRATE_BAUDRATE_Baud1M, /**< 1000000 baud. */ -} nrf_uart_baudrate_t; - -/** - * @enum nrf_uart_error_mask_t - * @brief Types of UART error masks. - */ -typedef enum -{ - NRF_UART_ERROR_OVERRUN_MASK = UART_ERRORSRC_OVERRUN_Msk, /**< Overrun error. */ - NRF_UART_ERROR_PARITY_MASK = UART_ERRORSRC_PARITY_Msk, /**< Parity error. */ - NRF_UART_ERROR_FRAMING_MASK = UART_ERRORSRC_FRAMING_Msk, /**< Framing error. */ - NRF_UART_ERROR_BREAK_MASK = UART_ERRORSRC_BREAK_Msk, /**< Break error. */ -} nrf_uart_error_mask_t; - -/** - * @enum nrf_uart_parity_t - * @brief Types of UART parity modes. - */ -typedef enum -{ - NRF_UART_PARITY_EXCLUDED = UART_CONFIG_PARITY_Excluded << UART_CONFIG_PARITY_Pos, /**< Parity excluded. */ - NRF_UART_PARITY_INCLUDED = UART_CONFIG_PARITY_Included << UART_CONFIG_PARITY_Pos, /**< Parity included. */ -} nrf_uart_parity_t; - -/** - * @enum nrf_uart_hwfc_t - * @brief Types of UART flow control modes. - */ -typedef enum -{ - NRF_UART_HWFC_DISABLED = UART_CONFIG_HWFC_Disabled, /**< HW flow control disabled. */ - NRF_UART_HWFC_ENABLED = UART_CONFIG_HWFC_Enabled, /**< HW flow control enabled. */ -} nrf_uart_hwfc_t; - -/** - * @brief Function for clearing a specific UART event. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] event Event to clear. - */ -__STATIC_INLINE void nrf_uart_event_clear(NRF_UART_Type * p_reg, nrf_uart_event_t event); - -/** - * @brief Function for checking the state of a specific UART event. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] event Event to check. - * - * @retval True if event is set, False otherwise. - */ -__STATIC_INLINE bool nrf_uart_event_check(NRF_UART_Type * p_reg, nrf_uart_event_t event); - -/** - * @brief Function for returning the address of a specific UART event register. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] event Desired event. - * - * @retval Address of specified event register. - */ -__STATIC_INLINE uint32_t nrf_uart_event_address_get(NRF_UART_Type * p_reg, - nrf_uart_event_t event); - -/** - * @brief Function for enabling a specific interrupt. - * - * @param p_reg Pointer to the peripheral registers structure. - * @param int_mask Interrupts to enable. - */ -__STATIC_INLINE void nrf_uart_int_enable(NRF_UART_Type * p_reg, uint32_t int_mask); - -/** - * @brief Function for retrieving the state of a given interrupt. - * - * @param p_reg Pointer to the peripheral registers structure. - * @param int_mask Mask of interrupt to check. - * - * @retval true If the interrupt is enabled. - * @retval false If the interrupt is not enabled. - */ -__STATIC_INLINE bool nrf_uart_int_enable_check(NRF_UART_Type * p_reg, uint32_t int_mask); - -/** - * @brief Function for disabling specific interrupts. - * - * @param p_reg Pointer to the peripheral registers structure. - * @param int_mask Interrupts to disable. - */ -__STATIC_INLINE void nrf_uart_int_disable(NRF_UART_Type * p_reg, uint32_t int_mask); - -/** - * @brief Function for getting error source mask. Function is clearing error source flags after reading. - * - * @param p_reg Pointer to the peripheral registers structure. - * @return Mask with error source flags. - */ -__STATIC_INLINE uint32_t nrf_uart_errorsrc_get_and_clear(NRF_UART_Type * p_reg); - -/** - * @brief Function for enabling UART. - * - * @param p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_uart_enable(NRF_UART_Type * p_reg); - -/** - * @brief Function for disabling UART. - * - * @param p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_uart_disable(NRF_UART_Type * p_reg); - -/** - * @brief Function for configuring TX/RX pins. - * - * @param p_reg Pointer to the peripheral registers structure. - * @param pseltxd TXD pin number. - * @param pselrxd RXD pin number. - */ -__STATIC_INLINE void nrf_uart_txrx_pins_set(NRF_UART_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd); - -/** - * @brief Function for disconnecting TX/RX pins. - * - * @param p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_uart_txrx_pins_disconnect(NRF_UART_Type * p_reg); - -/** - * @brief Function for getting TX pin. - * - * @param p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE uint32_t nrf_uart_tx_pin_get(NRF_UART_Type * p_reg); - -/** - * @brief Function for getting RX pin. - * - * @param p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE uint32_t nrf_uart_rx_pin_get(NRF_UART_Type * p_reg); - -/** - * @brief Function for getting RTS pin. - * - * @param p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE uint32_t nrf_uart_rts_pin_get(NRF_UART_Type * p_reg); - -/** - * @brief Function for getting CTS pin. - * - * @param p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE uint32_t nrf_uart_cts_pin_get(NRF_UART_Type * p_reg); - - -/** - * @brief Function for configuring flow control pins. - * - * @param p_reg Pointer to the peripheral registers structure. - * @param pselrts RTS pin number. - * @param pselcts CTS pin number. - */ -__STATIC_INLINE void nrf_uart_hwfc_pins_set(NRF_UART_Type * p_reg, - uint32_t pselrts, - uint32_t pselcts); - -/** - * @brief Function for disconnecting flow control pins. - * - * @param p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_uart_hwfc_pins_disconnect(NRF_UART_Type * p_reg); - -/** - * @brief Function for reading RX data. - * - * @param p_reg Pointer to the peripheral registers structure. - * @return Received byte. - */ -__STATIC_INLINE uint8_t nrf_uart_rxd_get(NRF_UART_Type * p_reg); - -/** - * @brief Function for setting Tx data. - * - * @param p_reg Pointer to the peripheral registers structure. - * @param txd Byte. - */ -__STATIC_INLINE void nrf_uart_txd_set(NRF_UART_Type * p_reg, uint8_t txd); - -/** - * @brief Function for starting an UART task. - * - * @param p_reg Pointer to the peripheral registers structure. - * @param task Task. - */ -__STATIC_INLINE void nrf_uart_task_trigger(NRF_UART_Type * p_reg, nrf_uart_task_t task); - -/** - * @brief Function for returning the address of a specific task register. - * - * @param p_reg Pointer to the peripheral registers structure. - * @param task Task. - * - * @return Task address. - */ -__STATIC_INLINE uint32_t nrf_uart_task_address_get(NRF_UART_Type * p_reg, nrf_uart_task_t task); - -/** - * @brief Function for configuring UART. - * - * @param p_reg Pointer to the peripheral registers structure. - * @param hwfc Hardware flow control. Enabled if true. - * @param parity Parity. Included if true. - */ -__STATIC_INLINE void nrf_uart_configure(NRF_UART_Type * p_reg, - nrf_uart_parity_t parity, - nrf_uart_hwfc_t hwfc); - -/** - * @brief Function for setting UART baudrate. - * - * @param p_reg Pointer to the peripheral registers structure. - * @param baudrate Baudrate. - */ -__STATIC_INLINE void nrf_uart_baudrate_set(NRF_UART_Type * p_reg, nrf_uart_baudrate_t baudrate); - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION -__STATIC_INLINE void nrf_uart_event_clear(NRF_UART_Type * p_reg, nrf_uart_event_t event) -{ - *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif - -} - -__STATIC_INLINE bool nrf_uart_event_check(NRF_UART_Type * p_reg, nrf_uart_event_t event) -{ - return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event); -} - -__STATIC_INLINE uint32_t nrf_uart_event_address_get(NRF_UART_Type * p_reg, - nrf_uart_event_t event) -{ - return (uint32_t)((uint8_t *)p_reg + (uint32_t)event); -} - -__STATIC_INLINE void nrf_uart_int_enable(NRF_UART_Type * p_reg, uint32_t int_mask) -{ - p_reg->INTENSET = int_mask; -} - -__STATIC_INLINE bool nrf_uart_int_enable_check(NRF_UART_Type * p_reg, uint32_t int_mask) -{ - return (bool)(p_reg->INTENSET & int_mask); -} - -__STATIC_INLINE void nrf_uart_int_disable(NRF_UART_Type * p_reg, uint32_t int_mask) -{ - p_reg->INTENCLR = int_mask; -} - -__STATIC_INLINE uint32_t nrf_uart_errorsrc_get_and_clear(NRF_UART_Type * p_reg) -{ - uint32_t errsrc_mask = p_reg->ERRORSRC; - p_reg->ERRORSRC = errsrc_mask; - return errsrc_mask; -} - -__STATIC_INLINE void nrf_uart_enable(NRF_UART_Type * p_reg) -{ - p_reg->ENABLE = UART_ENABLE_ENABLE_Enabled; -} - -__STATIC_INLINE void nrf_uart_disable(NRF_UART_Type * p_reg) -{ - p_reg->ENABLE = UART_ENABLE_ENABLE_Disabled; -} - -__STATIC_INLINE void nrf_uart_txrx_pins_set(NRF_UART_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd) -{ -#if defined(UART_PSEL_RXD_CONNECT_Pos) - p_reg->PSEL.RXD = pselrxd; -#else - p_reg->PSELRXD = pselrxd; -#endif -#if defined(UART_PSEL_TXD_CONNECT_Pos) - p_reg->PSEL.TXD = pseltxd; -#else - p_reg->PSELTXD = pseltxd; -#endif -} - -__STATIC_INLINE void nrf_uart_txrx_pins_disconnect(NRF_UART_Type * p_reg) -{ - nrf_uart_txrx_pins_set(p_reg, NRF_UART_PSEL_DISCONNECTED, NRF_UART_PSEL_DISCONNECTED); -} - -__STATIC_INLINE uint32_t nrf_uart_tx_pin_get(NRF_UART_Type * p_reg) -{ -#if defined(UART_PSEL_TXD_CONNECT_Pos) - return p_reg->PSEL.TXD; -#else - return p_reg->PSELTXD; -#endif -} - -__STATIC_INLINE uint32_t nrf_uart_rx_pin_get(NRF_UART_Type * p_reg) -{ -#if defined(UART_PSEL_RXD_CONNECT_Pos) - return p_reg->PSEL.RXD; -#else - return p_reg->PSELRXD; -#endif -} - -__STATIC_INLINE uint32_t nrf_uart_rts_pin_get(NRF_UART_Type * p_reg) -{ -#if defined(UART_PSEL_RTS_CONNECT_Pos) - return p_reg->PSEL.RTS; -#else - return p_reg->PSELRTS; -#endif -} - -__STATIC_INLINE uint32_t nrf_uart_cts_pin_get(NRF_UART_Type * p_reg) -{ -#if defined(UART_PSEL_RTS_CONNECT_Pos) - return p_reg->PSEL.CTS; -#else - return p_reg->PSELCTS; -#endif -} - -__STATIC_INLINE void nrf_uart_hwfc_pins_set(NRF_UART_Type * p_reg, uint32_t pselrts, uint32_t pselcts) -{ -#if defined(UART_PSEL_RTS_CONNECT_Pos) - p_reg->PSEL.RTS = pselrts; -#else - p_reg->PSELRTS = pselrts; -#endif - -#if defined(UART_PSEL_RTS_CONNECT_Pos) - p_reg->PSEL.CTS = pselcts; -#else - p_reg->PSELCTS = pselcts; -#endif -} - -__STATIC_INLINE void nrf_uart_hwfc_pins_disconnect(NRF_UART_Type * p_reg) -{ - nrf_uart_hwfc_pins_set(p_reg, NRF_UART_PSEL_DISCONNECTED, NRF_UART_PSEL_DISCONNECTED); -} - -__STATIC_INLINE uint8_t nrf_uart_rxd_get(NRF_UART_Type * p_reg) -{ - return p_reg->RXD; -} - -__STATIC_INLINE void nrf_uart_txd_set(NRF_UART_Type * p_reg, uint8_t txd) -{ - p_reg->TXD = txd; -} - -__STATIC_INLINE void nrf_uart_task_trigger(NRF_UART_Type * p_reg, nrf_uart_task_t task) -{ - *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; -} - -__STATIC_INLINE uint32_t nrf_uart_task_address_get(NRF_UART_Type * p_reg, nrf_uart_task_t task) -{ - return (uint32_t)p_reg + (uint32_t)task; -} - -__STATIC_INLINE void nrf_uart_configure(NRF_UART_Type * p_reg, - nrf_uart_parity_t parity, - nrf_uart_hwfc_t hwfc) -{ - p_reg->CONFIG = (uint32_t)parity | (uint32_t)hwfc; -} - -__STATIC_INLINE void nrf_uart_baudrate_set(NRF_UART_Type * p_reg, nrf_uart_baudrate_t baudrate) -{ - p_reg->BAUDRATE = baudrate; -} -#endif //SUPPRESS_INLINE_IMPLEMENTATION - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif //NRF_UART_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_uarte.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_uarte.h deleted file mode 100644 index 97a508c016..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_uarte.h +++ /dev/null @@ -1,579 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_UARTE_H__ -#define NRF_UARTE_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#define NRF_UARTE_PSEL_DISCONNECTED 0xFFFFFFFF - -/** - * @defgroup nrf_uarte_hal UARTE HAL - * @{ - * @ingroup nrf_uarte - * @brief Hardware access layer for managing the UARTE peripheral. - */ - -/** - * @enum nrf_uarte_task_t - * @brief UARTE tasks. - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_UARTE_TASK_STARTRX = offsetof(NRF_UARTE_Type, TASKS_STARTRX), ///< Start UART receiver. - NRF_UARTE_TASK_STOPRX = offsetof(NRF_UARTE_Type, TASKS_STOPRX), ///< Stop UART receiver. - NRF_UARTE_TASK_STARTTX = offsetof(NRF_UARTE_Type, TASKS_STARTTX), ///< Start UART transmitter. - NRF_UARTE_TASK_STOPTX = offsetof(NRF_UARTE_Type, TASKS_STOPTX), ///< Stop UART transmitter. - NRF_UARTE_TASK_FLUSHRX = offsetof(NRF_UARTE_Type, TASKS_FLUSHRX) ///< Flush RX FIFO in RX buffer. - /*lint -restore*/ -} nrf_uarte_task_t; - -/** - * @enum nrf_uarte_event_t - * @brief UARTE events. - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_UARTE_EVENT_CTS = offsetof(NRF_UARTE_Type, EVENTS_CTS), ///< CTS is activated. - NRF_UARTE_EVENT_NCTS = offsetof(NRF_UARTE_Type, EVENTS_NCTS), ///< CTS is deactivated. - NRF_UARTE_EVENT_RXDRDY = offsetof(NRF_UARTE_Type, EVENTS_RXDRDY), ///< Data received in RXD (but potentially not yet transferred to Data RAM). - NRF_UARTE_EVENT_ENDRX = offsetof(NRF_UARTE_Type, EVENTS_ENDRX), ///< Receive buffer is filled up. - NRF_UARTE_EVENT_TXDDY = offsetof(NRF_UARTE_Type, EVENTS_TXDRDY), ///< Data sent from TXD. - NRF_UARTE_EVENT_ENDTX = offsetof(NRF_UARTE_Type, EVENTS_ENDTX), ///< Last TX byte transmitted. - NRF_UARTE_EVENT_ERROR = offsetof(NRF_UARTE_Type, EVENTS_ERROR), ///< Error detected. - NRF_UARTE_EVENT_RXTO = offsetof(NRF_UARTE_Type, EVENTS_RXTO), ///< Receiver timeout. - NRF_UARTE_EVENT_RXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_RXSTARTED), ///< Receiver has started. - NRF_UARTE_EVENT_TXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_TXSTARTED), ///< Transmitter has started. - NRF_UARTE_EVENT_TXSTOPPED = offsetof(NRF_UARTE_Type, EVENTS_TXSTOPPED) ///< Transmitted stopped. - /*lint -restore*/ -} nrf_uarte_event_t; - -/** - * @brief Types of UARTE shortcuts. - */ -typedef enum -{ - NRF_UARTE_SHORT_ENDRX_STARTRX = UARTE_SHORTS_ENDRX_STARTRX_Msk, ///< Shortcut between ENDRX event and STARTRX task. - NRF_UARTE_SHORT_ENDRX_STOPRX = UARTE_SHORTS_ENDRX_STOPRX_Msk ///< Shortcut between ENDRX event and STOPRX task. -} nrf_uarte_short_t; - - -/** - * @enum nrf_uarte_int_mask_t - * @brief UARTE interrupts. - */ -typedef enum -{ - NRF_UARTE_INT_CTS_MASK = UARTE_INTENSET_CTS_Msk, ///< Interrupt on CTS event. - NRF_UARTE_INT_NCTS_MASK = UARTE_INTENSET_NCTS_Msk, ///< Interrupt on NCTS event. - NRF_UARTE_INT_RXDRDY_MASK = UARTE_INTENSET_RXDRDY_Msk, ///< Interrupt on RXDRDY event. - NRF_UARTE_INT_ENDRX_MASK = UARTE_INTENSET_ENDRX_Msk, ///< Interrupt on ENDRX event. - NRF_UARTE_INT_TXDRDY_MASK = UARTE_INTENSET_TXDRDY_Msk, ///< Interrupt on TXDRDY event. - NRF_UARTE_INT_ENDTX_MASK = UARTE_INTENSET_ENDTX_Msk, ///< Interrupt on ENDTX event. - NRF_UARTE_INT_ERROR_MASK = UARTE_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event. - NRF_UARTE_INT_RXTO_MASK = UARTE_INTENSET_RXTO_Msk, ///< Interrupt on RXTO event. - NRF_UARTE_INT_RXSTARTED_MASK = UARTE_INTENSET_RXSTARTED_Msk, ///< Interrupt on RXSTARTED event. - NRF_UARTE_INT_TXSTARTED_MASK = UARTE_INTENSET_TXSTARTED_Msk, ///< Interrupt on TXSTARTED event. - NRF_UARTE_INT_TXSTOPPED_MASK = UARTE_INTENSET_TXSTOPPED_Msk ///< Interrupt on TXSTOPPED event. -} nrf_uarte_int_mask_t; - -/** - * @enum nrf_uarte_baudrate_t - * @brief Baudrates supported by UARTE. - */ -typedef enum -{ - NRF_UARTE_BAUDRATE_1200 = UARTE_BAUDRATE_BAUDRATE_Baud1200, ///< 1200 baud. - NRF_UARTE_BAUDRATE_2400 = UARTE_BAUDRATE_BAUDRATE_Baud2400, ///< 2400 baud. - NRF_UARTE_BAUDRATE_4800 = UARTE_BAUDRATE_BAUDRATE_Baud4800, ///< 4800 baud. - NRF_UARTE_BAUDRATE_9600 = UARTE_BAUDRATE_BAUDRATE_Baud9600, ///< 9600 baud. - NRF_UARTE_BAUDRATE_14400 = UARTE_BAUDRATE_BAUDRATE_Baud14400, ///< 14400 baud. - NRF_UARTE_BAUDRATE_19200 = UARTE_BAUDRATE_BAUDRATE_Baud19200, ///< 19200 baud. - NRF_UARTE_BAUDRATE_28800 = UARTE_BAUDRATE_BAUDRATE_Baud28800, ///< 28800 baud. - NRF_UARTE_BAUDRATE_31250 = UARTE_BAUDRATE_BAUDRATE_Baud31250, ///< 31250 baud. - NRF_UARTE_BAUDRATE_38400 = UARTE_BAUDRATE_BAUDRATE_Baud38400, ///< 38400 baud. - NRF_UARTE_BAUDRATE_56000 = UARTE_BAUDRATE_BAUDRATE_Baud56000, ///< 56000 baud. - NRF_UARTE_BAUDRATE_57600 = UARTE_BAUDRATE_BAUDRATE_Baud57600, ///< 57600 baud. - NRF_UARTE_BAUDRATE_76800 = UARTE_BAUDRATE_BAUDRATE_Baud76800, ///< 76800 baud. - NRF_UARTE_BAUDRATE_115200 = UARTE_BAUDRATE_BAUDRATE_Baud115200, ///< 115200 baud. - NRF_UARTE_BAUDRATE_230400 = UARTE_BAUDRATE_BAUDRATE_Baud230400, ///< 230400 baud. - NRF_UARTE_BAUDRATE_250000 = UARTE_BAUDRATE_BAUDRATE_Baud250000, ///< 250000 baud. - NRF_UARTE_BAUDRATE_460800 = UARTE_BAUDRATE_BAUDRATE_Baud460800, ///< 460800 baud. - NRF_UARTE_BAUDRATE_921600 = UARTE_BAUDRATE_BAUDRATE_Baud921600, ///< 921600 baud. - NRF_UARTE_BAUDRATE_1000000 = UARTE_BAUDRATE_BAUDRATE_Baud1M ///< 1000000 baud. -} nrf_uarte_baudrate_t; - -/** - * @enum nrf_uarte_error_mask_t - * @brief Types of UARTE error masks. - */ -typedef enum -{ - NRF_UARTE_ERROR_OVERRUN_MASK = UARTE_ERRORSRC_OVERRUN_Msk, ///< Overrun error. - NRF_UARTE_ERROR_PARITY_MASK = UARTE_ERRORSRC_PARITY_Msk, ///< Parity error. - NRF_UARTE_ERROR_FRAMING_MASK = UARTE_ERRORSRC_FRAMING_Msk, ///< Framing error. - NRF_UARTE_ERROR_BREAK_MASK = UARTE_ERRORSRC_BREAK_Msk ///< Break error. -} nrf_uarte_error_mask_t; - -/** - * @enum nrf_uarte_parity_t - * @brief Types of UARTE parity modes. - */ -typedef enum -{ - NRF_UARTE_PARITY_EXCLUDED = UARTE_CONFIG_PARITY_Excluded << UARTE_CONFIG_PARITY_Pos, ///< Parity excluded. - NRF_UARTE_PARITY_INCLUDED = UARTE_CONFIG_PARITY_Included << UARTE_CONFIG_PARITY_Pos ///< Parity included. -} nrf_uarte_parity_t; - -/** - * @enum nrf_uarte_hwfc_t - * @brief Types of UARTE flow control modes. - */ -typedef enum -{ - NRF_UARTE_HWFC_DISABLED = UARTE_CONFIG_HWFC_Disabled << UARTE_CONFIG_HWFC_Pos, ///< HW flow control disabled. - NRF_UARTE_HWFC_ENABLED = UARTE_CONFIG_HWFC_Enabled << UARTE_CONFIG_HWFC_Pos ///< HW flow control enabled. -} nrf_uarte_hwfc_t; - - -/** - * @brief Function for clearing a specific UARTE event. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] event Event to clear. - */ -__STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event); - -/** - * @brief Function for checking the state of a specific UARTE event. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] event Event to check. - * - * @retval True if event is set, False otherwise. - */ -__STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event); - -/** - * @brief Function for returning the address of a specific UARTE event register. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] event Desired event. - * - * @retval Address of specified event register. - */ -__STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type * p_reg, - nrf_uarte_event_t event); - -/** - * @brief Function for enabling UARTE shortcuts. - * - * @param p_reg Pointer to the peripheral registers structure. - * @param shorts_mask Shortcuts to enable. - */ -__STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask); - -/** - * @brief Function for disabling UARTE shortcuts. - * - * @param p_reg Pointer to the peripheral registers structure. - * @param shorts_mask Shortcuts to disable. - */ -__STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask); - -/** - * @brief Function for enabling UARTE interrupts. - * - * @param p_reg Pointer to the peripheral registers structure. - * @param int_mask Interrupts to enable. - */ -__STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t int_mask); - -/** - * @brief Function for retrieving the state of a given interrupt. - * - * @param p_reg Pointer to the peripheral registers structure. - * @param int_mask Mask of interrupt to check. - * - * @retval true If the interrupt is enabled. - * @retval false If the interrupt is not enabled. - */ -__STATIC_INLINE bool nrf_uarte_int_enable_check(NRF_UARTE_Type * p_reg, nrf_uarte_int_mask_t int_mask); - -/** - * @brief Function for disabling specific interrupts. - * - * @param p_reg Instance. - * @param int_mask Interrupts to disable. - */ -__STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t int_mask); - -/** - * @brief Function for getting error source mask. Function is clearing error source flags after reading. - * - * @param p_reg Pointer to the peripheral registers structure. - * @return Mask with error source flags. - */ -__STATIC_INLINE uint32_t nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg); - -/** - * @brief Function for enabling UARTE. - * - * @param p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_uarte_enable(NRF_UARTE_Type * p_reg); - -/** - * @brief Function for disabling UARTE. - * - * @param p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg); - -/** - * @brief Function for configuring TX/RX pins. - * - * @param p_reg Pointer to the peripheral registers structure. - * @param pseltxd TXD pin number. - * @param pselrxd RXD pin number. - */ -__STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd); - -/** - * @brief Function for disconnecting TX/RX pins. - * - * @param p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg); - -/** - * @brief Function for getting TX pin. - * - * @param p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type * p_reg); - -/** - * @brief Function for getting RX pin. - * - * @param p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type * p_reg); - -/** - * @brief Function for getting RTS pin. - * - * @param p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type * p_reg); - -/** - * @brief Function for getting CTS pin. - * - * @param p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type * p_reg); - - -/** - * @brief Function for configuring flow control pins. - * - * @param p_reg Pointer to the peripheral registers structure. - * @param pselrts RTS pin number. - * @param pselcts CTS pin number. - */ -__STATIC_INLINE void nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg, - uint32_t pselrts, - uint32_t pselcts); - -/** - * @brief Function for disconnecting flow control pins. - * - * @param p_reg Pointer to the peripheral registers structure. - */ -__STATIC_INLINE void nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg); - -/** - * @brief Function for starting an UARTE task. - * - * @param p_reg Pointer to the peripheral registers structure. - * @param task Task. - */ -__STATIC_INLINE void nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task); - -/** - * @brief Function for returning the address of a specific task register. - * - * @param p_reg Pointer to the peripheral registers structure. - * @param task Task. - * - * @return Task address. - */ -__STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task); - -/** - * @brief Function for configuring UARTE. - * - * @param p_reg Pointer to the peripheral registers structure. - * @param hwfc Hardware flow control. Enabled if true. - * @param parity Parity. Included if true. - */ -__STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type * p_reg, - nrf_uarte_parity_t parity, - nrf_uarte_hwfc_t hwfc); - - -/** - * @brief Function for setting UARTE baudrate. - * - * @param p_reg Instance. - * @param baudrate Baudrate. - */ -__STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate); - -/** - * @brief Function for setting the transmit buffer. - * - * @param[in] p_reg Instance. - * @param[in] p_buffer Pointer to the buffer with data to send. - * @param[in] length Maximum number of data bytes to transmit. - */ -__STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg, - uint8_t const * p_buffer, - size_t length); - -/** - * @brief Function for getting number of bytes transmitted in the last transaction. - * - * @param[in] p_reg Instance. - * - * @retval Amount of bytes transmitted. - */ -__STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type * p_reg); - -/** - * @brief Function for setting the receive buffer. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * @param[in] p_buffer Pointer to the buffer for received data. - * @param[in] length Maximum number of data bytes to receive. - */ -__STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg, - uint8_t * p_buffer, - size_t length); - -/** - * @brief Function for getting number of bytes received in the last transaction. - * - * @param[in] p_reg Pointer to the peripheral registers structure. - * - * @retval Amount of bytes received. - */ -__STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type * p_reg); - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION -__STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event) -{ - *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif - -} - -__STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event) -{ - return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event); -} - -__STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type * p_reg, - nrf_uarte_event_t event) -{ - return (uint32_t)((uint8_t *)p_reg + (uint32_t)event); -} - -__STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask) -{ - p_reg->SHORTS |= shorts_mask; -} - -__STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask) -{ - p_reg->SHORTS &= ~(shorts_mask); -} - -__STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t int_mask) -{ - p_reg->INTENSET = int_mask; -} - -__STATIC_INLINE bool nrf_uarte_int_enable_check(NRF_UARTE_Type * p_reg, nrf_uarte_int_mask_t int_mask) -{ - return (bool)(p_reg->INTENSET & int_mask); -} - -__STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t int_mask) -{ - p_reg->INTENCLR = int_mask; -} - -__STATIC_INLINE uint32_t nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg) -{ - uint32_t errsrc_mask = p_reg->ERRORSRC; - p_reg->ERRORSRC = errsrc_mask; - return errsrc_mask; -} - -__STATIC_INLINE void nrf_uarte_enable(NRF_UARTE_Type * p_reg) -{ - p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled; -} - -__STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg) -{ - p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled; -} - -__STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd) -{ - p_reg->PSEL.TXD = pseltxd; - p_reg->PSEL.RXD = pselrxd; -} - -__STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg) -{ - nrf_uarte_txrx_pins_set(p_reg, NRF_UARTE_PSEL_DISCONNECTED, NRF_UARTE_PSEL_DISCONNECTED); -} - -__STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type * p_reg) -{ - return p_reg->PSEL.TXD; -} - -__STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type * p_reg) -{ - return p_reg->PSEL.RXD; -} - -__STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type * p_reg) -{ - return p_reg->PSEL.RTS; -} - -__STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type * p_reg) -{ - return p_reg->PSEL.CTS; -} - -__STATIC_INLINE void nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg, uint32_t pselrts, uint32_t pselcts) -{ - p_reg->PSEL.RTS = pselrts; - p_reg->PSEL.CTS = pselcts; -} - -__STATIC_INLINE void nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg) -{ - nrf_uarte_hwfc_pins_set(p_reg, NRF_UARTE_PSEL_DISCONNECTED, NRF_UARTE_PSEL_DISCONNECTED); -} - -__STATIC_INLINE void nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task) -{ - *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; -} - -__STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task) -{ - return (uint32_t)p_reg + (uint32_t)task; -} - -__STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type * p_reg, - nrf_uarte_parity_t parity, - nrf_uarte_hwfc_t hwfc) -{ - p_reg->CONFIG = (uint32_t)parity | (uint32_t)hwfc; -} - -__STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate) -{ - p_reg->BAUDRATE = baudrate; -} - -__STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg, - uint8_t const * p_buffer, - size_t length) -{ - p_reg->TXD.PTR = (uint32_t)p_buffer; - p_reg->TXD.MAXCNT = length; -} - -__STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type * p_reg) -{ - return p_reg->TXD.AMOUNT; -} - -__STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg, - uint8_t * p_buffer, - size_t length) -{ - p_reg->RXD.PTR = (uint32_t)p_buffer; - p_reg->RXD.MAXCNT = length; -} - -__STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type * p_reg) -{ - return p_reg->RXD.AMOUNT; -} -#endif //SUPPRESS_INLINE_IMPLEMENTATION - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif //NRF_UARTE_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_usbd.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_usbd.h deleted file mode 100644 index d99b90cb59..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_usbd.h +++ /dev/null @@ -1,1391 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_USBD_H__ -#define NRF_USBD_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_usbd_hal USBD HAL - * @{ - * @ingroup nrf_usbd - * @brief Hardware access layer for managing the Universal Serial Bus Device (USBD) - * peripheral. - */ - -/** - * @brief USBD tasks - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_USBD_TASK_STARTEPIN0 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[0] ), /**< Captures the EPIN[0].PTR, EPIN[0].MAXCNT and EPIN[0].CONFIG registers values, and enables control endpoint IN 0 to respond to traffic from host */ - NRF_USBD_TASK_STARTEPIN1 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[1] ), /**< Captures the EPIN[1].PTR, EPIN[1].MAXCNT and EPIN[1].CONFIG registers values, and enables data endpoint IN 1 to respond to traffic from host */ - NRF_USBD_TASK_STARTEPIN2 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[2] ), /**< Captures the EPIN[2].PTR, EPIN[2].MAXCNT and EPIN[2].CONFIG registers values, and enables data endpoint IN 2 to respond to traffic from host */ - NRF_USBD_TASK_STARTEPIN3 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[3] ), /**< Captures the EPIN[3].PTR, EPIN[3].MAXCNT and EPIN[3].CONFIG registers values, and enables data endpoint IN 3 to respond to traffic from host */ - NRF_USBD_TASK_STARTEPIN4 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[4] ), /**< Captures the EPIN[4].PTR, EPIN[4].MAXCNT and EPIN[4].CONFIG registers values, and enables data endpoint IN 4 to respond to traffic from host */ - NRF_USBD_TASK_STARTEPIN5 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[5] ), /**< Captures the EPIN[5].PTR, EPIN[5].MAXCNT and EPIN[5].CONFIG registers values, and enables data endpoint IN 5 to respond to traffic from host */ - NRF_USBD_TASK_STARTEPIN6 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[6] ), /**< Captures the EPIN[6].PTR, EPIN[6].MAXCNT and EPIN[6].CONFIG registers values, and enables data endpoint IN 6 to respond to traffic from host */ - NRF_USBD_TASK_STARTEPIN7 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[7] ), /**< Captures the EPIN[7].PTR, EPIN[7].MAXCNT and EPIN[7].CONFIG registers values, and enables data endpoint IN 7 to respond to traffic from host */ - NRF_USBD_TASK_STARTISOIN = offsetof(NRF_USBD_Type, TASKS_STARTISOIN ), /**< Captures the ISOIN.PTR, ISOIN.MAXCNT and ISOIN.CONFIG registers values, and enables sending data on iso endpoint 8 */ - NRF_USBD_TASK_STARTEPOUT0 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[0]), /**< Captures the EPOUT[0].PTR, EPOUT[0].MAXCNT and EPOUT[0].CONFIG registers values, and enables control endpoint 0 to respond to traffic from host */ - NRF_USBD_TASK_STARTEPOUT1 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[1]), /**< Captures the EPOUT[1].PTR, EPOUT[1].MAXCNT and EPOUT[1].CONFIG registers values, and enables data endpoint 1 to respond to traffic from host */ - NRF_USBD_TASK_STARTEPOUT2 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[2]), /**< Captures the EPOUT[2].PTR, EPOUT[2].MAXCNT and EPOUT[2].CONFIG registers values, and enables data endpoint 2 to respond to traffic from host */ - NRF_USBD_TASK_STARTEPOUT3 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[3]), /**< Captures the EPOUT[3].PTR, EPOUT[3].MAXCNT and EPOUT[3].CONFIG registers values, and enables data endpoint 3 to respond to traffic from host */ - NRF_USBD_TASK_STARTEPOUT4 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[4]), /**< Captures the EPOUT[4].PTR, EPOUT[4].MAXCNT and EPOUT[4].CONFIG registers values, and enables data endpoint 4 to respond to traffic from host */ - NRF_USBD_TASK_STARTEPOUT5 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[5]), /**< Captures the EPOUT[5].PTR, EPOUT[5].MAXCNT and EPOUT[5].CONFIG registers values, and enables data endpoint 5 to respond to traffic from host */ - NRF_USBD_TASK_STARTEPOUT6 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[6]), /**< Captures the EPOUT[6].PTR, EPOUT[6].MAXCNT and EPOUT[6].CONFIG registers values, and enables data endpoint 6 to respond to traffic from host */ - NRF_USBD_TASK_STARTEPOUT7 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[7]), /**< Captures the EPOUT[7].PTR, EPOUT[7].MAXCNT and EPOUT[7].CONFIG registers values, and enables data endpoint 7 to respond to traffic from host */ - NRF_USBD_TASK_STARTISOOUT = offsetof(NRF_USBD_Type, TASKS_STARTISOOUT ), /**< Captures the ISOOUT.PTR, ISOOUT.MAXCNT and ISOOUT.CONFIG registers values, and enables receiving of data on iso endpoint 8 */ - NRF_USBD_TASK_EP0RCVOUT = offsetof(NRF_USBD_Type, TASKS_EP0RCVOUT ), /**< Allows OUT data stage on control endpoint 0 */ - NRF_USBD_TASK_EP0STATUS = offsetof(NRF_USBD_Type, TASKS_EP0STATUS ), /**< Allows status stage on control endpoint 0 */ - NRF_USBD_TASK_EP0STALL = offsetof(NRF_USBD_Type, TASKS_EP0STALL ), /**< STALLs data and status stage on control endpoint 0 */ - NRF_USBD_TASK_DRIVEDPDM = offsetof(NRF_USBD_Type, TASKS_DPDMDRIVE ), /**< Forces D+ and D-lines to the state defined in the DPDMVALUE register */ - NRF_USBD_TASK_NODRIVEDPDM = offsetof(NRF_USBD_Type, TASKS_DPDMNODRIVE ), /**< Stops forcing D+ and D- lines to any state (USB engine takes control) */ - /*lint -restore*/ -}nrf_usbd_task_t; - -/** - * @brief USBD events - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_USBD_EVENT_USBRESET = offsetof(NRF_USBD_Type, EVENTS_USBRESET ), /**< Signals that a USB reset condition has been detected on the USB lines */ - NRF_USBD_EVENT_STARTED = offsetof(NRF_USBD_Type, EVENTS_STARTED ), /**< Confirms that the EPIN[n].PTR, EPIN[n].MAXCNT, EPIN[n].CONFIG, or EPOUT[n].PTR, EPOUT[n].MAXCNT and EPOUT[n].CONFIG registers have been captured on all endpoints reported in the EPSTATUS register */ - NRF_USBD_EVENT_ENDEPIN0 = offsetof(NRF_USBD_Type, EVENTS_ENDEPIN[0] ), /**< The whole EPIN[0] buffer has been consumed. The RAM buffer can be accessed safely by software. */ - NRF_USBD_EVENT_ENDEPIN1 = offsetof(NRF_USBD_Type, EVENTS_ENDEPIN[1] ), /**< The whole EPIN[1] buffer has been consumed. The RAM buffer can be accessed safely by software. */ - NRF_USBD_EVENT_ENDEPIN2 = offsetof(NRF_USBD_Type, EVENTS_ENDEPIN[2] ), /**< The whole EPIN[2] buffer has been consumed. The RAM buffer can be accessed safely by software. */ - NRF_USBD_EVENT_ENDEPIN3 = offsetof(NRF_USBD_Type, EVENTS_ENDEPIN[3] ), /**< The whole EPIN[3] buffer has been consumed. The RAM buffer can be accessed safely by software. */ - NRF_USBD_EVENT_ENDEPIN4 = offsetof(NRF_USBD_Type, EVENTS_ENDEPIN[4] ), /**< The whole EPIN[4] buffer has been consumed. The RAM buffer can be accessed safely by software. */ - NRF_USBD_EVENT_ENDEPIN5 = offsetof(NRF_USBD_Type, EVENTS_ENDEPIN[5] ), /**< The whole EPIN[5] buffer has been consumed. The RAM buffer can be accessed safely by software. */ - NRF_USBD_EVENT_ENDEPIN6 = offsetof(NRF_USBD_Type, EVENTS_ENDEPIN[6] ), /**< The whole EPIN[6] buffer has been consumed. The RAM buffer can be accessed safely by software. */ - NRF_USBD_EVENT_ENDEPIN7 = offsetof(NRF_USBD_Type, EVENTS_ENDEPIN[7] ), /**< The whole EPIN[7] buffer has been consumed. The RAM buffer can be accessed safely by software. */ - NRF_USBD_EVENT_EP0DATADONE = offsetof(NRF_USBD_Type, EVENTS_EP0DATADONE), /**< An acknowledged data transfer has taken place on the control endpoint */ - NRF_USBD_EVENT_ENDISOIN0 = offsetof(NRF_USBD_Type, EVENTS_ENDISOIN ), /**< The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. */ - NRF_USBD_EVENT_ENDEPOUT0 = offsetof(NRF_USBD_Type, EVENTS_ENDEPOUT[0]), /**< The whole EPOUT[0] buffer has been consumed. The RAM buffer can be accessed safely by software. */ - NRF_USBD_EVENT_ENDEPOUT1 = offsetof(NRF_USBD_Type, EVENTS_ENDEPOUT[1]), /**< The whole EPOUT[1] buffer has been consumed. The RAM buffer can be accessed safely by software. */ - NRF_USBD_EVENT_ENDEPOUT2 = offsetof(NRF_USBD_Type, EVENTS_ENDEPOUT[2]), /**< The whole EPOUT[2] buffer has been consumed. The RAM buffer can be accessed safely by software. */ - NRF_USBD_EVENT_ENDEPOUT3 = offsetof(NRF_USBD_Type, EVENTS_ENDEPOUT[3]), /**< The whole EPOUT[3] buffer has been consumed. The RAM buffer can be accessed safely by software. */ - NRF_USBD_EVENT_ENDEPOUT4 = offsetof(NRF_USBD_Type, EVENTS_ENDEPOUT[4]), /**< The whole EPOUT[4] buffer has been consumed. The RAM buffer can be accessed safely by software. */ - NRF_USBD_EVENT_ENDEPOUT5 = offsetof(NRF_USBD_Type, EVENTS_ENDEPOUT[5]), /**< The whole EPOUT[5] buffer has been consumed. The RAM buffer can be accessed safely by software. */ - NRF_USBD_EVENT_ENDEPOUT6 = offsetof(NRF_USBD_Type, EVENTS_ENDEPOUT[6]), /**< The whole EPOUT[6] buffer has been consumed. The RAM buffer can be accessed safely by software. */ - NRF_USBD_EVENT_ENDEPOUT7 = offsetof(NRF_USBD_Type, EVENTS_ENDEPOUT[7]), /**< The whole EPOUT[7] buffer has been consumed. The RAM buffer can be accessed safely by software. */ - NRF_USBD_EVENT_ENDISOOUT0 = offsetof(NRF_USBD_Type, EVENTS_ENDISOOUT ), /**< The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. */ - NRF_USBD_EVENT_SOF = offsetof(NRF_USBD_Type, EVENTS_SOF ), /**< Signals that a SOF (start of frame) condition has been detected on the USB lines */ - NRF_USBD_EVENT_USBEVENT = offsetof(NRF_USBD_Type, EVENTS_USBEVENT ), /**< An event or an error not covered by specific events has occurred, check EVENTCAUSE register to find the cause */ - NRF_USBD_EVENT_EP0SETUP = offsetof(NRF_USBD_Type, EVENTS_EP0SETUP ), /**< A valid SETUP token has been received (and acknowledged) on the control endpoint */ - NRF_USBD_EVENT_DATAEP = offsetof(NRF_USBD_Type, EVENTS_EPDATA ), /**< A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */ - /*lint -restore*/ -}nrf_usbd_event_t; - -/** - * @brief USBD shorts - */ -typedef enum -{ - NRF_USBD_SHORT_EP0DATADONE_STARTEPIN0_MASK = USBD_SHORTS_EP0DATADONE_STARTEPIN0_Msk , /**< Shortcut between EP0DATADONE event and STARTEPIN0 task */ - NRF_USBD_SHORT_EP0DATADONE_STARTEPOUT0_MASK = USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Msk, /**< Shortcut between EP0DATADONE event and STARTEPOUT0 task */ - NRF_USBD_SHORT_EP0DATADONE_EP0STATUS_MASK = USBD_SHORTS_EP0DATADONE_EP0STATUS_Msk , /**< Shortcut between EP0DATADONE event and EP0STATUS task */ - NRF_USBD_SHORT_ENDEPOUT0_EP0STATUS_MASK = USBD_SHORTS_ENDEPOUT0_EP0STATUS_Msk , /**< Shortcut between ENDEPOUT[0] event and EP0STATUS task */ - NRF_USBD_SHORT_ENDEPOUT0_EP0RCVOUT_MASK = USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Msk , /**< Shortcut between ENDEPOUT[0] event and EP0RCVOUT task */ -}nrf_usbd_short_mask_t; - -/** - * @brief USBD interrupts - */ -typedef enum -{ - NRF_USBD_INT_USBRESET_MASK = USBD_INTEN_USBRESET_Msk , /**< Enable or disable interrupt for USBRESET event */ - NRF_USBD_INT_STARTED_MASK = USBD_INTEN_STARTED_Msk , /**< Enable or disable interrupt for STARTED event */ - NRF_USBD_INT_ENDEPIN0_MASK = USBD_INTEN_ENDEPIN0_Msk , /**< Enable or disable interrupt for ENDEPIN[0] event */ - NRF_USBD_INT_ENDEPIN1_MASK = USBD_INTEN_ENDEPIN1_Msk , /**< Enable or disable interrupt for ENDEPIN[1] event */ - NRF_USBD_INT_ENDEPIN2_MASK = USBD_INTEN_ENDEPIN2_Msk , /**< Enable or disable interrupt for ENDEPIN[2] event */ - NRF_USBD_INT_ENDEPIN3_MASK = USBD_INTEN_ENDEPIN3_Msk , /**< Enable or disable interrupt for ENDEPIN[3] event */ - NRF_USBD_INT_ENDEPIN4_MASK = USBD_INTEN_ENDEPIN4_Msk , /**< Enable or disable interrupt for ENDEPIN[4] event */ - NRF_USBD_INT_ENDEPIN5_MASK = USBD_INTEN_ENDEPIN5_Msk , /**< Enable or disable interrupt for ENDEPIN[5] event */ - NRF_USBD_INT_ENDEPIN6_MASK = USBD_INTEN_ENDEPIN6_Msk , /**< Enable or disable interrupt for ENDEPIN[6] event */ - NRF_USBD_INT_ENDEPIN7_MASK = USBD_INTEN_ENDEPIN7_Msk , /**< Enable or disable interrupt for ENDEPIN[7] event */ - NRF_USBD_INT_EP0DATADONE_MASK = USBD_INTEN_EP0DATADONE_Msk, /**< Enable or disable interrupt for EP0DATADONE event */ - NRF_USBD_INT_ENDISOIN0_MASK = USBD_INTEN_ENDISOIN_Msk , /**< Enable or disable interrupt for ENDISOIN[0] event */ - NRF_USBD_INT_ENDEPOUT0_MASK = USBD_INTEN_ENDEPOUT0_Msk , /**< Enable or disable interrupt for ENDEPOUT[0] event */ - NRF_USBD_INT_ENDEPOUT1_MASK = USBD_INTEN_ENDEPOUT1_Msk , /**< Enable or disable interrupt for ENDEPOUT[1] event */ - NRF_USBD_INT_ENDEPOUT2_MASK = USBD_INTEN_ENDEPOUT2_Msk , /**< Enable or disable interrupt for ENDEPOUT[2] event */ - NRF_USBD_INT_ENDEPOUT3_MASK = USBD_INTEN_ENDEPOUT3_Msk , /**< Enable or disable interrupt for ENDEPOUT[3] event */ - NRF_USBD_INT_ENDEPOUT4_MASK = USBD_INTEN_ENDEPOUT4_Msk , /**< Enable or disable interrupt for ENDEPOUT[4] event */ - NRF_USBD_INT_ENDEPOUT5_MASK = USBD_INTEN_ENDEPOUT5_Msk , /**< Enable or disable interrupt for ENDEPOUT[5] event */ - NRF_USBD_INT_ENDEPOUT6_MASK = USBD_INTEN_ENDEPOUT6_Msk , /**< Enable or disable interrupt for ENDEPOUT[6] event */ - NRF_USBD_INT_ENDEPOUT7_MASK = USBD_INTEN_ENDEPOUT7_Msk , /**< Enable or disable interrupt for ENDEPOUT[7] event */ - NRF_USBD_INT_ENDISOOUT0_MASK = USBD_INTEN_ENDISOOUT_Msk , /**< Enable or disable interrupt for ENDISOOUT[0] event */ - NRF_USBD_INT_SOF_MASK = USBD_INTEN_SOF_Msk , /**< Enable or disable interrupt for SOF event */ - NRF_USBD_INT_USBEVENT_MASK = USBD_INTEN_USBEVENT_Msk , /**< Enable or disable interrupt for USBEVENT event */ - NRF_USBD_INT_EP0SETUP_MASK = USBD_INTEN_EP0SETUP_Msk , /**< Enable or disable interrupt for EP0SETUP event */ - NRF_USBD_INT_DATAEP_MASK = USBD_INTEN_EPDATA_Msk , /**< Enable or disable interrupt for EPDATA event */ -}nrf_usbd_int_mask_t; - - -/** - * @brief Function for activating a specific USBD task. - * - * @param task Task. - */ -__STATIC_INLINE void nrf_usbd_task_trigger(nrf_usbd_task_t task); - -/** - * @brief Function for returning the address of a specific USBD task register. - * - * @param task Task. - * - * @return Task address. - */ -__STATIC_INLINE uint32_t nrf_usbd_task_address_get(nrf_usbd_task_t task); - -/** - * @brief Function for clearing a specific event. - * - * @param event Event. - */ -__STATIC_INLINE void nrf_usbd_event_clear(nrf_usbd_event_t event); - -/** - * @brief Function for returning the state of a specific event. - * - * @param event Event. - * - * @retval true If the event is set. - * @retval false If the event is not set. - */ -__STATIC_INLINE bool nrf_usbd_event_check(nrf_usbd_event_t event); - -/** - * @brief Function for getting and clearing the state of specific event - * - * This function checks the state of the event and clears it. - * - * @param event Event. - * - * @retval true If the event was set. - * @retval false If the event was not set. - */ -__STATIC_INLINE bool nrf_usbd_event_get_and_clear(nrf_usbd_event_t event); - -/** - * @brief Function for returning the address of a specific USBD event register. - * - * @param event Event. - * - * @return Address. - */ -__STATIC_INLINE uint32_t nrf_usbd_event_address_get(nrf_usbd_event_t event); - -/** - * @brief Function for setting a shortcut. - * - * @param short_mask Shortcuts mask. - */ -__STATIC_INLINE void nrf_usbd_shorts_enable(uint32_t short_mask); - -/** - * @brief Function for clearing shortcuts. - * - * @param short_mask Shortcuts mask. - */ -__STATIC_INLINE void nrf_usbd_shorts_disable(uint32_t short_mask); - -/** - * @brief Get the shorts mask - * - * Function returns shorts register. - * - * @return Flags of currently enabled shortcuts - */ -__STATIC_INLINE uint32_t nrf_usbd_shorts_get(void); - -/** - * @brief Function for enabling selected interrupts. - * - * @param int_mask Interrupts mask. - */ -__STATIC_INLINE void nrf_usbd_int_enable(uint32_t int_mask); - -/** - * @brief Function for retrieving the state of selected interrupts. - * - * @param int_mask Interrupts mask. - * - * @retval true If any of selected interrupts is enabled. - * @retval false If none of selected interrupts is enabled. - */ -__STATIC_INLINE bool nrf_usbd_int_enable_check(uint32_t int_mask); - -/** - * @brief Function for retrieving the information about enabled interrupts. - * - * @return The flags of enabled interrupts. - */ -__STATIC_INLINE uint32_t nrf_usbd_int_enable_get(void); - -/** - * @brief Function for disabling selected interrupts. - * - * @param int_mask Interrupts mask. - */ -__STATIC_INLINE void nrf_usbd_int_disable(uint32_t int_mask); - - -/** @} */ /* End of nrf_usbd_hal */ - - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -/* ------------------------------------------------------------------------------------------------ - * Internal functions - */ - -/** - * @internal - * @brief Internal function for getting task/event register address - * - * @oaram offset Offset of the register from the instance beginning - * - * @attention offset has to be modulo 4 value. In other case we can get hardware fault. - * @return Pointer to the register - */ -__STATIC_INLINE volatile uint32_t* nrf_usbd_getRegPtr(uint32_t offset) -{ - return (volatile uint32_t*)(((uint8_t *)NRF_USBD) + (uint32_t)offset); -} - -/** - * @internal - * @brief Internal function for getting task/event register address - constant version - * - * @oaram offset Offset of the register from the instance beginning - * - * @attention offset has to be modulo 4 value. In other case we can get hardware fault. - * @return Pointer to the register - */ -__STATIC_INLINE volatile const uint32_t* nrf_usbd_getRegPtr_c(uint32_t offset) -{ - return (volatile const uint32_t*)(((uint8_t *)NRF_USBD) + (uint32_t)offset); -} - -/* ------------------------------------------------------------------------------------------------ - * Interface functions definitions - */ - -void nrf_usbd_task_trigger(nrf_usbd_task_t task) -{ - *(nrf_usbd_getRegPtr((uint32_t)task)) = 1UL; - __ISB(); - __DSB(); -} - -uint32_t nrf_usbd_task_address_get(nrf_usbd_task_t task) -{ - return (uint32_t)nrf_usbd_getRegPtr_c((uint32_t)task); -} - -void nrf_usbd_event_clear(nrf_usbd_event_t event) -{ - *(nrf_usbd_getRegPtr((uint32_t)event)) = 0UL; - __ISB(); - __DSB(); -} - -bool nrf_usbd_event_check(nrf_usbd_event_t event) -{ - return (bool)*nrf_usbd_getRegPtr_c((uint32_t)event); -} - -bool nrf_usbd_event_get_and_clear(nrf_usbd_event_t event) -{ - bool ret = nrf_usbd_event_check(event); - if (ret) - { - nrf_usbd_event_clear(event); - } - return ret; -} - -uint32_t nrf_usbd_event_address_get(nrf_usbd_event_t event) -{ - return (uint32_t)nrf_usbd_getRegPtr_c((uint32_t)event); -} - -void nrf_usbd_shorts_enable(uint32_t short_mask) -{ - NRF_USBD->SHORTS |= short_mask; -} - -void nrf_usbd_shorts_disable(uint32_t short_mask) -{ - if (~0U == short_mask) - { - /* Optimized version for "disable all" */ - NRF_USBD->SHORTS = 0; - } - else - { - NRF_USBD->SHORTS &= ~short_mask; - } -} - -uint32_t nrf_usbd_shorts_get(void) -{ - return NRF_USBD->SHORTS; -} - -void nrf_usbd_int_enable(uint32_t int_mask) -{ - NRF_USBD->INTENSET = int_mask; -} - -bool nrf_usbd_int_enable_check(uint32_t int_mask) -{ - return !!(NRF_USBD->INTENSET & int_mask); -} - -uint32_t nrf_usbd_int_enable_get(void) -{ - return NRF_USBD->INTENSET; -} - -void nrf_usbd_int_disable(uint32_t int_mask) -{ - NRF_USBD->INTENCLR = int_mask; -} - -#endif /* SUPPRESS_INLINE_IMPLEMENTATION */ - -/* ------------------------------------------------------------------------------------------------ - * End of automatically generated part - * ------------------------------------------------------------------------------------------------ - */ -/** - * @addtogroup nrf_usbd_hal - * @{ - */ - -/** - * @brief Frame counter size - * - * The number of counts that can be fitted into frame counter - */ -#define NRF_USBD_FRAMECNTR_SIZE \ - ( (USBD_FRAMECNTR_FRAMECNTR_Msk >> USBD_FRAMECNTR_FRAMECNTR_Pos) + 1UL ) -#ifndef USBD_FRAMECNTR_FRAMECNTR_Msk -#error USBD_FRAMECNTR_FRAMECNTR_Msk should be changed into USBD_FRAMECNTR_FRAMECNTR_Msk -#endif - -/** - * @brief First isochronous endpoint number - * - * The number of the first isochronous endpoint - */ -#define NRF_USBD_EPISO_FIRST 8 - -/** - * @brief Total number of IN endpoints - * - * Total number of IN endpoint (including ISOCHRONOUS). - */ -#define NRF_USBD_EPIN_CNT 9 - -/** - * @brief Total number of OUT endpoints - * - * Total number of OUT endpoint (including ISOCHRONOUS). - */ -#define NRF_USBD_EPOUT_CNT 9 - -/** - * @brief Mask of the direction bit in endpoint number - */ -#define NRF_USBD_EP_DIR_Msk (1U << 7) - -/** - * @brief The value of direction bit for IN endpoint direction - */ -#define NRF_USBD_EP_DIR_IN (1U << 7) - -/** - * @brief The value of direction bit for OUT endpoint direction - */ -#define NRF_USBD_EP_DIR_OUT (0U << 7) - -/** - * @brief Macro for making IN endpoint identifier from endpoint number - * - * Macro that sets direction bit to make IN endpoint - * @param[in] epnr Endpoint number - * @return IN Endpoint identifier - */ -#define NRF_USBD_EPIN(epnr) (((uint8_t)(epnr)) | NRF_USBD_EP_DIR_IN) - -/** - * @brief Macro for making OUT endpoint identifier from endpoint number - * - * Macro that sets direction bit to make OUT endpoint - * @param[in] epnr Endpoint number - * @return OUT Endpoint identifier - */ -#define NRF_USBD_EPOUT(epnr) (((uint8_t)(epnr)) | NRF_USBD_EP_DIR_OUT) - -/** - * @brief Macro for extracting the endpoint number from endpoint identifier - * - * Macro that strips out the information about endpoint direction. - * @param[in] ep Endpoint identifier - * @return Endpoint number - */ -#define NRF_USBD_EP_NR_GET(ep) ((uint8_t)(((uint8_t)(ep)) & 0xFU)) - -/** - * @brief Macro for checking endpoint direction - * - * This macro checks if given endpoint has IN direction - * @param ep Endpoint identifier - * @retval true If the endpoint direction is IN - * @retval false If the endpoint direction is OUT - */ -#define NRF_USBD_EPIN_CHECK(ep) ( (((uint8_t)(ep)) & NRF_USBD_EP_DIR_Msk) == NRF_USBD_EP_DIR_IN ) - -/** - * @brief Macro for checking endpoint direction - * - * This macro checks if given endpoint has OUT direction - * @param ep Endpoint identifier - * @retval true If the endpoint direction is OUT - * @retval false If the endpoint direction is IN - */ -#define NRF_USBD_EPOUT_CHECK(ep) ( (((uint8_t)(ep)) & NRF_USBD_EP_DIR_Msk) == NRF_USBD_EP_DIR_OUT ) - -/** - * @brief Macro for checking if endpoint is isochronous - * - * @param ep It can be endpoint identifier or just endpoint number to check - * @retval true The endpoint is isochronous type - * @retval false The endpoint is bulk of interrupt type - */ -#define NRF_USBD_EPISO_CHECK(ep) (NRF_USBD_EP_NR_GET(ep) >= NRF_USBD_EPISO_FIRST) - -/** - * @brief Macro for checking if given number is valid endpoint number - * - * @param ep Endpoint number to check - * @retval true The endpoint is valid - * @retval false The endpoint is not valid - */ -#define NRF_USBD_EP_VALIDATE(ep) ( \ - (NRF_USBD_EPIN_CHECK(ep) && (NRF_USBD_EP_NR_GET(ep) < NRF_USBD_EPIN_CNT)) \ - || \ - (NRF_USBD_EPOUT_CHECK(ep) && (NRF_USBD_EP_NR_GET(ep) < NRF_USBD_EPOUT_CNT)) \ - ) - -/** - * @brief Not isochronous data frame received - * - * Special value returned by @ref nrf_usbd_episoout_size_get function that means that - * data frame was not received at all. - * This allows differentiate between situations when zero size data comes or no data comes at all - * on isochronous endpoint. - */ -#define NRF_USBD_EPISOOUT_NO_DATA ((size_t)(-1)) - -/** - * @brief EVENTCAUSE register bit masks - */ -typedef enum -{ - NRF_USBD_EVENTCAUSE_ISOOUTCRC_MASK = USBD_EVENTCAUSE_ISOOUTCRC_Msk, /**< CRC error was detected on isochronous OUT endpoint 8. */ - NRF_USBD_EVENTCAUSE_SUSPEND_MASK = USBD_EVENTCAUSE_SUSPEND_Msk , /**< Signals that the USB lines have been seen idle long enough for the device to enter suspend. */ - NRF_USBD_EVENTCAUSE_RESUME_MASK = USBD_EVENTCAUSE_RESUME_Msk , /**< Signals that a RESUME condition (K state or activity restart) has been detected on the USB lines. */ - NRF_USBD_EVENTCAUSE_READY_MASK = USBD_EVENTCAUSE_READY_Msk, /**< MAC is ready for normal operation, rised few us after USBD enabling */ - NRF_USBD_EVENTCAUSE_WUREQ_MASK = (1U << 10) /**< The USBD peripheral has exited Low Power mode */ -}nrf_usbd_eventcause_mask_t; - -/** - * @brief DPDMVALUE register - */ -typedef enum -{ - /**Generate Resume signal. Signal is generated for 50 us or 5 ms, - * depending on bus state */ - NRF_USBD_DPDMVALUE_RESUME = USBD_DPDMVALUE_STATE_Resume, - /** D+ Forced high, D- forced low (J state) */ - NRF_USBD_DPDMVALUE_J = USBD_DPDMVALUE_STATE_J, - /** D+ Forced low, D- forced high (K state) */ - NRF_USBD_DPMVALUE_K = USBD_DPDMVALUE_STATE_K -}nrf_usbd_dpdmvalue_t; - -/** - * @brief Dtoggle value or operation - */ -typedef enum -{ - NRF_USBD_DTOGGLE_NOP = USBD_DTOGGLE_VALUE_Nop, /**< No operation - do not change current data toggle on selected endpoint */ - NRF_USBD_DTOGGLE_DATA0 = USBD_DTOGGLE_VALUE_Data0,/**< Data toggle is DATA0 on selected endpoint */ - NRF_USBD_DTOGGLE_DATA1 = USBD_DTOGGLE_VALUE_Data1 /**< Data toggle is DATA1 on selected endpoint */ -}nrf_usbd_dtoggle_t; - -/** - * @brief EPSTATUS bit masks - */ -typedef enum -{ - NRF_USBD_EPSTATUS_EPIN0_MASK = USBD_EPSTATUS_EPIN0_Msk, - NRF_USBD_EPSTATUS_EPIN1_MASK = USBD_EPSTATUS_EPIN1_Msk, - NRF_USBD_EPSTATUS_EPIN2_MASK = USBD_EPSTATUS_EPIN2_Msk, - NRF_USBD_EPSTATUS_EPIN3_MASK = USBD_EPSTATUS_EPIN3_Msk, - NRF_USBD_EPSTATUS_EPIN4_MASK = USBD_EPSTATUS_EPIN4_Msk, - NRF_USBD_EPSTATUS_EPIN5_MASK = USBD_EPSTATUS_EPIN5_Msk, - NRF_USBD_EPSTATUS_EPIN6_MASK = USBD_EPSTATUS_EPIN6_Msk, - NRF_USBD_EPSTATUS_EPIN7_MASK = USBD_EPSTATUS_EPIN7_Msk, - - NRF_USBD_EPSTATUS_EPOUT0_MASK = USBD_EPSTATUS_EPOUT0_Msk, - NRF_USBD_EPSTATUS_EPOUT1_MASK = USBD_EPSTATUS_EPOUT1_Msk, - NRF_USBD_EPSTATUS_EPOUT2_MASK = USBD_EPSTATUS_EPOUT2_Msk, - NRF_USBD_EPSTATUS_EPOUT3_MASK = USBD_EPSTATUS_EPOUT3_Msk, - NRF_USBD_EPSTATUS_EPOUT4_MASK = USBD_EPSTATUS_EPOUT4_Msk, - NRF_USBD_EPSTATUS_EPOUT5_MASK = USBD_EPSTATUS_EPOUT5_Msk, - NRF_USBD_EPSTATUS_EPOUT6_MASK = USBD_EPSTATUS_EPOUT6_Msk, - NRF_USBD_EPSTATUS_EPOUT7_MASK = USBD_EPSTATUS_EPOUT7_Msk, -}nrf_usbd_epstatus_mask_t; - -/** - * @brief DATAEPSTATUS bit masks - */ -typedef enum -{ - NRF_USBD_EPDATASTATUS_EPIN1_MASK = USBD_EPDATASTATUS_EPIN1_Msk, - NRF_USBD_EPDATASTATUS_EPIN2_MASK = USBD_EPDATASTATUS_EPIN2_Msk, - NRF_USBD_EPDATASTATUS_EPIN3_MASK = USBD_EPDATASTATUS_EPIN3_Msk, - NRF_USBD_EPDATASTATUS_EPIN4_MASK = USBD_EPDATASTATUS_EPIN4_Msk, - NRF_USBD_EPDATASTATUS_EPIN5_MASK = USBD_EPDATASTATUS_EPIN5_Msk, - NRF_USBD_EPDATASTATUS_EPIN6_MASK = USBD_EPDATASTATUS_EPIN6_Msk, - NRF_USBD_EPDATASTATUS_EPIN7_MASK = USBD_EPDATASTATUS_EPIN7_Msk, - - NRF_USBD_EPDATASTATUS_EPOUT1_MASK = USBD_EPDATASTATUS_EPOUT1_Msk, - NRF_USBD_EPDATASTATUS_EPOUT2_MASK = USBD_EPDATASTATUS_EPOUT2_Msk, - NRF_USBD_EPDATASTATUS_EPOUT3_MASK = USBD_EPDATASTATUS_EPOUT3_Msk, - NRF_USBD_EPDATASTATUS_EPOUT4_MASK = USBD_EPDATASTATUS_EPOUT4_Msk, - NRF_USBD_EPDATASTATUS_EPOUT5_MASK = USBD_EPDATASTATUS_EPOUT5_Msk, - NRF_USBD_EPDATASTATUS_EPOUT6_MASK = USBD_EPDATASTATUS_EPOUT6_Msk, - NRF_USBD_EPDATASTATUS_EPOUT7_MASK = USBD_EPDATASTATUS_EPOUT7_Msk, -}nrf_usbd_dataepstatus_mask_t; - -/** - * @brief ISOSPLIT configurations - */ -typedef enum -{ - NRF_USBD_ISOSPLIT_OneDir = USBD_ISOSPLIT_SPLIT_OneDir, /**< Full buffer dedicated to either iso IN or OUT */ - NRF_USBD_ISOSPLIT_Half = USBD_ISOSPLIT_SPLIT_HalfIN, /**< Buffer divided in half */ -}nrf_usbd_isosplit_t; - -/** - * @brief Function for enabling USBD - */ -__STATIC_INLINE void nrf_usbd_enable(void); - -/** - * @brief Function for disabling USBD - */ -__STATIC_INLINE void nrf_usbd_disable(void); - -/** - * @brief Function for getting EVENTCAUSE register - * - * @return Flag values defined in @ref nrf_usbd_eventcause_mask_t - */ -__STATIC_INLINE uint32_t nrf_usbd_eventcause_get(void); - -/** - * @brief Function for clearing EVENTCAUSE flags - * - * @param flags Flags defined in @ref nrf_usbd_eventcause_mask_t - */ -__STATIC_INLINE void nrf_usbd_eventcause_clear(uint32_t flags); - -/** - * @brief Function for getting EVENTCAUSE register and clear flags that are set - * - * The safest way to return current EVENTCAUSE register. - * All the flags that are returned would be cleared inside EVENTCAUSE register. - * - * @return Flag values defined in @ref nrf_usbd_eventcause_mask_t - */ -__STATIC_INLINE uint32_t nrf_usbd_eventcause_get_and_clear(void); - -/** - * @brief Function for getting HALTEDEPIN register value - * - * @param ep Endpoint number with IN/OUT flag - * - * @return The value of HALTEDEPIN or HALTEDOUT register for selected endpoint - * - * @note - * Use this function for the response for GetStatus() request to endpoint. - * To check if endpoint is stalled in the code use @ref nrf_usbd_ep_is_stall. - */ -__STATIC_INLINE uint32_t nrf_usbd_haltedep(uint8_t ep); - -/** - * @brief Function for checking if selected endpoint is stalled - * - * Function to be used as a syntax sweeter for @ref nrf_usbd_haltedep. - * - * Also as the isochronous endpoint cannot be halted - it returns always false - * if isochronous endpoint is checked. - * - * @param ep Endpoint number with IN/OUT flag - * - * @return The information if the enepoint is halted. - */ -__STATIC_INLINE bool nrf_usbd_ep_is_stall(uint8_t ep); - -/** - * @brief Function for getting EPSTATUS register value - * - * @return Flag values defined in @ref nrf_usbd_epstatus_mask_t - */ -__STATIC_INLINE uint32_t nrf_usbd_epstatus_get(void); - -/** - * @brief Function for clearing EPSTATUS register value - * - * @param flags Flags defined in @ref nrf_usbd_epstatus_mask_t - */ -__STATIC_INLINE void nrf_usbd_epstatus_clear(uint32_t flags); - -/** - * @brief Function for getting and clearing EPSTATUS register value - * - * Function clears all flags in register set before returning its value. - * @return Flag values defined in @ref nrf_usbd_epstatus_mask_t - */ -__STATIC_INLINE uint32_t nrf_usbd_epstatus_get_and_clear(void); - -/** - * @brief Function for getting DATAEPSTATUS register value - * - * @return Flag values defined in @ref nrf_usbd_dataepstatus_mask_t - */ -__STATIC_INLINE uint32_t nrf_usbd_epdatastatus_get(void); - -/** - * @brief Function for clearing DATAEPSTATUS register value - * - * @param flags Flags defined in @ref nrf_usbd_dataepstatus_mask_t - */ -__STATIC_INLINE void nrf_usbd_epdatastatus_clear(uint32_t flags); - -/** - * @brief Function for getting and clearing DATAEPSTATUS register value - * - * Function clears all flags in register set before returning its value. - * @return Flag values defined in @ref nrf_usbd_dataepstatus_mask_t - */ -__STATIC_INLINE uint32_t nrf_usbd_epdatastatus_get_and_clear(void); - -/** - * @name Setup command frame functions - * - * Functions for setup command frame parts access - * @{ - */ - /** - * @brief Function for reading BMREQUESTTYPE - part of SETUP packet - * - * @return the value of BREQUESTTYPE on last received SETUP frame - */ - __STATIC_INLINE uint8_t nrf_usbd_setup_bmrequesttype_get(void); - - /** - * @brief Function for reading BMREQUEST - part of SETUP packet - * - * @return the value of BREQUEST on last received SETUP frame - */ - __STATIC_INLINE uint8_t nrf_usbd_setup_brequest_get(void); - - /** - * @brief Function for reading WVALUE - part of SETUP packet - * - * @return the value of WVALUE on last received SETUP frame - */ - __STATIC_INLINE uint16_t nrf_usbd_setup_wvalue_get(void); - - /** - * @brief Function for reading WINDEX - part of SETUP packet - * - * @return the value of WINDEX on last received SETUP frame - */ - __STATIC_INLINE uint16_t nrf_usbd_setup_windex_get(void); - - /** - * @brief Function for reading WLENGTH - part of SETUP packet - * - * @return the value of WLENGTH on last received SETUP frame - */ - __STATIC_INLINE uint16_t nrf_usbd_setup_wlength_get(void); -/** @} */ - -/** - * @brief Function for getting number of received bytes on selected endpoint - * - * @param ep Endpoint identifier. - * - * @return Number of received bytes. - * - * @note This function may be used on Bulk/Interrupt and Isochronous endpoints. - * @note For the function that returns different value for ISOOUT zero transfer or no transfer at all, - * see @ref nrf_usbd_episoout_size_get function. This function would return 0 for both cases. - */ -__STATIC_INLINE size_t nrf_usbd_epout_size_get(uint8_t ep); - -/** - * @brief Function for getting number of received bytes on isochronous endpoint. - * - * @param ep Endpoint identifier, has to be isochronous out endpoint. - * - * @return Number of bytes received or @ref NRF_USBD_EPISOOUT_NO_DATA - */ -__STATIC_INLINE size_t nrf_usbd_episoout_size_get(uint8_t ep); - -/** - * @brief Function for clearing out endpoint to accept any new incoming traffic - * - * @param ep ep Endpoint identifier. Only OUT Interrupt/Bulk endpoints are accepted. - */ -__STATIC_INLINE void nrf_usbd_epout_clear(uint8_t ep); - -/** - * @brief Function for enabling USB pullup - */ -__STATIC_INLINE void nrf_usbd_pullup_enable(void); - -/** - * @brief Function for disabling USB pullup - */ -__STATIC_INLINE void nrf_usbd_pullup_disable(void); - -/** - * @brief Function for returning current USB pullup state - * - * @retval true USB pullup is enabled - * @retval false USB pullup is disabled - */ -__STATIC_INLINE bool nrf_usbd_pullup_check(void); - -/** - * @brief Function for configuring the value to be forced on the bus on DRIVEDPDM task - * - * Selected state would be forced on the bus when @ref NRF_USBD_TASK_DRIVEDPDM is set. - * The state would be removed from the bus on @ref NRF_USBD_TASK_NODRIVEDPDM and - * the control would be returned to the USBD peripheral. - * @param val State to be set - */ -__STATIC_INLINE void nrf_usbd_dpdmvalue_set(nrf_usbd_dpdmvalue_t val); - -/** - * @brief Function for setting data toggle - * - * Configuration of current state of data toggling - * @param ep Endpoint number with the information about its direction - * @param op Operation to execute - */ -__STATIC_INLINE void nrf_usbd_dtoggle_set(uint8_t ep, nrf_usbd_dtoggle_t op); - -/** - * @brief Function for getting data toggle - * - * Get the current state of data toggling - * @param ep Endpoint number to return the information about current data toggling - * @retval NRF_USBD_DTOGGLE_DATA0 Data toggle is DATA0 on selected endpoint - * @retval NRF_USBD_DTOGGLE_DATA1 Data toggle is DATA1 on selected endpoint - */ -__STATIC_INLINE nrf_usbd_dtoggle_t nrf_usbd_dtoggle_get(uint8_t ep); - -/** - * @brief Function for checking if endpoint is enabled - * - * @param ep Endpoint id to check - * - * @retval true Endpoint is enabled - * @retval false Endpoint is disabled - */ -__STATIC_INLINE bool nrf_usbd_ep_enable_check(uint8_t ep); - -/** - * @brief Function for enabling selected endpoint - * - * Enabled endpoint responds for the tokens on the USB bus - * - * @param ep Endpoint id to enable - */ -__STATIC_INLINE void nrf_usbd_ep_enable(uint8_t ep); - -/** - * @brief Function for disabling selected endpoint - * - * Disabled endpoint does not respond for the tokens on the USB bus - * - * @param ep Endpoint id to disable - */ -__STATIC_INLINE void nrf_usbd_ep_disable(uint8_t ep); - -/** - * @brief Function for disabling all endpoints - * - * Auxiliary function to simply disable all aviable endpoints. - * It lefts only EP0 IN and OUT enabled. - */ -__STATIC_INLINE void nrf_usbd_ep_all_disable(void); - -/** - * @brief Function for stalling selected endpoint - * - * @param ep Endpoint identifier - * @note This function cannot be called on isochronous endpoint - */ -__STATIC_INLINE void nrf_usbd_ep_stall(uint8_t ep); - -/** - * @brief Function for unstalling selected endpoint - * - * @param ep Endpoint identifier - * @note This function cannot be called on isochronous endpoint - */ -__STATIC_INLINE void nrf_usbd_ep_unstall(uint8_t ep); - -/** - * @brief Function for configuration of isochronous buffer splitting - * - * Configure isochronous buffer splitting between IN and OUT endpoints. - * - * @param split Required configuration - */ -__STATIC_INLINE void nrf_usbd_isosplit_set(nrf_usbd_isosplit_t split); - -/** - * @brief Function for getting the isochronous buffer splitting configuration - * - * Get the current isochronous buffer splitting configuration. - * - * @return Current configuration - */ -__STATIC_INLINE nrf_usbd_isosplit_t nrf_usbd_isosplit_get(void); - -/** - * @brief Function for getting current frame counter - * - * @return Current frame counter - */ -__STATIC_INLINE uint32_t nrf_usbd_framecntr_get(void); - -/** - * @brief Function for entering into low power mode - * - * After this function is called the clock source from the USBD is disconnected internally. - * After this function is called most of the USBD registers cannot be accessed anymore. - * - * @sa nrf_usbd_lowpower_disable - * @sa nrf_usbd_lowpower_check - */ -__STATIC_INLINE void nrf_usbd_lowpower_enable(void); - -/** - * @brief Function for exiting from low power mode - * - * After this function is called the clock source for the USBD is connected internally. - * The @ref NRF_USBD_EVENTCAUSE_WUREQ_MASK event would be generated and - * then the USBD registers may be accessed. - * - * @sa nrf_usbd_lowpower_enable - * @sa nrf_usbd_lowpower_check - */ -__STATIC_INLINE void nrf_usbd_lowpower_disable(void); - -/** - * @brief Function for checking the state of the low power mode - * - * @retval true USBD is in low power mode - * @retval false USBD is not in low power mode - */ -__STATIC_INLINE bool nrf_usbd_lowpower_check(void); - -/** - * @brief Function for configuring EasyDMA channel - * - * Configures EasyDMA for the transfer. - * - * @param ep Endpoint identifier (with direction) - * @param ptr Pointer to the data - * @param maxcnt Number of bytes to transfer - */ -__STATIC_INLINE void nrf_usbd_ep_easydma_set(uint8_t ep, uint32_t ptr, uint32_t maxcnt); - -/** - * @brief Function for getting number of transferred bytes - * - * Get number of transferred bytes in the last transaction - * - * @param ep Endpoint identifier - * - * @return The content of the AMOUNT register - */ -__STATIC_INLINE uint32_t nrf_usbd_ep_amount_get(uint8_t ep); - - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -void nrf_usbd_enable(void) -{ -#ifdef NRF_FPGA_IMPLEMENTATION - *(volatile uint32_t *)0x400005F4 = 3; - __ISB(); - __DSB(); - *(volatile uint32_t *)0x400005F0 = 3; - __ISB(); - __DSB(); -#endif - - NRF_USBD->ENABLE = USBD_ENABLE_ENABLE_Enabled << USBD_ENABLE_ENABLE_Pos; - __ISB(); - __DSB(); -} - -void nrf_usbd_disable(void) -{ - NRF_USBD->ENABLE = USBD_ENABLE_ENABLE_Disabled << USBD_ENABLE_ENABLE_Pos; - __ISB(); - __DSB(); -} - -uint32_t nrf_usbd_eventcause_get(void) -{ - return NRF_USBD->EVENTCAUSE; -} - -void nrf_usbd_eventcause_clear(uint32_t flags) -{ - NRF_USBD->EVENTCAUSE = flags; - __ISB(); - __DSB(); -} - -uint32_t nrf_usbd_eventcause_get_and_clear(void) -{ - uint32_t ret; - ret = nrf_usbd_eventcause_get(); - nrf_usbd_eventcause_clear(ret); - __ISB(); - __DSB(); - return ret; -} - -uint32_t nrf_usbd_haltedep(uint8_t ep) -{ - uint8_t epnr = NRF_USBD_EP_NR_GET(ep); - if (NRF_USBD_EPIN_CHECK(ep)) - { - NRFX_ASSERT(epnr < ARRAY_SIZE(NRF_USBD->HALTED.EPIN)); - return NRF_USBD->HALTED.EPIN[epnr]; - } - else - { - NRFX_ASSERT(epnr < ARRAY_SIZE(NRF_USBD->HALTED.EPOUT)); - return NRF_USBD->HALTED.EPOUT[epnr]; - } -} - -bool nrf_usbd_ep_is_stall(uint8_t ep) -{ - if (NRF_USBD_EPISO_CHECK(ep)) - return false; - return USBD_HALTED_EPOUT_GETSTATUS_Halted == nrf_usbd_haltedep(ep); -} - -uint32_t nrf_usbd_epstatus_get(void) -{ - return NRF_USBD->EPSTATUS; -} - -void nrf_usbd_epstatus_clear(uint32_t flags) -{ - NRF_USBD->EPSTATUS = flags; - __ISB(); - __DSB(); -} - -uint32_t nrf_usbd_epstatus_get_and_clear(void) -{ - uint32_t ret; - ret = nrf_usbd_epstatus_get(); - nrf_usbd_epstatus_clear(ret); - return ret; -} - -uint32_t nrf_usbd_epdatastatus_get(void) -{ - return NRF_USBD->EPDATASTATUS; -} - -void nrf_usbd_epdatastatus_clear(uint32_t flags) -{ - NRF_USBD->EPDATASTATUS = flags; - __ISB(); - __DSB(); -} - -uint32_t nrf_usbd_epdatastatus_get_and_clear(void) -{ - uint32_t ret; - ret = nrf_usbd_epdatastatus_get(); - nrf_usbd_epdatastatus_clear(ret); - __ISB(); - __DSB(); - return ret; -} - -uint8_t nrf_usbd_setup_bmrequesttype_get(void) -{ - return (uint8_t)(NRF_USBD->BMREQUESTTYPE); -} - -uint8_t nrf_usbd_setup_brequest_get(void) -{ - return (uint8_t)(NRF_USBD->BREQUEST); -} - -uint16_t nrf_usbd_setup_wvalue_get(void) -{ - const uint16_t val = NRF_USBD->WVALUEL; - return (uint16_t)(val | ((NRF_USBD->WVALUEH) << 8)); -} - -uint16_t nrf_usbd_setup_windex_get(void) -{ - const uint16_t val = NRF_USBD->WINDEXL; - return (uint16_t)(val | ((NRF_USBD->WINDEXH) << 8)); -} - -uint16_t nrf_usbd_setup_wlength_get(void) -{ - const uint16_t val = NRF_USBD->WLENGTHL; - return (uint16_t)(val | ((NRF_USBD->WLENGTHH) << 8)); -} - -size_t nrf_usbd_epout_size_get(uint8_t ep) -{ - NRFX_ASSERT(NRF_USBD_EP_VALIDATE(ep)); - NRFX_ASSERT(NRF_USBD_EPOUT_CHECK(ep)); - if (NRF_USBD_EPISO_CHECK(ep)) - { - size_t size_isoout = NRF_USBD->SIZE.ISOOUT; - if ((size_isoout & USBD_SIZE_ISOOUT_ZERO_Msk) == (USBD_SIZE_ISOOUT_ZERO_ZeroData << USBD_SIZE_ISOOUT_ZERO_Pos)) - { - size_isoout = 0; - } - return size_isoout; - } - - NRFX_ASSERT(NRF_USBD_EP_NR_GET(ep) < ARRAY_SIZE(NRF_USBD->SIZE.EPOUT)); - return NRF_USBD->SIZE.EPOUT[NRF_USBD_EP_NR_GET(ep)]; -} - -size_t nrf_usbd_episoout_size_get(uint8_t ep) -{ - NRFX_ASSERT(NRF_USBD_EP_VALIDATE(ep)); - NRFX_ASSERT(NRF_USBD_EPOUT_CHECK(ep)); - NRFX_ASSERT(NRF_USBD_EPISO_CHECK(ep)); - - size_t size_isoout = NRF_USBD->SIZE.ISOOUT; - if (size_isoout == 0) - { - size_isoout = NRF_USBD_EPISOOUT_NO_DATA; - } - else if ((size_isoout & USBD_SIZE_ISOOUT_ZERO_Msk) == (USBD_SIZE_ISOOUT_ZERO_ZeroData << USBD_SIZE_ISOOUT_ZERO_Pos)) - { - size_isoout = 0; - } - return size_isoout; -} - -void nrf_usbd_epout_clear(uint8_t ep) -{ - NRFX_ASSERT(NRF_USBD_EPOUT_CHECK(ep) && (NRF_USBD_EP_NR_GET(ep) < ARRAY_SIZE(NRF_USBD->SIZE.EPOUT))); - NRF_USBD->SIZE.EPOUT[NRF_USBD_EP_NR_GET(ep)] = 0; - __ISB(); - __DSB(); -} - -void nrf_usbd_pullup_enable(void) -{ - NRF_USBD->USBPULLUP = USBD_USBPULLUP_CONNECT_Enabled << USBD_USBPULLUP_CONNECT_Pos; - __ISB(); - __DSB(); -} - -void nrf_usbd_pullup_disable(void) -{ - NRF_USBD->USBPULLUP = USBD_USBPULLUP_CONNECT_Disabled << USBD_USBPULLUP_CONNECT_Pos; - __ISB(); - __DSB(); -} - -bool nrf_usbd_pullup_check(void) -{ - return NRF_USBD->USBPULLUP == (USBD_USBPULLUP_CONNECT_Enabled << USBD_USBPULLUP_CONNECT_Pos); -} - -void nrf_usbd_dpdmvalue_set(nrf_usbd_dpdmvalue_t val) -{ - NRF_USBD->DPDMVALUE = ((uint32_t)val) << USBD_DPDMVALUE_STATE_Pos; -} - -void nrf_usbd_dtoggle_set(uint8_t ep, nrf_usbd_dtoggle_t op) -{ - NRFX_ASSERT(NRF_USBD_EP_VALIDATE(ep)); - NRFX_ASSERT(!NRF_USBD_EPISO_CHECK(ep)); - NRF_USBD->DTOGGLE = ep | (NRF_USBD_DTOGGLE_NOP << USBD_DTOGGLE_VALUE_Pos); - __DSB(); - NRF_USBD->DTOGGLE = ep | (op << USBD_DTOGGLE_VALUE_Pos); - __ISB(); - __DSB(); -} - -nrf_usbd_dtoggle_t nrf_usbd_dtoggle_get(uint8_t ep) -{ - uint32_t retval; - /* Select the endpoint to read */ - NRF_USBD->DTOGGLE = ep | (NRF_USBD_DTOGGLE_NOP << USBD_DTOGGLE_VALUE_Pos); - retval = ((NRF_USBD->DTOGGLE) & USBD_DTOGGLE_VALUE_Msk) >> USBD_DTOGGLE_VALUE_Pos; - return (nrf_usbd_dtoggle_t)retval; -} - -bool nrf_usbd_ep_enable_check(uint8_t ep) -{ - NRFX_ASSERT(NRF_USBD_EP_VALIDATE(ep)); - uint8_t epnr = NRF_USBD_EP_NR_GET(ep); - - if (NRF_USBD_EPIN_CHECK(ep)) - { - return 0 != (NRF_USBD->EPINEN & (1UL << epnr)); - } - else - { - return 0 != (NRF_USBD->EPOUTEN & (1UL << epnr)); - } -} - -void nrf_usbd_ep_enable(uint8_t ep) -{ - NRFX_ASSERT(NRF_USBD_EP_VALIDATE(ep)); - uint8_t epnr = NRF_USBD_EP_NR_GET(ep); - - if (NRF_USBD_EPIN_CHECK(ep)) - { - NRF_USBD->EPINEN |= 1UL << epnr; - } - else - { - NRF_USBD->EPOUTEN |= 1UL << epnr; - } - __ISB(); - __DSB(); -} - -void nrf_usbd_ep_disable(uint8_t ep) -{ - NRFX_ASSERT(NRF_USBD_EP_VALIDATE(ep)); - uint8_t epnr = NRF_USBD_EP_NR_GET(ep); - - if (NRF_USBD_EPIN_CHECK(ep)) - { - NRF_USBD->EPINEN &= ~(1UL << epnr); - } - else - { - NRF_USBD->EPOUTEN &= ~(1UL << epnr); - } - __ISB(); - __DSB(); -} - -void nrf_usbd_ep_all_disable(void) -{ - NRF_USBD->EPINEN = USBD_EPINEN_IN0_Enable << USBD_EPINEN_IN0_Pos; - NRF_USBD->EPOUTEN = USBD_EPOUTEN_OUT0_Enable << USBD_EPOUTEN_OUT0_Pos; - __ISB(); - __DSB(); -} - -void nrf_usbd_ep_stall(uint8_t ep) -{ - NRFX_ASSERT(!NRF_USBD_EPISO_CHECK(ep)); - NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_Stall << USBD_EPSTALL_STALL_Pos) | ep; - __ISB(); - __DSB(); -} - -void nrf_usbd_ep_unstall(uint8_t ep) -{ - NRFX_ASSERT(!NRF_USBD_EPISO_CHECK(ep)); - NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_UnStall << USBD_EPSTALL_STALL_Pos) | ep; - __ISB(); - __DSB(); -} - -void nrf_usbd_isosplit_set(nrf_usbd_isosplit_t split) -{ - NRF_USBD->ISOSPLIT = split << USBD_ISOSPLIT_SPLIT_Pos; -} - -nrf_usbd_isosplit_t nrf_usbd_isosplit_get(void) -{ - return (nrf_usbd_isosplit_t) - (((NRF_USBD->ISOSPLIT) & USBD_ISOSPLIT_SPLIT_Msk) >> USBD_ISOSPLIT_SPLIT_Pos); -} - -uint32_t nrf_usbd_framecntr_get(void) -{ - return NRF_USBD->FRAMECNTR; -} - -void nrf_usbd_lowpower_enable(void) -{ - NRF_USBD->LOWPOWER = USBD_LOWPOWER_LOWPOWER_LowPower << USBD_LOWPOWER_LOWPOWER_Pos; -} - -void nrf_usbd_lowpower_disable(void) -{ - NRF_USBD->LOWPOWER = USBD_LOWPOWER_LOWPOWER_ForceNormal << USBD_LOWPOWER_LOWPOWER_Pos; -} - -bool nrf_usbd_lowpower_check(void) -{ - return (NRF_USBD->LOWPOWER != (USBD_LOWPOWER_LOWPOWER_ForceNormal << USBD_LOWPOWER_LOWPOWER_Pos)); -} - - -void nrf_usbd_ep_easydma_set(uint8_t ep, uint32_t ptr, uint32_t maxcnt) -{ - if (NRF_USBD_EPIN_CHECK(ep)) - { - if (NRF_USBD_EPISO_CHECK(ep)) - { - NRF_USBD->ISOIN.PTR = ptr; - NRF_USBD->ISOIN.MAXCNT = maxcnt; - } - else - { - uint8_t epnr = NRF_USBD_EP_NR_GET(ep); - NRFX_ASSERT(epnr < ARRAY_SIZE(NRF_USBD->EPIN)); - NRF_USBD->EPIN[epnr].PTR = ptr; - NRF_USBD->EPIN[epnr].MAXCNT = maxcnt; - } - } - else - { - if (NRF_USBD_EPISO_CHECK(ep)) - { - NRF_USBD->ISOOUT.PTR = ptr; - NRF_USBD->ISOOUT.MAXCNT = maxcnt; - } - else - { - uint8_t epnr = NRF_USBD_EP_NR_GET(ep); - NRFX_ASSERT(epnr < ARRAY_SIZE(NRF_USBD->EPOUT)); - NRF_USBD->EPOUT[epnr].PTR = ptr; - NRF_USBD->EPOUT[epnr].MAXCNT = maxcnt; - } - } -} - -uint32_t nrf_usbd_ep_amount_get(uint8_t ep) -{ - uint32_t ret; - - if (NRF_USBD_EPIN_CHECK(ep)) - { - if (NRF_USBD_EPISO_CHECK(ep)) - { - ret = NRF_USBD->ISOIN.AMOUNT; - } - else - { - uint8_t epnr = NRF_USBD_EP_NR_GET(ep); - NRFX_ASSERT(epnr < ARRAY_SIZE(NRF_USBD->EPOUT)); - ret = NRF_USBD->EPIN[epnr].AMOUNT; - } - } - else - { - if (NRF_USBD_EPISO_CHECK(ep)) - { - ret = NRF_USBD->ISOOUT.AMOUNT; - } - else - { - uint8_t epnr = NRF_USBD_EP_NR_GET(ep); - NRFX_ASSERT(epnr < ARRAY_SIZE(NRF_USBD->EPOUT)); - ret = NRF_USBD->EPOUT[epnr].AMOUNT; - } - } - - return ret; -} - -#endif /* SUPPRESS_INLINE_IMPLEMENTATION */ - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* NRF_USBD_H__ */ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_wdt.h b/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_wdt.h deleted file mode 100644 index 44a1f38159..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/hal/nrf_wdt.h +++ /dev/null @@ -1,333 +0,0 @@ -/** - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_WDT_H__ -#define NRF_WDT_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrf_wdt_hal WDT HAL - * @{ - * @ingroup nrf_wdt - * @brief Hardware access layer for managing the Watchdog Timer (WDT) peripheral. - */ - -#define NRF_WDT_CHANNEL_NUMBER 0x8UL -#define NRF_WDT_RR_VALUE 0x6E524635UL /* Fixed value, shouldn't be modified.*/ - -#define NRF_WDT_TASK_SET 1UL -#define NRF_WDT_EVENT_CLEAR 0UL - -/** - * @enum nrf_wdt_task_t - * @brief WDT tasks. - */ -typedef enum -{ - /*lint -save -e30 -esym(628,__INTADDR__)*/ - NRF_WDT_TASK_START = offsetof(NRF_WDT_Type, TASKS_START), /**< Task for starting WDT. */ - /*lint -restore*/ -} nrf_wdt_task_t; - -/** - * @enum nrf_wdt_event_t - * @brief WDT events. - */ -typedef enum -{ - /*lint -save -e30*/ - NRF_WDT_EVENT_TIMEOUT = offsetof(NRF_WDT_Type, EVENTS_TIMEOUT), /**< Event from WDT time-out. */ - /*lint -restore*/ -} nrf_wdt_event_t; - -/** - * @enum nrf_wdt_behaviour_t - * @brief WDT behavior in CPU SLEEP or HALT mode. - */ -typedef enum -{ - NRF_WDT_BEHAVIOUR_RUN_SLEEP = WDT_CONFIG_SLEEP_Msk, /**< WDT will run when CPU is in SLEEP mode. */ - NRF_WDT_BEHAVIOUR_RUN_HALT = WDT_CONFIG_HALT_Msk, /**< WDT will run when CPU is in HALT mode. */ - NRF_WDT_BEHAVIOUR_RUN_SLEEP_HALT = WDT_CONFIG_SLEEP_Msk | WDT_CONFIG_HALT_Msk, /**< WDT will run when CPU is in SLEEP or HALT mode. */ - NRF_WDT_BEHAVIOUR_PAUSE_SLEEP_HALT = 0, /**< WDT will be paused when CPU is in SLEEP or HALT mode. */ -} nrf_wdt_behaviour_t; - -/** - * @enum nrf_wdt_rr_register_t - * @brief WDT reload request registers. - */ -typedef enum -{ - NRF_WDT_RR0 = 0, /**< Reload request register 0. */ - NRF_WDT_RR1, /**< Reload request register 1. */ - NRF_WDT_RR2, /**< Reload request register 2. */ - NRF_WDT_RR3, /**< Reload request register 3. */ - NRF_WDT_RR4, /**< Reload request register 4. */ - NRF_WDT_RR5, /**< Reload request register 5. */ - NRF_WDT_RR6, /**< Reload request register 6. */ - NRF_WDT_RR7 /**< Reload request register 7. */ -} nrf_wdt_rr_register_t; - -/** - * @enum nrf_wdt_int_mask_t - * @brief WDT interrupts. - */ -typedef enum -{ - NRF_WDT_INT_TIMEOUT_MASK = WDT_INTENSET_TIMEOUT_Msk, /**< WDT interrupt from time-out event. */ -} nrf_wdt_int_mask_t; - -/** - * @brief Function for configuring the watchdog behavior when the CPU is sleeping or halted. - * - * @param behaviour Watchdog behavior when CPU is in SLEEP or HALT mode. - */ -__STATIC_INLINE void nrf_wdt_behaviour_set(nrf_wdt_behaviour_t behaviour) -{ - NRF_WDT->CONFIG = behaviour; -} - - -/** - * @brief Function for starting the watchdog. - * - * @param[in] task Task. - */ -__STATIC_INLINE void nrf_wdt_task_trigger(nrf_wdt_task_t task) -{ - *((volatile uint32_t *)((uint8_t *)NRF_WDT + task)) = NRF_WDT_TASK_SET; -} - - -/** - * @brief Function for clearing the WDT event. - * - * @param[in] event Event. - */ -__STATIC_INLINE void nrf_wdt_event_clear(nrf_wdt_event_t event) -{ - *((volatile uint32_t *)((uint8_t *)NRF_WDT + (uint32_t)event)) = NRF_WDT_EVENT_CLEAR; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_WDT + (uint32_t)event)); - (void)dummy; -#endif -} - - -/** - * @brief Function for retrieving the state of the WDT event. - * - * @param[in] event Event. - * - * @retval true If the event is set. - * @retval false If the event is not set. - */ -__STATIC_INLINE bool nrf_wdt_event_check(nrf_wdt_event_t event) -{ - return (bool)*((volatile uint32_t *)((uint8_t *)NRF_WDT + event)); -} - - -/** - * @brief Function for enabling a specific interrupt. - * - * @param[in] int_mask Interrupt. - */ -__STATIC_INLINE void nrf_wdt_int_enable(uint32_t int_mask) -{ - NRF_WDT->INTENSET = int_mask; -} - - -/** - * @brief Function for retrieving the state of given interrupt. - * - * @param[in] int_mask Interrupt. - * - * @retval true Interrupt is enabled. - * @retval false Interrupt is not enabled. - */ -__STATIC_INLINE bool nrf_wdt_int_enable_check(uint32_t int_mask) -{ - return (bool)(NRF_WDT->INTENSET & int_mask); -} - - -/** - * @brief Function for disabling a specific interrupt. - * - * @param[in] int_mask Interrupt. - */ -__STATIC_INLINE void nrf_wdt_int_disable(uint32_t int_mask) -{ - NRF_WDT->INTENCLR = int_mask; -} - - -/** - * @brief Function for returning the address of a specific WDT task register. - * - * @param[in] task Task. - */ -__STATIC_INLINE uint32_t nrf_wdt_task_address_get(nrf_wdt_task_t task) -{ - return ((uint32_t)NRF_WDT + task); -} - - -/** - * @brief Function for returning the address of a specific WDT event register. - * - * @param[in] event Event. - * - * @retval address of requested event register - */ -__STATIC_INLINE uint32_t nrf_wdt_event_address_get(nrf_wdt_event_t event) -{ - return ((uint32_t)NRF_WDT + event); -} - - -/** - * @brief Function for retrieving the watchdog status. - * - * @retval true If the watchdog is started. - * @retval false If the watchdog is not started. - */ -__STATIC_INLINE bool nrf_wdt_started(void) -{ - return (bool)(NRF_WDT->RUNSTATUS); -} - - -/** - * @brief Function for retrieving the watchdog reload request status. - * - * @param[in] rr_register Reload request register to check. - * - * @retval true If a reload request is running. - * @retval false If no reload request is running. - */ -__STATIC_INLINE bool nrf_wdt_request_status(nrf_wdt_rr_register_t rr_register) -{ - return (bool)(((NRF_WDT->REQSTATUS) >> rr_register) & 0x1UL); -} - - -/** - * @brief Function for setting the watchdog reload value. - * - * @param[in] reload_value Watchdog counter initial value. - */ -__STATIC_INLINE void nrf_wdt_reload_value_set(uint32_t reload_value) -{ - NRF_WDT->CRV = reload_value; -} - - -/** - * @brief Function for retrieving the watchdog reload value. - * - * @retval Reload value. - */ -__STATIC_INLINE uint32_t nrf_wdt_reload_value_get(void) -{ - return (uint32_t)NRF_WDT->CRV; -} - - -/** - * @brief Function for enabling a specific reload request register. - * - * @param[in] rr_register Reload request register to enable. - */ -__STATIC_INLINE void nrf_wdt_reload_request_enable(nrf_wdt_rr_register_t rr_register) -{ - NRF_WDT->RREN |= 0x1UL << rr_register; -} - - -/** - * @brief Function for disabling a specific reload request register. - * - * @param[in] rr_register Reload request register to disable. - */ -__STATIC_INLINE void nrf_wdt_reload_request_disable(nrf_wdt_rr_register_t rr_register) -{ - NRF_WDT->RREN &= ~(0x1UL << rr_register); -} - - -/** - * @brief Function for retrieving the status of a specific reload request register. - * - * @param[in] rr_register Reload request register to check. - * - * @retval true If the reload request register is enabled. - * @retval false If the reload request register is not enabled. - */ -__STATIC_INLINE bool nrf_wdt_reload_request_is_enabled(nrf_wdt_rr_register_t rr_register) -{ - return (bool)(NRF_WDT->RREN & (0x1UL << rr_register)); -} - - -/** - * @brief Function for setting a specific reload request register. - * - * @param[in] rr_register Reload request register to set. - */ -__STATIC_INLINE void nrf_wdt_reload_request_set(nrf_wdt_rr_register_t rr_register) -{ - NRF_WDT->RR[rr_register] = NRF_WDT_RR_VALUE; -} - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/arm_startup_nrf52.s b/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/arm_startup_nrf52.s deleted file mode 100644 index 37075dd854..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/arm_startup_nrf52.s +++ /dev/null @@ -1,369 +0,0 @@ -; Copyright (c) 2009-2018 ARM Limited. All rights reserved. -; -; SPDX-License-Identifier: Apache-2.0 -; -; Licensed under the Apache License, Version 2.0 (the License); you may -; not use this file except in compliance with the License. -; You may obtain a copy of the License at -; -; www.apache.org/licenses/LICENSE-2.0 -; -; Unless required by applicable law or agreed to in writing, software -; distributed under the License is distributed on an AS IS BASIS, WITHOUT -; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; See the License for the specific language governing permissions and -; limitations under the License. -; -; NOTICE: This file has been modified by Nordic Semiconductor ASA. - - IF :DEF: __STARTUP_CONFIG -#include "startup_config.h" -#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT -#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 -#endif - ENDIF - - IF :DEF: __STARTUP_CONFIG -Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE - ELIF :DEF: __STACK_SIZE -Stack_Size EQU __STACK_SIZE - ELSE -Stack_Size EQU 8192 - ENDIF - - IF :DEF: __STARTUP_CONFIG -Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT - ELSE -Stack_Align EQU 3 - ENDIF - - AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align -Stack_Mem SPACE Stack_Size -__initial_sp - - IF :DEF: __STARTUP_CONFIG -Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE - ELIF :DEF: __HEAP_SIZE -Heap_Size EQU __HEAP_SIZE - ELSE -Heap_Size EQU 8192 - ENDIF - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler - DCD NMI_Handler - DCD HardFault_Handler - DCD MemoryManagement_Handler - DCD BusFault_Handler - DCD UsageFault_Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 ; Reserved - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD POWER_CLOCK_IRQHandler - DCD RADIO_IRQHandler - DCD UARTE0_UART0_IRQHandler - DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler - DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler - DCD NFCT_IRQHandler - DCD GPIOTE_IRQHandler - DCD SAADC_IRQHandler - DCD TIMER0_IRQHandler - DCD TIMER1_IRQHandler - DCD TIMER2_IRQHandler - DCD RTC0_IRQHandler - DCD TEMP_IRQHandler - DCD RNG_IRQHandler - DCD ECB_IRQHandler - DCD CCM_AAR_IRQHandler - DCD WDT_IRQHandler - DCD RTC1_IRQHandler - DCD QDEC_IRQHandler - DCD COMP_LPCOMP_IRQHandler - DCD SWI0_EGU0_IRQHandler - DCD SWI1_EGU1_IRQHandler - DCD SWI2_EGU2_IRQHandler - DCD SWI3_EGU3_IRQHandler - DCD SWI4_EGU4_IRQHandler - DCD SWI5_EGU5_IRQHandler - DCD TIMER3_IRQHandler - DCD TIMER4_IRQHandler - DCD PWM0_IRQHandler - DCD PDM_IRQHandler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD MWU_IRQHandler - DCD PWM1_IRQHandler - DCD PWM2_IRQHandler - DCD SPIM2_SPIS2_SPI2_IRQHandler - DCD RTC2_IRQHandler - DCD I2S_IRQHandler - DCD FPU_IRQHandler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset Handler - - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemoryManagement_Handler\ - PROC - EXPORT MemoryManagement_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT POWER_CLOCK_IRQHandler [WEAK] - EXPORT RADIO_IRQHandler [WEAK] - EXPORT UARTE0_UART0_IRQHandler [WEAK] - EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler [WEAK] - EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler [WEAK] - EXPORT NFCT_IRQHandler [WEAK] - EXPORT GPIOTE_IRQHandler [WEAK] - EXPORT SAADC_IRQHandler [WEAK] - EXPORT TIMER0_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT RTC0_IRQHandler [WEAK] - EXPORT TEMP_IRQHandler [WEAK] - EXPORT RNG_IRQHandler [WEAK] - EXPORT ECB_IRQHandler [WEAK] - EXPORT CCM_AAR_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT RTC1_IRQHandler [WEAK] - EXPORT QDEC_IRQHandler [WEAK] - EXPORT COMP_LPCOMP_IRQHandler [WEAK] - EXPORT SWI0_EGU0_IRQHandler [WEAK] - EXPORT SWI1_EGU1_IRQHandler [WEAK] - EXPORT SWI2_EGU2_IRQHandler [WEAK] - EXPORT SWI3_EGU3_IRQHandler [WEAK] - EXPORT SWI4_EGU4_IRQHandler [WEAK] - EXPORT SWI5_EGU5_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT TIMER4_IRQHandler [WEAK] - EXPORT PWM0_IRQHandler [WEAK] - EXPORT PDM_IRQHandler [WEAK] - EXPORT MWU_IRQHandler [WEAK] - EXPORT PWM1_IRQHandler [WEAK] - EXPORT PWM2_IRQHandler [WEAK] - EXPORT SPIM2_SPIS2_SPI2_IRQHandler [WEAK] - EXPORT RTC2_IRQHandler [WEAK] - EXPORT I2S_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] -POWER_CLOCK_IRQHandler -RADIO_IRQHandler -UARTE0_UART0_IRQHandler -SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler -SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler -NFCT_IRQHandler -GPIOTE_IRQHandler -SAADC_IRQHandler -TIMER0_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -RTC0_IRQHandler -TEMP_IRQHandler -RNG_IRQHandler -ECB_IRQHandler -CCM_AAR_IRQHandler -WDT_IRQHandler -RTC1_IRQHandler -QDEC_IRQHandler -COMP_LPCOMP_IRQHandler -SWI0_EGU0_IRQHandler -SWI1_EGU1_IRQHandler -SWI2_EGU2_IRQHandler -SWI3_EGU3_IRQHandler -SWI4_EGU4_IRQHandler -SWI5_EGU5_IRQHandler -TIMER3_IRQHandler -TIMER4_IRQHandler -PWM0_IRQHandler -PDM_IRQHandler -MWU_IRQHandler -PWM1_IRQHandler -PWM2_IRQHandler -SPIM2_SPIS2_SPI2_IRQHandler -RTC2_IRQHandler -I2S_IRQHandler -FPU_IRQHandler - B . - ENDP - ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - - LDR R0, = Heap_Mem - LDR R1, = (Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - END diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/arm_startup_nrf52840.s b/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/arm_startup_nrf52840.s deleted file mode 100644 index 3649aa824e..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/arm_startup_nrf52840.s +++ /dev/null @@ -1,381 +0,0 @@ -; Copyright (c) 2009-2018 ARM Limited. All rights reserved. -; -; SPDX-License-Identifier: Apache-2.0 -; -; Licensed under the Apache License, Version 2.0 (the License); you may -; not use this file except in compliance with the License. -; You may obtain a copy of the License at -; -; www.apache.org/licenses/LICENSE-2.0 -; -; Unless required by applicable law or agreed to in writing, software -; distributed under the License is distributed on an AS IS BASIS, WITHOUT -; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; See the License for the specific language governing permissions and -; limitations under the License. -; -; NOTICE: This file has been modified by Nordic Semiconductor ASA. - - IF :DEF: __STARTUP_CONFIG -#include "startup_config.h" -#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT -#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 -#endif - ENDIF - - IF :DEF: __STARTUP_CONFIG -Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE - ELIF :DEF: __STACK_SIZE -Stack_Size EQU __STACK_SIZE - ELSE -Stack_Size EQU 8192 - ENDIF - - IF :DEF: __STARTUP_CONFIG -Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT - ELSE -Stack_Align EQU 3 - ENDIF - - AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align -Stack_Mem SPACE Stack_Size -__initial_sp - - IF :DEF: __STARTUP_CONFIG -Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE - ELIF :DEF: __HEAP_SIZE -Heap_Size EQU __HEAP_SIZE - ELSE -Heap_Size EQU 8192 - ENDIF - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler - DCD NMI_Handler - DCD HardFault_Handler - DCD MemoryManagement_Handler - DCD BusFault_Handler - DCD UsageFault_Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 ; Reserved - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD POWER_CLOCK_IRQHandler - DCD RADIO_IRQHandler - DCD UARTE0_UART0_IRQHandler - DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler - DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler - DCD NFCT_IRQHandler - DCD GPIOTE_IRQHandler - DCD SAADC_IRQHandler - DCD TIMER0_IRQHandler - DCD TIMER1_IRQHandler - DCD TIMER2_IRQHandler - DCD RTC0_IRQHandler - DCD TEMP_IRQHandler - DCD RNG_IRQHandler - DCD ECB_IRQHandler - DCD CCM_AAR_IRQHandler - DCD WDT_IRQHandler - DCD RTC1_IRQHandler - DCD QDEC_IRQHandler - DCD COMP_LPCOMP_IRQHandler - DCD SWI0_EGU0_IRQHandler - DCD SWI1_EGU1_IRQHandler - DCD SWI2_EGU2_IRQHandler - DCD SWI3_EGU3_IRQHandler - DCD SWI4_EGU4_IRQHandler - DCD SWI5_EGU5_IRQHandler - DCD TIMER3_IRQHandler - DCD TIMER4_IRQHandler - DCD PWM0_IRQHandler - DCD PDM_IRQHandler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD MWU_IRQHandler - DCD PWM1_IRQHandler - DCD PWM2_IRQHandler - DCD SPIM2_SPIS2_SPI2_IRQHandler - DCD RTC2_IRQHandler - DCD I2S_IRQHandler - DCD FPU_IRQHandler - DCD USBD_IRQHandler - DCD UARTE1_IRQHandler - DCD QSPI_IRQHandler - DCD CRYPTOCELL_IRQHandler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PWM3_IRQHandler - DCD 0 ; Reserved - DCD SPIM3_IRQHandler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset Handler - - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemoryManagement_Handler\ - PROC - EXPORT MemoryManagement_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT POWER_CLOCK_IRQHandler [WEAK] - EXPORT RADIO_IRQHandler [WEAK] - EXPORT UARTE0_UART0_IRQHandler [WEAK] - EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler [WEAK] - EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler [WEAK] - EXPORT NFCT_IRQHandler [WEAK] - EXPORT GPIOTE_IRQHandler [WEAK] - EXPORT SAADC_IRQHandler [WEAK] - EXPORT TIMER0_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT RTC0_IRQHandler [WEAK] - EXPORT TEMP_IRQHandler [WEAK] - EXPORT RNG_IRQHandler [WEAK] - EXPORT ECB_IRQHandler [WEAK] - EXPORT CCM_AAR_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT RTC1_IRQHandler [WEAK] - EXPORT QDEC_IRQHandler [WEAK] - EXPORT COMP_LPCOMP_IRQHandler [WEAK] - EXPORT SWI0_EGU0_IRQHandler [WEAK] - EXPORT SWI1_EGU1_IRQHandler [WEAK] - EXPORT SWI2_EGU2_IRQHandler [WEAK] - EXPORT SWI3_EGU3_IRQHandler [WEAK] - EXPORT SWI4_EGU4_IRQHandler [WEAK] - EXPORT SWI5_EGU5_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT TIMER4_IRQHandler [WEAK] - EXPORT PWM0_IRQHandler [WEAK] - EXPORT PDM_IRQHandler [WEAK] - EXPORT MWU_IRQHandler [WEAK] - EXPORT PWM1_IRQHandler [WEAK] - EXPORT PWM2_IRQHandler [WEAK] - EXPORT SPIM2_SPIS2_SPI2_IRQHandler [WEAK] - EXPORT RTC2_IRQHandler [WEAK] - EXPORT I2S_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT USBD_IRQHandler [WEAK] - EXPORT UARTE1_IRQHandler [WEAK] - EXPORT QSPI_IRQHandler [WEAK] - EXPORT CRYPTOCELL_IRQHandler [WEAK] - EXPORT PWM3_IRQHandler [WEAK] - EXPORT SPIM3_IRQHandler [WEAK] -POWER_CLOCK_IRQHandler -RADIO_IRQHandler -UARTE0_UART0_IRQHandler -SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler -SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler -NFCT_IRQHandler -GPIOTE_IRQHandler -SAADC_IRQHandler -TIMER0_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -RTC0_IRQHandler -TEMP_IRQHandler -RNG_IRQHandler -ECB_IRQHandler -CCM_AAR_IRQHandler -WDT_IRQHandler -RTC1_IRQHandler -QDEC_IRQHandler -COMP_LPCOMP_IRQHandler -SWI0_EGU0_IRQHandler -SWI1_EGU1_IRQHandler -SWI2_EGU2_IRQHandler -SWI3_EGU3_IRQHandler -SWI4_EGU4_IRQHandler -SWI5_EGU5_IRQHandler -TIMER3_IRQHandler -TIMER4_IRQHandler -PWM0_IRQHandler -PDM_IRQHandler -MWU_IRQHandler -PWM1_IRQHandler -PWM2_IRQHandler -SPIM2_SPIS2_SPI2_IRQHandler -RTC2_IRQHandler -I2S_IRQHandler -FPU_IRQHandler -USBD_IRQHandler -UARTE1_IRQHandler -QSPI_IRQHandler -CRYPTOCELL_IRQHandler -PWM3_IRQHandler -SPIM3_IRQHandler - B . - ENDP - ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - - LDR R0, = Heap_Mem - LDR R1, = (Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - END diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/gcc_startup_nrf52.S b/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/gcc_startup_nrf52.S deleted file mode 100644 index 73091fd471..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/gcc_startup_nrf52.S +++ /dev/null @@ -1,404 +0,0 @@ -/* - -Copyright (c) 2009-2018 ARM Limited. All rights reserved. - - SPDX-License-Identifier: Apache-2.0 - -Licensed under the Apache License, Version 2.0 (the License); you may -not use this file except in compliance with the License. -You may obtain a copy of the License at - - www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an AS IS BASIS, WITHOUT -WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -NOTICE: This file has been modified by Nordic Semiconductor ASA. - -*/ - - .syntax unified - .arch armv7e-m - -#ifdef __STARTUP_CONFIG -#include "startup_config.h" -#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT -#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 -#endif -#endif - - .section .stack -#if defined(__STARTUP_CONFIG) - .align __STARTUP_CONFIG_STACK_ALIGNEMENT - .equ Stack_Size, __STARTUP_CONFIG_STACK_SIZE -#elif defined(__STACK_SIZE) - .align 3 - .equ Stack_Size, __STACK_SIZE -#else - .align 3 - .equ Stack_Size, 8192 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#if defined(__STARTUP_CONFIG) - .equ Heap_Size, __STARTUP_CONFIG_HEAP_SIZE -#elif defined(__HEAP_SIZE) - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 8192 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .if Heap_Size - .space Heap_Size - .endif - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .isr_vector - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler - .long NMI_Handler - .long HardFault_Handler - .long MemoryManagement_Handler - .long BusFault_Handler - .long UsageFault_Handler - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long SVC_Handler - .long DebugMon_Handler - .long 0 /*Reserved */ - .long PendSV_Handler - .long SysTick_Handler - - /* External Interrupts */ - .long POWER_CLOCK_IRQHandler - .long RADIO_IRQHandler - .long UARTE0_UART0_IRQHandler - .long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler - .long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler - .long NFCT_IRQHandler - .long GPIOTE_IRQHandler - .long SAADC_IRQHandler - .long TIMER0_IRQHandler - .long TIMER1_IRQHandler - .long TIMER2_IRQHandler - .long RTC0_IRQHandler - .long TEMP_IRQHandler - .long RNG_IRQHandler - .long ECB_IRQHandler - .long CCM_AAR_IRQHandler - .long WDT_IRQHandler - .long RTC1_IRQHandler - .long QDEC_IRQHandler - .long COMP_LPCOMP_IRQHandler - .long SWI0_EGU0_IRQHandler - .long SWI1_EGU1_IRQHandler - .long SWI2_EGU2_IRQHandler - .long SWI3_EGU3_IRQHandler - .long SWI4_EGU4_IRQHandler - .long SWI5_EGU5_IRQHandler - .long TIMER3_IRQHandler - .long TIMER4_IRQHandler - .long PWM0_IRQHandler - .long PDM_IRQHandler - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long MWU_IRQHandler - .long PWM1_IRQHandler - .long PWM2_IRQHandler - .long SPIM2_SPIS2_SPI2_IRQHandler - .long RTC2_IRQHandler - .long I2S_IRQHandler - .long FPU_IRQHandler - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - - .size __isr_vector, . - __isr_vector - -/* Reset Handler */ - - - .text - .thumb - .thumb_func - .align 1 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - - -/* Loop to copy data from read only memory to RAM. - * The ranges of copy from/to are specified by following symbols: - * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to. - * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INTERT AFTER command. - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__bss_start__ - - subs r3, r2 - ble .L_loop1_done - -.L_loop1: - subs r3, #4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt .L_loop1 - -.L_loop1_done: - -/* This part of work usually is done in C library startup code. Otherwise, - * define __STARTUP_CLEAR_BSS to enable it in this startup. This section - * clears the RAM where BSS data is located. - * - * The BSS section is specified by following symbols - * __bss_start__: start of the BSS section. - * __bss_end__: end of the BSS section. - * - * All addresses must be aligned to 4 bytes boundary. - */ -#ifdef __STARTUP_CLEAR_BSS - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 - - subs r2, r1 - ble .L_loop3_done - -.L_loop3: - subs r2, #4 - str r0, [r1, r2] - bgt .L_loop3 - -.L_loop3_done: -#endif /* __STARTUP_CLEAR_BSS */ - -/* Execute SystemInit function. */ - bl SystemInit - -/* Call _start function provided by libraries. - * If those libraries are not accessible, define __START as your entry point. - */ -#ifndef __START -#define __START _start -#endif - bl __START - - .pool - .size Reset_Handler,.-Reset_Handler - - .section ".text" - - -/* Dummy Exception Handlers (infinite loops which can be modified) */ - - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - b . - .size NMI_Handler, . - NMI_Handler - - - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - b . - .size HardFault_Handler, . - HardFault_Handler - - - .weak MemoryManagement_Handler - .type MemoryManagement_Handler, %function -MemoryManagement_Handler: - b . - .size MemoryManagement_Handler, . - MemoryManagement_Handler - - - .weak BusFault_Handler - .type BusFault_Handler, %function -BusFault_Handler: - b . - .size BusFault_Handler, . - BusFault_Handler - - - .weak UsageFault_Handler - .type UsageFault_Handler, %function -UsageFault_Handler: - b . - .size UsageFault_Handler, . - UsageFault_Handler - - - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - b . - .size SVC_Handler, . - SVC_Handler - - - .weak DebugMon_Handler - .type DebugMon_Handler, %function -DebugMon_Handler: - b . - .size DebugMon_Handler, . - DebugMon_Handler - - - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - b . - .size PendSV_Handler, . - PendSV_Handler - - - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - b . - .size SysTick_Handler, . - SysTick_Handler - - -/* IRQ Handlers */ - - .globl Default_Handler - .type Default_Handler, %function -Default_Handler: - b . - .size Default_Handler, . - Default_Handler - - .macro IRQ handler - .weak \handler - .set \handler, Default_Handler - .endm - - IRQ POWER_CLOCK_IRQHandler - IRQ RADIO_IRQHandler - IRQ UARTE0_UART0_IRQHandler - IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler - IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler - IRQ NFCT_IRQHandler - IRQ GPIOTE_IRQHandler - IRQ SAADC_IRQHandler - IRQ TIMER0_IRQHandler - IRQ TIMER1_IRQHandler - IRQ TIMER2_IRQHandler - IRQ RTC0_IRQHandler - IRQ TEMP_IRQHandler - IRQ RNG_IRQHandler - IRQ ECB_IRQHandler - IRQ CCM_AAR_IRQHandler - IRQ WDT_IRQHandler - IRQ RTC1_IRQHandler - IRQ QDEC_IRQHandler - IRQ COMP_LPCOMP_IRQHandler - IRQ SWI0_EGU0_IRQHandler - IRQ SWI1_EGU1_IRQHandler - IRQ SWI2_EGU2_IRQHandler - IRQ SWI3_EGU3_IRQHandler - IRQ SWI4_EGU4_IRQHandler - IRQ SWI5_EGU5_IRQHandler - IRQ TIMER3_IRQHandler - IRQ TIMER4_IRQHandler - IRQ PWM0_IRQHandler - IRQ PDM_IRQHandler - IRQ MWU_IRQHandler - IRQ PWM1_IRQHandler - IRQ PWM2_IRQHandler - IRQ SPIM2_SPIS2_SPI2_IRQHandler - IRQ RTC2_IRQHandler - IRQ I2S_IRQHandler - IRQ FPU_IRQHandler - - .end diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/gcc_startup_nrf52840.S b/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/gcc_startup_nrf52840.S deleted file mode 100644 index eb510396fb..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/gcc_startup_nrf52840.S +++ /dev/null @@ -1,410 +0,0 @@ -/* - -Copyright (c) 2009-2018 ARM Limited. All rights reserved. - - SPDX-License-Identifier: Apache-2.0 - -Licensed under the Apache License, Version 2.0 (the License); you may -not use this file except in compliance with the License. -You may obtain a copy of the License at - - www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an AS IS BASIS, WITHOUT -WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -NOTICE: This file has been modified by Nordic Semiconductor ASA. - -*/ - - .syntax unified - .arch armv7e-m - -#ifdef __STARTUP_CONFIG -#include "startup_config.h" -#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT -#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 -#endif -#endif - - .section .stack -#if defined(__STARTUP_CONFIG) - .align __STARTUP_CONFIG_STACK_ALIGNEMENT - .equ Stack_Size, __STARTUP_CONFIG_STACK_SIZE -#elif defined(__STACK_SIZE) - .align 3 - .equ Stack_Size, __STACK_SIZE -#else - .align 3 - .equ Stack_Size, 8192 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#if defined(__STARTUP_CONFIG) - .equ Heap_Size, __STARTUP_CONFIG_HEAP_SIZE -#elif defined(__HEAP_SIZE) - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 8192 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .if Heap_Size - .space Heap_Size - .endif - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .isr_vector - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler - .long NMI_Handler - .long HardFault_Handler - .long MemoryManagement_Handler - .long BusFault_Handler - .long UsageFault_Handler - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long SVC_Handler - .long DebugMon_Handler - .long 0 /*Reserved */ - .long PendSV_Handler - .long SysTick_Handler - - /* External Interrupts */ - .long POWER_CLOCK_IRQHandler - .long RADIO_IRQHandler - .long UARTE0_UART0_IRQHandler - .long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler - .long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler - .long NFCT_IRQHandler - .long GPIOTE_IRQHandler - .long SAADC_IRQHandler - .long TIMER0_IRQHandler - .long TIMER1_IRQHandler - .long TIMER2_IRQHandler - .long RTC0_IRQHandler - .long TEMP_IRQHandler - .long RNG_IRQHandler - .long ECB_IRQHandler - .long CCM_AAR_IRQHandler - .long WDT_IRQHandler - .long RTC1_IRQHandler - .long QDEC_IRQHandler - .long COMP_LPCOMP_IRQHandler - .long SWI0_EGU0_IRQHandler - .long SWI1_EGU1_IRQHandler - .long SWI2_EGU2_IRQHandler - .long SWI3_EGU3_IRQHandler - .long SWI4_EGU4_IRQHandler - .long SWI5_EGU5_IRQHandler - .long TIMER3_IRQHandler - .long TIMER4_IRQHandler - .long PWM0_IRQHandler - .long PDM_IRQHandler - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long MWU_IRQHandler - .long PWM1_IRQHandler - .long PWM2_IRQHandler - .long SPIM2_SPIS2_SPI2_IRQHandler - .long RTC2_IRQHandler - .long I2S_IRQHandler - .long FPU_IRQHandler - .long USBD_IRQHandler - .long UARTE1_IRQHandler - .long QSPI_IRQHandler - .long CRYPTOCELL_IRQHandler - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long PWM3_IRQHandler - .long 0 /*Reserved */ - .long SPIM3_IRQHandler - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - - .size __isr_vector, . - __isr_vector - -/* Reset Handler */ - - - .text - .thumb - .thumb_func - .align 1 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - - -/* Loop to copy data from read only memory to RAM. - * The ranges of copy from/to are specified by following symbols: - * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to. - * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INTERT AFTER command. - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__bss_start__ - - subs r3, r2 - ble .L_loop1_done - -.L_loop1: - subs r3, #4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt .L_loop1 - -.L_loop1_done: - -/* This part of work usually is done in C library startup code. Otherwise, - * define __STARTUP_CLEAR_BSS to enable it in this startup. This section - * clears the RAM where BSS data is located. - * - * The BSS section is specified by following symbols - * __bss_start__: start of the BSS section. - * __bss_end__: end of the BSS section. - * - * All addresses must be aligned to 4 bytes boundary. - */ -#ifdef __STARTUP_CLEAR_BSS - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 - - subs r2, r1 - ble .L_loop3_done - -.L_loop3: - subs r2, #4 - str r0, [r1, r2] - bgt .L_loop3 - -.L_loop3_done: -#endif /* __STARTUP_CLEAR_BSS */ - -/* Execute SystemInit function. */ - bl SystemInit - -/* Call _start function provided by libraries. - * If those libraries are not accessible, define __START as your entry point. - */ -#ifndef __START -#define __START _start -#endif - bl __START - - .pool - .size Reset_Handler,.-Reset_Handler - - .section ".text" - - -/* Dummy Exception Handlers (infinite loops which can be modified) */ - - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - b . - .size NMI_Handler, . - NMI_Handler - - - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - b . - .size HardFault_Handler, . - HardFault_Handler - - - .weak MemoryManagement_Handler - .type MemoryManagement_Handler, %function -MemoryManagement_Handler: - b . - .size MemoryManagement_Handler, . - MemoryManagement_Handler - - - .weak BusFault_Handler - .type BusFault_Handler, %function -BusFault_Handler: - b . - .size BusFault_Handler, . - BusFault_Handler - - - .weak UsageFault_Handler - .type UsageFault_Handler, %function -UsageFault_Handler: - b . - .size UsageFault_Handler, . - UsageFault_Handler - - - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - b . - .size SVC_Handler, . - SVC_Handler - - - .weak DebugMon_Handler - .type DebugMon_Handler, %function -DebugMon_Handler: - b . - .size DebugMon_Handler, . - DebugMon_Handler - - - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - b . - .size PendSV_Handler, . - PendSV_Handler - - - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - b . - .size SysTick_Handler, . - SysTick_Handler - - -/* IRQ Handlers */ - - .globl Default_Handler - .type Default_Handler, %function -Default_Handler: - b . - .size Default_Handler, . - Default_Handler - - .macro IRQ handler - .weak \handler - .set \handler, Default_Handler - .endm - - IRQ POWER_CLOCK_IRQHandler - IRQ RADIO_IRQHandler - IRQ UARTE0_UART0_IRQHandler - IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler - IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler - IRQ NFCT_IRQHandler - IRQ GPIOTE_IRQHandler - IRQ SAADC_IRQHandler - IRQ TIMER0_IRQHandler - IRQ TIMER1_IRQHandler - IRQ TIMER2_IRQHandler - IRQ RTC0_IRQHandler - IRQ TEMP_IRQHandler - IRQ RNG_IRQHandler - IRQ ECB_IRQHandler - IRQ CCM_AAR_IRQHandler - IRQ WDT_IRQHandler - IRQ RTC1_IRQHandler - IRQ QDEC_IRQHandler - IRQ COMP_LPCOMP_IRQHandler - IRQ SWI0_EGU0_IRQHandler - IRQ SWI1_EGU1_IRQHandler - IRQ SWI2_EGU2_IRQHandler - IRQ SWI3_EGU3_IRQHandler - IRQ SWI4_EGU4_IRQHandler - IRQ SWI5_EGU5_IRQHandler - IRQ TIMER3_IRQHandler - IRQ TIMER4_IRQHandler - IRQ PWM0_IRQHandler - IRQ PDM_IRQHandler - IRQ MWU_IRQHandler - IRQ PWM1_IRQHandler - IRQ PWM2_IRQHandler - IRQ SPIM2_SPIS2_SPI2_IRQHandler - IRQ RTC2_IRQHandler - IRQ I2S_IRQHandler - IRQ FPU_IRQHandler - IRQ USBD_IRQHandler - IRQ UARTE1_IRQHandler - IRQ QSPI_IRQHandler - IRQ CRYPTOCELL_IRQHandler - IRQ PWM3_IRQHandler - IRQ SPIM3_IRQHandler - - .end diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/iar_startup_nrf52.s b/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/iar_startup_nrf52.s deleted file mode 100644 index 9e6376c8ff..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/iar_startup_nrf52.s +++ /dev/null @@ -1,457 +0,0 @@ -; Copyright (c) 2009-2018 ARM Limited. All rights reserved. -; -; SPDX-License-Identifier: Apache-2.0 -; -; Licensed under the Apache License, Version 2.0 (the License); you may -; not use this file except in compliance with the License. -; You may obtain a copy of the License at -; -; www.apache.org/licenses/LICENSE-2.0 -; -; Unless required by applicable law or agreed to in writing, software -; distributed under the License is distributed on an AS IS BASIS, WITHOUT -; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; See the License for the specific language governing permissions and -; limitations under the License. -; -; NOTICE: This file has been modified by Nordic Semiconductor ASA. - -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. - - MODULE ?cstartup - -#if defined(__STARTUP_CONFIG) - - #include "startup_config.h" - - #ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT - #define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 - #endif - - SECTION CSTACK:DATA:NOROOT(__STARTUP_CONFIG_STACK_ALIGNEMENT) - DS8 __STARTUP_CONFIG_STACK_SIZE - - SECTION HEAP:DATA:NOROOT(3) - DS8 __STARTUP_CONFIG_HEAP_SIZE - -#else - - ;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW. - ;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW. - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - -#endif - - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - DCD NMI_Handler - DCD HardFault_Handler - DCD MemoryManagement_Handler - DCD BusFault_Handler - DCD UsageFault_Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 ; Reserved - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD POWER_CLOCK_IRQHandler - DCD RADIO_IRQHandler - DCD UARTE0_UART0_IRQHandler - DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler - DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler - DCD NFCT_IRQHandler - DCD GPIOTE_IRQHandler - DCD SAADC_IRQHandler - DCD TIMER0_IRQHandler - DCD TIMER1_IRQHandler - DCD TIMER2_IRQHandler - DCD RTC0_IRQHandler - DCD TEMP_IRQHandler - DCD RNG_IRQHandler - DCD ECB_IRQHandler - DCD CCM_AAR_IRQHandler - DCD WDT_IRQHandler - DCD RTC1_IRQHandler - DCD QDEC_IRQHandler - DCD COMP_LPCOMP_IRQHandler - DCD SWI0_EGU0_IRQHandler - DCD SWI1_EGU1_IRQHandler - DCD SWI2_EGU2_IRQHandler - DCD SWI3_EGU3_IRQHandler - DCD SWI4_EGU4_IRQHandler - DCD SWI5_EGU5_IRQHandler - DCD TIMER3_IRQHandler - DCD TIMER4_IRQHandler - DCD PWM0_IRQHandler - DCD PDM_IRQHandler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD MWU_IRQHandler - DCD PWM1_IRQHandler - DCD PWM2_IRQHandler - DCD SPIM2_SPIS2_SPI2_IRQHandler - DCD RTC2_IRQHandler - DCD I2S_IRQHandler - DCD FPU_IRQHandler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - -__Vectors_End -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -; Default handlers. - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - ; Dummy exception handlers - - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK MemoryManagement_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemoryManagement_Handler - B . - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B . - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - - ; Dummy interrupt handlers - - PUBWEAK POWER_CLOCK_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -POWER_CLOCK_IRQHandler - B . - - PUBWEAK RADIO_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RADIO_IRQHandler - B . - - PUBWEAK UARTE0_UART0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UARTE0_UART0_IRQHandler - B . - - PUBWEAK SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler - B . - - PUBWEAK SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler - B . - - PUBWEAK NFCT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NFCT_IRQHandler - B . - - PUBWEAK GPIOTE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIOTE_IRQHandler - B . - - PUBWEAK SAADC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SAADC_IRQHandler - B . - - PUBWEAK TIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER0_IRQHandler - B . - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER1_IRQHandler - B . - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER2_IRQHandler - B . - - PUBWEAK RTC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC0_IRQHandler - B . - - PUBWEAK TEMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TEMP_IRQHandler - B . - - PUBWEAK RNG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RNG_IRQHandler - B . - - PUBWEAK ECB_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ECB_IRQHandler - B . - - PUBWEAK CCM_AAR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CCM_AAR_IRQHandler - B . - - PUBWEAK WDT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WDT_IRQHandler - B . - - PUBWEAK RTC1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC1_IRQHandler - B . - - PUBWEAK QDEC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -QDEC_IRQHandler - B . - - PUBWEAK COMP_LPCOMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -COMP_LPCOMP_IRQHandler - B . - - PUBWEAK SWI0_EGU0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SWI0_EGU0_IRQHandler - B . - - PUBWEAK SWI1_EGU1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SWI1_EGU1_IRQHandler - B . - - PUBWEAK SWI2_EGU2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SWI2_EGU2_IRQHandler - B . - - PUBWEAK SWI3_EGU3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SWI3_EGU3_IRQHandler - B . - - PUBWEAK SWI4_EGU4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SWI4_EGU4_IRQHandler - B . - - PUBWEAK SWI5_EGU5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SWI5_EGU5_IRQHandler - B . - - PUBWEAK TIMER3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER3_IRQHandler - B . - - PUBWEAK TIMER4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER4_IRQHandler - B . - - PUBWEAK PWM0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM0_IRQHandler - B . - - PUBWEAK PDM_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PDM_IRQHandler - B . - - PUBWEAK MWU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MWU_IRQHandler - B . - - PUBWEAK PWM1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM1_IRQHandler - B . - - PUBWEAK PWM2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM2_IRQHandler - B . - - PUBWEAK SPIM2_SPIS2_SPI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPIM2_SPIS2_SPI2_IRQHandler - B . - - PUBWEAK RTC2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC2_IRQHandler - B . - - PUBWEAK I2S_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2S_IRQHandler - B . - - PUBWEAK FPU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FPU_IRQHandler - B . - - - END - - diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/iar_startup_nrf52840.s b/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/iar_startup_nrf52840.s deleted file mode 100644 index 5f9e0a5000..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/iar_startup_nrf52840.s +++ /dev/null @@ -1,487 +0,0 @@ -; Copyright (c) 2009-2018 ARM Limited. All rights reserved. -; -; SPDX-License-Identifier: Apache-2.0 -; -; Licensed under the Apache License, Version 2.0 (the License); you may -; not use this file except in compliance with the License. -; You may obtain a copy of the License at -; -; www.apache.org/licenses/LICENSE-2.0 -; -; Unless required by applicable law or agreed to in writing, software -; distributed under the License is distributed on an AS IS BASIS, WITHOUT -; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; See the License for the specific language governing permissions and -; limitations under the License. -; -; NOTICE: This file has been modified by Nordic Semiconductor ASA. - -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. - - MODULE ?cstartup - -#if defined(__STARTUP_CONFIG) - - #include "startup_config.h" - - #ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT - #define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 - #endif - - SECTION CSTACK:DATA:NOROOT(__STARTUP_CONFIG_STACK_ALIGNEMENT) - DS8 __STARTUP_CONFIG_STACK_SIZE - - SECTION HEAP:DATA:NOROOT(3) - DS8 __STARTUP_CONFIG_HEAP_SIZE - -#else - - ;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW. - ;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW. - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - -#endif - - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - DCD NMI_Handler - DCD HardFault_Handler - DCD MemoryManagement_Handler - DCD BusFault_Handler - DCD UsageFault_Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 ; Reserved - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD POWER_CLOCK_IRQHandler - DCD RADIO_IRQHandler - DCD UARTE0_UART0_IRQHandler - DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler - DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler - DCD NFCT_IRQHandler - DCD GPIOTE_IRQHandler - DCD SAADC_IRQHandler - DCD TIMER0_IRQHandler - DCD TIMER1_IRQHandler - DCD TIMER2_IRQHandler - DCD RTC0_IRQHandler - DCD TEMP_IRQHandler - DCD RNG_IRQHandler - DCD ECB_IRQHandler - DCD CCM_AAR_IRQHandler - DCD WDT_IRQHandler - DCD RTC1_IRQHandler - DCD QDEC_IRQHandler - DCD COMP_LPCOMP_IRQHandler - DCD SWI0_EGU0_IRQHandler - DCD SWI1_EGU1_IRQHandler - DCD SWI2_EGU2_IRQHandler - DCD SWI3_EGU3_IRQHandler - DCD SWI4_EGU4_IRQHandler - DCD SWI5_EGU5_IRQHandler - DCD TIMER3_IRQHandler - DCD TIMER4_IRQHandler - DCD PWM0_IRQHandler - DCD PDM_IRQHandler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD MWU_IRQHandler - DCD PWM1_IRQHandler - DCD PWM2_IRQHandler - DCD SPIM2_SPIS2_SPI2_IRQHandler - DCD RTC2_IRQHandler - DCD I2S_IRQHandler - DCD FPU_IRQHandler - DCD USBD_IRQHandler - DCD UARTE1_IRQHandler - DCD QSPI_IRQHandler - DCD CRYPTOCELL_IRQHandler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PWM3_IRQHandler - DCD 0 ; Reserved - DCD SPIM3_IRQHandler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - -__Vectors_End -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -; Default handlers. - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - ; Dummy exception handlers - - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK MemoryManagement_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemoryManagement_Handler - B . - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B . - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - - ; Dummy interrupt handlers - - PUBWEAK POWER_CLOCK_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -POWER_CLOCK_IRQHandler - B . - - PUBWEAK RADIO_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RADIO_IRQHandler - B . - - PUBWEAK UARTE0_UART0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UARTE0_UART0_IRQHandler - B . - - PUBWEAK SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler - B . - - PUBWEAK SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler - B . - - PUBWEAK NFCT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NFCT_IRQHandler - B . - - PUBWEAK GPIOTE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIOTE_IRQHandler - B . - - PUBWEAK SAADC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SAADC_IRQHandler - B . - - PUBWEAK TIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER0_IRQHandler - B . - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER1_IRQHandler - B . - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER2_IRQHandler - B . - - PUBWEAK RTC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC0_IRQHandler - B . - - PUBWEAK TEMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TEMP_IRQHandler - B . - - PUBWEAK RNG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RNG_IRQHandler - B . - - PUBWEAK ECB_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ECB_IRQHandler - B . - - PUBWEAK CCM_AAR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CCM_AAR_IRQHandler - B . - - PUBWEAK WDT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WDT_IRQHandler - B . - - PUBWEAK RTC1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC1_IRQHandler - B . - - PUBWEAK QDEC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -QDEC_IRQHandler - B . - - PUBWEAK COMP_LPCOMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -COMP_LPCOMP_IRQHandler - B . - - PUBWEAK SWI0_EGU0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SWI0_EGU0_IRQHandler - B . - - PUBWEAK SWI1_EGU1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SWI1_EGU1_IRQHandler - B . - - PUBWEAK SWI2_EGU2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SWI2_EGU2_IRQHandler - B . - - PUBWEAK SWI3_EGU3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SWI3_EGU3_IRQHandler - B . - - PUBWEAK SWI4_EGU4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SWI4_EGU4_IRQHandler - B . - - PUBWEAK SWI5_EGU5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SWI5_EGU5_IRQHandler - B . - - PUBWEAK TIMER3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER3_IRQHandler - B . - - PUBWEAK TIMER4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER4_IRQHandler - B . - - PUBWEAK PWM0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM0_IRQHandler - B . - - PUBWEAK PDM_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PDM_IRQHandler - B . - - PUBWEAK MWU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MWU_IRQHandler - B . - - PUBWEAK PWM1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM1_IRQHandler - B . - - PUBWEAK PWM2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM2_IRQHandler - B . - - PUBWEAK SPIM2_SPIS2_SPI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPIM2_SPIS2_SPI2_IRQHandler - B . - - PUBWEAK RTC2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC2_IRQHandler - B . - - PUBWEAK I2S_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2S_IRQHandler - B . - - PUBWEAK FPU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FPU_IRQHandler - B . - - PUBWEAK USBD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USBD_IRQHandler - B . - - PUBWEAK UARTE1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UARTE1_IRQHandler - B . - - PUBWEAK QSPI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -QSPI_IRQHandler - B . - - PUBWEAK CRYPTOCELL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CRYPTOCELL_IRQHandler - B . - - PUBWEAK PWM3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM3_IRQHandler - B . - - PUBWEAK SPIM3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPIM3_IRQHandler - B . - - - END - - diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nRFxxx.h b/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nRFxxx.h deleted file mode 100644 index b2b9f118ca..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nRFxxx.h +++ /dev/null @@ -1,21 +0,0 @@ -/***************************************************************************** - * SEGGER Microcontroller GmbH & Co. KG * - * Solutions for real time microcontroller applications * - ***************************************************************************** - * * - * (c) 2017 SEGGER Microcontroller GmbH & Co. KG * - * * - * Internet: www.segger.com Support: support@segger.com * - * * - *****************************************************************************/ - -#ifndef __nRFxxx_h -#define __nRFxxx_h - -#if defined(NRF51) || defined(NRF51) || defined(NRF51) || defined(NRF51) || defined(NRF51) || defined(NRF51) || defined(NRF51) || defined(NRF51) || defined(NRF52) || defined(NRF52832_XXAB) || defined(NRF52840_XXAA) - -#include "nrf.h" - -#endif - -#endif diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf.h b/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf.h deleted file mode 100644 index 23db792faf..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - -Copyright (c) 2010 - 2018, Nordic Semiconductor ASA - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - -2. Redistributions in binary form, except as embedded into a Nordic - Semiconductor ASA integrated circuit in a product or a software update for - such product, must reproduce the above copyright notice, this list of - conditions and the following disclaimer in the documentation and/or other - materials provided with the distribution. - -3. Neither the name of Nordic Semiconductor ASA nor the names of its - contributors may be used to endorse or promote products derived from this - software without specific prior written permission. - -4. This software, with or without modification, must only be used with a - Nordic Semiconductor ASA integrated circuit. - -5. Any software provided in binary form under this license must not be reverse - engineered, decompiled, modified and/or disassembled. - -THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS -OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*/ - -#ifndef NRF_H -#define NRF_H - -/* MDK version */ -#define MDK_MAJOR_VERSION 8 -#define MDK_MINOR_VERSION 16 -#define MDK_MICRO_VERSION 0 - -/* Redefine "old" too-generic name NRF52 to NRF52832_XXAA to keep backwards compatibility. */ -#if defined (NRF52) - #ifndef NRF52832_XXAA - #define NRF52832_XXAA - #endif -#endif - -/* Define NRF52_SERIES for common use in nRF52 series devices. Only if not previously defined. */ -#if defined (NRF52810_XXAA) || defined (NRF52832_XXAA) || defined (NRF52832_XXAB) || defined (NRF52840_XXAA) - #ifndef NRF52_SERIES - #define NRF52_SERIES - #endif -#endif - - -#if defined(_WIN32) - /* Do not include nrf specific files when building for PC host */ -#elif defined(__unix) - /* Do not include nrf specific files when building for PC host */ -#elif defined(__APPLE__) - /* Do not include nrf specific files when building for PC host */ -#else - - /* Device selection for device includes. */ - #if defined (NRF51) - #include "nrf51.h" - #include "nrf51_bitfields.h" - #include "nrf51_deprecated.h" - #elif defined (NRF52840_XXAA) - #include "nrf52840.h" - #include "nrf52840_bitfields.h" - #include "nrf51_to_nrf52840.h" - #include "nrf52_to_nrf52840.h" - #elif defined (NRF52832_XXAA) || defined (NRF52832_XXAB) - #include "nrf52.h" - #include "nrf52_bitfields.h" - #include "nrf51_to_nrf52.h" - #include "nrf52_name_change.h" - #elif defined (NRF52810_XXAA) - #include "nrf52810.h" - #include "nrf52810_bitfields.h" - #include "nrf51_to_nrf52810.h" - #include "nrf52_to_nrf52810.h" - #else - #error "Device must be defined. See nrf.h." - #endif /* NRF51, NRF52832_XXAA, NRF52832_XXAB, NRF52810_XXAA, NRF52840_XXAA */ - - #include "compiler_abstraction.h" - -#endif /* _WIN32 || __unix || __APPLE__ */ - -#endif /* NRF_H */ - diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf51.h b/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf51.h deleted file mode 100644 index 8e9baace16..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf51.h +++ /dev/null @@ -1,1202 +0,0 @@ - -/****************************************************************************************************//** - * @file nrf51.h - * - * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for - * nrf51 from Nordic Semiconductor. - * - * @version V522 - * @date 8. March 2018 - * - * @note Generated with SVDConv V2.81d - * from CMSIS SVD File 'nrf51.svd' Version 522, - * - * @par Copyright (c) 2010 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - *******************************************************************************************************/ - - - -/** @addtogroup Nordic Semiconductor - * @{ - */ - -/** @addtogroup nrf51 - * @{ - */ - -#ifndef NRF51_H -#define NRF51_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum { -/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */ - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ - SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ - PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ - SysTick_IRQn = -1, /*!< 15 System Tick Timer */ -/* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */ - POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ - RADIO_IRQn = 1, /*!< 1 RADIO */ - UART0_IRQn = 2, /*!< 2 UART0 */ - SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */ - SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */ - GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ - ADC_IRQn = 7, /*!< 7 ADC */ - TIMER0_IRQn = 8, /*!< 8 TIMER0 */ - TIMER1_IRQn = 9, /*!< 9 TIMER1 */ - TIMER2_IRQn = 10, /*!< 10 TIMER2 */ - RTC0_IRQn = 11, /*!< 11 RTC0 */ - TEMP_IRQn = 12, /*!< 12 TEMP */ - RNG_IRQn = 13, /*!< 13 RNG */ - ECB_IRQn = 14, /*!< 14 ECB */ - CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ - WDT_IRQn = 16, /*!< 16 WDT */ - RTC1_IRQn = 17, /*!< 17 RTC1 */ - QDEC_IRQn = 18, /*!< 18 QDEC */ - LPCOMP_IRQn = 19, /*!< 19 LPCOMP */ - SWI0_IRQn = 20, /*!< 20 SWI0 */ - SWI1_IRQn = 21, /*!< 21 SWI1 */ - SWI2_IRQn = 22, /*!< 22 SWI2 */ - SWI3_IRQn = 23, /*!< 23 SWI3 */ - SWI4_IRQn = 24, /*!< 24 SWI4 */ - SWI5_IRQn = 25 /*!< 25 SWI5 */ -} IRQn_Type; - - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */ -#define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */ -#include "system_nrf51.h" /*!< nrf51 System */ - - -/* ================================================================================ */ -/* ================ Device Specific Peripheral Section ================ */ -/* ================================================================================ */ - - -/** @addtogroup Device_Peripheral_Registers - * @{ - */ - - -/* ------------------- Start of section using anonymous unions ------------------ */ -#if defined(__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined(__ICCARM__) - #pragma language=extended -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) -/* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning 586 -#else - #warning Not supported compiler type -#endif - - -typedef struct { - __O uint32_t EN; /*!< Enable channel group. */ - __O uint32_t DIS; /*!< Disable channel group. */ -} PPI_TASKS_CHG_Type; - -typedef struct { - __IO uint32_t EEP; /*!< Channel event end-point. */ - __IO uint32_t TEP; /*!< Channel task end-point. */ -} PPI_CH_Type; - - -/* ================================================================================ */ -/* ================ POWER ================ */ -/* ================================================================================ */ - - -/** - * @brief Power Control. (POWER) - */ - -typedef struct { /*!< POWER Structure */ - __I uint32_t RESERVED0[30]; - __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */ - __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */ - __I uint32_t RESERVED1[34]; - __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */ - __I uint32_t RESERVED2[126]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED3[61]; - __IO uint32_t RESETREAS; /*!< Reset reason. */ - __I uint32_t RESERVED4[9]; - __I uint32_t RAMSTATUS; /*!< Ram status register. */ - __I uint32_t RESERVED5[53]; - __O uint32_t SYSTEMOFF; /*!< System off register. */ - __I uint32_t RESERVED6[3]; - __IO uint32_t POFCON; /*!< Power failure configuration. */ - __I uint32_t RESERVED7[2]; - __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained - register. */ - __I uint32_t RESERVED8; - __IO uint32_t RAMON; /*!< Ram on/off. */ - __I uint32_t RESERVED9[7]; - __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register - is a retained register. */ - __I uint32_t RESERVED10[3]; - __IO uint32_t RAMONB; /*!< Ram on/off. */ - __I uint32_t RESERVED11[8]; - __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */ - __I uint32_t RESERVED12[291]; - __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */ -} NRF_POWER_Type; - - -/* ================================================================================ */ -/* ================ CLOCK ================ */ -/* ================================================================================ */ - - -/** - * @brief Clock control. (CLOCK) - */ - -typedef struct { /*!< CLOCK Structure */ - __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */ - __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */ - __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */ - __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */ - __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */ - __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */ - __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */ - __I uint32_t RESERVED0[57]; - __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */ - __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */ - __I uint32_t RESERVED1; - __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */ - __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */ - __I uint32_t RESERVED2[124]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED3[63]; - __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */ - __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */ - __I uint32_t RESERVED4; - __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */ - __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */ - __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is - triggered. */ - __I uint32_t RESERVED5[62]; - __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */ - __I uint32_t RESERVED6[7]; - __IO uint32_t CTIV; /*!< Calibration timer interval. */ - __I uint32_t RESERVED7[5]; - __IO uint32_t XTALFREQ; /*!< Crystal frequency. */ -} NRF_CLOCK_Type; - - -/* ================================================================================ */ -/* ================ MPU ================ */ -/* ================================================================================ */ - - -/** - * @brief Memory Protection Unit. (MPU) - */ - -typedef struct { /*!< MPU Structure */ - __I uint32_t RESERVED0[330]; - __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */ - __IO uint32_t RLENR0; /*!< Length of RAM region 0. */ - __I uint32_t RESERVED1[52]; - __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */ - __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */ - __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */ - __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */ -} NRF_MPU_Type; - - -/* ================================================================================ */ -/* ================ RADIO ================ */ -/* ================================================================================ */ - - -/** - * @brief The radio. (RADIO) - */ - -typedef struct { /*!< RADIO Structure */ - __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */ - __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */ - __O uint32_t TASKS_START; /*!< Start radio. */ - __O uint32_t TASKS_STOP; /*!< Stop radio. */ - __O uint32_t TASKS_DISABLE; /*!< Disable radio. */ - __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */ - __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */ - __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */ - __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */ - __I uint32_t RESERVED0[55]; - __IO uint32_t EVENTS_READY; /*!< Ready event. */ - __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */ - __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */ - __IO uint32_t EVENTS_END; /*!< End event. */ - __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */ - __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */ - __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */ - __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI - sample is ready for readout at the RSSISAMPLE register. */ - __I uint32_t RESERVED1[2]; - __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BCC register. */ - __I uint32_t RESERVED2[53]; - __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */ - __I uint32_t RESERVED3[64]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED4[61]; - __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */ - __I uint32_t RESERVED5; - __I uint32_t RXMATCH; /*!< Received address. */ - __I uint32_t RXCRC; /*!< Received CRC. */ - __I uint32_t DAI; /*!< Device address match index. */ - __I uint32_t RESERVED6[60]; - __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */ - __IO uint32_t FREQUENCY; /*!< Frequency. */ - __IO uint32_t TXPOWER; /*!< Output power. */ - __IO uint32_t MODE; /*!< Data rate and modulation. */ - __IO uint32_t PCNF0; /*!< Packet configuration 0. */ - __IO uint32_t PCNF1; /*!< Packet configuration 1. */ - __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */ - __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */ - __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */ - __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */ - __IO uint32_t TXADDRESS; /*!< Transmit address select. */ - __IO uint32_t RXADDRESSES; /*!< Receive address select. */ - __IO uint32_t CRCCNF; /*!< CRC configuration. */ - __IO uint32_t CRCPOLY; /*!< CRC polynomial. */ - __IO uint32_t CRCINIT; /*!< CRC initial value. */ - __IO uint32_t TEST; /*!< Test features enable register. */ - __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */ - __I uint32_t RSSISAMPLE; /*!< RSSI sample. */ - __I uint32_t RESERVED7; - __I uint32_t STATE; /*!< Current radio state. */ - __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */ - __I uint32_t RESERVED8[2]; - __IO uint32_t BCC; /*!< Bit counter compare. */ - __I uint32_t RESERVED9[39]; - __IO uint32_t DAB[8]; /*!< Device address base segment. */ - __IO uint32_t DAP[8]; /*!< Device address prefix. */ - __IO uint32_t DACNF; /*!< Device address match configuration. */ - __I uint32_t RESERVED10[56]; - __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */ - __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */ - __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */ - __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */ - __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */ - __I uint32_t RESERVED11[561]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_RADIO_Type; - - -/* ================================================================================ */ -/* ================ UART ================ */ -/* ================================================================================ */ - - -/** - * @brief Universal Asynchronous Receiver/Transmitter. (UART) - */ - -typedef struct { /*!< UART Structure */ - __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */ - __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */ - __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */ - __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */ - __I uint32_t RESERVED0[3]; - __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */ - __I uint32_t RESERVED1[56]; - __IO uint32_t EVENTS_CTS; /*!< CTS activated. */ - __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */ - __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */ - __I uint32_t RESERVED2[4]; - __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */ - __I uint32_t RESERVED3; - __IO uint32_t EVENTS_ERROR; /*!< Error detected. */ - __I uint32_t RESERVED4[7]; - __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */ - __I uint32_t RESERVED5[46]; - __IO uint32_t SHORTS; /*!< Shortcuts for UART. */ - __I uint32_t RESERVED6[64]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED7[93]; - __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */ - __I uint32_t RESERVED8[31]; - __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */ - __I uint32_t RESERVED9; - __IO uint32_t PSELRTS; /*!< Pin select for RTS. */ - __IO uint32_t PSELTXD; /*!< Pin select for TXD. */ - __IO uint32_t PSELCTS; /*!< Pin select for CTS. */ - __IO uint32_t PSELRXD; /*!< Pin select for RXD. */ - __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced. - Once read the character is consumed. If read when no character - available, the UART will stop working. */ - __O uint32_t TXD; /*!< TXD register. */ - __I uint32_t RESERVED10; - __IO uint32_t BAUDRATE; /*!< UART Baudrate. */ - __I uint32_t RESERVED11[17]; - __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */ - __I uint32_t RESERVED12[675]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_UART_Type; - - -/* ================================================================================ */ -/* ================ SPI ================ */ -/* ================================================================================ */ - - -/** - * @brief SPI master 0. (SPI) - */ - -typedef struct { /*!< SPI Structure */ - __I uint32_t RESERVED0[66]; - __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */ - __I uint32_t RESERVED1[126]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED2[125]; - __IO uint32_t ENABLE; /*!< Enable SPI. */ - __I uint32_t RESERVED3; - __IO uint32_t PSELSCK; /*!< Pin select for SCK. */ - __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */ - __IO uint32_t PSELMISO; /*!< Pin select for MISO. */ - __I uint32_t RESERVED4; - __I uint32_t RXD; /*!< RX data. */ - __IO uint32_t TXD; /*!< TX data. */ - __I uint32_t RESERVED5; - __IO uint32_t FREQUENCY; /*!< SPI frequency */ - __I uint32_t RESERVED6[11]; - __IO uint32_t CONFIG; /*!< Configuration register. */ - __I uint32_t RESERVED7[681]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_SPI_Type; - - -/* ================================================================================ */ -/* ================ TWI ================ */ -/* ================================================================================ */ - - -/** - * @brief Two-wire interface master 0. (TWI) - */ - -typedef struct { /*!< TWI Structure */ - __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */ - __I uint32_t RESERVED0; - __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */ - __I uint32_t RESERVED1[2]; - __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */ - __I uint32_t RESERVED2; - __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */ - __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */ - __I uint32_t RESERVED3[56]; - __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */ - __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */ - __I uint32_t RESERVED4[4]; - __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */ - __I uint32_t RESERVED5; - __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */ - __I uint32_t RESERVED6[4]; - __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */ - __I uint32_t RESERVED7[3]; - __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */ - __I uint32_t RESERVED8[45]; - __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */ - __I uint32_t RESERVED9[64]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED10[110]; - __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */ - __I uint32_t RESERVED11[14]; - __IO uint32_t ENABLE; /*!< Enable two-wire master. */ - __I uint32_t RESERVED12; - __IO uint32_t PSELSCL; /*!< Pin select for SCL. */ - __IO uint32_t PSELSDA; /*!< Pin select for SDA. */ - __I uint32_t RESERVED13[2]; - __I uint32_t RXD; /*!< RX data register. */ - __IO uint32_t TXD; /*!< TX data register. */ - __I uint32_t RESERVED14; - __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */ - __I uint32_t RESERVED15[24]; - __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */ - __I uint32_t RESERVED16[668]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_TWI_Type; - - -/* ================================================================================ */ -/* ================ SPIS ================ */ -/* ================================================================================ */ - - -/** - * @brief SPI slave 1. (SPIS) - */ - -typedef struct { /*!< SPIS Structure */ - __I uint32_t RESERVED0[9]; - __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */ - __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */ - __I uint32_t RESERVED1[54]; - __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */ - __I uint32_t RESERVED2[2]; - __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */ - __I uint32_t RESERVED3[5]; - __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */ - __I uint32_t RESERVED4[53]; - __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */ - __I uint32_t RESERVED5[64]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED6[61]; - __I uint32_t SEMSTAT; /*!< Semaphore status. */ - __I uint32_t RESERVED7[15]; - __IO uint32_t STATUS; /*!< Status from last transaction. */ - __I uint32_t RESERVED8[47]; - __IO uint32_t ENABLE; /*!< Enable SPIS. */ - __I uint32_t RESERVED9; - __IO uint32_t PSELSCK; /*!< Pin select for SCK. */ - __IO uint32_t PSELMISO; /*!< Pin select for MISO. */ - __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */ - __IO uint32_t PSELCSN; /*!< Pin select for CSN. */ - __I uint32_t RESERVED10[7]; - __IO uint32_t RXDPTR; /*!< RX data pointer. */ - __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */ - __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */ - __I uint32_t RESERVED11; - __IO uint32_t TXDPTR; /*!< TX data pointer. */ - __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */ - __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */ - __I uint32_t RESERVED12; - __IO uint32_t CONFIG; /*!< Configuration register. */ - __I uint32_t RESERVED13; - __IO uint32_t DEF; /*!< Default character. */ - __I uint32_t RESERVED14[24]; - __IO uint32_t ORC; /*!< Over-read character. */ - __I uint32_t RESERVED15[654]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_SPIS_Type; - - -/* ================================================================================ */ -/* ================ GPIOTE ================ */ -/* ================================================================================ */ - - -/** - * @brief GPIO tasks and events. (GPIOTE) - */ - -typedef struct { /*!< GPIOTE Structure */ - __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */ - __I uint32_t RESERVED0[60]; - __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */ - __I uint32_t RESERVED1[27]; - __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */ - __I uint32_t RESERVED2[97]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED3[129]; - __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */ - __I uint32_t RESERVED4[695]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_GPIOTE_Type; - - -/* ================================================================================ */ -/* ================ ADC ================ */ -/* ================================================================================ */ - - -/** - * @brief Analog to digital converter. (ADC) - */ - -typedef struct { /*!< ADC Structure */ - __O uint32_t TASKS_START; /*!< Start an ADC conversion. */ - __O uint32_t TASKS_STOP; /*!< Stop ADC. */ - __I uint32_t RESERVED0[62]; - __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */ - __I uint32_t RESERVED1[128]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED2[61]; - __I uint32_t BUSY; /*!< ADC busy register. */ - __I uint32_t RESERVED3[63]; - __IO uint32_t ENABLE; /*!< ADC enable. */ - __IO uint32_t CONFIG; /*!< ADC configuration register. */ - __I uint32_t RESULT; /*!< Result of ADC conversion. */ - __I uint32_t RESERVED4[700]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_ADC_Type; - - -/* ================================================================================ */ -/* ================ TIMER ================ */ -/* ================================================================================ */ - - -/** - * @brief Timer 0. (TIMER) - */ - -typedef struct { /*!< TIMER Structure */ - __O uint32_t TASKS_START; /*!< Start Timer. */ - __O uint32_t TASKS_STOP; /*!< Stop Timer. */ - __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */ - __O uint32_t TASKS_CLEAR; /*!< Clear timer. */ - __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */ - __I uint32_t RESERVED0[11]; - __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */ - __I uint32_t RESERVED1[60]; - __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */ - __I uint32_t RESERVED2[44]; - __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */ - __I uint32_t RESERVED3[64]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED4[126]; - __IO uint32_t MODE; /*!< Timer Mode selection. */ - __IO uint32_t BITMODE; /*!< Sets timer behaviour. */ - __I uint32_t RESERVED5; - __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source - clock frequency is divided by 2^SCALE. */ - __I uint32_t RESERVED6[11]; - __IO uint32_t CC[4]; /*!< Capture/compare registers. */ - __I uint32_t RESERVED7[683]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_TIMER_Type; - - -/* ================================================================================ */ -/* ================ RTC ================ */ -/* ================================================================================ */ - - -/** - * @brief Real time counter 0. (RTC) - */ - -typedef struct { /*!< RTC Structure */ - __O uint32_t TASKS_START; /*!< Start RTC Counter. */ - __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */ - __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */ - __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */ - __I uint32_t RESERVED0[60]; - __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */ - __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */ - __I uint32_t RESERVED1[14]; - __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */ - __I uint32_t RESERVED2[109]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED3[13]; - __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */ - __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives - the value of EVTEN. */ - __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register - gives the value of EVTEN. */ - __I uint32_t RESERVED4[110]; - __I uint32_t COUNTER; /*!< Current COUNTER value. */ - __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). - Must be written when RTC is STOPed. */ - __I uint32_t RESERVED5[13]; - __IO uint32_t CC[4]; /*!< Capture/compare registers. */ - __I uint32_t RESERVED6[683]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_RTC_Type; - - -/* ================================================================================ */ -/* ================ TEMP ================ */ -/* ================================================================================ */ - - -/** - * @brief Temperature Sensor. (TEMP) - */ - -typedef struct { /*!< TEMP Structure */ - __O uint32_t TASKS_START; /*!< Start temperature measurement. */ - __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */ - __I uint32_t RESERVED0[62]; - __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */ - __I uint32_t RESERVED1[128]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED2[127]; - __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */ - __I uint32_t RESERVED3[700]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_TEMP_Type; - - -/* ================================================================================ */ -/* ================ RNG ================ */ -/* ================================================================================ */ - - -/** - * @brief Random Number Generator. (RNG) - */ - -typedef struct { /*!< RNG Structure */ - __O uint32_t TASKS_START; /*!< Start the random number generator. */ - __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */ - __I uint32_t RESERVED0[62]; - __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */ - __I uint32_t RESERVED1[63]; - __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */ - __I uint32_t RESERVED2[64]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */ - __I uint32_t RESERVED3[126]; - __IO uint32_t CONFIG; /*!< Configuration register. */ - __I uint32_t VALUE; /*!< RNG random number. */ - __I uint32_t RESERVED4[700]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_RNG_Type; - - -/* ================================================================================ */ -/* ================ ECB ================ */ -/* ================================================================================ */ - - -/** - * @brief AES ECB Mode Encryption. (ECB) - */ - -typedef struct { /*!< ECB Structure */ - __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this - will not initiate a new encryption and the ERRORECB event will - be triggered. */ - __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running, - this will will trigger the ERRORECB event. */ - __I uint32_t RESERVED0[62]; - __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */ - __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an - error. */ - __I uint32_t RESERVED1[127]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED2[126]; - __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */ - __I uint32_t RESERVED3[701]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_ECB_Type; - - -/* ================================================================================ */ -/* ================ AAR ================ */ -/* ================================================================================ */ - - -/** - * @brief Accelerated Address Resolver. (AAR) - */ - -typedef struct { /*!< AAR Structure */ - __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK - data structure. */ - __I uint32_t RESERVED0; - __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */ - __I uint32_t RESERVED1[61]; - __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */ - __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */ - __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */ - __I uint32_t RESERVED2[126]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED3[61]; - __I uint32_t STATUS; /*!< Resolution status. */ - __I uint32_t RESERVED4[63]; - __IO uint32_t ENABLE; /*!< Enable AAR. */ - __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */ - __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */ - __I uint32_t RESERVED5; - __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */ - __IO uint32_t SCRATCHPTR; /*!< Pointer to a scratch data area used for temporary storage during - resolution. A minimum of 3 bytes must be reserved. */ - __I uint32_t RESERVED6[697]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_AAR_Type; - - -/* ================================================================================ */ -/* ================ CCM ================ */ -/* ================================================================================ */ - - -/** - * @brief AES CCM Mode Encryption. (CCM) - */ - -typedef struct { /*!< CCM Structure */ - __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by - itself when completed. */ - __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when - completed. */ - __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */ - __I uint32_t RESERVED0[61]; - __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */ - __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */ - __IO uint32_t EVENTS_ERROR; /*!< Error happened. */ - __I uint32_t RESERVED1[61]; - __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */ - __I uint32_t RESERVED2[64]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED3[61]; - __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */ - __I uint32_t RESERVED4[63]; - __IO uint32_t ENABLE; /*!< CCM enable. */ - __IO uint32_t MODE; /*!< Operation mode. */ - __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */ - __IO uint32_t INPTR; /*!< Pointer to the input packet. */ - __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */ - __IO uint32_t SCRATCHPTR; /*!< Pointer to a scratch data area used for temporary storage during - resolution. A minimum of 43 bytes must be reserved. */ - __I uint32_t RESERVED5[697]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_CCM_Type; - - -/* ================================================================================ */ -/* ================ WDT ================ */ -/* ================================================================================ */ - - -/** - * @brief Watchdog Timer. (WDT) - */ - -typedef struct { /*!< WDT Structure */ - __O uint32_t TASKS_START; /*!< Start the watchdog. */ - __I uint32_t RESERVED0[63]; - __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */ - __I uint32_t RESERVED1[128]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED2[61]; - __I uint32_t RUNSTATUS; /*!< Watchdog running status. */ - __I uint32_t REQSTATUS; /*!< Request status. */ - __I uint32_t RESERVED3[63]; - __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */ - __IO uint32_t RREN; /*!< Reload request enable. */ - __IO uint32_t CONFIG; /*!< Configuration register. */ - __I uint32_t RESERVED4[60]; - __O uint32_t RR[8]; /*!< Reload requests registers. */ - __I uint32_t RESERVED5[631]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_WDT_Type; - - -/* ================================================================================ */ -/* ================ QDEC ================ */ -/* ================================================================================ */ - - -/** - * @brief Rotary decoder. (QDEC) - */ - -typedef struct { /*!< QDEC Structure */ - __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */ - __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */ - __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers, - and clears the ACC registers. */ - __I uint32_t RESERVED0[61]; - __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */ - __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and - ACC register different than zero. */ - __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */ - __I uint32_t RESERVED1[61]; - __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */ - __I uint32_t RESERVED2[64]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED3[125]; - __IO uint32_t ENABLE; /*!< Enable the QDEC. */ - __IO uint32_t LEDPOL; /*!< LED output pin polarity. */ - __IO uint32_t SAMPLEPER; /*!< Sample period. */ - __I int32_t SAMPLE; /*!< Motion sample value. */ - __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */ - __I int32_t ACC; /*!< Accumulated valid transitions register. */ - __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC - task. */ - __IO uint32_t PSELLED; /*!< Pin select for LED output. */ - __IO uint32_t PSELA; /*!< Pin select for phase A input. */ - __IO uint32_t PSELB; /*!< Pin select for phase B input. */ - __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */ - __I uint32_t RESERVED4[5]; - __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */ - __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */ - __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC - task. */ - __I uint32_t RESERVED5[684]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_QDEC_Type; - - -/* ================================================================================ */ -/* ================ LPCOMP ================ */ -/* ================================================================================ */ - - -/** - * @brief Low power comparator. (LPCOMP) - */ - -typedef struct { /*!< LPCOMP Structure */ - __O uint32_t TASKS_START; /*!< Start the comparator. */ - __O uint32_t TASKS_STOP; /*!< Stop the comparator. */ - __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */ - __I uint32_t RESERVED0[61]; - __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */ - __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */ - __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */ - __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */ - __I uint32_t RESERVED1[60]; - __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */ - __I uint32_t RESERVED2[64]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED3[61]; - __I uint32_t RESULT; /*!< Result of last compare. */ - __I uint32_t RESERVED4[63]; - __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */ - __IO uint32_t PSEL; /*!< Input pin select. */ - __IO uint32_t REFSEL; /*!< Reference select. */ - __IO uint32_t EXTREFSEL; /*!< External reference select. */ - __I uint32_t RESERVED5[4]; - __IO uint32_t ANADETECT; /*!< Analog detect configuration. */ - __I uint32_t RESERVED6[694]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_LPCOMP_Type; - - -/* ================================================================================ */ -/* ================ SWI ================ */ -/* ================================================================================ */ - - -/** - * @brief SW Interrupts. (SWI) - */ - -typedef struct { /*!< SWI Structure */ - __I uint32_t UNUSED; /*!< Unused. */ -} NRF_SWI_Type; - - -/* ================================================================================ */ -/* ================ NVMC ================ */ -/* ================================================================================ */ - - -/** - * @brief Non Volatile Memory Controller. (NVMC) - */ - -typedef struct { /*!< NVMC Structure */ - __I uint32_t RESERVED0[256]; - __I uint32_t READY; /*!< Ready flag. */ - __I uint32_t RESERVED1[64]; - __IO uint32_t CONFIG; /*!< Configuration register. */ - - union { - __IO uint32_t ERASEPCR1; /*!< Register for erasing a non-protected non-volatile memory page. */ - __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */ - }; - __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */ - __IO uint32_t ERASEPCR0; /*!< Register for erasing a protected non-volatile memory page. */ - __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */ -} NRF_NVMC_Type; - - -/* ================================================================================ */ -/* ================ PPI ================ */ -/* ================================================================================ */ - - -/** - * @brief PPI controller. (PPI) - */ - -typedef struct { /*!< PPI Structure */ - PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */ - __I uint32_t RESERVED0[312]; - __IO uint32_t CHEN; /*!< Channel enable. */ - __IO uint32_t CHENSET; /*!< Channel enable set. */ - __IO uint32_t CHENCLR; /*!< Channel enable clear. */ - __I uint32_t RESERVED1; - PPI_CH_Type CH[16]; /*!< PPI Channel. */ - __I uint32_t RESERVED2[156]; - __IO uint32_t CHG[4]; /*!< Channel group configuration. */ -} NRF_PPI_Type; - - -/* ================================================================================ */ -/* ================ FICR ================ */ -/* ================================================================================ */ - - -/** - * @brief Factory Information Configuration. (FICR) - */ - -typedef struct { /*!< FICR Structure */ - __I uint32_t RESERVED0[4]; - __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */ - __I uint32_t CODESIZE; /*!< Code memory size in pages. */ - __I uint32_t RESERVED1[4]; - __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */ - __I uint32_t PPFC; /*!< Pre-programmed factory code present. */ - __I uint32_t RESERVED2; - __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */ - - union { - __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is - kept for backward compatinility purposes. Use SIZERAMBLOCKS - instead. */ - __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */ - }; - __I uint32_t RESERVED3[5]; - __I uint32_t CONFIGID; /*!< Configuration identifier. */ - __I uint32_t DEVICEID[2]; /*!< Device identifier. */ - __I uint32_t RESERVED4[6]; - __I uint32_t ER[4]; /*!< Encryption root. */ - __I uint32_t IR[4]; /*!< Identity root. */ - __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */ - __I uint32_t DEVICEADDR[2]; /*!< Device address. */ - __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */ - __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit - mode. */ - __I uint32_t RESERVED5[10]; - __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit - mode. */ -} NRF_FICR_Type; - - -/* ================================================================================ */ -/* ================ UICR ================ */ -/* ================================================================================ */ - - -/** - * @brief User Information Configuration. (UICR) - */ - -typedef struct { /*!< UICR Structure */ - __IO uint32_t CLENR0; /*!< Length of code region 0. */ - __IO uint32_t RBPCONF; /*!< Readback protection configuration. */ - __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */ - __I uint32_t RESERVED0; - __I uint32_t FWID; /*!< Firmware ID. */ - - union { - __IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */ - __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */ - }; - __IO uint32_t NRFHW[12]; /*!< Reserved for Nordic hardware design. */ - __IO uint32_t CUSTOMER[32]; /*!< Reserved for customer. */ -} NRF_UICR_Type; - - -/* ================================================================================ */ -/* ================ GPIO ================ */ -/* ================================================================================ */ - - -/** - * @brief General purpose input and output. (GPIO) - */ - -typedef struct { /*!< GPIO Structure */ - __I uint32_t RESERVED0[321]; - __IO uint32_t OUT; /*!< Write GPIO port. */ - __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */ - __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */ - __I uint32_t IN; /*!< Read GPIO port. */ - __IO uint32_t DIR; /*!< Direction of GPIO pins. */ - __IO uint32_t DIRSET; /*!< DIR set register. */ - __IO uint32_t DIRCLR; /*!< DIR clear register. */ - __I uint32_t RESERVED1[120]; - __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */ -} NRF_GPIO_Type; - - -/* -------------------- End of section using anonymous unions ------------------- */ -#if defined(__CC_ARM) - #pragma pop -#elif defined(__ICCARM__) - /* leave anonymous unions enabled */ -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning restore -#else - #warning Not supported compiler type -#endif - - - - -/* ================================================================================ */ -/* ================ Peripheral memory map ================ */ -/* ================================================================================ */ - -#define NRF_POWER_BASE 0x40000000UL -#define NRF_CLOCK_BASE 0x40000000UL -#define NRF_MPU_BASE 0x40000000UL -#define NRF_RADIO_BASE 0x40001000UL -#define NRF_UART0_BASE 0x40002000UL -#define NRF_SPI0_BASE 0x40003000UL -#define NRF_TWI0_BASE 0x40003000UL -#define NRF_SPI1_BASE 0x40004000UL -#define NRF_TWI1_BASE 0x40004000UL -#define NRF_SPIS1_BASE 0x40004000UL -#define NRF_GPIOTE_BASE 0x40006000UL -#define NRF_ADC_BASE 0x40007000UL -#define NRF_TIMER0_BASE 0x40008000UL -#define NRF_TIMER1_BASE 0x40009000UL -#define NRF_TIMER2_BASE 0x4000A000UL -#define NRF_RTC0_BASE 0x4000B000UL -#define NRF_TEMP_BASE 0x4000C000UL -#define NRF_RNG_BASE 0x4000D000UL -#define NRF_ECB_BASE 0x4000E000UL -#define NRF_AAR_BASE 0x4000F000UL -#define NRF_CCM_BASE 0x4000F000UL -#define NRF_WDT_BASE 0x40010000UL -#define NRF_RTC1_BASE 0x40011000UL -#define NRF_QDEC_BASE 0x40012000UL -#define NRF_LPCOMP_BASE 0x40013000UL -#define NRF_SWI_BASE 0x40014000UL -#define NRF_NVMC_BASE 0x4001E000UL -#define NRF_PPI_BASE 0x4001F000UL -#define NRF_FICR_BASE 0x10000000UL -#define NRF_UICR_BASE 0x10001000UL -#define NRF_GPIO_BASE 0x50000000UL - - -/* ================================================================================ */ -/* ================ Peripheral declaration ================ */ -/* ================================================================================ */ - -#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE) -#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE) -#define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE) -#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE) -#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE) -#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE) -#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE) -#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE) -#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE) -#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE) -#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE) -#define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE) -#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE) -#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE) -#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE) -#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE) -#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE) -#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE) -#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE) -#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE) -#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE) -#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE) -#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE) -#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE) -#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE) -#define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE) -#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE) -#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE) -#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE) -#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE) -#define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE) - - -/** @} */ /* End of group Device_Peripheral_Registers */ -/** @} */ /* End of group nrf51 */ -/** @} */ /* End of group Nordic Semiconductor */ - -#ifdef __cplusplus -} -#endif - - -#endif /* nrf51_H */ - diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf51_to_nrf52840.h b/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf51_to_nrf52840.h deleted file mode 100644 index e197c225d1..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf51_to_nrf52840.h +++ /dev/null @@ -1,578 +0,0 @@ -/* - -Copyright (c) 2010 - 2018, Nordic Semiconductor ASA - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - -2. Redistributions in binary form, except as embedded into a Nordic - Semiconductor ASA integrated circuit in a product or a software update for - such product, must reproduce the above copyright notice, this list of - conditions and the following disclaimer in the documentation and/or other - materials provided with the distribution. - -3. Neither the name of Nordic Semiconductor ASA nor the names of its - contributors may be used to endorse or promote products derived from this - software without specific prior written permission. - -4. This software, with or without modification, must only be used with a - Nordic Semiconductor ASA integrated circuit. - -5. Any software provided in binary form under this license must not be reverse - engineered, decompiled, modified and/or disassembled. - -THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS -OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*/ - -#ifndef NRF51_TO_NRF52840_H -#define NRF51_TO_NRF52840_H - -/*lint ++flb "Enter library region */ - -/* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52840 devices. - * It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the - * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros - * from the nrf51_deprecated.h file. */ - - -/* IRQ */ -/* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */ -#define UART0_IRQHandler UARTE0_UART0_IRQHandler -#define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler -#define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler -#define ADC_IRQHandler SAADC_IRQHandler -#define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler -#define SWI0_IRQHandler SWI0_EGU0_IRQHandler -#define SWI1_IRQHandler SWI1_EGU1_IRQHandler -#define SWI2_IRQHandler SWI2_EGU2_IRQHandler -#define SWI3_IRQHandler SWI3_EGU3_IRQHandler -#define SWI4_IRQHandler SWI4_EGU4_IRQHandler -#define SWI5_IRQHandler SWI5_EGU5_IRQHandler - -#define UART0_IRQn UARTE0_UART0_IRQn -#define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn -#define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn -#define ADC_IRQn SAADC_IRQn -#define LPCOMP_IRQn COMP_LPCOMP_IRQn -#define SWI0_IRQn SWI0_EGU0_IRQn -#define SWI1_IRQn SWI1_EGU1_IRQn -#define SWI2_IRQn SWI2_EGU2_IRQn -#define SWI3_IRQn SWI3_EGU3_IRQn -#define SWI4_IRQn SWI4_EGU4_IRQn -#define SWI5_IRQn SWI5_EGU5_IRQn - - -/* UICR */ -/* Register RBPCONF was renamed to APPROTECT. */ -#define RBPCONF APPROTECT - -#define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos -#define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk -#define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled -#define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled - - -/* GPIO */ -/* GPIO port was renamed to P0. */ -#define NRF_GPIO NRF_P0 -#define NRF_GPIO_BASE NRF_P0_BASE - - -/* QDEC */ -/* The registers PSELA, PSELB and PSELLED were restructured into a struct. */ -#define PSELLED PSEL.LED -#define PSELA PSEL.A -#define PSELB PSEL.B - - -/* SPIS */ -/* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */ -#define PSELSCK PSEL.SCK -#define PSELMISO PSEL.MISO -#define PSELMOSI PSEL.MOSI -#define PSELCSN PSEL.CSN - -/* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */ -#define RXDPTR RXD.PTR -#define MAXRX RXD.MAXCNT -#define AMOUNTRX RXD.AMOUNT - -#define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos -#define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk - -#define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos -#define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk - -/* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */ -#define TXDPTR TXD.PTR -#define MAXTX TXD.MAXCNT -#define AMOUNTTX TXD.AMOUNT - -#define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos -#define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk - -#define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos -#define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk - - -/* UART */ -/* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */ -#define PSELRTS PSEL.RTS -#define PSELTXD PSEL.TXD -#define PSELCTS PSEL.CTS -#define PSELRXD PSEL.RXD - -/* TWI */ -/* The registers PSELSCL, PSELSDA were restructured into a struct. */ -#define PSELSCL PSEL.SCL -#define PSELSDA PSEL.SDA - - - -/* From nrf51_deprecated.h */ - -/* NVMC */ -/* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */ -#define ERASEPROTECTEDPAGE ERASEPCR0 - - -/* IRQ */ -/* COMP module was eliminated. Adapted to nrf52840 headers. */ -#define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler -#define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn - - -/* REFSEL register redefined enumerated values and added some more. */ -#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling LPCOMP_REFSEL_REFSEL_Ref1_8Vdd -#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref2_8Vdd -#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref3_8Vdd -#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref4_8Vdd -#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref5_8Vdd -#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref6_8Vdd -#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref7_8Vdd - - -/* RADIO */ -/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ -#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos -#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk -#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include -#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip - - -/* FICR */ -/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ -#define DEVICEID0 DEVICEID[0] -#define DEVICEID1 DEVICEID[1] - -/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ -#define ER0 ER[0] -#define ER1 ER[1] -#define ER2 ER[2] -#define ER3 ER[3] - -/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ -#define IR0 IR[0] -#define IR1 IR[1] -#define IR2 IR[2] -#define IR3 IR[3] - -/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ -#define DEVICEADDR0 DEVICEADDR[0] -#define DEVICEADDR1 DEVICEADDR[1] - - -/* PPI */ -/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ -#define TASKS_CHG0EN TASKS_CHG[0].EN -#define TASKS_CHG0DIS TASKS_CHG[0].DIS -#define TASKS_CHG1EN TASKS_CHG[1].EN -#define TASKS_CHG1DIS TASKS_CHG[1].DIS -#define TASKS_CHG2EN TASKS_CHG[2].EN -#define TASKS_CHG2DIS TASKS_CHG[2].DIS -#define TASKS_CHG3EN TASKS_CHG[3].EN -#define TASKS_CHG3DIS TASKS_CHG[3].DIS - -/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ -#define CH0_EEP CH[0].EEP -#define CH0_TEP CH[0].TEP -#define CH1_EEP CH[1].EEP -#define CH1_TEP CH[1].TEP -#define CH2_EEP CH[2].EEP -#define CH2_TEP CH[2].TEP -#define CH3_EEP CH[3].EEP -#define CH3_TEP CH[3].TEP -#define CH4_EEP CH[4].EEP -#define CH4_TEP CH[4].TEP -#define CH5_EEP CH[5].EEP -#define CH5_TEP CH[5].TEP -#define CH6_EEP CH[6].EEP -#define CH6_TEP CH[6].TEP -#define CH7_EEP CH[7].EEP -#define CH7_TEP CH[7].TEP -#define CH8_EEP CH[8].EEP -#define CH8_TEP CH[8].TEP -#define CH9_EEP CH[9].EEP -#define CH9_TEP CH[9].TEP -#define CH10_EEP CH[10].EEP -#define CH10_TEP CH[10].TEP -#define CH11_EEP CH[11].EEP -#define CH11_TEP CH[11].TEP -#define CH12_EEP CH[12].EEP -#define CH12_TEP CH[12].TEP -#define CH13_EEP CH[13].EEP -#define CH13_TEP CH[13].TEP -#define CH14_EEP CH[14].EEP -#define CH14_TEP CH[14].TEP -#define CH15_EEP CH[15].EEP -#define CH15_TEP CH[15].TEP - -/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ -#define CHG0 CHG[0] -#define CHG1 CHG[1] -#define CHG2 CHG[2] -#define CHG3 CHG[3] - -/* All bitfield macros for the CHGx registers therefore changed name. */ -#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos -#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk -#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded -#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included - -#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos -#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk -#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded -#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included - -#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos -#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk -#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded -#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included - -#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos -#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk -#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded -#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included - -#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos -#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk -#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded -#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included - -#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos -#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk -#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded -#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included - -#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos -#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk -#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded -#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included - -#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos -#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk -#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded -#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included - -#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos -#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk -#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded -#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included - -#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos -#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk -#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded -#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included - -#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos -#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk -#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded -#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included - -#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos -#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk -#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded -#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included - -#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos -#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk -#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded -#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included - -#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos -#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk -#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded -#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included - -#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos -#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk -#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded -#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included - -#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos -#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk -#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded -#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included - -#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos -#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk -#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded -#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included - -#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos -#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk -#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded -#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included - -#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos -#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk -#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded -#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included - -#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos -#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk -#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded -#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included - -#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos -#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk -#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded -#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included - -#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos -#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk -#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded -#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included - -#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos -#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk -#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded -#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included - -#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos -#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk -#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded -#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included - -#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos -#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk -#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded -#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included - -#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos -#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk -#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded -#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included - -#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos -#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk -#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded -#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included - -#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos -#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk -#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded -#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included - -#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos -#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk -#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded -#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included - -#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos -#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk -#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded -#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included - -#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos -#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk -#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded -#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included - -#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos -#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk -#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded -#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included - -#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos -#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk -#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded -#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included - -#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos -#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk -#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded -#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included - -#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos -#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk -#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded -#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included - -#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos -#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk -#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded -#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included - -#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos -#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk -#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded -#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included - -#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos -#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk -#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded -#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included - -#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos -#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk -#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded -#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included - -#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos -#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk -#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded -#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included - -#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos -#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk -#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded -#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included - -#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos -#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk -#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded -#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included - -#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos -#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk -#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded -#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included - -#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos -#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk -#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded -#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included - -#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos -#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk -#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded -#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included - -#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos -#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk -#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded -#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included - -#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos -#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk -#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded -#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included - -#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos -#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk -#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded -#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included - -#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos -#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk -#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded -#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included - -#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos -#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk -#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded -#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included - -#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos -#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk -#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded -#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included - -#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos -#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk -#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded -#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included - -#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos -#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk -#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded -#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included - -#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos -#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk -#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded -#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included - -#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos -#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk -#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded -#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included - -#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos -#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk -#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded -#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included - -#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos -#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk -#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded -#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included - -#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos -#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk -#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded -#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included - -#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos -#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk -#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded -#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included - -#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos -#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk -#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded -#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included - -#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos -#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk -#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded -#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included - -#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos -#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk -#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded -#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included - -#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos -#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk -#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded -#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included - -#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos -#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk -#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded -#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included - - - - -/*lint --flb "Leave library region" */ - -#endif /* NRF51_TO_NRF52840_H */ - diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52.h b/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52.h deleted file mode 100644 index 215f327472..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52.h +++ /dev/null @@ -1,2100 +0,0 @@ - -/****************************************************************************************************//** - * @file nrf52.h - * - * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for - * nrf52 from Nordic Semiconductor. - * - * @version V1 - * @date 8. March 2018 - * - * @note Generated with SVDConv V2.81d - * from CMSIS SVD File 'nrf52.svd' Version 1, - * - * @par Copyright (c) 2010 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - *******************************************************************************************************/ - - - -/** @addtogroup Nordic Semiconductor - * @{ - */ - -/** @addtogroup nrf52 - * @{ - */ - -#ifndef NRF52_H -#define NRF52_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum { -/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */ - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation - and No Match */ - BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory - related Fault */ - UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ - PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ - SysTick_IRQn = -1, /*!< 15 System Tick Timer */ -/* ---------------------- nrf52 Specific Interrupt Numbers ---------------------- */ - POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ - RADIO_IRQn = 1, /*!< 1 RADIO */ - UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ - SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ - NFCT_IRQn = 5, /*!< 5 NFCT */ - GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ - SAADC_IRQn = 7, /*!< 7 SAADC */ - TIMER0_IRQn = 8, /*!< 8 TIMER0 */ - TIMER1_IRQn = 9, /*!< 9 TIMER1 */ - TIMER2_IRQn = 10, /*!< 10 TIMER2 */ - RTC0_IRQn = 11, /*!< 11 RTC0 */ - TEMP_IRQn = 12, /*!< 12 TEMP */ - RNG_IRQn = 13, /*!< 13 RNG */ - ECB_IRQn = 14, /*!< 14 ECB */ - CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ - WDT_IRQn = 16, /*!< 16 WDT */ - RTC1_IRQn = 17, /*!< 17 RTC1 */ - QDEC_IRQn = 18, /*!< 18 QDEC */ - COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */ - SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ - SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ - SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ - SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ - SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ - SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ - TIMER3_IRQn = 26, /*!< 26 TIMER3 */ - TIMER4_IRQn = 27, /*!< 27 TIMER4 */ - PWM0_IRQn = 28, /*!< 28 PWM0 */ - PDM_IRQn = 29, /*!< 29 PDM */ - MWU_IRQn = 32, /*!< 32 MWU */ - PWM1_IRQn = 33, /*!< 33 PWM1 */ - PWM2_IRQn = 34, /*!< 34 PWM2 */ - SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */ - RTC2_IRQn = 36, /*!< 36 RTC2 */ - I2S_IRQn = 37, /*!< 37 I2S */ - FPU_IRQn = 38 /*!< 38 FPU */ -} IRQn_Type; - - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */ -#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ -#include "system_nrf52.h" /*!< nrf52 System */ - - -/* ================================================================================ */ -/* ================ Device Specific Peripheral Section ================ */ -/* ================================================================================ */ - - -/** @addtogroup Device_Peripheral_Registers - * @{ - */ - - -/* ------------------- Start of section using anonymous unions ------------------ */ -#if defined(__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined(__ICCARM__) - #pragma language=extended -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) -/* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning 586 -#else - #warning Not supported compiler type -#endif - - -typedef struct { - __I uint32_t PART; /*!< Part code */ - __I uint32_t VARIANT; /*!< Part Variant, Hardware version and Production configuration */ - __I uint32_t PACKAGE; /*!< Package option */ - __I uint32_t RAM; /*!< RAM variant */ - __I uint32_t FLASH; /*!< Flash variant */ - __IO uint32_t UNUSED0[3]; /*!< Description collection[0]: Unspecified */ -} FICR_INFO_Type; - -typedef struct { - __I uint32_t A0; /*!< Slope definition A0. */ - __I uint32_t A1; /*!< Slope definition A1. */ - __I uint32_t A2; /*!< Slope definition A2. */ - __I uint32_t A3; /*!< Slope definition A3. */ - __I uint32_t A4; /*!< Slope definition A4. */ - __I uint32_t A5; /*!< Slope definition A5. */ - __I uint32_t B0; /*!< y-intercept B0. */ - __I uint32_t B1; /*!< y-intercept B1. */ - __I uint32_t B2; /*!< y-intercept B2. */ - __I uint32_t B3; /*!< y-intercept B3. */ - __I uint32_t B4; /*!< y-intercept B4. */ - __I uint32_t B5; /*!< y-intercept B5. */ - __I uint32_t T0; /*!< Segment end T0. */ - __I uint32_t T1; /*!< Segment end T1. */ - __I uint32_t T2; /*!< Segment end T2. */ - __I uint32_t T3; /*!< Segment end T3. */ - __I uint32_t T4; /*!< Segment end T4. */ -} FICR_TEMP_Type; - -typedef struct { - __I uint32_t TAGHEADER0; /*!< Default header for NFC Tag. Software can read these values to - populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ - __I uint32_t TAGHEADER1; /*!< Default header for NFC Tag. Software can read these values to - populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ - __I uint32_t TAGHEADER2; /*!< Default header for NFC Tag. Software can read these values to - populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ - __I uint32_t TAGHEADER3; /*!< Default header for NFC Tag. Software can read these values to - populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ -} FICR_NFC_Type; - -typedef struct { - __IO uint32_t POWER; /*!< Description cluster[0]: RAM0 power control register */ - __O uint32_t POWERSET; /*!< Description cluster[0]: RAM0 power control set register */ - __O uint32_t POWERCLR; /*!< Description cluster[0]: RAM0 power control clear register */ - __I uint32_t RESERVED0; -} POWER_RAM_Type; - -typedef struct { - __IO uint32_t RTS; /*!< Pin select for RTS signal */ - __IO uint32_t TXD; /*!< Pin select for TXD signal */ - __IO uint32_t CTS; /*!< Pin select for CTS signal */ - __IO uint32_t RXD; /*!< Pin select for RXD signal */ -} UARTE_PSEL_Type; - -typedef struct { - __IO uint32_t PTR; /*!< Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ -} UARTE_RXD_Type; - -typedef struct { - __IO uint32_t PTR; /*!< Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ -} UARTE_TXD_Type; - -typedef struct { - __IO uint32_t SCK; /*!< Pin select for SCK */ - __IO uint32_t MOSI; /*!< Pin select for MOSI signal */ - __IO uint32_t MISO; /*!< Pin select for MISO signal */ -} SPIM_PSEL_Type; - -typedef struct { - __IO uint32_t PTR; /*!< Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ - __IO uint32_t LIST; /*!< EasyDMA list type */ -} SPIM_RXD_Type; - -typedef struct { - __IO uint32_t PTR; /*!< Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ - __IO uint32_t LIST; /*!< EasyDMA list type */ -} SPIM_TXD_Type; - -typedef struct { - __IO uint32_t SCK; /*!< Pin select for SCK */ - __IO uint32_t MISO; /*!< Pin select for MISO signal */ - __IO uint32_t MOSI; /*!< Pin select for MOSI signal */ - __IO uint32_t CSN; /*!< Pin select for CSN signal */ -} SPIS_PSEL_Type; - -typedef struct { - __IO uint32_t PTR; /*!< RXD data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes received in last granted transaction */ -} SPIS_RXD_Type; - -typedef struct { - __IO uint32_t PTR; /*!< TXD data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes transmitted in last granted transaction */ -} SPIS_TXD_Type; - -typedef struct { - __IO uint32_t SCL; /*!< Pin select for SCL signal */ - __IO uint32_t SDA; /*!< Pin select for SDA signal */ -} TWIM_PSEL_Type; - -typedef struct { - __IO uint32_t PTR; /*!< Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ - __IO uint32_t LIST; /*!< EasyDMA list type */ -} TWIM_RXD_Type; - -typedef struct { - __IO uint32_t PTR; /*!< Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ - __IO uint32_t LIST; /*!< EasyDMA list type */ -} TWIM_TXD_Type; - -typedef struct { - __IO uint32_t SCL; /*!< Pin select for SCL signal */ - __IO uint32_t SDA; /*!< Pin select for SDA signal */ -} TWIS_PSEL_Type; - -typedef struct { - __IO uint32_t PTR; /*!< RXD Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in RXD buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last RXD transaction */ -} TWIS_RXD_Type; - -typedef struct { - __IO uint32_t PTR; /*!< TXD Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in TXD buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last TXD transaction */ -} TWIS_TXD_Type; - -typedef struct { - __IO uint32_t SCK; /*!< Pin select for SCK */ - __IO uint32_t MOSI; /*!< Pin select for MOSI */ - __IO uint32_t MISO; /*!< Pin select for MISO */ -} SPI_PSEL_Type; - -typedef struct { - __IO uint32_t RX; /*!< Result of last incoming frames */ -} NFCT_FRAMESTATUS_Type; - -typedef struct { - __IO uint32_t FRAMECONFIG; /*!< Configuration of outgoing frames */ - __IO uint32_t AMOUNT; /*!< Size of outgoing frame */ -} NFCT_TXD_Type; - -typedef struct { - __IO uint32_t FRAMECONFIG; /*!< Configuration of incoming frames */ - __I uint32_t AMOUNT; /*!< Size of last incoming frame */ -} NFCT_RXD_Type; - -typedef struct { - __IO uint32_t LIMITH; /*!< Description cluster[0]: Last results is equal or above CH[0].LIMIT.HIGH */ - __IO uint32_t LIMITL; /*!< Description cluster[0]: Last results is equal or below CH[0].LIMIT.LOW */ -} SAADC_EVENTS_CH_Type; - -typedef struct { - __IO uint32_t PSELP; /*!< Description cluster[0]: Input positive pin selection for CH[0] */ - __IO uint32_t PSELN; /*!< Description cluster[0]: Input negative pin selection for CH[0] */ - __IO uint32_t CONFIG; /*!< Description cluster[0]: Input configuration for CH[0] */ - __IO uint32_t LIMIT; /*!< Description cluster[0]: High/low limits for event monitoring - a channel */ -} SAADC_CH_Type; - -typedef struct { - __IO uint32_t PTR; /*!< Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of buffer words to transfer */ - __I uint32_t AMOUNT; /*!< Number of buffer words transferred since last START */ -} SAADC_RESULT_Type; - -typedef struct { - __IO uint32_t LED; /*!< Pin select for LED signal */ - __IO uint32_t A; /*!< Pin select for A signal */ - __IO uint32_t B; /*!< Pin select for B signal */ -} QDEC_PSEL_Type; - -typedef struct { - __IO uint32_t PTR; /*!< Description cluster[0]: Beginning address in Data RAM of this - sequence */ - __IO uint32_t CNT; /*!< Description cluster[0]: Amount of values (duty cycles) in this - sequence */ - __IO uint32_t REFRESH; /*!< Description cluster[0]: Amount of additional PWM periods between - samples loaded into compare register */ - __IO uint32_t ENDDELAY; /*!< Description cluster[0]: Time added after the sequence */ - __I uint32_t RESERVED1[4]; -} PWM_SEQ_Type; - -typedef struct { - __IO uint32_t OUT[4]; /*!< Description collection[0]: Output pin select for PWM channel - 0 */ -} PWM_PSEL_Type; - -typedef struct { - __IO uint32_t CLK; /*!< Pin number configuration for PDM CLK signal */ - __IO uint32_t DIN; /*!< Pin number configuration for PDM DIN signal */ -} PDM_PSEL_Type; - -typedef struct { - __IO uint32_t PTR; /*!< RAM address pointer to write samples to with EasyDMA */ - __IO uint32_t MAXCNT; /*!< Number of samples to allocate memory for in EasyDMA mode */ -} PDM_SAMPLE_Type; - -typedef struct { - __O uint32_t EN; /*!< Description cluster[0]: Enable channel group 0 */ - __O uint32_t DIS; /*!< Description cluster[0]: Disable channel group 0 */ -} PPI_TASKS_CHG_Type; - -typedef struct { - __IO uint32_t EEP; /*!< Description cluster[0]: Channel 0 event end-point */ - __IO uint32_t TEP; /*!< Description cluster[0]: Channel 0 task end-point */ -} PPI_CH_Type; - -typedef struct { - __IO uint32_t TEP; /*!< Description cluster[0]: Channel 0 task end-point */ -} PPI_FORK_Type; - -typedef struct { - __IO uint32_t WA; /*!< Description cluster[0]: Write access to region 0 detected */ - __IO uint32_t RA; /*!< Description cluster[0]: Read access to region 0 detected */ -} MWU_EVENTS_REGION_Type; - -typedef struct { - __IO uint32_t WA; /*!< Description cluster[0]: Write access to peripheral region 0 - detected */ - __IO uint32_t RA; /*!< Description cluster[0]: Read access to peripheral region 0 detected */ -} MWU_EVENTS_PREGION_Type; - -typedef struct { - __IO uint32_t SUBSTATWA; /*!< Description cluster[0]: Source of event/interrupt in region - 0, write access detected while corresponding subregion was enabled - for watching */ - __IO uint32_t SUBSTATRA; /*!< Description cluster[0]: Source of event/interrupt in region - 0, read access detected while corresponding subregion was enabled - for watching */ -} MWU_PERREGION_Type; - -typedef struct { - __IO uint32_t START; /*!< Description cluster[0]: Start address for region 0 */ - __IO uint32_t END; /*!< Description cluster[0]: End address of region 0 */ - __I uint32_t RESERVED2[2]; -} MWU_REGION_Type; - -typedef struct { - __I uint32_t START; /*!< Description cluster[0]: Reserved for future use */ - __I uint32_t END; /*!< Description cluster[0]: Reserved for future use */ - __IO uint32_t SUBS; /*!< Description cluster[0]: Subregions of region 0 */ - __I uint32_t RESERVED3; -} MWU_PREGION_Type; - -typedef struct { - __IO uint32_t MODE; /*!< I2S mode. */ - __IO uint32_t RXEN; /*!< Reception (RX) enable. */ - __IO uint32_t TXEN; /*!< Transmission (TX) enable. */ - __IO uint32_t MCKEN; /*!< Master clock generator enable. */ - __IO uint32_t MCKFREQ; /*!< Master clock generator frequency. */ - __IO uint32_t RATIO; /*!< MCK / LRCK ratio. */ - __IO uint32_t SWIDTH; /*!< Sample width. */ - __IO uint32_t ALIGN; /*!< Alignment of sample within a frame. */ - __IO uint32_t FORMAT; /*!< Frame format. */ - __IO uint32_t CHANNELS; /*!< Enable channels. */ -} I2S_CONFIG_Type; - -typedef struct { - __IO uint32_t PTR; /*!< Receive buffer RAM start address. */ -} I2S_RXD_Type; - -typedef struct { - __IO uint32_t PTR; /*!< Transmit buffer RAM start address. */ -} I2S_TXD_Type; - -typedef struct { - __IO uint32_t MAXCNT; /*!< Size of RXD and TXD buffers. */ -} I2S_RXTXD_Type; - -typedef struct { - __IO uint32_t MCK; /*!< Pin select for MCK signal. */ - __IO uint32_t SCK; /*!< Pin select for SCK signal. */ - __IO uint32_t LRCK; /*!< Pin select for LRCK signal. */ - __IO uint32_t SDIN; /*!< Pin select for SDIN signal. */ - __IO uint32_t SDOUT; /*!< Pin select for SDOUT signal. */ -} I2S_PSEL_Type; - - -/* ================================================================================ */ -/* ================ FICR ================ */ -/* ================================================================================ */ - - -/** - * @brief Factory Information Configuration Registers (FICR) - */ - -typedef struct { /*!< FICR Structure */ - __I uint32_t RESERVED0[4]; - __I uint32_t CODEPAGESIZE; /*!< Code memory page size */ - __I uint32_t CODESIZE; /*!< Code memory size */ - __I uint32_t RESERVED1[18]; - __I uint32_t DEVICEID[2]; /*!< Description collection[0]: Device identifier */ - __I uint32_t RESERVED2[6]; - __I uint32_t ER[4]; /*!< Description collection[0]: Encryption Root, word 0 */ - __I uint32_t IR[4]; /*!< Description collection[0]: Identity Root, word 0 */ - __I uint32_t DEVICEADDRTYPE; /*!< Device address type */ - __I uint32_t DEVICEADDR[2]; /*!< Description collection[0]: Device address 0 */ - __I uint32_t RESERVED3[21]; - FICR_INFO_Type INFO; /*!< Device info */ - __I uint32_t RESERVED4[185]; - FICR_TEMP_Type TEMP; /*!< Registers storing factory TEMP module linearization coefficients */ - __I uint32_t RESERVED5[2]; - FICR_NFC_Type NFC; /*!< Unspecified */ -} NRF_FICR_Type; - - -/* ================================================================================ */ -/* ================ UICR ================ */ -/* ================================================================================ */ - - -/** - * @brief User Information Configuration Registers (UICR) - */ - -typedef struct { /*!< UICR Structure */ - __IO uint32_t UNUSED0; /*!< Unspecified */ - __IO uint32_t UNUSED1; /*!< Unspecified */ - __IO uint32_t UNUSED2; /*!< Unspecified */ - __I uint32_t RESERVED0; - __IO uint32_t UNUSED3; /*!< Unspecified */ - __IO uint32_t NRFFW[15]; /*!< Description collection[0]: Reserved for Nordic firmware design */ - __IO uint32_t NRFHW[12]; /*!< Description collection[0]: Reserved for Nordic hardware design */ - __IO uint32_t CUSTOMER[32]; /*!< Description collection[0]: Reserved for customer */ - __I uint32_t RESERVED1[64]; - __IO uint32_t PSELRESET[2]; /*!< Description collection[0]: Mapping of the nRESET function (see - POWER chapter for details) */ - __IO uint32_t APPROTECT; /*!< Access Port protection */ - __IO uint32_t NFCPINS; /*!< Setting of pins dedicated to NFC functionality: NFC antenna - or GPIO */ -} NRF_UICR_Type; - - -/* ================================================================================ */ -/* ================ BPROT ================ */ -/* ================================================================================ */ - - -/** - * @brief Block Protect (BPROT) - */ - -typedef struct { /*!< BPROT Structure */ - __I uint32_t RESERVED0[384]; - __IO uint32_t CONFIG0; /*!< Block protect configuration register 0 */ - __IO uint32_t CONFIG1; /*!< Block protect configuration register 1 */ - __IO uint32_t DISABLEINDEBUG; /*!< Disable protection mechanism in debug interface mode */ - __IO uint32_t UNUSED0; /*!< Unspecified */ - __IO uint32_t CONFIG2; /*!< Block protect configuration register 2 */ - __IO uint32_t CONFIG3; /*!< Block protect configuration register 3 */ -} NRF_BPROT_Type; - - -/* ================================================================================ */ -/* ================ POWER ================ */ -/* ================================================================================ */ - - -/** - * @brief Power control (POWER) - */ - -typedef struct { /*!< POWER Structure */ - __I uint32_t RESERVED0[30]; - __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode */ - __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency) */ - __I uint32_t RESERVED1[34]; - __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning */ - __I uint32_t RESERVED2[2]; - __IO uint32_t EVENTS_SLEEPENTER; /*!< CPU entered WFI/WFE sleep */ - __IO uint32_t EVENTS_SLEEPEXIT; /*!< CPU exited WFI/WFE sleep */ - __I uint32_t RESERVED3[122]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED4[61]; - __IO uint32_t RESETREAS; /*!< Reset reason */ - __I uint32_t RESERVED5[9]; - __I uint32_t RAMSTATUS; /*!< Deprecated register - RAM status register */ - __I uint32_t RESERVED6[53]; - __O uint32_t SYSTEMOFF; /*!< System OFF register */ - __I uint32_t RESERVED7[3]; - __IO uint32_t POFCON; /*!< Power failure comparator configuration */ - __I uint32_t RESERVED8[2]; - __IO uint32_t GPREGRET; /*!< General purpose retention register */ - __IO uint32_t GPREGRET2; /*!< General purpose retention register */ - __IO uint32_t RAMON; /*!< Deprecated register - RAM on/off register (this register is - retained) */ - __I uint32_t RESERVED9[11]; - __IO uint32_t RAMONB; /*!< Deprecated register - RAM on/off register (this register is - retained) */ - __I uint32_t RESERVED10[8]; - __IO uint32_t DCDCEN; /*!< DC/DC enable register */ - __I uint32_t RESERVED11[225]; - POWER_RAM_Type RAM[8]; /*!< Unspecified */ -} NRF_POWER_Type; - - -/* ================================================================================ */ -/* ================ CLOCK ================ */ -/* ================================================================================ */ - - -/** - * @brief Clock control (CLOCK) - */ - -typedef struct { /*!< CLOCK Structure */ - __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK crystal oscillator */ - __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK crystal oscillator */ - __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK source */ - __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK source */ - __O uint32_t TASKS_CAL; /*!< Start calibration of LFRC oscillator */ - __O uint32_t TASKS_CTSTART; /*!< Start calibration timer */ - __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer */ - __I uint32_t RESERVED0[57]; - __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started */ - __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK started */ - __I uint32_t RESERVED1; - __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator complete event */ - __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout */ - __I uint32_t RESERVED2[124]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[63]; - __I uint32_t HFCLKRUN; /*!< Status indicating that HFCLKSTART task has been triggered */ - __I uint32_t HFCLKSTAT; /*!< HFCLK status */ - __I uint32_t RESERVED4; - __I uint32_t LFCLKRUN; /*!< Status indicating that LFCLKSTART task has been triggered */ - __I uint32_t LFCLKSTAT; /*!< LFCLK status */ - __I uint32_t LFCLKSRCCOPY; /*!< Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ - __I uint32_t RESERVED5[62]; - __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK */ - __I uint32_t RESERVED6[7]; - __IO uint32_t CTIV; /*!< Calibration timer interval */ - __I uint32_t RESERVED7[8]; - __IO uint32_t TRACECONFIG; /*!< Clocking options for the Trace Port debug interface */ -} NRF_CLOCK_Type; - - -/* ================================================================================ */ -/* ================ RADIO ================ */ -/* ================================================================================ */ - - -/** - * @brief 2.4 GHz Radio (RADIO) - */ - -typedef struct { /*!< RADIO Structure */ - __O uint32_t TASKS_TXEN; /*!< Enable RADIO in TX mode */ - __O uint32_t TASKS_RXEN; /*!< Enable RADIO in RX mode */ - __O uint32_t TASKS_START; /*!< Start RADIO */ - __O uint32_t TASKS_STOP; /*!< Stop RADIO */ - __O uint32_t TASKS_DISABLE; /*!< Disable RADIO */ - __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one single sample of the receive signal - strength. */ - __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement */ - __O uint32_t TASKS_BCSTART; /*!< Start the bit counter */ - __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter */ - __I uint32_t RESERVED0[55]; - __IO uint32_t EVENTS_READY; /*!< RADIO has ramped up and is ready to be started */ - __IO uint32_t EVENTS_ADDRESS; /*!< Address sent or received */ - __IO uint32_t EVENTS_PAYLOAD; /*!< Packet payload sent or received */ - __IO uint32_t EVENTS_END; /*!< Packet sent or received */ - __IO uint32_t EVENTS_DISABLED; /*!< RADIO has been disabled */ - __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet */ - __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet */ - __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of receive signal strength complete. */ - __I uint32_t RESERVED1[2]; - __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value. */ - __I uint32_t RESERVED2; - __IO uint32_t EVENTS_CRCOK; /*!< Packet received with CRC ok */ - __IO uint32_t EVENTS_CRCERROR; /*!< Packet received with CRC error */ - __I uint32_t RESERVED3[50]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED4[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED5[61]; - __I uint32_t CRCSTATUS; /*!< CRC status */ - __I uint32_t RESERVED6; - __I uint32_t RXMATCH; /*!< Received address */ - __I uint32_t RXCRC; /*!< CRC field of previously received packet */ - __I uint32_t DAI; /*!< Device address match index */ - __I uint32_t RESERVED7[60]; - __IO uint32_t PACKETPTR; /*!< Packet pointer */ - __IO uint32_t FREQUENCY; /*!< Frequency */ - __IO uint32_t TXPOWER; /*!< Output power */ - __IO uint32_t MODE; /*!< Data rate and modulation */ - __IO uint32_t PCNF0; /*!< Packet configuration register 0 */ - __IO uint32_t PCNF1; /*!< Packet configuration register 1 */ - __IO uint32_t BASE0; /*!< Base address 0 */ - __IO uint32_t BASE1; /*!< Base address 1 */ - __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0-3 */ - __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4-7 */ - __IO uint32_t TXADDRESS; /*!< Transmit address select */ - __IO uint32_t RXADDRESSES; /*!< Receive address select */ - __IO uint32_t CRCCNF; /*!< CRC configuration */ - __IO uint32_t CRCPOLY; /*!< CRC polynomial */ - __IO uint32_t CRCINIT; /*!< CRC initial value */ - __IO uint32_t UNUSED0; /*!< Unspecified */ - __IO uint32_t TIFS; /*!< Inter Frame Spacing in us */ - __I uint32_t RSSISAMPLE; /*!< RSSI sample */ - __I uint32_t RESERVED8; - __I uint32_t STATE; /*!< Current radio state */ - __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value */ - __I uint32_t RESERVED9[2]; - __IO uint32_t BCC; /*!< Bit counter compare */ - __I uint32_t RESERVED10[39]; - __IO uint32_t DAB[8]; /*!< Description collection[0]: Device address base segment 0 */ - __IO uint32_t DAP[8]; /*!< Description collection[0]: Device address prefix 0 */ - __IO uint32_t DACNF; /*!< Device address match configuration */ - __I uint32_t RESERVED11[3]; - __IO uint32_t MODECNF0; /*!< Radio mode configuration register 0 */ - __I uint32_t RESERVED12[618]; - __IO uint32_t POWER; /*!< Peripheral power control */ -} NRF_RADIO_Type; - - -/* ================================================================================ */ -/* ================ UARTE ================ */ -/* ================================================================================ */ - - -/** - * @brief UART with EasyDMA (UARTE) - */ - -typedef struct { /*!< UARTE Structure */ - __O uint32_t TASKS_STARTRX; /*!< Start UART receiver */ - __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver */ - __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter */ - __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter */ - __I uint32_t RESERVED0[7]; - __O uint32_t TASKS_FLUSHRX; /*!< Flush RX FIFO into RX buffer */ - __I uint32_t RESERVED1[52]; - __IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */ - __IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */ - __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD (but potentially not yet transferred to - Data RAM) */ - __I uint32_t RESERVED2; - __IO uint32_t EVENTS_ENDRX; /*!< Receive buffer is filled up */ - __I uint32_t RESERVED3[2]; - __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD */ - __IO uint32_t EVENTS_ENDTX; /*!< Last TX byte transmitted */ - __IO uint32_t EVENTS_ERROR; /*!< Error detected */ - __I uint32_t RESERVED4[7]; - __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout */ - __I uint32_t RESERVED5; - __IO uint32_t EVENTS_RXSTARTED; /*!< UART receiver has started */ - __IO uint32_t EVENTS_TXSTARTED; /*!< UART transmitter has started */ - __I uint32_t RESERVED6; - __IO uint32_t EVENTS_TXSTOPPED; /*!< Transmitter stopped */ - __I uint32_t RESERVED7[41]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED8[63]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED9[93]; - __IO uint32_t ERRORSRC; /*!< Error source */ - __I uint32_t RESERVED10[31]; - __IO uint32_t ENABLE; /*!< Enable UART */ - __I uint32_t RESERVED11; - UARTE_PSEL_Type PSEL; /*!< Unspecified */ - __I uint32_t RESERVED12[3]; - __IO uint32_t BAUDRATE; /*!< Baud rate. Accuracy depends on the HFCLK source selected. */ - __I uint32_t RESERVED13[3]; - UARTE_RXD_Type RXD; /*!< RXD EasyDMA channel */ - __I uint32_t RESERVED14; - UARTE_TXD_Type TXD; /*!< TXD EasyDMA channel */ - __I uint32_t RESERVED15[7]; - __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control */ -} NRF_UARTE_Type; - - -/* ================================================================================ */ -/* ================ UART ================ */ -/* ================================================================================ */ - - -/** - * @brief Universal Asynchronous Receiver/Transmitter (UART) - */ - -typedef struct { /*!< UART Structure */ - __O uint32_t TASKS_STARTRX; /*!< Start UART receiver */ - __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver */ - __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter */ - __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter */ - __I uint32_t RESERVED0[3]; - __O uint32_t TASKS_SUSPEND; /*!< Suspend UART */ - __I uint32_t RESERVED1[56]; - __IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */ - __IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */ - __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD */ - __I uint32_t RESERVED2[4]; - __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD */ - __I uint32_t RESERVED3; - __IO uint32_t EVENTS_ERROR; /*!< Error detected */ - __I uint32_t RESERVED4[7]; - __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout */ - __I uint32_t RESERVED5[46]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED6[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED7[93]; - __IO uint32_t ERRORSRC; /*!< Error source */ - __I uint32_t RESERVED8[31]; - __IO uint32_t ENABLE; /*!< Enable UART */ - __I uint32_t RESERVED9; - __IO uint32_t PSELRTS; /*!< Pin select for RTS */ - __IO uint32_t PSELTXD; /*!< Pin select for TXD */ - __IO uint32_t PSELCTS; /*!< Pin select for CTS */ - __IO uint32_t PSELRXD; /*!< Pin select for RXD */ - __I uint32_t RXD; /*!< RXD register */ - __O uint32_t TXD; /*!< TXD register */ - __I uint32_t RESERVED10; - __IO uint32_t BAUDRATE; /*!< Baud rate */ - __I uint32_t RESERVED11[17]; - __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control */ -} NRF_UART_Type; - - -/* ================================================================================ */ -/* ================ SPIM ================ */ -/* ================================================================================ */ - - -/** - * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM) - */ - -typedef struct { /*!< SPIM Structure */ - __I uint32_t RESERVED0[4]; - __O uint32_t TASKS_START; /*!< Start SPI transaction */ - __O uint32_t TASKS_STOP; /*!< Stop SPI transaction */ - __I uint32_t RESERVED1; - __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction */ - __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction */ - __I uint32_t RESERVED2[56]; - __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped */ - __I uint32_t RESERVED3[2]; - __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */ - __I uint32_t RESERVED4; - __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached */ - __I uint32_t RESERVED5; - __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached */ - __I uint32_t RESERVED6[10]; - __IO uint32_t EVENTS_STARTED; /*!< Transaction started */ - __I uint32_t RESERVED7[44]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED8[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED9[125]; - __IO uint32_t ENABLE; /*!< Enable SPIM */ - __I uint32_t RESERVED10; - SPIM_PSEL_Type PSEL; /*!< Unspecified */ - __I uint32_t RESERVED11[4]; - __IO uint32_t FREQUENCY; /*!< SPI frequency. Accuracy depends on the HFCLK source selected. */ - __I uint32_t RESERVED12[3]; - SPIM_RXD_Type RXD; /*!< RXD EasyDMA channel */ - SPIM_TXD_Type TXD; /*!< TXD EasyDMA channel */ - __IO uint32_t CONFIG; /*!< Configuration register */ - __I uint32_t RESERVED13[26]; - __IO uint32_t ORC; /*!< Over-read character. Character clocked out in case and over-read - of the TXD buffer. */ -} NRF_SPIM_Type; - - -/* ================================================================================ */ -/* ================ SPIS ================ */ -/* ================================================================================ */ - - -/** - * @brief SPI Slave 0 (SPIS) - */ - -typedef struct { /*!< SPIS Structure */ - __I uint32_t RESERVED0[9]; - __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore */ - __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore, enabling the SPI slave to acquire it */ - __I uint32_t RESERVED1[54]; - __IO uint32_t EVENTS_END; /*!< Granted transaction completed */ - __I uint32_t RESERVED2[2]; - __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */ - __I uint32_t RESERVED3[5]; - __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired */ - __I uint32_t RESERVED4[53]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED5[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED6[61]; - __I uint32_t SEMSTAT; /*!< Semaphore status register */ - __I uint32_t RESERVED7[15]; - __IO uint32_t STATUS; /*!< Status from last transaction */ - __I uint32_t RESERVED8[47]; - __IO uint32_t ENABLE; /*!< Enable SPI slave */ - __I uint32_t RESERVED9; - SPIS_PSEL_Type PSEL; /*!< Unspecified */ - __I uint32_t RESERVED10[7]; - SPIS_RXD_Type RXD; /*!< Unspecified */ - __I uint32_t RESERVED11; - SPIS_TXD_Type TXD; /*!< Unspecified */ - __I uint32_t RESERVED12; - __IO uint32_t CONFIG; /*!< Configuration register */ - __I uint32_t RESERVED13; - __IO uint32_t DEF; /*!< Default character. Character clocked out in case of an ignored - transaction. */ - __I uint32_t RESERVED14[24]; - __IO uint32_t ORC; /*!< Over-read character */ -} NRF_SPIS_Type; - - -/* ================================================================================ */ -/* ================ TWIM ================ */ -/* ================================================================================ */ - - -/** - * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM) - */ - -typedef struct { /*!< TWIM Structure */ - __O uint32_t TASKS_STARTRX; /*!< Start TWI receive sequence */ - __I uint32_t RESERVED0; - __O uint32_t TASKS_STARTTX; /*!< Start TWI transmit sequence */ - __I uint32_t RESERVED1[2]; - __O uint32_t TASKS_STOP; /*!< Stop TWI transaction. Must be issued while the TWI master is - not suspended. */ - __I uint32_t RESERVED2; - __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */ - __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */ - __I uint32_t RESERVED3[56]; - __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */ - __I uint32_t RESERVED4[7]; - __IO uint32_t EVENTS_ERROR; /*!< TWI error */ - __I uint32_t RESERVED5[8]; - __IO uint32_t EVENTS_SUSPENDED; /*!< Last byte has been sent out after the SUSPEND task has been - issued, TWI traffic is now suspended. */ - __IO uint32_t EVENTS_RXSTARTED; /*!< Receive sequence started */ - __IO uint32_t EVENTS_TXSTARTED; /*!< Transmit sequence started */ - __I uint32_t RESERVED6[2]; - __IO uint32_t EVENTS_LASTRX; /*!< Byte boundary, starting to receive the last byte */ - __IO uint32_t EVENTS_LASTTX; /*!< Byte boundary, starting to transmit the last byte */ - __I uint32_t RESERVED7[39]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED8[63]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED9[110]; - __IO uint32_t ERRORSRC; /*!< Error source */ - __I uint32_t RESERVED10[14]; - __IO uint32_t ENABLE; /*!< Enable TWIM */ - __I uint32_t RESERVED11; - TWIM_PSEL_Type PSEL; /*!< Unspecified */ - __I uint32_t RESERVED12[5]; - __IO uint32_t FREQUENCY; /*!< TWI frequency */ - __I uint32_t RESERVED13[3]; - TWIM_RXD_Type RXD; /*!< RXD EasyDMA channel */ - TWIM_TXD_Type TXD; /*!< TXD EasyDMA channel */ - __I uint32_t RESERVED14[13]; - __IO uint32_t ADDRESS; /*!< Address used in the TWI transfer */ -} NRF_TWIM_Type; - - -/* ================================================================================ */ -/* ================ TWIS ================ */ -/* ================================================================================ */ - - -/** - * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS) - */ - -typedef struct { /*!< TWIS Structure */ - __I uint32_t RESERVED0[5]; - __O uint32_t TASKS_STOP; /*!< Stop TWI transaction */ - __I uint32_t RESERVED1; - __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */ - __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */ - __I uint32_t RESERVED2[3]; - __O uint32_t TASKS_PREPARERX; /*!< Prepare the TWI slave to respond to a write command */ - __O uint32_t TASKS_PREPARETX; /*!< Prepare the TWI slave to respond to a read command */ - __I uint32_t RESERVED3[51]; - __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */ - __I uint32_t RESERVED4[7]; - __IO uint32_t EVENTS_ERROR; /*!< TWI error */ - __I uint32_t RESERVED5[9]; - __IO uint32_t EVENTS_RXSTARTED; /*!< Receive sequence started */ - __IO uint32_t EVENTS_TXSTARTED; /*!< Transmit sequence started */ - __I uint32_t RESERVED6[4]; - __IO uint32_t EVENTS_WRITE; /*!< Write command received */ - __IO uint32_t EVENTS_READ; /*!< Read command received */ - __I uint32_t RESERVED7[37]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED8[63]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED9[113]; - __IO uint32_t ERRORSRC; /*!< Error source */ - __I uint32_t MATCH; /*!< Status register indicating which address had a match */ - __I uint32_t RESERVED10[10]; - __IO uint32_t ENABLE; /*!< Enable TWIS */ - __I uint32_t RESERVED11; - TWIS_PSEL_Type PSEL; /*!< Unspecified */ - __I uint32_t RESERVED12[9]; - TWIS_RXD_Type RXD; /*!< RXD EasyDMA channel */ - __I uint32_t RESERVED13; - TWIS_TXD_Type TXD; /*!< TXD EasyDMA channel */ - __I uint32_t RESERVED14[14]; - __IO uint32_t ADDRESS[2]; /*!< Description collection[0]: TWI slave address 0 */ - __I uint32_t RESERVED15; - __IO uint32_t CONFIG; /*!< Configuration register for the address match mechanism */ - __I uint32_t RESERVED16[10]; - __IO uint32_t ORC; /*!< Over-read character. Character sent out in case of an over-read - of the transmit buffer. */ -} NRF_TWIS_Type; - - -/* ================================================================================ */ -/* ================ SPI ================ */ -/* ================================================================================ */ - - -/** - * @brief Serial Peripheral Interface 0 (SPI) - */ - -typedef struct { /*!< SPI Structure */ - __I uint32_t RESERVED0[66]; - __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received */ - __I uint32_t RESERVED1[126]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED2[125]; - __IO uint32_t ENABLE; /*!< Enable SPI */ - __I uint32_t RESERVED3; - SPI_PSEL_Type PSEL; /*!< Unspecified */ - __I uint32_t RESERVED4; - __I uint32_t RXD; /*!< RXD register */ - __IO uint32_t TXD; /*!< TXD register */ - __I uint32_t RESERVED5; - __IO uint32_t FREQUENCY; /*!< SPI frequency */ - __I uint32_t RESERVED6[11]; - __IO uint32_t CONFIG; /*!< Configuration register */ -} NRF_SPI_Type; - - -/* ================================================================================ */ -/* ================ TWI ================ */ -/* ================================================================================ */ - - -/** - * @brief I2C compatible Two-Wire Interface 0 (TWI) - */ - -typedef struct { /*!< TWI Structure */ - __O uint32_t TASKS_STARTRX; /*!< Start TWI receive sequence */ - __I uint32_t RESERVED0; - __O uint32_t TASKS_STARTTX; /*!< Start TWI transmit sequence */ - __I uint32_t RESERVED1[2]; - __O uint32_t TASKS_STOP; /*!< Stop TWI transaction */ - __I uint32_t RESERVED2; - __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */ - __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */ - __I uint32_t RESERVED3[56]; - __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */ - __IO uint32_t EVENTS_RXDREADY; /*!< TWI RXD byte received */ - __I uint32_t RESERVED4[4]; - __IO uint32_t EVENTS_TXDSENT; /*!< TWI TXD byte sent */ - __I uint32_t RESERVED5; - __IO uint32_t EVENTS_ERROR; /*!< TWI error */ - __I uint32_t RESERVED6[4]; - __IO uint32_t EVENTS_BB; /*!< TWI byte boundary, generated before each byte that is sent or - received */ - __I uint32_t RESERVED7[3]; - __IO uint32_t EVENTS_SUSPENDED; /*!< TWI entered the suspended state */ - __I uint32_t RESERVED8[45]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED9[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED10[110]; - __IO uint32_t ERRORSRC; /*!< Error source */ - __I uint32_t RESERVED11[14]; - __IO uint32_t ENABLE; /*!< Enable TWI */ - __I uint32_t RESERVED12; - __IO uint32_t PSELSCL; /*!< Pin select for SCL */ - __IO uint32_t PSELSDA; /*!< Pin select for SDA */ - __I uint32_t RESERVED13[2]; - __I uint32_t RXD; /*!< RXD register */ - __IO uint32_t TXD; /*!< TXD register */ - __I uint32_t RESERVED14; - __IO uint32_t FREQUENCY; /*!< TWI frequency */ - __I uint32_t RESERVED15[24]; - __IO uint32_t ADDRESS; /*!< Address used in the TWI transfer */ -} NRF_TWI_Type; - - -/* ================================================================================ */ -/* ================ NFCT ================ */ -/* ================================================================================ */ - - -/** - * @brief NFC-A compatible radio (NFCT) - */ - -typedef struct { /*!< NFCT Structure */ - __O uint32_t TASKS_ACTIVATE; /*!< Activate NFC peripheral for incoming and outgoing frames, change - state to activated */ - __O uint32_t TASKS_DISABLE; /*!< Disable NFC peripheral */ - __O uint32_t TASKS_SENSE; /*!< Enable NFC sense field mode, change state to sense mode */ - __O uint32_t TASKS_STARTTX; /*!< Start transmission of a outgoing frame, change state to transmit */ - __I uint32_t RESERVED0[3]; - __O uint32_t TASKS_ENABLERXDATA; /*!< Initializes the EasyDMA for receive. */ - __I uint32_t RESERVED1; - __O uint32_t TASKS_GOIDLE; /*!< Force state machine to IDLE state */ - __O uint32_t TASKS_GOSLEEP; /*!< Force state machine to SLEEP_A state */ - __I uint32_t RESERVED2[53]; - __IO uint32_t EVENTS_READY; /*!< The NFC peripheral is ready to receive and send frames */ - __IO uint32_t EVENTS_FIELDDETECTED; /*!< Remote NFC field detected */ - __IO uint32_t EVENTS_FIELDLOST; /*!< Remote NFC field lost */ - __IO uint32_t EVENTS_TXFRAMESTART; /*!< Marks the start of the first symbol of a transmitted frame */ - __IO uint32_t EVENTS_TXFRAMEEND; /*!< Marks the end of the last transmitted on-air symbol of a frame */ - __IO uint32_t EVENTS_RXFRAMESTART; /*!< Marks the end of the first symbol of a received frame */ - __IO uint32_t EVENTS_RXFRAMEEND; /*!< Received data have been checked (CRC, parity) and transferred - to RAM, and EasyDMA has ended accessing the RX buffer */ - __IO uint32_t EVENTS_ERROR; /*!< NFC error reported. The ERRORSTATUS register contains details - on the source of the error. */ - __I uint32_t RESERVED3[2]; - __IO uint32_t EVENTS_RXERROR; /*!< NFC RX frame error reported. The FRAMESTATUS.RX register contains - details on the source of the error. */ - __IO uint32_t EVENTS_ENDRX; /*!< RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */ - __IO uint32_t EVENTS_ENDTX; /*!< Transmission of data in RAM has ended, and EasyDMA has ended - accessing the TX buffer */ - __I uint32_t RESERVED4; - __IO uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< Auto collision resolution process has started */ - __I uint32_t RESERVED5[3]; - __IO uint32_t EVENTS_COLLISION; /*!< NFC Auto collision resolution error reported. */ - __IO uint32_t EVENTS_SELECTED; /*!< NFC Auto collision resolution successfully completed */ - __IO uint32_t EVENTS_STARTED; /*!< EasyDMA is ready to receive or send frames. */ - __I uint32_t RESERVED6[43]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED7[63]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED8[62]; - __IO uint32_t ERRORSTATUS; /*!< NFC Error Status register */ - __I uint32_t RESERVED9; - NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< Unspecified */ - __I uint32_t RESERVED10[8]; - __I uint32_t CURRENTLOADCTRL; /*!< Current value driven to the NFC Load Control */ - __I uint32_t RESERVED11[2]; - __I uint32_t FIELDPRESENT; /*!< Indicates the presence or not of a valid field */ - __I uint32_t RESERVED12[49]; - __IO uint32_t FRAMEDELAYMIN; /*!< Minimum frame delay */ - __IO uint32_t FRAMEDELAYMAX; /*!< Maximum frame delay */ - __IO uint32_t FRAMEDELAYMODE; /*!< Configuration register for the Frame Delay Timer */ - __IO uint32_t PACKETPTR; /*!< Packet pointer for TXD and RXD data storage in Data RAM */ - __IO uint32_t MAXLEN; /*!< Size of allocated for TXD and RXD data storage buffer in Data - RAM */ - NFCT_TXD_Type TXD; /*!< Unspecified */ - NFCT_RXD_Type RXD; /*!< Unspecified */ - __I uint32_t RESERVED13[26]; - __IO uint32_t NFCID1_LAST; /*!< Last NFCID1 part (4, 7 or 10 bytes ID) */ - __IO uint32_t NFCID1_2ND_LAST; /*!< Second last NFCID1 part (7 or 10 bytes ID) */ - __IO uint32_t NFCID1_3RD_LAST; /*!< Third last NFCID1 part (10 bytes ID) */ - __I uint32_t RESERVED14; - __IO uint32_t SENSRES; /*!< NFC-A SENS_RES auto-response settings */ - __IO uint32_t SELRES; /*!< NFC-A SEL_RES auto-response settings */ -} NRF_NFCT_Type; - - -/* ================================================================================ */ -/* ================ GPIOTE ================ */ -/* ================================================================================ */ - - -/** - * @brief GPIO Tasks and Events (GPIOTE) - */ - -typedef struct { /*!< GPIOTE Structure */ - __O uint32_t TASKS_OUT[8]; /*!< Description collection[0]: Task for writing to pin specified - in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. */ - __I uint32_t RESERVED0[4]; - __O uint32_t TASKS_SET[8]; /*!< Description collection[0]: Task for writing to pin specified - in CONFIG[0].PSEL. Action on pin is to set it high. */ - __I uint32_t RESERVED1[4]; - __O uint32_t TASKS_CLR[8]; /*!< Description collection[0]: Task for writing to pin specified - in CONFIG[0].PSEL. Action on pin is to set it low. */ - __I uint32_t RESERVED2[32]; - __IO uint32_t EVENTS_IN[8]; /*!< Description collection[0]: Event generated from pin specified - in CONFIG[0].PSEL */ - __I uint32_t RESERVED3[23]; - __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple input GPIO pins with SENSE mechanism - enabled */ - __I uint32_t RESERVED4[97]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED5[129]; - __IO uint32_t CONFIG[8]; /*!< Description collection[0]: Configuration for OUT[n], SET[n] - and CLR[n] tasks and IN[n] event */ -} NRF_GPIOTE_Type; - - -/* ================================================================================ */ -/* ================ SAADC ================ */ -/* ================================================================================ */ - - -/** - * @brief Analog to Digital Converter (SAADC) - */ - -typedef struct { /*!< SAADC Structure */ - __O uint32_t TASKS_START; /*!< Start the ADC and prepare the result buffer in RAM */ - __O uint32_t TASKS_SAMPLE; /*!< Take one ADC sample, if scan is enabled all channels are sampled */ - __O uint32_t TASKS_STOP; /*!< Stop the ADC and terminate any on-going conversion */ - __O uint32_t TASKS_CALIBRATEOFFSET; /*!< Starts offset auto-calibration */ - __I uint32_t RESERVED0[60]; - __IO uint32_t EVENTS_STARTED; /*!< The ADC has started */ - __IO uint32_t EVENTS_END; /*!< The ADC has filled up the Result buffer */ - __IO uint32_t EVENTS_DONE; /*!< A conversion task has been completed. Depending on the mode, - multiple conversions might be needed for a result to be transferred - to RAM. */ - __IO uint32_t EVENTS_RESULTDONE; /*!< A result is ready to get transferred to RAM. */ - __IO uint32_t EVENTS_CALIBRATEDONE; /*!< Calibration is complete */ - __IO uint32_t EVENTS_STOPPED; /*!< The ADC has stopped */ - SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< Unspecified */ - __I uint32_t RESERVED1[106]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED2[61]; - __I uint32_t STATUS; /*!< Status */ - __I uint32_t RESERVED3[63]; - __IO uint32_t ENABLE; /*!< Enable or disable ADC */ - __I uint32_t RESERVED4[3]; - SAADC_CH_Type CH[8]; /*!< Unspecified */ - __I uint32_t RESERVED5[24]; - __IO uint32_t RESOLUTION; /*!< Resolution configuration */ - __IO uint32_t OVERSAMPLE; /*!< Oversampling configuration. OVERSAMPLE should not be combined - with SCAN. The RESOLUTION is applied before averaging, thus - for high OVERSAMPLE a higher RESOLUTION should be used. */ - __IO uint32_t SAMPLERATE; /*!< Controls normal or continuous sample rate */ - __I uint32_t RESERVED6[12]; - SAADC_RESULT_Type RESULT; /*!< RESULT EasyDMA channel */ -} NRF_SAADC_Type; - - -/* ================================================================================ */ -/* ================ TIMER ================ */ -/* ================================================================================ */ - - -/** - * @brief Timer/Counter 0 (TIMER) - */ - -typedef struct { /*!< TIMER Structure */ - __O uint32_t TASKS_START; /*!< Start Timer */ - __O uint32_t TASKS_STOP; /*!< Stop Timer */ - __O uint32_t TASKS_COUNT; /*!< Increment Timer (Counter mode only) */ - __O uint32_t TASKS_CLEAR; /*!< Clear time */ - __O uint32_t TASKS_SHUTDOWN; /*!< Deprecated register - Shut down timer */ - __I uint32_t RESERVED0[11]; - __O uint32_t TASKS_CAPTURE[6]; /*!< Description collection[0]: Capture Timer value to CC[0] register */ - __I uint32_t RESERVED1[58]; - __IO uint32_t EVENTS_COMPARE[6]; /*!< Description collection[0]: Compare event on CC[0] match */ - __I uint32_t RESERVED2[42]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED3[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED4[126]; - __IO uint32_t MODE; /*!< Timer mode selection */ - __IO uint32_t BITMODE; /*!< Configure the number of bits used by the TIMER */ - __I uint32_t RESERVED5; - __IO uint32_t PRESCALER; /*!< Timer prescaler register */ - __I uint32_t RESERVED6[11]; - __IO uint32_t CC[6]; /*!< Description collection[0]: Capture/Compare register 0 */ -} NRF_TIMER_Type; - - -/* ================================================================================ */ -/* ================ RTC ================ */ -/* ================================================================================ */ - - -/** - * @brief Real time counter 0 (RTC) - */ - -typedef struct { /*!< RTC Structure */ - __O uint32_t TASKS_START; /*!< Start RTC COUNTER */ - __O uint32_t TASKS_STOP; /*!< Stop RTC COUNTER */ - __O uint32_t TASKS_CLEAR; /*!< Clear RTC COUNTER */ - __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFF0 */ - __I uint32_t RESERVED0[60]; - __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment */ - __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow */ - __I uint32_t RESERVED1[14]; - __IO uint32_t EVENTS_COMPARE[4]; /*!< Description collection[0]: Compare event on CC[0] match */ - __I uint32_t RESERVED2[109]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[13]; - __IO uint32_t EVTEN; /*!< Enable or disable event routing */ - __IO uint32_t EVTENSET; /*!< Enable event routing */ - __IO uint32_t EVTENCLR; /*!< Disable event routing */ - __I uint32_t RESERVED4[110]; - __I uint32_t COUNTER; /*!< Current COUNTER value */ - __IO uint32_t PRESCALER; /*!< 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must - be written when RTC is stopped */ - __I uint32_t RESERVED5[13]; - __IO uint32_t CC[4]; /*!< Description collection[0]: Compare register 0 */ -} NRF_RTC_Type; - - -/* ================================================================================ */ -/* ================ TEMP ================ */ -/* ================================================================================ */ - - -/** - * @brief Temperature Sensor (TEMP) - */ - -typedef struct { /*!< TEMP Structure */ - __O uint32_t TASKS_START; /*!< Start temperature measurement */ - __O uint32_t TASKS_STOP; /*!< Stop temperature measurement */ - __I uint32_t RESERVED0[62]; - __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready */ - __I uint32_t RESERVED1[128]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED2[127]; - __I int32_t TEMP; /*!< Temperature in degC (0.25deg steps) */ - __I uint32_t RESERVED3[5]; - __IO uint32_t A0; /*!< Slope of 1st piece wise linear function */ - __IO uint32_t A1; /*!< Slope of 2nd piece wise linear function */ - __IO uint32_t A2; /*!< Slope of 3rd piece wise linear function */ - __IO uint32_t A3; /*!< Slope of 4th piece wise linear function */ - __IO uint32_t A4; /*!< Slope of 5th piece wise linear function */ - __IO uint32_t A5; /*!< Slope of 6th piece wise linear function */ - __I uint32_t RESERVED4[2]; - __IO uint32_t B0; /*!< y-intercept of 1st piece wise linear function */ - __IO uint32_t B1; /*!< y-intercept of 2nd piece wise linear function */ - __IO uint32_t B2; /*!< y-intercept of 3rd piece wise linear function */ - __IO uint32_t B3; /*!< y-intercept of 4th piece wise linear function */ - __IO uint32_t B4; /*!< y-intercept of 5th piece wise linear function */ - __IO uint32_t B5; /*!< y-intercept of 6th piece wise linear function */ - __I uint32_t RESERVED5[2]; - __IO uint32_t T0; /*!< End point of 1st piece wise linear function */ - __IO uint32_t T1; /*!< End point of 2nd piece wise linear function */ - __IO uint32_t T2; /*!< End point of 3rd piece wise linear function */ - __IO uint32_t T3; /*!< End point of 4th piece wise linear function */ - __IO uint32_t T4; /*!< End point of 5th piece wise linear function */ -} NRF_TEMP_Type; - - -/* ================================================================================ */ -/* ================ RNG ================ */ -/* ================================================================================ */ - - -/** - * @brief Random Number Generator (RNG) - */ - -typedef struct { /*!< RNG Structure */ - __O uint32_t TASKS_START; /*!< Task starting the random number generator */ - __O uint32_t TASKS_STOP; /*!< Task stopping the random number generator */ - __I uint32_t RESERVED0[62]; - __IO uint32_t EVENTS_VALRDY; /*!< Event being generated for every new random number written to - the VALUE register */ - __I uint32_t RESERVED1[63]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED2[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[126]; - __IO uint32_t CONFIG; /*!< Configuration register */ - __I uint32_t VALUE; /*!< Output random number */ -} NRF_RNG_Type; - - -/* ================================================================================ */ -/* ================ ECB ================ */ -/* ================================================================================ */ - - -/** - * @brief AES ECB Mode Encryption (ECB) - */ - -typedef struct { /*!< ECB Structure */ - __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt */ - __O uint32_t TASKS_STOPECB; /*!< Abort a possible executing ECB operation */ - __I uint32_t RESERVED0[62]; - __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete */ - __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted because of a STOPECB task or due to - an error */ - __I uint32_t RESERVED1[127]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED2[126]; - __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointers */ -} NRF_ECB_Type; - - -/* ================================================================================ */ -/* ================ CCM ================ */ -/* ================================================================================ */ - - -/** - * @brief AES CCM Mode Encryption (CCM) - */ - -typedef struct { /*!< CCM Structure */ - __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by - itself when completed. */ - __O uint32_t TASKS_CRYPT; /*!< Start encryption/decryption. This operation will stop by itself - when completed. */ - __O uint32_t TASKS_STOP; /*!< Stop encryption/decryption */ - __I uint32_t RESERVED0[61]; - __IO uint32_t EVENTS_ENDKSGEN; /*!< Key-stream generation complete */ - __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt complete */ - __IO uint32_t EVENTS_ERROR; /*!< CCM error event */ - __I uint32_t RESERVED1[61]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED2[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[61]; - __I uint32_t MICSTATUS; /*!< MIC check result */ - __I uint32_t RESERVED4[63]; - __IO uint32_t ENABLE; /*!< Enable */ - __IO uint32_t MODE; /*!< Operation mode */ - __IO uint32_t CNFPTR; /*!< Pointer to data structure holding AES key and NONCE vector */ - __IO uint32_t INPTR; /*!< Input pointer */ - __IO uint32_t OUTPTR; /*!< Output pointer */ - __IO uint32_t SCRATCHPTR; /*!< Pointer to data area used for temporary storage */ -} NRF_CCM_Type; - - -/* ================================================================================ */ -/* ================ AAR ================ */ -/* ================================================================================ */ - - -/** - * @brief Accelerated Address Resolver (AAR) - */ - -typedef struct { /*!< AAR Structure */ - __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK - data structure */ - __I uint32_t RESERVED0; - __O uint32_t TASKS_STOP; /*!< Stop resolving addresses */ - __I uint32_t RESERVED1[61]; - __IO uint32_t EVENTS_END; /*!< Address resolution procedure complete */ - __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved */ - __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved */ - __I uint32_t RESERVED2[126]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[61]; - __I uint32_t STATUS; /*!< Resolution status */ - __I uint32_t RESERVED4[63]; - __IO uint32_t ENABLE; /*!< Enable AAR */ - __IO uint32_t NIRK; /*!< Number of IRKs */ - __IO uint32_t IRKPTR; /*!< Pointer to IRK data structure */ - __I uint32_t RESERVED5; - __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address */ - __IO uint32_t SCRATCHPTR; /*!< Pointer to data area used for temporary storage */ -} NRF_AAR_Type; - - -/* ================================================================================ */ -/* ================ WDT ================ */ -/* ================================================================================ */ - - -/** - * @brief Watchdog Timer (WDT) - */ - -typedef struct { /*!< WDT Structure */ - __O uint32_t TASKS_START; /*!< Start the watchdog */ - __I uint32_t RESERVED0[63]; - __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout */ - __I uint32_t RESERVED1[128]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED2[61]; - __I uint32_t RUNSTATUS; /*!< Run status */ - __I uint32_t REQSTATUS; /*!< Request status */ - __I uint32_t RESERVED3[63]; - __IO uint32_t CRV; /*!< Counter reload value */ - __IO uint32_t RREN; /*!< Enable register for reload request registers */ - __IO uint32_t CONFIG; /*!< Configuration register */ - __I uint32_t RESERVED4[60]; - __O uint32_t RR[8]; /*!< Description collection[0]: Reload request 0 */ -} NRF_WDT_Type; - - -/* ================================================================================ */ -/* ================ QDEC ================ */ -/* ================================================================================ */ - - -/** - * @brief Quadrature Decoder (QDEC) - */ - -typedef struct { /*!< QDEC Structure */ - __O uint32_t TASKS_START; /*!< Task starting the quadrature decoder */ - __O uint32_t TASKS_STOP; /*!< Task stopping the quadrature decoder */ - __O uint32_t TASKS_READCLRACC; /*!< Read and clear ACC and ACCDBL */ - __O uint32_t TASKS_RDCLRACC; /*!< Read and clear ACC */ - __O uint32_t TASKS_RDCLRDBL; /*!< Read and clear ACCDBL */ - __I uint32_t RESERVED0[59]; - __IO uint32_t EVENTS_SAMPLERDY; /*!< Event being generated for every new sample value written to - the SAMPLE register */ - __IO uint32_t EVENTS_REPORTRDY; /*!< Non-null report ready */ - __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow */ - __IO uint32_t EVENTS_DBLRDY; /*!< Double displacement(s) detected */ - __IO uint32_t EVENTS_STOPPED; /*!< QDEC has been stopped */ - __I uint32_t RESERVED1[59]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED2[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[125]; - __IO uint32_t ENABLE; /*!< Enable the quadrature decoder */ - __IO uint32_t LEDPOL; /*!< LED output pin polarity */ - __IO uint32_t SAMPLEPER; /*!< Sample period */ - __I int32_t SAMPLE; /*!< Motion sample value */ - __IO uint32_t REPORTPER; /*!< Number of samples to be taken before REPORTRDY and DBLRDY events - can be generated */ - __I int32_t ACC; /*!< Register accumulating the valid transitions */ - __I int32_t ACCREAD; /*!< Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC - task */ - QDEC_PSEL_Type PSEL; /*!< Unspecified */ - __IO uint32_t DBFEN; /*!< Enable input debounce filters */ - __I uint32_t RESERVED4[5]; - __IO uint32_t LEDPRE; /*!< Time period the LED is switched ON prior to sampling */ - __I uint32_t ACCDBL; /*!< Register accumulating the number of detected double transitions */ - __I uint32_t ACCDBLREAD; /*!< Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL - task */ -} NRF_QDEC_Type; - - -/* ================================================================================ */ -/* ================ COMP ================ */ -/* ================================================================================ */ - - -/** - * @brief Comparator (COMP) - */ - -typedef struct { /*!< COMP Structure */ - __O uint32_t TASKS_START; /*!< Start comparator */ - __O uint32_t TASKS_STOP; /*!< Stop comparator */ - __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value */ - __I uint32_t RESERVED0[61]; - __IO uint32_t EVENTS_READY; /*!< COMP is ready and output is valid */ - __IO uint32_t EVENTS_DOWN; /*!< Downward crossing */ - __IO uint32_t EVENTS_UP; /*!< Upward crossing */ - __IO uint32_t EVENTS_CROSS; /*!< Downward or upward crossing */ - __I uint32_t RESERVED1[60]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED2[63]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[61]; - __I uint32_t RESULT; /*!< Compare result */ - __I uint32_t RESERVED4[63]; - __IO uint32_t ENABLE; /*!< COMP enable */ - __IO uint32_t PSEL; /*!< Pin select */ - __IO uint32_t REFSEL; /*!< Reference source select for single-ended mode */ - __IO uint32_t EXTREFSEL; /*!< External reference select */ - __I uint32_t RESERVED5[8]; - __IO uint32_t TH; /*!< Threshold configuration for hysteresis unit */ - __IO uint32_t MODE; /*!< Mode configuration */ - __IO uint32_t HYST; /*!< Comparator hysteresis enable */ - __IO uint32_t ISOURCE; /*!< Current source select on analog input */ -} NRF_COMP_Type; - - -/* ================================================================================ */ -/* ================ LPCOMP ================ */ -/* ================================================================================ */ - - -/** - * @brief Low Power Comparator (LPCOMP) - */ - -typedef struct { /*!< LPCOMP Structure */ - __O uint32_t TASKS_START; /*!< Start comparator */ - __O uint32_t TASKS_STOP; /*!< Stop comparator */ - __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value */ - __I uint32_t RESERVED0[61]; - __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid */ - __IO uint32_t EVENTS_DOWN; /*!< Downward crossing */ - __IO uint32_t EVENTS_UP; /*!< Upward crossing */ - __IO uint32_t EVENTS_CROSS; /*!< Downward or upward crossing */ - __I uint32_t RESERVED1[60]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED2[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[61]; - __I uint32_t RESULT; /*!< Compare result */ - __I uint32_t RESERVED4[63]; - __IO uint32_t ENABLE; /*!< Enable LPCOMP */ - __IO uint32_t PSEL; /*!< Input pin select */ - __IO uint32_t REFSEL; /*!< Reference select */ - __IO uint32_t EXTREFSEL; /*!< External reference select */ - __I uint32_t RESERVED5[4]; - __IO uint32_t ANADETECT; /*!< Analog detect configuration */ - __I uint32_t RESERVED6[5]; - __IO uint32_t HYST; /*!< Comparator hysteresis enable */ -} NRF_LPCOMP_Type; - - -/* ================================================================================ */ -/* ================ SWI ================ */ -/* ================================================================================ */ - - -/** - * @brief Software interrupt 0 (SWI) - */ - -typedef struct { /*!< SWI Structure */ - __I uint32_t UNUSED; /*!< Unused. */ -} NRF_SWI_Type; - - -/* ================================================================================ */ -/* ================ EGU ================ */ -/* ================================================================================ */ - - -/** - * @brief Event Generator Unit 0 (EGU) - */ - -typedef struct { /*!< EGU Structure */ - __O uint32_t TASKS_TRIGGER[16]; /*!< Description collection[0]: Trigger 0 for triggering the corresponding - TRIGGERED[0] event */ - __I uint32_t RESERVED0[48]; - __IO uint32_t EVENTS_TRIGGERED[16]; /*!< Description collection[0]: Event number 0 generated by triggering - the corresponding TRIGGER[0] task */ - __I uint32_t RESERVED1[112]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ -} NRF_EGU_Type; - - -/* ================================================================================ */ -/* ================ PWM ================ */ -/* ================================================================================ */ - - -/** - * @brief Pulse Width Modulation Unit 0 (PWM) - */ - -typedef struct { /*!< PWM Structure */ - __I uint32_t RESERVED0; - __O uint32_t TASKS_STOP; /*!< Stops PWM pulse generation on all channels at the end of current - PWM period, and stops sequence playback */ - __O uint32_t TASKS_SEQSTART[2]; /*!< Description collection[0]: Loads the first PWM value on all - enabled channels from sequence 0, and starts playing that sequence - at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes - PWM generation to start it was not running. */ - __O uint32_t TASKS_NEXTSTEP; /*!< Steps by one value in the current sequence on all enabled channels - if DECODER.MODE=NextStep. Does not cause PWM generation to start - it was not running. */ - __I uint32_t RESERVED1[60]; - __IO uint32_t EVENTS_STOPPED; /*!< Response to STOP task, emitted when PWM pulses are no longer - generated */ - __IO uint32_t EVENTS_SEQSTARTED[2]; /*!< Description collection[0]: First PWM period started on sequence - 0 */ - __IO uint32_t EVENTS_SEQEND[2]; /*!< Description collection[0]: Emitted at end of every sequence - 0, when last value from RAM has been applied to wave counter */ - __IO uint32_t EVENTS_PWMPERIODEND; /*!< Emitted at the end of each PWM period */ - __IO uint32_t EVENTS_LOOPSDONE; /*!< Concatenated sequences have been played the amount of times - defined in LOOP.CNT */ - __I uint32_t RESERVED2[56]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED3[63]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED4[125]; - __IO uint32_t ENABLE; /*!< PWM module enable register */ - __IO uint32_t MODE; /*!< Selects operating mode of the wave counter */ - __IO uint32_t COUNTERTOP; /*!< Value up to which the pulse generator counter counts */ - __IO uint32_t PRESCALER; /*!< Configuration for PWM_CLK */ - __IO uint32_t DECODER; /*!< Configuration of the decoder */ - __IO uint32_t LOOP; /*!< Amount of playback of a loop */ - __I uint32_t RESERVED5[2]; - PWM_SEQ_Type SEQ[2]; /*!< Unspecified */ - PWM_PSEL_Type PSEL; /*!< Unspecified */ -} NRF_PWM_Type; - - -/* ================================================================================ */ -/* ================ PDM ================ */ -/* ================================================================================ */ - - -/** - * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) - */ - -typedef struct { /*!< PDM Structure */ - __O uint32_t TASKS_START; /*!< Starts continuous PDM transfer */ - __O uint32_t TASKS_STOP; /*!< Stops PDM transfer */ - __I uint32_t RESERVED0[62]; - __IO uint32_t EVENTS_STARTED; /*!< PDM transfer has started */ - __IO uint32_t EVENTS_STOPPED; /*!< PDM transfer has finished */ - __IO uint32_t EVENTS_END; /*!< The PDM has written the last sample specified by SAMPLE.MAXCNT - (or the last sample after a STOP task has been received) to - Data RAM */ - __I uint32_t RESERVED1[125]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED2[125]; - __IO uint32_t ENABLE; /*!< PDM module enable register */ - __IO uint32_t PDMCLKCTRL; /*!< PDM clock generator control */ - __IO uint32_t MODE; /*!< Defines the routing of the connected PDM microphones' signals */ - __I uint32_t RESERVED3[3]; - __IO uint32_t GAINL; /*!< Left output gain adjustment */ - __IO uint32_t GAINR; /*!< Right output gain adjustment */ - __I uint32_t RESERVED4[8]; - PDM_PSEL_Type PSEL; /*!< Unspecified */ - __I uint32_t RESERVED5[6]; - PDM_SAMPLE_Type SAMPLE; /*!< Unspecified */ -} NRF_PDM_Type; - - -/* ================================================================================ */ -/* ================ NVMC ================ */ -/* ================================================================================ */ - - -/** - * @brief Non Volatile Memory Controller (NVMC) - */ - -typedef struct { /*!< NVMC Structure */ - __I uint32_t RESERVED0[256]; - __I uint32_t READY; /*!< Ready flag */ - __I uint32_t RESERVED1[64]; - __IO uint32_t CONFIG; /*!< Configuration register */ - - union { - __IO uint32_t ERASEPCR1; /*!< Deprecated register - Register for erasing a page in Code area. - Equivalent to ERASEPAGE. */ - __IO uint32_t ERASEPAGE; /*!< Register for erasing a page in Code area */ - }; - __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory */ - __IO uint32_t ERASEPCR0; /*!< Deprecated register - Register for erasing a page in Code area. - Equivalent to ERASEPAGE. */ - __IO uint32_t ERASEUICR; /*!< Register for erasing User Information Configuration Registers */ - __I uint32_t RESERVED2[10]; - __IO uint32_t ICACHECNF; /*!< I-Code cache configuration register. */ - __I uint32_t RESERVED3; - __IO uint32_t IHIT; /*!< I-Code cache hit counter. */ - __IO uint32_t IMISS; /*!< I-Code cache miss counter. */ -} NRF_NVMC_Type; - - -/* ================================================================================ */ -/* ================ PPI ================ */ -/* ================================================================================ */ - - -/** - * @brief Programmable Peripheral Interconnect (PPI) - */ - -typedef struct { /*!< PPI Structure */ - PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< Channel group tasks */ - __I uint32_t RESERVED0[308]; - __IO uint32_t CHEN; /*!< Channel enable register */ - __IO uint32_t CHENSET; /*!< Channel enable set register */ - __IO uint32_t CHENCLR; /*!< Channel enable clear register */ - __I uint32_t RESERVED1; - PPI_CH_Type CH[20]; /*!< PPI Channel */ - __I uint32_t RESERVED2[148]; - __IO uint32_t CHG[6]; /*!< Description collection[0]: Channel group 0 */ - __I uint32_t RESERVED3[62]; - PPI_FORK_Type FORK[32]; /*!< Fork */ -} NRF_PPI_Type; - - -/* ================================================================================ */ -/* ================ MWU ================ */ -/* ================================================================================ */ - - -/** - * @brief Memory Watch Unit (MWU) - */ - -typedef struct { /*!< MWU Structure */ - __I uint32_t RESERVED0[64]; - MWU_EVENTS_REGION_Type EVENTS_REGION[4]; /*!< Unspecified */ - __I uint32_t RESERVED1[16]; - MWU_EVENTS_PREGION_Type EVENTS_PREGION[2]; /*!< Unspecified */ - __I uint32_t RESERVED2[100]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[5]; - __IO uint32_t NMIEN; /*!< Enable or disable non-maskable interrupt */ - __IO uint32_t NMIENSET; /*!< Enable non-maskable interrupt */ - __IO uint32_t NMIENCLR; /*!< Disable non-maskable interrupt */ - __I uint32_t RESERVED4[53]; - MWU_PERREGION_Type PERREGION[2]; /*!< Unspecified */ - __I uint32_t RESERVED5[64]; - __IO uint32_t REGIONEN; /*!< Enable/disable regions watch */ - __IO uint32_t REGIONENSET; /*!< Enable regions watch */ - __IO uint32_t REGIONENCLR; /*!< Disable regions watch */ - __I uint32_t RESERVED6[57]; - MWU_REGION_Type REGION[4]; /*!< Unspecified */ - __I uint32_t RESERVED7[32]; - MWU_PREGION_Type PREGION[2]; /*!< Unspecified */ -} NRF_MWU_Type; - - -/* ================================================================================ */ -/* ================ I2S ================ */ -/* ================================================================================ */ - - -/** - * @brief Inter-IC Sound (I2S) - */ - -typedef struct { /*!< I2S Structure */ - __O uint32_t TASKS_START; /*!< Starts continuous I2S transfer. Also starts MCK generator when - this is enabled. */ - __O uint32_t TASKS_STOP; /*!< Stops I2S transfer. Also stops MCK generator. Triggering this - task will cause the {event:STOPPED} event to be generated. */ - __I uint32_t RESERVED0[63]; - __IO uint32_t EVENTS_RXPTRUPD; /*!< The RXD.PTR register has been copied to internal double-buffers. - When the I2S module is started and RX is enabled, this event - will be generated for every RXTXD.MAXCNT words that are received - on the SDIN pin. */ - __IO uint32_t EVENTS_STOPPED; /*!< I2S transfer stopped. */ - __I uint32_t RESERVED1[2]; - __IO uint32_t EVENTS_TXPTRUPD; /*!< The TDX.PTR register has been copied to internal double-buffers. - When the I2S module is started and TX is enabled, this event - will be generated for every RXTXD.MAXCNT words that are sent - on the SDOUT pin. */ - __I uint32_t RESERVED2[122]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[125]; - __IO uint32_t ENABLE; /*!< Enable I2S module. */ - I2S_CONFIG_Type CONFIG; /*!< Unspecified */ - __I uint32_t RESERVED4[3]; - I2S_RXD_Type RXD; /*!< Unspecified */ - __I uint32_t RESERVED5; - I2S_TXD_Type TXD; /*!< Unspecified */ - __I uint32_t RESERVED6[3]; - I2S_RXTXD_Type RXTXD; /*!< Unspecified */ - __I uint32_t RESERVED7[3]; - I2S_PSEL_Type PSEL; /*!< Unspecified */ -} NRF_I2S_Type; - - -/* ================================================================================ */ -/* ================ FPU ================ */ -/* ================================================================================ */ - - -/** - * @brief FPU (FPU) - */ - -typedef struct { /*!< FPU Structure */ - __I uint32_t UNUSED; /*!< Unused. */ -} NRF_FPU_Type; - - -/* ================================================================================ */ -/* ================ GPIO ================ */ -/* ================================================================================ */ - - -/** - * @brief GPIO Port 1 (GPIO) - */ - -typedef struct { /*!< GPIO Structure */ - __I uint32_t RESERVED0[321]; - __IO uint32_t OUT; /*!< Write GPIO port */ - __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port */ - __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port */ - __I uint32_t IN; /*!< Read GPIO port */ - __IO uint32_t DIR; /*!< Direction of GPIO pins */ - __IO uint32_t DIRSET; /*!< DIR set register */ - __IO uint32_t DIRCLR; /*!< DIR clear register */ - __IO uint32_t LATCH; /*!< Latch register indicating what GPIO pins that have met the criteria - set in the PIN_CNF[n].SENSE registers */ - __IO uint32_t DETECTMODE; /*!< Select between default DETECT signal behaviour and LDETECT mode */ - __I uint32_t RESERVED1[118]; - __IO uint32_t PIN_CNF[32]; /*!< Description collection[0]: Configuration of GPIO pins */ -} NRF_GPIO_Type; - - -/* -------------------- End of section using anonymous unions ------------------- */ -#if defined(__CC_ARM) - #pragma pop -#elif defined(__ICCARM__) - /* leave anonymous unions enabled */ -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning restore -#else - #warning Not supported compiler type -#endif - - - - -/* ================================================================================ */ -/* ================ Peripheral memory map ================ */ -/* ================================================================================ */ - -#define NRF_FICR_BASE 0x10000000UL -#define NRF_UICR_BASE 0x10001000UL -#define NRF_BPROT_BASE 0x40000000UL -#define NRF_POWER_BASE 0x40000000UL -#define NRF_CLOCK_BASE 0x40000000UL -#define NRF_RADIO_BASE 0x40001000UL -#define NRF_UARTE0_BASE 0x40002000UL -#define NRF_UART0_BASE 0x40002000UL -#define NRF_SPIM0_BASE 0x40003000UL -#define NRF_SPIS0_BASE 0x40003000UL -#define NRF_TWIM0_BASE 0x40003000UL -#define NRF_TWIS0_BASE 0x40003000UL -#define NRF_SPI0_BASE 0x40003000UL -#define NRF_TWI0_BASE 0x40003000UL -#define NRF_SPIM1_BASE 0x40004000UL -#define NRF_SPIS1_BASE 0x40004000UL -#define NRF_TWIM1_BASE 0x40004000UL -#define NRF_TWIS1_BASE 0x40004000UL -#define NRF_SPI1_BASE 0x40004000UL -#define NRF_TWI1_BASE 0x40004000UL -#define NRF_NFCT_BASE 0x40005000UL -#define NRF_GPIOTE_BASE 0x40006000UL -#define NRF_SAADC_BASE 0x40007000UL -#define NRF_TIMER0_BASE 0x40008000UL -#define NRF_TIMER1_BASE 0x40009000UL -#define NRF_TIMER2_BASE 0x4000A000UL -#define NRF_RTC0_BASE 0x4000B000UL -#define NRF_TEMP_BASE 0x4000C000UL -#define NRF_RNG_BASE 0x4000D000UL -#define NRF_ECB_BASE 0x4000E000UL -#define NRF_CCM_BASE 0x4000F000UL -#define NRF_AAR_BASE 0x4000F000UL -#define NRF_WDT_BASE 0x40010000UL -#define NRF_RTC1_BASE 0x40011000UL -#define NRF_QDEC_BASE 0x40012000UL -#define NRF_COMP_BASE 0x40013000UL -#define NRF_LPCOMP_BASE 0x40013000UL -#define NRF_SWI0_BASE 0x40014000UL -#define NRF_EGU0_BASE 0x40014000UL -#define NRF_SWI1_BASE 0x40015000UL -#define NRF_EGU1_BASE 0x40015000UL -#define NRF_SWI2_BASE 0x40016000UL -#define NRF_EGU2_BASE 0x40016000UL -#define NRF_SWI3_BASE 0x40017000UL -#define NRF_EGU3_BASE 0x40017000UL -#define NRF_SWI4_BASE 0x40018000UL -#define NRF_EGU4_BASE 0x40018000UL -#define NRF_SWI5_BASE 0x40019000UL -#define NRF_EGU5_BASE 0x40019000UL -#define NRF_TIMER3_BASE 0x4001A000UL -#define NRF_TIMER4_BASE 0x4001B000UL -#define NRF_PWM0_BASE 0x4001C000UL -#define NRF_PDM_BASE 0x4001D000UL -#define NRF_NVMC_BASE 0x4001E000UL -#define NRF_PPI_BASE 0x4001F000UL -#define NRF_MWU_BASE 0x40020000UL -#define NRF_PWM1_BASE 0x40021000UL -#define NRF_PWM2_BASE 0x40022000UL -#define NRF_SPIM2_BASE 0x40023000UL -#define NRF_SPIS2_BASE 0x40023000UL -#define NRF_SPI2_BASE 0x40023000UL -#define NRF_RTC2_BASE 0x40024000UL -#define NRF_I2S_BASE 0x40025000UL -#define NRF_FPU_BASE 0x40026000UL -#define NRF_P0_BASE 0x50000000UL - - -/* ================================================================================ */ -/* ================ Peripheral declaration ================ */ -/* ================================================================================ */ - -#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE) -#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE) -#define NRF_BPROT ((NRF_BPROT_Type *) NRF_BPROT_BASE) -#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE) -#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE) -#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE) -#define NRF_UARTE0 ((NRF_UARTE_Type *) NRF_UARTE0_BASE) -#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE) -#define NRF_SPIM0 ((NRF_SPIM_Type *) NRF_SPIM0_BASE) -#define NRF_SPIS0 ((NRF_SPIS_Type *) NRF_SPIS0_BASE) -#define NRF_TWIM0 ((NRF_TWIM_Type *) NRF_TWIM0_BASE) -#define NRF_TWIS0 ((NRF_TWIS_Type *) NRF_TWIS0_BASE) -#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE) -#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE) -#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE) -#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE) -#define NRF_TWIM1 ((NRF_TWIM_Type *) NRF_TWIM1_BASE) -#define NRF_TWIS1 ((NRF_TWIS_Type *) NRF_TWIS1_BASE) -#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE) -#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE) -#define NRF_NFCT ((NRF_NFCT_Type *) NRF_NFCT_BASE) -#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE) -#define NRF_SAADC ((NRF_SAADC_Type *) NRF_SAADC_BASE) -#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE) -#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE) -#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE) -#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE) -#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE) -#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE) -#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE) -#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE) -#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE) -#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE) -#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE) -#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE) -#define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE) -#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE) -#define NRF_SWI0 ((NRF_SWI_Type *) NRF_SWI0_BASE) -#define NRF_EGU0 ((NRF_EGU_Type *) NRF_EGU0_BASE) -#define NRF_SWI1 ((NRF_SWI_Type *) NRF_SWI1_BASE) -#define NRF_EGU1 ((NRF_EGU_Type *) NRF_EGU1_BASE) -#define NRF_SWI2 ((NRF_SWI_Type *) NRF_SWI2_BASE) -#define NRF_EGU2 ((NRF_EGU_Type *) NRF_EGU2_BASE) -#define NRF_SWI3 ((NRF_SWI_Type *) NRF_SWI3_BASE) -#define NRF_EGU3 ((NRF_EGU_Type *) NRF_EGU3_BASE) -#define NRF_SWI4 ((NRF_SWI_Type *) NRF_SWI4_BASE) -#define NRF_EGU4 ((NRF_EGU_Type *) NRF_EGU4_BASE) -#define NRF_SWI5 ((NRF_SWI_Type *) NRF_SWI5_BASE) -#define NRF_EGU5 ((NRF_EGU_Type *) NRF_EGU5_BASE) -#define NRF_TIMER3 ((NRF_TIMER_Type *) NRF_TIMER3_BASE) -#define NRF_TIMER4 ((NRF_TIMER_Type *) NRF_TIMER4_BASE) -#define NRF_PWM0 ((NRF_PWM_Type *) NRF_PWM0_BASE) -#define NRF_PDM ((NRF_PDM_Type *) NRF_PDM_BASE) -#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE) -#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE) -#define NRF_MWU ((NRF_MWU_Type *) NRF_MWU_BASE) -#define NRF_PWM1 ((NRF_PWM_Type *) NRF_PWM1_BASE) -#define NRF_PWM2 ((NRF_PWM_Type *) NRF_PWM2_BASE) -#define NRF_SPIM2 ((NRF_SPIM_Type *) NRF_SPIM2_BASE) -#define NRF_SPIS2 ((NRF_SPIS_Type *) NRF_SPIS2_BASE) -#define NRF_SPI2 ((NRF_SPI_Type *) NRF_SPI2_BASE) -#define NRF_RTC2 ((NRF_RTC_Type *) NRF_RTC2_BASE) -#define NRF_I2S ((NRF_I2S_Type *) NRF_I2S_BASE) -#define NRF_FPU ((NRF_FPU_Type *) NRF_FPU_BASE) -#define NRF_P0 ((NRF_GPIO_Type *) NRF_P0_BASE) - - -/** @} */ /* End of group Device_Peripheral_Registers */ -/** @} */ /* End of group nrf52 */ -/** @} */ /* End of group Nordic Semiconductor */ - -#ifdef __cplusplus -} -#endif - - -#endif /* nrf52_H */ - diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52840.h b/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52840.h deleted file mode 100644 index d66bb77ae9..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52840.h +++ /dev/null @@ -1,2488 +0,0 @@ - -/****************************************************************************************************//** - * @file nrf52840.h - * - * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for - * nrf52840 from Nordic Semiconductor. - * - * @version V1 - * @date 8. March 2018 - * - * @note Generated with SVDConv V2.81d - * from CMSIS SVD File 'nrf52840.svd' Version 1, - * - * @par Copyright (c) 2010 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - *******************************************************************************************************/ - - - -/** @addtogroup Nordic Semiconductor - * @{ - */ - -/** @addtogroup nrf52840 - * @{ - */ - -#ifndef NRF52840_H -#define NRF52840_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum { -/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */ - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation - and No Match */ - BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory - related Fault */ - UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ - PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ - SysTick_IRQn = -1, /*!< 15 System Tick Timer */ -/* --------------------- nrf52840 Specific Interrupt Numbers -------------------- */ - POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ - RADIO_IRQn = 1, /*!< 1 RADIO */ - UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ - SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ - NFCT_IRQn = 5, /*!< 5 NFCT */ - GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ - SAADC_IRQn = 7, /*!< 7 SAADC */ - TIMER0_IRQn = 8, /*!< 8 TIMER0 */ - TIMER1_IRQn = 9, /*!< 9 TIMER1 */ - TIMER2_IRQn = 10, /*!< 10 TIMER2 */ - RTC0_IRQn = 11, /*!< 11 RTC0 */ - TEMP_IRQn = 12, /*!< 12 TEMP */ - RNG_IRQn = 13, /*!< 13 RNG */ - ECB_IRQn = 14, /*!< 14 ECB */ - CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ - WDT_IRQn = 16, /*!< 16 WDT */ - RTC1_IRQn = 17, /*!< 17 RTC1 */ - QDEC_IRQn = 18, /*!< 18 QDEC */ - COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */ - SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ - SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ - SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ - SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ - SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ - SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ - TIMER3_IRQn = 26, /*!< 26 TIMER3 */ - TIMER4_IRQn = 27, /*!< 27 TIMER4 */ - PWM0_IRQn = 28, /*!< 28 PWM0 */ - PDM_IRQn = 29, /*!< 29 PDM */ - MWU_IRQn = 32, /*!< 32 MWU */ - PWM1_IRQn = 33, /*!< 33 PWM1 */ - PWM2_IRQn = 34, /*!< 34 PWM2 */ - SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */ - RTC2_IRQn = 36, /*!< 36 RTC2 */ - I2S_IRQn = 37, /*!< 37 I2S */ - FPU_IRQn = 38, /*!< 38 FPU */ - USBD_IRQn = 39, /*!< 39 USBD */ - UARTE1_IRQn = 40, /*!< 40 UARTE1 */ - QSPI_IRQn = 41, /*!< 41 QSPI */ - CRYPTOCELL_IRQn = 42, /*!< 42 CRYPTOCELL */ - PWM3_IRQn = 45, /*!< 45 PWM3 */ - SPIM3_IRQn = 47 /*!< 47 SPIM3 */ -} IRQn_Type; - - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */ -#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ -#include "system_nrf52840.h" /*!< nrf52840 System */ - - -/* ================================================================================ */ -/* ================ Device Specific Peripheral Section ================ */ -/* ================================================================================ */ - - -/** @addtogroup Device_Peripheral_Registers - * @{ - */ - - -/* ------------------- Start of section using anonymous unions ------------------ */ -#if defined(__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined(__ICCARM__) - #pragma language=extended -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) -/* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning 586 -#else - #warning Not supported compiler type -#endif - - -typedef struct { - __I uint32_t PART; /*!< Part code */ - __I uint32_t VARIANT; /*!< Build code (hardware version and production configuration) */ - __I uint32_t PACKAGE; /*!< Package option */ - __I uint32_t RAM; /*!< RAM variant */ - __I uint32_t FLASH; /*!< Flash variant */ - __IO uint32_t UNUSED8[3]; /*!< Unspecified */ -} FICR_INFO_Type; - -typedef struct { - __I uint32_t A0; /*!< Slope definition A0 */ - __I uint32_t A1; /*!< Slope definition A1 */ - __I uint32_t A2; /*!< Slope definition A2 */ - __I uint32_t A3; /*!< Slope definition A3 */ - __I uint32_t A4; /*!< Slope definition A4 */ - __I uint32_t A5; /*!< Slope definition A5 */ - __I uint32_t B0; /*!< Y-intercept B0 */ - __I uint32_t B1; /*!< Y-intercept B1 */ - __I uint32_t B2; /*!< Y-intercept B2 */ - __I uint32_t B3; /*!< Y-intercept B3 */ - __I uint32_t B4; /*!< Y-intercept B4 */ - __I uint32_t B5; /*!< Y-intercept B5 */ - __I uint32_t T0; /*!< Segment end T0 */ - __I uint32_t T1; /*!< Segment end T1 */ - __I uint32_t T2; /*!< Segment end T2 */ - __I uint32_t T3; /*!< Segment end T3 */ - __I uint32_t T4; /*!< Segment end T4 */ -} FICR_TEMP_Type; - -typedef struct { - __I uint32_t TAGHEADER0; /*!< Default header for NFC tag. Software can read these values to - populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ - __I uint32_t TAGHEADER1; /*!< Default header for NFC tag. Software can read these values to - populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ - __I uint32_t TAGHEADER2; /*!< Default header for NFC tag. Software can read these values to - populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ - __I uint32_t TAGHEADER3; /*!< Default header for NFC tag. Software can read these values to - populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ -} FICR_NFC_Type; - -typedef struct { - __I uint32_t BYTES; /*!< Amount of bytes for the required entropy bits */ - __I uint32_t RCCUTOFF; /*!< Repetition counter cutoff */ - __I uint32_t APCUTOFF; /*!< Adaptive proportion cutoff */ - __I uint32_t STARTUP; /*!< Amount of bytes for the startup tests */ - __I uint32_t ROSC1; /*!< Sample count for ring oscillator 1 */ - __I uint32_t ROSC2; /*!< Sample count for ring oscillator 2 */ - __I uint32_t ROSC3; /*!< Sample count for ring oscillator 3 */ - __I uint32_t ROSC4; /*!< Sample count for ring oscillator 4 */ -} FICR_TRNG90B_Type; - -typedef struct { - __IO uint32_t POWER; /*!< Description cluster[n]: RAMn power control register */ - __O uint32_t POWERSET; /*!< Description cluster[n]: RAMn power control set register */ - __O uint32_t POWERCLR; /*!< Description cluster[n]: RAMn power control clear register */ - __I uint32_t RESERVED0; -} POWER_RAM_Type; - -typedef struct { - __IO uint32_t RTS; /*!< Pin select for RTS */ - __IO uint32_t TXD; /*!< Pin select for TXD */ - __IO uint32_t CTS; /*!< Pin select for CTS */ - __IO uint32_t RXD; /*!< Pin select for RXD */ -} UART_PSEL_Type; - -typedef struct { - __IO uint32_t RTS; /*!< Pin select for RTS signal */ - __IO uint32_t TXD; /*!< Pin select for TXD signal */ - __IO uint32_t CTS; /*!< Pin select for CTS signal */ - __IO uint32_t RXD; /*!< Pin select for RXD signal */ -} UARTE_PSEL_Type; - -typedef struct { - __IO uint32_t PTR; /*!< Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ -} UARTE_RXD_Type; - -typedef struct { - __IO uint32_t PTR; /*!< Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ -} UARTE_TXD_Type; - -typedef struct { - __IO uint32_t SCK; /*!< Pin select for SCK */ - __IO uint32_t MOSI; /*!< Pin select for MOSI signal */ - __IO uint32_t MISO; /*!< Pin select for MISO signal */ -} SPI_PSEL_Type; - -typedef struct { - __IO uint32_t SCK; /*!< Pin select for SCK */ - __IO uint32_t MOSI; /*!< Pin select for MOSI signal */ - __IO uint32_t MISO; /*!< Pin select for MISO signal */ - __IO uint32_t CSN; /*!< Pin select for CSN */ -} SPIM_PSEL_Type; - -typedef struct { - __IO uint32_t PTR; /*!< Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ - __IO uint32_t LIST; /*!< EasyDMA list type */ -} SPIM_RXD_Type; - -typedef struct { - __IO uint32_t PTR; /*!< Data pointer */ - __IO uint32_t MAXCNT; /*!< Number of bytes in transmit buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ - __IO uint32_t LIST; /*!< EasyDMA list type */ -} SPIM_TXD_Type; - -typedef struct { - __IO uint32_t RXDELAY; /*!< Sample delay for input serial data on MISO */ - __IO uint32_t CSNDUR; /*!< Minimum duration between edge of CSN and edge of SCK and minimum - duration CSN must stay high between transactions */ -} SPIM_IFTIMING_Type; - -typedef struct { - __IO uint32_t SCK; /*!< Pin select for SCK */ - __IO uint32_t MISO; /*!< Pin select for MISO signal */ - __IO uint32_t MOSI; /*!< Pin select for MOSI signal */ - __IO uint32_t CSN; /*!< Pin select for CSN signal */ -} SPIS_PSEL_Type; - -typedef struct { - __IO uint32_t PTR; /*!< RXD data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes received in last granted transaction */ -} SPIS_RXD_Type; - -typedef struct { - __IO uint32_t PTR; /*!< TXD data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes transmitted in last granted transaction */ -} SPIS_TXD_Type; - -typedef struct { - __IO uint32_t SCL; /*!< Pin select for SCL */ - __IO uint32_t SDA; /*!< Pin select for SDA */ -} TWI_PSEL_Type; - -typedef struct { - __IO uint32_t SCL; /*!< Pin select for SCL signal */ - __IO uint32_t SDA; /*!< Pin select for SDA signal */ -} TWIM_PSEL_Type; - -typedef struct { - __IO uint32_t PTR; /*!< Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ - __IO uint32_t LIST; /*!< EasyDMA list type */ -} TWIM_RXD_Type; - -typedef struct { - __IO uint32_t PTR; /*!< Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ - __IO uint32_t LIST; /*!< EasyDMA list type */ -} TWIM_TXD_Type; - -typedef struct { - __IO uint32_t SCL; /*!< Pin select for SCL signal */ - __IO uint32_t SDA; /*!< Pin select for SDA signal */ -} TWIS_PSEL_Type; - -typedef struct { - __IO uint32_t PTR; /*!< RXD Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in RXD buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last RXD transaction */ -} TWIS_RXD_Type; - -typedef struct { - __IO uint32_t PTR; /*!< TXD Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in TXD buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last TXD transaction */ -} TWIS_TXD_Type; - -typedef struct { - __IO uint32_t RX; /*!< Result of last incoming frame */ -} NFCT_FRAMESTATUS_Type; - -typedef struct { - __IO uint32_t FRAMECONFIG; /*!< Configuration of outgoing frames */ - __IO uint32_t AMOUNT; /*!< Size of outgoing frame */ -} NFCT_TXD_Type; - -typedef struct { - __IO uint32_t FRAMECONFIG; /*!< Configuration of incoming frames */ - __I uint32_t AMOUNT; /*!< Size of last incoming frame */ -} NFCT_RXD_Type; - -typedef struct { - __IO uint32_t LIMITH; /*!< Description cluster[n]: Last result is equal or above CH[n].LIMIT.HIGH */ - __IO uint32_t LIMITL; /*!< Description cluster[n]: Last result is equal or below CH[n].LIMIT.LOW */ -} SAADC_EVENTS_CH_Type; - -typedef struct { - __IO uint32_t PSELP; /*!< Description cluster[n]: Input positive pin selection for CH[n] */ - __IO uint32_t PSELN; /*!< Description cluster[n]: Input negative pin selection for CH[n] */ - __IO uint32_t CONFIG; /*!< Description cluster[n]: Input configuration for CH[n] */ - __IO uint32_t LIMIT; /*!< Description cluster[n]: High/low limits for event monitoring - of a channel */ -} SAADC_CH_Type; - -typedef struct { - __IO uint32_t PTR; /*!< Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of 16-bit samples to be written to output RAM - buffer */ - __I uint32_t AMOUNT; /*!< Number of 16-bit samples written to output RAM buffer since - the previous START task */ -} SAADC_RESULT_Type; - -typedef struct { - __IO uint32_t LED; /*!< Pin select for LED signal */ - __IO uint32_t A; /*!< Pin select for A signal */ - __IO uint32_t B; /*!< Pin select for B signal */ -} QDEC_PSEL_Type; - -typedef struct { - __IO uint32_t PTR; /*!< Description cluster[n]: Beginning address in RAM of this sequence */ - __IO uint32_t CNT; /*!< Description cluster[n]: Number of values (duty cycles) in this - sequence */ - __IO uint32_t REFRESH; /*!< Description cluster[n]: Number of additional PWM periods between - samples loaded into compare register */ - __IO uint32_t ENDDELAY; /*!< Description cluster[n]: Time added after the sequence */ - __I uint32_t RESERVED1[4]; -} PWM_SEQ_Type; - -typedef struct { - __IO uint32_t OUT[4]; /*!< Description collection[n]: Output pin select for PWM channel - n */ -} PWM_PSEL_Type; - -typedef struct { - __IO uint32_t CLK; /*!< Pin number configuration for PDM CLK signal */ - __IO uint32_t DIN; /*!< Pin number configuration for PDM DIN signal */ -} PDM_PSEL_Type; - -typedef struct { - __IO uint32_t PTR; /*!< RAM address pointer to write samples to with EasyDMA */ - __IO uint32_t MAXCNT; /*!< Number of samples to allocate memory for in EasyDMA mode */ -} PDM_SAMPLE_Type; - -typedef struct { - __IO uint32_t ADDR; /*!< Description cluster[n]: Configure the word-aligned start address - of region n to protect */ - __IO uint32_t SIZE; /*!< Description cluster[n]: Size of region to protect counting from - address ACL[n].ADDR. Write '0' as no effect. */ - __IO uint32_t PERM; /*!< Description cluster[n]: Access permissions for region n as defined - by start address ACL[n].ADDR and size ACL[n].SIZE */ - __IO uint32_t UNUSED0; /*!< Unspecified */ -} ACL_ACL_Type; - -typedef struct { - __O uint32_t EN; /*!< Description cluster[n]: Enable channel group n */ - __O uint32_t DIS; /*!< Description cluster[n]: Disable channel group n */ -} PPI_TASKS_CHG_Type; - -typedef struct { - __IO uint32_t EEP; /*!< Description cluster[n]: Channel n event end-point */ - __IO uint32_t TEP; /*!< Description cluster[n]: Channel n task end-point */ -} PPI_CH_Type; - -typedef struct { - __IO uint32_t TEP; /*!< Description cluster[n]: Channel n task end-point */ -} PPI_FORK_Type; - -typedef struct { - __IO uint32_t WA; /*!< Description cluster[n]: Write access to region n detected */ - __IO uint32_t RA; /*!< Description cluster[n]: Read access to region n detected */ -} MWU_EVENTS_REGION_Type; - -typedef struct { - __IO uint32_t WA; /*!< Description cluster[n]: Write access to peripheral region n - detected */ - __IO uint32_t RA; /*!< Description cluster[n]: Read access to peripheral region n detected */ -} MWU_EVENTS_PREGION_Type; - -typedef struct { - __IO uint32_t SUBSTATWA; /*!< Description cluster[n]: Source of event/interrupt in region - n, write access detected while corresponding subregion was enabled - for watching */ - __IO uint32_t SUBSTATRA; /*!< Description cluster[n]: Source of event/interrupt in region - n, read access detected while corresponding subregion was enabled - for watching */ -} MWU_PERREGION_Type; - -typedef struct { - __IO uint32_t START; /*!< Description cluster[n]: Start address for region n */ - __IO uint32_t END; /*!< Description cluster[n]: End address of region n */ - __I uint32_t RESERVED2[2]; -} MWU_REGION_Type; - -typedef struct { - __I uint32_t START; /*!< Description cluster[n]: Reserved for future use */ - __I uint32_t END; /*!< Description cluster[n]: Reserved for future use */ - __IO uint32_t SUBS; /*!< Description cluster[n]: Subregions of region n */ - __I uint32_t RESERVED3; -} MWU_PREGION_Type; - -typedef struct { - __IO uint32_t MODE; /*!< I2S mode. */ - __IO uint32_t RXEN; /*!< Reception (RX) enable. */ - __IO uint32_t TXEN; /*!< Transmission (TX) enable. */ - __IO uint32_t MCKEN; /*!< Master clock generator enable. */ - __IO uint32_t MCKFREQ; /*!< Master clock generator frequency. */ - __IO uint32_t RATIO; /*!< MCK / LRCK ratio. */ - __IO uint32_t SWIDTH; /*!< Sample width. */ - __IO uint32_t ALIGN; /*!< Alignment of sample within a frame. */ - __IO uint32_t FORMAT; /*!< Frame format. */ - __IO uint32_t CHANNELS; /*!< Enable channels. */ -} I2S_CONFIG_Type; - -typedef struct { - __IO uint32_t PTR; /*!< Receive buffer RAM start address. */ -} I2S_RXD_Type; - -typedef struct { - __IO uint32_t PTR; /*!< Transmit buffer RAM start address. */ -} I2S_TXD_Type; - -typedef struct { - __IO uint32_t MAXCNT; /*!< Size of RXD and TXD buffers. */ -} I2S_RXTXD_Type; - -typedef struct { - __IO uint32_t MCK; /*!< Pin select for MCK signal. */ - __IO uint32_t SCK; /*!< Pin select for SCK signal. */ - __IO uint32_t LRCK; /*!< Pin select for LRCK signal. */ - __IO uint32_t SDIN; /*!< Pin select for SDIN signal. */ - __IO uint32_t SDOUT; /*!< Pin select for SDOUT signal. */ -} I2S_PSEL_Type; - -typedef struct { - __I uint32_t EPIN[8]; /*!< Description collection[n]: IN endpoint halted status. Can be - used as is as response to a GetStatus() request to endpoint. */ - __I uint32_t RESERVED4; - __I uint32_t EPOUT[8]; /*!< Description collection[n]: OUT endpoint halted status. Can be - used as is as response to a GetStatus() request to endpoint. */ -} USBD_HALTED_Type; - -typedef struct { - __IO uint32_t EPOUT[8]; /*!< Description collection[n]: Number of bytes received last in - the data stage of this OUT endpoint */ - __I uint32_t ISOOUT; /*!< Number of bytes received last on this ISO OUT data endpoint */ -} USBD_SIZE_Type; - -typedef struct { - __IO uint32_t PTR; /*!< Description cluster[n]: Data pointer */ - __IO uint32_t MAXCNT; /*!< Description cluster[n]: Maximum number of bytes to transfer */ - __I uint32_t AMOUNT; /*!< Description cluster[n]: Number of bytes transferred in the last - transaction */ - __I uint32_t RESERVED5[2]; -} USBD_EPIN_Type; - -typedef struct { - __IO uint32_t PTR; /*!< Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes to transfer */ - __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ -} USBD_ISOIN_Type; - -typedef struct { - __IO uint32_t PTR; /*!< Description cluster[n]: Data pointer */ - __IO uint32_t MAXCNT; /*!< Description cluster[n]: Maximum number of bytes to transfer */ - __I uint32_t AMOUNT; /*!< Description cluster[n]: Number of bytes transferred in the last - transaction */ - __I uint32_t RESERVED6[2]; -} USBD_EPOUT_Type; - -typedef struct { - __IO uint32_t PTR; /*!< Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes to transfer */ - __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ -} USBD_ISOOUT_Type; - -typedef struct { - __IO uint32_t SRC; /*!< Flash memory source address */ - __IO uint32_t DST; /*!< RAM destination address */ - __IO uint32_t CNT; /*!< Read transfer length */ -} QSPI_READ_Type; - -typedef struct { - __IO uint32_t DST; /*!< Flash destination address */ - __IO uint32_t SRC; /*!< RAM source address */ - __IO uint32_t CNT; /*!< Write transfer length */ -} QSPI_WRITE_Type; - -typedef struct { - __IO uint32_t PTR; /*!< Start address of flash block to be erased */ - __IO uint32_t LEN; /*!< Size of block to be erased. */ -} QSPI_ERASE_Type; - -typedef struct { - __IO uint32_t SCK; /*!< Pin select for serial clock SCK */ - __IO uint32_t CSN; /*!< Pin select for chip select signal CSN. */ - __I uint32_t RESERVED7; - __IO uint32_t IO0; /*!< Pin select for serial data MOSI/IO0. */ - __IO uint32_t IO1; /*!< Pin select for serial data MISO/IO1. */ - __IO uint32_t IO2; /*!< Pin select for serial data IO2. */ - __IO uint32_t IO3; /*!< Pin select for serial data IO3. */ -} QSPI_PSEL_Type; - - -/* ================================================================================ */ -/* ================ FICR ================ */ -/* ================================================================================ */ - - -/** - * @brief Factory information configuration registers (FICR) - */ - -typedef struct { /*!< FICR Structure */ - __I uint32_t RESERVED0[4]; - __I uint32_t CODEPAGESIZE; /*!< Code memory page size */ - __I uint32_t CODESIZE; /*!< Code memory size */ - __I uint32_t RESERVED1[18]; - __I uint32_t DEVICEID[2]; /*!< Description collection[n]: Device identifier */ - __I uint32_t RESERVED2[6]; - __I uint32_t ER[4]; /*!< Description collection[n]: Encryption root, word n */ - __I uint32_t IR[4]; /*!< Description collection[n]: Identity Root, word n */ - __I uint32_t DEVICEADDRTYPE; /*!< Device address type */ - __I uint32_t DEVICEADDR[2]; /*!< Description collection[n]: Device address n */ - __I uint32_t RESERVED3[21]; - FICR_INFO_Type INFO; /*!< Device info */ - __I uint32_t RESERVED4[140]; - __I uint32_t PRODTEST[3]; /*!< Description collection[n]: Production test signature n */ - __I uint32_t RESERVED5[42]; - FICR_TEMP_Type TEMP; /*!< Registers storing factory TEMP module linearization coefficients */ - __I uint32_t RESERVED6[2]; - FICR_NFC_Type NFC; /*!< Unspecified */ - __I uint32_t RESERVED7[488]; - FICR_TRNG90B_Type TRNG90B; /*!< NIST800-90B RNG calibration data */ -} NRF_FICR_Type; - - -/* ================================================================================ */ -/* ================ UICR ================ */ -/* ================================================================================ */ - - -/** - * @brief User information configuration registers (UICR) - */ - -typedef struct { /*!< UICR Structure */ - __IO uint32_t UNUSED0; /*!< Unspecified */ - __IO uint32_t UNUSED1; /*!< Unspecified */ - __IO uint32_t UNUSED2; /*!< Unspecified */ - __I uint32_t RESERVED0; - __IO uint32_t UNUSED3; /*!< Unspecified */ - __IO uint32_t NRFFW[15]; /*!< Description collection[n]: Reserved for Nordic firmware design */ - __IO uint32_t NRFHW[12]; /*!< Description collection[n]: Reserved for Nordic hardware design */ - __IO uint32_t CUSTOMER[32]; /*!< Description collection[n]: Reserved for customer */ - __I uint32_t RESERVED1[64]; - __IO uint32_t PSELRESET[2]; /*!< Description collection[n]: Mapping of the nRESET function */ - __IO uint32_t APPROTECT; /*!< Access port protection */ - __IO uint32_t NFCPINS; /*!< Setting of pins dedicated to NFC functionality: NFC antenna - or GPIO */ - __IO uint32_t DEBUGCTRL; /*!< Processor debug control */ - __I uint32_t RESERVED2[60]; - __IO uint32_t REGOUT0; /*!< GPIO reference voltage / external output supply voltage in high - voltage mode */ -} NRF_UICR_Type; - - -/* ================================================================================ */ -/* ================ CLOCK ================ */ -/* ================================================================================ */ - - -/** - * @brief Clock control (CLOCK) - */ - -typedef struct { /*!< CLOCK Structure */ - __O uint32_t TASKS_HFCLKSTART; /*!< Start HFXO crystal oscillator */ - __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFXO crystal oscillator */ - __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK */ - __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK */ - __O uint32_t TASKS_CAL; /*!< Start calibration of LFRC */ - __O uint32_t TASKS_CTSTART; /*!< Start calibration timer */ - __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer */ - __I uint32_t RESERVED0[57]; - __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFXO crystal oscillator started */ - __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK started */ - __I uint32_t RESERVED1; - __IO uint32_t EVENTS_DONE; /*!< Calibration of LFRC completed */ - __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout */ - __I uint32_t RESERVED2[5]; - __IO uint32_t EVENTS_CTSTARTED; /*!< Calibration timer has been started and is ready to process new - tasks */ - __IO uint32_t EVENTS_CTSTOPPED; /*!< Calibration timer has been stopped and is ready to process new - tasks */ - __I uint32_t RESERVED3[117]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED4[63]; - __I uint32_t HFCLKRUN; /*!< Status indicating that HFCLKSTART task has been triggered */ - __I uint32_t HFCLKSTAT; /*!< HFCLK status */ - __I uint32_t RESERVED5; - __I uint32_t LFCLKRUN; /*!< Status indicating that LFCLKSTART task has been triggered */ - __I uint32_t LFCLKSTAT; /*!< LFCLK status */ - __I uint32_t LFCLKSRCCOPY; /*!< Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ - __I uint32_t RESERVED6[62]; - __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK */ - __I uint32_t RESERVED7[3]; - __IO uint32_t HFXODEBOUNCE; /*!< HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART - task. */ - __I uint32_t RESERVED8[3]; - __IO uint32_t CTIV; /*!< Calibration timer interval */ - __I uint32_t RESERVED9[8]; - __IO uint32_t TRACECONFIG; /*!< Clocking options for the trace port debug interface */ - __I uint32_t RESERVED10[21]; - __IO uint32_t LFRCMODE; /*!< LFRC mode configuration */ -} NRF_CLOCK_Type; - - -/* ================================================================================ */ -/* ================ POWER ================ */ -/* ================================================================================ */ - - -/** - * @brief Power control (POWER) - */ - -typedef struct { /*!< POWER Structure */ - __I uint32_t RESERVED0[30]; - __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode */ - __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency) */ - __I uint32_t RESERVED1[34]; - __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning */ - __I uint32_t RESERVED2[2]; - __IO uint32_t EVENTS_SLEEPENTER; /*!< CPU entered WFI/WFE sleep */ - __IO uint32_t EVENTS_SLEEPEXIT; /*!< CPU exited WFI/WFE sleep */ - __IO uint32_t EVENTS_USBDETECTED; /*!< Voltage supply detected on VBUS */ - __IO uint32_t EVENTS_USBREMOVED; /*!< Voltage supply removed from VBUS */ - __IO uint32_t EVENTS_USBPWRRDY; /*!< USB 3.3 V supply ready */ - __I uint32_t RESERVED3[119]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED4[61]; - __IO uint32_t RESETREAS; /*!< Reset reason */ - __I uint32_t RESERVED5[9]; - __I uint32_t RAMSTATUS; /*!< Deprecated register - RAM status register */ - __I uint32_t RESERVED6[3]; - __I uint32_t USBREGSTATUS; /*!< USB supply status */ - __I uint32_t RESERVED7[49]; - __O uint32_t SYSTEMOFF; /*!< System OFF register */ - __I uint32_t RESERVED8[3]; - __IO uint32_t POFCON; /*!< Power-fail comparator configuration */ - __I uint32_t RESERVED9[2]; - __IO uint32_t GPREGRET; /*!< General purpose retention register */ - __IO uint32_t GPREGRET2; /*!< General purpose retention register */ - __I uint32_t RESERVED10[21]; - __IO uint32_t DCDCEN; /*!< Enable DC/DC converter for REG1 stage. */ - __I uint32_t RESERVED11; - __IO uint32_t DCDCEN0; /*!< Enable DC/DC converter for REG0 stage. */ - __I uint32_t RESERVED12[47]; - __I uint32_t MAINREGSTATUS; /*!< Main supply status */ - __I uint32_t RESERVED13[175]; - POWER_RAM_Type RAM[9]; /*!< Unspecified */ -} NRF_POWER_Type; - - -/* ================================================================================ */ -/* ================ RADIO ================ */ -/* ================================================================================ */ - - -/** - * @brief 2.4 GHz radio (RADIO) - */ - -typedef struct { /*!< RADIO Structure */ - __O uint32_t TASKS_TXEN; /*!< Enable RADIO in TX mode */ - __O uint32_t TASKS_RXEN; /*!< Enable RADIO in RX mode */ - __O uint32_t TASKS_START; /*!< Start RADIO */ - __O uint32_t TASKS_STOP; /*!< Stop RADIO */ - __O uint32_t TASKS_DISABLE; /*!< Disable RADIO */ - __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one single sample of the receive signal - strength */ - __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement */ - __O uint32_t TASKS_BCSTART; /*!< Start the bit counter */ - __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter */ - __O uint32_t TASKS_EDSTART; /*!< Start the energy detect measurement used in IEEE 802.15.4 mode */ - __O uint32_t TASKS_EDSTOP; /*!< Stop the energy detect measurement */ - __O uint32_t TASKS_CCASTART; /*!< Start the clear channel assessment used in IEEE 802.15.4 mode */ - __O uint32_t TASKS_CCASTOP; /*!< Stop the clear channel assessment */ - __I uint32_t RESERVED0[51]; - __IO uint32_t EVENTS_READY; /*!< RADIO has ramped up and is ready to be started */ - __IO uint32_t EVENTS_ADDRESS; /*!< Address sent or received */ - __IO uint32_t EVENTS_PAYLOAD; /*!< Packet payload sent or received */ - __IO uint32_t EVENTS_END; /*!< Packet sent or received */ - __IO uint32_t EVENTS_DISABLED; /*!< RADIO has been disabled */ - __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet */ - __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet */ - __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of receive signal strength complete */ - __I uint32_t RESERVED1[2]; - __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value */ - __I uint32_t RESERVED2; - __IO uint32_t EVENTS_CRCOK; /*!< Packet received with CRC ok */ - __IO uint32_t EVENTS_CRCERROR; /*!< Packet received with CRC error */ - __IO uint32_t EVENTS_FRAMESTART; /*!< IEEE 802.15.4 length field received */ - __IO uint32_t EVENTS_EDEND; /*!< Sampling of energy detection complete. A new ED sample is ready - for readout from the RADIO.EDSAMPLE register. */ - __IO uint32_t EVENTS_EDSTOPPED; /*!< The sampling of energy detection has stopped */ - __IO uint32_t EVENTS_CCAIDLE; /*!< Wireless medium in idle - clear to send */ - __IO uint32_t EVENTS_CCABUSY; /*!< Wireless medium busy - do not send */ - __IO uint32_t EVENTS_CCASTOPPED; /*!< The CCA has stopped */ - __IO uint32_t EVENTS_RATEBOOST; /*!< Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit - to Ble_LR500Kbit. */ - __IO uint32_t EVENTS_TXREADY; /*!< RADIO has ramped up and is ready to be started TX path */ - __IO uint32_t EVENTS_RXREADY; /*!< RADIO has ramped up and is ready to be started RX path */ - __IO uint32_t EVENTS_MHRMATCH; /*!< MAC header match found */ - __I uint32_t RESERVED3[3]; - __IO uint32_t EVENTS_PHYEND; /*!< Generated in Ble_LR125Kbit, Ble_LR500Kbit and BleIeee802154_250Kbit - modes when last bit is sent on air. */ - __I uint32_t RESERVED4[36]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED5[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED6[61]; - __I uint32_t CRCSTATUS; /*!< CRC status */ - __I uint32_t RESERVED7; - __I uint32_t RXMATCH; /*!< Received address */ - __I uint32_t RXCRC; /*!< CRC field of previously received packet */ - __I uint32_t DAI; /*!< Device address match index */ - __I uint32_t PDUSTAT; /*!< Payload status */ - __I uint32_t RESERVED8[59]; - __IO uint32_t PACKETPTR; /*!< Packet pointer */ - __IO uint32_t FREQUENCY; /*!< Frequency */ - __IO uint32_t TXPOWER; /*!< Output power */ - __IO uint32_t MODE; /*!< Data rate and modulation */ - __IO uint32_t PCNF0; /*!< Packet configuration register 0 */ - __IO uint32_t PCNF1; /*!< Packet configuration register 1 */ - __IO uint32_t BASE0; /*!< Base address 0 */ - __IO uint32_t BASE1; /*!< Base address 1 */ - __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0-3 */ - __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4-7 */ - __IO uint32_t TXADDRESS; /*!< Transmit address select */ - __IO uint32_t RXADDRESSES; /*!< Receive address select */ - __IO uint32_t CRCCNF; /*!< CRC configuration */ - __IO uint32_t CRCPOLY; /*!< CRC polynomial */ - __IO uint32_t CRCINIT; /*!< CRC initial value */ - __I uint32_t RESERVED9; - __IO uint32_t TIFS; /*!< Interframe spacing in us */ - __I uint32_t RSSISAMPLE; /*!< RSSI sample */ - __I uint32_t RESERVED10; - __I uint32_t STATE; /*!< Current radio state */ - __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value */ - __I uint32_t RESERVED11[2]; - __IO uint32_t BCC; /*!< Bit counter compare */ - __I uint32_t RESERVED12[39]; - __IO uint32_t DAB[8]; /*!< Description collection[n]: Device address base segment n */ - __IO uint32_t DAP[8]; /*!< Description collection[n]: Device address prefix n */ - __IO uint32_t DACNF; /*!< Device address match configuration */ - __IO uint32_t MHRMATCHCONF; /*!< Search pattern configuration */ - __IO uint32_t MHRMATCHMAS; /*!< Pattern mask */ - __I uint32_t RESERVED13; - __IO uint32_t MODECNF0; /*!< Radio mode configuration register 0 */ - __I uint32_t RESERVED14[3]; - __IO uint32_t SFD; /*!< IEEE 802.15.4 start of frame delimiter */ - __IO uint32_t EDCNT; /*!< IEEE 802.15.4 energy detect loop count */ - __IO uint32_t EDSAMPLE; /*!< IEEE 802.15.4 energy detect level */ - __IO uint32_t CCACTRL; /*!< IEEE 802.15.4 clear channel assessment control */ - __I uint32_t RESERVED15[611]; - __IO uint32_t POWER; /*!< Peripheral power control */ -} NRF_RADIO_Type; - - -/* ================================================================================ */ -/* ================ UART ================ */ -/* ================================================================================ */ - - -/** - * @brief Universal Asynchronous Receiver/Transmitter (UART) - */ - -typedef struct { /*!< UART Structure */ - __O uint32_t TASKS_STARTRX; /*!< Start UART receiver */ - __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver */ - __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter */ - __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter */ - __I uint32_t RESERVED0[3]; - __O uint32_t TASKS_SUSPEND; /*!< Suspend UART */ - __I uint32_t RESERVED1[56]; - __IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */ - __IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */ - __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD */ - __I uint32_t RESERVED2[4]; - __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD */ - __I uint32_t RESERVED3; - __IO uint32_t EVENTS_ERROR; /*!< Error detected */ - __I uint32_t RESERVED4[7]; - __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout */ - __I uint32_t RESERVED5[46]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED6[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED7[93]; - __IO uint32_t ERRORSRC; /*!< Error source */ - __I uint32_t RESERVED8[31]; - __IO uint32_t ENABLE; /*!< Enable UART */ - __I uint32_t RESERVED9; - UART_PSEL_Type PSEL; /*!< Unspecified */ - __I uint32_t RXD; /*!< RXD register */ - __O uint32_t TXD; /*!< TXD register */ - __I uint32_t RESERVED10; - __IO uint32_t BAUDRATE; /*!< Baud rate. Accuracy depends on the HFCLK source selected. */ - __I uint32_t RESERVED11[17]; - __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control */ -} NRF_UART_Type; - - -/* ================================================================================ */ -/* ================ UARTE ================ */ -/* ================================================================================ */ - - -/** - * @brief UART with EasyDMA 0 (UARTE) - */ - -typedef struct { /*!< UARTE Structure */ - __O uint32_t TASKS_STARTRX; /*!< Start UART receiver */ - __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver */ - __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter */ - __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter */ - __I uint32_t RESERVED0[7]; - __O uint32_t TASKS_FLUSHRX; /*!< Flush RX FIFO into RX buffer */ - __I uint32_t RESERVED1[52]; - __IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */ - __IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */ - __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD (but potentially not yet transferred to - Data RAM) */ - __I uint32_t RESERVED2; - __IO uint32_t EVENTS_ENDRX; /*!< Receive buffer is filled up */ - __I uint32_t RESERVED3[2]; - __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD */ - __IO uint32_t EVENTS_ENDTX; /*!< Last TX byte transmitted */ - __IO uint32_t EVENTS_ERROR; /*!< Error detected */ - __I uint32_t RESERVED4[7]; - __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout */ - __I uint32_t RESERVED5; - __IO uint32_t EVENTS_RXSTARTED; /*!< UART receiver has started */ - __IO uint32_t EVENTS_TXSTARTED; /*!< UART transmitter has started */ - __I uint32_t RESERVED6; - __IO uint32_t EVENTS_TXSTOPPED; /*!< Transmitter stopped */ - __I uint32_t RESERVED7[41]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED8[63]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED9[93]; - __IO uint32_t ERRORSRC; /*!< Error source Note : this register is read / write one to clear. */ - __I uint32_t RESERVED10[31]; - __IO uint32_t ENABLE; /*!< Enable UART */ - __I uint32_t RESERVED11; - UARTE_PSEL_Type PSEL; /*!< Unspecified */ - __I uint32_t RESERVED12[3]; - __IO uint32_t BAUDRATE; /*!< Baud rate. Accuracy depends on the HFCLK source selected. */ - __I uint32_t RESERVED13[3]; - UARTE_RXD_Type RXD; /*!< RXD EasyDMA channel */ - __I uint32_t RESERVED14; - UARTE_TXD_Type TXD; /*!< TXD EasyDMA channel */ - __I uint32_t RESERVED15[7]; - __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control */ -} NRF_UARTE_Type; - - -/* ================================================================================ */ -/* ================ SPI ================ */ -/* ================================================================================ */ - - -/** - * @brief Serial Peripheral Interface 0 (SPI) - */ - -typedef struct { /*!< SPI Structure */ - __I uint32_t RESERVED0[66]; - __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received */ - __I uint32_t RESERVED1[126]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED2[125]; - __IO uint32_t ENABLE; /*!< Enable SPI */ - __I uint32_t RESERVED3; - SPI_PSEL_Type PSEL; /*!< Unspecified */ - __I uint32_t RESERVED4; - __I uint32_t RXD; /*!< RXD register */ - __IO uint32_t TXD; /*!< TXD register */ - __I uint32_t RESERVED5; - __IO uint32_t FREQUENCY; /*!< SPI frequency. Accuracy depends on the HFCLK source selected. */ - __I uint32_t RESERVED6[11]; - __IO uint32_t CONFIG; /*!< Configuration register */ -} NRF_SPI_Type; - - -/* ================================================================================ */ -/* ================ SPIM ================ */ -/* ================================================================================ */ - - -/** - * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM) - */ - -typedef struct { /*!< SPIM Structure */ - __I uint32_t RESERVED0[4]; - __O uint32_t TASKS_START; /*!< Start SPI transaction */ - __O uint32_t TASKS_STOP; /*!< Stop SPI transaction */ - __I uint32_t RESERVED1; - __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction */ - __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction */ - __I uint32_t RESERVED2[56]; - __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped */ - __I uint32_t RESERVED3[2]; - __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */ - __I uint32_t RESERVED4; - __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached */ - __I uint32_t RESERVED5; - __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached */ - __I uint32_t RESERVED6[10]; - __IO uint32_t EVENTS_STARTED; /*!< Transaction started */ - __I uint32_t RESERVED7[44]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED8[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED9[61]; - __IO uint32_t STALLSTAT; /*!< Stall status for EasyDMA RAM accesses. The fields in this register - is set to STALL by hardware whenever a stall occurres and can - be cleared (set to NOSTALL) by the CPU. */ - __I uint32_t RESERVED10[63]; - __IO uint32_t ENABLE; /*!< Enable SPIM */ - __I uint32_t RESERVED11; - SPIM_PSEL_Type PSEL; /*!< Unspecified */ - __I uint32_t RESERVED12[3]; - __IO uint32_t FREQUENCY; /*!< SPI frequency. Accuracy depends on the HFCLK source selected. */ - __I uint32_t RESERVED13[3]; - SPIM_RXD_Type RXD; /*!< RXD EasyDMA channel */ - SPIM_TXD_Type TXD; /*!< TXD EasyDMA channel */ - __IO uint32_t CONFIG; /*!< Configuration register */ - __I uint32_t RESERVED14[2]; - SPIM_IFTIMING_Type IFTIMING; /*!< Unspecified */ - __IO uint32_t CSNPOL; /*!< Polarity of CSN output */ - __IO uint32_t PSELDCX; /*!< Pin select for DCX signal */ - __IO uint32_t DCXCNT; /*!< DCX configuration */ - __I uint32_t RESERVED15[19]; - __IO uint32_t ORC; /*!< Byte transmitted after TXD.MAXCNT bytes have been transmitted - in the case when RXD.MAXCNT is greater than TXD.MAXCNT */ -} NRF_SPIM_Type; - - -/* ================================================================================ */ -/* ================ SPIS ================ */ -/* ================================================================================ */ - - -/** - * @brief SPI Slave 0 (SPIS) - */ - -typedef struct { /*!< SPIS Structure */ - __I uint32_t RESERVED0[9]; - __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore */ - __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore, enabling the SPI slave to acquire it */ - __I uint32_t RESERVED1[54]; - __IO uint32_t EVENTS_END; /*!< Granted transaction completed */ - __I uint32_t RESERVED2[2]; - __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */ - __I uint32_t RESERVED3[5]; - __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired */ - __I uint32_t RESERVED4[53]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED5[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED6[61]; - __I uint32_t SEMSTAT; /*!< Semaphore status register */ - __I uint32_t RESERVED7[15]; - __IO uint32_t STATUS; /*!< Status from last transaction */ - __I uint32_t RESERVED8[47]; - __IO uint32_t ENABLE; /*!< Enable SPI slave */ - __I uint32_t RESERVED9; - SPIS_PSEL_Type PSEL; /*!< Unspecified */ - __I uint32_t RESERVED10[7]; - SPIS_RXD_Type RXD; /*!< Unspecified */ - __I uint32_t RESERVED11; - SPIS_TXD_Type TXD; /*!< Unspecified */ - __I uint32_t RESERVED12; - __IO uint32_t CONFIG; /*!< Configuration register */ - __I uint32_t RESERVED13; - __IO uint32_t DEF; /*!< Default character. Character clocked out in case of an ignored - transaction. */ - __I uint32_t RESERVED14[24]; - __IO uint32_t ORC; /*!< Over-read character */ -} NRF_SPIS_Type; - - -/* ================================================================================ */ -/* ================ TWI ================ */ -/* ================================================================================ */ - - -/** - * @brief I2C compatible Two-Wire Interface 0 (TWI) - */ - -typedef struct { /*!< TWI Structure */ - __O uint32_t TASKS_STARTRX; /*!< Start TWI receive sequence */ - __I uint32_t RESERVED0; - __O uint32_t TASKS_STARTTX; /*!< Start TWI transmit sequence */ - __I uint32_t RESERVED1[2]; - __O uint32_t TASKS_STOP; /*!< Stop TWI transaction */ - __I uint32_t RESERVED2; - __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */ - __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */ - __I uint32_t RESERVED3[56]; - __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */ - __IO uint32_t EVENTS_RXDREADY; /*!< TWI RXD byte received */ - __I uint32_t RESERVED4[4]; - __IO uint32_t EVENTS_TXDSENT; /*!< TWI TXD byte sent */ - __I uint32_t RESERVED5; - __IO uint32_t EVENTS_ERROR; /*!< TWI error */ - __I uint32_t RESERVED6[4]; - __IO uint32_t EVENTS_BB; /*!< TWI byte boundary, generated before each byte that is sent or - received */ - __I uint32_t RESERVED7[3]; - __IO uint32_t EVENTS_SUSPENDED; /*!< TWI entered the suspended state */ - __I uint32_t RESERVED8[45]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED9[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED10[110]; - __IO uint32_t ERRORSRC; /*!< Error source */ - __I uint32_t RESERVED11[14]; - __IO uint32_t ENABLE; /*!< Enable TWI */ - __I uint32_t RESERVED12; - TWI_PSEL_Type PSEL; /*!< Unspecified */ - __I uint32_t RESERVED13[2]; - __I uint32_t RXD; /*!< RXD register */ - __IO uint32_t TXD; /*!< TXD register */ - __I uint32_t RESERVED14; - __IO uint32_t FREQUENCY; /*!< TWI frequency. Accuracy depends on the HFCLK source selected. */ - __I uint32_t RESERVED15[24]; - __IO uint32_t ADDRESS; /*!< Address used in the TWI transfer */ -} NRF_TWI_Type; - - -/* ================================================================================ */ -/* ================ TWIM ================ */ -/* ================================================================================ */ - - -/** - * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM) - */ - -typedef struct { /*!< TWIM Structure */ - __O uint32_t TASKS_STARTRX; /*!< Start TWI receive sequence */ - __I uint32_t RESERVED0; - __O uint32_t TASKS_STARTTX; /*!< Start TWI transmit sequence */ - __I uint32_t RESERVED1[2]; - __O uint32_t TASKS_STOP; /*!< Stop TWI transaction. Must be issued while the TWI master is - not suspended. */ - __I uint32_t RESERVED2; - __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */ - __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */ - __I uint32_t RESERVED3[56]; - __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */ - __I uint32_t RESERVED4[7]; - __IO uint32_t EVENTS_ERROR; /*!< TWI error */ - __I uint32_t RESERVED5[8]; - __IO uint32_t EVENTS_SUSPENDED; /*!< Last byte has been sent out after the SUSPEND task has been - issued, TWI traffic is now suspended. */ - __IO uint32_t EVENTS_RXSTARTED; /*!< Receive sequence started */ - __IO uint32_t EVENTS_TXSTARTED; /*!< Transmit sequence started */ - __I uint32_t RESERVED6[2]; - __IO uint32_t EVENTS_LASTRX; /*!< Byte boundary, starting to receive the last byte */ - __IO uint32_t EVENTS_LASTTX; /*!< Byte boundary, starting to transmit the last byte */ - __I uint32_t RESERVED7[39]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED8[63]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED9[110]; - __IO uint32_t ERRORSRC; /*!< Error source */ - __I uint32_t RESERVED10[14]; - __IO uint32_t ENABLE; /*!< Enable TWIM */ - __I uint32_t RESERVED11; - TWIM_PSEL_Type PSEL; /*!< Unspecified */ - __I uint32_t RESERVED12[5]; - __IO uint32_t FREQUENCY; /*!< TWI frequency. Accuracy depends on the HFCLK source selected. */ - __I uint32_t RESERVED13[3]; - TWIM_RXD_Type RXD; /*!< RXD EasyDMA channel */ - TWIM_TXD_Type TXD; /*!< TXD EasyDMA channel */ - __I uint32_t RESERVED14[13]; - __IO uint32_t ADDRESS; /*!< Address used in the TWI transfer */ -} NRF_TWIM_Type; - - -/* ================================================================================ */ -/* ================ TWIS ================ */ -/* ================================================================================ */ - - -/** - * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS) - */ - -typedef struct { /*!< TWIS Structure */ - __I uint32_t RESERVED0[5]; - __O uint32_t TASKS_STOP; /*!< Stop TWI transaction */ - __I uint32_t RESERVED1; - __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */ - __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */ - __I uint32_t RESERVED2[3]; - __O uint32_t TASKS_PREPARERX; /*!< Prepare the TWI slave to respond to a write command */ - __O uint32_t TASKS_PREPARETX; /*!< Prepare the TWI slave to respond to a read command */ - __I uint32_t RESERVED3[51]; - __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */ - __I uint32_t RESERVED4[7]; - __IO uint32_t EVENTS_ERROR; /*!< TWI error */ - __I uint32_t RESERVED5[9]; - __IO uint32_t EVENTS_RXSTARTED; /*!< Receive sequence started */ - __IO uint32_t EVENTS_TXSTARTED; /*!< Transmit sequence started */ - __I uint32_t RESERVED6[4]; - __IO uint32_t EVENTS_WRITE; /*!< Write command received */ - __IO uint32_t EVENTS_READ; /*!< Read command received */ - __I uint32_t RESERVED7[37]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED8[63]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED9[113]; - __IO uint32_t ERRORSRC; /*!< Error source */ - __I uint32_t MATCH; /*!< Status register indicating which address had a match */ - __I uint32_t RESERVED10[10]; - __IO uint32_t ENABLE; /*!< Enable TWIS */ - __I uint32_t RESERVED11; - TWIS_PSEL_Type PSEL; /*!< Unspecified */ - __I uint32_t RESERVED12[9]; - TWIS_RXD_Type RXD; /*!< RXD EasyDMA channel */ - __I uint32_t RESERVED13; - TWIS_TXD_Type TXD; /*!< TXD EasyDMA channel */ - __I uint32_t RESERVED14[14]; - __IO uint32_t ADDRESS[2]; /*!< Description collection[n]: TWI slave address n */ - __I uint32_t RESERVED15; - __IO uint32_t CONFIG; /*!< Configuration register for the address match mechanism */ - __I uint32_t RESERVED16[10]; - __IO uint32_t ORC; /*!< Over-read character. Character sent out in case of an over-read - of the transmit buffer. */ -} NRF_TWIS_Type; - - -/* ================================================================================ */ -/* ================ NFCT ================ */ -/* ================================================================================ */ - - -/** - * @brief NFC-A compatible radio (NFCT) - */ - -typedef struct { /*!< NFCT Structure */ - __O uint32_t TASKS_ACTIVATE; /*!< Activate NFCT peripheral for incoming and outgoing frames, change - state to activated */ - __O uint32_t TASKS_DISABLE; /*!< Disable NFCT peripheral */ - __O uint32_t TASKS_SENSE; /*!< Enable NFC sense field mode, change state to sense mode */ - __O uint32_t TASKS_STARTTX; /*!< Start transmission of an outgoing frame, change state to transmit */ - __I uint32_t RESERVED0[3]; - __O uint32_t TASKS_ENABLERXDATA; /*!< Initializes the EasyDMA for receive. */ - __I uint32_t RESERVED1; - __O uint32_t TASKS_GOIDLE; /*!< Force state machine to IDLE state */ - __O uint32_t TASKS_GOSLEEP; /*!< Force state machine to SLEEP_A state */ - __I uint32_t RESERVED2[53]; - __IO uint32_t EVENTS_READY; /*!< The NFCT peripheral is ready to receive and send frames */ - __IO uint32_t EVENTS_FIELDDETECTED; /*!< Remote NFC field detected */ - __IO uint32_t EVENTS_FIELDLOST; /*!< Remote NFC field lost */ - __IO uint32_t EVENTS_TXFRAMESTART; /*!< Marks the start of the first symbol of a transmitted frame */ - __IO uint32_t EVENTS_TXFRAMEEND; /*!< Marks the end of the last transmitted on-air symbol of a frame */ - __IO uint32_t EVENTS_RXFRAMESTART; /*!< Marks the end of the first symbol of a received frame */ - __IO uint32_t EVENTS_RXFRAMEEND; /*!< Received data has been checked (CRC, parity) and transferred - to RAM, and EasyDMA has ended accessing the RX buffer */ - __IO uint32_t EVENTS_ERROR; /*!< NFC error reported. The ERRORSTATUS register contains details - on the source of the error. */ - __I uint32_t RESERVED3[2]; - __IO uint32_t EVENTS_RXERROR; /*!< NFC RX frame error reported. The FRAMESTATUS.RX register contains - details on the source of the error. */ - __IO uint32_t EVENTS_ENDRX; /*!< RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */ - __IO uint32_t EVENTS_ENDTX; /*!< Transmission of data in RAM has ended, and EasyDMA has ended - accessing the TX buffer */ - __I uint32_t RESERVED4; - __IO uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< Auto collision resolution process has started */ - __I uint32_t RESERVED5[3]; - __IO uint32_t EVENTS_COLLISION; /*!< NFC auto collision resolution error reported. */ - __IO uint32_t EVENTS_SELECTED; /*!< NFC auto collision resolution successfully completed */ - __IO uint32_t EVENTS_STARTED; /*!< EasyDMA is ready to receive or send frames. */ - __I uint32_t RESERVED6[43]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED7[63]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED8[62]; - __IO uint32_t ERRORSTATUS; /*!< NFC Error Status register */ - __I uint32_t RESERVED9; - NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< Unspecified */ - __I uint32_t NFCTAGSTATE; /*!< NfcTag state register */ - __I uint32_t RESERVED10[3]; - __I uint32_t SLEEPSTATE; /*!< Sleep state during automatic collision resolution */ - __I uint32_t RESERVED11[6]; - __I uint32_t FIELDPRESENT; /*!< Indicates the presence or not of a valid field */ - __I uint32_t RESERVED12[49]; - __IO uint32_t FRAMEDELAYMIN; /*!< Minimum frame delay */ - __IO uint32_t FRAMEDELAYMAX; /*!< Maximum frame delay */ - __IO uint32_t FRAMEDELAYMODE; /*!< Configuration register for the Frame Delay Timer */ - __IO uint32_t PACKETPTR; /*!< Packet pointer for TXD and RXD data storage in Data RAM */ - __IO uint32_t MAXLEN; /*!< Size of the RAM buffer allocated to TXD and RXD data storage - each */ - NFCT_TXD_Type TXD; /*!< Unspecified */ - NFCT_RXD_Type RXD; /*!< Unspecified */ - __I uint32_t RESERVED13[26]; - __IO uint32_t NFCID1_LAST; /*!< Last NFCID1 part (4, 7 or 10 bytes ID) */ - __IO uint32_t NFCID1_2ND_LAST; /*!< Second last NFCID1 part (7 or 10 bytes ID) */ - __IO uint32_t NFCID1_3RD_LAST; /*!< Third last NFCID1 part (10 bytes ID) */ - __IO uint32_t AUTOCOLRESCONFIG; /*!< Controls the auto collision resolution function. This setting - must be done before the NFCT peripheral is enabled. */ - __IO uint32_t SENSRES; /*!< NFC-A SENS_RES auto-response settings */ - __IO uint32_t SELRES; /*!< NFC-A SEL_RES auto-response settings */ -} NRF_NFCT_Type; - - -/* ================================================================================ */ -/* ================ GPIOTE ================ */ -/* ================================================================================ */ - - -/** - * @brief GPIO Tasks and Events (GPIOTE) - */ - -typedef struct { /*!< GPIOTE Structure */ - __O uint32_t TASKS_OUT[8]; /*!< Description collection[n]: Task for writing to pin specified - in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ - __I uint32_t RESERVED0[4]; - __O uint32_t TASKS_SET[8]; /*!< Description collection[n]: Task for writing to pin specified - in CONFIG[n].PSEL. Action on pin is to set it high. */ - __I uint32_t RESERVED1[4]; - __O uint32_t TASKS_CLR[8]; /*!< Description collection[n]: Task for writing to pin specified - in CONFIG[n].PSEL. Action on pin is to set it low. */ - __I uint32_t RESERVED2[32]; - __IO uint32_t EVENTS_IN[8]; /*!< Description collection[n]: Event generated from pin specified - in CONFIG[n].PSEL */ - __I uint32_t RESERVED3[23]; - __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple input GPIO pins with SENSE mechanism - enabled */ - __I uint32_t RESERVED4[97]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED5[129]; - __IO uint32_t CONFIG[8]; /*!< Description collection[n]: Configuration for OUT[n], SET[n] - and CLR[n] tasks and IN[n] event */ -} NRF_GPIOTE_Type; - - -/* ================================================================================ */ -/* ================ SAADC ================ */ -/* ================================================================================ */ - - -/** - * @brief Successive approximation register (SAR) analog-to-digital converter (SAADC) - */ - -typedef struct { /*!< SAADC Structure */ - __O uint32_t TASKS_START; /*!< Starts the SAADC and prepares the result buffer in RAM */ - __O uint32_t TASKS_SAMPLE; /*!< Takes one SAADC sample */ - __O uint32_t TASKS_STOP; /*!< Stops the SAADC and terminates all on-going conversions */ - __O uint32_t TASKS_CALIBRATEOFFSET; /*!< Starts offset auto-calibration */ - __I uint32_t RESERVED0[60]; - __IO uint32_t EVENTS_STARTED; /*!< The SAADC has started */ - __IO uint32_t EVENTS_END; /*!< The SAADC has filled up the result buffer */ - __IO uint32_t EVENTS_DONE; /*!< A conversion task has been completed. Depending on the configuration, - multiple conversions might be needed for a result to be transferred - to RAM. */ - __IO uint32_t EVENTS_RESULTDONE; /*!< Result ready for transfer to RAM */ - __IO uint32_t EVENTS_CALIBRATEDONE; /*!< Calibration is complete */ - __IO uint32_t EVENTS_STOPPED; /*!< The SAADC has stopped */ - SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< Unspecified */ - __I uint32_t RESERVED1[106]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED2[61]; - __I uint32_t STATUS; /*!< Status */ - __I uint32_t RESERVED3[63]; - __IO uint32_t ENABLE; /*!< Enable or disable SAADC */ - __I uint32_t RESERVED4[3]; - SAADC_CH_Type CH[8]; /*!< Unspecified */ - __I uint32_t RESERVED5[24]; - __IO uint32_t RESOLUTION; /*!< Resolution configuration */ - __IO uint32_t OVERSAMPLE; /*!< Oversampling configuration. The RESOLUTION is applied before - averaging, thus for high OVERSAMPLE a higher RESOLUTION should - be used. */ - __IO uint32_t SAMPLERATE; /*!< Controls normal or continuous sample rate */ - __I uint32_t RESERVED6[12]; - SAADC_RESULT_Type RESULT; /*!< RESULT EasyDMA channel */ -} NRF_SAADC_Type; - - -/* ================================================================================ */ -/* ================ TIMER ================ */ -/* ================================================================================ */ - - -/** - * @brief Timer/Counter 0 (TIMER) - */ - -typedef struct { /*!< TIMER Structure */ - __O uint32_t TASKS_START; /*!< Start Timer */ - __O uint32_t TASKS_STOP; /*!< Stop Timer */ - __O uint32_t TASKS_COUNT; /*!< Increment Timer (Counter mode only) */ - __O uint32_t TASKS_CLEAR; /*!< Clear time */ - __O uint32_t TASKS_SHUTDOWN; /*!< Deprecated register - Shut down timer */ - __I uint32_t RESERVED0[11]; - __O uint32_t TASKS_CAPTURE[6]; /*!< Description collection[n]: Capture Timer value to CC[n] register */ - __I uint32_t RESERVED1[58]; - __IO uint32_t EVENTS_COMPARE[6]; /*!< Description collection[n]: Compare event on CC[n] match */ - __I uint32_t RESERVED2[42]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED3[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED4[126]; - __IO uint32_t MODE; /*!< Timer mode selection */ - __IO uint32_t BITMODE; /*!< Configure the number of bits used by the TIMER */ - __I uint32_t RESERVED5; - __IO uint32_t PRESCALER; /*!< Timer prescaler register */ - __I uint32_t RESERVED6[11]; - __IO uint32_t CC[6]; /*!< Description collection[n]: Capture/Compare register n */ -} NRF_TIMER_Type; - - -/* ================================================================================ */ -/* ================ RTC ================ */ -/* ================================================================================ */ - - -/** - * @brief Real time counter 0 (RTC) - */ - -typedef struct { /*!< RTC Structure */ - __O uint32_t TASKS_START; /*!< Start RTC COUNTER */ - __O uint32_t TASKS_STOP; /*!< Stop RTC COUNTER */ - __O uint32_t TASKS_CLEAR; /*!< Clear RTC COUNTER */ - __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFF0 */ - __I uint32_t RESERVED0[60]; - __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment */ - __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow */ - __I uint32_t RESERVED1[14]; - __IO uint32_t EVENTS_COMPARE[4]; /*!< Description collection[n]: Compare event on CC[n] match */ - __I uint32_t RESERVED2[109]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[13]; - __IO uint32_t EVTEN; /*!< Enable or disable event routing */ - __IO uint32_t EVTENSET; /*!< Enable event routing */ - __IO uint32_t EVTENCLR; /*!< Disable event routing */ - __I uint32_t RESERVED4[110]; - __I uint32_t COUNTER; /*!< Current COUNTER value */ - __IO uint32_t PRESCALER; /*!< 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must - be written when RTC is stopped */ - __I uint32_t RESERVED5[13]; - __IO uint32_t CC[4]; /*!< Description collection[n]: Compare register n */ -} NRF_RTC_Type; - - -/* ================================================================================ */ -/* ================ TEMP ================ */ -/* ================================================================================ */ - - -/** - * @brief Temperature Sensor (TEMP) - */ - -typedef struct { /*!< TEMP Structure */ - __O uint32_t TASKS_START; /*!< Start temperature measurement */ - __O uint32_t TASKS_STOP; /*!< Stop temperature measurement */ - __I uint32_t RESERVED0[62]; - __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready */ - __I uint32_t RESERVED1[128]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED2[127]; - __I int32_t TEMP; /*!< Temperature in degC (0.25deg steps) */ - __I uint32_t RESERVED3[5]; - __IO uint32_t A0; /*!< Slope of 1st piece wise linear function */ - __IO uint32_t A1; /*!< Slope of 2nd piece wise linear function */ - __IO uint32_t A2; /*!< Slope of 3rd piece wise linear function */ - __IO uint32_t A3; /*!< Slope of 4th piece wise linear function */ - __IO uint32_t A4; /*!< Slope of 5th piece wise linear function */ - __IO uint32_t A5; /*!< Slope of 6th piece wise linear function */ - __I uint32_t RESERVED4[2]; - __IO uint32_t B0; /*!< y-intercept of 1st piece wise linear function */ - __IO uint32_t B1; /*!< y-intercept of 2nd piece wise linear function */ - __IO uint32_t B2; /*!< y-intercept of 3rd piece wise linear function */ - __IO uint32_t B3; /*!< y-intercept of 4th piece wise linear function */ - __IO uint32_t B4; /*!< y-intercept of 5th piece wise linear function */ - __IO uint32_t B5; /*!< y-intercept of 6th piece wise linear function */ - __I uint32_t RESERVED5[2]; - __IO uint32_t T0; /*!< End point of 1st piece wise linear function */ - __IO uint32_t T1; /*!< End point of 2nd piece wise linear function */ - __IO uint32_t T2; /*!< End point of 3rd piece wise linear function */ - __IO uint32_t T3; /*!< End point of 4th piece wise linear function */ - __IO uint32_t T4; /*!< End point of 5th piece wise linear function */ -} NRF_TEMP_Type; - - -/* ================================================================================ */ -/* ================ RNG ================ */ -/* ================================================================================ */ - - -/** - * @brief Random Number Generator (RNG) - */ - -typedef struct { /*!< RNG Structure */ - __O uint32_t TASKS_START; /*!< Task starting the random number generator */ - __O uint32_t TASKS_STOP; /*!< Task stopping the random number generator */ - __I uint32_t RESERVED0[62]; - __IO uint32_t EVENTS_VALRDY; /*!< Event being generated for every new random number written to - the VALUE register */ - __I uint32_t RESERVED1[63]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED2[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[126]; - __IO uint32_t CONFIG; /*!< Configuration register */ - __I uint32_t VALUE; /*!< Output random number */ -} NRF_RNG_Type; - - -/* ================================================================================ */ -/* ================ ECB ================ */ -/* ================================================================================ */ - - -/** - * @brief AES ECB Mode Encryption (ECB) - */ - -typedef struct { /*!< ECB Structure */ - __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt */ - __O uint32_t TASKS_STOPECB; /*!< Abort a possible executing ECB operation */ - __I uint32_t RESERVED0[62]; - __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete */ - __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted because of a STOPECB task or due to - an error */ - __I uint32_t RESERVED1[127]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED2[126]; - __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointers */ -} NRF_ECB_Type; - - -/* ================================================================================ */ -/* ================ AAR ================ */ -/* ================================================================================ */ - - -/** - * @brief Accelerated Address Resolver (AAR) - */ - -typedef struct { /*!< AAR Structure */ - __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK - data structure */ - __I uint32_t RESERVED0; - __O uint32_t TASKS_STOP; /*!< Stop resolving addresses */ - __I uint32_t RESERVED1[61]; - __IO uint32_t EVENTS_END; /*!< Address resolution procedure complete */ - __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved */ - __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved */ - __I uint32_t RESERVED2[126]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[61]; - __I uint32_t STATUS; /*!< Resolution status */ - __I uint32_t RESERVED4[63]; - __IO uint32_t ENABLE; /*!< Enable AAR */ - __IO uint32_t NIRK; /*!< Number of IRKs */ - __IO uint32_t IRKPTR; /*!< Pointer to IRK data structure */ - __I uint32_t RESERVED5; - __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address */ - __IO uint32_t SCRATCHPTR; /*!< Pointer to data area used for temporary storage */ -} NRF_AAR_Type; - - -/* ================================================================================ */ -/* ================ CCM ================ */ -/* ================================================================================ */ - - -/** - * @brief AES CCM Mode Encryption (CCM) - */ - -typedef struct { /*!< CCM Structure */ - __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by - itself when completed. */ - __O uint32_t TASKS_CRYPT; /*!< Start encryption/decryption. This operation will stop by itself - when completed. */ - __O uint32_t TASKS_STOP; /*!< Stop encryption/decryption */ - __O uint32_t TASKS_RATEOVERRIDE; /*!< Override DATARATE setting in MODE register with the contents - of the RATEOVERRIDE register for any ongoing encryption/decryption */ - __I uint32_t RESERVED0[60]; - __IO uint32_t EVENTS_ENDKSGEN; /*!< Key-stream generation complete */ - __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt complete */ - __IO uint32_t EVENTS_ERROR; /*!< Deprecated register - CCM error event */ - __I uint32_t RESERVED1[61]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED2[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[61]; - __I uint32_t MICSTATUS; /*!< MIC check result */ - __I uint32_t RESERVED4[63]; - __IO uint32_t ENABLE; /*!< Enable */ - __IO uint32_t MODE; /*!< Operation mode */ - __IO uint32_t CNFPTR; /*!< Pointer to data structure holding AES key and NONCE vector */ - __IO uint32_t INPTR; /*!< Input pointer */ - __IO uint32_t OUTPTR; /*!< Output pointer */ - __IO uint32_t SCRATCHPTR; /*!< Pointer to data area used for temporary storage */ - __IO uint32_t MAXPACKETSIZE; /*!< Length of key-stream generated when MODE.LENGTH = Extended. */ - __IO uint32_t RATEOVERRIDE; /*!< Data rate override setting. */ -} NRF_CCM_Type; - - -/* ================================================================================ */ -/* ================ WDT ================ */ -/* ================================================================================ */ - - -/** - * @brief Watchdog Timer (WDT) - */ - -typedef struct { /*!< WDT Structure */ - __O uint32_t TASKS_START; /*!< Start the watchdog */ - __I uint32_t RESERVED0[63]; - __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout */ - __I uint32_t RESERVED1[128]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED2[61]; - __I uint32_t RUNSTATUS; /*!< Run status */ - __I uint32_t REQSTATUS; /*!< Request status */ - __I uint32_t RESERVED3[63]; - __IO uint32_t CRV; /*!< Counter reload value */ - __IO uint32_t RREN; /*!< Enable register for reload request registers */ - __IO uint32_t CONFIG; /*!< Configuration register */ - __I uint32_t RESERVED4[60]; - __O uint32_t RR[8]; /*!< Description collection[n]: Reload request n */ -} NRF_WDT_Type; - - -/* ================================================================================ */ -/* ================ QDEC ================ */ -/* ================================================================================ */ - - -/** - * @brief Quadrature Decoder (QDEC) - */ - -typedef struct { /*!< QDEC Structure */ - __O uint32_t TASKS_START; /*!< Task starting the quadrature decoder */ - __O uint32_t TASKS_STOP; /*!< Task stopping the quadrature decoder */ - __O uint32_t TASKS_READCLRACC; /*!< Read and clear ACC and ACCDBL */ - __O uint32_t TASKS_RDCLRACC; /*!< Read and clear ACC */ - __O uint32_t TASKS_RDCLRDBL; /*!< Read and clear ACCDBL */ - __I uint32_t RESERVED0[59]; - __IO uint32_t EVENTS_SAMPLERDY; /*!< Event being generated for every new sample value written to - the SAMPLE register */ - __IO uint32_t EVENTS_REPORTRDY; /*!< Non-null report ready */ - __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow */ - __IO uint32_t EVENTS_DBLRDY; /*!< Double displacement(s) detected */ - __IO uint32_t EVENTS_STOPPED; /*!< QDEC has been stopped */ - __I uint32_t RESERVED1[59]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED2[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[125]; - __IO uint32_t ENABLE; /*!< Enable the quadrature decoder */ - __IO uint32_t LEDPOL; /*!< LED output pin polarity */ - __IO uint32_t SAMPLEPER; /*!< Sample period */ - __I int32_t SAMPLE; /*!< Motion sample value */ - __IO uint32_t REPORTPER; /*!< Number of samples to be taken before REPORTRDY and DBLRDY events - can be generated */ - __I int32_t ACC; /*!< Register accumulating the valid transitions */ - __I int32_t ACCREAD; /*!< Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC - task */ - QDEC_PSEL_Type PSEL; /*!< Unspecified */ - __IO uint32_t DBFEN; /*!< Enable input debounce filters */ - __I uint32_t RESERVED4[5]; - __IO uint32_t LEDPRE; /*!< Time period the LED is switched ON prior to sampling */ - __I uint32_t ACCDBL; /*!< Register accumulating the number of detected double transitions */ - __I uint32_t ACCDBLREAD; /*!< Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL - task */ -} NRF_QDEC_Type; - - -/* ================================================================================ */ -/* ================ COMP ================ */ -/* ================================================================================ */ - - -/** - * @brief Comparator (COMP) - */ - -typedef struct { /*!< COMP Structure */ - __O uint32_t TASKS_START; /*!< Start comparator */ - __O uint32_t TASKS_STOP; /*!< Stop comparator */ - __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value */ - __I uint32_t RESERVED0[61]; - __IO uint32_t EVENTS_READY; /*!< COMP is ready and output is valid */ - __IO uint32_t EVENTS_DOWN; /*!< Downward crossing */ - __IO uint32_t EVENTS_UP; /*!< Upward crossing */ - __IO uint32_t EVENTS_CROSS; /*!< Downward or upward crossing */ - __I uint32_t RESERVED1[60]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED2[63]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[61]; - __I uint32_t RESULT; /*!< Compare result */ - __I uint32_t RESERVED4[63]; - __IO uint32_t ENABLE; /*!< COMP enable */ - __IO uint32_t PSEL; /*!< Pin select */ - __IO uint32_t REFSEL; /*!< Reference source select for single-ended mode */ - __IO uint32_t EXTREFSEL; /*!< External reference select */ - __I uint32_t RESERVED5[8]; - __IO uint32_t TH; /*!< Threshold configuration for hysteresis unit */ - __IO uint32_t MODE; /*!< Mode configuration */ - __IO uint32_t HYST; /*!< Comparator hysteresis enable */ -} NRF_COMP_Type; - - -/* ================================================================================ */ -/* ================ LPCOMP ================ */ -/* ================================================================================ */ - - -/** - * @brief Low Power Comparator (LPCOMP) - */ - -typedef struct { /*!< LPCOMP Structure */ - __O uint32_t TASKS_START; /*!< Start comparator */ - __O uint32_t TASKS_STOP; /*!< Stop comparator */ - __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value */ - __I uint32_t RESERVED0[61]; - __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid */ - __IO uint32_t EVENTS_DOWN; /*!< Downward crossing */ - __IO uint32_t EVENTS_UP; /*!< Upward crossing */ - __IO uint32_t EVENTS_CROSS; /*!< Downward or upward crossing */ - __I uint32_t RESERVED1[60]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED2[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[61]; - __I uint32_t RESULT; /*!< Compare result */ - __I uint32_t RESERVED4[63]; - __IO uint32_t ENABLE; /*!< Enable LPCOMP */ - __IO uint32_t PSEL; /*!< Input pin select */ - __IO uint32_t REFSEL; /*!< Reference select */ - __IO uint32_t EXTREFSEL; /*!< External reference select */ - __I uint32_t RESERVED5[4]; - __IO uint32_t ANADETECT; /*!< Analog detect configuration */ - __I uint32_t RESERVED6[5]; - __IO uint32_t HYST; /*!< Comparator hysteresis enable */ -} NRF_LPCOMP_Type; - - -/* ================================================================================ */ -/* ================ EGU ================ */ -/* ================================================================================ */ - - -/** - * @brief Event Generator Unit 0 (EGU) - */ - -typedef struct { /*!< EGU Structure */ - __O uint32_t TASKS_TRIGGER[16]; /*!< Description collection[n]: Trigger n for triggering the corresponding - TRIGGERED[n] event */ - __I uint32_t RESERVED0[48]; - __IO uint32_t EVENTS_TRIGGERED[16]; /*!< Description collection[n]: Event number n generated by triggering - the corresponding TRIGGER[n] task */ - __I uint32_t RESERVED1[112]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ -} NRF_EGU_Type; - - -/* ================================================================================ */ -/* ================ SWI ================ */ -/* ================================================================================ */ - - -/** - * @brief Software interrupt 0 (SWI) - */ - -typedef struct { /*!< SWI Structure */ - __I uint32_t UNUSED; /*!< Unused. */ -} NRF_SWI_Type; - - -/* ================================================================================ */ -/* ================ PWM ================ */ -/* ================================================================================ */ - - -/** - * @brief Pulse width modulation unit 0 (PWM) - */ - -typedef struct { /*!< PWM Structure */ - __I uint32_t RESERVED0; - __O uint32_t TASKS_STOP; /*!< Stops PWM pulse generation on all channels at the end of current - PWM period, and stops sequence playback */ - __O uint32_t TASKS_SEQSTART[2]; /*!< Description collection[n]: Loads the first PWM value on all - enabled channels from sequence n, and starts playing that sequence - at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes - PWM generation to start if not running. */ - __O uint32_t TASKS_NEXTSTEP; /*!< Steps by one value in the current sequence on all enabled channels - if DECODER.MODE=NextStep. Does not cause PWM generation to start - if not running. */ - __I uint32_t RESERVED1[60]; - __IO uint32_t EVENTS_STOPPED; /*!< Response to STOP task, emitted when PWM pulses are no longer - generated */ - __IO uint32_t EVENTS_SEQSTARTED[2]; /*!< Description collection[n]: First PWM period started on sequence - n */ - __IO uint32_t EVENTS_SEQEND[2]; /*!< Description collection[n]: Emitted at end of every sequence - n, when last value from RAM has been applied to wave counter */ - __IO uint32_t EVENTS_PWMPERIODEND; /*!< Emitted at the end of each PWM period */ - __IO uint32_t EVENTS_LOOPSDONE; /*!< Concatenated sequences have been played the amount of times - defined in LOOP.CNT */ - __I uint32_t RESERVED2[56]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED3[63]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED4[125]; - __IO uint32_t ENABLE; /*!< PWM module enable register */ - __IO uint32_t MODE; /*!< Selects operating mode of the wave counter */ - __IO uint32_t COUNTERTOP; /*!< Value up to which the pulse generator counter counts */ - __IO uint32_t PRESCALER; /*!< Configuration for PWM_CLK */ - __IO uint32_t DECODER; /*!< Configuration of the decoder */ - __IO uint32_t LOOP; /*!< Number of playbacks of a loop */ - __I uint32_t RESERVED5[2]; - PWM_SEQ_Type SEQ[2]; /*!< Unspecified */ - PWM_PSEL_Type PSEL; /*!< Unspecified */ -} NRF_PWM_Type; - - -/* ================================================================================ */ -/* ================ PDM ================ */ -/* ================================================================================ */ - - -/** - * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) - */ - -typedef struct { /*!< PDM Structure */ - __O uint32_t TASKS_START; /*!< Starts continuous PDM transfer */ - __O uint32_t TASKS_STOP; /*!< Stops PDM transfer */ - __I uint32_t RESERVED0[62]; - __IO uint32_t EVENTS_STARTED; /*!< PDM transfer has started */ - __IO uint32_t EVENTS_STOPPED; /*!< PDM transfer has finished */ - __IO uint32_t EVENTS_END; /*!< The PDM has written the last sample specified by SAMPLE.MAXCNT - (or the last sample after a STOP task has been received) to - Data RAM */ - __I uint32_t RESERVED1[125]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED2[125]; - __IO uint32_t ENABLE; /*!< PDM module enable register */ - __IO uint32_t PDMCLKCTRL; /*!< PDM clock generator control */ - __IO uint32_t MODE; /*!< Defines the routing of the connected PDM microphones' signals */ - __I uint32_t RESERVED3[3]; - __IO uint32_t GAINL; /*!< Left output gain adjustment */ - __IO uint32_t GAINR; /*!< Right output gain adjustment */ - __IO uint32_t RATIO; /*!< Selects the ratio between PDM_CLK and output sample rate. Change - PDMCLKCTRL accordingly. */ - __I uint32_t RESERVED4[7]; - PDM_PSEL_Type PSEL; /*!< Unspecified */ - __I uint32_t RESERVED5[6]; - PDM_SAMPLE_Type SAMPLE; /*!< Unspecified */ -} NRF_PDM_Type; - - -/* ================================================================================ */ -/* ================ ACL ================ */ -/* ================================================================================ */ - - -/** - * @brief Access control lists (ACL) - */ - -typedef struct { /*!< ACL Structure */ - __I uint32_t RESERVED0[512]; - ACL_ACL_Type ACL[8]; /*!< Unspecified */ -} NRF_ACL_Type; - - -/* ================================================================================ */ -/* ================ NVMC ================ */ -/* ================================================================================ */ - - -/** - * @brief Non Volatile Memory Controller (NVMC) - */ - -typedef struct { /*!< NVMC Structure */ - __I uint32_t RESERVED0[256]; - __I uint32_t READY; /*!< Ready flag */ - __I uint32_t RESERVED1; - __I uint32_t READYNEXT; /*!< Ready flag */ - __I uint32_t RESERVED2[62]; - __IO uint32_t CONFIG; /*!< Configuration register */ - - union { - __IO uint32_t ERASEPCR1; /*!< Deprecated register - Register for erasing a page in code area. - Equivalent to ERASEPAGE. */ - __IO uint32_t ERASEPAGE; /*!< Register for erasing a page in code area */ - }; - __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory */ - __IO uint32_t ERASEPCR0; /*!< Deprecated register - Register for erasing a page in code area. - Equivalent to ERASEPAGE. */ - __IO uint32_t ERASEUICR; /*!< Register for erasing user information configuration registers */ - __IO uint32_t ERASEPAGEPARTIAL; /*!< Register for partial erase of a page in code area */ - __IO uint32_t ERASEPAGEPARTIALCFG; /*!< Register for partial erase configuration */ - __I uint32_t RESERVED3[8]; - __IO uint32_t ICACHECNF; /*!< I-code cache configuration register. */ - __I uint32_t RESERVED4; - __IO uint32_t IHIT; /*!< I-code cache hit counter. */ - __IO uint32_t IMISS; /*!< I-code cache miss counter. */ -} NRF_NVMC_Type; - - -/* ================================================================================ */ -/* ================ PPI ================ */ -/* ================================================================================ */ - - -/** - * @brief Programmable Peripheral Interconnect (PPI) - */ - -typedef struct { /*!< PPI Structure */ - PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< Channel group tasks */ - __I uint32_t RESERVED0[308]; - __IO uint32_t CHEN; /*!< Channel enable register */ - __IO uint32_t CHENSET; /*!< Channel enable set register */ - __IO uint32_t CHENCLR; /*!< Channel enable clear register */ - __I uint32_t RESERVED1; - PPI_CH_Type CH[20]; /*!< PPI Channel */ - __I uint32_t RESERVED2[148]; - __IO uint32_t CHG[6]; /*!< Description collection[n]: Channel group n */ - __I uint32_t RESERVED3[62]; - PPI_FORK_Type FORK[32]; /*!< Fork */ -} NRF_PPI_Type; - - -/* ================================================================================ */ -/* ================ MWU ================ */ -/* ================================================================================ */ - - -/** - * @brief Memory Watch Unit (MWU) - */ - -typedef struct { /*!< MWU Structure */ - __I uint32_t RESERVED0[64]; - MWU_EVENTS_REGION_Type EVENTS_REGION[4]; /*!< Unspecified */ - __I uint32_t RESERVED1[16]; - MWU_EVENTS_PREGION_Type EVENTS_PREGION[2]; /*!< Unspecified */ - __I uint32_t RESERVED2[100]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[5]; - __IO uint32_t NMIEN; /*!< Enable or disable non-maskable interrupt */ - __IO uint32_t NMIENSET; /*!< Enable non-maskable interrupt */ - __IO uint32_t NMIENCLR; /*!< Disable non-maskable interrupt */ - __I uint32_t RESERVED4[53]; - MWU_PERREGION_Type PERREGION[2]; /*!< Unspecified */ - __I uint32_t RESERVED5[64]; - __IO uint32_t REGIONEN; /*!< Enable/disable regions watch */ - __IO uint32_t REGIONENSET; /*!< Enable regions watch */ - __IO uint32_t REGIONENCLR; /*!< Disable regions watch */ - __I uint32_t RESERVED6[57]; - MWU_REGION_Type REGION[4]; /*!< Unspecified */ - __I uint32_t RESERVED7[32]; - MWU_PREGION_Type PREGION[2]; /*!< Unspecified */ -} NRF_MWU_Type; - - -/* ================================================================================ */ -/* ================ I2S ================ */ -/* ================================================================================ */ - - -/** - * @brief Inter-IC Sound (I2S) - */ - -typedef struct { /*!< I2S Structure */ - __O uint32_t TASKS_START; /*!< Starts continuous I2S transfer. Also starts MCK generator when - this is enabled. */ - __O uint32_t TASKS_STOP; /*!< Stops I2S transfer. Also stops MCK generator. Triggering this - task will cause the {event:STOPPED} event to be generated. */ - __I uint32_t RESERVED0[63]; - __IO uint32_t EVENTS_RXPTRUPD; /*!< The RXD.PTR register has been copied to internal double-buffers. - When the I2S module is started and RX is enabled, this event - will be generated for every RXTXD.MAXCNT words that are received - on the SDIN pin. */ - __IO uint32_t EVENTS_STOPPED; /*!< I2S transfer stopped. */ - __I uint32_t RESERVED1[2]; - __IO uint32_t EVENTS_TXPTRUPD; /*!< The TDX.PTR register has been copied to internal double-buffers. - When the I2S module is started and TX is enabled, this event - will be generated for every RXTXD.MAXCNT words that are sent - on the SDOUT pin. */ - __I uint32_t RESERVED2[122]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[125]; - __IO uint32_t ENABLE; /*!< Enable I2S module. */ - I2S_CONFIG_Type CONFIG; /*!< Unspecified */ - __I uint32_t RESERVED4[3]; - I2S_RXD_Type RXD; /*!< Unspecified */ - __I uint32_t RESERVED5; - I2S_TXD_Type TXD; /*!< Unspecified */ - __I uint32_t RESERVED6[3]; - I2S_RXTXD_Type RXTXD; /*!< Unspecified */ - __I uint32_t RESERVED7[3]; - I2S_PSEL_Type PSEL; /*!< Unspecified */ -} NRF_I2S_Type; - - -/* ================================================================================ */ -/* ================ FPU ================ */ -/* ================================================================================ */ - - -/** - * @brief FPU (FPU) - */ - -typedef struct { /*!< FPU Structure */ - __I uint32_t UNUSED; /*!< Unused. */ -} NRF_FPU_Type; - - -/* ================================================================================ */ -/* ================ USBD ================ */ -/* ================================================================================ */ - - -/** - * @brief Universal serial bus device (USBD) - */ - -typedef struct { /*!< USBD Structure */ - __I uint32_t RESERVED0; - __O uint32_t TASKS_STARTEPIN[8]; /*!< Description collection[n]: Captures the EPIN[n].PTR and EPIN[n].MAXCNT - registers values, and enables endpoint IN n to respond to traffic - from host */ - __O uint32_t TASKS_STARTISOIN; /*!< Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and - enables sending data on ISO endpoint */ - __O uint32_t TASKS_STARTEPOUT[8]; /*!< Description collection[n]: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT - registers values, and enables endpoint n to respond to traffic - from host */ - __O uint32_t TASKS_STARTISOOUT; /*!< Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, - and enables receiving of data on ISO endpoint */ - __O uint32_t TASKS_EP0RCVOUT; /*!< Allows OUT data stage on control endpoint 0 */ - __O uint32_t TASKS_EP0STATUS; /*!< Allows status stage on control endpoint 0 */ - __O uint32_t TASKS_EP0STALL; /*!< Stalls data and status stage on control endpoint 0 */ - __O uint32_t TASKS_DPDMDRIVE; /*!< Forces D+ and D- lines into the state defined in the DPDMVALUE - register */ - __O uint32_t TASKS_DPDMNODRIVE; /*!< Stops forcing D+ and D- lines into any state (USB engine takes - control) */ - __I uint32_t RESERVED1[40]; - __IO uint32_t EVENTS_USBRESET; /*!< Signals that a USB reset condition has been detected on USB - lines */ - __IO uint32_t EVENTS_STARTED; /*!< Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR - and EPOUT[n].MAXCNT registers have been captured on all endpoints - reported in the EPSTATUS register */ - __IO uint32_t EVENTS_ENDEPIN[8]; /*!< Description collection[n]: The whole EPIN[n] buffer has been - consumed. The RAM buffer can be accessed safely by software. */ - __IO uint32_t EVENTS_EP0DATADONE; /*!< An acknowledged data transfer has taken place on the control - endpoint */ - __IO uint32_t EVENTS_ENDISOIN; /*!< The whole ISOIN buffer has been consumed. The RAM buffer can - be accessed safely by software. */ - __IO uint32_t EVENTS_ENDEPOUT[8]; /*!< Description collection[n]: The whole EPOUT[n] buffer has been - consumed. The RAM buffer can be accessed safely by software. */ - __IO uint32_t EVENTS_ENDISOOUT; /*!< The whole ISOOUT buffer has been consumed. The RAM buffer can - be accessed safely by software. */ - __IO uint32_t EVENTS_SOF; /*!< Signals that a SOF (start of frame) condition has been detected - on USB lines */ - __IO uint32_t EVENTS_USBEVENT; /*!< An event or an error not covered by specific events has occurred. - Check EVENTCAUSE register to find the cause. */ - __IO uint32_t EVENTS_EP0SETUP; /*!< A valid SETUP token has been received (and acknowledged) on - the control endpoint */ - __IO uint32_t EVENTS_EPDATA; /*!< A data transfer has occurred on a data endpoint, indicated by - the EPDATASTATUS register */ - __I uint32_t RESERVED2[39]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED3[63]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED4[61]; - __IO uint32_t EVENTCAUSE; /*!< Details on what caused the USBEVENT event */ - __I uint32_t RESERVED5[7]; - USBD_HALTED_Type HALTED; /*!< Unspecified */ - __I uint32_t RESERVED6; - __IO uint32_t EPSTATUS; /*!< Provides information on which endpoint's EasyDMA registers have - been captured */ - __IO uint32_t EPDATASTATUS; /*!< Provides information on which endpoint(s) an acknowledged data - transfer has occurred (EPDATA event) */ - __I uint32_t USBADDR; /*!< Device USB address */ - __I uint32_t RESERVED7[3]; - __I uint32_t BMREQUESTTYPE; /*!< SETUP data, byte 0, bmRequestType */ - __I uint32_t BREQUEST; /*!< SETUP data, byte 1, bRequest */ - __I uint32_t WVALUEL; /*!< SETUP data, byte 2, LSB of wValue */ - __I uint32_t WVALUEH; /*!< SETUP data, byte 3, MSB of wValue */ - __I uint32_t WINDEXL; /*!< SETUP data, byte 4, LSB of wIndex */ - __I uint32_t WINDEXH; /*!< SETUP data, byte 5, MSB of wIndex */ - __I uint32_t WLENGTHL; /*!< SETUP data, byte 6, LSB of wLength */ - __I uint32_t WLENGTHH; /*!< SETUP data, byte 7, MSB of wLength */ - USBD_SIZE_Type SIZE; /*!< Unspecified */ - __I uint32_t RESERVED8[15]; - __IO uint32_t ENABLE; /*!< Enable USB */ - __IO uint32_t USBPULLUP; /*!< Control of the USB pull-up */ - __IO uint32_t DPDMVALUE; /*!< State D+ and D- lines will be forced into by the DPDMDRIVE task. - The DPDMNODRIVE task reverts the control of the lines to MAC - IP (no forcing). */ - __IO uint32_t DTOGGLE; /*!< Data toggle control and status */ - __IO uint32_t EPINEN; /*!< Endpoint IN enable */ - __IO uint32_t EPOUTEN; /*!< Endpoint OUT enable */ - __O uint32_t EPSTALL; /*!< STALL endpoints */ - __IO uint32_t ISOSPLIT; /*!< Controls the split of ISO buffers */ - __I uint32_t FRAMECNTR; /*!< Returns the current value of the start of frame counter */ - __I uint32_t RESERVED9[2]; - __IO uint32_t LOWPOWER; /*!< Controls USBD peripheral low power mode during USB suspend */ - __IO uint32_t ISOINCONFIG; /*!< Controls the response of the ISO IN endpoint to an IN token - when no data is ready to be sent */ - __I uint32_t RESERVED10[51]; - USBD_EPIN_Type EPIN[8]; /*!< Unspecified */ - USBD_ISOIN_Type ISOIN; /*!< Unspecified */ - __I uint32_t RESERVED11[21]; - USBD_EPOUT_Type EPOUT[8]; /*!< Unspecified */ - USBD_ISOOUT_Type ISOOUT; /*!< Unspecified */ -} NRF_USBD_Type; - - -/* ================================================================================ */ -/* ================ QSPI ================ */ -/* ================================================================================ */ - - -/** - * @brief External flash interface (QSPI) - */ - -typedef struct { /*!< QSPI Structure */ - __O uint32_t TASKS_ACTIVATE; /*!< Activate QSPI interface */ - __O uint32_t TASKS_READSTART; /*!< Start transfer from external flash memory to internal RAM */ - __O uint32_t TASKS_WRITESTART; /*!< Start transfer from internal RAM to external flash memory */ - __O uint32_t TASKS_ERASESTART; /*!< Start external flash memory erase operation */ - __O uint32_t TASKS_DEACTIVATE; /*!< Deactivate QSPI interface */ - __I uint32_t RESERVED0[59]; - __IO uint32_t EVENTS_READY; /*!< QSPI peripheral is ready. This event will be generated as a - response to any QSPI task. */ - __I uint32_t RESERVED1[127]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED2[125]; - __IO uint32_t ENABLE; /*!< Enable QSPI peripheral and acquire the pins selected in PSELn - registers */ - QSPI_READ_Type READ; /*!< Unspecified */ - QSPI_WRITE_Type WRITE; /*!< Unspecified */ - QSPI_ERASE_Type ERASE; /*!< Unspecified */ - QSPI_PSEL_Type PSEL; /*!< Unspecified */ - __IO uint32_t XIPOFFSET; /*!< Address offset into the external memory for Execute in Place - operation. */ - __IO uint32_t IFCONFIG0; /*!< Interface configuration. */ - __I uint32_t RESERVED3[46]; - __IO uint32_t IFCONFIG1; /*!< Interface configuration. */ - __I uint32_t STATUS; /*!< Status register. */ - __I uint32_t RESERVED4[3]; - __IO uint32_t DPMDUR; /*!< Set the duration required to enter/exit deep power-down mode - (DPM). */ - __I uint32_t RESERVED5[3]; - __IO uint32_t ADDRCONF; /*!< Extended address configuration. */ - __I uint32_t RESERVED6[3]; - __IO uint32_t CINSTRCONF; /*!< Custom instruction configuration register. */ - __IO uint32_t CINSTRDAT0; /*!< Custom instruction data register 0. */ - __IO uint32_t CINSTRDAT1; /*!< Custom instruction data register 1. */ - __IO uint32_t IFTIMING; /*!< SPI interface timing. */ -} NRF_QSPI_Type; - - -/* ================================================================================ */ -/* ================ GPIO ================ */ -/* ================================================================================ */ - - -/** - * @brief GPIO Port 1 (GPIO) - */ - -typedef struct { /*!< GPIO Structure */ - __I uint32_t RESERVED0[321]; - __IO uint32_t OUT; /*!< Write GPIO port */ - __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port */ - __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port */ - __I uint32_t IN; /*!< Read GPIO port */ - __IO uint32_t DIR; /*!< Direction of GPIO pins */ - __IO uint32_t DIRSET; /*!< DIR set register */ - __IO uint32_t DIRCLR; /*!< DIR clear register */ - __IO uint32_t LATCH; /*!< Latch register indicating what GPIO pins that have met the criteria - set in the PIN_CNF[n].SENSE registers */ - __IO uint32_t DETECTMODE; /*!< Select between default DETECT signal behaviour and LDETECT mode */ - __I uint32_t RESERVED1[118]; - __IO uint32_t PIN_CNF[32]; /*!< Description collection[n]: Configuration of GPIO pins */ -} NRF_GPIO_Type; - - -/* ================================================================================ */ -/* ================ CC_HOST_RGF ================ */ -/* ================================================================================ */ - - -/** - * @brief CRYPTOCELL HOST_RGF interface (CC_HOST_RGF) - */ - -typedef struct { /*!< CC_HOST_RGF Structure */ - __I uint32_t RESERVED0[1678]; - __IO uint32_t HOST_CRYPTOKEY_SEL; /*!< AES hardware key select */ - __I uint32_t RESERVED1[4]; - __IO uint32_t HOST_IOT_KPRTL_LOCK; /*!< This write-once register is the K_PRTL lock register. When this - register is set, K_PRTL can not be used and a zeroed key will - be used instead. The value of this register is saved in the - CRYPTOCELL AO power domain. */ - __IO uint32_t HOST_IOT_KDR0; /*!< This register holds bits 31:0 of K_DR. The value of this register - is saved in the CRYPTOCELL AO power domain. Reading from this - address returns the K_DR valid status indicating if K_DR is - successfully retained. */ - __O uint32_t HOST_IOT_KDR1; /*!< This register holds bits 63:32 of K_DR. The value of this register - is saved in the CRYPTOCELL AO power domain. */ - __O uint32_t HOST_IOT_KDR2; /*!< This register holds bits 95:64 of K_DR. The value of this register - is saved in the CRYPTOCELL AO power domain. */ - __O uint32_t HOST_IOT_KDR3; /*!< This register holds bits 127:96 of K_DR. The value of this register - is saved in the CRYPTOCELL AO power domain. */ - __IO uint32_t HOST_IOT_LCS; /*!< Controls lifecycle state (LCS) for CRYPTOCELL subsystem */ -} NRF_CC_HOST_RGF_Type; - - -/* ================================================================================ */ -/* ================ CRYPTOCELL ================ */ -/* ================================================================================ */ - - -/** - * @brief ARM TrustZone CryptoCell register interface (CRYPTOCELL) - */ - -typedef struct { /*!< CRYPTOCELL Structure */ - __I uint32_t RESERVED0[320]; - __IO uint32_t ENABLE; /*!< Enable CRYPTOCELL subsystem */ -} NRF_CRYPTOCELL_Type; - - -/* -------------------- End of section using anonymous unions ------------------- */ -#if defined(__CC_ARM) - #pragma pop -#elif defined(__ICCARM__) - /* leave anonymous unions enabled */ -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning restore -#else - #warning Not supported compiler type -#endif - - - - -/* ================================================================================ */ -/* ================ Peripheral memory map ================ */ -/* ================================================================================ */ - -#define NRF_FICR_BASE 0x10000000UL -#define NRF_UICR_BASE 0x10001000UL -#define NRF_CLOCK_BASE 0x40000000UL -#define NRF_POWER_BASE 0x40000000UL -#define NRF_RADIO_BASE 0x40001000UL -#define NRF_UART0_BASE 0x40002000UL -#define NRF_UARTE0_BASE 0x40002000UL -#define NRF_SPI0_BASE 0x40003000UL -#define NRF_SPIM0_BASE 0x40003000UL -#define NRF_SPIS0_BASE 0x40003000UL -#define NRF_TWI0_BASE 0x40003000UL -#define NRF_TWIM0_BASE 0x40003000UL -#define NRF_TWIS0_BASE 0x40003000UL -#define NRF_SPI1_BASE 0x40004000UL -#define NRF_SPIM1_BASE 0x40004000UL -#define NRF_SPIS1_BASE 0x40004000UL -#define NRF_TWI1_BASE 0x40004000UL -#define NRF_TWIM1_BASE 0x40004000UL -#define NRF_TWIS1_BASE 0x40004000UL -#define NRF_NFCT_BASE 0x40005000UL -#define NRF_GPIOTE_BASE 0x40006000UL -#define NRF_SAADC_BASE 0x40007000UL -#define NRF_TIMER0_BASE 0x40008000UL -#define NRF_TIMER1_BASE 0x40009000UL -#define NRF_TIMER2_BASE 0x4000A000UL -#define NRF_RTC0_BASE 0x4000B000UL -#define NRF_TEMP_BASE 0x4000C000UL -#define NRF_RNG_BASE 0x4000D000UL -#define NRF_ECB_BASE 0x4000E000UL -#define NRF_AAR_BASE 0x4000F000UL -#define NRF_CCM_BASE 0x4000F000UL -#define NRF_WDT_BASE 0x40010000UL -#define NRF_RTC1_BASE 0x40011000UL -#define NRF_QDEC_BASE 0x40012000UL -#define NRF_COMP_BASE 0x40013000UL -#define NRF_LPCOMP_BASE 0x40013000UL -#define NRF_EGU0_BASE 0x40014000UL -#define NRF_SWI0_BASE 0x40014000UL -#define NRF_EGU1_BASE 0x40015000UL -#define NRF_SWI1_BASE 0x40015000UL -#define NRF_EGU2_BASE 0x40016000UL -#define NRF_SWI2_BASE 0x40016000UL -#define NRF_EGU3_BASE 0x40017000UL -#define NRF_SWI3_BASE 0x40017000UL -#define NRF_EGU4_BASE 0x40018000UL -#define NRF_SWI4_BASE 0x40018000UL -#define NRF_EGU5_BASE 0x40019000UL -#define NRF_SWI5_BASE 0x40019000UL -#define NRF_TIMER3_BASE 0x4001A000UL -#define NRF_TIMER4_BASE 0x4001B000UL -#define NRF_PWM0_BASE 0x4001C000UL -#define NRF_PDM_BASE 0x4001D000UL -#define NRF_ACL_BASE 0x4001E000UL -#define NRF_NVMC_BASE 0x4001E000UL -#define NRF_PPI_BASE 0x4001F000UL -#define NRF_MWU_BASE 0x40020000UL -#define NRF_PWM1_BASE 0x40021000UL -#define NRF_PWM2_BASE 0x40022000UL -#define NRF_SPI2_BASE 0x40023000UL -#define NRF_SPIM2_BASE 0x40023000UL -#define NRF_SPIS2_BASE 0x40023000UL -#define NRF_RTC2_BASE 0x40024000UL -#define NRF_I2S_BASE 0x40025000UL -#define NRF_FPU_BASE 0x40026000UL -#define NRF_USBD_BASE 0x40027000UL -#define NRF_UARTE1_BASE 0x40028000UL -#define NRF_QSPI_BASE 0x40029000UL -#define NRF_PWM3_BASE 0x4002D000UL -#define NRF_SPIM3_BASE 0x4002F000UL -#define NRF_P0_BASE 0x50000000UL -#define NRF_P1_BASE 0x50000300UL -#define NRF_CC_HOST_RGF_BASE 0x5002A000UL -#define NRF_CRYPTOCELL_BASE 0x5002A000UL - - -/* ================================================================================ */ -/* ================ Peripheral declaration ================ */ -/* ================================================================================ */ - -#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE) -#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE) -#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE) -#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE) -#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE) -#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE) -#define NRF_UARTE0 ((NRF_UARTE_Type *) NRF_UARTE0_BASE) -#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE) -#define NRF_SPIM0 ((NRF_SPIM_Type *) NRF_SPIM0_BASE) -#define NRF_SPIS0 ((NRF_SPIS_Type *) NRF_SPIS0_BASE) -#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE) -#define NRF_TWIM0 ((NRF_TWIM_Type *) NRF_TWIM0_BASE) -#define NRF_TWIS0 ((NRF_TWIS_Type *) NRF_TWIS0_BASE) -#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE) -#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE) -#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE) -#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE) -#define NRF_TWIM1 ((NRF_TWIM_Type *) NRF_TWIM1_BASE) -#define NRF_TWIS1 ((NRF_TWIS_Type *) NRF_TWIS1_BASE) -#define NRF_NFCT ((NRF_NFCT_Type *) NRF_NFCT_BASE) -#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE) -#define NRF_SAADC ((NRF_SAADC_Type *) NRF_SAADC_BASE) -#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE) -#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE) -#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE) -#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE) -#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE) -#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE) -#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE) -#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE) -#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE) -#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE) -#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE) -#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE) -#define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE) -#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE) -#define NRF_EGU0 ((NRF_EGU_Type *) NRF_EGU0_BASE) -#define NRF_SWI0 ((NRF_SWI_Type *) NRF_SWI0_BASE) -#define NRF_EGU1 ((NRF_EGU_Type *) NRF_EGU1_BASE) -#define NRF_SWI1 ((NRF_SWI_Type *) NRF_SWI1_BASE) -#define NRF_EGU2 ((NRF_EGU_Type *) NRF_EGU2_BASE) -#define NRF_SWI2 ((NRF_SWI_Type *) NRF_SWI2_BASE) -#define NRF_EGU3 ((NRF_EGU_Type *) NRF_EGU3_BASE) -#define NRF_SWI3 ((NRF_SWI_Type *) NRF_SWI3_BASE) -#define NRF_EGU4 ((NRF_EGU_Type *) NRF_EGU4_BASE) -#define NRF_SWI4 ((NRF_SWI_Type *) NRF_SWI4_BASE) -#define NRF_EGU5 ((NRF_EGU_Type *) NRF_EGU5_BASE) -#define NRF_SWI5 ((NRF_SWI_Type *) NRF_SWI5_BASE) -#define NRF_TIMER3 ((NRF_TIMER_Type *) NRF_TIMER3_BASE) -#define NRF_TIMER4 ((NRF_TIMER_Type *) NRF_TIMER4_BASE) -#define NRF_PWM0 ((NRF_PWM_Type *) NRF_PWM0_BASE) -#define NRF_PDM ((NRF_PDM_Type *) NRF_PDM_BASE) -#define NRF_ACL ((NRF_ACL_Type *) NRF_ACL_BASE) -#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE) -#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE) -#define NRF_MWU ((NRF_MWU_Type *) NRF_MWU_BASE) -#define NRF_PWM1 ((NRF_PWM_Type *) NRF_PWM1_BASE) -#define NRF_PWM2 ((NRF_PWM_Type *) NRF_PWM2_BASE) -#define NRF_SPI2 ((NRF_SPI_Type *) NRF_SPI2_BASE) -#define NRF_SPIM2 ((NRF_SPIM_Type *) NRF_SPIM2_BASE) -#define NRF_SPIS2 ((NRF_SPIS_Type *) NRF_SPIS2_BASE) -#define NRF_RTC2 ((NRF_RTC_Type *) NRF_RTC2_BASE) -#define NRF_I2S ((NRF_I2S_Type *) NRF_I2S_BASE) -#define NRF_FPU ((NRF_FPU_Type *) NRF_FPU_BASE) -#define NRF_USBD ((NRF_USBD_Type *) NRF_USBD_BASE) -#define NRF_UARTE1 ((NRF_UARTE_Type *) NRF_UARTE1_BASE) -#define NRF_QSPI ((NRF_QSPI_Type *) NRF_QSPI_BASE) -#define NRF_PWM3 ((NRF_PWM_Type *) NRF_PWM3_BASE) -#define NRF_SPIM3 ((NRF_SPIM_Type *) NRF_SPIM3_BASE) -#define NRF_P0 ((NRF_GPIO_Type *) NRF_P0_BASE) -#define NRF_P1 ((NRF_GPIO_Type *) NRF_P1_BASE) -#define NRF_CC_HOST_RGF ((NRF_CC_HOST_RGF_Type *) NRF_CC_HOST_RGF_BASE) -#define NRF_CRYPTOCELL ((NRF_CRYPTOCELL_Type *) NRF_CRYPTOCELL_BASE) - - -/** @} */ /* End of group Device_Peripheral_Registers */ -/** @} */ /* End of group nrf52840 */ -/** @} */ /* End of group Nordic Semiconductor */ - -#ifdef __cplusplus -} -#endif - - -#endif /* nrf52840_H */ - diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52840_xxaa.ld b/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52840_xxaa.ld deleted file mode 100644 index d29f5f64cc..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52840_xxaa.ld +++ /dev/null @@ -1,13 +0,0 @@ -/* Linker script to configure memory regions. */ - -SEARCH_DIR(.) -GROUP(-lgcc -lc -lnosys) - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x100000 - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000 -} - - -INCLUDE "nrf_common.ld" diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52_bitfields.h b/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52_bitfields.h deleted file mode 100644 index e938c051f4..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52_bitfields.h +++ /dev/null @@ -1,12663 +0,0 @@ -/* - -Copyright (c) 2010 - 2018, Nordic Semiconductor ASA - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - -2. Redistributions in binary form, except as embedded into a Nordic - Semiconductor ASA integrated circuit in a product or a software update for - such product, must reproduce the above copyright notice, this list of - conditions and the following disclaimer in the documentation and/or other - materials provided with the distribution. - -3. Neither the name of Nordic Semiconductor ASA nor the names of its - contributors may be used to endorse or promote products derived from this - software without specific prior written permission. - -4. This software, with or without modification, must only be used with a - Nordic Semiconductor ASA integrated circuit. - -5. Any software provided in binary form under this license must not be reverse - engineered, decompiled, modified and/or disassembled. - -THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS -OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*/ - -#ifndef __NRF52_BITS_H -#define __NRF52_BITS_H - -/*lint ++flb "Enter library region" */ - -/* Peripheral: AAR */ -/* Description: Accelerated Address Resolver */ - -/* Register: AAR_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */ -#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ -#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ -#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ -#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ -#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */ - -/* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */ -#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ -#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ -#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ -#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ -#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */ - -/* Bit 0 : Write '1' to Enable interrupt for END event */ -#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ -#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ -#define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ -#define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ -#define AAR_INTENSET_END_Set (1UL) /*!< Enable */ - -/* Register: AAR_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */ -#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ -#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ -#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ -#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ -#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */ - -/* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */ -#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ -#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ -#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ -#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ -#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */ - -/* Bit 0 : Write '1' to Disable interrupt for END event */ -#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ -#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ -#define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ -#define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ -#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */ - -/* Register: AAR_STATUS */ -/* Description: Resolution status */ - -/* Bits 3..0 : The IRK that was used last time an address was resolved */ -#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ -#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ - -/* Register: AAR_ENABLE */ -/* Description: Enable AAR */ - -/* Bits 1..0 : Enable or disable AAR */ -#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ -#define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */ - -/* Register: AAR_NIRK */ -/* Description: Number of IRKs */ - -/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */ -#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ -#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ - -/* Register: AAR_IRKPTR */ -/* Description: Pointer to IRK data structure */ - -/* Bits 31..0 : Pointer to the IRK data structure */ -#define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */ -#define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */ - -/* Register: AAR_ADDRPTR */ -/* Description: Pointer to the resolvable address */ - -/* Bits 31..0 : Pointer to the resolvable address (6-bytes) */ -#define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */ -#define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */ - -/* Register: AAR_SCRATCHPTR */ -/* Description: Pointer to data area used for temporary storage */ - -/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */ -#define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ -#define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ - - -/* Peripheral: BPROT */ -/* Description: Block Protect */ - -/* Register: BPROT_CONFIG0 */ -/* Description: Block protect configuration register 0 */ - -/* Bit 31 : Enable protection for region 31. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION31_Pos (31UL) /*!< Position of REGION31 field. */ -#define BPROT_CONFIG0_REGION31_Msk (0x1UL << BPROT_CONFIG0_REGION31_Pos) /*!< Bit mask of REGION31 field. */ -#define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enable */ - -/* Bit 30 : Enable protection for region 30. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION30_Pos (30UL) /*!< Position of REGION30 field. */ -#define BPROT_CONFIG0_REGION30_Msk (0x1UL << BPROT_CONFIG0_REGION30_Pos) /*!< Bit mask of REGION30 field. */ -#define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enable */ - -/* Bit 29 : Enable protection for region 29. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION29_Pos (29UL) /*!< Position of REGION29 field. */ -#define BPROT_CONFIG0_REGION29_Msk (0x1UL << BPROT_CONFIG0_REGION29_Pos) /*!< Bit mask of REGION29 field. */ -#define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enable */ - -/* Bit 28 : Enable protection for region 28. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION28_Pos (28UL) /*!< Position of REGION28 field. */ -#define BPROT_CONFIG0_REGION28_Msk (0x1UL << BPROT_CONFIG0_REGION28_Pos) /*!< Bit mask of REGION28 field. */ -#define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enable */ - -/* Bit 27 : Enable protection for region 27. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION27_Pos (27UL) /*!< Position of REGION27 field. */ -#define BPROT_CONFIG0_REGION27_Msk (0x1UL << BPROT_CONFIG0_REGION27_Pos) /*!< Bit mask of REGION27 field. */ -#define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enable */ - -/* Bit 26 : Enable protection for region 26. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION26_Pos (26UL) /*!< Position of REGION26 field. */ -#define BPROT_CONFIG0_REGION26_Msk (0x1UL << BPROT_CONFIG0_REGION26_Pos) /*!< Bit mask of REGION26 field. */ -#define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enable */ - -/* Bit 25 : Enable protection for region 25. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION25_Pos (25UL) /*!< Position of REGION25 field. */ -#define BPROT_CONFIG0_REGION25_Msk (0x1UL << BPROT_CONFIG0_REGION25_Pos) /*!< Bit mask of REGION25 field. */ -#define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enable */ - -/* Bit 24 : Enable protection for region 24. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION24_Pos (24UL) /*!< Position of REGION24 field. */ -#define BPROT_CONFIG0_REGION24_Msk (0x1UL << BPROT_CONFIG0_REGION24_Pos) /*!< Bit mask of REGION24 field. */ -#define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enable */ - -/* Bit 23 : Enable protection for region 23. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION23_Pos (23UL) /*!< Position of REGION23 field. */ -#define BPROT_CONFIG0_REGION23_Msk (0x1UL << BPROT_CONFIG0_REGION23_Pos) /*!< Bit mask of REGION23 field. */ -#define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enable */ - -/* Bit 22 : Enable protection for region 22. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION22_Pos (22UL) /*!< Position of REGION22 field. */ -#define BPROT_CONFIG0_REGION22_Msk (0x1UL << BPROT_CONFIG0_REGION22_Pos) /*!< Bit mask of REGION22 field. */ -#define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enable */ - -/* Bit 21 : Enable protection for region 21. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION21_Pos (21UL) /*!< Position of REGION21 field. */ -#define BPROT_CONFIG0_REGION21_Msk (0x1UL << BPROT_CONFIG0_REGION21_Pos) /*!< Bit mask of REGION21 field. */ -#define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enable */ - -/* Bit 20 : Enable protection for region 20. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION20_Pos (20UL) /*!< Position of REGION20 field. */ -#define BPROT_CONFIG0_REGION20_Msk (0x1UL << BPROT_CONFIG0_REGION20_Pos) /*!< Bit mask of REGION20 field. */ -#define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enable */ - -/* Bit 19 : Enable protection for region 19. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION19_Pos (19UL) /*!< Position of REGION19 field. */ -#define BPROT_CONFIG0_REGION19_Msk (0x1UL << BPROT_CONFIG0_REGION19_Pos) /*!< Bit mask of REGION19 field. */ -#define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enable */ - -/* Bit 18 : Enable protection for region 18. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION18_Pos (18UL) /*!< Position of REGION18 field. */ -#define BPROT_CONFIG0_REGION18_Msk (0x1UL << BPROT_CONFIG0_REGION18_Pos) /*!< Bit mask of REGION18 field. */ -#define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enable */ - -/* Bit 17 : Enable protection for region 17. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION17_Pos (17UL) /*!< Position of REGION17 field. */ -#define BPROT_CONFIG0_REGION17_Msk (0x1UL << BPROT_CONFIG0_REGION17_Pos) /*!< Bit mask of REGION17 field. */ -#define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enable */ - -/* Bit 16 : Enable protection for region 16. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION16_Pos (16UL) /*!< Position of REGION16 field. */ -#define BPROT_CONFIG0_REGION16_Msk (0x1UL << BPROT_CONFIG0_REGION16_Pos) /*!< Bit mask of REGION16 field. */ -#define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enable */ - -/* Bit 15 : Enable protection for region 15. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION15_Pos (15UL) /*!< Position of REGION15 field. */ -#define BPROT_CONFIG0_REGION15_Msk (0x1UL << BPROT_CONFIG0_REGION15_Pos) /*!< Bit mask of REGION15 field. */ -#define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enable */ - -/* Bit 14 : Enable protection for region 14. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION14_Pos (14UL) /*!< Position of REGION14 field. */ -#define BPROT_CONFIG0_REGION14_Msk (0x1UL << BPROT_CONFIG0_REGION14_Pos) /*!< Bit mask of REGION14 field. */ -#define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enable */ - -/* Bit 13 : Enable protection for region 13. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION13_Pos (13UL) /*!< Position of REGION13 field. */ -#define BPROT_CONFIG0_REGION13_Msk (0x1UL << BPROT_CONFIG0_REGION13_Pos) /*!< Bit mask of REGION13 field. */ -#define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enable */ - -/* Bit 12 : Enable protection for region 12. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION12_Pos (12UL) /*!< Position of REGION12 field. */ -#define BPROT_CONFIG0_REGION12_Msk (0x1UL << BPROT_CONFIG0_REGION12_Pos) /*!< Bit mask of REGION12 field. */ -#define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enable */ - -/* Bit 11 : Enable protection for region 11. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION11_Pos (11UL) /*!< Position of REGION11 field. */ -#define BPROT_CONFIG0_REGION11_Msk (0x1UL << BPROT_CONFIG0_REGION11_Pos) /*!< Bit mask of REGION11 field. */ -#define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enable */ - -/* Bit 10 : Enable protection for region 10. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION10_Pos (10UL) /*!< Position of REGION10 field. */ -#define BPROT_CONFIG0_REGION10_Msk (0x1UL << BPROT_CONFIG0_REGION10_Pos) /*!< Bit mask of REGION10 field. */ -#define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enable */ - -/* Bit 9 : Enable protection for region 9. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION9_Pos (9UL) /*!< Position of REGION9 field. */ -#define BPROT_CONFIG0_REGION9_Msk (0x1UL << BPROT_CONFIG0_REGION9_Pos) /*!< Bit mask of REGION9 field. */ -#define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enable */ - -/* Bit 8 : Enable protection for region 8. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION8_Pos (8UL) /*!< Position of REGION8 field. */ -#define BPROT_CONFIG0_REGION8_Msk (0x1UL << BPROT_CONFIG0_REGION8_Pos) /*!< Bit mask of REGION8 field. */ -#define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enable */ - -/* Bit 7 : Enable protection for region 7. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION7_Pos (7UL) /*!< Position of REGION7 field. */ -#define BPROT_CONFIG0_REGION7_Msk (0x1UL << BPROT_CONFIG0_REGION7_Pos) /*!< Bit mask of REGION7 field. */ -#define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enable */ - -/* Bit 6 : Enable protection for region 6. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION6_Pos (6UL) /*!< Position of REGION6 field. */ -#define BPROT_CONFIG0_REGION6_Msk (0x1UL << BPROT_CONFIG0_REGION6_Pos) /*!< Bit mask of REGION6 field. */ -#define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enable */ - -/* Bit 5 : Enable protection for region 5. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION5_Pos (5UL) /*!< Position of REGION5 field. */ -#define BPROT_CONFIG0_REGION5_Msk (0x1UL << BPROT_CONFIG0_REGION5_Pos) /*!< Bit mask of REGION5 field. */ -#define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enable */ - -/* Bit 4 : Enable protection for region 4. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION4_Pos (4UL) /*!< Position of REGION4 field. */ -#define BPROT_CONFIG0_REGION4_Msk (0x1UL << BPROT_CONFIG0_REGION4_Pos) /*!< Bit mask of REGION4 field. */ -#define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enable */ - -/* Bit 3 : Enable protection for region 3. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION3_Pos (3UL) /*!< Position of REGION3 field. */ -#define BPROT_CONFIG0_REGION3_Msk (0x1UL << BPROT_CONFIG0_REGION3_Pos) /*!< Bit mask of REGION3 field. */ -#define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enable */ - -/* Bit 2 : Enable protection for region 2. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */ -#define BPROT_CONFIG0_REGION2_Msk (0x1UL << BPROT_CONFIG0_REGION2_Pos) /*!< Bit mask of REGION2 field. */ -#define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enable */ - -/* Bit 1 : Enable protection for region 1. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */ -#define BPROT_CONFIG0_REGION1_Msk (0x1UL << BPROT_CONFIG0_REGION1_Pos) /*!< Bit mask of REGION1 field. */ -#define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enable */ - -/* Bit 0 : Enable protection for region 0. Write '0' has no effect. */ -#define BPROT_CONFIG0_REGION0_Pos (0UL) /*!< Position of REGION0 field. */ -#define BPROT_CONFIG0_REGION0_Msk (0x1UL << BPROT_CONFIG0_REGION0_Pos) /*!< Bit mask of REGION0 field. */ -#define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enable */ - -/* Register: BPROT_CONFIG1 */ -/* Description: Block protect configuration register 1 */ - -/* Bit 31 : Enable protection for region 63. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION63_Pos (31UL) /*!< Position of REGION63 field. */ -#define BPROT_CONFIG1_REGION63_Msk (0x1UL << BPROT_CONFIG1_REGION63_Pos) /*!< Bit mask of REGION63 field. */ -#define BPROT_CONFIG1_REGION63_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION63_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 30 : Enable protection for region 62. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION62_Pos (30UL) /*!< Position of REGION62 field. */ -#define BPROT_CONFIG1_REGION62_Msk (0x1UL << BPROT_CONFIG1_REGION62_Pos) /*!< Bit mask of REGION62 field. */ -#define BPROT_CONFIG1_REGION62_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION62_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 29 : Enable protection for region 61. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION61_Pos (29UL) /*!< Position of REGION61 field. */ -#define BPROT_CONFIG1_REGION61_Msk (0x1UL << BPROT_CONFIG1_REGION61_Pos) /*!< Bit mask of REGION61 field. */ -#define BPROT_CONFIG1_REGION61_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION61_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 28 : Enable protection for region 60. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION60_Pos (28UL) /*!< Position of REGION60 field. */ -#define BPROT_CONFIG1_REGION60_Msk (0x1UL << BPROT_CONFIG1_REGION60_Pos) /*!< Bit mask of REGION60 field. */ -#define BPROT_CONFIG1_REGION60_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION60_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 27 : Enable protection for region 59. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION59_Pos (27UL) /*!< Position of REGION59 field. */ -#define BPROT_CONFIG1_REGION59_Msk (0x1UL << BPROT_CONFIG1_REGION59_Pos) /*!< Bit mask of REGION59 field. */ -#define BPROT_CONFIG1_REGION59_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION59_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 26 : Enable protection for region 58. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION58_Pos (26UL) /*!< Position of REGION58 field. */ -#define BPROT_CONFIG1_REGION58_Msk (0x1UL << BPROT_CONFIG1_REGION58_Pos) /*!< Bit mask of REGION58 field. */ -#define BPROT_CONFIG1_REGION58_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION58_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 25 : Enable protection for region 57. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION57_Pos (25UL) /*!< Position of REGION57 field. */ -#define BPROT_CONFIG1_REGION57_Msk (0x1UL << BPROT_CONFIG1_REGION57_Pos) /*!< Bit mask of REGION57 field. */ -#define BPROT_CONFIG1_REGION57_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION57_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 24 : Enable protection for region 56. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION56_Pos (24UL) /*!< Position of REGION56 field. */ -#define BPROT_CONFIG1_REGION56_Msk (0x1UL << BPROT_CONFIG1_REGION56_Pos) /*!< Bit mask of REGION56 field. */ -#define BPROT_CONFIG1_REGION56_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION56_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 23 : Enable protection for region 55. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION55_Pos (23UL) /*!< Position of REGION55 field. */ -#define BPROT_CONFIG1_REGION55_Msk (0x1UL << BPROT_CONFIG1_REGION55_Pos) /*!< Bit mask of REGION55 field. */ -#define BPROT_CONFIG1_REGION55_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION55_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 22 : Enable protection for region 54. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION54_Pos (22UL) /*!< Position of REGION54 field. */ -#define BPROT_CONFIG1_REGION54_Msk (0x1UL << BPROT_CONFIG1_REGION54_Pos) /*!< Bit mask of REGION54 field. */ -#define BPROT_CONFIG1_REGION54_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION54_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 21 : Enable protection for region 53. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION53_Pos (21UL) /*!< Position of REGION53 field. */ -#define BPROT_CONFIG1_REGION53_Msk (0x1UL << BPROT_CONFIG1_REGION53_Pos) /*!< Bit mask of REGION53 field. */ -#define BPROT_CONFIG1_REGION53_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION53_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 20 : Enable protection for region 52. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION52_Pos (20UL) /*!< Position of REGION52 field. */ -#define BPROT_CONFIG1_REGION52_Msk (0x1UL << BPROT_CONFIG1_REGION52_Pos) /*!< Bit mask of REGION52 field. */ -#define BPROT_CONFIG1_REGION52_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION52_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 19 : Enable protection for region 51. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION51_Pos (19UL) /*!< Position of REGION51 field. */ -#define BPROT_CONFIG1_REGION51_Msk (0x1UL << BPROT_CONFIG1_REGION51_Pos) /*!< Bit mask of REGION51 field. */ -#define BPROT_CONFIG1_REGION51_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION51_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 18 : Enable protection for region 50. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION50_Pos (18UL) /*!< Position of REGION50 field. */ -#define BPROT_CONFIG1_REGION50_Msk (0x1UL << BPROT_CONFIG1_REGION50_Pos) /*!< Bit mask of REGION50 field. */ -#define BPROT_CONFIG1_REGION50_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION50_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 17 : Enable protection for region 49. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION49_Pos (17UL) /*!< Position of REGION49 field. */ -#define BPROT_CONFIG1_REGION49_Msk (0x1UL << BPROT_CONFIG1_REGION49_Pos) /*!< Bit mask of REGION49 field. */ -#define BPROT_CONFIG1_REGION49_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION49_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 16 : Enable protection for region 48. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION48_Pos (16UL) /*!< Position of REGION48 field. */ -#define BPROT_CONFIG1_REGION48_Msk (0x1UL << BPROT_CONFIG1_REGION48_Pos) /*!< Bit mask of REGION48 field. */ -#define BPROT_CONFIG1_REGION48_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION48_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 15 : Enable protection for region 47. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION47_Pos (15UL) /*!< Position of REGION47 field. */ -#define BPROT_CONFIG1_REGION47_Msk (0x1UL << BPROT_CONFIG1_REGION47_Pos) /*!< Bit mask of REGION47 field. */ -#define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 14 : Enable protection for region 46. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION46_Pos (14UL) /*!< Position of REGION46 field. */ -#define BPROT_CONFIG1_REGION46_Msk (0x1UL << BPROT_CONFIG1_REGION46_Pos) /*!< Bit mask of REGION46 field. */ -#define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 13 : Enable protection for region 45. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION45_Pos (13UL) /*!< Position of REGION45 field. */ -#define BPROT_CONFIG1_REGION45_Msk (0x1UL << BPROT_CONFIG1_REGION45_Pos) /*!< Bit mask of REGION45 field. */ -#define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 12 : Enable protection for region 44. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION44_Pos (12UL) /*!< Position of REGION44 field. */ -#define BPROT_CONFIG1_REGION44_Msk (0x1UL << BPROT_CONFIG1_REGION44_Pos) /*!< Bit mask of REGION44 field. */ -#define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 11 : Enable protection for region 43. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION43_Pos (11UL) /*!< Position of REGION43 field. */ -#define BPROT_CONFIG1_REGION43_Msk (0x1UL << BPROT_CONFIG1_REGION43_Pos) /*!< Bit mask of REGION43 field. */ -#define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 10 : Enable protection for region 42. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION42_Pos (10UL) /*!< Position of REGION42 field. */ -#define BPROT_CONFIG1_REGION42_Msk (0x1UL << BPROT_CONFIG1_REGION42_Pos) /*!< Bit mask of REGION42 field. */ -#define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 9 : Enable protection for region 41. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION41_Pos (9UL) /*!< Position of REGION41 field. */ -#define BPROT_CONFIG1_REGION41_Msk (0x1UL << BPROT_CONFIG1_REGION41_Pos) /*!< Bit mask of REGION41 field. */ -#define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 8 : Enable protection for region 40. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION40_Pos (8UL) /*!< Position of REGION40 field. */ -#define BPROT_CONFIG1_REGION40_Msk (0x1UL << BPROT_CONFIG1_REGION40_Pos) /*!< Bit mask of REGION40 field. */ -#define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 7 : Enable protection for region 39. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION39_Pos (7UL) /*!< Position of REGION39 field. */ -#define BPROT_CONFIG1_REGION39_Msk (0x1UL << BPROT_CONFIG1_REGION39_Pos) /*!< Bit mask of REGION39 field. */ -#define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 6 : Enable protection for region 38. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION38_Pos (6UL) /*!< Position of REGION38 field. */ -#define BPROT_CONFIG1_REGION38_Msk (0x1UL << BPROT_CONFIG1_REGION38_Pos) /*!< Bit mask of REGION38 field. */ -#define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 5 : Enable protection for region 37. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION37_Pos (5UL) /*!< Position of REGION37 field. */ -#define BPROT_CONFIG1_REGION37_Msk (0x1UL << BPROT_CONFIG1_REGION37_Pos) /*!< Bit mask of REGION37 field. */ -#define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 4 : Enable protection for region 36. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION36_Pos (4UL) /*!< Position of REGION36 field. */ -#define BPROT_CONFIG1_REGION36_Msk (0x1UL << BPROT_CONFIG1_REGION36_Pos) /*!< Bit mask of REGION36 field. */ -#define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 3 : Enable protection for region 35. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION35_Pos (3UL) /*!< Position of REGION35 field. */ -#define BPROT_CONFIG1_REGION35_Msk (0x1UL << BPROT_CONFIG1_REGION35_Pos) /*!< Bit mask of REGION35 field. */ -#define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 2 : Enable protection for region 34. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */ -#define BPROT_CONFIG1_REGION34_Msk (0x1UL << BPROT_CONFIG1_REGION34_Pos) /*!< Bit mask of REGION34 field. */ -#define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 1 : Enable protection for region 33. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */ -#define BPROT_CONFIG1_REGION33_Msk (0x1UL << BPROT_CONFIG1_REGION33_Pos) /*!< Bit mask of REGION33 field. */ -#define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 0 : Enable protection for region 32. Write '0' has no effect. */ -#define BPROT_CONFIG1_REGION32_Pos (0UL) /*!< Position of REGION32 field. */ -#define BPROT_CONFIG1_REGION32_Msk (0x1UL << BPROT_CONFIG1_REGION32_Pos) /*!< Bit mask of REGION32 field. */ -#define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */ - -/* Register: BPROT_DISABLEINDEBUG */ -/* Description: Disable protection mechanism in debug interface mode */ - -/* Bit 0 : Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode. */ -#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */ -#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */ -#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enable in debug */ -#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disable in debug */ - -/* Register: BPROT_CONFIG2 */ -/* Description: Block protect configuration register 2 */ - -/* Bit 31 : Enable protection for region 95. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION95_Pos (31UL) /*!< Position of REGION95 field. */ -#define BPROT_CONFIG2_REGION95_Msk (0x1UL << BPROT_CONFIG2_REGION95_Pos) /*!< Bit mask of REGION95 field. */ -#define BPROT_CONFIG2_REGION95_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION95_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 30 : Enable protection for region 94. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION94_Pos (30UL) /*!< Position of REGION94 field. */ -#define BPROT_CONFIG2_REGION94_Msk (0x1UL << BPROT_CONFIG2_REGION94_Pos) /*!< Bit mask of REGION94 field. */ -#define BPROT_CONFIG2_REGION94_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION94_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 29 : Enable protection for region 93. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION93_Pos (29UL) /*!< Position of REGION93 field. */ -#define BPROT_CONFIG2_REGION93_Msk (0x1UL << BPROT_CONFIG2_REGION93_Pos) /*!< Bit mask of REGION93 field. */ -#define BPROT_CONFIG2_REGION93_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION93_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 28 : Enable protection for region 92. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION92_Pos (28UL) /*!< Position of REGION92 field. */ -#define BPROT_CONFIG2_REGION92_Msk (0x1UL << BPROT_CONFIG2_REGION92_Pos) /*!< Bit mask of REGION92 field. */ -#define BPROT_CONFIG2_REGION92_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION92_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 27 : Enable protection for region 91. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION91_Pos (27UL) /*!< Position of REGION91 field. */ -#define BPROT_CONFIG2_REGION91_Msk (0x1UL << BPROT_CONFIG2_REGION91_Pos) /*!< Bit mask of REGION91 field. */ -#define BPROT_CONFIG2_REGION91_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION91_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 26 : Enable protection for region 90. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION90_Pos (26UL) /*!< Position of REGION90 field. */ -#define BPROT_CONFIG2_REGION90_Msk (0x1UL << BPROT_CONFIG2_REGION90_Pos) /*!< Bit mask of REGION90 field. */ -#define BPROT_CONFIG2_REGION90_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION90_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 25 : Enable protection for region 89. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION89_Pos (25UL) /*!< Position of REGION89 field. */ -#define BPROT_CONFIG2_REGION89_Msk (0x1UL << BPROT_CONFIG2_REGION89_Pos) /*!< Bit mask of REGION89 field. */ -#define BPROT_CONFIG2_REGION89_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION89_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 24 : Enable protection for region 88. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION88_Pos (24UL) /*!< Position of REGION88 field. */ -#define BPROT_CONFIG2_REGION88_Msk (0x1UL << BPROT_CONFIG2_REGION88_Pos) /*!< Bit mask of REGION88 field. */ -#define BPROT_CONFIG2_REGION88_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION88_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 23 : Enable protection for region 87. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION87_Pos (23UL) /*!< Position of REGION87 field. */ -#define BPROT_CONFIG2_REGION87_Msk (0x1UL << BPROT_CONFIG2_REGION87_Pos) /*!< Bit mask of REGION87 field. */ -#define BPROT_CONFIG2_REGION87_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION87_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 22 : Enable protection for region 86. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION86_Pos (22UL) /*!< Position of REGION86 field. */ -#define BPROT_CONFIG2_REGION86_Msk (0x1UL << BPROT_CONFIG2_REGION86_Pos) /*!< Bit mask of REGION86 field. */ -#define BPROT_CONFIG2_REGION86_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION86_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 21 : Enable protection for region 85. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION85_Pos (21UL) /*!< Position of REGION85 field. */ -#define BPROT_CONFIG2_REGION85_Msk (0x1UL << BPROT_CONFIG2_REGION85_Pos) /*!< Bit mask of REGION85 field. */ -#define BPROT_CONFIG2_REGION85_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION85_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 20 : Enable protection for region 84. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION84_Pos (20UL) /*!< Position of REGION84 field. */ -#define BPROT_CONFIG2_REGION84_Msk (0x1UL << BPROT_CONFIG2_REGION84_Pos) /*!< Bit mask of REGION84 field. */ -#define BPROT_CONFIG2_REGION84_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION84_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 19 : Enable protection for region 83. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION83_Pos (19UL) /*!< Position of REGION83 field. */ -#define BPROT_CONFIG2_REGION83_Msk (0x1UL << BPROT_CONFIG2_REGION83_Pos) /*!< Bit mask of REGION83 field. */ -#define BPROT_CONFIG2_REGION83_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION83_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 18 : Enable protection for region 82. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION82_Pos (18UL) /*!< Position of REGION82 field. */ -#define BPROT_CONFIG2_REGION82_Msk (0x1UL << BPROT_CONFIG2_REGION82_Pos) /*!< Bit mask of REGION82 field. */ -#define BPROT_CONFIG2_REGION82_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION82_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 17 : Enable protection for region 81. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION81_Pos (17UL) /*!< Position of REGION81 field. */ -#define BPROT_CONFIG2_REGION81_Msk (0x1UL << BPROT_CONFIG2_REGION81_Pos) /*!< Bit mask of REGION81 field. */ -#define BPROT_CONFIG2_REGION81_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION81_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 16 : Enable protection for region 80. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION80_Pos (16UL) /*!< Position of REGION80 field. */ -#define BPROT_CONFIG2_REGION80_Msk (0x1UL << BPROT_CONFIG2_REGION80_Pos) /*!< Bit mask of REGION80 field. */ -#define BPROT_CONFIG2_REGION80_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION80_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 15 : Enable protection for region 79. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION79_Pos (15UL) /*!< Position of REGION79 field. */ -#define BPROT_CONFIG2_REGION79_Msk (0x1UL << BPROT_CONFIG2_REGION79_Pos) /*!< Bit mask of REGION79 field. */ -#define BPROT_CONFIG2_REGION79_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION79_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 14 : Enable protection for region 78. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION78_Pos (14UL) /*!< Position of REGION78 field. */ -#define BPROT_CONFIG2_REGION78_Msk (0x1UL << BPROT_CONFIG2_REGION78_Pos) /*!< Bit mask of REGION78 field. */ -#define BPROT_CONFIG2_REGION78_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION78_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 13 : Enable protection for region 77. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION77_Pos (13UL) /*!< Position of REGION77 field. */ -#define BPROT_CONFIG2_REGION77_Msk (0x1UL << BPROT_CONFIG2_REGION77_Pos) /*!< Bit mask of REGION77 field. */ -#define BPROT_CONFIG2_REGION77_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION77_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 12 : Enable protection for region 76. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION76_Pos (12UL) /*!< Position of REGION76 field. */ -#define BPROT_CONFIG2_REGION76_Msk (0x1UL << BPROT_CONFIG2_REGION76_Pos) /*!< Bit mask of REGION76 field. */ -#define BPROT_CONFIG2_REGION76_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION76_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 11 : Enable protection for region 75. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION75_Pos (11UL) /*!< Position of REGION75 field. */ -#define BPROT_CONFIG2_REGION75_Msk (0x1UL << BPROT_CONFIG2_REGION75_Pos) /*!< Bit mask of REGION75 field. */ -#define BPROT_CONFIG2_REGION75_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION75_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 10 : Enable protection for region 74. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION74_Pos (10UL) /*!< Position of REGION74 field. */ -#define BPROT_CONFIG2_REGION74_Msk (0x1UL << BPROT_CONFIG2_REGION74_Pos) /*!< Bit mask of REGION74 field. */ -#define BPROT_CONFIG2_REGION74_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION74_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 9 : Enable protection for region 73. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION73_Pos (9UL) /*!< Position of REGION73 field. */ -#define BPROT_CONFIG2_REGION73_Msk (0x1UL << BPROT_CONFIG2_REGION73_Pos) /*!< Bit mask of REGION73 field. */ -#define BPROT_CONFIG2_REGION73_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION73_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 8 : Enable protection for region 72. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION72_Pos (8UL) /*!< Position of REGION72 field. */ -#define BPROT_CONFIG2_REGION72_Msk (0x1UL << BPROT_CONFIG2_REGION72_Pos) /*!< Bit mask of REGION72 field. */ -#define BPROT_CONFIG2_REGION72_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION72_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 7 : Enable protection for region 71. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION71_Pos (7UL) /*!< Position of REGION71 field. */ -#define BPROT_CONFIG2_REGION71_Msk (0x1UL << BPROT_CONFIG2_REGION71_Pos) /*!< Bit mask of REGION71 field. */ -#define BPROT_CONFIG2_REGION71_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION71_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 6 : Enable protection for region 70. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION70_Pos (6UL) /*!< Position of REGION70 field. */ -#define BPROT_CONFIG2_REGION70_Msk (0x1UL << BPROT_CONFIG2_REGION70_Pos) /*!< Bit mask of REGION70 field. */ -#define BPROT_CONFIG2_REGION70_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION70_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 5 : Enable protection for region 69. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION69_Pos (5UL) /*!< Position of REGION69 field. */ -#define BPROT_CONFIG2_REGION69_Msk (0x1UL << BPROT_CONFIG2_REGION69_Pos) /*!< Bit mask of REGION69 field. */ -#define BPROT_CONFIG2_REGION69_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION69_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 4 : Enable protection for region 68. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION68_Pos (4UL) /*!< Position of REGION68 field. */ -#define BPROT_CONFIG2_REGION68_Msk (0x1UL << BPROT_CONFIG2_REGION68_Pos) /*!< Bit mask of REGION68 field. */ -#define BPROT_CONFIG2_REGION68_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION68_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 3 : Enable protection for region 67. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION67_Pos (3UL) /*!< Position of REGION67 field. */ -#define BPROT_CONFIG2_REGION67_Msk (0x1UL << BPROT_CONFIG2_REGION67_Pos) /*!< Bit mask of REGION67 field. */ -#define BPROT_CONFIG2_REGION67_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION67_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 2 : Enable protection for region 66. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION66_Pos (2UL) /*!< Position of REGION66 field. */ -#define BPROT_CONFIG2_REGION66_Msk (0x1UL << BPROT_CONFIG2_REGION66_Pos) /*!< Bit mask of REGION66 field. */ -#define BPROT_CONFIG2_REGION66_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION66_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 1 : Enable protection for region 65. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION65_Pos (1UL) /*!< Position of REGION65 field. */ -#define BPROT_CONFIG2_REGION65_Msk (0x1UL << BPROT_CONFIG2_REGION65_Pos) /*!< Bit mask of REGION65 field. */ -#define BPROT_CONFIG2_REGION65_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION65_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 0 : Enable protection for region 64. Write '0' has no effect. */ -#define BPROT_CONFIG2_REGION64_Pos (0UL) /*!< Position of REGION64 field. */ -#define BPROT_CONFIG2_REGION64_Msk (0x1UL << BPROT_CONFIG2_REGION64_Pos) /*!< Bit mask of REGION64 field. */ -#define BPROT_CONFIG2_REGION64_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG2_REGION64_Enabled (1UL) /*!< Protection enabled */ - -/* Register: BPROT_CONFIG3 */ -/* Description: Block protect configuration register 3 */ - -/* Bit 31 : Enable protection for region 127. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION127_Pos (31UL) /*!< Position of REGION127 field. */ -#define BPROT_CONFIG3_REGION127_Msk (0x1UL << BPROT_CONFIG3_REGION127_Pos) /*!< Bit mask of REGION127 field. */ -#define BPROT_CONFIG3_REGION127_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION127_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 30 : Enable protection for region 126. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION126_Pos (30UL) /*!< Position of REGION126 field. */ -#define BPROT_CONFIG3_REGION126_Msk (0x1UL << BPROT_CONFIG3_REGION126_Pos) /*!< Bit mask of REGION126 field. */ -#define BPROT_CONFIG3_REGION126_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION126_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 29 : Enable protection for region 125. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION125_Pos (29UL) /*!< Position of REGION125 field. */ -#define BPROT_CONFIG3_REGION125_Msk (0x1UL << BPROT_CONFIG3_REGION125_Pos) /*!< Bit mask of REGION125 field. */ -#define BPROT_CONFIG3_REGION125_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION125_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 28 : Enable protection for region 124. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION124_Pos (28UL) /*!< Position of REGION124 field. */ -#define BPROT_CONFIG3_REGION124_Msk (0x1UL << BPROT_CONFIG3_REGION124_Pos) /*!< Bit mask of REGION124 field. */ -#define BPROT_CONFIG3_REGION124_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION124_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 27 : Enable protection for region 123. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION123_Pos (27UL) /*!< Position of REGION123 field. */ -#define BPROT_CONFIG3_REGION123_Msk (0x1UL << BPROT_CONFIG3_REGION123_Pos) /*!< Bit mask of REGION123 field. */ -#define BPROT_CONFIG3_REGION123_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION123_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 26 : Enable protection for region 122. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION122_Pos (26UL) /*!< Position of REGION122 field. */ -#define BPROT_CONFIG3_REGION122_Msk (0x1UL << BPROT_CONFIG3_REGION122_Pos) /*!< Bit mask of REGION122 field. */ -#define BPROT_CONFIG3_REGION122_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION122_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 25 : Enable protection for region 121. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION121_Pos (25UL) /*!< Position of REGION121 field. */ -#define BPROT_CONFIG3_REGION121_Msk (0x1UL << BPROT_CONFIG3_REGION121_Pos) /*!< Bit mask of REGION121 field. */ -#define BPROT_CONFIG3_REGION121_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION121_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 24 : Enable protection for region 120. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION120_Pos (24UL) /*!< Position of REGION120 field. */ -#define BPROT_CONFIG3_REGION120_Msk (0x1UL << BPROT_CONFIG3_REGION120_Pos) /*!< Bit mask of REGION120 field. */ -#define BPROT_CONFIG3_REGION120_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION120_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 23 : Enable protection for region 119. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION119_Pos (23UL) /*!< Position of REGION119 field. */ -#define BPROT_CONFIG3_REGION119_Msk (0x1UL << BPROT_CONFIG3_REGION119_Pos) /*!< Bit mask of REGION119 field. */ -#define BPROT_CONFIG3_REGION119_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION119_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 22 : Enable protection for region 118. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION118_Pos (22UL) /*!< Position of REGION118 field. */ -#define BPROT_CONFIG3_REGION118_Msk (0x1UL << BPROT_CONFIG3_REGION118_Pos) /*!< Bit mask of REGION118 field. */ -#define BPROT_CONFIG3_REGION118_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION118_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 21 : Enable protection for region 117. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION117_Pos (21UL) /*!< Position of REGION117 field. */ -#define BPROT_CONFIG3_REGION117_Msk (0x1UL << BPROT_CONFIG3_REGION117_Pos) /*!< Bit mask of REGION117 field. */ -#define BPROT_CONFIG3_REGION117_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION117_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 20 : Enable protection for region 116. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION116_Pos (20UL) /*!< Position of REGION116 field. */ -#define BPROT_CONFIG3_REGION116_Msk (0x1UL << BPROT_CONFIG3_REGION116_Pos) /*!< Bit mask of REGION116 field. */ -#define BPROT_CONFIG3_REGION116_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION116_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 19 : Enable protection for region 115. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION115_Pos (19UL) /*!< Position of REGION115 field. */ -#define BPROT_CONFIG3_REGION115_Msk (0x1UL << BPROT_CONFIG3_REGION115_Pos) /*!< Bit mask of REGION115 field. */ -#define BPROT_CONFIG3_REGION115_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION115_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 18 : Enable protection for region 114. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION114_Pos (18UL) /*!< Position of REGION114 field. */ -#define BPROT_CONFIG3_REGION114_Msk (0x1UL << BPROT_CONFIG3_REGION114_Pos) /*!< Bit mask of REGION114 field. */ -#define BPROT_CONFIG3_REGION114_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION114_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 17 : Enable protection for region 113. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION113_Pos (17UL) /*!< Position of REGION113 field. */ -#define BPROT_CONFIG3_REGION113_Msk (0x1UL << BPROT_CONFIG3_REGION113_Pos) /*!< Bit mask of REGION113 field. */ -#define BPROT_CONFIG3_REGION113_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION113_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 16 : Enable protection for region 112. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION112_Pos (16UL) /*!< Position of REGION112 field. */ -#define BPROT_CONFIG3_REGION112_Msk (0x1UL << BPROT_CONFIG3_REGION112_Pos) /*!< Bit mask of REGION112 field. */ -#define BPROT_CONFIG3_REGION112_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION112_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 15 : Enable protection for region 111. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION111_Pos (15UL) /*!< Position of REGION111 field. */ -#define BPROT_CONFIG3_REGION111_Msk (0x1UL << BPROT_CONFIG3_REGION111_Pos) /*!< Bit mask of REGION111 field. */ -#define BPROT_CONFIG3_REGION111_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION111_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 14 : Enable protection for region 110. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION110_Pos (14UL) /*!< Position of REGION110 field. */ -#define BPROT_CONFIG3_REGION110_Msk (0x1UL << BPROT_CONFIG3_REGION110_Pos) /*!< Bit mask of REGION110 field. */ -#define BPROT_CONFIG3_REGION110_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION110_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 13 : Enable protection for region 109. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION109_Pos (13UL) /*!< Position of REGION109 field. */ -#define BPROT_CONFIG3_REGION109_Msk (0x1UL << BPROT_CONFIG3_REGION109_Pos) /*!< Bit mask of REGION109 field. */ -#define BPROT_CONFIG3_REGION109_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION109_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 12 : Enable protection for region 108. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION108_Pos (12UL) /*!< Position of REGION108 field. */ -#define BPROT_CONFIG3_REGION108_Msk (0x1UL << BPROT_CONFIG3_REGION108_Pos) /*!< Bit mask of REGION108 field. */ -#define BPROT_CONFIG3_REGION108_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION108_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 11 : Enable protection for region 107. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION107_Pos (11UL) /*!< Position of REGION107 field. */ -#define BPROT_CONFIG3_REGION107_Msk (0x1UL << BPROT_CONFIG3_REGION107_Pos) /*!< Bit mask of REGION107 field. */ -#define BPROT_CONFIG3_REGION107_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION107_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 10 : Enable protection for region 106. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION106_Pos (10UL) /*!< Position of REGION106 field. */ -#define BPROT_CONFIG3_REGION106_Msk (0x1UL << BPROT_CONFIG3_REGION106_Pos) /*!< Bit mask of REGION106 field. */ -#define BPROT_CONFIG3_REGION106_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION106_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 9 : Enable protection for region 105. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION105_Pos (9UL) /*!< Position of REGION105 field. */ -#define BPROT_CONFIG3_REGION105_Msk (0x1UL << BPROT_CONFIG3_REGION105_Pos) /*!< Bit mask of REGION105 field. */ -#define BPROT_CONFIG3_REGION105_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION105_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 8 : Enable protection for region 104. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION104_Pos (8UL) /*!< Position of REGION104 field. */ -#define BPROT_CONFIG3_REGION104_Msk (0x1UL << BPROT_CONFIG3_REGION104_Pos) /*!< Bit mask of REGION104 field. */ -#define BPROT_CONFIG3_REGION104_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION104_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 7 : Enable protection for region 103. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION103_Pos (7UL) /*!< Position of REGION103 field. */ -#define BPROT_CONFIG3_REGION103_Msk (0x1UL << BPROT_CONFIG3_REGION103_Pos) /*!< Bit mask of REGION103 field. */ -#define BPROT_CONFIG3_REGION103_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION103_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 6 : Enable protection for region 102. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION102_Pos (6UL) /*!< Position of REGION102 field. */ -#define BPROT_CONFIG3_REGION102_Msk (0x1UL << BPROT_CONFIG3_REGION102_Pos) /*!< Bit mask of REGION102 field. */ -#define BPROT_CONFIG3_REGION102_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION102_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 5 : Enable protection for region 101. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION101_Pos (5UL) /*!< Position of REGION101 field. */ -#define BPROT_CONFIG3_REGION101_Msk (0x1UL << BPROT_CONFIG3_REGION101_Pos) /*!< Bit mask of REGION101 field. */ -#define BPROT_CONFIG3_REGION101_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION101_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 4 : Enable protection for region 100. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION100_Pos (4UL) /*!< Position of REGION100 field. */ -#define BPROT_CONFIG3_REGION100_Msk (0x1UL << BPROT_CONFIG3_REGION100_Pos) /*!< Bit mask of REGION100 field. */ -#define BPROT_CONFIG3_REGION100_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION100_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 3 : Enable protection for region 99. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION99_Pos (3UL) /*!< Position of REGION99 field. */ -#define BPROT_CONFIG3_REGION99_Msk (0x1UL << BPROT_CONFIG3_REGION99_Pos) /*!< Bit mask of REGION99 field. */ -#define BPROT_CONFIG3_REGION99_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION99_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 2 : Enable protection for region 98. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION98_Pos (2UL) /*!< Position of REGION98 field. */ -#define BPROT_CONFIG3_REGION98_Msk (0x1UL << BPROT_CONFIG3_REGION98_Pos) /*!< Bit mask of REGION98 field. */ -#define BPROT_CONFIG3_REGION98_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION98_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 1 : Enable protection for region 97. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION97_Pos (1UL) /*!< Position of REGION97 field. */ -#define BPROT_CONFIG3_REGION97_Msk (0x1UL << BPROT_CONFIG3_REGION97_Pos) /*!< Bit mask of REGION97 field. */ -#define BPROT_CONFIG3_REGION97_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION97_Enabled (1UL) /*!< Protection enabled */ - -/* Bit 0 : Enable protection for region 96. Write '0' has no effect. */ -#define BPROT_CONFIG3_REGION96_Pos (0UL) /*!< Position of REGION96 field. */ -#define BPROT_CONFIG3_REGION96_Msk (0x1UL << BPROT_CONFIG3_REGION96_Pos) /*!< Bit mask of REGION96 field. */ -#define BPROT_CONFIG3_REGION96_Disabled (0UL) /*!< Protection disabled */ -#define BPROT_CONFIG3_REGION96_Enabled (1UL) /*!< Protection enabled */ - - -/* Peripheral: CCM */ -/* Description: AES CCM Mode Encryption */ - -/* Register: CCM_SHORTS */ -/* Description: Shortcut register */ - -/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */ -#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ -#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ -#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */ -#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */ - -/* Register: CCM_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 2 : Write '1' to Enable interrupt for ERROR event */ -#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ -#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ -#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ -#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */ - -/* Bit 1 : Write '1' to Enable interrupt for ENDCRYPT event */ -#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ -#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ -#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ -#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ -#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */ - -/* Bit 0 : Write '1' to Enable interrupt for ENDKSGEN event */ -#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ -#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ -#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ -#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ -#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */ - -/* Register: CCM_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 2 : Write '1' to Disable interrupt for ERROR event */ -#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ -#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ -#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ -#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ - -/* Bit 1 : Write '1' to Disable interrupt for ENDCRYPT event */ -#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ -#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ -#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ -#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ -#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */ - -/* Bit 0 : Write '1' to Disable interrupt for ENDKSGEN event */ -#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ -#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ -#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ -#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ -#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */ - -/* Register: CCM_MICSTATUS */ -/* Description: MIC check result */ - -/* Bit 0 : The result of the MIC check performed during the previous decryption operation */ -#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */ -#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */ -#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */ -#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */ - -/* Register: CCM_ENABLE */ -/* Description: Enable */ - -/* Bits 1..0 : Enable or disable CCM */ -#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ -#define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ - -/* Register: CCM_MODE */ -/* Description: Operation mode */ - -/* Bit 24 : Packet length configuration */ -#define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */ -#define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */ -#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field is 5-bit */ -#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field is 8-bit */ - -/* Bit 16 : Data rate that the CCM shall run in synch with */ -#define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */ -#define CCM_MODE_DATARATE_Msk (0x1UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */ -#define CCM_MODE_DATARATE_1Mbit (0UL) /*!< In synch with 1 Mbit data rate */ -#define CCM_MODE_DATARATE_2Mbit (1UL) /*!< In synch with 2 Mbit data rate */ - -/* Bit 0 : The mode of operation to be used */ -#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ -#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ -#define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */ -#define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */ - -/* Register: CCM_CNFPTR */ -/* Description: Pointer to data structure holding AES key and NONCE vector */ - -/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */ -#define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */ -#define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */ - -/* Register: CCM_INPTR */ -/* Description: Input pointer */ - -/* Bits 31..0 : Input pointer */ -#define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */ -#define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */ - -/* Register: CCM_OUTPTR */ -/* Description: Output pointer */ - -/* Bits 31..0 : Output pointer */ -#define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */ -#define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */ - -/* Register: CCM_SCRATCHPTR */ -/* Description: Pointer to data area used for temporary storage */ - -/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. */ -#define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ -#define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ - - -/* Peripheral: CLOCK */ -/* Description: Clock control */ - -/* Register: CLOCK_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 4 : Write '1' to Enable interrupt for CTTO event */ -#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ -#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ -#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */ -#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */ -#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */ - -/* Bit 3 : Write '1' to Enable interrupt for DONE event */ -#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ -#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ -#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ -#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ -#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */ - -/* Bit 1 : Write '1' to Enable interrupt for LFCLKSTARTED event */ -#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ -#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ -#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */ - -/* Bit 0 : Write '1' to Enable interrupt for HFCLKSTARTED event */ -#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ -#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ -#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */ - -/* Register: CLOCK_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 4 : Write '1' to Disable interrupt for CTTO event */ -#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ -#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ -#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */ -#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */ -#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */ - -/* Bit 3 : Write '1' to Disable interrupt for DONE event */ -#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ -#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ -#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ -#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ -#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */ - -/* Bit 1 : Write '1' to Disable interrupt for LFCLKSTARTED event */ -#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ -#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ -#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */ - -/* Bit 0 : Write '1' to Disable interrupt for HFCLKSTARTED event */ -#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ -#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ -#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */ - -/* Register: CLOCK_HFCLKRUN */ -/* Description: Status indicating that HFCLKSTART task has been triggered */ - -/* Bit 0 : HFCLKSTART task triggered or not */ -#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ -#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ -#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ -#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ - -/* Register: CLOCK_HFCLKSTAT */ -/* Description: HFCLK status */ - -/* Bit 16 : HFCLK state */ -#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ -#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ -#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */ -#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */ - -/* Bit 0 : Source of HFCLK */ -#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ -#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */ -#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */ - -/* Register: CLOCK_LFCLKRUN */ -/* Description: Status indicating that LFCLKSTART task has been triggered */ - -/* Bit 0 : LFCLKSTART task triggered or not */ -#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ -#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ -#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ -#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ - -/* Register: CLOCK_LFCLKSTAT */ -/* Description: LFCLK status */ - -/* Bit 16 : LFCLK state */ -#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ -#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ -#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */ -#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */ - -/* Bits 1..0 : Source of LFCLK */ -#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ -#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ -#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ -#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ - -/* Register: CLOCK_LFCLKSRCCOPY */ -/* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ - -/* Bits 1..0 : Clock source */ -#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ -#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ -#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ -#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ - -/* Register: CLOCK_LFCLKSRC */ -/* Description: Clock source for the LFCLK */ - -/* Bit 17 : Enable or disable external source for LFCLK */ -#define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */ -#define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */ -#define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */ -#define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */ - -/* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */ -#define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */ -#define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */ -#define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */ -#define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */ - -/* Bits 1..0 : Clock source */ -#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ -#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ -#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ -#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ - -/* Register: CLOCK_CTIV */ -/* Description: Calibration timer interval */ - -/* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */ -#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */ -#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */ - -/* Register: CLOCK_TRACECONFIG */ -/* Description: Clocking options for the Trace Port debug interface */ - -/* Bits 17..16 : Pin multiplexing of trace signals. */ -#define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */ -#define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */ -#define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< GPIOs multiplexed onto all trace-pins */ -#define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins */ -#define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. */ - -/* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */ -#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */ -#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */ -#define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */ -#define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */ -#define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */ -#define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */ - - -/* Peripheral: COMP */ -/* Description: Comparator */ - -/* Register: COMP_SHORTS */ -/* Description: Shortcut register */ - -/* Bit 4 : Shortcut between CROSS event and STOP task */ -#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ -#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ -#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 3 : Shortcut between UP event and STOP task */ -#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ -#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ -#define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 2 : Shortcut between DOWN event and STOP task */ -#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ -#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ -#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 1 : Shortcut between READY event and STOP task */ -#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ -#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ -#define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 0 : Shortcut between READY event and SAMPLE task */ -#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ -#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ -#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ -#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */ - -/* Register: COMP_INTEN */ -/* Description: Enable or disable interrupt */ - -/* Bit 3 : Enable or disable interrupt for CROSS event */ -#define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */ -#define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */ -#define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */ -#define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */ - -/* Bit 2 : Enable or disable interrupt for UP event */ -#define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */ -#define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */ -#define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */ -#define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */ - -/* Bit 1 : Enable or disable interrupt for DOWN event */ -#define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */ -#define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */ -#define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */ -#define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */ - -/* Bit 0 : Enable or disable interrupt for READY event */ -#define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ -#define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */ -#define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */ -#define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */ - -/* Register: COMP_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 3 : Write '1' to Enable interrupt for CROSS event */ -#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ -#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ -#define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ -#define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ -#define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ - -/* Bit 2 : Write '1' to Enable interrupt for UP event */ -#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ -#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ -#define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ -#define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ -#define COMP_INTENSET_UP_Set (1UL) /*!< Enable */ - -/* Bit 1 : Write '1' to Enable interrupt for DOWN event */ -#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ -#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ -#define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ -#define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ -#define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ - -/* Bit 0 : Write '1' to Enable interrupt for READY event */ -#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ -#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ -#define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ -#define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ -#define COMP_INTENSET_READY_Set (1UL) /*!< Enable */ - -/* Register: COMP_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 3 : Write '1' to Disable interrupt for CROSS event */ -#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ -#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ -#define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ -#define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ -#define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ - -/* Bit 2 : Write '1' to Disable interrupt for UP event */ -#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ -#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ -#define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ -#define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ -#define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ - -/* Bit 1 : Write '1' to Disable interrupt for DOWN event */ -#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ -#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ -#define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ -#define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ -#define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ - -/* Bit 0 : Write '1' to Disable interrupt for READY event */ -#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ -#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ -#define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ -#define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ -#define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */ - -/* Register: COMP_RESULT */ -/* Description: Compare result */ - -/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ -#define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ -#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ -#define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ < VIN-) */ -#define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ > VIN-) */ - -/* Register: COMP_ENABLE */ -/* Description: COMP enable */ - -/* Bits 1..0 : Enable or disable COMP */ -#define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ -#define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ - -/* Register: COMP_PSEL */ -/* Description: Pin select */ - -/* Bits 2..0 : Analog pin select */ -#define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ -#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ -#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */ -#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */ -#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */ -#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */ -#define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */ -#define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */ -#define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */ -#define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */ - -/* Register: COMP_REFSEL */ -/* Description: Reference source select for single-ended mode */ - -/* Bits 2..0 : Reference select */ -#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ -#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ -#define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD >= 1.7 V) */ -#define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) */ -#define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) */ -#define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */ -#define COMP_REFSEL_REFSEL_ARef (7UL) /*!< VREF = AREF (VDD >= VREF >= AREFMIN) */ - -/* Register: COMP_EXTREFSEL */ -/* Description: External reference select */ - -/* Bits 2..0 : External analog reference select */ -#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ -#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x7UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (2UL) /*!< Use AIN2 as external analog reference */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3 (3UL) /*!< Use AIN3 as external analog reference */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference4 (4UL) /*!< Use AIN4 as external analog reference */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference5 (5UL) /*!< Use AIN5 as external analog reference */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference6 (6UL) /*!< Use AIN6 as external analog reference */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference7 (7UL) /*!< Use AIN7 as external analog reference */ - -/* Register: COMP_TH */ -/* Description: Threshold configuration for hysteresis unit */ - -/* Bits 13..8 : VUP = (THUP+1)/64*VREF */ -#define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */ -#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */ - -/* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */ -#define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */ -#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */ - -/* Register: COMP_MODE */ -/* Description: Mode configuration */ - -/* Bit 8 : Main operation modes */ -#define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */ -#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */ -#define COMP_MODE_MAIN_SE (0UL) /*!< Single-ended mode */ -#define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */ - -/* Bits 1..0 : Speed and power modes */ -#define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */ -#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */ -#define COMP_MODE_SP_Low (0UL) /*!< Low-power mode */ -#define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */ -#define COMP_MODE_SP_High (2UL) /*!< High-speed mode */ - -/* Register: COMP_HYST */ -/* Description: Comparator hysteresis enable */ - -/* Bit 0 : Comparator hysteresis */ -#define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */ -#define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */ -#define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */ -#define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */ - -/* Register: COMP_ISOURCE */ -/* Description: Current source select on analog input */ - -/* Bits 1..0 : Comparator hysteresis */ -#define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */ -#define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */ -#define COMP_ISOURCE_ISOURCE_Off (0UL) /*!< Current source disabled */ -#define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */ -#define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */ -#define COMP_ISOURCE_ISOURCE_Ien10mA (3UL) /*!< Current source enabled (+/- 10 uA) */ - - -/* Peripheral: ECB */ -/* Description: AES ECB Mode Encryption */ - -/* Register: ECB_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 1 : Write '1' to Enable interrupt for ERRORECB event */ -#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ -#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ -#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ -#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ -#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */ - -/* Bit 0 : Write '1' to Enable interrupt for ENDECB event */ -#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ -#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ -#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */ -#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */ -#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */ - -/* Register: ECB_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 1 : Write '1' to Disable interrupt for ERRORECB event */ -#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ -#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ -#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ -#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ -#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */ - -/* Bit 0 : Write '1' to Disable interrupt for ENDECB event */ -#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ -#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ -#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */ -#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */ -#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */ - -/* Register: ECB_ECBDATAPTR */ -/* Description: ECB block encrypt memory pointers */ - -/* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */ -#define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */ -#define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */ - - -/* Peripheral: EGU */ -/* Description: Event Generator Unit 0 */ - -/* Register: EGU_INTEN */ -/* Description: Enable or disable interrupt */ - -/* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */ -#define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ -#define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ -#define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */ - -/* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */ -#define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ -#define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ -#define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */ - -/* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */ -#define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ -#define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ -#define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */ - -/* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */ -#define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ -#define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ -#define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */ - -/* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */ -#define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ -#define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ -#define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */ - -/* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */ -#define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ -#define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ -#define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */ - -/* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */ -#define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ -#define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ -#define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */ - -/* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */ -#define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ -#define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ -#define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */ - -/* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */ -#define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ -#define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ -#define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */ - -/* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */ -#define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ -#define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ -#define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */ - -/* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */ -#define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ -#define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ -#define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */ - -/* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */ -#define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ -#define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ -#define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */ - -/* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */ -#define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ -#define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ -#define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */ - -/* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */ -#define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ -#define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ -#define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */ - -/* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */ -#define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ -#define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ -#define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */ - -/* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */ -#define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ -#define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ -#define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */ - -/* Register: EGU_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 15 : Write '1' to Enable interrupt for TRIGGERED[15] event */ -#define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ -#define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ -#define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */ - -/* Bit 14 : Write '1' to Enable interrupt for TRIGGERED[14] event */ -#define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ -#define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ -#define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */ - -/* Bit 13 : Write '1' to Enable interrupt for TRIGGERED[13] event */ -#define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ -#define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ -#define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */ - -/* Bit 12 : Write '1' to Enable interrupt for TRIGGERED[12] event */ -#define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ -#define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ -#define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */ - -/* Bit 11 : Write '1' to Enable interrupt for TRIGGERED[11] event */ -#define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ -#define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ -#define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */ - -/* Bit 10 : Write '1' to Enable interrupt for TRIGGERED[10] event */ -#define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ -#define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ -#define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */ - -/* Bit 9 : Write '1' to Enable interrupt for TRIGGERED[9] event */ -#define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ -#define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ -#define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */ - -/* Bit 8 : Write '1' to Enable interrupt for TRIGGERED[8] event */ -#define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ -#define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ -#define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */ - -/* Bit 7 : Write '1' to Enable interrupt for TRIGGERED[7] event */ -#define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ -#define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ -#define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */ - -/* Bit 6 : Write '1' to Enable interrupt for TRIGGERED[6] event */ -#define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ -#define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ -#define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */ - -/* Bit 5 : Write '1' to Enable interrupt for TRIGGERED[5] event */ -#define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ -#define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ -#define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */ - -/* Bit 4 : Write '1' to Enable interrupt for TRIGGERED[4] event */ -#define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ -#define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ -#define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */ - -/* Bit 3 : Write '1' to Enable interrupt for TRIGGERED[3] event */ -#define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ -#define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ -#define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */ - -/* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */ -#define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ -#define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ -#define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */ - -/* Bit 1 : Write '1' to Enable interrupt for TRIGGERED[1] event */ -#define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ -#define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ -#define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */ - -/* Bit 0 : Write '1' to Enable interrupt for TRIGGERED[0] event */ -#define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ -#define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ -#define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */ - -/* Register: EGU_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 15 : Write '1' to Disable interrupt for TRIGGERED[15] event */ -#define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ -#define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ -#define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */ - -/* Bit 14 : Write '1' to Disable interrupt for TRIGGERED[14] event */ -#define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ -#define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ -#define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */ - -/* Bit 13 : Write '1' to Disable interrupt for TRIGGERED[13] event */ -#define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ -#define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ -#define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */ - -/* Bit 12 : Write '1' to Disable interrupt for TRIGGERED[12] event */ -#define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ -#define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ -#define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */ - -/* Bit 11 : Write '1' to Disable interrupt for TRIGGERED[11] event */ -#define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ -#define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ -#define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */ - -/* Bit 10 : Write '1' to Disable interrupt for TRIGGERED[10] event */ -#define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ -#define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ -#define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */ - -/* Bit 9 : Write '1' to Disable interrupt for TRIGGERED[9] event */ -#define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ -#define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ -#define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */ - -/* Bit 8 : Write '1' to Disable interrupt for TRIGGERED[8] event */ -#define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ -#define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ -#define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */ - -/* Bit 7 : Write '1' to Disable interrupt for TRIGGERED[7] event */ -#define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ -#define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ -#define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */ - -/* Bit 6 : Write '1' to Disable interrupt for TRIGGERED[6] event */ -#define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ -#define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ -#define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */ - -/* Bit 5 : Write '1' to Disable interrupt for TRIGGERED[5] event */ -#define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ -#define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ -#define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */ - -/* Bit 4 : Write '1' to Disable interrupt for TRIGGERED[4] event */ -#define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ -#define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ -#define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */ - -/* Bit 3 : Write '1' to Disable interrupt for TRIGGERED[3] event */ -#define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ -#define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ -#define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */ - -/* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */ -#define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ -#define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ -#define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */ - -/* Bit 1 : Write '1' to Disable interrupt for TRIGGERED[1] event */ -#define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ -#define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ -#define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */ - -/* Bit 0 : Write '1' to Disable interrupt for TRIGGERED[0] event */ -#define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ -#define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ -#define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */ - - -/* Peripheral: FICR */ -/* Description: Factory Information Configuration Registers */ - -/* Register: FICR_CODEPAGESIZE */ -/* Description: Code memory page size */ - -/* Bits 31..0 : Code memory page size */ -#define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */ -#define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */ - -/* Register: FICR_CODESIZE */ -/* Description: Code memory size */ - -/* Bits 31..0 : Code memory size in number of pages */ -#define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */ -#define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */ - -/* Register: FICR_DEVICEID */ -/* Description: Description collection[0]: Device identifier */ - -/* Bits 31..0 : 64 bit unique device identifier */ -#define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */ -#define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */ - -/* Register: FICR_ER */ -/* Description: Description collection[0]: Encryption Root, word 0 */ - -/* Bits 31..0 : Encryption Root, word n */ -#define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */ -#define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */ - -/* Register: FICR_IR */ -/* Description: Description collection[0]: Identity Root, word 0 */ - -/* Bits 31..0 : Identity Root, word n */ -#define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */ -#define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */ - -/* Register: FICR_DEVICEADDRTYPE */ -/* Description: Device address type */ - -/* Bit 0 : Device address type */ -#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */ -#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */ -#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */ -#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */ - -/* Register: FICR_DEVICEADDR */ -/* Description: Description collection[0]: Device address 0 */ - -/* Bits 31..0 : 48 bit device address */ -#define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */ -#define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */ - -/* Register: FICR_INFO_PART */ -/* Description: Part code */ - -/* Bits 31..0 : Part code */ -#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ -#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ -#define FICR_INFO_PART_PART_N52832 (0x52832UL) /*!< nRF52832 */ -#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ - -/* Register: FICR_INFO_VARIANT */ -/* Description: Part Variant, Hardware version and Production configuration */ - -/* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */ -#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ -#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ -#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ -#define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */ -#define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */ -#define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */ -#define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */ -#define FICR_INFO_VARIANT_VARIANT_AAE0 (0x41414530UL) /*!< AAE0 */ -#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ - -/* Register: FICR_INFO_PACKAGE */ -/* Description: Package option */ - -/* Bits 31..0 : Package option */ -#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ -#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ -#define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */ -#define FICR_INFO_PACKAGE_PACKAGE_CH (0x2001UL) /*!< CHxx - 7x8 WLCSP 56 balls */ -#define FICR_INFO_PACKAGE_PACKAGE_CI (0x2002UL) /*!< CIxx - 7x8 WLCSP 56 balls */ -#define FICR_INFO_PACKAGE_PACKAGE_CK (0x2005UL) /*!< CKxx - 7x8 WLCSP 56 balls with backside coating for light protection */ -#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ - -/* Register: FICR_INFO_RAM */ -/* Description: RAM variant */ - -/* Bits 31..0 : RAM variant */ -#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ -#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ -#define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */ -#define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */ -#define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */ -#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ - -/* Register: FICR_INFO_FLASH */ -/* Description: Flash variant */ - -/* Bits 31..0 : Flash variant */ -#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */ -#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */ -#define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */ -#define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */ -#define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */ -#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ - -/* Register: FICR_TEMP_A0 */ -/* Description: Slope definition A0. */ - -/* Bits 11..0 : A (slope definition) register. */ -#define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */ -#define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */ - -/* Register: FICR_TEMP_A1 */ -/* Description: Slope definition A1. */ - -/* Bits 11..0 : A (slope definition) register. */ -#define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */ -#define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */ - -/* Register: FICR_TEMP_A2 */ -/* Description: Slope definition A2. */ - -/* Bits 11..0 : A (slope definition) register. */ -#define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */ -#define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */ - -/* Register: FICR_TEMP_A3 */ -/* Description: Slope definition A3. */ - -/* Bits 11..0 : A (slope definition) register. */ -#define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */ -#define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */ - -/* Register: FICR_TEMP_A4 */ -/* Description: Slope definition A4. */ - -/* Bits 11..0 : A (slope definition) register. */ -#define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */ -#define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */ - -/* Register: FICR_TEMP_A5 */ -/* Description: Slope definition A5. */ - -/* Bits 11..0 : A (slope definition) register. */ -#define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */ -#define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */ - -/* Register: FICR_TEMP_B0 */ -/* Description: y-intercept B0. */ - -/* Bits 13..0 : B (y-intercept) */ -#define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */ -#define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */ - -/* Register: FICR_TEMP_B1 */ -/* Description: y-intercept B1. */ - -/* Bits 13..0 : B (y-intercept) */ -#define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */ -#define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */ - -/* Register: FICR_TEMP_B2 */ -/* Description: y-intercept B2. */ - -/* Bits 13..0 : B (y-intercept) */ -#define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */ -#define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */ - -/* Register: FICR_TEMP_B3 */ -/* Description: y-intercept B3. */ - -/* Bits 13..0 : B (y-intercept) */ -#define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */ -#define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */ - -/* Register: FICR_TEMP_B4 */ -/* Description: y-intercept B4. */ - -/* Bits 13..0 : B (y-intercept) */ -#define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */ -#define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */ - -/* Register: FICR_TEMP_B5 */ -/* Description: y-intercept B5. */ - -/* Bits 13..0 : B (y-intercept) */ -#define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */ -#define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */ - -/* Register: FICR_TEMP_T0 */ -/* Description: Segment end T0. */ - -/* Bits 7..0 : T (segment end)register. */ -#define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */ -#define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */ - -/* Register: FICR_TEMP_T1 */ -/* Description: Segment end T1. */ - -/* Bits 7..0 : T (segment end)register. */ -#define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */ -#define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */ - -/* Register: FICR_TEMP_T2 */ -/* Description: Segment end T2. */ - -/* Bits 7..0 : T (segment end)register. */ -#define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */ -#define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */ - -/* Register: FICR_TEMP_T3 */ -/* Description: Segment end T3. */ - -/* Bits 7..0 : T (segment end)register. */ -#define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */ -#define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */ - -/* Register: FICR_TEMP_T4 */ -/* Description: Segment end T4. */ - -/* Bits 7..0 : T (segment end)register. */ -#define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */ -#define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */ - -/* Register: FICR_NFC_TAGHEADER0 */ -/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ - -/* Bits 31..24 : Unique identifier byte 3 */ -#define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */ -#define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */ - -/* Bits 23..16 : Unique identifier byte 2 */ -#define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */ -#define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */ - -/* Bits 15..8 : Unique identifier byte 1 */ -#define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */ -#define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */ - -/* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */ -#define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */ -#define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */ - -/* Register: FICR_NFC_TAGHEADER1 */ -/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ - -/* Bits 31..24 : Unique identifier byte 7 */ -#define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */ -#define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */ - -/* Bits 23..16 : Unique identifier byte 6 */ -#define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */ -#define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */ - -/* Bits 15..8 : Unique identifier byte 5 */ -#define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */ -#define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */ - -/* Bits 7..0 : Unique identifier byte 4 */ -#define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */ -#define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */ - -/* Register: FICR_NFC_TAGHEADER2 */ -/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ - -/* Bits 31..24 : Unique identifier byte 11 */ -#define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */ -#define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */ - -/* Bits 23..16 : Unique identifier byte 10 */ -#define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */ -#define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */ - -/* Bits 15..8 : Unique identifier byte 9 */ -#define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */ -#define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */ - -/* Bits 7..0 : Unique identifier byte 8 */ -#define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */ -#define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */ - -/* Register: FICR_NFC_TAGHEADER3 */ -/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ - -/* Bits 31..24 : Unique identifier byte 15 */ -#define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */ -#define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */ - -/* Bits 23..16 : Unique identifier byte 14 */ -#define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */ -#define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */ - -/* Bits 15..8 : Unique identifier byte 13 */ -#define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */ -#define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */ - -/* Bits 7..0 : Unique identifier byte 12 */ -#define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */ -#define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */ - - -/* Peripheral: GPIOTE */ -/* Description: GPIO Tasks and Events */ - -/* Register: GPIOTE_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 31 : Write '1' to Enable interrupt for PORT event */ -#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ -#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ -#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */ - -/* Bit 7 : Write '1' to Enable interrupt for IN[7] event */ -#define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */ -#define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */ -#define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */ - -/* Bit 6 : Write '1' to Enable interrupt for IN[6] event */ -#define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */ -#define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */ -#define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */ - -/* Bit 5 : Write '1' to Enable interrupt for IN[5] event */ -#define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */ -#define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */ -#define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */ - -/* Bit 4 : Write '1' to Enable interrupt for IN[4] event */ -#define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */ -#define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */ -#define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */ - -/* Bit 3 : Write '1' to Enable interrupt for IN[3] event */ -#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ -#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ -#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */ - -/* Bit 2 : Write '1' to Enable interrupt for IN[2] event */ -#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ -#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ -#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */ - -/* Bit 1 : Write '1' to Enable interrupt for IN[1] event */ -#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ -#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ -#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */ - -/* Bit 0 : Write '1' to Enable interrupt for IN[0] event */ -#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ -#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ -#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */ - -/* Register: GPIOTE_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 31 : Write '1' to Disable interrupt for PORT event */ -#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ -#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ -#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */ - -/* Bit 7 : Write '1' to Disable interrupt for IN[7] event */ -#define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */ -#define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */ -#define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */ - -/* Bit 6 : Write '1' to Disable interrupt for IN[6] event */ -#define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */ -#define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */ -#define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */ - -/* Bit 5 : Write '1' to Disable interrupt for IN[5] event */ -#define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */ -#define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */ -#define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */ - -/* Bit 4 : Write '1' to Disable interrupt for IN[4] event */ -#define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */ -#define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */ -#define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */ - -/* Bit 3 : Write '1' to Disable interrupt for IN[3] event */ -#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ -#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ -#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */ - -/* Bit 2 : Write '1' to Disable interrupt for IN[2] event */ -#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ -#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ -#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */ - -/* Bit 1 : Write '1' to Disable interrupt for IN[1] event */ -#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ -#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ -#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */ - -/* Bit 0 : Write '1' to Disable interrupt for IN[0] event */ -#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ -#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ -#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ - -/* Register: GPIOTE_CONFIG */ -/* Description: Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */ - -/* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */ -#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ -#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ -#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */ -#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */ - -/* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */ -#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ -#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ -#define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */ -#define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */ -#define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */ -#define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */ - -/* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */ -#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ -#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ - -/* Bits 1..0 : Mode */ -#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ -#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ -#define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */ -#define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */ -#define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */ - - -/* Peripheral: I2S */ -/* Description: Inter-IC Sound */ - -/* Register: I2S_INTEN */ -/* Description: Enable or disable interrupt */ - -/* Bit 5 : Enable or disable interrupt for TXPTRUPD event */ -#define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ -#define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ -#define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */ -#define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */ - -/* Bit 2 : Enable or disable interrupt for STOPPED event */ -#define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ -#define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ -#define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ - -/* Bit 1 : Enable or disable interrupt for RXPTRUPD event */ -#define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ -#define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ -#define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */ -#define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */ - -/* Register: I2S_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 5 : Write '1' to Enable interrupt for TXPTRUPD event */ -#define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ -#define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ -#define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ -#define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ -#define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */ - -/* Bit 2 : Write '1' to Enable interrupt for STOPPED event */ -#define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ -#define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */ - -/* Bit 1 : Write '1' to Enable interrupt for RXPTRUPD event */ -#define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ -#define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ -#define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ -#define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ -#define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */ - -/* Register: I2S_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 5 : Write '1' to Disable interrupt for TXPTRUPD event */ -#define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ -#define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ -#define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ -#define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ -#define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */ - -/* Bit 2 : Write '1' to Disable interrupt for STOPPED event */ -#define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ -#define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ - -/* Bit 1 : Write '1' to Disable interrupt for RXPTRUPD event */ -#define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ -#define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ -#define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ -#define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ -#define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */ - -/* Register: I2S_ENABLE */ -/* Description: Enable I2S module. */ - -/* Bit 0 : Enable I2S module. */ -#define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ -#define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ - -/* Register: I2S_CONFIG_MODE */ -/* Description: I2S mode. */ - -/* Bit 0 : I2S mode. */ -#define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ -#define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ -#define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */ -#define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */ - -/* Register: I2S_CONFIG_RXEN */ -/* Description: Reception (RX) enable. */ - -/* Bit 0 : Reception (RX) enable. */ -#define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */ -#define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */ -#define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */ -#define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */ - -/* Register: I2S_CONFIG_TXEN */ -/* Description: Transmission (TX) enable. */ - -/* Bit 0 : Transmission (TX) enable. */ -#define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */ -#define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */ -#define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */ -#define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */ - -/* Register: I2S_CONFIG_MCKEN */ -/* Description: Master clock generator enable. */ - -/* Bit 0 : Master clock generator enable. */ -#define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */ -#define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */ -#define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */ -#define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */ - -/* Register: I2S_CONFIG_MCKFREQ */ -/* Description: Master clock generator frequency. */ - -/* Bits 31..0 : Master clock generator frequency. */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */ - -/* Register: I2S_CONFIG_RATIO */ -/* Description: MCK / LRCK ratio. */ - -/* Bits 3..0 : MCK / LRCK ratio. */ -#define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */ -#define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */ -#define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */ -#define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */ -#define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */ -#define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */ -#define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */ -#define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */ -#define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */ -#define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */ -#define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */ - -/* Register: I2S_CONFIG_SWIDTH */ -/* Description: Sample width. */ - -/* Bits 1..0 : Sample width. */ -#define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */ -#define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */ -#define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */ -#define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */ -#define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */ - -/* Register: I2S_CONFIG_ALIGN */ -/* Description: Alignment of sample within a frame. */ - -/* Bit 0 : Alignment of sample within a frame. */ -#define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */ -#define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */ -#define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */ -#define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */ - -/* Register: I2S_CONFIG_FORMAT */ -/* Description: Frame format. */ - -/* Bit 0 : Frame format. */ -#define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */ -#define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */ -#define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */ -#define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */ - -/* Register: I2S_CONFIG_CHANNELS */ -/* Description: Enable channels. */ - -/* Bits 1..0 : Enable channels. */ -#define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */ -#define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */ -#define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */ -#define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */ -#define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */ - -/* Register: I2S_RXD_PTR */ -/* Description: Receive buffer RAM start address. */ - -/* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */ -#define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ -#define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ - -/* Register: I2S_TXD_PTR */ -/* Description: Transmit buffer RAM start address. */ - -/* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */ -#define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ -#define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ - -/* Register: I2S_RXTXD_MAXCNT */ -/* Description: Size of RXD and TXD buffers. */ - -/* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */ -#define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ -#define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ - -/* Register: I2S_PSEL_MCK */ -/* Description: Pin select for MCK signal. */ - -/* Bit 31 : Connection */ -#define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */ -#define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bits 4..0 : Pin number */ -#define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */ - -/* Register: I2S_PSEL_SCK */ -/* Description: Pin select for SCK signal. */ - -/* Bit 31 : Connection */ -#define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ -#define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bits 4..0 : Pin number */ -#define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ - -/* Register: I2S_PSEL_LRCK */ -/* Description: Pin select for LRCK signal. */ - -/* Bit 31 : Connection */ -#define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */ -#define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bits 4..0 : Pin number */ -#define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */ - -/* Register: I2S_PSEL_SDIN */ -/* Description: Pin select for SDIN signal. */ - -/* Bit 31 : Connection */ -#define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */ -#define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bits 4..0 : Pin number */ -#define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */ - -/* Register: I2S_PSEL_SDOUT */ -/* Description: Pin select for SDOUT signal. */ - -/* Bit 31 : Connection */ -#define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */ -#define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bits 4..0 : Pin number */ -#define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */ - - -/* Peripheral: LPCOMP */ -/* Description: Low Power Comparator */ - -/* Register: LPCOMP_SHORTS */ -/* Description: Shortcut register */ - -/* Bit 4 : Shortcut between CROSS event and STOP task */ -#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ -#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ -#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 3 : Shortcut between UP event and STOP task */ -#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ -#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ -#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 2 : Shortcut between DOWN event and STOP task */ -#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ -#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ -#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 1 : Shortcut between READY event and STOP task */ -#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ -#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ -#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 0 : Shortcut between READY event and SAMPLE task */ -#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ -#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ -#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ -#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */ - -/* Register: LPCOMP_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 3 : Write '1' to Enable interrupt for CROSS event */ -#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ -#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ -#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ -#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ -#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ - -/* Bit 2 : Write '1' to Enable interrupt for UP event */ -#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ -#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ -#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ -#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ -#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */ - -/* Bit 1 : Write '1' to Enable interrupt for DOWN event */ -#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ -#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ -#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ -#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ -#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ - -/* Bit 0 : Write '1' to Enable interrupt for READY event */ -#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ -#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ -#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ -#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ -#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */ - -/* Register: LPCOMP_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 3 : Write '1' to Disable interrupt for CROSS event */ -#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ -#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ -#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ -#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ -#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ - -/* Bit 2 : Write '1' to Disable interrupt for UP event */ -#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ -#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ -#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ -#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ -#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ - -/* Bit 1 : Write '1' to Disable interrupt for DOWN event */ -#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ -#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ -#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ -#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ -#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ - -/* Bit 0 : Write '1' to Disable interrupt for READY event */ -#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ -#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ -#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ -#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ -#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */ - -/* Register: LPCOMP_RESULT */ -/* Description: Compare result */ - -/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ -#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ -#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ -#define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ < VIN-). */ -#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ > VIN-). */ - -/* Register: LPCOMP_ENABLE */ -/* Description: Enable LPCOMP */ - -/* Bits 1..0 : Enable or disable LPCOMP */ -#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ -#define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ - -/* Register: LPCOMP_PSEL */ -/* Description: Input pin select */ - -/* Bits 2..0 : Analog pin select */ -#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ -#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ -#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */ -#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */ -#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */ -#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */ -#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */ -#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */ -#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */ -#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */ - -/* Register: LPCOMP_REFSEL */ -/* Description: Reference select */ - -/* Bits 3..0 : Reference select */ -#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ -#define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ -#define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */ -#define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */ -#define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */ -#define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */ -#define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */ -#define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */ -#define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */ -#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */ -#define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */ -#define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */ -#define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */ -#define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */ -#define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */ -#define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */ -#define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */ -#define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */ - -/* Register: LPCOMP_EXTREFSEL */ -/* Description: External reference select */ - -/* Bit 0 : External analog reference select */ -#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ -#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ -#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */ -#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */ - -/* Register: LPCOMP_ANADETECT */ -/* Description: Analog detect configuration */ - -/* Bits 1..0 : Analog detect configuration */ -#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */ -#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */ -#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */ -#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */ -#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */ - -/* Register: LPCOMP_HYST */ -/* Description: Comparator hysteresis enable */ - -/* Bit 0 : Comparator hysteresis enable */ -#define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */ -#define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */ -#define LPCOMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */ -#define LPCOMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis disabled (typ. 50 mV) */ - - -/* Peripheral: MWU */ -/* Description: Memory Watch Unit */ - -/* Register: MWU_INTEN */ -/* Description: Enable or disable interrupt */ - -/* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */ -#define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ -#define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ -#define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */ -#define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */ - -/* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */ -#define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ -#define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ -#define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */ -#define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */ - -/* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */ -#define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ -#define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ -#define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */ -#define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */ - -/* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */ -#define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ -#define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ -#define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */ -#define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */ - -/* Bit 7 : Enable or disable interrupt for REGION[3].RA event */ -#define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ -#define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ -#define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */ -#define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */ - -/* Bit 6 : Enable or disable interrupt for REGION[3].WA event */ -#define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ -#define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ -#define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */ -#define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */ - -/* Bit 5 : Enable or disable interrupt for REGION[2].RA event */ -#define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ -#define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ -#define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */ -#define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */ - -/* Bit 4 : Enable or disable interrupt for REGION[2].WA event */ -#define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ -#define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ -#define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */ -#define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */ - -/* Bit 3 : Enable or disable interrupt for REGION[1].RA event */ -#define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ -#define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ -#define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */ -#define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */ - -/* Bit 2 : Enable or disable interrupt for REGION[1].WA event */ -#define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ -#define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ -#define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */ -#define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */ - -/* Bit 1 : Enable or disable interrupt for REGION[0].RA event */ -#define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ -#define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ -#define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */ -#define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */ - -/* Bit 0 : Enable or disable interrupt for REGION[0].WA event */ -#define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ -#define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ -#define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */ -#define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */ - -/* Register: MWU_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 27 : Write '1' to Enable interrupt for PREGION[1].RA event */ -#define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ -#define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ -#define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */ - -/* Bit 26 : Write '1' to Enable interrupt for PREGION[1].WA event */ -#define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ -#define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ -#define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */ - -/* Bit 25 : Write '1' to Enable interrupt for PREGION[0].RA event */ -#define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ -#define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ -#define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */ - -/* Bit 24 : Write '1' to Enable interrupt for PREGION[0].WA event */ -#define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ -#define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ -#define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */ - -/* Bit 7 : Write '1' to Enable interrupt for REGION[3].RA event */ -#define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ -#define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ -#define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */ - -/* Bit 6 : Write '1' to Enable interrupt for REGION[3].WA event */ -#define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ -#define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ -#define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */ - -/* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */ -#define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ -#define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ -#define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */ - -/* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */ -#define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ -#define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ -#define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */ - -/* Bit 3 : Write '1' to Enable interrupt for REGION[1].RA event */ -#define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ -#define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ -#define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */ - -/* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */ -#define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ -#define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ -#define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */ - -/* Bit 1 : Write '1' to Enable interrupt for REGION[0].RA event */ -#define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ -#define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ -#define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */ - -/* Bit 0 : Write '1' to Enable interrupt for REGION[0].WA event */ -#define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ -#define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ -#define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */ - -/* Register: MWU_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 27 : Write '1' to Disable interrupt for PREGION[1].RA event */ -#define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ -#define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ -#define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ - -/* Bit 26 : Write '1' to Disable interrupt for PREGION[1].WA event */ -#define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ -#define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ -#define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ - -/* Bit 25 : Write '1' to Disable interrupt for PREGION[0].RA event */ -#define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ -#define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ -#define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ - -/* Bit 24 : Write '1' to Disable interrupt for PREGION[0].WA event */ -#define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ -#define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ -#define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ - -/* Bit 7 : Write '1' to Disable interrupt for REGION[3].RA event */ -#define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ -#define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ -#define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */ - -/* Bit 6 : Write '1' to Disable interrupt for REGION[3].WA event */ -#define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ -#define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ -#define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */ - -/* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */ -#define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ -#define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ -#define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */ - -/* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */ -#define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ -#define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ -#define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */ - -/* Bit 3 : Write '1' to Disable interrupt for REGION[1].RA event */ -#define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ -#define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ -#define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */ - -/* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */ -#define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ -#define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ -#define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */ - -/* Bit 1 : Write '1' to Disable interrupt for REGION[0].RA event */ -#define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ -#define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ -#define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */ - -/* Bit 0 : Write '1' to Disable interrupt for REGION[0].WA event */ -#define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ -#define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ -#define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */ - -/* Register: MWU_NMIEN */ -/* Description: Enable or disable non-maskable interrupt */ - -/* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */ -#define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ -#define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ -#define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */ -#define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */ - -/* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */ -#define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ -#define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ -#define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */ -#define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */ - -/* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */ -#define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ -#define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ -#define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */ -#define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */ - -/* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */ -#define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ -#define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ -#define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */ -#define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */ - -/* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */ -#define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ -#define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ -#define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */ -#define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */ - -/* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */ -#define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ -#define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ -#define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */ -#define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */ - -/* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */ -#define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ -#define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ -#define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */ -#define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */ - -/* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */ -#define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ -#define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ -#define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */ -#define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */ - -/* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */ -#define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ -#define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ -#define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */ -#define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */ - -/* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */ -#define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ -#define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ -#define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */ -#define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */ - -/* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */ -#define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ -#define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ -#define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */ -#define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */ - -/* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */ -#define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ -#define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ -#define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */ -#define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */ - -/* Register: MWU_NMIENSET */ -/* Description: Enable non-maskable interrupt */ - -/* Bit 27 : Write '1' to Enable non-maskable interrupt for PREGION[1].RA event */ -#define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ -#define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ -#define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */ - -/* Bit 26 : Write '1' to Enable non-maskable interrupt for PREGION[1].WA event */ -#define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ -#define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ -#define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */ - -/* Bit 25 : Write '1' to Enable non-maskable interrupt for PREGION[0].RA event */ -#define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ -#define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ -#define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */ - -/* Bit 24 : Write '1' to Enable non-maskable interrupt for PREGION[0].WA event */ -#define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ -#define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ -#define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */ - -/* Bit 7 : Write '1' to Enable non-maskable interrupt for REGION[3].RA event */ -#define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ -#define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ -#define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */ - -/* Bit 6 : Write '1' to Enable non-maskable interrupt for REGION[3].WA event */ -#define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ -#define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ -#define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */ - -/* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */ -#define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ -#define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ -#define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */ - -/* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */ -#define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ -#define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ -#define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */ - -/* Bit 3 : Write '1' to Enable non-maskable interrupt for REGION[1].RA event */ -#define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ -#define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ -#define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */ - -/* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */ -#define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ -#define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ -#define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */ - -/* Bit 1 : Write '1' to Enable non-maskable interrupt for REGION[0].RA event */ -#define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ -#define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ -#define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */ - -/* Bit 0 : Write '1' to Enable non-maskable interrupt for REGION[0].WA event */ -#define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ -#define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ -#define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */ - -/* Register: MWU_NMIENCLR */ -/* Description: Disable non-maskable interrupt */ - -/* Bit 27 : Write '1' to Disable non-maskable interrupt for PREGION[1].RA event */ -#define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ -#define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ -#define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ - -/* Bit 26 : Write '1' to Disable non-maskable interrupt for PREGION[1].WA event */ -#define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ -#define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ -#define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ - -/* Bit 25 : Write '1' to Disable non-maskable interrupt for PREGION[0].RA event */ -#define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ -#define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ -#define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ - -/* Bit 24 : Write '1' to Disable non-maskable interrupt for PREGION[0].WA event */ -#define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ -#define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ -#define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ - -/* Bit 7 : Write '1' to Disable non-maskable interrupt for REGION[3].RA event */ -#define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ -#define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ -#define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */ - -/* Bit 6 : Write '1' to Disable non-maskable interrupt for REGION[3].WA event */ -#define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ -#define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ -#define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */ - -/* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */ -#define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ -#define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ -#define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */ - -/* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */ -#define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ -#define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ -#define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */ - -/* Bit 3 : Write '1' to Disable non-maskable interrupt for REGION[1].RA event */ -#define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ -#define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ -#define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */ - -/* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */ -#define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ -#define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ -#define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */ - -/* Bit 1 : Write '1' to Disable non-maskable interrupt for REGION[0].RA event */ -#define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ -#define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ -#define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */ - -/* Bit 0 : Write '1' to Disable non-maskable interrupt for REGION[0].WA event */ -#define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ -#define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ -#define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ -#define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ -#define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */ - -/* Register: MWU_PERREGION_SUBSTATWA */ -/* Description: Description cluster[0]: Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching */ - -/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */ -#define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */ -#define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */ -#define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */ -#define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */ -#define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */ -#define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */ -#define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */ -#define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */ -#define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */ -#define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */ -#define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */ -#define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */ -#define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */ -#define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */ -#define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */ -#define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */ -#define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */ -#define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */ -#define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */ -#define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */ -#define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */ -#define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */ -#define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */ -#define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */ -#define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */ -#define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */ -#define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */ -#define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */ -#define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */ -#define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */ -#define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */ -#define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */ -#define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */ -#define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */ -#define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */ -#define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */ -#define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */ -#define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */ -#define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */ -#define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */ -#define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */ -#define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */ -#define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */ -#define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */ -#define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */ -#define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */ -#define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */ -#define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */ -#define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */ -#define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */ -#define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */ -#define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */ -#define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */ -#define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */ -#define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */ -#define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */ -#define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */ -#define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */ -#define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */ -#define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */ -#define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */ -#define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */ -#define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */ -#define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */ - -/* Register: MWU_PERREGION_SUBSTATRA */ -/* Description: Description cluster[0]: Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching */ - -/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */ -#define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */ -#define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */ -#define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */ -#define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */ -#define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */ -#define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */ -#define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */ -#define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */ -#define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */ -#define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */ -#define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */ -#define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */ -#define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */ -#define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */ -#define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */ -#define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */ -#define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */ -#define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */ -#define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */ -#define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */ -#define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */ -#define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */ -#define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */ -#define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */ -#define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */ -#define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */ -#define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */ -#define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */ -#define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */ -#define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */ -#define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */ -#define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */ -#define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */ -#define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */ -#define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */ -#define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */ -#define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */ -#define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */ -#define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */ -#define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */ -#define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */ -#define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */ -#define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */ -#define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */ -#define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */ -#define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */ -#define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */ -#define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */ -#define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */ -#define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */ -#define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */ -#define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */ -#define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */ -#define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */ -#define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */ -#define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */ -#define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */ -#define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */ -#define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */ -#define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */ -#define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */ -#define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */ -#define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */ -#define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */ -#define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */ -#define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */ - -/* Register: MWU_REGIONEN */ -/* Description: Enable/disable regions watch */ - -/* Bit 27 : Enable/disable read access watch in PREGION[1] */ -#define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */ -#define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */ -#define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */ -#define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */ - -/* Bit 26 : Enable/disable write access watch in PREGION[1] */ -#define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */ -#define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */ -#define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */ -#define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */ - -/* Bit 25 : Enable/disable read access watch in PREGION[0] */ -#define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */ -#define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */ -#define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */ -#define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */ - -/* Bit 24 : Enable/disable write access watch in PREGION[0] */ -#define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */ -#define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */ -#define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */ -#define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */ - -/* Bit 7 : Enable/disable read access watch in region[3] */ -#define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */ -#define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */ -#define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */ -#define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */ - -/* Bit 6 : Enable/disable write access watch in region[3] */ -#define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */ -#define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */ -#define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */ -#define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */ - -/* Bit 5 : Enable/disable read access watch in region[2] */ -#define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */ -#define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */ -#define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */ -#define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */ - -/* Bit 4 : Enable/disable write access watch in region[2] */ -#define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */ -#define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */ -#define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */ -#define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */ - -/* Bit 3 : Enable/disable read access watch in region[1] */ -#define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */ -#define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */ -#define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */ -#define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */ - -/* Bit 2 : Enable/disable write access watch in region[1] */ -#define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */ -#define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */ -#define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */ -#define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */ - -/* Bit 1 : Enable/disable read access watch in region[0] */ -#define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */ -#define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */ -#define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */ -#define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */ - -/* Bit 0 : Enable/disable write access watch in region[0] */ -#define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */ -#define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */ -#define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */ -#define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */ - -/* Register: MWU_REGIONENSET */ -/* Description: Enable regions watch */ - -/* Bit 27 : Enable read access watch in PREGION[1] */ -#define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */ -#define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */ -#define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ -#define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ -#define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */ - -/* Bit 26 : Enable write access watch in PREGION[1] */ -#define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */ -#define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */ -#define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ -#define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ -#define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */ - -/* Bit 25 : Enable read access watch in PREGION[0] */ -#define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */ -#define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */ -#define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ -#define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ -#define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */ - -/* Bit 24 : Enable write access watch in PREGION[0] */ -#define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */ -#define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */ -#define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ -#define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ -#define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */ - -/* Bit 7 : Enable read access watch in region[3] */ -#define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */ -#define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */ -#define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ -#define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ -#define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */ - -/* Bit 6 : Enable write access watch in region[3] */ -#define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */ -#define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */ -#define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ -#define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ -#define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */ - -/* Bit 5 : Enable read access watch in region[2] */ -#define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */ -#define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */ -#define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ -#define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ -#define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */ - -/* Bit 4 : Enable write access watch in region[2] */ -#define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */ -#define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */ -#define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ -#define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ -#define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */ - -/* Bit 3 : Enable read access watch in region[1] */ -#define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */ -#define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */ -#define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ -#define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ -#define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */ - -/* Bit 2 : Enable write access watch in region[1] */ -#define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */ -#define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */ -#define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ -#define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ -#define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */ - -/* Bit 1 : Enable read access watch in region[0] */ -#define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */ -#define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */ -#define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ -#define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ -#define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */ - -/* Bit 0 : Enable write access watch in region[0] */ -#define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */ -#define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */ -#define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ -#define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ -#define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */ - -/* Register: MWU_REGIONENCLR */ -/* Description: Disable regions watch */ - -/* Bit 27 : Disable read access watch in PREGION[1] */ -#define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */ -#define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */ -#define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ -#define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ -#define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */ - -/* Bit 26 : Disable write access watch in PREGION[1] */ -#define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */ -#define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */ -#define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ -#define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ -#define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */ - -/* Bit 25 : Disable read access watch in PREGION[0] */ -#define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */ -#define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */ -#define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ -#define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ -#define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */ - -/* Bit 24 : Disable write access watch in PREGION[0] */ -#define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */ -#define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */ -#define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ -#define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ -#define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */ - -/* Bit 7 : Disable read access watch in region[3] */ -#define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */ -#define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */ -#define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ -#define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ -#define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */ - -/* Bit 6 : Disable write access watch in region[3] */ -#define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */ -#define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */ -#define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ -#define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ -#define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */ - -/* Bit 5 : Disable read access watch in region[2] */ -#define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */ -#define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */ -#define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ -#define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ -#define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */ - -/* Bit 4 : Disable write access watch in region[2] */ -#define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */ -#define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */ -#define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ -#define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ -#define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */ - -/* Bit 3 : Disable read access watch in region[1] */ -#define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */ -#define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */ -#define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ -#define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ -#define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */ - -/* Bit 2 : Disable write access watch in region[1] */ -#define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */ -#define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */ -#define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ -#define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ -#define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */ - -/* Bit 1 : Disable read access watch in region[0] */ -#define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */ -#define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */ -#define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ -#define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ -#define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */ - -/* Bit 0 : Disable write access watch in region[0] */ -#define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */ -#define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */ -#define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ -#define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ -#define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */ - -/* Register: MWU_REGION_START */ -/* Description: Description cluster[0]: Start address for region 0 */ - -/* Bits 31..0 : Start address for region */ -#define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */ -#define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */ - -/* Register: MWU_REGION_END */ -/* Description: Description cluster[0]: End address of region 0 */ - -/* Bits 31..0 : End address of region. */ -#define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */ -#define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */ - -/* Register: MWU_PREGION_START */ -/* Description: Description cluster[0]: Reserved for future use */ - -/* Bits 31..0 : Reserved for future use */ -#define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */ -#define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */ - -/* Register: MWU_PREGION_END */ -/* Description: Description cluster[0]: Reserved for future use */ - -/* Bits 31..0 : Reserved for future use */ -#define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */ -#define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */ - -/* Register: MWU_PREGION_SUBS */ -/* Description: Description cluster[0]: Subregions of region 0 */ - -/* Bit 31 : Include or exclude subregion 31 in region */ -#define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */ -#define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */ -#define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */ - -/* Bit 30 : Include or exclude subregion 30 in region */ -#define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */ -#define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */ -#define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */ - -/* Bit 29 : Include or exclude subregion 29 in region */ -#define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */ -#define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */ -#define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */ - -/* Bit 28 : Include or exclude subregion 28 in region */ -#define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */ -#define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */ -#define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */ - -/* Bit 27 : Include or exclude subregion 27 in region */ -#define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */ -#define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */ -#define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */ - -/* Bit 26 : Include or exclude subregion 26 in region */ -#define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */ -#define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */ -#define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */ - -/* Bit 25 : Include or exclude subregion 25 in region */ -#define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */ -#define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */ -#define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */ - -/* Bit 24 : Include or exclude subregion 24 in region */ -#define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */ -#define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */ -#define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */ - -/* Bit 23 : Include or exclude subregion 23 in region */ -#define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */ -#define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */ -#define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */ - -/* Bit 22 : Include or exclude subregion 22 in region */ -#define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */ -#define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */ -#define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */ - -/* Bit 21 : Include or exclude subregion 21 in region */ -#define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */ -#define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */ -#define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */ - -/* Bit 20 : Include or exclude subregion 20 in region */ -#define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */ -#define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */ -#define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */ - -/* Bit 19 : Include or exclude subregion 19 in region */ -#define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */ -#define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */ -#define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */ - -/* Bit 18 : Include or exclude subregion 18 in region */ -#define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */ -#define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */ -#define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */ - -/* Bit 17 : Include or exclude subregion 17 in region */ -#define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */ -#define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */ -#define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */ - -/* Bit 16 : Include or exclude subregion 16 in region */ -#define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */ -#define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */ -#define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */ - -/* Bit 15 : Include or exclude subregion 15 in region */ -#define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */ -#define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */ -#define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */ - -/* Bit 14 : Include or exclude subregion 14 in region */ -#define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */ -#define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */ -#define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */ - -/* Bit 13 : Include or exclude subregion 13 in region */ -#define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */ -#define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */ -#define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */ - -/* Bit 12 : Include or exclude subregion 12 in region */ -#define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */ -#define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */ -#define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */ - -/* Bit 11 : Include or exclude subregion 11 in region */ -#define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */ -#define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */ -#define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */ - -/* Bit 10 : Include or exclude subregion 10 in region */ -#define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */ -#define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */ -#define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */ - -/* Bit 9 : Include or exclude subregion 9 in region */ -#define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */ -#define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */ -#define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */ - -/* Bit 8 : Include or exclude subregion 8 in region */ -#define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */ -#define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */ -#define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */ - -/* Bit 7 : Include or exclude subregion 7 in region */ -#define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */ -#define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */ -#define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */ - -/* Bit 6 : Include or exclude subregion 6 in region */ -#define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */ -#define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */ -#define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */ - -/* Bit 5 : Include or exclude subregion 5 in region */ -#define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */ -#define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */ -#define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */ - -/* Bit 4 : Include or exclude subregion 4 in region */ -#define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */ -#define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */ -#define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */ - -/* Bit 3 : Include or exclude subregion 3 in region */ -#define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */ -#define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */ -#define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */ - -/* Bit 2 : Include or exclude subregion 2 in region */ -#define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */ -#define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */ -#define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */ - -/* Bit 1 : Include or exclude subregion 1 in region */ -#define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */ -#define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */ -#define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */ - -/* Bit 0 : Include or exclude subregion 0 in region */ -#define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */ -#define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */ -#define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */ -#define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */ - - -/* Peripheral: NFCT */ -/* Description: NFC-A compatible radio */ - -/* Register: NFCT_SHORTS */ -/* Description: Shortcut register */ - -/* Bit 1 : Shortcut between FIELDLOST event and SENSE task */ -#define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */ -#define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */ -#define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */ -#define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 0 : Shortcut between FIELDDETECTED event and ACTIVATE task */ -#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */ -#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */ -#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */ -#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */ - -/* Register: NFCT_INTEN */ -/* Description: Enable or disable interrupt */ - -/* Bit 20 : Enable or disable interrupt for STARTED event */ -#define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */ -#define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ -#define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */ -#define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */ - -/* Bit 19 : Enable or disable interrupt for SELECTED event */ -#define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ -#define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ -#define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */ -#define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */ - -/* Bit 18 : Enable or disable interrupt for COLLISION event */ -#define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ -#define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ -#define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */ -#define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */ - -/* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */ -#define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ -#define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ -#define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */ -#define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */ - -/* Bit 12 : Enable or disable interrupt for ENDTX event */ -#define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ -#define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ -#define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ -#define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ - -/* Bit 11 : Enable or disable interrupt for ENDRX event */ -#define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ -#define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ -#define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ -#define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ - -/* Bit 10 : Enable or disable interrupt for RXERROR event */ -#define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ -#define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ -#define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */ -#define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */ - -/* Bit 7 : Enable or disable interrupt for ERROR event */ -#define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */ -#define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */ -#define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */ - -/* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */ -#define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ -#define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ -#define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */ -#define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */ - -/* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */ -#define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ -#define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ -#define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */ -#define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */ - -/* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */ -#define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ -#define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ -#define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */ -#define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */ - -/* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */ -#define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ -#define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ -#define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */ -#define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */ - -/* Bit 2 : Enable or disable interrupt for FIELDLOST event */ -#define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ -#define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ -#define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */ -#define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */ - -/* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */ -#define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ -#define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ -#define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */ -#define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */ - -/* Bit 0 : Enable or disable interrupt for READY event */ -#define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ -#define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */ -#define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */ -#define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */ - -/* Register: NFCT_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 20 : Write '1' to Enable interrupt for STARTED event */ -#define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */ -#define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ -#define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */ - -/* Bit 19 : Write '1' to Enable interrupt for SELECTED event */ -#define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ -#define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ -#define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */ - -/* Bit 18 : Write '1' to Enable interrupt for COLLISION event */ -#define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ -#define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ -#define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */ - -/* Bit 14 : Write '1' to Enable interrupt for AUTOCOLRESSTARTED event */ -#define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ -#define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ -#define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */ - -/* Bit 12 : Write '1' to Enable interrupt for ENDTX event */ -#define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ -#define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ -#define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */ - -/* Bit 11 : Write '1' to Enable interrupt for ENDRX event */ -#define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ -#define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ -#define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */ - -/* Bit 10 : Write '1' to Enable interrupt for RXERROR event */ -#define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ -#define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ -#define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */ - -/* Bit 7 : Write '1' to Enable interrupt for ERROR event */ -#define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */ -#define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */ - -/* Bit 6 : Write '1' to Enable interrupt for RXFRAMEEND event */ -#define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ -#define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ -#define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */ - -/* Bit 5 : Write '1' to Enable interrupt for RXFRAMESTART event */ -#define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ -#define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ -#define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */ - -/* Bit 4 : Write '1' to Enable interrupt for TXFRAMEEND event */ -#define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ -#define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ -#define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */ - -/* Bit 3 : Write '1' to Enable interrupt for TXFRAMESTART event */ -#define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ -#define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ -#define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */ - -/* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */ -#define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ -#define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ -#define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */ - -/* Bit 1 : Write '1' to Enable interrupt for FIELDDETECTED event */ -#define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ -#define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ -#define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */ - -/* Bit 0 : Write '1' to Enable interrupt for READY event */ -#define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ -#define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ -#define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */ - -/* Register: NFCT_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 20 : Write '1' to Disable interrupt for STARTED event */ -#define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */ -#define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ -#define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ - -/* Bit 19 : Write '1' to Disable interrupt for SELECTED event */ -#define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ -#define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ -#define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */ - -/* Bit 18 : Write '1' to Disable interrupt for COLLISION event */ -#define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ -#define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ -#define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */ - -/* Bit 14 : Write '1' to Disable interrupt for AUTOCOLRESSTARTED event */ -#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ -#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ -#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */ - -/* Bit 12 : Write '1' to Disable interrupt for ENDTX event */ -#define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ -#define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ -#define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ - -/* Bit 11 : Write '1' to Disable interrupt for ENDRX event */ -#define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ -#define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ -#define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ - -/* Bit 10 : Write '1' to Disable interrupt for RXERROR event */ -#define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ -#define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ -#define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */ - -/* Bit 7 : Write '1' to Disable interrupt for ERROR event */ -#define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */ -#define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ - -/* Bit 6 : Write '1' to Disable interrupt for RXFRAMEEND event */ -#define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ -#define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ -#define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */ - -/* Bit 5 : Write '1' to Disable interrupt for RXFRAMESTART event */ -#define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ -#define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ -#define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */ - -/* Bit 4 : Write '1' to Disable interrupt for TXFRAMEEND event */ -#define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ -#define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ -#define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */ - -/* Bit 3 : Write '1' to Disable interrupt for TXFRAMESTART event */ -#define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ -#define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ -#define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */ - -/* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */ -#define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ -#define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ -#define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */ - -/* Bit 1 : Write '1' to Disable interrupt for FIELDDETECTED event */ -#define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ -#define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ -#define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */ - -/* Bit 0 : Write '1' to Disable interrupt for READY event */ -#define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ -#define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ -#define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ -#define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ -#define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */ - -/* Register: NFCT_ERRORSTATUS */ -/* Description: NFC Error Status register */ - -/* Bit 3 : Field level is too low at min load resistance */ -#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos (3UL) /*!< Position of NFCFIELDTOOWEAK field. */ -#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos) /*!< Bit mask of NFCFIELDTOOWEAK field. */ - -/* Bit 2 : Field level is too high at max load resistance */ -#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos (2UL) /*!< Position of NFCFIELDTOOSTRONG field. */ -#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos) /*!< Bit mask of NFCFIELDTOOSTRONG field. */ - -/* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */ -#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */ -#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */ - -/* Register: NFCT_FRAMESTATUS_RX */ -/* Description: Result of last incoming frames */ - -/* Bit 3 : Overrun detected */ -#define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */ -#define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ -#define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */ -#define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */ - -/* Bit 2 : Parity status of received frame */ -#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */ -#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */ -#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */ -#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */ - -/* Bit 0 : No valid End of Frame detected */ -#define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */ -#define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ -#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */ -#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */ - -/* Register: NFCT_CURRENTLOADCTRL */ -/* Description: Current value driven to the NFC Load Control */ - -/* Bits 5..0 : Current value driven to the NFC Load Control */ -#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos (0UL) /*!< Position of CURRENTLOADCTRL field. */ -#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Msk (0x3FUL << NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos) /*!< Bit mask of CURRENTLOADCTRL field. */ - -/* Register: NFCT_FIELDPRESENT */ -/* Description: Indicates the presence or not of a valid field */ - -/* Bit 1 : Indicates if the low level has locked to the field */ -#define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */ -#define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */ -#define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */ -#define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */ - -/* Bit 0 : Indicates the presence or not of a valid field. Available only in the activated state. */ -#define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */ -#define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */ -#define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */ -#define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */ - -/* Register: NFCT_FRAMEDELAYMIN */ -/* Description: Minimum frame delay */ - -/* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */ -#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */ -#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */ - -/* Register: NFCT_FRAMEDELAYMAX */ -/* Description: Maximum frame delay */ - -/* Bits 15..0 : Maximum frame delay in number of 13.56 MHz clocks */ -#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */ -#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */ - -/* Register: NFCT_FRAMEDELAYMODE */ -/* Description: Configuration register for the Frame Delay Timer */ - -/* Bits 1..0 : Configuration register for the Frame Delay Timer */ -#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */ -#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */ -#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */ -#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */ -#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */ -#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */ - -/* Register: NFCT_PACKETPTR */ -/* Description: Packet pointer for TXD and RXD data storage in Data RAM */ - -/* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address. */ -#define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */ -#define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */ - -/* Register: NFCT_MAXLEN */ -/* Description: Size of allocated for TXD and RXD data storage buffer in Data RAM */ - -/* Bits 8..0 : Size of allocated for TXD and RXD data storage buffer in Data RAM */ -#define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ -#define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ - -/* Register: NFCT_TXD_FRAMECONFIG */ -/* Description: Configuration of outgoing frames */ - -/* Bit 4 : CRC mode for outgoing frames */ -#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */ -#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */ -#define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */ -#define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */ - -/* Bit 2 : Adding SoF or not in TX frames */ -#define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */ -#define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */ -#define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol not added */ -#define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol added */ - -/* Bit 1 : Discarding unused bits in start or at end of a Frame */ -#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */ -#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */ -#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits is discarded at end of frame */ -#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits is discarded at start of frame */ - -/* Bit 0 : Adding parity or not in the frame */ -#define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */ -#define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ -#define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added in TX frames */ -#define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added TX frames */ - -/* Register: NFCT_TXD_AMOUNT */ -/* Description: Size of outgoing frame */ - -/* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */ -#define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */ -#define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */ - -/* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */ -#define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */ -#define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */ - -/* Register: NFCT_RXD_FRAMECONFIG */ -/* Description: Configuration of incoming frames */ - -/* Bit 4 : CRC mode for incoming frames */ -#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */ -#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */ -#define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */ -#define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */ - -/* Bit 2 : SoF expected or not in RX frames */ -#define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */ -#define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */ -#define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol is not expected in RX frames */ -#define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol is expected in RX frames */ - -/* Bit 0 : Parity expected or not in RX frame */ -#define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */ -#define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ -#define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */ -#define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */ - -/* Register: NFCT_RXD_AMOUNT */ -/* Description: Size of last incoming frame */ - -/* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */ -#define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */ -#define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */ - -/* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */ -#define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */ -#define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */ - -/* Register: NFCT_NFCID1_LAST */ -/* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */ - -/* Bits 31..24 : NFCID1 byte W */ -#define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */ -#define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */ - -/* Bits 23..16 : NFCID1 byte X */ -#define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */ -#define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */ - -/* Bits 15..8 : NFCID1 byte Y */ -#define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */ -#define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */ - -/* Bits 7..0 : NFCID1 byte Z (very last byte sent) */ -#define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */ -#define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */ - -/* Register: NFCT_NFCID1_2ND_LAST */ -/* Description: Second last NFCID1 part (7 or 10 bytes ID) */ - -/* Bits 23..16 : NFCID1 byte T */ -#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */ -#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */ - -/* Bits 15..8 : NFCID1 byte U */ -#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */ -#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */ - -/* Bits 7..0 : NFCID1 byte V */ -#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */ -#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */ - -/* Register: NFCT_NFCID1_3RD_LAST */ -/* Description: Third last NFCID1 part (10 bytes ID) */ - -/* Bits 23..16 : NFCID1 byte Q */ -#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */ -#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */ - -/* Bits 15..8 : NFCID1 byte R */ -#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */ -#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */ - -/* Bits 7..0 : NFCID1 byte S */ -#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */ -#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */ - -/* Register: NFCT_SENSRES */ -/* Description: NFC-A SENS_RES auto-response settings */ - -/* Bits 15..12 : Reserved for future use. Shall be 0. */ -#define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */ -#define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */ - -/* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ -#define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */ -#define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */ - -/* Bits 7..6 : NFCID1 size. This value is used by the Auto collision resolution engine. */ -#define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */ -#define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */ -#define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */ -#define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */ -#define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */ - -/* Bit 5 : Reserved for future use. Shall be 0. */ -#define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */ -#define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */ - -/* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ -#define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */ -#define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */ -#define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */ -#define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */ -#define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */ -#define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */ -#define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */ -#define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */ - -/* Register: NFCT_SELRES */ -/* Description: NFC-A SEL_RES auto-response settings */ - -/* Bit 7 : Reserved for future use. Shall be 0. */ -#define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */ -#define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */ - -/* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ -#define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */ -#define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */ - -/* Bits 4..3 : Reserved for future use. Shall be 0. */ -#define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */ -#define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */ - -/* Bit 2 : Cascade bit (controlled by hardware, write has no effect) */ -#define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */ -#define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */ -#define NFCT_SELRES_CASCADE_Complete (0UL) /*!< NFCID1 complete */ -#define NFCT_SELRES_CASCADE_NotComplete (1UL) /*!< NFCID1 not complete */ - -/* Bits 1..0 : Reserved for future use. Shall be 0. */ -#define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */ -#define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */ - - -/* Peripheral: NVMC */ -/* Description: Non Volatile Memory Controller */ - -/* Register: NVMC_READY */ -/* Description: Ready flag */ - -/* Bit 0 : NVMC is ready or busy */ -#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ -#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ -#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */ -#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */ - -/* Register: NVMC_CONFIG */ -/* Description: Configuration register */ - -/* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */ -#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ -#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ -#define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */ -#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */ -#define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */ - -/* Register: NVMC_ERASEPAGE */ -/* Description: Register for erasing a page in Code area */ - -/* Bits 31..0 : Register for starting erase of a page in Code area */ -#define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */ -#define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */ - -/* Register: NVMC_ERASEPCR1 */ -/* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */ - -/* Bits 31..0 : Register for erasing a page in Code area. Equivalent to ERASEPAGE. */ -#define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */ -#define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */ - -/* Register: NVMC_ERASEALL */ -/* Description: Register for erasing all non-volatile user memory */ - -/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */ -#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ -#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ -#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */ -#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */ - -/* Register: NVMC_ERASEPCR0 */ -/* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */ - -/* Bits 31..0 : Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. */ -#define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */ -#define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */ - -/* Register: NVMC_ERASEUICR */ -/* Description: Register for erasing User Information Configuration Registers */ - -/* Bit 0 : Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */ -#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */ -#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */ -#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */ -#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */ - -/* Register: NVMC_ICACHECNF */ -/* Description: I-Code cache configuration register. */ - -/* Bit 8 : Cache profiling enable */ -#define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */ -#define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */ -#define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */ -#define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */ - -/* Bit 0 : Cache enable */ -#define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */ -#define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */ -#define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */ -#define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */ - -/* Register: NVMC_IHIT */ -/* Description: I-Code cache hit counter. */ - -/* Bits 31..0 : Number of cache hits */ -#define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */ -#define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */ - -/* Register: NVMC_IMISS */ -/* Description: I-Code cache miss counter. */ - -/* Bits 31..0 : Number of cache misses */ -#define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */ -#define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */ - - -/* Peripheral: GPIO */ -/* Description: GPIO Port 1 */ - -/* Register: GPIO_OUT */ -/* Description: Write GPIO port */ - -/* Bit 31 : Pin 31 */ -#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */ - -/* Bit 30 : Pin 30 */ -#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */ - -/* Bit 29 : Pin 29 */ -#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */ - -/* Bit 28 : Pin 28 */ -#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */ - -/* Bit 27 : Pin 27 */ -#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */ - -/* Bit 26 : Pin 26 */ -#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */ - -/* Bit 25 : Pin 25 */ -#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */ - -/* Bit 24 : Pin 24 */ -#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */ - -/* Bit 23 : Pin 23 */ -#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */ - -/* Bit 22 : Pin 22 */ -#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */ - -/* Bit 21 : Pin 21 */ -#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */ - -/* Bit 20 : Pin 20 */ -#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */ - -/* Bit 19 : Pin 19 */ -#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */ - -/* Bit 18 : Pin 18 */ -#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */ - -/* Bit 17 : Pin 17 */ -#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */ - -/* Bit 16 : Pin 16 */ -#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */ - -/* Bit 15 : Pin 15 */ -#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */ - -/* Bit 14 : Pin 14 */ -#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */ - -/* Bit 13 : Pin 13 */ -#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */ - -/* Bit 12 : Pin 12 */ -#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */ - -/* Bit 11 : Pin 11 */ -#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */ - -/* Bit 10 : Pin 10 */ -#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */ - -/* Bit 9 : Pin 9 */ -#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */ - -/* Bit 8 : Pin 8 */ -#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */ - -/* Bit 7 : Pin 7 */ -#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */ - -/* Bit 6 : Pin 6 */ -#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */ - -/* Bit 5 : Pin 5 */ -#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */ - -/* Bit 4 : Pin 4 */ -#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */ - -/* Bit 3 : Pin 3 */ -#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */ - -/* Bit 2 : Pin 2 */ -#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */ - -/* Bit 1 : Pin 1 */ -#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */ - -/* Bit 0 : Pin 0 */ -#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */ - -/* Register: GPIO_OUTSET */ -/* Description: Set individual bits in GPIO port */ - -/* Bit 31 : Pin 31 */ -#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 30 : Pin 30 */ -#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 29 : Pin 29 */ -#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 28 : Pin 28 */ -#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 27 : Pin 27 */ -#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 26 : Pin 26 */ -#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 25 : Pin 25 */ -#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 24 : Pin 24 */ -#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 23 : Pin 23 */ -#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 22 : Pin 22 */ -#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 21 : Pin 21 */ -#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 20 : Pin 20 */ -#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 19 : Pin 19 */ -#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 18 : Pin 18 */ -#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 17 : Pin 17 */ -#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 16 : Pin 16 */ -#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 15 : Pin 15 */ -#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 14 : Pin 14 */ -#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 13 : Pin 13 */ -#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 12 : Pin 12 */ -#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 11 : Pin 11 */ -#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 10 : Pin 10 */ -#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 9 : Pin 9 */ -#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 8 : Pin 8 */ -#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 7 : Pin 7 */ -#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 6 : Pin 6 */ -#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 5 : Pin 5 */ -#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 4 : Pin 4 */ -#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 3 : Pin 3 */ -#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 2 : Pin 2 */ -#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 1 : Pin 1 */ -#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Bit 0 : Pin 0 */ -#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ - -/* Register: GPIO_OUTCLR */ -/* Description: Clear individual bits in GPIO port */ - -/* Bit 31 : Pin 31 */ -#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 30 : Pin 30 */ -#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 29 : Pin 29 */ -#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 28 : Pin 28 */ -#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 27 : Pin 27 */ -#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 26 : Pin 26 */ -#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 25 : Pin 25 */ -#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 24 : Pin 24 */ -#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 23 : Pin 23 */ -#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 22 : Pin 22 */ -#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 21 : Pin 21 */ -#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 20 : Pin 20 */ -#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 19 : Pin 19 */ -#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 18 : Pin 18 */ -#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 17 : Pin 17 */ -#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 16 : Pin 16 */ -#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 15 : Pin 15 */ -#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 14 : Pin 14 */ -#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 13 : Pin 13 */ -#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 12 : Pin 12 */ -#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 11 : Pin 11 */ -#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 10 : Pin 10 */ -#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 9 : Pin 9 */ -#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 8 : Pin 8 */ -#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 7 : Pin 7 */ -#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 6 : Pin 6 */ -#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 5 : Pin 5 */ -#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 4 : Pin 4 */ -#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 3 : Pin 3 */ -#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 2 : Pin 2 */ -#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 1 : Pin 1 */ -#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Bit 0 : Pin 0 */ -#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ - -/* Register: GPIO_IN */ -/* Description: Read GPIO port */ - -/* Bit 31 : Pin 31 */ -#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */ - -/* Bit 30 : Pin 30 */ -#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */ - -/* Bit 29 : Pin 29 */ -#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */ - -/* Bit 28 : Pin 28 */ -#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */ - -/* Bit 27 : Pin 27 */ -#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */ - -/* Bit 26 : Pin 26 */ -#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */ - -/* Bit 25 : Pin 25 */ -#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */ - -/* Bit 24 : Pin 24 */ -#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */ - -/* Bit 23 : Pin 23 */ -#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */ - -/* Bit 22 : Pin 22 */ -#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */ - -/* Bit 21 : Pin 21 */ -#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */ - -/* Bit 20 : Pin 20 */ -#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */ - -/* Bit 19 : Pin 19 */ -#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */ - -/* Bit 18 : Pin 18 */ -#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */ - -/* Bit 17 : Pin 17 */ -#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */ - -/* Bit 16 : Pin 16 */ -#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */ - -/* Bit 15 : Pin 15 */ -#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */ - -/* Bit 14 : Pin 14 */ -#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */ - -/* Bit 13 : Pin 13 */ -#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */ - -/* Bit 12 : Pin 12 */ -#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */ - -/* Bit 11 : Pin 11 */ -#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */ - -/* Bit 10 : Pin 10 */ -#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */ - -/* Bit 9 : Pin 9 */ -#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */ - -/* Bit 8 : Pin 8 */ -#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */ - -/* Bit 7 : Pin 7 */ -#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */ - -/* Bit 6 : Pin 6 */ -#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */ - -/* Bit 5 : Pin 5 */ -#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */ - -/* Bit 4 : Pin 4 */ -#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */ - -/* Bit 3 : Pin 3 */ -#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */ - -/* Bit 2 : Pin 2 */ -#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */ - -/* Bit 1 : Pin 1 */ -#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */ - -/* Bit 0 : Pin 0 */ -#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */ - -/* Register: GPIO_DIR */ -/* Description: Direction of GPIO pins */ - -/* Bit 31 : Pin 31 */ -#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */ - -/* Bit 30 : Pin 30 */ -#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */ - -/* Bit 29 : Pin 29 */ -#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */ - -/* Bit 28 : Pin 28 */ -#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */ - -/* Bit 27 : Pin 27 */ -#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */ - -/* Bit 26 : Pin 26 */ -#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */ - -/* Bit 25 : Pin 25 */ -#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */ - -/* Bit 24 : Pin 24 */ -#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */ - -/* Bit 23 : Pin 23 */ -#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */ - -/* Bit 22 : Pin 22 */ -#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */ - -/* Bit 21 : Pin 21 */ -#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */ - -/* Bit 20 : Pin 20 */ -#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */ - -/* Bit 19 : Pin 19 */ -#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */ - -/* Bit 18 : Pin 18 */ -#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */ - -/* Bit 17 : Pin 17 */ -#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */ - -/* Bit 16 : Pin 16 */ -#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */ - -/* Bit 15 : Pin 15 */ -#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */ - -/* Bit 14 : Pin 14 */ -#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */ - -/* Bit 13 : Pin 13 */ -#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */ - -/* Bit 12 : Pin 12 */ -#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */ - -/* Bit 11 : Pin 11 */ -#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */ - -/* Bit 10 : Pin 10 */ -#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */ - -/* Bit 9 : Pin 9 */ -#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */ - -/* Bit 8 : Pin 8 */ -#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */ - -/* Bit 7 : Pin 7 */ -#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */ - -/* Bit 6 : Pin 6 */ -#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */ - -/* Bit 5 : Pin 5 */ -#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */ - -/* Bit 4 : Pin 4 */ -#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */ - -/* Bit 3 : Pin 3 */ -#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */ - -/* Bit 2 : Pin 2 */ -#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */ - -/* Bit 1 : Pin 1 */ -#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */ - -/* Bit 0 : Pin 0 */ -#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */ - -/* Register: GPIO_DIRSET */ -/* Description: DIR set register */ - -/* Bit 31 : Set as output pin 31 */ -#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 30 : Set as output pin 30 */ -#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 29 : Set as output pin 29 */ -#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 28 : Set as output pin 28 */ -#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 27 : Set as output pin 27 */ -#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 26 : Set as output pin 26 */ -#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 25 : Set as output pin 25 */ -#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 24 : Set as output pin 24 */ -#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 23 : Set as output pin 23 */ -#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 22 : Set as output pin 22 */ -#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 21 : Set as output pin 21 */ -#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 20 : Set as output pin 20 */ -#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 19 : Set as output pin 19 */ -#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 18 : Set as output pin 18 */ -#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 17 : Set as output pin 17 */ -#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 16 : Set as output pin 16 */ -#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 15 : Set as output pin 15 */ -#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 14 : Set as output pin 14 */ -#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 13 : Set as output pin 13 */ -#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 12 : Set as output pin 12 */ -#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 11 : Set as output pin 11 */ -#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 10 : Set as output pin 10 */ -#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 9 : Set as output pin 9 */ -#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 8 : Set as output pin 8 */ -#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 7 : Set as output pin 7 */ -#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 6 : Set as output pin 6 */ -#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 5 : Set as output pin 5 */ -#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 4 : Set as output pin 4 */ -#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 3 : Set as output pin 3 */ -#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 2 : Set as output pin 2 */ -#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 1 : Set as output pin 1 */ -#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Bit 0 : Set as output pin 0 */ -#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ - -/* Register: GPIO_DIRCLR */ -/* Description: DIR clear register */ - -/* Bit 31 : Set as input pin 31 */ -#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 30 : Set as input pin 30 */ -#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 29 : Set as input pin 29 */ -#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 28 : Set as input pin 28 */ -#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 27 : Set as input pin 27 */ -#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 26 : Set as input pin 26 */ -#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 25 : Set as input pin 25 */ -#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 24 : Set as input pin 24 */ -#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 23 : Set as input pin 23 */ -#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 22 : Set as input pin 22 */ -#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 21 : Set as input pin 21 */ -#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 20 : Set as input pin 20 */ -#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 19 : Set as input pin 19 */ -#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 18 : Set as input pin 18 */ -#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 17 : Set as input pin 17 */ -#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 16 : Set as input pin 16 */ -#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 15 : Set as input pin 15 */ -#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 14 : Set as input pin 14 */ -#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 13 : Set as input pin 13 */ -#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 12 : Set as input pin 12 */ -#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 11 : Set as input pin 11 */ -#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 10 : Set as input pin 10 */ -#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 9 : Set as input pin 9 */ -#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 8 : Set as input pin 8 */ -#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 7 : Set as input pin 7 */ -#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 6 : Set as input pin 6 */ -#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 5 : Set as input pin 5 */ -#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 4 : Set as input pin 4 */ -#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 3 : Set as input pin 3 */ -#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 2 : Set as input pin 2 */ -#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 1 : Set as input pin 1 */ -#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Bit 0 : Set as input pin 0 */ -#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ - -/* Register: GPIO_LATCH */ -/* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ - -/* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */ - -/* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */ -#define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */ - -/* Register: GPIO_DETECTMODE */ -/* Description: Select between default DETECT signal behaviour and LDETECT mode */ - -/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */ -#define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ -#define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ -#define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */ -#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */ - -/* Register: GPIO_PIN_CNF */ -/* Description: Description collection[0]: Configuration of GPIO pins */ - -/* Bits 17..16 : Pin sensing mechanism */ -#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ -#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ -#define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */ -#define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */ -#define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */ - -/* Bits 10..8 : Drive configuration */ -#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */ -#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */ -#define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */ -#define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */ -#define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */ -#define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */ -#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */ -#define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */ -#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */ -#define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */ - -/* Bits 3..2 : Pull configuration */ -#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ -#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ -#define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */ -#define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */ -#define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */ - -/* Bit 1 : Connect or disconnect input buffer */ -#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ -#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ -#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */ -#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */ - -/* Bit 0 : Pin direction. Same physical register as DIR register */ -#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ -#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ -#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */ -#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */ - - -/* Peripheral: PDM */ -/* Description: Pulse Density Modulation (Digital Microphone) Interface */ - -/* Register: PDM_INTEN */ -/* Description: Enable or disable interrupt */ - -/* Bit 2 : Enable or disable interrupt for END event */ -#define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */ -#define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */ -#define PDM_INTEN_END_Disabled (0UL) /*!< Disable */ -#define PDM_INTEN_END_Enabled (1UL) /*!< Enable */ - -/* Bit 1 : Enable or disable interrupt for STOPPED event */ -#define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ -#define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ -#define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ - -/* Bit 0 : Enable or disable interrupt for STARTED event */ -#define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ -#define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ -#define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */ -#define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */ - -/* Register: PDM_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 2 : Write '1' to Enable interrupt for END event */ -#define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */ -#define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */ -#define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ -#define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ -#define PDM_INTENSET_END_Set (1UL) /*!< Enable */ - -/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ -#define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ -#define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ - -/* Bit 0 : Write '1' to Enable interrupt for STARTED event */ -#define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ -#define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ -#define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ -#define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ -#define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */ - -/* Register: PDM_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 2 : Write '1' to Disable interrupt for END event */ -#define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */ -#define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ -#define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ -#define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ -#define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */ - -/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ -#define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ -#define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ - -/* Bit 0 : Write '1' to Disable interrupt for STARTED event */ -#define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ -#define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ -#define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ -#define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ -#define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ - -/* Register: PDM_ENABLE */ -/* Description: PDM module enable register */ - -/* Bit 0 : Enable or disable PDM module */ -#define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ -#define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ - -/* Register: PDM_PDMCLKCTRL */ -/* Description: PDM clock generator control */ - -/* Bits 31..0 : PDM_CLK frequency */ -#define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */ -#define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */ -#define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */ -#define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz */ -#define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */ - -/* Register: PDM_MODE */ -/* Description: Defines the routing of the connected PDM microphones' signals */ - -/* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */ -#define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */ -#define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */ -#define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */ -#define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */ - -/* Bit 0 : Mono or stereo operation */ -#define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */ -#define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */ -#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */ -#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */ - -/* Register: PDM_GAINL */ -/* Description: Left output gain adjustment */ - -/* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */ -#define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */ -#define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */ -#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ -#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */ -#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ - -/* Register: PDM_GAINR */ -/* Description: Right output gain adjustment */ - -/* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */ -#define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */ -#define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */ -#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ -#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */ -#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ - -/* Register: PDM_PSEL_CLK */ -/* Description: Pin number configuration for PDM CLK signal */ - -/* Bit 31 : Connection */ -#define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */ -#define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bits 4..0 : Pin number */ -#define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */ - -/* Register: PDM_PSEL_DIN */ -/* Description: Pin number configuration for PDM DIN signal */ - -/* Bit 31 : Connection */ -#define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */ -#define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bits 4..0 : Pin number */ -#define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */ - -/* Register: PDM_SAMPLE_PTR */ -/* Description: RAM address pointer to write samples to with EasyDMA */ - -/* Bits 31..0 : Address to write PDM samples to over DMA */ -#define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */ -#define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */ - -/* Register: PDM_SAMPLE_MAXCNT */ -/* Description: Number of samples to allocate memory for in EasyDMA mode */ - -/* Bits 14..0 : Length of DMA RAM allocation in number of samples */ -#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */ -#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */ - - -/* Peripheral: POWER */ -/* Description: Power control */ - -/* Register: POWER_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 6 : Write '1' to Enable interrupt for SLEEPEXIT event */ -#define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ -#define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ -#define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ -#define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ -#define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */ - -/* Bit 5 : Write '1' to Enable interrupt for SLEEPENTER event */ -#define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ -#define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ -#define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ -#define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ -#define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */ - -/* Bit 2 : Write '1' to Enable interrupt for POFWARN event */ -#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ -#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ -#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */ -#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */ -#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */ - -/* Register: POWER_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 6 : Write '1' to Disable interrupt for SLEEPEXIT event */ -#define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ -#define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ -#define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ -#define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ -#define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */ - -/* Bit 5 : Write '1' to Disable interrupt for SLEEPENTER event */ -#define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ -#define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ -#define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ -#define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ -#define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */ - -/* Bit 2 : Write '1' to Disable interrupt for POFWARN event */ -#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ -#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ -#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */ -#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */ -#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */ - -/* Register: POWER_RESETREAS */ -/* Description: Reset reason */ - -/* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */ -#define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */ -#define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */ -#define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */ -#define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */ - -/* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */ -#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */ -#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ -#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */ -#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */ - -/* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */ -#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */ -#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ -#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */ -#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */ - -/* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */ -#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */ -#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ -#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */ -#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */ - -/* Bit 3 : Reset from CPU lock-up detected */ -#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */ -#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ -#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */ -#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */ - -/* Bit 2 : Reset from soft reset detected */ -#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */ -#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ -#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */ -#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */ - -/* Bit 1 : Reset from watchdog detected */ -#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ -#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ -#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */ -#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */ - -/* Bit 0 : Reset from pin-reset detected */ -#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ -#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ -#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */ -#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */ - -/* Register: POWER_RAMSTATUS */ -/* Description: Deprecated register - RAM status register */ - -/* Bit 3 : RAM block 3 is on or off/powering up */ -#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */ -#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */ -#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */ -#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */ - -/* Bit 2 : RAM block 2 is on or off/powering up */ -#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */ -#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */ -#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */ -#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */ - -/* Bit 1 : RAM block 1 is on or off/powering up */ -#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */ -#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */ -#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */ -#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */ - -/* Bit 0 : RAM block 0 is on or off/powering up */ -#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */ -#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */ -#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */ -#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */ - -/* Register: POWER_SYSTEMOFF */ -/* Description: System OFF register */ - -/* Bit 0 : Enable System OFF mode */ -#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ -#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ -#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */ - -/* Register: POWER_POFCON */ -/* Description: Power failure comparator configuration */ - -/* Bits 4..1 : Power failure comparator threshold setting */ -#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */ -#define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ -#define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */ -#define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */ -#define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */ -#define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */ -#define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */ -#define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */ -#define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */ -#define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */ -#define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */ -#define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */ -#define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */ -#define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */ - -/* Bit 0 : Enable or disable power failure comparator */ -#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */ -#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */ -#define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */ -#define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */ - -/* Register: POWER_GPREGRET */ -/* Description: General purpose retention register */ - -/* Bits 7..0 : General purpose retention register */ -#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ -#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ - -/* Register: POWER_GPREGRET2 */ -/* Description: General purpose retention register */ - -/* Bits 7..0 : General purpose retention register */ -#define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ -#define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ - -/* Register: POWER_RAMON */ -/* Description: Deprecated register - RAM on/off register (this register is retained) */ - -/* Bit 17 : Keep retention on RAM block 1 when RAM block is switched off */ -#define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */ -#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */ -#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< Off */ -#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< On */ - -/* Bit 16 : Keep retention on RAM block 0 when RAM block is switched off */ -#define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */ -#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */ -#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< Off */ -#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< On */ - -/* Bit 1 : Keep RAM block 1 on or off in system ON Mode */ -#define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */ -#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */ -#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< Off */ -#define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< On */ - -/* Bit 0 : Keep RAM block 0 on or off in system ON Mode */ -#define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */ -#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */ -#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< Off */ -#define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< On */ - -/* Register: POWER_RAMONB */ -/* Description: Deprecated register - RAM on/off register (this register is retained) */ - -/* Bit 17 : Keep retention on RAM block 3 when RAM block is switched off */ -#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */ -#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */ -#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< Off */ -#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< On */ - -/* Bit 16 : Keep retention on RAM block 2 when RAM block is switched off */ -#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */ -#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */ -#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< Off */ -#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< On */ - -/* Bit 1 : Keep RAM block 3 on or off in system ON Mode */ -#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */ -#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */ -#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< Off */ -#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< On */ - -/* Bit 0 : Keep RAM block 2 on or off in system ON Mode */ -#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */ -#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */ -#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< Off */ -#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< On */ - -/* Register: POWER_DCDCEN */ -/* Description: DC/DC enable register */ - -/* Bit 0 : Enable or disable DC/DC converter */ -#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ -#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ -#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */ -#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */ - -/* Register: POWER_RAM_POWER */ -/* Description: Description cluster[0]: RAM0 power control register */ - -/* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */ -#define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ -#define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ -#define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */ -#define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */ - -/* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */ -#define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ -#define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ -#define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */ -#define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */ - -/* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */ -#define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ -#define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ -#define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */ -#define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */ - -/* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */ -#define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ -#define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ -#define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */ -#define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */ - -/* Register: POWER_RAM_POWERSET */ -/* Description: Description cluster[0]: RAM0 power control set register */ - -/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ -#define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ -#define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ -#define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */ - -/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ -#define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ -#define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ -#define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */ - -/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */ -#define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ -#define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ -#define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */ - -/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */ -#define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ -#define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ -#define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */ - -/* Register: POWER_RAM_POWERCLR */ -/* Description: Description cluster[0]: RAM0 power control clear register */ - -/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ -#define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ -#define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ -#define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */ - -/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ -#define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ -#define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ -#define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */ - -/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */ -#define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ -#define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ -#define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */ - -/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */ -#define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ -#define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ -#define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */ - - -/* Peripheral: PPI */ -/* Description: Programmable Peripheral Interconnect */ - -/* Register: PPI_CHEN */ -/* Description: Channel enable register */ - -/* Bit 31 : Enable or disable channel 31 */ -#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */ -#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */ -#define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */ - -/* Bit 30 : Enable or disable channel 30 */ -#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */ -#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */ -#define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */ - -/* Bit 29 : Enable or disable channel 29 */ -#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */ -#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */ -#define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */ - -/* Bit 28 : Enable or disable channel 28 */ -#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */ -#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */ -#define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */ - -/* Bit 27 : Enable or disable channel 27 */ -#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */ -#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */ -#define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */ - -/* Bit 26 : Enable or disable channel 26 */ -#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */ -#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */ -#define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */ - -/* Bit 25 : Enable or disable channel 25 */ -#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */ -#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */ -#define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */ - -/* Bit 24 : Enable or disable channel 24 */ -#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */ -#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */ -#define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */ - -/* Bit 23 : Enable or disable channel 23 */ -#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */ -#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */ -#define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */ - -/* Bit 22 : Enable or disable channel 22 */ -#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */ -#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */ -#define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */ - -/* Bit 21 : Enable or disable channel 21 */ -#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */ -#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */ -#define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */ - -/* Bit 20 : Enable or disable channel 20 */ -#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */ -#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */ -#define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */ - -/* Bit 19 : Enable or disable channel 19 */ -#define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */ -#define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */ -#define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */ - -/* Bit 18 : Enable or disable channel 18 */ -#define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */ -#define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */ -#define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */ - -/* Bit 17 : Enable or disable channel 17 */ -#define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */ -#define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */ -#define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */ - -/* Bit 16 : Enable or disable channel 16 */ -#define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */ -#define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */ -#define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */ - -/* Bit 15 : Enable or disable channel 15 */ -#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ -#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ -#define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */ - -/* Bit 14 : Enable or disable channel 14 */ -#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ -#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ -#define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */ - -/* Bit 13 : Enable or disable channel 13 */ -#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ -#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ -#define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */ - -/* Bit 12 : Enable or disable channel 12 */ -#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ -#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ -#define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */ - -/* Bit 11 : Enable or disable channel 11 */ -#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ -#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ -#define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */ - -/* Bit 10 : Enable or disable channel 10 */ -#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ -#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ -#define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */ - -/* Bit 9 : Enable or disable channel 9 */ -#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ -#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ -#define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */ - -/* Bit 8 : Enable or disable channel 8 */ -#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ -#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ -#define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */ - -/* Bit 7 : Enable or disable channel 7 */ -#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ -#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ -#define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */ - -/* Bit 6 : Enable or disable channel 6 */ -#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ -#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ -#define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */ - -/* Bit 5 : Enable or disable channel 5 */ -#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ -#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ -#define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */ - -/* Bit 4 : Enable or disable channel 4 */ -#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ -#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ -#define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */ - -/* Bit 3 : Enable or disable channel 3 */ -#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ -#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ -#define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */ - -/* Bit 2 : Enable or disable channel 2 */ -#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ -#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ -#define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */ - -/* Bit 1 : Enable or disable channel 1 */ -#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ -#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ -#define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */ - -/* Bit 0 : Enable or disable channel 0 */ -#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ -#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ -#define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */ - -/* Register: PPI_CHENSET */ -/* Description: Channel enable set register */ - -/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ -#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ -#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ -#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ -#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ -#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ -#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ -#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ -#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ -#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ -#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ -#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ -#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ -#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ -#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ -#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ -#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ -#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ -#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ -#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ -#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ -#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ -#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ -#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ -#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */ -#define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */ -#define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */ -#define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */ -#define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */ -#define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */ -#define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */ -#define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */ -#define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ -#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ -#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ -#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ -#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ -#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ -#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ -#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ -#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ -#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ -#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ -#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ -#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ -#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ -#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ -#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ -#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ -#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ -#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ -#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ -#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ -#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ -#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ -#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ -#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ -#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ -#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ -#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ -#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ -#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ -#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ -#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ -#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */ - -/* Register: PPI_CHENCLR */ -/* Description: Channel enable clear register */ - -/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ -#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ -#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ -#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ -#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ -#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ -#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ -#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ -#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ -#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ -#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ -#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ -#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ -#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ -#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ -#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ -#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ -#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ -#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ -#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ -#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ -#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ -#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ -#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ -#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */ -#define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */ -#define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */ -#define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */ -#define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */ -#define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */ -#define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */ -#define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */ -#define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ -#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ -#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ -#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ -#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ -#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ -#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ -#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ -#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ -#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ -#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ -#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ -#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ -#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ -#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ -#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ -#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ -#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ -#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ -#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ -#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ -#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ -#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ -#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ -#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ -#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ -#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ -#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ -#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ -#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ -#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ -#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ -#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */ - -/* Register: PPI_CH_EEP */ -/* Description: Description cluster[0]: Channel 0 event end-point */ - -/* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */ -#define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */ -#define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */ - -/* Register: PPI_CH_TEP */ -/* Description: Description cluster[0]: Channel 0 task end-point */ - -/* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */ -#define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ -#define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ - -/* Register: PPI_CHG */ -/* Description: Description collection[0]: Channel group 0 */ - -/* Bit 31 : Include or exclude channel 31 */ -#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ -#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */ -#define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH31_Included (1UL) /*!< Include */ - -/* Bit 30 : Include or exclude channel 30 */ -#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */ -#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */ -#define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH30_Included (1UL) /*!< Include */ - -/* Bit 29 : Include or exclude channel 29 */ -#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */ -#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */ -#define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH29_Included (1UL) /*!< Include */ - -/* Bit 28 : Include or exclude channel 28 */ -#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */ -#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */ -#define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH28_Included (1UL) /*!< Include */ - -/* Bit 27 : Include or exclude channel 27 */ -#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */ -#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */ -#define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH27_Included (1UL) /*!< Include */ - -/* Bit 26 : Include or exclude channel 26 */ -#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */ -#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */ -#define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH26_Included (1UL) /*!< Include */ - -/* Bit 25 : Include or exclude channel 25 */ -#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */ -#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */ -#define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH25_Included (1UL) /*!< Include */ - -/* Bit 24 : Include or exclude channel 24 */ -#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */ -#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */ -#define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH24_Included (1UL) /*!< Include */ - -/* Bit 23 : Include or exclude channel 23 */ -#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */ -#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */ -#define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH23_Included (1UL) /*!< Include */ - -/* Bit 22 : Include or exclude channel 22 */ -#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */ -#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */ -#define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH22_Included (1UL) /*!< Include */ - -/* Bit 21 : Include or exclude channel 21 */ -#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */ -#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */ -#define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH21_Included (1UL) /*!< Include */ - -/* Bit 20 : Include or exclude channel 20 */ -#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */ -#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */ -#define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH20_Included (1UL) /*!< Include */ - -/* Bit 19 : Include or exclude channel 19 */ -#define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */ -#define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */ -#define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH19_Included (1UL) /*!< Include */ - -/* Bit 18 : Include or exclude channel 18 */ -#define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */ -#define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */ -#define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH18_Included (1UL) /*!< Include */ - -/* Bit 17 : Include or exclude channel 17 */ -#define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */ -#define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */ -#define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH17_Included (1UL) /*!< Include */ - -/* Bit 16 : Include or exclude channel 16 */ -#define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */ -#define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */ -#define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH16_Included (1UL) /*!< Include */ - -/* Bit 15 : Include or exclude channel 15 */ -#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ -#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ -#define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH15_Included (1UL) /*!< Include */ - -/* Bit 14 : Include or exclude channel 14 */ -#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ -#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ -#define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH14_Included (1UL) /*!< Include */ - -/* Bit 13 : Include or exclude channel 13 */ -#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ -#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ -#define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH13_Included (1UL) /*!< Include */ - -/* Bit 12 : Include or exclude channel 12 */ -#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ -#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ -#define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH12_Included (1UL) /*!< Include */ - -/* Bit 11 : Include or exclude channel 11 */ -#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ -#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ -#define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH11_Included (1UL) /*!< Include */ - -/* Bit 10 : Include or exclude channel 10 */ -#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ -#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ -#define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH10_Included (1UL) /*!< Include */ - -/* Bit 9 : Include or exclude channel 9 */ -#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ -#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ -#define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH9_Included (1UL) /*!< Include */ - -/* Bit 8 : Include or exclude channel 8 */ -#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ -#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ -#define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH8_Included (1UL) /*!< Include */ - -/* Bit 7 : Include or exclude channel 7 */ -#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ -#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ -#define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH7_Included (1UL) /*!< Include */ - -/* Bit 6 : Include or exclude channel 6 */ -#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ -#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ -#define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH6_Included (1UL) /*!< Include */ - -/* Bit 5 : Include or exclude channel 5 */ -#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ -#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ -#define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH5_Included (1UL) /*!< Include */ - -/* Bit 4 : Include or exclude channel 4 */ -#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ -#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ -#define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH4_Included (1UL) /*!< Include */ - -/* Bit 3 : Include or exclude channel 3 */ -#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ -#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ -#define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH3_Included (1UL) /*!< Include */ - -/* Bit 2 : Include or exclude channel 2 */ -#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ -#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ -#define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH2_Included (1UL) /*!< Include */ - -/* Bit 1 : Include or exclude channel 1 */ -#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ -#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ -#define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH1_Included (1UL) /*!< Include */ - -/* Bit 0 : Include or exclude channel 0 */ -#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ -#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ -#define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH0_Included (1UL) /*!< Include */ - -/* Register: PPI_FORK_TEP */ -/* Description: Description cluster[0]: Channel 0 task end-point */ - -/* Bits 31..0 : Pointer to task register */ -#define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ -#define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ - - -/* Peripheral: PWM */ -/* Description: Pulse Width Modulation Unit 0 */ - -/* Register: PWM_SHORTS */ -/* Description: Shortcut register */ - -/* Bit 4 : Shortcut between LOOPSDONE event and STOP task */ -#define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */ -#define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */ -#define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */ -#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */ -#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */ -#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */ -#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */ -#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */ -#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */ -#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */ -#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 1 : Shortcut between SEQEND[1] event and STOP task */ -#define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */ -#define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */ -#define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 0 : Shortcut between SEQEND[0] event and STOP task */ -#define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */ -#define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */ -#define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */ - -/* Register: PWM_INTEN */ -/* Description: Enable or disable interrupt */ - -/* Bit 7 : Enable or disable interrupt for LOOPSDONE event */ -#define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ -#define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ -#define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */ -#define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */ - -/* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */ -#define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ -#define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ -#define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */ -#define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */ - -/* Bit 5 : Enable or disable interrupt for SEQEND[1] event */ -#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ -#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ -#define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */ -#define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */ - -/* Bit 4 : Enable or disable interrupt for SEQEND[0] event */ -#define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ -#define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ -#define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */ -#define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */ - -/* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */ -#define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ -#define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ -#define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */ -#define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */ - -/* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */ -#define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ -#define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ -#define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */ -#define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */ - -/* Bit 1 : Enable or disable interrupt for STOPPED event */ -#define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ -#define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ -#define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ - -/* Register: PWM_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 7 : Write '1' to Enable interrupt for LOOPSDONE event */ -#define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ -#define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ -#define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */ - -/* Bit 6 : Write '1' to Enable interrupt for PWMPERIODEND event */ -#define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ -#define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ -#define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */ - -/* Bit 5 : Write '1' to Enable interrupt for SEQEND[1] event */ -#define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ -#define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ -#define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */ - -/* Bit 4 : Write '1' to Enable interrupt for SEQEND[0] event */ -#define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ -#define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ -#define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */ - -/* Bit 3 : Write '1' to Enable interrupt for SEQSTARTED[1] event */ -#define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ -#define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ -#define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */ - -/* Bit 2 : Write '1' to Enable interrupt for SEQSTARTED[0] event */ -#define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ -#define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ -#define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */ - -/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ -#define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ -#define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ - -/* Register: PWM_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 7 : Write '1' to Disable interrupt for LOOPSDONE event */ -#define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ -#define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ -#define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */ - -/* Bit 6 : Write '1' to Disable interrupt for PWMPERIODEND event */ -#define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ -#define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ -#define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */ - -/* Bit 5 : Write '1' to Disable interrupt for SEQEND[1] event */ -#define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ -#define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ -#define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */ - -/* Bit 4 : Write '1' to Disable interrupt for SEQEND[0] event */ -#define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ -#define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ -#define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */ - -/* Bit 3 : Write '1' to Disable interrupt for SEQSTARTED[1] event */ -#define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ -#define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ -#define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */ - -/* Bit 2 : Write '1' to Disable interrupt for SEQSTARTED[0] event */ -#define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ -#define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ -#define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */ - -/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ -#define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ -#define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ - -/* Register: PWM_ENABLE */ -/* Description: PWM module enable register */ - -/* Bit 0 : Enable or disable PWM module */ -#define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */ -#define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ - -/* Register: PWM_MODE */ -/* Description: Selects operating mode of the wave counter */ - -/* Bit 0 : Selects up or up and down as wave counter mode */ -#define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */ -#define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */ -#define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter - edge aligned PWM duty-cycle */ -#define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter - center aligned PWM duty cycle */ - -/* Register: PWM_COUNTERTOP */ -/* Description: Value up to which the pulse generator counter counts */ - -/* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. */ -#define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */ -#define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */ - -/* Register: PWM_PRESCALER */ -/* Description: Configuration for PWM_CLK */ - -/* Bits 2..0 : Pre-scaler of PWM_CLK */ -#define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ -#define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ -#define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16MHz) */ -#define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 ( 8MHz) */ -#define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 ( 4MHz) */ -#define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 ( 2MHz) */ -#define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 ( 1MHz) */ -#define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 ( 500kHz) */ -#define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 ( 250kHz) */ -#define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 ( 125kHz) */ - -/* Register: PWM_DECODER */ -/* Description: Configuration of the decoder */ - -/* Bit 8 : Selects source for advancing the active sequence */ -#define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */ -#define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */ -#define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */ -#define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */ - -/* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */ -#define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */ -#define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */ -#define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */ -#define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */ -#define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */ -#define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */ - -/* Register: PWM_LOOP */ -/* Description: Amount of playback of a loop */ - -/* Bits 15..0 : Amount of playback of pattern cycles */ -#define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */ -#define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */ -#define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */ - -/* Register: PWM_SEQ_PTR */ -/* Description: Description cluster[0]: Beginning address in Data RAM of this sequence */ - -/* Bits 31..0 : Beginning address in Data RAM of this sequence */ -#define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ -#define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ - -/* Register: PWM_SEQ_CNT */ -/* Description: Description cluster[0]: Amount of values (duty cycles) in this sequence */ - -/* Bits 14..0 : Amount of values (duty cycles) in this sequence */ -#define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ -#define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ -#define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */ - -/* Register: PWM_SEQ_REFRESH */ -/* Description: Description cluster[0]: Amount of additional PWM periods between samples loaded into compare register */ - -/* Bits 23..0 : Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */ -#define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */ -#define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */ -#define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */ - -/* Register: PWM_SEQ_ENDDELAY */ -/* Description: Description cluster[0]: Time added after the sequence */ - -/* Bits 23..0 : Time added after the sequence in PWM periods */ -#define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */ -#define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */ - -/* Register: PWM_PSEL_OUT */ -/* Description: Description collection[0]: Output pin select for PWM channel 0 */ - -/* Bit 31 : Connection */ -#define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */ -#define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bits 4..0 : Pin number */ -#define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */ - - -/* Peripheral: QDEC */ -/* Description: Quadrature Decoder */ - -/* Register: QDEC_SHORTS */ -/* Description: Shortcut register */ - -/* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */ -#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */ -#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */ -#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ -#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 5 : Shortcut between DBLRDY event and STOP task */ -#define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */ -#define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */ -#define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */ -#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */ -#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */ -#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */ -#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 3 : Shortcut between REPORTRDY event and STOP task */ -#define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */ -#define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */ -#define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */ -#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */ -#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */ -#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */ -#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 1 : Shortcut between SAMPLERDY event and STOP task */ -#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ -#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ -#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */ -#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ -#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ -#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ -#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ - -/* Register: QDEC_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 4 : Write '1' to Enable interrupt for STOPPED event */ -#define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ -#define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ - -/* Bit 3 : Write '1' to Enable interrupt for DBLRDY event */ -#define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ -#define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ -#define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ -#define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ -#define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */ - -/* Bit 2 : Write '1' to Enable interrupt for ACCOF event */ -#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ -#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ -#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */ -#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */ -#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */ - -/* Bit 1 : Write '1' to Enable interrupt for REPORTRDY event */ -#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ -#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ -#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ -#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ -#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */ - -/* Bit 0 : Write '1' to Enable interrupt for SAMPLERDY event */ -#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ -#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ -#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ -#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ -#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */ - -/* Register: QDEC_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 4 : Write '1' to Disable interrupt for STOPPED event */ -#define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ -#define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ - -/* Bit 3 : Write '1' to Disable interrupt for DBLRDY event */ -#define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ -#define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ -#define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ -#define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ -#define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */ - -/* Bit 2 : Write '1' to Disable interrupt for ACCOF event */ -#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ -#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ -#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */ -#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */ -#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */ - -/* Bit 1 : Write '1' to Disable interrupt for REPORTRDY event */ -#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ -#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ -#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ -#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ -#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */ - -/* Bit 0 : Write '1' to Disable interrupt for SAMPLERDY event */ -#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ -#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ -#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ -#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ -#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */ - -/* Register: QDEC_ENABLE */ -/* Description: Enable the quadrature decoder */ - -/* Bit 0 : Enable or disable the quadrature decoder */ -#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ -#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ - -/* Register: QDEC_LEDPOL */ -/* Description: LED output pin polarity */ - -/* Bit 0 : LED output pin polarity */ -#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */ -#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */ -#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */ -#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */ - -/* Register: QDEC_SAMPLEPER */ -/* Description: Sample period */ - -/* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */ -#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */ -#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */ -#define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */ -#define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */ -#define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */ -#define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */ -#define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */ -#define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */ -#define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */ -#define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */ -#define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */ -#define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */ -#define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */ - -/* Register: QDEC_SAMPLE */ -/* Description: Motion sample value */ - -/* Bits 31..0 : Last motion sample */ -#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */ -#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */ - -/* Register: QDEC_REPORTPER */ -/* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */ - -/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */ -#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ -#define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ -#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */ -#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */ -#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */ -#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */ -#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */ -#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */ -#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */ -#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */ -#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */ - -/* Register: QDEC_ACC */ -/* Description: Register accumulating the valid transitions */ - -/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */ -#define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */ -#define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */ - -/* Register: QDEC_ACCREAD */ -/* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */ - -/* Bits 31..0 : Snapshot of the ACC register. */ -#define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */ -#define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */ - -/* Register: QDEC_PSEL_LED */ -/* Description: Pin select for LED signal */ - -/* Bit 31 : Connection */ -#define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */ -#define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bits 4..0 : Pin number */ -#define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */ - -/* Register: QDEC_PSEL_A */ -/* Description: Pin select for A signal */ - -/* Bit 31 : Connection */ -#define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */ -#define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bits 4..0 : Pin number */ -#define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */ - -/* Register: QDEC_PSEL_B */ -/* Description: Pin select for B signal */ - -/* Bit 31 : Connection */ -#define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */ -#define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bits 4..0 : Pin number */ -#define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */ - -/* Register: QDEC_DBFEN */ -/* Description: Enable input debounce filters */ - -/* Bit 0 : Enable input debounce filters */ -#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */ -#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */ -#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */ -#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */ - -/* Register: QDEC_LEDPRE */ -/* Description: Time period the LED is switched ON prior to sampling */ - -/* Bits 8..0 : Period in us the LED is switched on prior to sampling */ -#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ -#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ - -/* Register: QDEC_ACCDBL */ -/* Description: Register accumulating the number of detected double transitions */ - -/* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */ -#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */ -#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */ - -/* Register: QDEC_ACCDBLREAD */ -/* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */ - -/* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */ -#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */ -#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */ - - -/* Peripheral: RADIO */ -/* Description: 2.4 GHz Radio */ - -/* Register: RADIO_SHORTS */ -/* Description: Shortcut register */ - -/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */ -#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ -#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ -#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */ -#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 6 : Shortcut between ADDRESS event and BCSTART task */ -#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ -#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ -#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */ -#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 5 : Shortcut between END event and START task */ -#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ -#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ -#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ -#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */ -#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ -#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ -#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */ -#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 3 : Shortcut between DISABLED event and RXEN task */ -#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ -#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ -#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */ -#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 2 : Shortcut between DISABLED event and TXEN task */ -#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ -#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ -#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */ -#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 1 : Shortcut between END event and DISABLE task */ -#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ -#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ -#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */ -#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 0 : Shortcut between READY event and START task */ -#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ -#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ -#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */ -#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */ - -/* Register: RADIO_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 13 : Write '1' to Enable interrupt for CRCERROR event */ -#define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ -#define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ -#define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */ - -/* Bit 12 : Write '1' to Enable interrupt for CRCOK event */ -#define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ -#define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ -#define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */ - -/* Bit 10 : Write '1' to Enable interrupt for BCMATCH event */ -#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ -#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ -#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */ - -/* Bit 7 : Write '1' to Enable interrupt for RSSIEND event */ -#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ -#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ -#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */ - -/* Bit 6 : Write '1' to Enable interrupt for DEVMISS event */ -#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ -#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ -#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */ - -/* Bit 5 : Write '1' to Enable interrupt for DEVMATCH event */ -#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ -#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ -#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */ - -/* Bit 4 : Write '1' to Enable interrupt for DISABLED event */ -#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ -#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ -#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */ - -/* Bit 3 : Write '1' to Enable interrupt for END event */ -#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ -#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ -#define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENSET_END_Set (1UL) /*!< Enable */ - -/* Bit 2 : Write '1' to Enable interrupt for PAYLOAD event */ -#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ -#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ -#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */ - -/* Bit 1 : Write '1' to Enable interrupt for ADDRESS event */ -#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ -#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ -#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */ - -/* Bit 0 : Write '1' to Enable interrupt for READY event */ -#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ -#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ -#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */ - -/* Register: RADIO_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 13 : Write '1' to Disable interrupt for CRCERROR event */ -#define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ -#define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ -#define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */ - -/* Bit 12 : Write '1' to Disable interrupt for CRCOK event */ -#define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ -#define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ -#define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */ - -/* Bit 10 : Write '1' to Disable interrupt for BCMATCH event */ -#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ -#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ -#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */ - -/* Bit 7 : Write '1' to Disable interrupt for RSSIEND event */ -#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ -#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ -#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */ - -/* Bit 6 : Write '1' to Disable interrupt for DEVMISS event */ -#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ -#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ -#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */ - -/* Bit 5 : Write '1' to Disable interrupt for DEVMATCH event */ -#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ -#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ -#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */ - -/* Bit 4 : Write '1' to Disable interrupt for DISABLED event */ -#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ -#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ -#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */ - -/* Bit 3 : Write '1' to Disable interrupt for END event */ -#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ -#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ -#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */ - -/* Bit 2 : Write '1' to Disable interrupt for PAYLOAD event */ -#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ -#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ -#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */ - -/* Bit 1 : Write '1' to Disable interrupt for ADDRESS event */ -#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ -#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ -#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */ - -/* Bit 0 : Write '1' to Disable interrupt for READY event */ -#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ -#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ -#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */ - -/* Register: RADIO_CRCSTATUS */ -/* Description: CRC status */ - -/* Bit 0 : CRC status of packet received */ -#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */ -#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */ -#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */ -#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */ - -/* Register: RADIO_RXMATCH */ -/* Description: Received address */ - -/* Bits 2..0 : Received address */ -#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */ -#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */ - -/* Register: RADIO_RXCRC */ -/* Description: CRC field of previously received packet */ - -/* Bits 23..0 : CRC field of previously received packet */ -#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */ -#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */ - -/* Register: RADIO_DAI */ -/* Description: Device address match index */ - -/* Bits 2..0 : Device address match index */ -#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ -#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ - -/* Register: RADIO_PACKETPTR */ -/* Description: Packet pointer */ - -/* Bits 31..0 : Packet pointer */ -#define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */ -#define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */ - -/* Register: RADIO_FREQUENCY */ -/* Description: Frequency */ - -/* Bit 8 : Channel map selection. */ -#define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */ -#define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */ -#define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */ -#define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */ - -/* Bits 6..0 : Radio channel frequency */ -#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ -#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ - -/* Register: RADIO_TXPOWER */ -/* Description: Output power */ - -/* Bits 7..0 : RADIO output power. */ -#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ -#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ -#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0 dBm */ -#define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL) /*!< +3 dBm */ -#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4 dBm */ -#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< Deprecated enumerator - -40 dBm */ -#define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */ -#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */ -#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */ -#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */ -#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */ -#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */ - -/* Register: RADIO_MODE */ -/* Description: Data rate and modulation */ - -/* Bits 3..0 : Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. */ -#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ -#define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ -#define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */ -#define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */ -#define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator - 250 kbit/s Nordic proprietary radio mode */ -#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */ -#define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s Bluetooth Low Energy */ - -/* Register: RADIO_PCNF0 */ -/* Description: Packet configuration register 0 */ - -/* Bit 24 : Length of preamble on air. Decision point: TASKS_START task */ -#define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */ -#define RADIO_PCNF0_PLEN_Msk (0x1UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */ -#define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */ -#define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */ - -/* Bit 20 : Include or exclude S1 field in RAM */ -#define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */ -#define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */ -#define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */ -#define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */ - -/* Bits 19..16 : Length on air of S1 field in number of bits. */ -#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ -#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ - -/* Bit 8 : Length on air of S0 field in number of bytes. */ -#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ -#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ - -/* Bits 3..0 : Length on air of LENGTH field in number of bits. */ -#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ -#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ - -/* Register: RADIO_PCNF1 */ -/* Description: Packet configuration register 1 */ - -/* Bit 25 : Enable or disable packet whitening */ -#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */ -#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */ -#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */ -#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */ - -/* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */ -#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ -#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ -#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least Significant bit on air first */ -#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */ - -/* Bits 18..16 : Base address length in number of bytes */ -#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */ -#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */ - -/* Bits 15..8 : Static length in number of bytes */ -#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */ -#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */ - -/* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */ -#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ -#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ - -/* Register: RADIO_BASE0 */ -/* Description: Base address 0 */ - -/* Bits 31..0 : Base address 0 */ -#define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */ -#define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */ - -/* Register: RADIO_BASE1 */ -/* Description: Base address 1 */ - -/* Bits 31..0 : Base address 1 */ -#define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */ -#define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */ - -/* Register: RADIO_PREFIX0 */ -/* Description: Prefixes bytes for logical addresses 0-3 */ - -/* Bits 31..24 : Address prefix 3. */ -#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */ -#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */ - -/* Bits 23..16 : Address prefix 2. */ -#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */ -#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */ - -/* Bits 15..8 : Address prefix 1. */ -#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */ -#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */ - -/* Bits 7..0 : Address prefix 0. */ -#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */ -#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */ - -/* Register: RADIO_PREFIX1 */ -/* Description: Prefixes bytes for logical addresses 4-7 */ - -/* Bits 31..24 : Address prefix 7. */ -#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */ -#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */ - -/* Bits 23..16 : Address prefix 6. */ -#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */ -#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */ - -/* Bits 15..8 : Address prefix 5. */ -#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */ -#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */ - -/* Bits 7..0 : Address prefix 4. */ -#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */ -#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */ - -/* Register: RADIO_TXADDRESS */ -/* Description: Transmit address select */ - -/* Bits 2..0 : Transmit address select */ -#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */ -#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */ - -/* Register: RADIO_RXADDRESSES */ -/* Description: Receive address select */ - -/* Bit 7 : Enable or disable reception on logical address 7. */ -#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */ -#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */ -#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */ -#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */ - -/* Bit 6 : Enable or disable reception on logical address 6. */ -#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */ -#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */ -#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */ -#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */ - -/* Bit 5 : Enable or disable reception on logical address 5. */ -#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */ -#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */ -#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */ -#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */ - -/* Bit 4 : Enable or disable reception on logical address 4. */ -#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */ -#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */ -#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */ -#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */ - -/* Bit 3 : Enable or disable reception on logical address 3. */ -#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */ -#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */ -#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */ -#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */ - -/* Bit 2 : Enable or disable reception on logical address 2. */ -#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */ -#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */ -#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */ -#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */ - -/* Bit 1 : Enable or disable reception on logical address 1. */ -#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */ -#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */ -#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */ -#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */ - -/* Bit 0 : Enable or disable reception on logical address 0. */ -#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */ -#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */ -#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */ -#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */ - -/* Register: RADIO_CRCCNF */ -/* Description: CRC configuration */ - -/* Bit 8 : Include or exclude packet address field out of CRC calculation. */ -#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ -#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ -#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */ -#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */ - -/* Bits 1..0 : CRC length in number of bytes. */ -#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ -#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ -#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */ -#define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */ -#define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */ -#define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */ - -/* Register: RADIO_CRCPOLY */ -/* Description: CRC polynomial */ - -/* Bits 23..0 : CRC polynomial */ -#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ -#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ - -/* Register: RADIO_CRCINIT */ -/* Description: CRC initial value */ - -/* Bits 23..0 : CRC initial value */ -#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */ -#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ - -/* Register: RADIO_TIFS */ -/* Description: Inter Frame Spacing in us */ - -/* Bits 7..0 : Inter Frame Spacing in us */ -#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ -#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ - -/* Register: RADIO_RSSISAMPLE */ -/* Description: RSSI sample */ - -/* Bits 6..0 : RSSI sample */ -#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ -#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ - -/* Register: RADIO_STATE */ -/* Description: Current radio state */ - -/* Bits 3..0 : Current radio state */ -#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */ -#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ -#define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */ -#define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */ -#define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */ -#define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */ -#define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */ -#define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */ -#define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */ -#define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */ -#define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */ - -/* Register: RADIO_DATAWHITEIV */ -/* Description: Data whitening initial value */ - -/* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */ -#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ -#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ - -/* Register: RADIO_BCC */ -/* Description: Bit counter compare */ - -/* Bits 31..0 : Bit counter compare */ -#define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */ -#define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */ - -/* Register: RADIO_DAB */ -/* Description: Description collection[0]: Device address base segment 0 */ - -/* Bits 31..0 : Device address base segment 0 */ -#define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */ -#define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */ - -/* Register: RADIO_DAP */ -/* Description: Description collection[0]: Device address prefix 0 */ - -/* Bits 15..0 : Device address prefix 0 */ -#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ -#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ - -/* Register: RADIO_DACNF */ -/* Description: Device address match configuration */ - -/* Bit 15 : TxAdd for device address 7 */ -#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */ -#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */ - -/* Bit 14 : TxAdd for device address 6 */ -#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */ -#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */ - -/* Bit 13 : TxAdd for device address 5 */ -#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */ -#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */ - -/* Bit 12 : TxAdd for device address 4 */ -#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */ -#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */ - -/* Bit 11 : TxAdd for device address 3 */ -#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */ -#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */ - -/* Bit 10 : TxAdd for device address 2 */ -#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */ -#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */ - -/* Bit 9 : TxAdd for device address 1 */ -#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */ -#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */ - -/* Bit 8 : TxAdd for device address 0 */ -#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */ -#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */ - -/* Bit 7 : Enable or disable device address matching using device address 7 */ -#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */ -#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */ -#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */ -#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */ - -/* Bit 6 : Enable or disable device address matching using device address 6 */ -#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */ -#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */ -#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */ -#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */ - -/* Bit 5 : Enable or disable device address matching using device address 5 */ -#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */ -#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */ -#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */ -#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */ - -/* Bit 4 : Enable or disable device address matching using device address 4 */ -#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */ -#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */ -#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */ -#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */ - -/* Bit 3 : Enable or disable device address matching using device address 3 */ -#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */ -#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */ -#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */ -#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */ - -/* Bit 2 : Enable or disable device address matching using device address 2 */ -#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */ -#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */ -#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */ -#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */ - -/* Bit 1 : Enable or disable device address matching using device address 1 */ -#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */ -#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */ -#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */ -#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */ - -/* Bit 0 : Enable or disable device address matching using device address 0 */ -#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */ -#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */ -#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */ -#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */ - -/* Register: RADIO_MODECNF0 */ -/* Description: Radio mode configuration register 0 */ - -/* Bits 9..8 : Default TX value */ -#define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */ -#define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */ -#define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */ -#define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */ -#define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */ - -/* Bit 0 : Radio ramp-up time */ -#define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */ -#define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */ -#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */ -#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */ - -/* Register: RADIO_POWER */ -/* Description: Peripheral power control */ - -/* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */ -#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */ -#define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */ - - -/* Peripheral: RNG */ -/* Description: Random Number Generator */ - -/* Register: RNG_SHORTS */ -/* Description: Shortcut register */ - -/* Bit 0 : Shortcut between VALRDY event and STOP task */ -#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ -#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ -#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ - -/* Register: RNG_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 0 : Write '1' to Enable interrupt for VALRDY event */ -#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ -#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ -#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */ -#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */ -#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */ - -/* Register: RNG_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 0 : Write '1' to Disable interrupt for VALRDY event */ -#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ -#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ -#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */ -#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */ -#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */ - -/* Register: RNG_CONFIG */ -/* Description: Configuration register */ - -/* Bit 0 : Bias correction */ -#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */ -#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */ -#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */ -#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */ - -/* Register: RNG_VALUE */ -/* Description: Output random number */ - -/* Bits 7..0 : Generated random number */ -#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ -#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ - - -/* Peripheral: RTC */ -/* Description: Real time counter 0 */ - -/* Register: RTC_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */ -#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ - -/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */ -#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ - -/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */ -#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ - -/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */ -#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ - -/* Bit 1 : Write '1' to Enable interrupt for OVRFLW event */ -#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ -#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ -#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */ - -/* Bit 0 : Write '1' to Enable interrupt for TICK event */ -#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ -#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ -#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */ - -/* Register: RTC_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */ -#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ - -/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */ -#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ - -/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */ -#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ - -/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */ -#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ - -/* Bit 1 : Write '1' to Disable interrupt for OVRFLW event */ -#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ -#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ -#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ - -/* Bit 0 : Write '1' to Disable interrupt for TICK event */ -#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ -#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ -#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */ - -/* Register: RTC_EVTEN */ -/* Description: Enable or disable event routing */ - -/* Bit 19 : Enable or disable event routing for COMPARE[3] event */ -#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */ - -/* Bit 18 : Enable or disable event routing for COMPARE[2] event */ -#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */ - -/* Bit 17 : Enable or disable event routing for COMPARE[1] event */ -#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */ - -/* Bit 16 : Enable or disable event routing for COMPARE[0] event */ -#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */ - -/* Bit 1 : Enable or disable event routing for OVRFLW event */ -#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ -#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ -#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */ - -/* Bit 0 : Enable or disable event routing for TICK event */ -#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ -#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ -#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */ - -/* Register: RTC_EVTENSET */ -/* Description: Enable event routing */ - -/* Bit 19 : Write '1' to Enable event routing for COMPARE[3] event */ -#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */ - -/* Bit 18 : Write '1' to Enable event routing for COMPARE[2] event */ -#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */ - -/* Bit 17 : Write '1' to Enable event routing for COMPARE[1] event */ -#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */ - -/* Bit 16 : Write '1' to Enable event routing for COMPARE[0] event */ -#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */ - -/* Bit 1 : Write '1' to Enable event routing for OVRFLW event */ -#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ -#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ -#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */ - -/* Bit 0 : Write '1' to Enable event routing for TICK event */ -#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ -#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ -#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */ - -/* Register: RTC_EVTENCLR */ -/* Description: Disable event routing */ - -/* Bit 19 : Write '1' to Disable event routing for COMPARE[3] event */ -#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ - -/* Bit 18 : Write '1' to Disable event routing for COMPARE[2] event */ -#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ - -/* Bit 17 : Write '1' to Disable event routing for COMPARE[1] event */ -#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ - -/* Bit 16 : Write '1' to Disable event routing for COMPARE[0] event */ -#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ - -/* Bit 1 : Write '1' to Disable event routing for OVRFLW event */ -#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ -#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ -#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ - -/* Bit 0 : Write '1' to Disable event routing for TICK event */ -#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ -#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ -#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */ - -/* Register: RTC_COUNTER */ -/* Description: Current COUNTER value */ - -/* Bits 23..0 : Counter value */ -#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ -#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ - -/* Register: RTC_PRESCALER */ -/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */ - -/* Bits 11..0 : Prescaler value */ -#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ -#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ - -/* Register: RTC_CC */ -/* Description: Description collection[0]: Compare register 0 */ - -/* Bits 23..0 : Compare value */ -#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ -#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ - - -/* Peripheral: SAADC */ -/* Description: Analog to Digital Converter */ - -/* Register: SAADC_INTEN */ -/* Description: Enable or disable interrupt */ - -/* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */ -#define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ -#define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ -#define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */ - -/* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */ -#define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ -#define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ -#define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */ - -/* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */ -#define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ -#define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ -#define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */ - -/* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */ -#define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ -#define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ -#define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */ - -/* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */ -#define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ -#define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ -#define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */ - -/* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */ -#define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ -#define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ -#define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */ - -/* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */ -#define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ -#define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ -#define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */ - -/* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */ -#define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ -#define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ -#define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */ - -/* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */ -#define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ -#define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ -#define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */ - -/* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */ -#define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ -#define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ -#define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */ - -/* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */ -#define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ -#define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ -#define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */ - -/* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */ -#define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ -#define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ -#define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */ - -/* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */ -#define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ -#define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ -#define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */ - -/* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */ -#define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ -#define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ -#define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */ - -/* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */ -#define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ -#define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ -#define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */ - -/* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */ -#define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ -#define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ -#define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */ - -/* Bit 5 : Enable or disable interrupt for STOPPED event */ -#define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ -#define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ - -/* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */ -#define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ -#define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ -#define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */ - -/* Bit 3 : Enable or disable interrupt for RESULTDONE event */ -#define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ -#define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ -#define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */ - -/* Bit 2 : Enable or disable interrupt for DONE event */ -#define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */ -#define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ -#define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */ - -/* Bit 1 : Enable or disable interrupt for END event */ -#define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */ -#define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */ -#define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */ - -/* Bit 0 : Enable or disable interrupt for STARTED event */ -#define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ -#define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ -#define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */ - -/* Register: SAADC_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 21 : Write '1' to Enable interrupt for CH[7].LIMITL event */ -#define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ -#define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ -#define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */ - -/* Bit 20 : Write '1' to Enable interrupt for CH[7].LIMITH event */ -#define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ -#define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ -#define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */ - -/* Bit 19 : Write '1' to Enable interrupt for CH[6].LIMITL event */ -#define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ -#define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ -#define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */ - -/* Bit 18 : Write '1' to Enable interrupt for CH[6].LIMITH event */ -#define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ -#define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ -#define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */ - -/* Bit 17 : Write '1' to Enable interrupt for CH[5].LIMITL event */ -#define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ -#define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ -#define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */ - -/* Bit 16 : Write '1' to Enable interrupt for CH[5].LIMITH event */ -#define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ -#define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ -#define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */ - -/* Bit 15 : Write '1' to Enable interrupt for CH[4].LIMITL event */ -#define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ -#define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ -#define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */ - -/* Bit 14 : Write '1' to Enable interrupt for CH[4].LIMITH event */ -#define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ -#define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ -#define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */ - -/* Bit 13 : Write '1' to Enable interrupt for CH[3].LIMITL event */ -#define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ -#define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ -#define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */ - -/* Bit 12 : Write '1' to Enable interrupt for CH[3].LIMITH event */ -#define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ -#define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ -#define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */ - -/* Bit 11 : Write '1' to Enable interrupt for CH[2].LIMITL event */ -#define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ -#define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ -#define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */ - -/* Bit 10 : Write '1' to Enable interrupt for CH[2].LIMITH event */ -#define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ -#define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ -#define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */ - -/* Bit 9 : Write '1' to Enable interrupt for CH[1].LIMITL event */ -#define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ -#define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ -#define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */ - -/* Bit 8 : Write '1' to Enable interrupt for CH[1].LIMITH event */ -#define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ -#define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ -#define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */ - -/* Bit 7 : Write '1' to Enable interrupt for CH[0].LIMITL event */ -#define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ -#define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ -#define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */ - -/* Bit 6 : Write '1' to Enable interrupt for CH[0].LIMITH event */ -#define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ -#define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ -#define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */ - -/* Bit 5 : Write '1' to Enable interrupt for STOPPED event */ -#define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ -#define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ - -/* Bit 4 : Write '1' to Enable interrupt for CALIBRATEDONE event */ -#define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ -#define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ -#define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */ - -/* Bit 3 : Write '1' to Enable interrupt for RESULTDONE event */ -#define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ -#define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ -#define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */ - -/* Bit 2 : Write '1' to Enable interrupt for DONE event */ -#define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */ -#define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ -#define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */ - -/* Bit 1 : Write '1' to Enable interrupt for END event */ -#define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */ -#define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ -#define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_END_Set (1UL) /*!< Enable */ - -/* Bit 0 : Write '1' to Enable interrupt for STARTED event */ -#define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ -#define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ -#define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */ - -/* Register: SAADC_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 21 : Write '1' to Disable interrupt for CH[7].LIMITL event */ -#define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ -#define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ -#define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */ - -/* Bit 20 : Write '1' to Disable interrupt for CH[7].LIMITH event */ -#define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ -#define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ -#define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */ - -/* Bit 19 : Write '1' to Disable interrupt for CH[6].LIMITL event */ -#define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ -#define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ -#define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */ - -/* Bit 18 : Write '1' to Disable interrupt for CH[6].LIMITH event */ -#define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ -#define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ -#define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */ - -/* Bit 17 : Write '1' to Disable interrupt for CH[5].LIMITL event */ -#define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ -#define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ -#define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */ - -/* Bit 16 : Write '1' to Disable interrupt for CH[5].LIMITH event */ -#define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ -#define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ -#define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */ - -/* Bit 15 : Write '1' to Disable interrupt for CH[4].LIMITL event */ -#define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ -#define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ -#define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */ - -/* Bit 14 : Write '1' to Disable interrupt for CH[4].LIMITH event */ -#define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ -#define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ -#define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */ - -/* Bit 13 : Write '1' to Disable interrupt for CH[3].LIMITL event */ -#define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ -#define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ -#define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */ - -/* Bit 12 : Write '1' to Disable interrupt for CH[3].LIMITH event */ -#define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ -#define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ -#define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */ - -/* Bit 11 : Write '1' to Disable interrupt for CH[2].LIMITL event */ -#define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ -#define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ -#define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */ - -/* Bit 10 : Write '1' to Disable interrupt for CH[2].LIMITH event */ -#define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ -#define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ -#define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */ - -/* Bit 9 : Write '1' to Disable interrupt for CH[1].LIMITL event */ -#define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ -#define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ -#define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */ - -/* Bit 8 : Write '1' to Disable interrupt for CH[1].LIMITH event */ -#define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ -#define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ -#define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */ - -/* Bit 7 : Write '1' to Disable interrupt for CH[0].LIMITL event */ -#define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ -#define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ -#define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */ - -/* Bit 6 : Write '1' to Disable interrupt for CH[0].LIMITH event */ -#define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ -#define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ -#define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */ - -/* Bit 5 : Write '1' to Disable interrupt for STOPPED event */ -#define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ -#define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ - -/* Bit 4 : Write '1' to Disable interrupt for CALIBRATEDONE event */ -#define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ -#define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ -#define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */ - -/* Bit 3 : Write '1' to Disable interrupt for RESULTDONE event */ -#define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ -#define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ -#define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */ - -/* Bit 2 : Write '1' to Disable interrupt for DONE event */ -#define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */ -#define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ -#define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */ - -/* Bit 1 : Write '1' to Disable interrupt for END event */ -#define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ -#define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ -#define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */ - -/* Bit 0 : Write '1' to Disable interrupt for STARTED event */ -#define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ -#define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ -#define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ - -/* Register: SAADC_STATUS */ -/* Description: Status */ - -/* Bit 0 : Status */ -#define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ -#define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ -#define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */ -#define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */ - -/* Register: SAADC_ENABLE */ -/* Description: Enable or disable ADC */ - -/* Bit 0 : Enable or disable ADC */ -#define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */ -#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */ - -/* Register: SAADC_CH_PSELP */ -/* Description: Description cluster[0]: Input positive pin selection for CH[0] */ - -/* Bits 4..0 : Analog positive input channel */ -#define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */ -#define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */ -#define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */ -#define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */ -#define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */ -#define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */ -#define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */ -#define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */ -#define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */ -#define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */ -#define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */ -#define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */ - -/* Register: SAADC_CH_PSELN */ -/* Description: Description cluster[0]: Input negative pin selection for CH[0] */ - -/* Bits 4..0 : Analog negative input, enables differential channel */ -#define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */ -#define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */ -#define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */ -#define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */ -#define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */ -#define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */ -#define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */ -#define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */ -#define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */ -#define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */ -#define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */ -#define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */ - -/* Register: SAADC_CH_CONFIG */ -/* Description: Description cluster[0]: Input configuration for CH[0] */ - -/* Bit 24 : Enable burst mode */ -#define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */ -#define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */ -#define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */ -#define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */ - -/* Bit 20 : Enable differential mode */ -#define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */ -#define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ -#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */ -#define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */ - -/* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */ -#define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */ -#define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */ -#define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */ -#define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */ -#define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */ -#define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */ -#define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */ -#define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */ - -/* Bit 12 : Reference control */ -#define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */ -#define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ -#define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */ -#define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */ - -/* Bits 10..8 : Gain control */ -#define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */ -#define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */ -#define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */ -#define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */ -#define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */ -#define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */ -#define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */ -#define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */ -#define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */ -#define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */ - -/* Bits 5..4 : Negative channel resistor control */ -#define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */ -#define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */ -#define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */ -#define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */ -#define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */ -#define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */ - -/* Bits 1..0 : Positive channel resistor control */ -#define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */ -#define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */ -#define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */ -#define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */ -#define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */ -#define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */ - -/* Register: SAADC_CH_LIMIT */ -/* Description: Description cluster[0]: High/low limits for event monitoring a channel */ - -/* Bits 31..16 : High level limit */ -#define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */ -#define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */ - -/* Bits 15..0 : Low level limit */ -#define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */ -#define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */ - -/* Register: SAADC_RESOLUTION */ -/* Description: Resolution configuration */ - -/* Bits 2..0 : Set the resolution */ -#define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */ -#define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */ -#define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */ -#define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */ -#define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */ -#define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */ - -/* Register: SAADC_OVERSAMPLE */ -/* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */ - -/* Bits 3..0 : Oversample control */ -#define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */ -#define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */ -#define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */ -#define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */ -#define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */ -#define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */ -#define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */ -#define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */ -#define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */ -#define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */ -#define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */ - -/* Register: SAADC_SAMPLERATE */ -/* Description: Controls normal or continuous sample rate */ - -/* Bit 12 : Select mode for sample rate control */ -#define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */ -#define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */ -#define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */ -#define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */ - -/* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */ -#define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */ -#define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */ - -/* Register: SAADC_RESULT_PTR */ -/* Description: Data pointer */ - -/* Bits 31..0 : Data pointer */ -#define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ -#define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ - -/* Register: SAADC_RESULT_MAXCNT */ -/* Description: Maximum number of buffer words to transfer */ - -/* Bits 14..0 : Maximum number of buffer words to transfer */ -#define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ -#define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ - -/* Register: SAADC_RESULT_AMOUNT */ -/* Description: Number of buffer words transferred since last START */ - -/* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */ -#define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ -#define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ - - -/* Peripheral: SPI */ -/* Description: Serial Peripheral Interface 0 */ - -/* Register: SPI_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 2 : Write '1' to Enable interrupt for READY event */ -#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ -#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ -#define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ -#define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ -#define SPI_INTENSET_READY_Set (1UL) /*!< Enable */ - -/* Register: SPI_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 2 : Write '1' to Disable interrupt for READY event */ -#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ -#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ -#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ -#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ -#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */ - -/* Register: SPI_ENABLE */ -/* Description: Enable SPI */ - -/* Bits 3..0 : Enable or disable SPI */ -#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */ -#define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */ - -/* Register: SPI_PSEL_SCK */ -/* Description: Pin select for SCK */ - -/* Bits 31..0 : Pin number configuration for SPI SCK signal */ -#define SPI_PSEL_SCK_PSELSCK_Pos (0UL) /*!< Position of PSELSCK field. */ -#define SPI_PSEL_SCK_PSELSCK_Msk (0xFFFFFFFFUL << SPI_PSEL_SCK_PSELSCK_Pos) /*!< Bit mask of PSELSCK field. */ -#define SPI_PSEL_SCK_PSELSCK_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ - -/* Register: SPI_PSEL_MOSI */ -/* Description: Pin select for MOSI */ - -/* Bits 31..0 : Pin number configuration for SPI MOSI signal */ -#define SPI_PSEL_MOSI_PSELMOSI_Pos (0UL) /*!< Position of PSELMOSI field. */ -#define SPI_PSEL_MOSI_PSELMOSI_Msk (0xFFFFFFFFUL << SPI_PSEL_MOSI_PSELMOSI_Pos) /*!< Bit mask of PSELMOSI field. */ -#define SPI_PSEL_MOSI_PSELMOSI_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ - -/* Register: SPI_PSEL_MISO */ -/* Description: Pin select for MISO */ - -/* Bits 31..0 : Pin number configuration for SPI MISO signal */ -#define SPI_PSEL_MISO_PSELMISO_Pos (0UL) /*!< Position of PSELMISO field. */ -#define SPI_PSEL_MISO_PSELMISO_Msk (0xFFFFFFFFUL << SPI_PSEL_MISO_PSELMISO_Pos) /*!< Bit mask of PSELMISO field. */ -#define SPI_PSEL_MISO_PSELMISO_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ - -/* Register: SPI_RXD */ -/* Description: RXD register */ - -/* Bits 7..0 : RX data received. Double buffered */ -#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ -#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ - -/* Register: SPI_TXD */ -/* Description: TXD register */ - -/* Bits 7..0 : TX data to send. Double buffered */ -#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ -#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ - -/* Register: SPI_FREQUENCY */ -/* Description: SPI frequency */ - -/* Bits 31..0 : SPI master data rate */ -#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ -#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ -#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ -#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ -#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ -#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ -#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ -#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ -#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ - -/* Register: SPI_CONFIG */ -/* Description: Configuration register */ - -/* Bit 2 : Serial clock (SCK) polarity */ -#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ -#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ -#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ -#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ - -/* Bit 1 : Serial clock (SCK) phase */ -#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ -#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ -#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ -#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ - -/* Bit 0 : Bit order */ -#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ -#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ -#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ -#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ - - -/* Peripheral: SPIM */ -/* Description: Serial Peripheral Interface Master with EasyDMA 0 */ - -/* Register: SPIM_SHORTS */ -/* Description: Shortcut register */ - -/* Bit 17 : Shortcut between END event and START task */ -#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ -#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ -#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ -#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ - -/* Register: SPIM_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 19 : Write '1' to Enable interrupt for STARTED event */ -#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ -#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ -#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ -#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ -#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */ - -/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */ -#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ -#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ -#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ -#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ -#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */ - -/* Bit 6 : Write '1' to Enable interrupt for END event */ -#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ -#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ -#define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ -#define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ -#define SPIM_INTENSET_END_Set (1UL) /*!< Enable */ - -/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ -#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ -#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ -#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ -#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ -#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */ - -/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ -#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ -#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ - -/* Register: SPIM_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 19 : Write '1' to Disable interrupt for STARTED event */ -#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ -#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ -#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ -#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ -#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ - -/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */ -#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ -#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ -#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ -#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ -#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ - -/* Bit 6 : Write '1' to Disable interrupt for END event */ -#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ -#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ -#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ -#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ -#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */ - -/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ -#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ -#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ -#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ -#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ -#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ - -/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ -#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ -#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ - -/* Register: SPIM_ENABLE */ -/* Description: Enable SPIM */ - -/* Bits 3..0 : Enable or disable SPIM */ -#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */ -#define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */ - -/* Register: SPIM_PSEL_SCK */ -/* Description: Pin select for SCK */ - -/* Bit 31 : Connection */ -#define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ -#define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bits 4..0 : Pin number */ -#define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ - -/* Register: SPIM_PSEL_MOSI */ -/* Description: Pin select for MOSI signal */ - -/* Bit 31 : Connection */ -#define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ -#define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bits 4..0 : Pin number */ -#define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ - -/* Register: SPIM_PSEL_MISO */ -/* Description: Pin select for MISO signal */ - -/* Bit 31 : Connection */ -#define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ -#define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bits 4..0 : Pin number */ -#define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ - -/* Register: SPIM_FREQUENCY */ -/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */ - -/* Bits 31..0 : SPI master data rate */ -#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ -#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ -#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ -#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ -#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ -#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ -#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ -#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ -#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ - -/* Register: SPIM_RXD_PTR */ -/* Description: Data pointer */ - -/* Bits 31..0 : Data pointer */ -#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ -#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ - -/* Register: SPIM_RXD_MAXCNT */ -/* Description: Maximum number of bytes in receive buffer */ - -/* Bits 7..0 : Maximum number of bytes in receive buffer */ -#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ -#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ - -/* Register: SPIM_RXD_AMOUNT */ -/* Description: Number of bytes transferred in the last transaction */ - -/* Bits 7..0 : Number of bytes transferred in the last transaction */ -#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ -#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ - -/* Register: SPIM_RXD_LIST */ -/* Description: EasyDMA list type */ - -/* Bits 2..0 : List type */ -#define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ -#define SPIM_RXD_LIST_LIST_Msk (0x7UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ -#define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ -#define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ - -/* Register: SPIM_TXD_PTR */ -/* Description: Data pointer */ - -/* Bits 31..0 : Data pointer */ -#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ -#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ - -/* Register: SPIM_TXD_MAXCNT */ -/* Description: Maximum number of bytes in transmit buffer */ - -/* Bits 7..0 : Maximum number of bytes in transmit buffer */ -#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ -#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ - -/* Register: SPIM_TXD_AMOUNT */ -/* Description: Number of bytes transferred in the last transaction */ - -/* Bits 7..0 : Number of bytes transferred in the last transaction */ -#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ -#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ - -/* Register: SPIM_TXD_LIST */ -/* Description: EasyDMA list type */ - -/* Bits 2..0 : List type */ -#define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ -#define SPIM_TXD_LIST_LIST_Msk (0x7UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ -#define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ -#define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ - -/* Register: SPIM_CONFIG */ -/* Description: Configuration register */ - -/* Bit 2 : Serial clock (SCK) polarity */ -#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ -#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ -#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ -#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ - -/* Bit 1 : Serial clock (SCK) phase */ -#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ -#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ -#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ -#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ - -/* Bit 0 : Bit order */ -#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ -#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ -#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ -#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ - -/* Register: SPIM_ORC */ -/* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer. */ - -/* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. */ -#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ -#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ - - -/* Peripheral: SPIS */ -/* Description: SPI Slave 0 */ - -/* Register: SPIS_SHORTS */ -/* Description: Shortcut register */ - -/* Bit 2 : Shortcut between END event and ACQUIRE task */ -#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ -#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ -#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */ -#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */ - -/* Register: SPIS_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 10 : Write '1' to Enable interrupt for ACQUIRED event */ -#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ -#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ -#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ -#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ -#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */ - -/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ -#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ -#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ -#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ -#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ -#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */ - -/* Bit 1 : Write '1' to Enable interrupt for END event */ -#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ -#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ -#define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ -#define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ -#define SPIS_INTENSET_END_Set (1UL) /*!< Enable */ - -/* Register: SPIS_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 10 : Write '1' to Disable interrupt for ACQUIRED event */ -#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ -#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ -#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ -#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ -#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */ - -/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ -#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ -#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ -#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ -#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ -#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ - -/* Bit 1 : Write '1' to Disable interrupt for END event */ -#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ -#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ -#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ -#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ -#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */ - -/* Register: SPIS_SEMSTAT */ -/* Description: Semaphore status register */ - -/* Bits 1..0 : Semaphore status */ -#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ -#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ -#define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */ -#define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */ -#define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */ -#define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */ - -/* Register: SPIS_STATUS */ -/* Description: Status from last transaction */ - -/* Bit 1 : RX buffer overflow detected, and prevented */ -#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ -#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ -#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */ -#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */ -#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */ - -/* Bit 0 : TX buffer over-read detected, and prevented */ -#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ -#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ -#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */ -#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */ -#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */ - -/* Register: SPIS_ENABLE */ -/* Description: Enable SPI slave */ - -/* Bits 3..0 : Enable or disable SPI slave */ -#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */ -#define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */ - -/* Register: SPIS_PSEL_SCK */ -/* Description: Pin select for SCK */ - -/* Bit 31 : Connection */ -#define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ -#define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bits 4..0 : Pin number */ -#define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ - -/* Register: SPIS_PSEL_MISO */ -/* Description: Pin select for MISO signal */ - -/* Bit 31 : Connection */ -#define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ -#define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bits 4..0 : Pin number */ -#define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ - -/* Register: SPIS_PSEL_MOSI */ -/* Description: Pin select for MOSI signal */ - -/* Bit 31 : Connection */ -#define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ -#define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bits 4..0 : Pin number */ -#define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ - -/* Register: SPIS_PSEL_CSN */ -/* Description: Pin select for CSN signal */ - -/* Bit 31 : Connection */ -#define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */ -#define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bits 4..0 : Pin number */ -#define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */ - -/* Register: SPIS_RXD_PTR */ -/* Description: RXD data pointer */ - -/* Bits 31..0 : RXD data pointer */ -#define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ -#define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ - -/* Register: SPIS_RXD_MAXCNT */ -/* Description: Maximum number of bytes in receive buffer */ - -/* Bits 7..0 : Maximum number of bytes in receive buffer */ -#define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ -#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ - -/* Register: SPIS_RXD_AMOUNT */ -/* Description: Number of bytes received in last granted transaction */ - -/* Bits 7..0 : Number of bytes received in the last granted transaction */ -#define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ -#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ - -/* Register: SPIS_TXD_PTR */ -/* Description: TXD data pointer */ - -/* Bits 31..0 : TXD data pointer */ -#define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ -#define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ - -/* Register: SPIS_TXD_MAXCNT */ -/* Description: Maximum number of bytes in transmit buffer */ - -/* Bits 7..0 : Maximum number of bytes in transmit buffer */ -#define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ -#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ - -/* Register: SPIS_TXD_AMOUNT */ -/* Description: Number of bytes transmitted in last granted transaction */ - -/* Bits 7..0 : Number of bytes transmitted in last granted transaction */ -#define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ -#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ - -/* Register: SPIS_CONFIG */ -/* Description: Configuration register */ - -/* Bit 2 : Serial clock (SCK) polarity */ -#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ -#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ -#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ -#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ - -/* Bit 1 : Serial clock (SCK) phase */ -#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ -#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ -#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ -#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ - -/* Bit 0 : Bit order */ -#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ -#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ -#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ -#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ - -/* Register: SPIS_DEF */ -/* Description: Default character. Character clocked out in case of an ignored transaction. */ - -/* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */ -#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ -#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ - -/* Register: SPIS_ORC */ -/* Description: Over-read character */ - -/* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */ -#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ -#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ - - -/* Peripheral: TEMP */ -/* Description: Temperature Sensor */ - -/* Register: TEMP_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 0 : Write '1' to Enable interrupt for DATARDY event */ -#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ -#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ -#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */ -#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */ -#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */ - -/* Register: TEMP_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 0 : Write '1' to Disable interrupt for DATARDY event */ -#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ -#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ -#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */ -#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */ -#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */ - -/* Register: TEMP_TEMP */ -/* Description: Temperature in degC (0.25deg steps) */ - -/* Bits 31..0 : Temperature in degC (0.25deg steps) */ -#define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */ -#define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */ - -/* Register: TEMP_A0 */ -/* Description: Slope of 1st piece wise linear function */ - -/* Bits 11..0 : Slope of 1st piece wise linear function */ -#define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */ -#define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */ - -/* Register: TEMP_A1 */ -/* Description: Slope of 2nd piece wise linear function */ - -/* Bits 11..0 : Slope of 2nd piece wise linear function */ -#define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */ -#define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */ - -/* Register: TEMP_A2 */ -/* Description: Slope of 3rd piece wise linear function */ - -/* Bits 11..0 : Slope of 3rd piece wise linear function */ -#define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */ -#define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */ - -/* Register: TEMP_A3 */ -/* Description: Slope of 4th piece wise linear function */ - -/* Bits 11..0 : Slope of 4th piece wise linear function */ -#define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */ -#define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */ - -/* Register: TEMP_A4 */ -/* Description: Slope of 5th piece wise linear function */ - -/* Bits 11..0 : Slope of 5th piece wise linear function */ -#define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */ -#define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */ - -/* Register: TEMP_A5 */ -/* Description: Slope of 6th piece wise linear function */ - -/* Bits 11..0 : Slope of 6th piece wise linear function */ -#define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */ -#define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */ - -/* Register: TEMP_B0 */ -/* Description: y-intercept of 1st piece wise linear function */ - -/* Bits 13..0 : y-intercept of 1st piece wise linear function */ -#define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */ -#define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */ - -/* Register: TEMP_B1 */ -/* Description: y-intercept of 2nd piece wise linear function */ - -/* Bits 13..0 : y-intercept of 2nd piece wise linear function */ -#define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */ -#define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */ - -/* Register: TEMP_B2 */ -/* Description: y-intercept of 3rd piece wise linear function */ - -/* Bits 13..0 : y-intercept of 3rd piece wise linear function */ -#define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */ -#define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */ - -/* Register: TEMP_B3 */ -/* Description: y-intercept of 4th piece wise linear function */ - -/* Bits 13..0 : y-intercept of 4th piece wise linear function */ -#define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */ -#define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */ - -/* Register: TEMP_B4 */ -/* Description: y-intercept of 5th piece wise linear function */ - -/* Bits 13..0 : y-intercept of 5th piece wise linear function */ -#define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */ -#define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */ - -/* Register: TEMP_B5 */ -/* Description: y-intercept of 6th piece wise linear function */ - -/* Bits 13..0 : y-intercept of 6th piece wise linear function */ -#define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */ -#define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ - -/* Register: TEMP_T0 */ -/* Description: End point of 1st piece wise linear function */ - -/* Bits 7..0 : End point of 1st piece wise linear function */ -#define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */ -#define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */ - -/* Register: TEMP_T1 */ -/* Description: End point of 2nd piece wise linear function */ - -/* Bits 7..0 : End point of 2nd piece wise linear function */ -#define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ -#define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */ - -/* Register: TEMP_T2 */ -/* Description: End point of 3rd piece wise linear function */ - -/* Bits 7..0 : End point of 3rd piece wise linear function */ -#define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */ -#define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */ - -/* Register: TEMP_T3 */ -/* Description: End point of 4th piece wise linear function */ - -/* Bits 7..0 : End point of 4th piece wise linear function */ -#define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */ -#define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */ - -/* Register: TEMP_T4 */ -/* Description: End point of 5th piece wise linear function */ - -/* Bits 7..0 : End point of 5th piece wise linear function */ -#define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */ -#define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */ - - -/* Peripheral: TIMER */ -/* Description: Timer/Counter 0 */ - -/* Register: TIMER_SHORTS */ -/* Description: Shortcut register */ - -/* Bit 13 : Shortcut between COMPARE[5] event and STOP task */ -#define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */ -#define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */ -#define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 12 : Shortcut between COMPARE[4] event and STOP task */ -#define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */ -#define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */ -#define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 11 : Shortcut between COMPARE[3] event and STOP task */ -#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ -#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ -#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 10 : Shortcut between COMPARE[2] event and STOP task */ -#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ -#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ -#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 9 : Shortcut between COMPARE[1] event and STOP task */ -#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ -#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ -#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 8 : Shortcut between COMPARE[0] event and STOP task */ -#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ -#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ -#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */ -#define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */ -#define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */ -#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */ -#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */ -#define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */ -#define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */ -#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */ -#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */ -#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ -#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ -#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */ -#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */ -#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ -#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ -#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */ -#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */ -#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ -#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ -#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */ -#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */ -#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ -#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ -#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */ -#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */ - -/* Register: TIMER_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 21 : Write '1' to Enable interrupt for COMPARE[5] event */ -#define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ -#define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ -#define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ -#define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ -#define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */ - -/* Bit 20 : Write '1' to Enable interrupt for COMPARE[4] event */ -#define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ -#define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ -#define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ -#define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ -#define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */ - -/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */ -#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ -#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ -#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ - -/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */ -#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ -#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ -#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ - -/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */ -#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ -#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ -#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ - -/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */ -#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ -#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ -#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ - -/* Register: TIMER_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 21 : Write '1' to Disable interrupt for COMPARE[5] event */ -#define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ -#define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ -#define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ -#define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ -#define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */ - -/* Bit 20 : Write '1' to Disable interrupt for COMPARE[4] event */ -#define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ -#define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ -#define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ -#define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ -#define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */ - -/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */ -#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ -#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ -#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ - -/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */ -#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ -#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ -#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ - -/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */ -#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ -#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ -#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ - -/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */ -#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ -#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ -#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ - -/* Register: TIMER_MODE */ -/* Description: Timer mode selection */ - -/* Bits 1..0 : Timer mode */ -#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ -#define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ -#define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */ -#define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */ -#define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */ - -/* Register: TIMER_BITMODE */ -/* Description: Configure the number of bits used by the TIMER */ - -/* Bits 1..0 : Timer bit width */ -#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ -#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ -#define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */ -#define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */ -#define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */ -#define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */ - -/* Register: TIMER_PRESCALER */ -/* Description: Timer prescaler register */ - -/* Bits 3..0 : Prescaler value */ -#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ -#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ - -/* Register: TIMER_CC */ -/* Description: Description collection[0]: Capture/Compare register 0 */ - -/* Bits 31..0 : Capture/Compare value */ -#define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */ -#define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */ - - -/* Peripheral: TWI */ -/* Description: I2C compatible Two-Wire Interface 0 */ - -/* Register: TWI_SHORTS */ -/* Description: Shortcut register */ - -/* Bit 1 : Shortcut between BB event and STOP task */ -#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */ -#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */ -#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 0 : Shortcut between BB event and SUSPEND task */ -#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */ -#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */ -#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ -#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ - -/* Register: TWI_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */ -#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ -#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ -#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ -#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ -#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ - -/* Bit 14 : Write '1' to Enable interrupt for BB event */ -#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ -#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ -#define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */ -#define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */ -#define TWI_INTENSET_BB_Set (1UL) /*!< Enable */ - -/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ -#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ -#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ -#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ -#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */ - -/* Bit 7 : Write '1' to Enable interrupt for TXDSENT event */ -#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ -#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ -#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ -#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ -#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */ - -/* Bit 2 : Write '1' to Enable interrupt for RXDREADY event */ -#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ -#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ -#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ -#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ -#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */ - -/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ -#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ -#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */ - -/* Register: TWI_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */ -#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ -#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ -#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ -#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ -#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ - -/* Bit 14 : Write '1' to Disable interrupt for BB event */ -#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ -#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ -#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */ -#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */ -#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */ - -/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ -#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ -#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ -#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ -#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ - -/* Bit 7 : Write '1' to Disable interrupt for TXDSENT event */ -#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ -#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ -#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ -#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ -#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */ - -/* Bit 2 : Write '1' to Disable interrupt for RXDREADY event */ -#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ -#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ -#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ -#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ -#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */ - -/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ -#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ -#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ - -/* Register: TWI_ERRORSRC */ -/* Description: Error source */ - -/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ -#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ -#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ -#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */ -#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */ -#define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Write: clear error on writing '1' */ - -/* Bit 1 : NACK received after sending the address (write '1' to clear) */ -#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ -#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ -#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */ -#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */ -#define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Write: clear error on writing '1' */ - -/* Bit 0 : Overrun error */ -#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ -#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ -#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */ -#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */ -#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Write: clear error on writing '1' */ - -/* Register: TWI_ENABLE */ -/* Description: Enable TWI */ - -/* Bits 3..0 : Enable or disable TWI */ -#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */ -#define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */ - -/* Register: TWI_PSELSCL */ -/* Description: Pin select for SCL */ - -/* Bits 31..0 : Pin number configuration for TWI SCL signal */ -#define TWI_PSELSCL_PSELSCL_Pos (0UL) /*!< Position of PSELSCL field. */ -#define TWI_PSELSCL_PSELSCL_Msk (0xFFFFFFFFUL << TWI_PSELSCL_PSELSCL_Pos) /*!< Bit mask of PSELSCL field. */ -#define TWI_PSELSCL_PSELSCL_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ - -/* Register: TWI_PSELSDA */ -/* Description: Pin select for SDA */ - -/* Bits 31..0 : Pin number configuration for TWI SDA signal */ -#define TWI_PSELSDA_PSELSDA_Pos (0UL) /*!< Position of PSELSDA field. */ -#define TWI_PSELSDA_PSELSDA_Msk (0xFFFFFFFFUL << TWI_PSELSDA_PSELSDA_Pos) /*!< Bit mask of PSELSDA field. */ -#define TWI_PSELSDA_PSELSDA_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ - -/* Register: TWI_RXD */ -/* Description: RXD register */ - -/* Bits 7..0 : RXD register */ -#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ -#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ - -/* Register: TWI_TXD */ -/* Description: TXD register */ - -/* Bits 7..0 : TXD register */ -#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ -#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ - -/* Register: TWI_FREQUENCY */ -/* Description: TWI frequency */ - -/* Bits 31..0 : TWI master clock frequency */ -#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ -#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ -#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ -#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ -#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */ - -/* Register: TWI_ADDRESS */ -/* Description: Address used in the TWI transfer */ - -/* Bits 6..0 : Address used in the TWI transfer */ -#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ -#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ - - -/* Peripheral: TWIM */ -/* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */ - -/* Register: TWIM_SHORTS */ -/* Description: Shortcut register */ - -/* Bit 12 : Shortcut between LASTRX event and STOP task */ -#define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */ -#define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */ -#define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 10 : Shortcut between LASTRX event and STARTTX task */ -#define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */ -#define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */ -#define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */ -#define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 9 : Shortcut between LASTTX event and STOP task */ -#define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */ -#define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */ -#define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 8 : Shortcut between LASTTX event and SUSPEND task */ -#define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */ -#define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */ -#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ -#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 7 : Shortcut between LASTTX event and STARTRX task */ -#define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */ -#define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */ -#define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ -#define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ - -/* Register: TWIM_INTEN */ -/* Description: Enable or disable interrupt */ - -/* Bit 24 : Enable or disable interrupt for LASTTX event */ -#define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ -#define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ -#define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */ -#define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */ - -/* Bit 23 : Enable or disable interrupt for LASTRX event */ -#define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ -#define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ -#define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */ -#define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */ - -/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ -#define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ -#define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ -#define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ -#define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ - -/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ -#define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ -#define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ -#define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ -#define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ - -/* Bit 18 : Enable or disable interrupt for SUSPENDED event */ -#define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ -#define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ -#define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */ -#define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */ - -/* Bit 9 : Enable or disable interrupt for ERROR event */ -#define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ -#define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */ -#define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */ - -/* Bit 1 : Enable or disable interrupt for STOPPED event */ -#define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ -#define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ -#define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ - -/* Register: TWIM_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 24 : Write '1' to Enable interrupt for LASTTX event */ -#define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ -#define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ -#define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */ - -/* Bit 23 : Write '1' to Enable interrupt for LASTRX event */ -#define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ -#define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ -#define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */ - -/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */ -#define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ -#define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ -#define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ - -/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */ -#define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ -#define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ -#define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ - -/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */ -#define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ -#define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ -#define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ - -/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ -#define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ -#define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */ - -/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ -#define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ -#define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ - -/* Register: TWIM_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 24 : Write '1' to Disable interrupt for LASTTX event */ -#define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ -#define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ -#define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */ - -/* Bit 23 : Write '1' to Disable interrupt for LASTRX event */ -#define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ -#define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ -#define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */ - -/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */ -#define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ -#define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ -#define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ - -/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */ -#define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ -#define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ -#define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ - -/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */ -#define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ -#define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ -#define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ - -/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ -#define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ -#define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ - -/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ -#define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ -#define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ - -/* Register: TWIM_ERRORSRC */ -/* Description: Error source */ - -/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ -#define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ -#define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ -#define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ -#define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ - -/* Bit 1 : NACK received after sending the address (write '1' to clear) */ -#define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ -#define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ -#define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */ -#define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */ - -/* Bit 0 : Overrun error */ -#define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ -#define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ -#define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */ -#define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */ - -/* Register: TWIM_ENABLE */ -/* Description: Enable TWIM */ - -/* Bits 3..0 : Enable or disable TWIM */ -#define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */ -#define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */ - -/* Register: TWIM_PSEL_SCL */ -/* Description: Pin select for SCL signal */ - -/* Bit 31 : Connection */ -#define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ -#define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bits 4..0 : Pin number */ -#define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ - -/* Register: TWIM_PSEL_SDA */ -/* Description: Pin select for SDA signal */ - -/* Bit 31 : Connection */ -#define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ -#define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bits 4..0 : Pin number */ -#define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ - -/* Register: TWIM_FREQUENCY */ -/* Description: TWI frequency */ - -/* Bits 31..0 : TWI master clock frequency */ -#define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ -#define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ -#define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ -#define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ -#define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */ - -/* Register: TWIM_RXD_PTR */ -/* Description: Data pointer */ - -/* Bits 31..0 : Data pointer */ -#define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ -#define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ - -/* Register: TWIM_RXD_MAXCNT */ -/* Description: Maximum number of bytes in receive buffer */ - -/* Bits 7..0 : Maximum number of bytes in receive buffer */ -#define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ -#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ - -/* Register: TWIM_RXD_AMOUNT */ -/* Description: Number of bytes transferred in the last transaction */ - -/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ -#define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ -#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ - -/* Register: TWIM_RXD_LIST */ -/* Description: EasyDMA list type */ - -/* Bits 2..0 : List type */ -#define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ -#define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ -#define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ -#define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ - -/* Register: TWIM_TXD_PTR */ -/* Description: Data pointer */ - -/* Bits 31..0 : Data pointer */ -#define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ -#define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ - -/* Register: TWIM_TXD_MAXCNT */ -/* Description: Maximum number of bytes in transmit buffer */ - -/* Bits 7..0 : Maximum number of bytes in transmit buffer */ -#define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ -#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ - -/* Register: TWIM_TXD_AMOUNT */ -/* Description: Number of bytes transferred in the last transaction */ - -/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ -#define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ -#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ - -/* Register: TWIM_TXD_LIST */ -/* Description: EasyDMA list type */ - -/* Bits 2..0 : List type */ -#define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ -#define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ -#define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ -#define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ - -/* Register: TWIM_ADDRESS */ -/* Description: Address used in the TWI transfer */ - -/* Bits 6..0 : Address used in the TWI transfer */ -#define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ -#define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ - - -/* Peripheral: TWIS */ -/* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */ - -/* Register: TWIS_SHORTS */ -/* Description: Shortcut register */ - -/* Bit 14 : Shortcut between READ event and SUSPEND task */ -#define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */ -#define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */ -#define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ -#define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 13 : Shortcut between WRITE event and SUSPEND task */ -#define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */ -#define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */ -#define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ -#define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ - -/* Register: TWIS_INTEN */ -/* Description: Enable or disable interrupt */ - -/* Bit 26 : Enable or disable interrupt for READ event */ -#define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */ -#define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */ -#define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */ -#define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */ - -/* Bit 25 : Enable or disable interrupt for WRITE event */ -#define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */ -#define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */ -#define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */ -#define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */ - -/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ -#define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ -#define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ -#define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ -#define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ - -/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ -#define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ -#define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ -#define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ -#define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ - -/* Bit 9 : Enable or disable interrupt for ERROR event */ -#define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ -#define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */ -#define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */ - -/* Bit 1 : Enable or disable interrupt for STOPPED event */ -#define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ -#define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ -#define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ - -/* Register: TWIS_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 26 : Write '1' to Enable interrupt for READ event */ -#define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */ -#define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */ -#define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */ -#define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */ -#define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */ - -/* Bit 25 : Write '1' to Enable interrupt for WRITE event */ -#define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */ -#define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */ -#define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */ -#define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */ -#define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */ - -/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */ -#define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ -#define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ -#define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ - -/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */ -#define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ -#define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ -#define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ - -/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ -#define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ -#define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ -#define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ -#define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */ - -/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ -#define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ -#define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */ - -/* Register: TWIS_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 26 : Write '1' to Disable interrupt for READ event */ -#define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */ -#define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */ -#define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */ -#define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */ -#define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */ - -/* Bit 25 : Write '1' to Disable interrupt for WRITE event */ -#define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */ -#define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */ -#define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */ -#define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */ -#define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */ - -/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */ -#define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ -#define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ -#define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ - -/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */ -#define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ -#define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ -#define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ - -/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ -#define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ -#define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ -#define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ -#define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ - -/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ -#define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ -#define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ - -/* Register: TWIS_ERRORSRC */ -/* Description: Error source */ - -/* Bit 3 : TX buffer over-read detected, and prevented */ -#define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */ -#define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ -#define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */ -#define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */ - -/* Bit 2 : NACK sent after receiving a data byte */ -#define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ -#define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ -#define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ -#define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ - -/* Bit 0 : RX buffer overflow detected, and prevented */ -#define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */ -#define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ -#define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */ -#define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */ - -/* Register: TWIS_MATCH */ -/* Description: Status register indicating which address had a match */ - -/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */ -#define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ -#define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ - -/* Register: TWIS_ENABLE */ -/* Description: Enable TWIS */ - -/* Bits 3..0 : Enable or disable TWIS */ -#define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */ -#define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */ - -/* Register: TWIS_PSEL_SCL */ -/* Description: Pin select for SCL signal */ - -/* Bit 31 : Connection */ -#define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ -#define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bits 4..0 : Pin number */ -#define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ - -/* Register: TWIS_PSEL_SDA */ -/* Description: Pin select for SDA signal */ - -/* Bit 31 : Connection */ -#define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ -#define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bits 4..0 : Pin number */ -#define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ - -/* Register: TWIS_RXD_PTR */ -/* Description: RXD Data pointer */ - -/* Bits 31..0 : RXD Data pointer */ -#define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ -#define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ - -/* Register: TWIS_RXD_MAXCNT */ -/* Description: Maximum number of bytes in RXD buffer */ - -/* Bits 7..0 : Maximum number of bytes in RXD buffer */ -#define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ -#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ - -/* Register: TWIS_RXD_AMOUNT */ -/* Description: Number of bytes transferred in the last RXD transaction */ - -/* Bits 7..0 : Number of bytes transferred in the last RXD transaction */ -#define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ -#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ - -/* Register: TWIS_TXD_PTR */ -/* Description: TXD Data pointer */ - -/* Bits 31..0 : TXD Data pointer */ -#define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ -#define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ - -/* Register: TWIS_TXD_MAXCNT */ -/* Description: Maximum number of bytes in TXD buffer */ - -/* Bits 7..0 : Maximum number of bytes in TXD buffer */ -#define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ -#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ - -/* Register: TWIS_TXD_AMOUNT */ -/* Description: Number of bytes transferred in the last TXD transaction */ - -/* Bits 7..0 : Number of bytes transferred in the last TXD transaction */ -#define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ -#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ - -/* Register: TWIS_ADDRESS */ -/* Description: Description collection[0]: TWI slave address 0 */ - -/* Bits 6..0 : TWI slave address */ -#define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ -#define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ - -/* Register: TWIS_CONFIG */ -/* Description: Configuration register for the address match mechanism */ - -/* Bit 1 : Enable or disable address matching on ADDRESS[1] */ -#define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */ -#define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */ -#define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */ -#define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */ - -/* Bit 0 : Enable or disable address matching on ADDRESS[0] */ -#define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */ -#define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */ -#define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */ -#define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */ - -/* Register: TWIS_ORC */ -/* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */ - -/* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */ -#define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ -#define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ - - -/* Peripheral: UART */ -/* Description: Universal Asynchronous Receiver/Transmitter */ - -/* Register: UART_SHORTS */ -/* Description: Shortcut register */ - -/* Bit 4 : Shortcut between NCTS event and STOPRX task */ -#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ -#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ -#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */ -#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 3 : Shortcut between CTS event and STARTRX task */ -#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ -#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ -#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */ -#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */ - -/* Register: UART_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 17 : Write '1' to Enable interrupt for RXTO event */ -#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ -#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ -#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ -#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ -#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */ - -/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ -#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ -#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ -#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ -#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */ - -/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */ -#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ -#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ -#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ -#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ -#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ - -/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */ -#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ -#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ -#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ -#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ -#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ - -/* Bit 1 : Write '1' to Enable interrupt for NCTS event */ -#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ -#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ -#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ -#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ -#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */ - -/* Bit 0 : Write '1' to Enable interrupt for CTS event */ -#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ -#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ -#define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ -#define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ -#define UART_INTENSET_CTS_Set (1UL) /*!< Enable */ - -/* Register: UART_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 17 : Write '1' to Disable interrupt for RXTO event */ -#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ -#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ -#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ -#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ -#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ - -/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ -#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ -#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ -#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ -#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ - -/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */ -#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ -#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ -#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ -#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ -#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ - -/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */ -#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ -#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ -#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ -#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ -#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ - -/* Bit 1 : Write '1' to Disable interrupt for NCTS event */ -#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ -#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ -#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ -#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ -#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ - -/* Bit 0 : Write '1' to Disable interrupt for CTS event */ -#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ -#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ -#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ -#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ -#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */ - -/* Register: UART_ERRORSRC */ -/* Description: Error source */ - -/* Bit 3 : Break condition */ -#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ -#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ -#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ -#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ - -/* Bit 2 : Framing error occurred */ -#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ -#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ -#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ -#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ - -/* Bit 1 : Parity error */ -#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ -#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ -#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ -#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ - -/* Bit 0 : Overrun error */ -#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ -#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ -#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ -#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ - -/* Register: UART_ENABLE */ -/* Description: Enable UART */ - -/* Bits 3..0 : Enable or disable UART */ -#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */ -#define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */ - -/* Register: UART_PSELRTS */ -/* Description: Pin select for RTS */ - -/* Bits 31..0 : Pin number configuration for UART RTS signal */ -#define UART_PSELRTS_PSELRTS_Pos (0UL) /*!< Position of PSELRTS field. */ -#define UART_PSELRTS_PSELRTS_Msk (0xFFFFFFFFUL << UART_PSELRTS_PSELRTS_Pos) /*!< Bit mask of PSELRTS field. */ -#define UART_PSELRTS_PSELRTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ - -/* Register: UART_PSELTXD */ -/* Description: Pin select for TXD */ - -/* Bits 31..0 : Pin number configuration for UART TXD signal */ -#define UART_PSELTXD_PSELTXD_Pos (0UL) /*!< Position of PSELTXD field. */ -#define UART_PSELTXD_PSELTXD_Msk (0xFFFFFFFFUL << UART_PSELTXD_PSELTXD_Pos) /*!< Bit mask of PSELTXD field. */ -#define UART_PSELTXD_PSELTXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ - -/* Register: UART_PSELCTS */ -/* Description: Pin select for CTS */ - -/* Bits 31..0 : Pin number configuration for UART CTS signal */ -#define UART_PSELCTS_PSELCTS_Pos (0UL) /*!< Position of PSELCTS field. */ -#define UART_PSELCTS_PSELCTS_Msk (0xFFFFFFFFUL << UART_PSELCTS_PSELCTS_Pos) /*!< Bit mask of PSELCTS field. */ -#define UART_PSELCTS_PSELCTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ - -/* Register: UART_PSELRXD */ -/* Description: Pin select for RXD */ - -/* Bits 31..0 : Pin number configuration for UART RXD signal */ -#define UART_PSELRXD_PSELRXD_Pos (0UL) /*!< Position of PSELRXD field. */ -#define UART_PSELRXD_PSELRXD_Msk (0xFFFFFFFFUL << UART_PSELRXD_PSELRXD_Pos) /*!< Bit mask of PSELRXD field. */ -#define UART_PSELRXD_PSELRXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ - -/* Register: UART_RXD */ -/* Description: RXD register */ - -/* Bits 7..0 : RX data received in previous transfers, double buffered */ -#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ -#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ - -/* Register: UART_TXD */ -/* Description: TXD register */ - -/* Bits 7..0 : TX data to be transferred */ -#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ -#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ - -/* Register: UART_BAUDRATE */ -/* Description: Baud rate */ - -/* Bits 31..0 : Baud rate */ -#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ -#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ -#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ -#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ -#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ -#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ -#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */ -#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ -#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */ -#define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ -#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */ -#define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ -#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */ -#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ -#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */ -#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */ -#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ -#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */ -#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */ -#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ - -/* Register: UART_CONFIG */ -/* Description: Configuration of parity and hardware flow control */ - -/* Bits 3..1 : Parity */ -#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ -#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ -#define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ -#define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */ - -/* Bit 0 : Hardware flow control */ -#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ -#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ -#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ -#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ - - -/* Peripheral: UARTE */ -/* Description: UART with EasyDMA */ - -/* Register: UARTE_SHORTS */ -/* Description: Shortcut register */ - -/* Bit 6 : Shortcut between ENDRX event and STOPRX task */ -#define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */ -#define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */ -#define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */ -#define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 5 : Shortcut between ENDRX event and STARTRX task */ -#define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */ -#define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */ -#define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ -#define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ - -/* Register: UARTE_INTEN */ -/* Description: Enable or disable interrupt */ - -/* Bit 22 : Enable or disable interrupt for TXSTOPPED event */ -#define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ -#define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ -#define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */ -#define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */ - -/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ -#define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ -#define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ -#define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ -#define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ - -/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ -#define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ -#define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ -#define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ -#define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ - -/* Bit 17 : Enable or disable interrupt for RXTO event */ -#define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */ -#define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */ -#define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */ -#define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */ - -/* Bit 9 : Enable or disable interrupt for ERROR event */ -#define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ -#define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */ -#define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */ - -/* Bit 8 : Enable or disable interrupt for ENDTX event */ -#define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ -#define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ -#define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ -#define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ - -/* Bit 7 : Enable or disable interrupt for TXDRDY event */ -#define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ -#define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ -#define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */ -#define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */ - -/* Bit 4 : Enable or disable interrupt for ENDRX event */ -#define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ -#define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ -#define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ -#define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ - -/* Bit 2 : Enable or disable interrupt for RXDRDY event */ -#define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ -#define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ -#define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */ -#define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */ - -/* Bit 1 : Enable or disable interrupt for NCTS event */ -#define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ -#define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ -#define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */ -#define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */ - -/* Bit 0 : Enable or disable interrupt for CTS event */ -#define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */ -#define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */ -#define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */ -#define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */ - -/* Register: UARTE_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 22 : Write '1' to Enable interrupt for TXSTOPPED event */ -#define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ -#define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ -#define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */ - -/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */ -#define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ -#define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ -#define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ - -/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */ -#define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ -#define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ -#define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ - -/* Bit 17 : Write '1' to Enable interrupt for RXTO event */ -#define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ -#define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ -#define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */ - -/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ -#define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ -#define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */ - -/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */ -#define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ -#define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ -#define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */ - -/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */ -#define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ -#define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ -#define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ - -/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ -#define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ -#define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ -#define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */ - -/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */ -#define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ -#define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ -#define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ - -/* Bit 1 : Write '1' to Enable interrupt for NCTS event */ -#define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ -#define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ -#define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */ - -/* Bit 0 : Write '1' to Enable interrupt for CTS event */ -#define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ -#define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ -#define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */ - -/* Register: UARTE_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 22 : Write '1' to Disable interrupt for TXSTOPPED event */ -#define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ -#define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ -#define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */ - -/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */ -#define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ -#define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ -#define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ - -/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */ -#define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ -#define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ -#define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ - -/* Bit 17 : Write '1' to Disable interrupt for RXTO event */ -#define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ -#define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ -#define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ - -/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ -#define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ -#define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ - -/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */ -#define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ -#define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ -#define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ - -/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */ -#define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ -#define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ -#define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ - -/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ -#define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ -#define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ -#define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ - -/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */ -#define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ -#define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ -#define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ - -/* Bit 1 : Write '1' to Disable interrupt for NCTS event */ -#define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ -#define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ -#define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ - -/* Bit 0 : Write '1' to Disable interrupt for CTS event */ -#define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ -#define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ -#define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */ - -/* Register: UARTE_ERRORSRC */ -/* Description: Error source */ - -/* Bit 3 : Break condition */ -#define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ -#define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ -#define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ -#define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ - -/* Bit 2 : Framing error occurred */ -#define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ -#define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ -#define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ -#define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ - -/* Bit 1 : Parity error */ -#define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ -#define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ -#define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ -#define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ - -/* Bit 0 : Overrun error */ -#define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ -#define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ -#define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ -#define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ - -/* Register: UARTE_ENABLE */ -/* Description: Enable UART */ - -/* Bits 3..0 : Enable or disable UARTE */ -#define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */ -#define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */ - -/* Register: UARTE_PSEL_RTS */ -/* Description: Pin select for RTS signal */ - -/* Bit 31 : Connection */ -#define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ -#define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bits 4..0 : Pin number */ -#define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ - -/* Register: UARTE_PSEL_TXD */ -/* Description: Pin select for TXD signal */ - -/* Bit 31 : Connection */ -#define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ -#define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bits 4..0 : Pin number */ -#define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ - -/* Register: UARTE_PSEL_CTS */ -/* Description: Pin select for CTS signal */ - -/* Bit 31 : Connection */ -#define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ -#define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bits 4..0 : Pin number */ -#define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ - -/* Register: UARTE_PSEL_RXD */ -/* Description: Pin select for RXD signal */ - -/* Bit 31 : Connection */ -#define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ -#define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bits 4..0 : Pin number */ -#define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ - -/* Register: UARTE_BAUDRATE */ -/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */ - -/* Bits 31..0 : Baud rate */ -#define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ -#define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ -#define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ -#define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ -#define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ -#define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ -#define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */ -#define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ -#define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */ -#define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ -#define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */ -#define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ -#define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */ -#define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ -#define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */ -#define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */ -#define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ -#define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ -#define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ -#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ - -/* Register: UARTE_RXD_PTR */ -/* Description: Data pointer */ - -/* Bits 31..0 : Data pointer */ -#define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ -#define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ - -/* Register: UARTE_RXD_MAXCNT */ -/* Description: Maximum number of bytes in receive buffer */ - -/* Bits 7..0 : Maximum number of bytes in receive buffer */ -#define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ -#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ - -/* Register: UARTE_RXD_AMOUNT */ -/* Description: Number of bytes transferred in the last transaction */ - -/* Bits 7..0 : Number of bytes transferred in the last transaction */ -#define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ -#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ - -/* Register: UARTE_TXD_PTR */ -/* Description: Data pointer */ - -/* Bits 31..0 : Data pointer */ -#define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ -#define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ - -/* Register: UARTE_TXD_MAXCNT */ -/* Description: Maximum number of bytes in transmit buffer */ - -/* Bits 7..0 : Maximum number of bytes in transmit buffer */ -#define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ -#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ - -/* Register: UARTE_TXD_AMOUNT */ -/* Description: Number of bytes transferred in the last transaction */ - -/* Bits 7..0 : Number of bytes transferred in the last transaction */ -#define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ -#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ - -/* Register: UARTE_CONFIG */ -/* Description: Configuration of parity and hardware flow control */ - -/* Bits 3..1 : Parity */ -#define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ -#define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ -#define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ -#define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */ - -/* Bit 0 : Hardware flow control */ -#define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ -#define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ -#define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ -#define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ - - -/* Peripheral: UICR */ -/* Description: User Information Configuration Registers */ - -/* Register: UICR_NRFFW */ -/* Description: Description collection[0]: Reserved for Nordic firmware design */ - -/* Bits 31..0 : Reserved for Nordic firmware design */ -#define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */ -#define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */ - -/* Register: UICR_NRFHW */ -/* Description: Description collection[0]: Reserved for Nordic hardware design */ - -/* Bits 31..0 : Reserved for Nordic hardware design */ -#define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */ -#define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */ - -/* Register: UICR_CUSTOMER */ -/* Description: Description collection[0]: Reserved for customer */ - -/* Bits 31..0 : Reserved for customer */ -#define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */ -#define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */ - -/* Register: UICR_PSELRESET */ -/* Description: Description collection[0]: Mapping of the nRESET function (see POWER chapter for details) */ - -/* Bit 31 : Connection */ -#define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */ -#define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bits 5..0 : GPIO number P0.n onto which Reset is exposed */ -#define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define UICR_PSELRESET_PIN_Msk (0x3FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ - -/* Register: UICR_APPROTECT */ -/* Description: Access Port protection */ - -/* Bits 7..0 : Enable or disable Access Port protection. Any other value than 0xFF being written to this field will enable protection. */ -#define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ -#define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ -#define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ -#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */ - -/* Register: UICR_NFCPINS */ -/* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */ - -/* Bit 0 : Setting of pins dedicated to NFC functionality */ -#define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */ -#define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */ -#define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */ -#define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */ - - -/* Peripheral: WDT */ -/* Description: Watchdog Timer */ - -/* Register: WDT_INTENSET */ -/* Description: Enable interrupt */ - -/* Bit 0 : Write '1' to Enable interrupt for TIMEOUT event */ -#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ -#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ -#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ -#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ -#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */ - -/* Register: WDT_INTENCLR */ -/* Description: Disable interrupt */ - -/* Bit 0 : Write '1' to Disable interrupt for TIMEOUT event */ -#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ -#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ -#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ -#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ -#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */ - -/* Register: WDT_RUNSTATUS */ -/* Description: Run status */ - -/* Bit 0 : Indicates whether or not the watchdog is running */ -#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */ -#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */ -#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */ -#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */ - -/* Register: WDT_REQSTATUS */ -/* Description: Request status */ - -/* Bit 7 : Request status for RR[7] register */ -#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ -#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ -#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */ -#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */ - -/* Bit 6 : Request status for RR[6] register */ -#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ -#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ -#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */ -#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */ - -/* Bit 5 : Request status for RR[5] register */ -#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ -#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ -#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */ -#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */ - -/* Bit 4 : Request status for RR[4] register */ -#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ -#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ -#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */ -#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */ - -/* Bit 3 : Request status for RR[3] register */ -#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ -#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ -#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */ -#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */ - -/* Bit 2 : Request status for RR[2] register */ -#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ -#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ -#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */ -#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */ - -/* Bit 1 : Request status for RR[1] register */ -#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ -#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ -#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */ -#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */ - -/* Bit 0 : Request status for RR[0] register */ -#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ -#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ -#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */ -#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */ - -/* Register: WDT_CRV */ -/* Description: Counter reload value */ - -/* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */ -#define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */ -#define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */ - -/* Register: WDT_RREN */ -/* Description: Enable register for reload request registers */ - -/* Bit 7 : Enable or disable RR[7] register */ -#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ -#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ -#define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */ -#define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */ - -/* Bit 6 : Enable or disable RR[6] register */ -#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ -#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ -#define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */ -#define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */ - -/* Bit 5 : Enable or disable RR[5] register */ -#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ -#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ -#define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */ -#define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */ - -/* Bit 4 : Enable or disable RR[4] register */ -#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ -#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ -#define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */ -#define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */ - -/* Bit 3 : Enable or disable RR[3] register */ -#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ -#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ -#define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */ -#define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */ - -/* Bit 2 : Enable or disable RR[2] register */ -#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ -#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ -#define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */ -#define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */ - -/* Bit 1 : Enable or disable RR[1] register */ -#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ -#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ -#define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */ -#define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */ - -/* Bit 0 : Enable or disable RR[0] register */ -#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ -#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ -#define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */ -#define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */ - -/* Register: WDT_CONFIG */ -/* Description: Configuration register */ - -/* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */ -#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ -#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ -#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */ -#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */ - -/* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */ -#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ -#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ -#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */ -#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */ - -/* Register: WDT_RR */ -/* Description: Description collection[0]: Reload request 0 */ - -/* Bits 31..0 : Reload request register */ -#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ -#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ -#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */ - - -/*lint --flb "Leave library region" */ -#endif diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52_common.ld b/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52_common.ld deleted file mode 100644 index 51f43d2b87..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52_common.ld +++ /dev/null @@ -1,170 +0,0 @@ -/* Deprecated linker script for Nordic Semiconductor nRF52 devices, - * please use nrfx_common.ld. This version exists for backwards - * compatibility. - * - * Version: Sourcery G++ 4.5-1 - * Support: https://support.codesourcery.com/GNUToolchain/ - * - * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc. - * - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - */ -OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapBase - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY): - { - __HeapBase = .; - __end__ = .; - PROVIDE(end = .); - KEEP(*(.heap*)) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - KEEP(*(.stack*)) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - /* Check if text sections + data exceeds FLASH limit */ - DataInitFlashUsed = __bss_start__ - __data_start__; - CodeFlashUsed = __etext - ORIGIN(FLASH); - TotalFlashUsed = CodeFlashUsed + DataInitFlashUsed; - ASSERT(TotalFlashUsed <= LENGTH(FLASH), "region FLASH overflowed with .data and user data") - -} diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52_name_change.h b/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52_name_change.h deleted file mode 100644 index 0d8620b58a..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52_name_change.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - -Copyright (c) 2010 - 2018, Nordic Semiconductor ASA - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - -2. Redistributions in binary form, except as embedded into a Nordic - Semiconductor ASA integrated circuit in a product or a software update for - such product, must reproduce the above copyright notice, this list of - conditions and the following disclaimer in the documentation and/or other - materials provided with the distribution. - -3. Neither the name of Nordic Semiconductor ASA nor the names of its - contributors may be used to endorse or promote products derived from this - software without specific prior written permission. - -4. This software, with or without modification, must only be used with a - Nordic Semiconductor ASA integrated circuit. - -5. Any software provided in binary form under this license must not be reverse - engineered, decompiled, modified and/or disassembled. - -THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS -OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*/ - -#ifndef NRF52_NAME_CHANGE_H -#define NRF52_NAME_CHANGE_H - -/*lint ++flb "Enter library region */ - -/* This file is given to prevent your SW from not compiling with the updates made to nrf52.h and - * nrf52_bitfields.h. The macros defined in this file were available previously. Do not use these - * macros on purpose. Use the ones defined in nrf52.h and nrf52_bitfields.h instead. - */ - -/* I2S */ -/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */ -#define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled -#define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled -#define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master -#define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave -#define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled -#define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled -#define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled -#define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled -#define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled -#define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled -#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit -#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit -#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit -#define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left -#define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right -#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned -#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo -#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left -#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right - -/* LPCOMP */ -/* Corrected typo in RESULT register. */ -#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below - -/*lint --flb "Leave library region" */ - -#endif /* NRF52_NAME_CHANGE_H */ - diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52_to_nrf52840.h b/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52_to_nrf52840.h deleted file mode 100644 index cee66a7ddf..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52_to_nrf52840.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - -Copyright (c) 2010 - 2018, Nordic Semiconductor ASA - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - -2. Redistributions in binary form, except as embedded into a Nordic - Semiconductor ASA integrated circuit in a product or a software update for - such product, must reproduce the above copyright notice, this list of - conditions and the following disclaimer in the documentation and/or other - materials provided with the distribution. - -3. Neither the name of Nordic Semiconductor ASA nor the names of its - contributors may be used to endorse or promote products derived from this - software without specific prior written permission. - -4. This software, with or without modification, must only be used with a - Nordic Semiconductor ASA integrated circuit. - -5. Any software provided in binary form under this license must not be reverse - engineered, decompiled, modified and/or disassembled. - -THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS -OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*/ - -#ifndef NRF52_TO_NRF52840_H -#define NRF52_TO_NRF52840_H - -/*lint ++flb "Enter library region */ - -/* This file is given to prevent your SW from not compiling with the name changes between nRF51 or nRF52832 and nRF52840 devices. - * It redefines the old nRF51 or nRF52832 names into the new ones as long as the functionality is still supported. If the - * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros - * from the nrf52_namechange.h file. */ - -/* Differences between latest nRF52 headers and nRF52840 headers. */ - -/* UART */ -/* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */ -#define PSELRTS PSEL.RTS -#define PSELTXD PSEL.TXD -#define PSELCTS PSEL.CTS -#define PSELRXD PSEL.RXD - -/* TWI */ -/* The registers PSELSCL, PSELSDA were restructured into a struct. */ -#define PSELSCL PSEL.SCL -#define PSELSDA PSEL.SDA - - -/* LPCOMP */ -/* The hysteresis control enumerated values has changed name for nRF52840 devices. */ -#define LPCOMP_HYST_HYST_NoHyst LPCOMP_HYST_HYST_Disabled -#define LPCOMP_HYST_HYST_Hyst50mV LPCOMP_HYST_HYST_Enabled - - -/* From nrf52_name_change.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */ - -/* I2S */ -/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */ -#define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled -#define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled -#define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master -#define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave -#define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled -#define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled -#define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled -#define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled -#define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled -#define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled -#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit -#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit -#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit -#define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left -#define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right -#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned -#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo -#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left -#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right - -/* LPCOMP */ -/* Corrected typo in RESULT register. */ -#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below - - -/*lint --flb "Leave library region" */ - -#endif /* NRF51_TO_NRF52840_H */ - diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52_xxaa.ld b/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52_xxaa.ld deleted file mode 100644 index 12b5d689b5..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52_xxaa.ld +++ /dev/null @@ -1,13 +0,0 @@ -/* Linker script to configure memory regions. */ - -SEARCH_DIR(.) -GROUP(-lgcc -lc -lnosys) - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x10000 -} - - -INCLUDE "nrf_common.ld" diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf_common.ld b/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf_common.ld deleted file mode 100644 index df9f69dc93..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf_common.ld +++ /dev/null @@ -1,168 +0,0 @@ -/* Linker script for Nordic Semiconductor nRF devices - * - * Version: Sourcery G++ 4.5-1 - * Support: https://support.codesourcery.com/GNUToolchain/ - * - * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc. - * - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - */ -OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapBase - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY): - { - __HeapBase = .; - __end__ = .; - PROVIDE(end = .); - KEEP(*(.heap*)) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - KEEP(*(.stack*)) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - /* Check if text sections + data exceeds FLASH limit */ - DataInitFlashUsed = __bss_start__ - __data_start__; - CodeFlashUsed = __etext - ORIGIN(FLASH); - TotalFlashUsed = CodeFlashUsed + DataInitFlashUsed; - ASSERT(TotalFlashUsed <= LENGTH(FLASH), "region FLASH overflowed with .data and user data") - -} diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/ses_nRF_Startup.s b/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/ses_nRF_Startup.s deleted file mode 100644 index b658a5cd33..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/ses_nRF_Startup.s +++ /dev/null @@ -1,148 +0,0 @@ -/***************************************************************************** - * SEGGER Microcontroller GmbH & Co. KG * - * Solutions for real time microcontroller applications * - ***************************************************************************** - * * - * (c) 2017 SEGGER Microcontroller GmbH & Co. KG * - * * - * Internet: www.segger.com Support: support@segger.com * - * * - *****************************************************************************/ - -/***************************************************************************** - * Preprocessor Definitions * - * ------------------------ * - * NO_FPU_ENABLE * - * * - * If defined, FPU will not be enabled. * - * * - * NO_STACK_INIT * - * * - * If defined, the stack pointer will not be initialised. * - * * - * NO_SYSTEM_INIT * - * * - * If defined, the SystemInit() function will not be called. By default * - * SystemInit() is called after reset to enable the clocks and memories to * - * be initialised prior to any C startup initialisation. * - * * - * NO_VTOR_CONFIG * - * * - * If defined, the vector table offset register will not be configured. * - * * - * MEMORY_INIT * - * * - * If defined, the MemoryInit() function will be called. By default * - * MemoryInit() is called after SystemInit() to enable an external memory * - * controller. * - * * - * STACK_INIT_VAL * - * * - * If defined, specifies the initial stack pointer value. If undefined, * - * the stack pointer will be initialised to point to the end of the * - * RAM segment. * - * * - * VECTORS_IN_RAM * - * * - * If defined, the exception vectors will be copied from Flash to RAM. * - * * - *****************************************************************************/ - - .syntax unified - - .global Reset_Handler -#ifdef INITIALIZE_USER_SECTIONS - .global InitializeUserMemorySections -#endif - .extern _vectors - - .section .init, "ax" - .thumb_func - - .equ VTOR_REG, 0xE000ED08 - .equ FPU_CPACR_REG, 0xE000ED88 - -#ifndef STACK_INIT_VAL -#define STACK_INIT_VAL __RAM_segment_end__ -#endif - -Reset_Handler: -#ifndef NO_STACK_INIT - /* Initialise main stack */ - ldr r0, =STACK_INIT_VAL - ldr r1, =0x7 - bics r0, r1 - mov sp, r0 -#endif - -#ifndef NO_SYSTEM_INIT - /* Initialise system */ - ldr r0, =SystemInit - blx r0 -#endif - -#ifdef MEMORY_INIT - ldr r0, =MemoryInit - blx r0 -#endif - -#ifdef VECTORS_IN_RAM - /* Copy exception vectors into RAM */ - ldr r0, =__vectors_start__ - ldr r1, =__vectors_end__ - ldr r2, =__vectors_ram_start__ -1: - cmp r0, r1 - beq 2f - ldr r3, [r0] - str r3, [r2] - adds r0, r0, #4 - adds r2, r2, #4 - b 1b -2: -#endif - -#ifndef NO_VTOR_CONFIG - /* Configure vector table offset register */ - ldr r0, =VTOR_REG -#ifdef VECTORS_IN_RAM - ldr r1, =_vectors_ram -#else - ldr r1, =_vectors -#endif - str r1, [r0] -#endif - -#if (defined(__ARM_ARCH_FPV4_SP_D16__) || defined(__ARM_ARCH_FPV5_D16__)) && !defined(NO_FPU_ENABLE) - /* Enable FPU */ - ldr r0, =FPU_CPACR_REG - ldr r1, [r0] - orr r1, r1, #(0xF << 20) - str r1, [r0] - dsb - isb -#endif - - /* Jump to program start */ - b _start - -#ifdef INITIALIZE_USER_SECTIONS - .thumb_func -InitializeUserMemorySections: - ldr r0, =__start_nrf_sections - ldr r1, =__start_nrf_sections_run - ldr r2, =__end_nrf_sections_run - cmp r0, r1 - beq 2f - subs r2, r2, r1 - beq 2f -1: - ldrb r3, [r0] - adds r0, r0, #1 - strb r3, [r1] - adds r1, r1, #1 - subs r2, r2, #1 - bne 1b -2: - bx lr -#endif \ No newline at end of file diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/ses_nrf52840_Vectors.s b/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/ses_nrf52840_Vectors.s deleted file mode 100644 index 284bc98db2..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/ses_nrf52840_Vectors.s +++ /dev/null @@ -1,515 +0,0 @@ -/***************************************************************************** - * SEGGER Microcontroller GmbH & Co. KG * - * Solutions for real time microcontroller applications * - ***************************************************************************** - * * - * (c) 2017 SEGGER Microcontroller GmbH & Co. KG * - * * - * Internet: www.segger.com Support: support@segger.com * - * * - *****************************************************************************/ - -/***************************************************************************** - * Preprocessor Definitions * - * ------------------------ * - * VECTORS_IN_RAM * - * * - * If defined, an area of RAM will large enough to store the vector table * - * will be reserved. * - * * - *****************************************************************************/ - - .syntax unified - .code 16 - - .section .init, "ax" - .align 0 - -/***************************************************************************** - * Default Exception Handlers * - *****************************************************************************/ - - .thumb_func - .weak NMI_Handler -NMI_Handler: - b . - - .thumb_func - .weak HardFault_Handler -HardFault_Handler: - b . - - .thumb_func - .weak MemoryManagement_Handler -MemoryManagement_Handler: - b . - - .thumb_func - .weak BusFault_Handler -BusFault_Handler: - b . - - .thumb_func - .weak UsageFault_Handler -UsageFault_Handler: - b . - - .thumb_func - .weak SVC_Handler -SVC_Handler: - b . - - .thumb_func - .weak DebugMon_Handler -DebugMon_Handler: - b . - - .thumb_func - .weak PendSV_Handler -PendSV_Handler: - b . - - .thumb_func - .weak SysTick_Handler -SysTick_Handler: - b . - - .thumb_func -Dummy_Handler: - b . - -#if defined(__OPTIMIZATION_SMALL) - - .weak POWER_CLOCK_IRQHandler - .thumb_set POWER_CLOCK_IRQHandler,Dummy_Handler - - .weak RADIO_IRQHandler - .thumb_set RADIO_IRQHandler,Dummy_Handler - - .weak UARTE0_UART0_IRQHandler - .thumb_set UARTE0_UART0_IRQHandler,Dummy_Handler - - .weak SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler - .thumb_set SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler,Dummy_Handler - - .weak SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler - .thumb_set SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler,Dummy_Handler - - .weak NFCT_IRQHandler - .thumb_set NFCT_IRQHandler,Dummy_Handler - - .weak GPIOTE_IRQHandler - .thumb_set GPIOTE_IRQHandler,Dummy_Handler - - .weak SAADC_IRQHandler - .thumb_set SAADC_IRQHandler,Dummy_Handler - - .weak TIMER0_IRQHandler - .thumb_set TIMER0_IRQHandler,Dummy_Handler - - .weak TIMER1_IRQHandler - .thumb_set TIMER1_IRQHandler,Dummy_Handler - - .weak TIMER2_IRQHandler - .thumb_set TIMER2_IRQHandler,Dummy_Handler - - .weak RTC0_IRQHandler - .thumb_set RTC0_IRQHandler,Dummy_Handler - - .weak TEMP_IRQHandler - .thumb_set TEMP_IRQHandler,Dummy_Handler - - .weak RNG_IRQHandler - .thumb_set RNG_IRQHandler,Dummy_Handler - - .weak ECB_IRQHandler - .thumb_set ECB_IRQHandler,Dummy_Handler - - .weak CCM_AAR_IRQHandler - .thumb_set CCM_AAR_IRQHandler,Dummy_Handler - - .weak WDT_IRQHandler - .thumb_set WDT_IRQHandler,Dummy_Handler - - .weak RTC1_IRQHandler - .thumb_set RTC1_IRQHandler,Dummy_Handler - - .weak QDEC_IRQHandler - .thumb_set QDEC_IRQHandler,Dummy_Handler - - .weak COMP_LPCOMP_IRQHandler - .thumb_set COMP_LPCOMP_IRQHandler,Dummy_Handler - - .weak SWI0_EGU0_IRQHandler - .thumb_set SWI0_EGU0_IRQHandler,Dummy_Handler - - .weak SWI1_EGU1_IRQHandler - .thumb_set SWI1_EGU1_IRQHandler,Dummy_Handler - - .weak SWI2_EGU2_IRQHandler - .thumb_set SWI2_EGU2_IRQHandler,Dummy_Handler - - .weak SWI3_EGU3_IRQHandler - .thumb_set SWI3_EGU3_IRQHandler,Dummy_Handler - - .weak SWI4_EGU4_IRQHandler - .thumb_set SWI4_EGU4_IRQHandler,Dummy_Handler - - .weak SWI5_EGU5_IRQHandler - .thumb_set SWI5_EGU5_IRQHandler,Dummy_Handler - - .weak TIMER3_IRQHandler - .thumb_set TIMER3_IRQHandler,Dummy_Handler - - .weak TIMER4_IRQHandler - .thumb_set TIMER4_IRQHandler,Dummy_Handler - - .weak PWM0_IRQHandler - .thumb_set PWM0_IRQHandler,Dummy_Handler - - .weak PDM_IRQHandler - .thumb_set PDM_IRQHandler,Dummy_Handler - - .weak MWU_IRQHandler - .thumb_set MWU_IRQHandler,Dummy_Handler - - .weak PWM1_IRQHandler - .thumb_set PWM1_IRQHandler,Dummy_Handler - - .weak PWM2_IRQHandler - .thumb_set PWM2_IRQHandler,Dummy_Handler - - .weak SPIM2_SPIS2_SPI2_IRQHandler - .thumb_set SPIM2_SPIS2_SPI2_IRQHandler,Dummy_Handler - - .weak RTC2_IRQHandler - .thumb_set RTC2_IRQHandler,Dummy_Handler - - .weak I2S_IRQHandler - .thumb_set I2S_IRQHandler,Dummy_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Dummy_Handler - - .weak USBD_IRQHandler - .thumb_set USBD_IRQHandler,Dummy_Handler - - .weak UARTE1_IRQHandler - .thumb_set UARTE1_IRQHandler,Dummy_Handler - - .weak QSPI_IRQHandler - .thumb_set QSPI_IRQHandler,Dummy_Handler - - .weak CRYPTOCELL_IRQHandler - .thumb_set CRYPTOCELL_IRQHandler,Dummy_Handler - - .weak SPIM3_IRQHandler - .thumb_set SPIM3_IRQHandler,Dummy_Handler - - .weak PWM3_IRQHandler - .thumb_set PWM3_IRQHandler,Dummy_Handler - -#else - - .thumb_func - .weak POWER_CLOCK_IRQHandler -POWER_CLOCK_IRQHandler: - b . - - .thumb_func - .weak RADIO_IRQHandler -RADIO_IRQHandler: - b . - - .thumb_func - .weak UARTE0_UART0_IRQHandler -UARTE0_UART0_IRQHandler: - b . - - .thumb_func - .weak SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler -SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler: - b . - - .thumb_func - .weak SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler -SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler: - b . - - .thumb_func - .weak NFCT_IRQHandler -NFCT_IRQHandler: - b . - - .thumb_func - .weak GPIOTE_IRQHandler -GPIOTE_IRQHandler: - b . - - .thumb_func - .weak SAADC_IRQHandler -SAADC_IRQHandler: - b . - - .thumb_func - .weak TIMER0_IRQHandler -TIMER0_IRQHandler: - b . - - .thumb_func - .weak TIMER1_IRQHandler -TIMER1_IRQHandler: - b . - - .thumb_func - .weak TIMER2_IRQHandler -TIMER2_IRQHandler: - b . - - .thumb_func - .weak RTC0_IRQHandler -RTC0_IRQHandler: - b . - - .thumb_func - .weak TEMP_IRQHandler -TEMP_IRQHandler: - b . - - .thumb_func - .weak RNG_IRQHandler -RNG_IRQHandler: - b . - - .thumb_func - .weak ECB_IRQHandler -ECB_IRQHandler: - b . - - .thumb_func - .weak CCM_AAR_IRQHandler -CCM_AAR_IRQHandler: - b . - - .thumb_func - .weak WDT_IRQHandler -WDT_IRQHandler: - b . - - .thumb_func - .weak RTC1_IRQHandler -RTC1_IRQHandler: - b . - - .thumb_func - .weak QDEC_IRQHandler -QDEC_IRQHandler: - b . - - .thumb_func - .weak COMP_LPCOMP_IRQHandler -COMP_LPCOMP_IRQHandler: - b . - - .thumb_func - .weak SWI0_EGU0_IRQHandler -SWI0_EGU0_IRQHandler: - b . - - .thumb_func - .weak SWI1_EGU1_IRQHandler -SWI1_EGU1_IRQHandler: - b . - - .thumb_func - .weak SWI2_EGU2_IRQHandler -SWI2_EGU2_IRQHandler: - b . - - .thumb_func - .weak SWI3_EGU3_IRQHandler -SWI3_EGU3_IRQHandler: - b . - - .thumb_func - .weak SWI4_EGU4_IRQHandler -SWI4_EGU4_IRQHandler: - b . - - .thumb_func - .weak SWI5_EGU5_IRQHandler -SWI5_EGU5_IRQHandler: - b . - - .thumb_func - .weak TIMER3_IRQHandler -TIMER3_IRQHandler: - b . - - .thumb_func - .weak TIMER4_IRQHandler -TIMER4_IRQHandler: - b . - - .thumb_func - .weak PWM0_IRQHandler -PWM0_IRQHandler: - b . - - .thumb_func - .weak PDM_IRQHandler -PDM_IRQHandler: - b . - - .thumb_func - .weak MWU_IRQHandler -MWU_IRQHandler: - b . - - .thumb_func - .weak PWM1_IRQHandler -PWM1_IRQHandler: - b . - - .thumb_func - .weak PWM2_IRQHandler -PWM2_IRQHandler: - b . - - .thumb_func - .weak SPIM2_SPIS2_SPI2_IRQHandler -SPIM2_SPIS2_SPI2_IRQHandler: - b . - - .thumb_func - .weak RTC2_IRQHandler -RTC2_IRQHandler: - b . - - .thumb_func - .weak I2S_IRQHandler -I2S_IRQHandler: - b . - - .thumb_func - .weak FPU_IRQHandler -FPU_IRQHandler: - b . - - .thumb_func - .weak USBD_IRQHandler -USBD_IRQHandler: - b . - - .thumb_func - .weak UARTE1_IRQHandler -UARTE1_IRQHandler: - b . - - .thumb_func - .weak QSPI_IRQHandler -QSPI_IRQHandler: - b . - - .thumb_func - .weak CRYPTOCELL_IRQHandler -CRYPTOCELL_IRQHandler: - b . - - .thumb_func - .weak SPIM3_IRQHandler -SPIM3_IRQHandler: - b . - - .thumb_func - .weak PWM3_IRQHandler -PWM3_IRQHandler: - b . - -#endif - -/***************************************************************************** - * Vector Table * - *****************************************************************************/ - - .section .vectors, "ax" - .align 0 - .global _vectors - .extern __stack_end__ - .extern Reset_Handler - -_vectors: - .word __stack_end__ - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemoryManagement_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word SVC_Handler - .word DebugMon_Handler - .word 0 /* Reserved */ - .word PendSV_Handler - .word SysTick_Handler - .word POWER_CLOCK_IRQHandler - .word RADIO_IRQHandler - .word UARTE0_UART0_IRQHandler - .word SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler - .word SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler - .word NFCT_IRQHandler - .word GPIOTE_IRQHandler - .word SAADC_IRQHandler - .word TIMER0_IRQHandler - .word TIMER1_IRQHandler - .word TIMER2_IRQHandler - .word RTC0_IRQHandler - .word TEMP_IRQHandler - .word RNG_IRQHandler - .word ECB_IRQHandler - .word CCM_AAR_IRQHandler - .word WDT_IRQHandler - .word RTC1_IRQHandler - .word QDEC_IRQHandler - .word COMP_LPCOMP_IRQHandler - .word SWI0_EGU0_IRQHandler - .word SWI1_EGU1_IRQHandler - .word SWI2_EGU2_IRQHandler - .word SWI3_EGU3_IRQHandler - .word SWI4_EGU4_IRQHandler - .word SWI5_EGU5_IRQHandler - .word TIMER3_IRQHandler - .word TIMER4_IRQHandler - .word PWM0_IRQHandler - .word PDM_IRQHandler - .word Dummy_Handler /* Reserved */ - .word Dummy_Handler /* Reserved */ - .word MWU_IRQHandler - .word PWM1_IRQHandler - .word PWM2_IRQHandler - .word SPIM2_SPIS2_SPI2_IRQHandler - .word RTC2_IRQHandler - .word I2S_IRQHandler - .word FPU_IRQHandler - .word USBD_IRQHandler - .word UARTE1_IRQHandler - .word QSPI_IRQHandler - .word CRYPTOCELL_IRQHandler - .word Dummy_Handler /* Reserved */ - .word Dummy_Handler /* Reserved */ - .word PWM3_IRQHandler - .word Dummy_Handler /* Reserved */ - .word SPIM3_IRQHandler -_vectors_end: - -#ifdef VECTORS_IN_RAM - .section .vectors_ram, "ax" - .align 0 - .global _vectors_ram - -_vectors_ram: - .space _vectors_end - _vectors, 0 -#endif diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/ses_nrf52_Vectors.s b/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/ses_nrf52_Vectors.s deleted file mode 100644 index 7dfa61f607..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/ses_nrf52_Vectors.s +++ /dev/null @@ -1,458 +0,0 @@ -/***************************************************************************** - * SEGGER Microcontroller GmbH & Co. KG * - * Solutions for real time microcontroller applications * - ***************************************************************************** - * * - * (c) 2017 SEGGER Microcontroller GmbH & Co. KG * - * * - * Internet: www.segger.com Support: support@segger.com * - * * - *****************************************************************************/ - -/***************************************************************************** - * Preprocessor Definitions * - * ------------------------ * - * VECTORS_IN_RAM * - * * - * If defined, an area of RAM will large enough to store the vector table * - * will be reserved. * - * * - *****************************************************************************/ - - .syntax unified - .code 16 - - .section .init, "ax" - .align 0 - -/***************************************************************************** - * Default Exception Handlers * - *****************************************************************************/ - - .thumb_func - .weak NMI_Handler -NMI_Handler: - b . - - .thumb_func - .weak HardFault_Handler -HardFault_Handler: - b . - - .thumb_func - .weak MemoryManagement_Handler -MemoryManagement_Handler: - b . - - .thumb_func - .weak BusFault_Handler -BusFault_Handler: - b . - - .thumb_func - .weak UsageFault_Handler -UsageFault_Handler: - b . - - .thumb_func - .weak SVC_Handler -SVC_Handler: - b . - - .thumb_func - .weak DebugMon_Handler -DebugMon_Handler: - b . - - .thumb_func - .weak PendSV_Handler -PendSV_Handler: - b . - - .thumb_func - .weak SysTick_Handler -SysTick_Handler: - b . - - .thumb_func -Dummy_Handler: - b . - -#if defined(__OPTIMIZATION_SMALL) - - .weak POWER_CLOCK_IRQHandler - .thumb_set POWER_CLOCK_IRQHandler,Dummy_Handler - - .weak RADIO_IRQHandler - .thumb_set RADIO_IRQHandler,Dummy_Handler - - .weak UARTE0_UART0_IRQHandler - .thumb_set UARTE0_UART0_IRQHandler,Dummy_Handler - - .weak SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler - .thumb_set SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler,Dummy_Handler - - .weak SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler - .thumb_set SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler,Dummy_Handler - - .weak NFCT_IRQHandler - .thumb_set NFCT_IRQHandler,Dummy_Handler - - .weak GPIOTE_IRQHandler - .thumb_set GPIOTE_IRQHandler,Dummy_Handler - - .weak SAADC_IRQHandler - .thumb_set SAADC_IRQHandler,Dummy_Handler - - .weak TIMER0_IRQHandler - .thumb_set TIMER0_IRQHandler,Dummy_Handler - - .weak TIMER1_IRQHandler - .thumb_set TIMER1_IRQHandler,Dummy_Handler - - .weak TIMER2_IRQHandler - .thumb_set TIMER2_IRQHandler,Dummy_Handler - - .weak RTC0_IRQHandler - .thumb_set RTC0_IRQHandler,Dummy_Handler - - .weak TEMP_IRQHandler - .thumb_set TEMP_IRQHandler,Dummy_Handler - - .weak RNG_IRQHandler - .thumb_set RNG_IRQHandler,Dummy_Handler - - .weak ECB_IRQHandler - .thumb_set ECB_IRQHandler,Dummy_Handler - - .weak CCM_AAR_IRQHandler - .thumb_set CCM_AAR_IRQHandler,Dummy_Handler - - .weak WDT_IRQHandler - .thumb_set WDT_IRQHandler,Dummy_Handler - - .weak RTC1_IRQHandler - .thumb_set RTC1_IRQHandler,Dummy_Handler - - .weak QDEC_IRQHandler - .thumb_set QDEC_IRQHandler,Dummy_Handler - - .weak COMP_LPCOMP_IRQHandler - .thumb_set COMP_LPCOMP_IRQHandler,Dummy_Handler - - .weak SWI0_EGU0_IRQHandler - .thumb_set SWI0_EGU0_IRQHandler,Dummy_Handler - - .weak SWI1_EGU1_IRQHandler - .thumb_set SWI1_EGU1_IRQHandler,Dummy_Handler - - .weak SWI2_EGU2_IRQHandler - .thumb_set SWI2_EGU2_IRQHandler,Dummy_Handler - - .weak SWI3_EGU3_IRQHandler - .thumb_set SWI3_EGU3_IRQHandler,Dummy_Handler - - .weak SWI4_EGU4_IRQHandler - .thumb_set SWI4_EGU4_IRQHandler,Dummy_Handler - - .weak SWI5_EGU5_IRQHandler - .thumb_set SWI5_EGU5_IRQHandler,Dummy_Handler - - .weak TIMER3_IRQHandler - .thumb_set TIMER3_IRQHandler,Dummy_Handler - - .weak TIMER4_IRQHandler - .thumb_set TIMER4_IRQHandler,Dummy_Handler - - .weak PWM0_IRQHandler - .thumb_set PWM0_IRQHandler,Dummy_Handler - - .weak PDM_IRQHandler - .thumb_set PDM_IRQHandler,Dummy_Handler - - .weak MWU_IRQHandler - .thumb_set MWU_IRQHandler,Dummy_Handler - - .weak PWM1_IRQHandler - .thumb_set PWM1_IRQHandler,Dummy_Handler - - .weak PWM2_IRQHandler - .thumb_set PWM2_IRQHandler,Dummy_Handler - - .weak SPIM2_SPIS2_SPI2_IRQHandler - .thumb_set SPIM2_SPIS2_SPI2_IRQHandler,Dummy_Handler - - .weak RTC2_IRQHandler - .thumb_set RTC2_IRQHandler,Dummy_Handler - - .weak I2S_IRQHandler - .thumb_set I2S_IRQHandler,Dummy_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Dummy_Handler - -#else - - .thumb_func - .weak POWER_CLOCK_IRQHandler -POWER_CLOCK_IRQHandler: - b . - - .thumb_func - .weak RADIO_IRQHandler -RADIO_IRQHandler: - b . - - .thumb_func - .weak UARTE0_UART0_IRQHandler -UARTE0_UART0_IRQHandler: - b . - - .thumb_func - .weak SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler -SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler: - b . - - .thumb_func - .weak SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler -SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler: - b . - - .thumb_func - .weak NFCT_IRQHandler -NFCT_IRQHandler: - b . - - .thumb_func - .weak GPIOTE_IRQHandler -GPIOTE_IRQHandler: - b . - - .thumb_func - .weak SAADC_IRQHandler -SAADC_IRQHandler: - b . - - .thumb_func - .weak TIMER0_IRQHandler -TIMER0_IRQHandler: - b . - - .thumb_func - .weak TIMER1_IRQHandler -TIMER1_IRQHandler: - b . - - .thumb_func - .weak TIMER2_IRQHandler -TIMER2_IRQHandler: - b . - - .thumb_func - .weak RTC0_IRQHandler -RTC0_IRQHandler: - b . - - .thumb_func - .weak TEMP_IRQHandler -TEMP_IRQHandler: - b . - - .thumb_func - .weak RNG_IRQHandler -RNG_IRQHandler: - b . - - .thumb_func - .weak ECB_IRQHandler -ECB_IRQHandler: - b . - - .thumb_func - .weak CCM_AAR_IRQHandler -CCM_AAR_IRQHandler: - b . - - .thumb_func - .weak WDT_IRQHandler -WDT_IRQHandler: - b . - - .thumb_func - .weak RTC1_IRQHandler -RTC1_IRQHandler: - b . - - .thumb_func - .weak QDEC_IRQHandler -QDEC_IRQHandler: - b . - - .thumb_func - .weak COMP_LPCOMP_IRQHandler -COMP_LPCOMP_IRQHandler: - b . - - .thumb_func - .weak SWI0_EGU0_IRQHandler -SWI0_EGU0_IRQHandler: - b . - - .thumb_func - .weak SWI1_EGU1_IRQHandler -SWI1_EGU1_IRQHandler: - b . - - .thumb_func - .weak SWI2_EGU2_IRQHandler -SWI2_EGU2_IRQHandler: - b . - - .thumb_func - .weak SWI3_EGU3_IRQHandler -SWI3_EGU3_IRQHandler: - b . - - .thumb_func - .weak SWI4_EGU4_IRQHandler -SWI4_EGU4_IRQHandler: - b . - - .thumb_func - .weak SWI5_EGU5_IRQHandler -SWI5_EGU5_IRQHandler: - b . - - .thumb_func - .weak TIMER3_IRQHandler -TIMER3_IRQHandler: - b . - - .thumb_func - .weak TIMER4_IRQHandler -TIMER4_IRQHandler: - b . - - .thumb_func - .weak PWM0_IRQHandler -PWM0_IRQHandler: - b . - - .thumb_func - .weak PDM_IRQHandler -PDM_IRQHandler: - b . - - .thumb_func - .weak MWU_IRQHandler -MWU_IRQHandler: - b . - - .thumb_func - .weak PWM1_IRQHandler -PWM1_IRQHandler: - b . - - .thumb_func - .weak PWM2_IRQHandler -PWM2_IRQHandler: - b . - - .thumb_func - .weak SPIM2_SPIS2_SPI2_IRQHandler -SPIM2_SPIS2_SPI2_IRQHandler: - b . - - .thumb_func - .weak RTC2_IRQHandler -RTC2_IRQHandler: - b . - - .thumb_func - .weak I2S_IRQHandler -I2S_IRQHandler: - b . - - .thumb_func - .weak FPU_IRQHandler -FPU_IRQHandler: - b . - -#endif - -/***************************************************************************** - * Vector Table * - *****************************************************************************/ - - .section .vectors, "ax" - .align 0 - .global _vectors - .extern __stack_end__ - .extern Reset_Handler - -_vectors: - .word __stack_end__ - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemoryManagement_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word SVC_Handler - .word DebugMon_Handler - .word 0 /* Reserved */ - .word PendSV_Handler - .word SysTick_Handler - .word POWER_CLOCK_IRQHandler - .word RADIO_IRQHandler - .word UARTE0_UART0_IRQHandler - .word SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler - .word SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler - .word NFCT_IRQHandler - .word GPIOTE_IRQHandler - .word SAADC_IRQHandler - .word TIMER0_IRQHandler - .word TIMER1_IRQHandler - .word TIMER2_IRQHandler - .word RTC0_IRQHandler - .word TEMP_IRQHandler - .word RNG_IRQHandler - .word ECB_IRQHandler - .word CCM_AAR_IRQHandler - .word WDT_IRQHandler - .word RTC1_IRQHandler - .word QDEC_IRQHandler - .word COMP_LPCOMP_IRQHandler - .word SWI0_EGU0_IRQHandler - .word SWI1_EGU1_IRQHandler - .word SWI2_EGU2_IRQHandler - .word SWI3_EGU3_IRQHandler - .word SWI4_EGU4_IRQHandler - .word SWI5_EGU5_IRQHandler - .word TIMER3_IRQHandler - .word TIMER4_IRQHandler - .word PWM0_IRQHandler - .word PDM_IRQHandler - .word Dummy_Handler /* Reserved */ - .word Dummy_Handler /* Reserved */ - .word MWU_IRQHandler - .word PWM1_IRQHandler - .word PWM2_IRQHandler - .word SPIM2_SPIS2_SPI2_IRQHandler - .word RTC2_IRQHandler - .word I2S_IRQHandler - .word FPU_IRQHandler -_vectors_end: - -#ifdef VECTORS_IN_RAM - .section .vectors_ram, "ax" - .align 0 - .global _vectors_ram - -_vectors_ram: - .space _vectors_end - _vectors, 0 -#endif diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/system_nrf51.h b/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/system_nrf51.h deleted file mode 100644 index b00c92ef21..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/system_nrf51.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - -Copyright (c) 2009-2018 ARM Limited. All rights reserved. - - SPDX-License-Identifier: Apache-2.0 - -Licensed under the Apache License, Version 2.0 (the License); you may -not use this file except in compliance with the License. -You may obtain a copy of the License at - - www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an AS IS BASIS, WITHOUT -WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -NOTICE: This file has been modified by Nordic Semiconductor ASA. - -*/ - -#ifndef SYSTEM_NRF51_H -#define SYSTEM_NRF51_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_NRF51_H */ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/system_nrf52.c b/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/system_nrf52.c deleted file mode 100644 index cf394bb598..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/system_nrf52.c +++ /dev/null @@ -1,373 +0,0 @@ -/* - -Copyright (c) 2009-2018 ARM Limited. All rights reserved. - - SPDX-License-Identifier: Apache-2.0 - -Licensed under the Apache License, Version 2.0 (the License); you may -not use this file except in compliance with the License. -You may obtain a copy of the License at - - www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an AS IS BASIS, WITHOUT -WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -NOTICE: This file has been modified by Nordic Semiconductor ASA. - -*/ - -/* NOTE: Template files (including this one) are application specific and therefore expected to - be copied into the application project folder prior to its use! */ - -#include -#include -#include "nrf.h" -#include "system_nrf52.h" - -/*lint ++flb "Enter library region" */ - -#define __SYSTEM_CLOCK_64M (64000000UL) - -static bool errata_12(void); -static bool errata_16(void); -static bool errata_31(void); -static bool errata_32(void); -static bool errata_36(void); -static bool errata_37(void); -static bool errata_57(void); -static bool errata_66(void); -static bool errata_108(void); -static bool errata_136(void); -static bool errata_182(void); - - -#if defined ( __CC_ARM ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; -#elif defined ( __ICCARM__ ) - __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M; -#elif defined ( __GNUC__ ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; -#endif - -void SystemCoreClockUpdate(void) -{ - SystemCoreClock = __SYSTEM_CLOCK_64M; -} - -void SystemInit(void) -{ - /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product - Specification to see which one). */ - #if defined (ENABLE_SWO) - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos; - NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - #endif - - /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product - Specification to see which ones). */ - #if defined (ENABLE_TRACE) - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos; - NRF_P0->PIN_CNF[14] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - NRF_P0->PIN_CNF[15] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - NRF_P0->PIN_CNF[16] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - #endif - - /* Workaround for Errata 12 "COMP: Reference ladder not correctly calibrated" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ - if (errata_12()){ - *(volatile uint32_t *)0x40013540 = (*(uint32_t *)0x10000324 & 0x00001F00) >> 8; - } - - /* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ - if (errata_16()){ - *(volatile uint32_t *)0x4007C074 = 3131961357ul; - } - - /* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ - if (errata_31()){ - *(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13; - } - - /* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ - if (errata_32()){ - CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; - } - - /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ - if (errata_36()){ - NRF_CLOCK->EVENTS_DONE = 0; - NRF_CLOCK->EVENTS_CTTO = 0; - NRF_CLOCK->CTIV = 0; - } - - /* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ - if (errata_37()){ - *(volatile uint32_t *)0x400005A0 = 0x3; - } - - /* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ - if (errata_57()){ - *(volatile uint32_t *)0x40005610 = 0x00000005; - *(volatile uint32_t *)0x40005688 = 0x00000001; - *(volatile uint32_t *)0x40005618 = 0x00000000; - *(volatile uint32_t *)0x40005614 = 0x0000003F; - } - - /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ - if (errata_66()){ - NRF_TEMP->A0 = NRF_FICR->TEMP.A0; - NRF_TEMP->A1 = NRF_FICR->TEMP.A1; - NRF_TEMP->A2 = NRF_FICR->TEMP.A2; - NRF_TEMP->A3 = NRF_FICR->TEMP.A3; - NRF_TEMP->A4 = NRF_FICR->TEMP.A4; - NRF_TEMP->A5 = NRF_FICR->TEMP.A5; - NRF_TEMP->B0 = NRF_FICR->TEMP.B0; - NRF_TEMP->B1 = NRF_FICR->TEMP.B1; - NRF_TEMP->B2 = NRF_FICR->TEMP.B2; - NRF_TEMP->B3 = NRF_FICR->TEMP.B3; - NRF_TEMP->B4 = NRF_FICR->TEMP.B4; - NRF_TEMP->B5 = NRF_FICR->TEMP.B5; - NRF_TEMP->T0 = NRF_FICR->TEMP.T0; - NRF_TEMP->T1 = NRF_FICR->TEMP.T1; - NRF_TEMP->T2 = NRF_FICR->TEMP.T2; - NRF_TEMP->T3 = NRF_FICR->TEMP.T3; - NRF_TEMP->T4 = NRF_FICR->TEMP.T4; - } - - /* Workaround for Errata 108 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ - if (errata_108()){ - *(volatile uint32_t *)0x40000EE4 = *(volatile uint32_t *)0x10000258 & 0x0000004F; - } - - /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ - if (errata_136()){ - if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){ - NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk; - } - } - - /* Workaround for Errata 182 "RADIO: Fixes for anomalies #102, #106, and #107 do not take effect" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ - if (errata_182()){ - *(volatile uint32_t *) 0x4000173C |= (0x1 << 10); - } - - /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the - * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit - * operations are not used in your code. */ - #if (__FPU_USED == 1) - SCB->CPACR |= (3UL << 20) | (3UL << 22); - __DSB(); - __ISB(); - #endif - - /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined, - two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as - normal GPIOs. */ - #if defined (CONFIG_NFCT_PINS_AS_GPIOS) - if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){ - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NVIC_SystemReset(); - } - #endif - - /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not - defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be - reserved for PinReset and not available as normal GPIO. */ - #if defined (CONFIG_GPIO_AS_PINRESET) - if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) || - ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){ - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NRF_UICR->PSELRESET[0] = 21; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NRF_UICR->PSELRESET[1] = 21; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NVIC_SystemReset(); - } - #endif - - SystemCoreClockUpdate(); -} - - -static bool errata_12(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ - return true; - } - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40){ - return true; - } - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){ - return true; - } - } - - return false; -} - -static bool errata_16(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ - return true; - } - } - - return false; -} - -static bool errata_31(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ - return true; - } - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40){ - return true; - } - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){ - return true; - } - } - - return false; -} - -static bool errata_32(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ - return true; - } - } - - return false; -} - -static bool errata_36(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ - return true; - } - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40){ - return true; - } - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){ - return true; - } - } - - return false; -} - -static bool errata_37(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ - return true; - } - } - - return false; -} - -static bool errata_57(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ - return true; - } - } - - return false; -} - -static bool errata_66(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){ - return true; - } - } - - return false; -} - - -static bool errata_108(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ - return true; - } - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40){ - return true; - } - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){ - return true; - } - } - - return false; -} - - -static bool errata_136(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ - return true; - } - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40){ - return true; - } - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){ - return true; - } - } - - return false; -} - - -static bool errata_182(void) -{ - if (*(uint32_t *)0x10000130ul == 0x6ul){ - if (*(uint32_t *)0x10000134ul == 0x6ul){ - return true; - } - } - - return false; -} - - -/*lint --flb "Leave library region" */ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/system_nrf52840.c b/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/system_nrf52840.c deleted file mode 100644 index fb9e01a0bc..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/system_nrf52840.c +++ /dev/null @@ -1,288 +0,0 @@ -/* - -Copyright (c) 2009-2018 ARM Limited. All rights reserved. - - SPDX-License-Identifier: Apache-2.0 - -Licensed under the Apache License, Version 2.0 (the License); you may -not use this file except in compliance with the License. -You may obtain a copy of the License at - - www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an AS IS BASIS, WITHOUT -WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -NOTICE: This file has been modified by Nordic Semiconductor ASA. - -*/ - -/* NOTE: Template files (including this one) are application specific and therefore expected to - be copied into the application project folder prior to its use! */ - -#include -#include -#include "nrf.h" -#include "system_nrf52840.h" - -/*lint ++flb "Enter library region" */ - -#define __SYSTEM_CLOCK_64M (64000000UL) - -static bool errata_36(void); -static bool errata_66(void); -static bool errata_98(void); -static bool errata_103(void); -static bool errata_115(void); -static bool errata_120(void); -static bool errata_136(void); - - -#if defined ( __CC_ARM ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; -#elif defined ( __ICCARM__ ) - __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M; -#elif defined ( __GNUC__ ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; -#endif - -void SystemCoreClockUpdate(void) -{ - SystemCoreClock = __SYSTEM_CLOCK_64M; -} - -void SystemInit(void) -{ - /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product - Specification to see which one). */ - #if defined (ENABLE_SWO) - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos; - NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - #endif - - /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product - Specification to see which ones). */ - #if defined (ENABLE_TRACE) - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos; - NRF_P0->PIN_CNF[7] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - NRF_P0->PIN_CNF[12] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - NRF_P0->PIN_CNF[11] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - NRF_P1->PIN_CNF[9] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - #endif - - /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ - if (errata_36()){ - NRF_CLOCK->EVENTS_DONE = 0; - NRF_CLOCK->EVENTS_CTTO = 0; - NRF_CLOCK->CTIV = 0; - } - - /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ - if (errata_66()){ - NRF_TEMP->A0 = NRF_FICR->TEMP.A0; - NRF_TEMP->A1 = NRF_FICR->TEMP.A1; - NRF_TEMP->A2 = NRF_FICR->TEMP.A2; - NRF_TEMP->A3 = NRF_FICR->TEMP.A3; - NRF_TEMP->A4 = NRF_FICR->TEMP.A4; - NRF_TEMP->A5 = NRF_FICR->TEMP.A5; - NRF_TEMP->B0 = NRF_FICR->TEMP.B0; - NRF_TEMP->B1 = NRF_FICR->TEMP.B1; - NRF_TEMP->B2 = NRF_FICR->TEMP.B2; - NRF_TEMP->B3 = NRF_FICR->TEMP.B3; - NRF_TEMP->B4 = NRF_FICR->TEMP.B4; - NRF_TEMP->B5 = NRF_FICR->TEMP.B5; - NRF_TEMP->T0 = NRF_FICR->TEMP.T0; - NRF_TEMP->T1 = NRF_FICR->TEMP.T1; - NRF_TEMP->T2 = NRF_FICR->TEMP.T2; - NRF_TEMP->T3 = NRF_FICR->TEMP.T3; - NRF_TEMP->T4 = NRF_FICR->TEMP.T4; - } - - /* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ - if (errata_98()){ - *(volatile uint32_t *)0x4000568Cul = 0x00038148ul; - } - - /* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ - if (errata_103()){ - NRF_CCM->MAXPACKETSIZE = 0xFBul; - } - - /* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ - if (errata_115()){ - *(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F); - } - - /* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ - if (errata_120()){ - *(volatile uint32_t *)0x40029640ul = 0x200ul; - } - - /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ - if (errata_136()){ - if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){ - NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk; - } - } - - /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the - * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit - * operations are not used in your code. */ - #if (__FPU_USED == 1) - SCB->CPACR |= (3UL << 20) | (3UL << 22); - __DSB(); - __ISB(); - #endif - - /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined, - two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as - normal GPIOs. */ - #if defined (CONFIG_NFCT_PINS_AS_GPIOS) - if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){ - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NVIC_SystemReset(); - } - #endif - - /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not - defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be - reserved for PinReset and not available as normal GPIO. */ - #if defined (CONFIG_GPIO_AS_PINRESET) - if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) || - ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){ - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NRF_UICR->PSELRESET[0] = 18; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NRF_UICR->PSELRESET[1] = 18; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NVIC_SystemReset(); - } - #endif - - SystemCoreClockUpdate(); -} - - -static bool errata_36(void) -{ - if (*(uint32_t *)0x10000130ul == 0x8ul){ - if (*(uint32_t *)0x10000134ul == 0x0ul){ - return true; - } - if (*(uint32_t *)0x10000134ul == 0x1ul){ - return true; - } - if (*(uint32_t *)0x10000134ul == 0x2ul){ - return true; - } - } - - return true; -} - - -static bool errata_66(void) -{ - if (*(uint32_t *)0x10000130ul == 0x8ul){ - if (*(uint32_t *)0x10000134ul == 0x0ul){ - return true; - } - if (*(uint32_t *)0x10000134ul == 0x1ul){ - return true; - } - if (*(uint32_t *)0x10000134ul == 0x2ul){ - return true; - } - } - - return true; -} - - -static bool errata_98(void) -{ - if (*(uint32_t *)0x10000130ul == 0x8ul){ - if (*(uint32_t *)0x10000134ul == 0x0ul){ - return true; - } - } - - return false; -} - - -static bool errata_103(void) -{ - if (*(uint32_t *)0x10000130ul == 0x8ul){ - if (*(uint32_t *)0x10000134ul == 0x0ul){ - return true; - } - } - - return false; -} - - -static bool errata_115(void) -{ - if (*(uint32_t *)0x10000130ul == 0x8ul){ - if (*(uint32_t *)0x10000134ul == 0x0ul){ - return true; - } - } - - return false; -} - - -static bool errata_120(void) -{ - if (*(uint32_t *)0x10000130ul == 0x8ul){ - if (*(uint32_t *)0x10000134ul == 0x0ul){ - return true; - } - } - - return false; -} - - -static bool errata_136(void) -{ - if (*(uint32_t *)0x10000130ul == 0x8ul){ - if (*(uint32_t *)0x10000134ul == 0x0ul){ - return true; - } - if (*(uint32_t *)0x10000134ul == 0x1ul){ - return true; - } - if (*(uint32_t *)0x10000134ul == 0x2ul){ - return true; - } - } - - return true; -} - -/*lint --flb "Leave library region" */ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/nrfx.h b/bsp/boards/nrf52840/sdk/modules/nrfx/nrfx.h deleted file mode 100644 index 036c7eee18..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/nrfx.h +++ /dev/null @@ -1,49 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_H__ -#define NRFX_H__ - -#include -#include -#include -#include - -#endif // NRFX_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/soc/nrfx_coredep.h b/bsp/boards/nrf52840/sdk/modules/nrfx/soc/nrfx_coredep.h deleted file mode 100644 index e338c03e5f..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/soc/nrfx_coredep.h +++ /dev/null @@ -1,171 +0,0 @@ -/** - * Copyright (c) 2018 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_COREDEP_H__ -#define NRFX_COREDEP_H__ - -/** - * @defgroup nrfx_coredep Core-dependent functionality - * @{ - * @ingroup nrfx - * @brief Module containing functions with core-dependent implementation, like delay. - */ - -#if defined(__NRFX_DOXYGEN__) - -/** @brief Core frequency (in MHz). */ -#define NRFX_DELAY_CPU_FREQ_MHZ -/** @brief Availability of DWT unit in the given SoC. */ -#define NRFX_DELAY_DWT_PRESENT - -#elif defined(NRF51) - #define NRFX_DELAY_CPU_FREQ_MHZ 16 - #define NRFX_DELAY_DWT_PRESENT 0 -#elif defined(NRF52810_XXAA) - #define NRFX_DELAY_CPU_FREQ_MHZ 64 - #define NRFX_DELAY_DWT_PRESENT 0 -#elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB) - #define NRFX_DELAY_CPU_FREQ_MHZ 64 - #define NRFX_DELAY_DWT_PRESENT 1 -#elif defined(NRF52840_XXAA) - #define NRFX_DELAY_CPU_FREQ_MHZ 64 - #define NRFX_DELAY_DWT_PRESENT 1 -#else - #error "Unknown device." -#endif - -/** - * @brief Function for delaying execution for a number of microseconds. - * - * The value of @p time_us is multiplied by the frequency in MHz. Therefore, the delay is limited to - * maximum uint32_t capacity divided by frequency. For example: - * - For SoCs working at 64MHz: 0xFFFFFFFF/64 = 0x03FFFFFF (67108863 microseconds) - * - For SoCs working at 16MHz: 0xFFFFFFFF/16 = 0x0FFFFFFF (268435455 microseconds) - * - * @param time_us Number of microseconds to wait. - */ -__STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us); - -/** @} */ - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -#if NRFX_CHECK(NRFX_DELAY_DWT_BASED) - -#if !NRFX_DELAY_DWT_PRESENT -#error "DWT unit not present in the SoC that is used." -#endif - -__STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us) -{ - if (time_us == 0) - { - return; - } - uint32_t time_cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ; - - // Save the current state of the DEMCR register to be able to restore it before exiting - // this function. Enable the trace and debug blocks (DWT is one of them). - uint32_t core_debug = CoreDebug->DEMCR; - CoreDebug->DEMCR = core_debug | CoreDebug_DEMCR_TRCENA_Msk; - - // Save the current state of the CTRL register in DWT block. Make sure - // that cycle counter is enabled. - uint32_t dwt_ctrl = DWT->CTRL; - DWT->CTRL = dwt_ctrl | DWT_CTRL_CYCCNTENA_Msk; - - // Store start value of cycle counter. - uint32_t cyccnt_initial = DWT->CYCCNT; - - // Delay required time. - while ((DWT->CYCCNT - cyccnt_initial) < time_cycles) - {} - - // Restore preserved registers. - DWT->CTRL = dwt_ctrl; - CoreDebug->DEMCR = core_debug; -} -#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED) - - -__STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us) -{ - if (time_us == 0) - { - return; - } - - #if defined(NRF51) - // The loop takes 4 cycles: 1 for SUBS and 3 for BHI. - static const uint16_t delay_bytecode[] = { - 0x3804, // SUBS r0, #4 - 0xd8fd, // BHI .-2 - 0x4770 // BX LR - }; - #elif defined(NRF52810_XXAA) - // The loop takes 7 cycles: 1 for SUBS and 2 for BHI and 2 for flash wait states. - static const uint16_t delay_bytecode[] = { - 0x3807, // SUBS r0, #7 - 0xd8fd, // BHI .-2 - 0x4770 // BX LR - }; - #elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB) || defined(NRF52840_XXAA) - // The loop takes 3 cycles: 1 for SUBS and 2 for BHI. - // Make sure that code will be cached properly, so that no extra wait states appear. - __ALIGN(16) - static const uint16_t delay_bytecode[] = { - 0x3803, // SUBS r0, #3 - 0xd8fd, // BHI .-2 - 0x4770 // BX LR - }; - #endif - - typedef void (* delay_func_t)(uint32_t); - // Set LSB to 1 to execute code in Thumb mode. - const delay_func_t delay_cycles = (delay_func_t)((((uint32_t)delay_bytecode) | 1)); - uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ; - delay_cycles(cycles); -} - -#endif // !NRFX_CHECK(NRFX_DELAY_DWT_BASED_DELAY) - -#endif // SUPPRESS_INLINE_IMPLEMENTATION - -#endif // NRFX_COREDEP_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/soc/nrfx_irqs.h b/bsp/boards/nrf52840/sdk/modules/nrfx/soc/nrfx_irqs.h deleted file mode 100644 index e76b8c2030..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/soc/nrfx_irqs.h +++ /dev/null @@ -1,56 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_IRQS_H__ -#define NRFX_IRQS_H__ - -#if defined(NRF51) - #include -#elif defined(NRF52810_XXAA) - #include -#elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB) - #include -#elif defined(NRF52840_XXAA) - #include -#else - #error "Unknown device." -#endif - -#endif // NRFX_IRQS_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/soc/nrfx_irqs_nrf52840.h b/bsp/boards/nrf52840/sdk/modules/nrfx/soc/nrfx_irqs_nrf52840.h deleted file mode 100644 index 25c932befe..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/soc/nrfx_irqs_nrf52840.h +++ /dev/null @@ -1,208 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_IRQS_NRF52840_H__ -#define NRFX_IRQS_NRF52840_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -// POWER_CLOCK_IRQn -#define nrfx_power_clock_irq_handler POWER_CLOCK_IRQHandler - -// RADIO_IRQn - -// UARTE0_UART0_IRQn -#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_4_ENABLED) -#define nrfx_prs_box_4_irq_handler UARTE0_UART0_IRQHandler -#else -#define nrfx_uarte_0_irq_handler UARTE0_UART0_IRQHandler -#define nrfx_uart_0_irq_handler UARTE0_UART0_IRQHandler -#endif - -// SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn -#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED) -#define nrfx_prs_box_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler -#else -#define nrfx_spim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler -#define nrfx_spis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler -#define nrfx_twim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler -#define nrfx_twis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler -#define nrfx_spi_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler -#define nrfx_twi_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler -#endif - -// SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn -#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED) -#define nrfx_prs_box_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler -#else -#define nrfx_spim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler -#define nrfx_spis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler -#define nrfx_twim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler -#define nrfx_twis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler -#define nrfx_spi_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler -#define nrfx_twi_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler -#endif - -// NFCT_IRQn - -// GPIOTE_IRQn -#define nrfx_gpiote_irq_handler GPIOTE_IRQHandler - -// SAADC_IRQn -#define nrfx_saadc_irq_handler SAADC_IRQHandler - -// TIMER0_IRQn -#define nrfx_timer_0_irq_handler TIMER0_IRQHandler - -// TIMER1_IRQn -#define nrfx_timer_1_irq_handler TIMER1_IRQHandler - -// TIMER2_IRQn -#define nrfx_timer_2_irq_handler TIMER2_IRQHandler - -// RTC0_IRQn -#define nrfx_rtc_0_irq_handler RTC0_IRQHandler - -// TEMP_IRQn - -// RNG_IRQn -#define nrfx_rng_irq_handler RNG_IRQHandler - -// ECB_IRQn - -// CCM_AAR_IRQn - -// WDT_IRQn -#define nrfx_wdt_irq_handler WDT_IRQHandler - -// RTC1_IRQn -#define nrfx_rtc_1_irq_handler RTC1_IRQHandler - -// QDEC_IRQn -#define nrfx_qdec_irq_handler QDEC_IRQHandler - -// COMP_LPCOMP_IRQn -#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_3_ENABLED) -#define nrfx_prs_box_3_irq_handler COMP_LPCOMP_IRQHandler -#else -#define nrfx_comp_irq_handler COMP_LPCOMP_IRQHandler -#define nrfx_lpcomp_irq_handler COMP_LPCOMP_IRQHandler -#endif - -// SWI0_EGU0_IRQn -#define nrfx_swi_0_irq_handler SWI0_EGU0_IRQHandler - -// SWI1_EGU1_IRQn -#define nrfx_swi_1_irq_handler SWI1_EGU1_IRQHandler - -// SWI2_EGU2_IRQn -#define nrfx_swi_2_irq_handler SWI2_EGU2_IRQHandler - -// SWI3_EGU3_IRQn -#define nrfx_swi_3_irq_handler SWI3_EGU3_IRQHandler - -// SWI4_EGU4_IRQn -#define nrfx_swi_4_irq_handler SWI4_EGU4_IRQHandler - -// SWI5_EGU5_IRQn -#define nrfx_swi_5_irq_handler SWI5_EGU5_IRQHandler - -// TIMER3_IRQn -#define nrfx_timer_3_irq_handler TIMER3_IRQHandler - -// TIMER4_IRQn -#define nrfx_timer_4_irq_handler TIMER4_IRQHandler - -// PWM0_IRQn -#define nrfx_pwm_0_irq_handler PWM0_IRQHandler - -// PDM_IRQn -#define nrfx_pdm_irq_handler PDM_IRQHandler - -// MWU_IRQn - -// PWM1_IRQn -#define nrfx_pwm_1_irq_handler PWM1_IRQHandler - -// PWM2_IRQn -#define nrfx_pwm_2_irq_handler PWM2_IRQHandler - -// SPIM2_SPIS2_SPI2_IRQn -#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED) -#define nrfx_prs_box_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler -#else -#define nrfx_spim_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler -#define nrfx_spis_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler -#define nrfx_spi_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler -#endif - -// RTC2_IRQn -#define nrfx_rtc_2_irq_handler RTC2_IRQHandler - -// I2S_IRQn -#define nrfx_i2s_irq_handler I2S_IRQHandler - -// FPU_IRQn - -// USBD_IRQn - -// UARTE1_IRQn -#define nrfx_uarte_1_irq_handler UARTE1_IRQHandler - -// QSPI_IRQn -#define nrfx_qspi_irq_handler QSPI_IRQHandler - -// CRYPTOCELL_IRQn - -// PWM3_IRQn -#define nrfx_pwm_3_irq_handler PWM3_IRQHandler - -// SPIM3_IRQn -#define nrfx_spim_3_irq_handler SPIM3_IRQHandler - - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_IRQS_NRF52840_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/templates/nRF52840/nrfx_config.h b/bsp/boards/nrf52840/sdk/modules/nrfx/templates/nRF52840/nrfx_config.h deleted file mode 100644 index ae4bb542f7..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/templates/nRF52840/nrfx_config.h +++ /dev/null @@ -1,2964 +0,0 @@ -#ifndef NRFX_CONFIG_H__ -#define NRFX_CONFIG_H__ - -// <<< Use Configuration Wizard in Context Menu >>>\n - -// nRF_Drivers - -// NRFX_CLOCK_ENABLED - nrfx_clock - CLOCK peripheral driver -//========================================================== -#ifndef NRFX_CLOCK_ENABLED -#define NRFX_CLOCK_ENABLED 1 -#endif -// NRFX_CLOCK_CONFIG_LF_SRC - LF Clock Source - -// <0=> RC -// <1=> XTAL -// <2=> Synth - -#ifndef NRFX_CLOCK_CONFIG_LF_SRC -#define NRFX_CLOCK_CONFIG_LF_SRC 1 -#endif - -// NRFX_CLOCK_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_CLOCK_CONFIG_IRQ_PRIORITY -#define NRFX_CLOCK_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_CLOCK_CONFIG_LOG_ENABLED -#define NRFX_CLOCK_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_CLOCK_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_CLOCK_CONFIG_LOG_LEVEL -#define NRFX_CLOCK_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_CLOCK_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_CLOCK_CONFIG_INFO_COLOR -#define NRFX_CLOCK_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_CLOCK_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_CLOCK_CONFIG_DEBUG_COLOR -#define NRFX_CLOCK_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_COMP_ENABLED - nrfx_comp - COMP peripheral driver -//========================================================== -#ifndef NRFX_COMP_ENABLED -#define NRFX_COMP_ENABLED 1 -#endif -// NRFX_COMP_CONFIG_REF - Reference voltage - -// <0=> Internal 1.2V -// <1=> Internal 1.8V -// <2=> Internal 2.4V -// <4=> VDD -// <7=> ARef - -#ifndef NRFX_COMP_CONFIG_REF -#define NRFX_COMP_CONFIG_REF 1 -#endif - -// NRFX_COMP_CONFIG_MAIN_MODE - Main mode - -// <0=> Single ended -// <1=> Differential - -#ifndef NRFX_COMP_CONFIG_MAIN_MODE -#define NRFX_COMP_CONFIG_MAIN_MODE 0 -#endif - -// NRFX_COMP_CONFIG_SPEED_MODE - Speed mode - -// <0=> Low power -// <1=> Normal -// <2=> High speed - -#ifndef NRFX_COMP_CONFIG_SPEED_MODE -#define NRFX_COMP_CONFIG_SPEED_MODE 2 -#endif - -// NRFX_COMP_CONFIG_HYST - Hystheresis - -// <0=> No -// <1=> 50mV - -#ifndef NRFX_COMP_CONFIG_HYST -#define NRFX_COMP_CONFIG_HYST 0 -#endif - -// NRFX_COMP_CONFIG_ISOURCE - Current Source - -// <0=> Off -// <1=> 2.5 uA -// <2=> 5 uA -// <3=> 10 uA - -#ifndef NRFX_COMP_CONFIG_ISOURCE -#define NRFX_COMP_CONFIG_ISOURCE 0 -#endif - -// NRFX_COMP_CONFIG_INPUT - Analog input - -// <0=> 0 -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_COMP_CONFIG_INPUT -#define NRFX_COMP_CONFIG_INPUT 0 -#endif - -// NRFX_COMP_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_COMP_CONFIG_IRQ_PRIORITY -#define NRFX_COMP_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_COMP_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_COMP_CONFIG_LOG_ENABLED -#define NRFX_COMP_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_COMP_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_COMP_CONFIG_LOG_LEVEL -#define NRFX_COMP_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_COMP_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_COMP_CONFIG_INFO_COLOR -#define NRFX_COMP_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_COMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_COMP_CONFIG_DEBUG_COLOR -#define NRFX_COMP_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_GPIOTE_ENABLED - nrfx_gpiote - GPIOTE peripheral driver -//========================================================== -#ifndef NRFX_GPIOTE_ENABLED -#define NRFX_GPIOTE_ENABLED 1 -#endif -// NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins -#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS -#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 -#endif - -// NRFX_GPIOTE_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_GPIOTE_CONFIG_IRQ_PRIORITY -#define NRFX_GPIOTE_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED -#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_GPIOTE_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL -#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_GPIOTE_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_GPIOTE_CONFIG_INFO_COLOR -#define NRFX_GPIOTE_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_GPIOTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_GPIOTE_CONFIG_DEBUG_COLOR -#define NRFX_GPIOTE_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_I2S_ENABLED - nrfx_i2s - I2S peripheral driver -//========================================================== -#ifndef NRFX_I2S_ENABLED -#define NRFX_I2S_ENABLED 1 -#endif -// NRFX_I2S_CONFIG_SCK_PIN - SCK pin <0-31> - - -#ifndef NRFX_I2S_CONFIG_SCK_PIN -#define NRFX_I2S_CONFIG_SCK_PIN 31 -#endif - -// NRFX_I2S_CONFIG_LRCK_PIN - LRCK pin <1-31> - - -#ifndef NRFX_I2S_CONFIG_LRCK_PIN -#define NRFX_I2S_CONFIG_LRCK_PIN 30 -#endif - -// NRFX_I2S_CONFIG_MCK_PIN - MCK pin -#ifndef NRFX_I2S_CONFIG_MCK_PIN -#define NRFX_I2S_CONFIG_MCK_PIN 255 -#endif - -// NRFX_I2S_CONFIG_SDOUT_PIN - SDOUT pin <0-31> - - -#ifndef NRFX_I2S_CONFIG_SDOUT_PIN -#define NRFX_I2S_CONFIG_SDOUT_PIN 29 -#endif - -// NRFX_I2S_CONFIG_SDIN_PIN - SDIN pin <0-31> - - -#ifndef NRFX_I2S_CONFIG_SDIN_PIN -#define NRFX_I2S_CONFIG_SDIN_PIN 28 -#endif - -// NRFX_I2S_CONFIG_MASTER - Mode - -// <0=> Master -// <1=> Slave - -#ifndef NRFX_I2S_CONFIG_MASTER -#define NRFX_I2S_CONFIG_MASTER 0 -#endif - -// NRFX_I2S_CONFIG_FORMAT - Format - -// <0=> I2S -// <1=> Aligned - -#ifndef NRFX_I2S_CONFIG_FORMAT -#define NRFX_I2S_CONFIG_FORMAT 0 -#endif - -// NRFX_I2S_CONFIG_ALIGN - Alignment - -// <0=> Left -// <1=> Right - -#ifndef NRFX_I2S_CONFIG_ALIGN -#define NRFX_I2S_CONFIG_ALIGN 0 -#endif - -// NRFX_I2S_CONFIG_SWIDTH - Sample width (bits) - -// <0=> 8 -// <1=> 16 -// <2=> 24 - -#ifndef NRFX_I2S_CONFIG_SWIDTH -#define NRFX_I2S_CONFIG_SWIDTH 1 -#endif - -// NRFX_I2S_CONFIG_CHANNELS - Channels - -// <0=> Stereo -// <1=> Left -// <2=> Right - -#ifndef NRFX_I2S_CONFIG_CHANNELS -#define NRFX_I2S_CONFIG_CHANNELS 1 -#endif - -// NRFX_I2S_CONFIG_MCK_SETUP - MCK behavior - -// <0=> Disabled -// <2147483648=> 32MHz/2 -// <1342177280=> 32MHz/3 -// <1073741824=> 32MHz/4 -// <805306368=> 32MHz/5 -// <671088640=> 32MHz/6 -// <536870912=> 32MHz/8 -// <402653184=> 32MHz/10 -// <369098752=> 32MHz/11 -// <285212672=> 32MHz/15 -// <268435456=> 32MHz/16 -// <201326592=> 32MHz/21 -// <184549376=> 32MHz/23 -// <142606336=> 32MHz/30 -// <138412032=> 32MHz/31 -// <134217728=> 32MHz/32 -// <100663296=> 32MHz/42 -// <68157440=> 32MHz/63 -// <34340864=> 32MHz/125 - -#ifndef NRFX_I2S_CONFIG_MCK_SETUP -#define NRFX_I2S_CONFIG_MCK_SETUP 536870912 -#endif - -// NRFX_I2S_CONFIG_RATIO - MCK/LRCK ratio - -// <0=> 32x -// <1=> 48x -// <2=> 64x -// <3=> 96x -// <4=> 128x -// <5=> 192x -// <6=> 256x -// <7=> 384x -// <8=> 512x - -#ifndef NRFX_I2S_CONFIG_RATIO -#define NRFX_I2S_CONFIG_RATIO 2000 -#endif - -// NRFX_I2S_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_I2S_CONFIG_IRQ_PRIORITY -#define NRFX_I2S_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_I2S_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_I2S_CONFIG_LOG_ENABLED -#define NRFX_I2S_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_I2S_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_I2S_CONFIG_LOG_LEVEL -#define NRFX_I2S_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_I2S_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_I2S_CONFIG_INFO_COLOR -#define NRFX_I2S_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_I2S_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_I2S_CONFIG_DEBUG_COLOR -#define NRFX_I2S_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_LPCOMP_ENABLED - nrfx_lpcomp - LPCOMP peripheral driver -//========================================================== -#ifndef NRFX_LPCOMP_ENABLED -#define NRFX_LPCOMP_ENABLED 1 -#endif -// NRFX_LPCOMP_CONFIG_REFERENCE - Reference voltage - -// <0=> Supply 1/8 -// <1=> Supply 2/8 -// <2=> Supply 3/8 -// <3=> Supply 4/8 -// <4=> Supply 5/8 -// <5=> Supply 6/8 -// <6=> Supply 7/8 -// <8=> Supply 1/16 (nRF52) -// <9=> Supply 3/16 (nRF52) -// <10=> Supply 5/16 (nRF52) -// <11=> Supply 7/16 (nRF52) -// <12=> Supply 9/16 (nRF52) -// <13=> Supply 11/16 (nRF52) -// <14=> Supply 13/16 (nRF52) -// <15=> Supply 15/16 (nRF52) -// <7=> External Ref 0 -// <65543=> External Ref 1 - -#ifndef NRFX_LPCOMP_CONFIG_REFERENCE -#define NRFX_LPCOMP_CONFIG_REFERENCE 3 -#endif - -// NRFX_LPCOMP_CONFIG_DETECTION - Detection - -// <0=> Crossing -// <1=> Up -// <2=> Down - -#ifndef NRFX_LPCOMP_CONFIG_DETECTION -#define NRFX_LPCOMP_CONFIG_DETECTION 2 -#endif - -// NRFX_LPCOMP_CONFIG_INPUT - Analog input - -// <0=> 0 -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_LPCOMP_CONFIG_INPUT -#define NRFX_LPCOMP_CONFIG_INPUT 0 -#endif - -// NRFX_LPCOMP_CONFIG_HYST - Hysteresis - - -#ifndef NRFX_LPCOMP_CONFIG_HYST -#define NRFX_LPCOMP_CONFIG_HYST 0 -#endif - -// NRFX_LPCOMP_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_LPCOMP_CONFIG_IRQ_PRIORITY -#define NRFX_LPCOMP_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_LPCOMP_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED -#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_LPCOMP_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL -#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_LPCOMP_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_LPCOMP_CONFIG_INFO_COLOR -#define NRFX_LPCOMP_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_LPCOMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_LPCOMP_CONFIG_DEBUG_COLOR -#define NRFX_LPCOMP_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_PDM_ENABLED - nrfx_pdm - PDM peripheral driver -//========================================================== -#ifndef NRFX_PDM_ENABLED -#define NRFX_PDM_ENABLED 1 -#endif -// NRFX_PDM_CONFIG_MODE - Mode - -// <0=> Stereo -// <1=> Mono - -#ifndef NRFX_PDM_CONFIG_MODE -#define NRFX_PDM_CONFIG_MODE 1 -#endif - -// NRFX_PDM_CONFIG_EDGE - Edge - -// <0=> Left falling -// <1=> Left rising - -#ifndef NRFX_PDM_CONFIG_EDGE -#define NRFX_PDM_CONFIG_EDGE 0 -#endif - -// NRFX_PDM_CONFIG_CLOCK_FREQ - Clock frequency - -// <134217728=> 1000k -// <138412032=> 1032k (default) -// <142606336=> 1067k - -#ifndef NRFX_PDM_CONFIG_CLOCK_FREQ -#define NRFX_PDM_CONFIG_CLOCK_FREQ 138412032 -#endif - -// NRFX_PDM_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_PDM_CONFIG_IRQ_PRIORITY -#define NRFX_PDM_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_PDM_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_PDM_CONFIG_LOG_ENABLED -#define NRFX_PDM_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_PDM_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_PDM_CONFIG_LOG_LEVEL -#define NRFX_PDM_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_PDM_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_PDM_CONFIG_INFO_COLOR -#define NRFX_PDM_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_PDM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_PDM_CONFIG_DEBUG_COLOR -#define NRFX_PDM_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_POWER_ENABLED - nrfx_power - POWER peripheral driver -//========================================================== -#ifndef NRFX_POWER_ENABLED -#define NRFX_POWER_ENABLED 1 -#endif -// NRFX_POWER_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_POWER_CONFIG_IRQ_PRIORITY -#define NRFX_POWER_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_POWER_CONFIG_DEFAULT_DCDCEN - The default configuration of main DCDC regulator - - -// This settings means only that components for DCDC regulator are installed and it can be enabled. - -#ifndef NRFX_POWER_CONFIG_DEFAULT_DCDCEN -#define NRFX_POWER_CONFIG_DEFAULT_DCDCEN 1 -#endif - -// NRFX_POWER_CONFIG_DEFAULT_DCDCENHV - The default configuration of High Voltage DCDC regulator - - -// This settings means only that components for DCDC regulator are installed and it can be enabled. - -#ifndef NRFX_POWER_CONFIG_DEFAULT_DCDCENHV -#define NRFX_POWER_CONFIG_DEFAULT_DCDCENHV 0 -#endif - -// - -// NRFX_PPI_ENABLED - nrfx_ppi - PPI peripheral allocator -//========================================================== -#ifndef NRFX_PPI_ENABLED -#define NRFX_PPI_ENABLED 1 -#endif -// NRFX_PPI_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_PPI_CONFIG_LOG_ENABLED -#define NRFX_PPI_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_PPI_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_PPI_CONFIG_LOG_LEVEL -#define NRFX_PPI_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_PPI_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_PPI_CONFIG_INFO_COLOR -#define NRFX_PPI_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_PPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_PPI_CONFIG_DEBUG_COLOR -#define NRFX_PPI_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_PRS_ENABLED - nrfx_prs - Peripheral Resource Sharing module -//========================================================== -#ifndef NRFX_PRS_ENABLED -#define NRFX_PRS_ENABLED 1 -#endif -// NRFX_PRS_BOX_0_ENABLED - Enables box 0 in the module. - - -#ifndef NRFX_PRS_BOX_0_ENABLED -#define NRFX_PRS_BOX_0_ENABLED 1 -#endif - -// NRFX_PRS_BOX_1_ENABLED - Enables box 1 in the module. - - -#ifndef NRFX_PRS_BOX_1_ENABLED -#define NRFX_PRS_BOX_1_ENABLED 1 -#endif - -// NRFX_PRS_BOX_2_ENABLED - Enables box 2 in the module. - - -#ifndef NRFX_PRS_BOX_2_ENABLED -#define NRFX_PRS_BOX_2_ENABLED 1 -#endif - -// NRFX_PRS_BOX_3_ENABLED - Enables box 3 in the module. - - -#ifndef NRFX_PRS_BOX_3_ENABLED -#define NRFX_PRS_BOX_3_ENABLED 1 -#endif - -// NRFX_PRS_BOX_4_ENABLED - Enables box 4 in the module. - - -#ifndef NRFX_PRS_BOX_4_ENABLED -#define NRFX_PRS_BOX_4_ENABLED 1 -#endif - -// NRFX_PRS_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_PRS_CONFIG_LOG_ENABLED -#define NRFX_PRS_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_PRS_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_PRS_CONFIG_LOG_LEVEL -#define NRFX_PRS_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_PRS_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_PRS_CONFIG_INFO_COLOR -#define NRFX_PRS_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_PRS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_PRS_CONFIG_DEBUG_COLOR -#define NRFX_PRS_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_PWM_ENABLED - nrfx_pwm - PWM peripheral driver -//========================================================== -#ifndef NRFX_PWM_ENABLED -#define NRFX_PWM_ENABLED 1 -#endif -// NRFX_PWM0_ENABLED - Enable PWM0 instance - - -#ifndef NRFX_PWM0_ENABLED -#define NRFX_PWM0_ENABLED 1 -#endif - -// NRFX_PWM1_ENABLED - Enable PWM1 instance - - -#ifndef NRFX_PWM1_ENABLED -#define NRFX_PWM1_ENABLED 1 -#endif - -// NRFX_PWM2_ENABLED - Enable PWM2 instance - - -#ifndef NRFX_PWM2_ENABLED -#define NRFX_PWM2_ENABLED 1 -#endif - -// NRFX_PWM3_ENABLED - Enable PWM3 instance - - -#ifndef NRFX_PWM3_ENABLED -#define NRFX_PWM3_ENABLED 1 -#endif - -// NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin <0-31> - - -#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN -#define NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN 31 -#endif - -// NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin <0-31> - - -#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN -#define NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN 31 -#endif - -// NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin <0-31> - - -#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN -#define NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN 31 -#endif - -// NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin <0-31> - - -#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN -#define NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN 31 -#endif - -// NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK - Base clock - -// <0=> 16 MHz -// <1=> 8 MHz -// <2=> 4 MHz -// <3=> 2 MHz -// <4=> 1 MHz -// <5=> 500 kHz -// <6=> 250 kHz -// <7=> 125 kHz - -#ifndef NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK -#define NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK 4 -#endif - -// NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE - Count mode - -// <0=> Up -// <1=> Up and Down - -#ifndef NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE -#define NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE 0 -#endif - -// NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE - Top value -#ifndef NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE -#define NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE 1000 -#endif - -// NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE - Load mode - -// <0=> Common -// <1=> Grouped -// <2=> Individual -// <3=> Waveform - -#ifndef NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE -#define NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE 0 -#endif - -// NRFX_PWM_DEFAULT_CONFIG_STEP_MODE - Step mode - -// <0=> Auto -// <1=> Triggered - -#ifndef NRFX_PWM_DEFAULT_CONFIG_STEP_MODE -#define NRFX_PWM_DEFAULT_CONFIG_STEP_MODE 0 -#endif - -// NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_PWM_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_PWM_CONFIG_LOG_ENABLED -#define NRFX_PWM_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_PWM_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_PWM_CONFIG_LOG_LEVEL -#define NRFX_PWM_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_PWM_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_PWM_CONFIG_INFO_COLOR -#define NRFX_PWM_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_PWM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_PWM_CONFIG_DEBUG_COLOR -#define NRFX_PWM_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_QDEC_ENABLED - nrfx_qdec - QDEC peripheral driver -//========================================================== -#ifndef NRFX_QDEC_ENABLED -#define NRFX_QDEC_ENABLED 1 -#endif -// NRFX_QDEC_CONFIG_REPORTPER - Report period - -// <0=> 10 Samples -// <1=> 40 Samples -// <2=> 80 Samples -// <3=> 120 Samples -// <4=> 160 Samples -// <5=> 200 Samples -// <6=> 240 Samples -// <7=> 280 Samples - -#ifndef NRFX_QDEC_CONFIG_REPORTPER -#define NRFX_QDEC_CONFIG_REPORTPER 0 -#endif - -// NRFX_QDEC_CONFIG_SAMPLEPER - Sample period - -// <0=> 128 us -// <1=> 256 us -// <2=> 512 us -// <3=> 1024 us -// <4=> 2048 us -// <5=> 4096 us -// <6=> 8192 us -// <7=> 16384 us - -#ifndef NRFX_QDEC_CONFIG_SAMPLEPER -#define NRFX_QDEC_CONFIG_SAMPLEPER 7 -#endif - -// NRFX_QDEC_CONFIG_PIO_A - A pin <0-31> - - -#ifndef NRFX_QDEC_CONFIG_PIO_A -#define NRFX_QDEC_CONFIG_PIO_A 31 -#endif - -// NRFX_QDEC_CONFIG_PIO_B - B pin <0-31> - - -#ifndef NRFX_QDEC_CONFIG_PIO_B -#define NRFX_QDEC_CONFIG_PIO_B 31 -#endif - -// NRFX_QDEC_CONFIG_PIO_LED - LED pin <0-31> - - -#ifndef NRFX_QDEC_CONFIG_PIO_LED -#define NRFX_QDEC_CONFIG_PIO_LED 31 -#endif - -// NRFX_QDEC_CONFIG_LEDPRE - LED pre -#ifndef NRFX_QDEC_CONFIG_LEDPRE -#define NRFX_QDEC_CONFIG_LEDPRE 511 -#endif - -// NRFX_QDEC_CONFIG_LEDPOL - LED polarity - -// <0=> Active low -// <1=> Active high - -#ifndef NRFX_QDEC_CONFIG_LEDPOL -#define NRFX_QDEC_CONFIG_LEDPOL 1 -#endif - -// NRFX_QDEC_CONFIG_DBFEN - Debouncing enable - - -#ifndef NRFX_QDEC_CONFIG_DBFEN -#define NRFX_QDEC_CONFIG_DBFEN 0 -#endif - -// NRFX_QDEC_CONFIG_SAMPLE_INTEN - Sample ready interrupt enable - - -#ifndef NRFX_QDEC_CONFIG_SAMPLE_INTEN -#define NRFX_QDEC_CONFIG_SAMPLE_INTEN 0 -#endif - -// NRFX_QDEC_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_QDEC_CONFIG_IRQ_PRIORITY -#define NRFX_QDEC_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_QDEC_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED -#define NRFX_QDEC_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_QDEC_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL -#define NRFX_QDEC_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_QDEC_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_QDEC_CONFIG_INFO_COLOR -#define NRFX_QDEC_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_QDEC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_QDEC_CONFIG_DEBUG_COLOR -#define NRFX_QDEC_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_QSPI_ENABLED - nrfx_qspi - QSPI peripheral driver -//========================================================== -#ifndef NRFX_QSPI_ENABLED -#define NRFX_QSPI_ENABLED 1 -#endif -// NRFX_QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns). <0-255> - - -#ifndef NRFX_QSPI_CONFIG_SCK_DELAY -#define NRFX_QSPI_CONFIG_SCK_DELAY 1 -#endif - -// NRFX_QSPI_CONFIG_XIP_OFFSET - Address offset in the external memory for Execute in Place operation. -#ifndef NRFX_QSPI_CONFIG_XIP_OFFSET -#define NRFX_QSPI_CONFIG_XIP_OFFSET 0 -#endif - -// NRFX_QSPI_CONFIG_READOC - Number of data lines and opcode used for reading. - -// <0=> FastRead -// <1=> Read2O -// <2=> Read2IO -// <3=> Read4O -// <4=> Read4IO - -#ifndef NRFX_QSPI_CONFIG_READOC -#define NRFX_QSPI_CONFIG_READOC 0 -#endif - -// NRFX_QSPI_CONFIG_WRITEOC - Number of data lines and opcode used for writing. - -// <0=> PP -// <1=> PP2O -// <2=> PP4O -// <3=> PP4IO - -#ifndef NRFX_QSPI_CONFIG_WRITEOC -#define NRFX_QSPI_CONFIG_WRITEOC 0 -#endif - -// NRFX_QSPI_CONFIG_ADDRMODE - Addressing mode. - -// <0=> 24bit -// <1=> 32bit - -#ifndef NRFX_QSPI_CONFIG_ADDRMODE -#define NRFX_QSPI_CONFIG_ADDRMODE 0 -#endif - -// NRFX_QSPI_CONFIG_MODE - SPI mode. - -// <0=> Mode 0 -// <1=> Mode 1 - -#ifndef NRFX_QSPI_CONFIG_MODE -#define NRFX_QSPI_CONFIG_MODE 0 -#endif - -// NRFX_QSPI_CONFIG_FREQUENCY - Frequency divider. - -// <0=> 32MHz/1 -// <1=> 32MHz/2 -// <2=> 32MHz/3 -// <3=> 32MHz/4 -// <4=> 32MHz/5 -// <5=> 32MHz/6 -// <6=> 32MHz/7 -// <7=> 32MHz/8 -// <8=> 32MHz/9 -// <9=> 32MHz/10 -// <10=> 32MHz/11 -// <11=> 32MHz/12 -// <12=> 32MHz/13 -// <13=> 32MHz/14 -// <14=> 32MHz/15 -// <15=> 32MHz/16 - -#ifndef NRFX_QSPI_CONFIG_FREQUENCY -#define NRFX_QSPI_CONFIG_FREQUENCY 15 -#endif - -// NRFX_QSPI_PIN_SCK - SCK pin value. -#ifndef NRFX_QSPI_PIN_SCK -#define NRFX_QSPI_PIN_SCK NRF_QSPI_PIN_NOT_CONNECTED -#endif - -// NRFX_QSPI_PIN_CSN - CSN pin value. -#ifndef NRFX_QSPI_PIN_CSN -#define NRFX_QSPI_PIN_CSN NRF_QSPI_PIN_NOT_CONNECTED -#endif - -// NRFX_QSPI_PIN_IO0 - IO0 pin value. -#ifndef NRFX_QSPI_PIN_IO0 -#define NRFX_QSPI_PIN_IO0 NRF_QSPI_PIN_NOT_CONNECTED -#endif - -// NRFX_QSPI_PIN_IO1 - IO1 pin value. -#ifndef NRFX_QSPI_PIN_IO1 -#define NRFX_QSPI_PIN_IO1 NRF_QSPI_PIN_NOT_CONNECTED -#endif - -// NRFX_QSPI_PIN_IO2 - IO2 pin value. -#ifndef NRFX_QSPI_PIN_IO2 -#define NRFX_QSPI_PIN_IO2 NRF_QSPI_PIN_NOT_CONNECTED -#endif - -// NRFX_QSPI_PIN_IO3 - IO3 pin value. -#ifndef NRFX_QSPI_PIN_IO3 -#define NRFX_QSPI_PIN_IO3 NRF_QSPI_PIN_NOT_CONNECTED -#endif - -// NRFX_QSPI_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_QSPI_CONFIG_IRQ_PRIORITY -#define NRFX_QSPI_CONFIG_IRQ_PRIORITY 7 -#endif - -// - -// NRFX_RNG_ENABLED - nrfx_rng - RNG peripheral driver -//========================================================== -#ifndef NRFX_RNG_ENABLED -#define NRFX_RNG_ENABLED 1 -#endif -// NRFX_RNG_CONFIG_ERROR_CORRECTION - Error correction - - -#ifndef NRFX_RNG_CONFIG_ERROR_CORRECTION -#define NRFX_RNG_CONFIG_ERROR_CORRECTION 1 -#endif - -// NRFX_RNG_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_RNG_CONFIG_IRQ_PRIORITY -#define NRFX_RNG_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_RNG_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_RNG_CONFIG_LOG_ENABLED -#define NRFX_RNG_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_RNG_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_RNG_CONFIG_LOG_LEVEL -#define NRFX_RNG_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_RNG_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_RNG_CONFIG_INFO_COLOR -#define NRFX_RNG_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_RNG_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_RNG_CONFIG_DEBUG_COLOR -#define NRFX_RNG_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_RTC_ENABLED - nrfx_rtc - RTC peripheral driver -//========================================================== -#ifndef NRFX_RTC_ENABLED -#define NRFX_RTC_ENABLED 1 -#endif -// NRFX_RTC0_ENABLED - Enable RTC0 instance - - -#ifndef NRFX_RTC0_ENABLED -#define NRFX_RTC0_ENABLED 1 -#endif - -// NRFX_RTC1_ENABLED - Enable RTC1 instance - - -#ifndef NRFX_RTC1_ENABLED -#define NRFX_RTC1_ENABLED 1 -#endif - -// NRFX_RTC2_ENABLED - Enable RTC2 instance - - -#ifndef NRFX_RTC2_ENABLED -#define NRFX_RTC2_ENABLED 1 -#endif - -// NRFX_RTC_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt -#ifndef NRFX_RTC_MAXIMUM_LATENCY_US -#define NRFX_RTC_MAXIMUM_LATENCY_US 2000 -#endif - -// NRFX_RTC_DEFAULT_CONFIG_FREQUENCY - Frequency <16-32768> - - -#ifndef NRFX_RTC_DEFAULT_CONFIG_FREQUENCY -#define NRFX_RTC_DEFAULT_CONFIG_FREQUENCY 32768 -#endif - -// NRFX_RTC_DEFAULT_CONFIG_RELIABLE - Ensures safe compare event triggering - - -#ifndef NRFX_RTC_DEFAULT_CONFIG_RELIABLE -#define NRFX_RTC_DEFAULT_CONFIG_RELIABLE 0 -#endif - -// NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_RTC_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_RTC_CONFIG_LOG_ENABLED -#define NRFX_RTC_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_RTC_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_RTC_CONFIG_LOG_LEVEL -#define NRFX_RTC_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_RTC_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_RTC_CONFIG_INFO_COLOR -#define NRFX_RTC_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_RTC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_RTC_CONFIG_DEBUG_COLOR -#define NRFX_RTC_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_SAADC_ENABLED - nrfx_saadc - SAADC peripheral driver -//========================================================== -#ifndef NRFX_SAADC_ENABLED -#define NRFX_SAADC_ENABLED 1 -#endif -// NRFX_SAADC_CONFIG_RESOLUTION - Resolution - -// <0=> 8 bit -// <1=> 10 bit -// <2=> 12 bit -// <3=> 14 bit - -#ifndef NRFX_SAADC_CONFIG_RESOLUTION -#define NRFX_SAADC_CONFIG_RESOLUTION 1 -#endif - -// NRFX_SAADC_CONFIG_OVERSAMPLE - Sample period - -// <0=> Disabled -// <1=> 2x -// <2=> 4x -// <3=> 8x -// <4=> 16x -// <5=> 32x -// <6=> 64x -// <7=> 128x -// <8=> 256x - -#ifndef NRFX_SAADC_CONFIG_OVERSAMPLE -#define NRFX_SAADC_CONFIG_OVERSAMPLE 0 -#endif - -// NRFX_SAADC_CONFIG_LP_MODE - Enabling low power mode - - -#ifndef NRFX_SAADC_CONFIG_LP_MODE -#define NRFX_SAADC_CONFIG_LP_MODE 0 -#endif - -// NRFX_SAADC_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_SAADC_CONFIG_IRQ_PRIORITY -#define NRFX_SAADC_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_SAADC_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED -#define NRFX_SAADC_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_SAADC_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL -#define NRFX_SAADC_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_SAADC_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SAADC_CONFIG_INFO_COLOR -#define NRFX_SAADC_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_SAADC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SAADC_CONFIG_DEBUG_COLOR -#define NRFX_SAADC_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_SPIM_ENABLED - nrfx_spim - SPIM peripheral driver -//========================================================== -#ifndef NRFX_SPIM_ENABLED -#define NRFX_SPIM_ENABLED 1 -#endif -// NRFX_SPIM0_ENABLED - Enable SPIM0 instance - - -#ifndef NRFX_SPIM0_ENABLED -#define NRFX_SPIM0_ENABLED 1 -#endif - -// NRFX_SPIM1_ENABLED - Enable SPIM1 instance - - -#ifndef NRFX_SPIM1_ENABLED -#define NRFX_SPIM1_ENABLED 1 -#endif - -// NRFX_SPIM2_ENABLED - Enable SPIM2 instance - - -#ifndef NRFX_SPIM2_ENABLED -#define NRFX_SPIM2_ENABLED 1 -#endif - -// NRFX_SPIM3_ENABLED - Enable SPIM3 instance - - -#ifndef NRFX_SPIM3_ENABLED -#define NRFX_SPIM3_ENABLED 1 -#endif - -// NRFX_SPIM_EXTENDED_ENABLED - Enable extended SPIM features - - -#ifndef NRFX_SPIM_EXTENDED_ENABLED -#define NRFX_SPIM_EXTENDED_ENABLED 0 -#endif - -// NRFX_SPIM_MISO_PULL_CFG - MISO pin pull configuration. - -// <0=> NRF_GPIO_PIN_NOPULL -// <1=> NRF_GPIO_PIN_PULLDOWN -// <3=> NRF_GPIO_PIN_PULLUP - -#ifndef NRFX_SPIM_MISO_PULL_CFG -#define NRFX_SPIM_MISO_PULL_CFG 1 -#endif - -// NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_SPIM_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED -#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_SPIM_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL -#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_SPIM_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SPIM_CONFIG_INFO_COLOR -#define NRFX_SPIM_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_SPIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SPIM_CONFIG_DEBUG_COLOR -#define NRFX_SPIM_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED - Enables nRF52840 anomaly 198 workaround for SPIM3. - - -// See more in the Errata document located at -// https://infocenter.nordicsemi.com/ - -#ifndef NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED -#define NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED 0 -#endif - -// - -// NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver -//========================================================== -#ifndef NRFX_SPIS_ENABLED -#define NRFX_SPIS_ENABLED 1 -#endif -// NRFX_SPIS0_ENABLED - Enable SPIS0 instance - - -#ifndef NRFX_SPIS0_ENABLED -#define NRFX_SPIS0_ENABLED 1 -#endif - -// NRFX_SPIS1_ENABLED - Enable SPIS1 instance - - -#ifndef NRFX_SPIS1_ENABLED -#define NRFX_SPIS1_ENABLED 1 -#endif - -// NRFX_SPIS2_ENABLED - Enable SPIS2 instance - - -#ifndef NRFX_SPIS2_ENABLED -#define NRFX_SPIS2_ENABLED 1 -#endif - -// NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_SPIS_DEFAULT_DEF - SPIS default DEF character <0-255> - - -#ifndef NRFX_SPIS_DEFAULT_DEF -#define NRFX_SPIS_DEFAULT_DEF 255 -#endif - -// NRFX_SPIS_DEFAULT_ORC - SPIS default ORC character <0-255> - - -#ifndef NRFX_SPIS_DEFAULT_ORC -#define NRFX_SPIS_DEFAULT_ORC 255 -#endif - -// NRFX_SPIS_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED -#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_SPIS_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL -#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_SPIS_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SPIS_CONFIG_INFO_COLOR -#define NRFX_SPIS_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_SPIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SPIS_CONFIG_DEBUG_COLOR -#define NRFX_SPIS_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_SPI_ENABLED - nrfx_spi - SPI peripheral driver -//========================================================== -#ifndef NRFX_SPI_ENABLED -#define NRFX_SPI_ENABLED 1 -#endif -// NRFX_SPI0_ENABLED - Enable SPI0 instance - - -#ifndef NRFX_SPI0_ENABLED -#define NRFX_SPI0_ENABLED 1 -#endif - -// NRFX_SPI1_ENABLED - Enable SPI1 instance - - -#ifndef NRFX_SPI1_ENABLED -#define NRFX_SPI1_ENABLED 1 -#endif - -// NRFX_SPI2_ENABLED - Enable SPI2 instance - - -#ifndef NRFX_SPI2_ENABLED -#define NRFX_SPI2_ENABLED 1 -#endif - -// NRFX_SPI_MISO_PULL_CFG - MISO pin pull configuration. - -// <0=> NRF_GPIO_PIN_NOPULL -// <1=> NRF_GPIO_PIN_PULLDOWN -// <3=> NRF_GPIO_PIN_PULLUP - -#ifndef NRFX_SPI_MISO_PULL_CFG -#define NRFX_SPI_MISO_PULL_CFG 1 -#endif - -// NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_SPI_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_SPI_CONFIG_LOG_ENABLED -#define NRFX_SPI_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_SPI_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_SPI_CONFIG_LOG_LEVEL -#define NRFX_SPI_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_SPI_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SPI_CONFIG_INFO_COLOR -#define NRFX_SPI_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_SPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SPI_CONFIG_DEBUG_COLOR -#define NRFX_SPI_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_SWI_ENABLED - nrfx_swi - SWI/EGU peripheral allocator -//========================================================== -#ifndef NRFX_SWI_ENABLED -#define NRFX_SWI_ENABLED 1 -#endif -// NRFX_EGU_ENABLED - Enable EGU support - - -#ifndef NRFX_EGU_ENABLED -#define NRFX_EGU_ENABLED 0 -#endif - -// NRFX_SWI0_DISABLED - Exclude SWI0 from being utilized by the driver - - -#ifndef NRFX_SWI0_DISABLED -#define NRFX_SWI0_DISABLED 0 -#endif - -// NRFX_SWI1_DISABLED - Exclude SWI1 from being utilized by the driver - - -#ifndef NRFX_SWI1_DISABLED -#define NRFX_SWI1_DISABLED 0 -#endif - -// NRFX_SWI2_DISABLED - Exclude SWI2 from being utilized by the driver - - -#ifndef NRFX_SWI2_DISABLED -#define NRFX_SWI2_DISABLED 0 -#endif - -// NRFX_SWI3_DISABLED - Exclude SWI3 from being utilized by the driver - - -#ifndef NRFX_SWI3_DISABLED -#define NRFX_SWI3_DISABLED 0 -#endif - -// NRFX_SWI4_DISABLED - Exclude SWI4 from being utilized by the driver - - -#ifndef NRFX_SWI4_DISABLED -#define NRFX_SWI4_DISABLED 0 -#endif - -// NRFX_SWI5_DISABLED - Exclude SWI5 from being utilized by the driver - - -#ifndef NRFX_SWI5_DISABLED -#define NRFX_SWI5_DISABLED 0 -#endif - -// NRFX_SWI_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_SWI_CONFIG_LOG_ENABLED -#define NRFX_SWI_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_SWI_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_SWI_CONFIG_LOG_LEVEL -#define NRFX_SWI_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_SWI_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SWI_CONFIG_INFO_COLOR -#define NRFX_SWI_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_SWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SWI_CONFIG_DEBUG_COLOR -#define NRFX_SWI_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_SYSTICK_ENABLED - nrfx_systick - ARM(R) SysTick driver - - -#ifndef NRFX_SYSTICK_ENABLED -#define NRFX_SYSTICK_ENABLED 1 -#endif - -// NRFX_TIMER_ENABLED - nrfx_timer - TIMER periperal driver -//========================================================== -#ifndef NRFX_TIMER_ENABLED -#define NRFX_TIMER_ENABLED 1 -#endif -// NRFX_TIMER0_ENABLED - Enable TIMER0 instance - - -#ifndef NRFX_TIMER0_ENABLED -#define NRFX_TIMER0_ENABLED 1 -#endif - -// NRFX_TIMER1_ENABLED - Enable TIMER1 instance - - -#ifndef NRFX_TIMER1_ENABLED -#define NRFX_TIMER1_ENABLED 1 -#endif - -// NRFX_TIMER2_ENABLED - Enable TIMER2 instance - - -#ifndef NRFX_TIMER2_ENABLED -#define NRFX_TIMER2_ENABLED 1 -#endif - -// NRFX_TIMER3_ENABLED - Enable TIMER3 instance - - -#ifndef NRFX_TIMER3_ENABLED -#define NRFX_TIMER3_ENABLED 1 -#endif - -// NRFX_TIMER4_ENABLED - Enable TIMER4 instance - - -#ifndef NRFX_TIMER4_ENABLED -#define NRFX_TIMER4_ENABLED 1 -#endif - -// NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY - Timer frequency if in Timer mode - -// <0=> 16 MHz -// <1=> 8 MHz -// <2=> 4 MHz -// <3=> 2 MHz -// <4=> 1 MHz -// <5=> 500 kHz -// <6=> 250 kHz -// <7=> 125 kHz -// <8=> 62.5 kHz -// <9=> 31.25 kHz - -#ifndef NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY -#define NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY 0 -#endif - -// NRFX_TIMER_DEFAULT_CONFIG_MODE - Timer mode or operation - -// <0=> Timer -// <1=> Counter - -#ifndef NRFX_TIMER_DEFAULT_CONFIG_MODE -#define NRFX_TIMER_DEFAULT_CONFIG_MODE 0 -#endif - -// NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH - Timer counter bit width - -// <0=> 16 bit -// <1=> 8 bit -// <2=> 24 bit -// <3=> 32 bit - -#ifndef NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH -#define NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH 0 -#endif - -// NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_TIMER_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED -#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_TIMER_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL -#define NRFX_TIMER_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TIMER_CONFIG_INFO_COLOR -#define NRFX_TIMER_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TIMER_CONFIG_DEBUG_COLOR -#define NRFX_TIMER_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_TWIM_ENABLED - nrfx_twim - TWIM peripheral driver -//========================================================== -#ifndef NRFX_TWIM_ENABLED -#define NRFX_TWIM_ENABLED 1 -#endif -// NRFX_TWIM0_ENABLED - Enable TWIM0 instance - - -#ifndef NRFX_TWIM0_ENABLED -#define NRFX_TWIM0_ENABLED 1 -#endif - -// NRFX_TWIM1_ENABLED - Enable TWIM1 instance - - -#ifndef NRFX_TWIM1_ENABLED -#define NRFX_TWIM1_ENABLED 1 -#endif - -// NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY - Frequency - -// <26738688=> 100k -// <67108864=> 250k -// <104857600=> 400k - -#ifndef NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY -#define NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY 26738688 -#endif - -// NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit - - -#ifndef NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT -#define NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 -#endif - -// NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_TWIM_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED -#define NRFX_TWIM_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_TWIM_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL -#define NRFX_TWIM_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_TWIM_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TWIM_CONFIG_INFO_COLOR -#define NRFX_TWIM_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_TWIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TWIM_CONFIG_DEBUG_COLOR -#define NRFX_TWIM_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_TWIS_ENABLED - nrfx_twis - TWIS peripheral driver -//========================================================== -#ifndef NRFX_TWIS_ENABLED -#define NRFX_TWIS_ENABLED 1 -#endif -// NRFX_TWIS0_ENABLED - Enable TWIS0 instance - - -#ifndef NRFX_TWIS0_ENABLED -#define NRFX_TWIS0_ENABLED 1 -#endif - -// NRFX_TWIS1_ENABLED - Enable TWIS1 instance - - -#ifndef NRFX_TWIS1_ENABLED -#define NRFX_TWIS1_ENABLED 1 -#endif - -// NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once - - -// Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code. - -#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY -#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 -#endif - -// NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode - - -// Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources. - -#ifndef NRFX_TWIS_NO_SYNC_MODE -#define NRFX_TWIS_NO_SYNC_MODE 0 -#endif - -// NRFX_TWIS_DEFAULT_CONFIG_ADDR0 - Address0 -#ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR0 -#define NRFX_TWIS_DEFAULT_CONFIG_ADDR0 0 -#endif - -// NRFX_TWIS_DEFAULT_CONFIG_ADDR1 - Address1 -#ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR1 -#define NRFX_TWIS_DEFAULT_CONFIG_ADDR1 0 -#endif - -// NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL - SCL pin pull configuration - -// <0=> Disabled -// <1=> Pull down -// <3=> Pull up - -#ifndef NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL -#define NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL 0 -#endif - -// NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL - SDA pin pull configuration - -// <0=> Disabled -// <1=> Pull down -// <3=> Pull up - -#ifndef NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL -#define NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL 0 -#endif - -// NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_TWIS_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED -#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_TWIS_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL -#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_TWIS_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TWIS_CONFIG_INFO_COLOR -#define NRFX_TWIS_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_TWIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TWIS_CONFIG_DEBUG_COLOR -#define NRFX_TWIS_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_TWI_ENABLED - nrfx_twi - TWI peripheral driver -//========================================================== -#ifndef NRFX_TWI_ENABLED -#define NRFX_TWI_ENABLED 1 -#endif -// NRFX_TWI0_ENABLED - Enable TWI0 instance - - -#ifndef NRFX_TWI0_ENABLED -#define NRFX_TWI0_ENABLED 1 -#endif - -// NRFX_TWI1_ENABLED - Enable TWI1 instance - - -#ifndef NRFX_TWI1_ENABLED -#define NRFX_TWI1_ENABLED 1 -#endif - -// NRFX_TWI_DEFAULT_CONFIG_FREQUENCY - Frequency - -// <26738688=> 100k -// <67108864=> 250k -// <104857600=> 400k - -#ifndef NRFX_TWI_DEFAULT_CONFIG_FREQUENCY -#define NRFX_TWI_DEFAULT_CONFIG_FREQUENCY 26738688 -#endif - -// NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit - - -#ifndef NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT -#define NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 -#endif - -// NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_TWI_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_TWI_CONFIG_LOG_ENABLED -#define NRFX_TWI_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_TWI_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_TWI_CONFIG_LOG_LEVEL -#define NRFX_TWI_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_TWI_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TWI_CONFIG_INFO_COLOR -#define NRFX_TWI_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_TWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_TWI_CONFIG_DEBUG_COLOR -#define NRFX_TWI_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_UARTE_ENABLED - nrfx_uarte - UARTE peripheral driver -//========================================================== -#ifndef NRFX_UARTE_ENABLED -#define NRFX_UARTE_ENABLED 1 -#endif -// NRFX_UARTE0_ENABLED - Enable UARTE0 instance -#ifndef NRFX_UARTE0_ENABLED -#define NRFX_UARTE0_ENABLED 1 -#endif - -// NRFX_UARTE1_ENABLED - Enable UARTE1 instance -#ifndef NRFX_UARTE1_ENABLED -#define NRFX_UARTE1_ENABLED 1 -#endif - -// NRFX_UARTE_DEFAULT_CONFIG_HWFC - Hardware Flow Control - -// <0=> Disabled -// <1=> Enabled - -#ifndef NRFX_UARTE_DEFAULT_CONFIG_HWFC -#define NRFX_UARTE_DEFAULT_CONFIG_HWFC 0 -#endif - -// NRFX_UARTE_DEFAULT_CONFIG_PARITY - Parity - -// <0=> Excluded -// <14=> Included - -#ifndef NRFX_UARTE_DEFAULT_CONFIG_PARITY -#define NRFX_UARTE_DEFAULT_CONFIG_PARITY 0 -#endif - -// NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE - Default Baudrate - -// <323584=> 1200 baud -// <643072=> 2400 baud -// <1290240=> 4800 baud -// <2576384=> 9600 baud -// <3862528=> 14400 baud -// <5152768=> 19200 baud -// <7716864=> 28800 baud -// <8388608=> 31250 baud -// <10289152=> 38400 baud -// <15007744=> 56000 baud -// <15400960=> 57600 baud -// <20615168=> 76800 baud -// <30801920=> 115200 baud -// <61865984=> 230400 baud -// <67108864=> 250000 baud -// <121634816=> 460800 baud -// <251658240=> 921600 baud -// <268435456=> 1000000 baud - -#ifndef NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE -#define NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE 30801920 -#endif - -// NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_UARTE_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED -#define NRFX_UARTE_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_UARTE_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL -#define NRFX_UARTE_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_UARTE_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_UARTE_CONFIG_INFO_COLOR -#define NRFX_UARTE_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_UARTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_UARTE_CONFIG_DEBUG_COLOR -#define NRFX_UARTE_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_UART_ENABLED - nrfx_uart - UART peripheral driver -//========================================================== -#ifndef NRFX_UART_ENABLED -#define NRFX_UART_ENABLED 1 -#endif -// NRFX_UART0_ENABLED - Enable UART0 instance -#ifndef NRFX_UART0_ENABLED -#define NRFX_UART0_ENABLED 1 -#endif - -// NRFX_UART_DEFAULT_CONFIG_HWFC - Hardware Flow Control - -// <0=> Disabled -// <1=> Enabled - -#ifndef NRFX_UART_DEFAULT_CONFIG_HWFC -#define NRFX_UART_DEFAULT_CONFIG_HWFC 0 -#endif - -// NRFX_UART_DEFAULT_CONFIG_PARITY - Parity - -// <0=> Excluded -// <14=> Included - -#ifndef NRFX_UART_DEFAULT_CONFIG_PARITY -#define NRFX_UART_DEFAULT_CONFIG_PARITY 0 -#endif - -// NRFX_UART_DEFAULT_CONFIG_BAUDRATE - Default Baudrate - -// <323584=> 1200 baud -// <643072=> 2400 baud -// <1290240=> 4800 baud -// <2576384=> 9600 baud -// <3866624=> 14400 baud -// <5152768=> 19200 baud -// <7729152=> 28800 baud -// <8388608=> 31250 baud -// <10309632=> 38400 baud -// <15007744=> 56000 baud -// <15462400=> 57600 baud -// <20615168=> 76800 baud -// <30924800=> 115200 baud -// <61845504=> 230400 baud -// <67108864=> 250000 baud -// <123695104=> 460800 baud -// <247386112=> 921600 baud -// <268435456=> 1000000 baud - -#ifndef NRFX_UART_DEFAULT_CONFIG_BAUDRATE -#define NRFX_UART_DEFAULT_CONFIG_BAUDRATE 30924800 -#endif - -// NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_UART_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_UART_CONFIG_LOG_ENABLED -#define NRFX_UART_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_UART_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_UART_CONFIG_LOG_LEVEL -#define NRFX_UART_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_UART_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_UART_CONFIG_INFO_COLOR -#define NRFX_UART_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_UART_CONFIG_DEBUG_COLOR -#define NRFX_UART_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// NRFX_WDT_ENABLED - nrfx_wdt - WDT peripheral driver -//========================================================== -#ifndef NRFX_WDT_ENABLED -#define NRFX_WDT_ENABLED 1 -#endif -// NRFX_WDT_CONFIG_BEHAVIOUR - WDT behavior in CPU SLEEP or HALT mode - -// <1=> Run in SLEEP, Pause in HALT -// <8=> Pause in SLEEP, Run in HALT -// <9=> Run in SLEEP and HALT -// <0=> Pause in SLEEP and HALT - -#ifndef NRFX_WDT_CONFIG_BEHAVIOUR -#define NRFX_WDT_CONFIG_BEHAVIOUR 1 -#endif - -// NRFX_WDT_CONFIG_RELOAD_VALUE - Reload value <15-4294967295> - - -#ifndef NRFX_WDT_CONFIG_RELOAD_VALUE -#define NRFX_WDT_CONFIG_RELOAD_VALUE 2000 -#endif - -// NRFX_WDT_CONFIG_IRQ_PRIORITY - Interrupt priority - -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_WDT_CONFIG_IRQ_PRIORITY -#define NRFX_WDT_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_WDT_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_WDT_CONFIG_LOG_ENABLED -#define NRFX_WDT_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_WDT_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_WDT_CONFIG_LOG_LEVEL -#define NRFX_WDT_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_WDT_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_WDT_CONFIG_INFO_COLOR -#define NRFX_WDT_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_WDT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_WDT_CONFIG_DEBUG_COLOR -#define NRFX_WDT_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - -// - -#endif // NRFX_CONFIG_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/templates/nrfx_glue.h b/bsp/boards/nrf52840/sdk/modules/nrfx/templates/nrfx_glue.h deleted file mode 100644 index 87769d8383..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/templates/nrfx_glue.h +++ /dev/null @@ -1,204 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_GLUE_H__ -#define NRFX_GLUE_H__ - -// THIS IS A TEMPLATE FILE. -// It should be copied to a suitable location within the host environment into -// which nrfx is integrated, and the following macros should be provided with -// appropriate implementations. -// And this comment should be removed from the customized file. - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_glue nrfx_glue.h - * @{ - * @ingroup nrfx - * - * @brief This file contains macros that should be implemented according to - * the needs of the host environment into which @em nrfx is integrated. - */ - -// Uncomment this line to use the standard MDK way of binding IRQ handlers -// at linking time. -//#include - -//------------------------------------------------------------------------------ - -/** - * @brief Macro for placing a runtime assertion. - * - * @param expression Expression to evaluate. - */ -#define NRFX_ASSERT(expression) - -/** - * @brief Macro for placing a compile time assertion. - * - * @param expression Expression to evaluate. - */ -#define NRFX_STATIC_ASSERT(expression) - -//------------------------------------------------------------------------------ - -/** - * @brief Macro for setting the priority of a specific IRQ. - * - * @param irq_number IRQ number. - * @param priority Priority to set. - */ -#define NRFX_IRQ_PRIORITY_SET(irq_number, priority) - -/** - * @brief Macro for enabling a specific IRQ. - * - * @param irq_number IRQ number. - */ -#define NRFX_IRQ_ENABLE(irq_number) - -/** - * @brief Macro for checking if a specific IRQ is enabled. - * - * @param irq_number IRQ number. - * - * @retval true If the IRQ is enabled. - * @retval false Otherwise. - */ -#define NRFX_IRQ_IS_ENABLED(irq_number) - -/** - * @brief Macro for disabling a specific IRQ. - * - * @param irq_number IRQ number. - */ -#define NRFX_IRQ_DISABLE(irq_number) - -/** - * @brief Macro for setting a specific IRQ as pending. - * - * @param irq_number IRQ number. - */ -#define NRFX_IRQ_PENDING_SET(irq_number) - -/** - * @brief Macro for clearing the pending status of a specific IRQ. - * - * @param irq_number IRQ number. - */ -#define NRFX_IRQ_PENDING_CLEAR(irq_number) - -/** - * @brief Macro for checking the pending status of a specific IRQ. - * - * @retval true If the IRQ is pending. - * @retval false Otherwise. - */ -#define NRFX_IRQ_IS_PENDING(irq_number) - -/** - * @brief Macro for entering into a critical section. - */ -#define NRFX_CRITICAL_SECTION_ENTER() - -/** - * @brief Macro for exiting from a critical section. - */ -#define NRFX_CRITICAL_SECTION_EXIT() - -//------------------------------------------------------------------------------ - -/** - * @brief When set to a non-zero value, this macro specifies that - * @ref nrfx_coredep_delay_us uses a precise DWT-based solution. - * A compilation error is generated if the DWT unit is not present - * in the SoC used. - */ -#define NRFX_DELAY_DWT_BASED 0 - -/** - * @brief Macro for delaying the code execution for at least the specified time. - * - * @param us_time Number of microseconds to wait. - */ -#define NRFX_DELAY_US(us_time) - -//------------------------------------------------------------------------------ - -/** - * @brief When set to a non-zero value, this macro specifies that the - * @ref nrfx_error_codes and the @ref nrfx_err_t type itself are defined - * in a customized way and the default definitions from @c - * should not be used. - */ -#define NRFX_CUSTOM_ERROR_CODES 0 - -//------------------------------------------------------------------------------ - -/** - * @brief Bitmask defining PPI channels reserved to be used outside of nrfx. - */ -#define NRFX_PPI_CHANNELS_USED 0 - -/** - * @brief Bitmask defining PPI groups reserved to be used outside of nrfx. - */ -#define NRFX_PPI_GROUPS_USED 0 - -/** - * @brief Bitmask defining SWI instances reserved to be used outside of nrfx. - */ -#define NRFX_SWI_USED 0 - -/** - * @brief Bitmask defining TIMER instances reserved to be used outside of nrfx. - */ -#define NRFX_TIMERS_USED 0 - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_GLUE_H__ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/templates/nrfx_log.h b/bsp/boards/nrf52840/sdk/modules/nrfx/templates/nrfx_log.h deleted file mode 100644 index b2943b7256..0000000000 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/templates/nrfx_log.h +++ /dev/null @@ -1,144 +0,0 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRFX_LOG_H__ -#define NRFX_LOG_H__ - -// THIS IS A TEMPLATE FILE. -// It should be copied to a suitable location within the host environment into -// which nrfx is integrated, and the following macros should be provided with -// appropriate implementations. -// And this comment should be removed from the customized file. - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_log nrfx_log.h - * @{ - * @ingroup nrfx - * - * @brief This file contains macros that should be implemented according to - * the needs of the host environment into which @em nrfx is integrated. - */ - -/** - * @brief Macro for logging a message with the severity level ERROR. - * - * @param format printf-style format string, optionally followed by arguments - * to be formatted and inserted in the resulting string. - */ -#define NRFX_LOG_ERROR(format, ...) - -/** - * @brief Macro for logging a message with the severity level WARNING. - * - * @param format printf-style format string, optionally followed by arguments - * to be formatted and inserted in the resulting string. - */ -#define NRFX_LOG_WARNING(format, ...) - -/** - * @brief Macro for logging a message with the severity level INFO. - * - * @param format printf-style format string, optionally followed by arguments - * to be formatted and inserted in the resulting string. - */ -#define NRFX_LOG_INFO(format, ...) - -/** - * @brief Macro for logging a message with the severity level DEBUG. - * - * @param format printf-style format string, optionally followed by arguments - * to be formatted and inserted in the resulting string. - */ -#define NRFX_LOG_DEBUG(format, ...) - - -/** - * @brief Macro for logging a memory dump with the severity level ERROR. - * - * @param[in] p_memory Pointer to the memory region to be dumped. - * @param[in] length Length of the memory region in bytes. - */ -#define NRFX_LOG_HEXDUMP_ERROR(p_memory, length) - -/** - * @brief Macro for logging a memory dump with the severity level WARNING. - * - * @param[in] p_memory Pointer to the memory region to be dumped. - * @param[in] length Length of the memory region in bytes. - */ -#define NRFX_LOG_HEXDUMP_WARNING(p_memory, length) - -/** - * @brief Macro for logging a memory dump with the severity level INFO. - * - * @param[in] p_memory Pointer to the memory region to be dumped. - * @param[in] length Length of the memory region in bytes. - */ -#define NRFX_LOG_HEXDUMP_INFO(p_memory, length) - -/** - * @brief Macro for logging a memory dump with the severity level DEBUG. - * - * @param[in] p_memory Pointer to the memory region to be dumped. - * @param[in] length Length of the memory region in bytes. - */ -#define NRFX_LOG_HEXDUMP_DEBUG(p_memory, length) - - -/** - * @brief Macro for getting the textual representation of a given error code. - * - * @param[in] error_code Error code. - * - * @return String containing the textual representation of the error code. - */ -#define NRFX_LOG_ERROR_STRING_GET(error_code) - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_LOG_H__ diff --git a/bsp/boards/nrf52840/spi.c b/bsp/boards/nrf52840/spi.c deleted file mode 100644 index fb16ccb644..0000000000 --- a/bsp/boards/nrf52840/spi.c +++ /dev/null @@ -1,116 +0,0 @@ -/** - * Author: Adam Sedmak (adam.sedmak@gmail.com) - * Company: Faculty of Electronics and Computing, Zagreb, Croatia - * Date: Apr 2018 - * Description: nRF52840-specific definition of the "spi" bsp module. - */ - -#include "sdk/components/boards/boards.h" -#include "sdk/modules/nrfx/drivers/include/nrfx_spi.h" - -#include "app_config.h" -#include "leds.h" -#include "spi.h" -#include "board.h" -#include "board_info.h" -#include "debugpins.h" - -#include -#include -#include - -//=========================== defines ========================================= - -#if BOARD_PCA10056 // nrf52840-DK - #define SPI_SS_PIN 33 ///< P1.01 - #define SPI_MISO_PIN 34 ///< P1.02 - #define SPI_MOSI_PIN 35 ///< P1.03 - #define SPI_SCK_PIN 36 ///< P1.04 -#endif -#if BOARD_PCA10059 // nrf52840-DONGLE - #define SPI_SS_PIN 02 - #define SPI_MISO_PIN 15 - #define SPI_MOSI_PIN 17 - #define SPI_SCK_PIN 20 -#endif - - -#define SPI_INSTANCE 0 ///< SPI instance index - - -//=========================== variables ======================================= - -static const nrfx_spi_t spi = NRFX_SPI_INSTANCE(SPI_INSTANCE); /**< SPI instance. */ -static volatile bool spi_xfer_done; /**< Flag used to indicate that SPI instance completed the transfer. */ - - -//=========================== prototypes ====================================== - -void spi_event_handler(nrfx_spi_evt_t const * p_event,void * p_context); - - -//=========================== public ========================================== - -void spi_init(void) { - nrfx_spi_config_t spi_config = NRFX_SPI_DEFAULT_CONFIG; - - spi_config.ss_pin = SPI_SS_PIN; - spi_config.miso_pin = SPI_MISO_PIN; - spi_config.mosi_pin = SPI_MOSI_PIN; - spi_config.sck_pin = SPI_SCK_PIN; - - if(NRF_SUCCESS != nrfx_spi_init(&spi, &spi_config, spi_event_handler, NULL)) - { - leds_error_blink(); - board_reset(); - } -} - - -void spi_txrx(uint8_t* bufTx, - uint16_t lenbufTx, - spi_return_t returnType, - uint8_t* bufRx, - uint16_t maxLenBufRx, - spi_first_t isFirst, - spi_last_t isLast) -{ - // Fill in transfer descriptor - nrfx_spi_xfer_desc_t nrfx_spi_xfer_desc; - - nrfx_spi_xfer_desc.p_tx_buffer = bufTx; - nrfx_spi_xfer_desc.tx_length = lenbufTx; - nrfx_spi_xfer_desc.p_rx_buffer = bufRx; - nrfx_spi_xfer_desc.rx_length = maxLenBufRx; - - memset(bufRx, 0, maxLenBufRx); - - spi_xfer_done = false; - - if (NRFX_SUCCESS != nrfx_spi_xfer(&spi, &nrfx_spi_xfer_desc, 0)) { - leds_error_blink(); - } - - while (!spi_xfer_done) { - board_sleep(); - } -} - - -// interrupt handlers -kick_scheduler_t spi_isr(void) { - return DO_NOT_KICK_SCHEDULER; -} - - -//=========================== private ========================================= - -/** - * @brief SPI user event handler. - * @param event - */ -void spi_event_handler(nrfx_spi_evt_t const * p_event, - void * p_context) -{ - spi_xfer_done = true; -} diff --git a/bsp/boards/nrf52840/tools/flash.bat b/bsp/boards/nrf52840/tools/flash.bat deleted file mode 100644 index b117b72e8f..0000000000 --- a/bsp/boards/nrf52840/tools/flash.bat +++ /dev/null @@ -1,10 +0,0 @@ -@echo off - -rem Erase board ------------------------------------------ -nrfjprog.exe --family nRF52 -e - -rem Program board ---------------------------------------- -nrfjprog.exe --family nRF52 --program %1 - -rem Reset board ------------------------------------------ -nrfjprog.exe --family nRF52 -r diff --git a/bsp/boards/nrf52840/tools/flash.sh b/bsp/boards/nrf52840/tools/flash.sh deleted file mode 100644 index 571184eeb2..0000000000 --- a/bsp/boards/nrf52840/tools/flash.sh +++ /dev/null @@ -1,18 +0,0 @@ -#!/bin/bash - -if [ -d "./bsp/boards/nrf52840/tools/nrfjprog" ]; then - - echo -e "\n\t FLASHING $1 to nrf52840dk\n" - - ./bsp/boards/nrf52840/tools/nrfjprog/nrfjprog -f nrf52 --program $1 --sectorerase - ./bsp/boards/nrf52840/tools/nrfjprog/nrfjprog -f nrf52 --reset - -else - - echo -e "\n\n[WARNING]\n" - echo -e "To be able to flash the Nordic nRF52840 Development Kit you will need to install" - echo -e "both the latest JLink Software (https://www.segger.com/downloads/jlink/) and" - echo -e "nRF5x-Command-Line-Tools (https://www.nordicsemi.com/eng/Products/nRF52840#Downloads)" - echo -e "into the directory './bsp/boards/nrf52840/tools/nrfjprog'.\n" - -fi diff --git a/bsp/boards/nrf52840/uart.c b/bsp/boards/nrf52840/uart.c deleted file mode 100644 index e857732cb6..0000000000 --- a/bsp/boards/nrf52840/uart.c +++ /dev/null @@ -1,230 +0,0 @@ - /** - * Author: Tamas Harczos (tamas.harczos@imms.de) - * Date: Apr 2018 - * Description: nRF52840-specific definition of the "uart" bsp module. - */ - - -#include "sdk/components/boards/boards.h" -#include "sdk/components/libraries/uart/app_uart.h" -#include "sdk/modules/nrfx/hal/nrf_uart.h" -#include "sdk/integration/nrfx/legacy/nrf_drv_clock.h" -#include "sdk/modules/nrfx/drivers/include/nrfx_systick.h" -#include "sdk/modules/nrfx/mdk/nrf52840_bitfields.h" -#include "sdk/modules/nrfx/mdk/nrf52840.h" - -#include "board.h" -#include "leds.h" -#include "debugpins.h" -#include "uart.h" - -#include -#include -#include - -#ifndef UART_DISABLED - -//=========================== defines ========================================= - -// see sdk/config/nrf52840/config/sdk_config.h for UART related settings -#if BOARD_PCA10059 -// nrf52840-DONGLE -#define RX_PIN_NUMBER 47 -#define TX_PIN_NUMBER 45 -#define RTS_PIN_NUMBER UART_PIN_DISCONNECTED -#define CTS_PIN_NUMBER UART_PIN_DISCONNECTED -#endif - -#define NRF_GPIO_PIN_MAP(port, pin) (((port) << 5) | ((pin) & 0x1F)) - -#define UART_RX_PIN NRF_GPIO_PIN_MAP(0,8) // p0.08 -#define UART_TX_PIN NRF_GPIO_PIN_MAP(0,6) // p0.06 -#define UART_CTS_PIN NRF_GPIO_PIN_MAP(0,7) // p0.07 -#define UART_RTS_PIN NRF_GPIO_PIN_MAP(0,5) // p0.05 - -#define UART_BAUDRATE_115200 0x01D7E000 // Baud 115200 -#define UART_BAUDRATE_1M 0x10000000 // Baud 1M - -#define UART_INTEN_RXDRDY_POS 2 -#define UART_INTEN_TXDRDY_POS 7 - -#define UART_CONFIG_PARITY 0 // excluded -#define UART_CONFIG_PARITY_POS 1 -#define UART_CONFIG_HWFC 0 -#define UART_CONFIG_HWFC_POS 0 - -//=========================== variables ======================================= - -typedef struct -{ - uart_tx_cbt txCb; - uart_rx_cbt rxCb; - bool fXonXoffEscaping; - uint8_t xonXoffEscapedByte; -} uart_vars_t; - -uart_vars_t uart_vars; - -//=========================== prototypes ====================================== - -static void uart_event_handler(app_uart_evt_t * p_event); - -//=========================== public ========================================== - -void uart_init(void) { - // reset local variables - memset(&uart_vars,0,sizeof(uart_vars_t)); - - // UART baudrate accuracy depends on HFCLK - // see radio.c for details on enabling HFCLK - #define hfclk_request_timeout_us 380 - { - nrfx_systick_state_t systick_time; - nrfx_systick_get(&systick_time); - nrf_drv_clock_hfclk_request(NULL); - while ((!nrf_drv_clock_hfclk_is_running()) && (!nrfx_systick_test(&systick_time, hfclk_request_timeout_us))) {} - } - - // configure txd and rxd pin - NRF_P0->OUTSET = 1 << UART_TX_PIN; - - // tx pin configured as output - NRF_P0->PIN_CNF[UART_TX_PIN] = \ - ((uint32_t)GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos) - | ((uint32_t)GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) - | ((uint32_t)GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) - | ((uint32_t)GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) - | ((uint32_t)GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos); - - // rx pin configured as input - NRF_P0->PIN_CNF[UART_RX_PIN] = \ - ((uint32_t)GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) - | ((uint32_t)GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) - | ((uint32_t)GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) - | ((uint32_t)GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) - | ((uint32_t)GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos); - - // configure uart - NRF_UART0->BAUDRATE = (uint32_t)(UART_BAUDRATE_115200); - NRF_UART0->CONFIG = - (uint32_t)(UART_CONFIG_PARITY << UART_CONFIG_PARITY_POS) - | (uint32_t)(UART_CONFIG_HWFC << UART_CONFIG_HWFC_POS); - NRF_UART0->PSEL.RXD = (uint32_t)UART_RX_PIN; - NRF_UART0->PSEL.TXD = (uint32_t)UART_TX_PIN; - - // enable UART rx done ready and tx done ready interrupts - - NRF_UART0->INTENSET = - (uint32_t)(1<ISER[((uint32_t)UARTE0_UART0_IRQn)>>5] = - ((uint32_t)1) << ( ((uint32_t)UARTE0_UART0_IRQn) & 0x1f); - - // enable uart - NRF_UART0->ENABLE = (uint32_t)UART_ENABLE_ENABLE_Enabled; - - // start to tx and rx - NRF_UART0->TASKS_STARTTX = (uint32_t)1; - NRF_UART0->TASKS_STARTRX = (uint32_t)1; -} - -void uart_setCallbacks(uart_tx_cbt txCb, uart_rx_cbt rxCb) { - uart_vars.txCb = txCb; - uart_vars.rxCb = rxCb; -} - -void uart_enableInterrupts(void) { - - NRF_UART0->INTENSET = - (uint32_t)(1<EVENTS_RXDRDY = (uint32_t)0; -} - -void uart_clearTxInterrupts(void) { - - NRF_UART0->EVENTS_TXDRDY = (uint32_t)0; -} - -void uart_setCTS(bool state) { - - if (state==0x01) { - NRF_UART0->TXD = XON; - } else { - NRF_UART0->TXD = XOFF; - } -} - -void uart_writeByte(uint8_t byteToWrite){ - - if (byteToWrite==XON || byteToWrite==XOFF || byteToWrite==XONXOFF_ESCAPE) { - uart_vars.fXonXoffEscaping = 0x01; - uart_vars.xonXoffEscapedByte = byteToWrite; - NRF_UART0->TXD = XONXOFF_ESCAPE; - } else { - NRF_UART0->TXD = byteToWrite; - } -} - -uint8_t uart_readByte(void) { - - return NRF_UART0->RXD; -} - -//=========================== private ========================================= - -void UARTE0_UART0_IRQHandler(void) { - - debugpins_isr_set(); - - if (NRF_UART0->EVENTS_RXDRDY) { - - NRF_UART0->EVENTS_RXDRDY = (uint32_t)0; - uart_rx_isr(); - } - - - if (NRF_UART0->EVENTS_TXDRDY) { - - NRF_UART0->EVENTS_TXDRDY = (uint32_t)0; - uart_tx_isr(); - } - - debugpins_isr_clr(); -} - -//=========================== interrupt handlers ============================== - -kick_scheduler_t uart_tx_isr(void) { - - if (uart_vars.fXonXoffEscaping==0x01) { - uart_vars.fXonXoffEscaping = 0x00; - NRF_UART0->TXD = uart_vars.xonXoffEscapedByte^XONXOFF_MASK; - } else { - if (uart_vars.txCb != NULL){ - uart_vars.txCb(); - return KICK_SCHEDULER; - } - } - - return DO_NOT_KICK_SCHEDULER; -} - -kick_scheduler_t uart_rx_isr(void) { - - if (uart_vars.rxCb != NULL){ - uart_vars.rxCb(); - return KICK_SCHEDULER; - } - - return DO_NOT_KICK_SCHEDULER; -} -#endif // UART_DISABLED diff --git a/bsp/boards/nrf52840/SConscript b/bsp/boards/nrf52840_dk/SConscript similarity index 100% rename from bsp/boards/nrf52840/SConscript rename to bsp/boards/nrf52840_dk/SConscript diff --git a/bsp/boards/nrf52840_dk/adc.c b/bsp/boards/nrf52840_dk/adc.c new file mode 100644 index 0000000000..4dcb1be0c6 --- /dev/null +++ b/bsp/boards/nrf52840_dk/adc.c @@ -0,0 +1,28 @@ +/** + \brief Definition of the nrf52480 ADC driver. + \author Frank Senf , July 2018. + \author Tengfei Chang , April, 2023 +*/ + + +#include "adc.h" + + +//=========================== defines ========================================= + +//=========================== typedef ========================================= + +//=========================== variables ======================================= + +//=========================== prototype ======================================= + +//=========================== public ========================================== + +void adc_init(void) { +} + +uint16_t adc_read(void) { +} + + +//=========================== private ========================================= \ No newline at end of file diff --git a/bsp/boards/nrf52840/adc_sensor.h b/bsp/boards/nrf52840_dk/adc.h similarity index 65% rename from bsp/boards/nrf52840/adc_sensor.h rename to bsp/boards/nrf52840_dk/adc.h index c61c41b690..5fd68f4c0d 100644 --- a/bsp/boards/nrf52840/adc_sensor.h +++ b/bsp/boards/nrf52840_dk/adc.h @@ -3,8 +3,8 @@ \author Frank Senf , July 2018. */ -#ifndef __ADC_SENSOR_H__ -#define __ADC_SENSOR_H__ +#ifndef __ADC_H__ +#define __ADC_H__ #include "board_info.h" @@ -16,12 +16,7 @@ //=========================== prototypes ====================================== -bool adc_sens_init(void); -uint16_t adc_sens_read_battery(void); -float adc_sens_convert_battery(uint16_t raw); - -uint16_t adc_sens_read_temperature(void); -float adc_sens_convert_temperature(uint16_t cpu_temp_raw); - +void adc_init(void); +uint16_t adc_read(void); #endif // __ADC_SENSOR_H__ diff --git a/bsp/boards/nrf52840_dk/board.c b/bsp/boards/nrf52840_dk/board.c new file mode 100644 index 0000000000..af42929940 --- /dev/null +++ b/bsp/boards/nrf52840_dk/board.c @@ -0,0 +1,90 @@ +/** + * Author: Tamas Harczos (tamas.harczos@imms.de) + * Date: Apr 2018 + * Description: nRF52840-specific definition of the "board" bsp module. + */ + +#include "nrf52840.h" +#include "board.h" +#include "leds.h" +#include "sctimer.h" +#include "debugpins.h" +#include "uart.h" +#include "radio.h" +#include "spi.h" +#include "radio.h" +#include "sensors.h" +#include "i2c.h" + + +//=========================== variables ======================================= + +//=========================== prototypes ====================================== + +void enable_dcdc(void); + +//=========================== main ============================================ + +extern int mote_main(void); + +int main(void) { + return mote_main(); +} + + +//=========================== public ========================================== + +void board_init(void) { + + // start hfclock + NRF_CLOCK->EVENTS_HFCLKSTARTED = 0; + NRF_CLOCK->TASKS_HFCLKSTART = 1; + while (NRF_CLOCK->EVENTS_HFCLKSTARTED == 0); + + leds_init(); + debugpins_init(); + uart_init(); + sctimer_init(); + radio_init(); + + i2c_init(); + + // configure dcdc + enable_dcdc(); +} + +/** + * Puts the board to sleep + */ +void board_sleep(void) { + + __WFE(); + __WFE(); +} + +/** + * Resets the board + */ +void board_reset(void) { + + NVIC_SystemReset(); +} + +//=========================== private ========================================= + +void enable_dcdc(void) { + + uint32_t status; + + status = NRF_POWER->MAINREGSTATUS; + + if (status == 0) { + + while (NRF_POWER->DCDCEN == 0){ + // in normal voltage mode: PS1.2, page 59 + NRF_POWER->DCDCEN = (uint32_t)1; + } + } +} + +//=========================== interrupt handlers ============================== diff --git a/bsp/boards/nrf52840/board_info.h b/bsp/boards/nrf52840_dk/board_info.h similarity index 93% rename from bsp/boards/nrf52840/board_info.h rename to bsp/boards/nrf52840_dk/board_info.h index 0a00b98d55..9e4dc5debc 100644 --- a/bsp/boards/nrf52840/board_info.h +++ b/bsp/boards/nrf52840_dk/board_info.h @@ -9,18 +9,15 @@ #include #include - -#include "sdk/modules/nrfx/templates/nRF52840/nrfx_config.h" -#include "opendefs.h" - +#include "cmsis_gcc.h" //=========================== defines ========================================= //===== interrupt state #define INTERRUPT_DECLARATION() -#define DISABLE_INTERRUPTS() __asm volatile ("cpsid i" : : : "memory") ///< or use __disable_irq() from core_cmFunc.h -#define ENABLE_INTERRUPTS() __asm volatile ("cpsie i" : : : "memory") ///< or use __enable_irq() from core_cmFunc.h +#define DISABLE_INTERRUPTS() __disable_irq() +#define ENABLE_INTERRUPTS() __enable_irq() //===== timer @@ -30,6 +27,7 @@ #define PORT_SIGNED_INT_WIDTH int32_t #define PORT_TICS_PER_MS 33 #define PORT_US_PER_TICK 30 // number of us per 32kHz clock tick +#define PORT_MAX_TICKS_IN_SINGLE_CLOCK (uint32_t)(0x00ffffff) // on GINA, we use the comparatorA interrupt for the OS #define SCHEDULER_WAKEUP() @@ -39,6 +37,15 @@ // is not connected to a pin on the MSP which allows time capture. #define CAPTURE_TIME() + +// pin selection +#define NRF_GPIO_PIN_MAP(port, pin) (((port) << 5) | ((pin) & 0x1F)) + +// interrupt priority +#define RTC_PRIORITY 0 +#define RADIO_PRIORITY 0 +#define UART_PRIORITY 2 + //===== IEEE802154E timing // 1 clock tick = 30.5 us @@ -115,7 +122,7 @@ #define PORT_maxTxAckPrepare 13 // ~397us (measured 364us) // radio speed related - #define PORT_delayTx 1 // 305us (measured 282us; radio_txNow() to RADIO_IRQHandler() / NRF_RADIO->EVENTS_READY) + #define PORT_delayTx 8 // 305us (measured 282us; radio_txNow() to RADIO_IRQHandler() / NRF_RADIO->EVENTS_READY) #define PORT_delayRx 0 // ~153us (measured 147us; radio_rxNow() to RADIO_IRQHandler() / NRF_RADIO->EVENTS_READY) #endif #if BOARD_PCA10059 diff --git a/bsp/boards/nrf52840/cryptoengine.c b/bsp/boards/nrf52840_dk/cryptoengine.c similarity index 100% rename from bsp/boards/nrf52840/cryptoengine.c rename to bsp/boards/nrf52840_dk/cryptoengine.c diff --git a/bsp/boards/nrf52840_dk/debugpins.c b/bsp/boards/nrf52840_dk/debugpins.c new file mode 100644 index 0000000000..0a72531841 --- /dev/null +++ b/bsp/boards/nrf52840_dk/debugpins.c @@ -0,0 +1,153 @@ +/** +\brief nRF52840-specific definition of the "debugpins" bsp module. + +\author Tamas Harczos , April 2018. +\author Tengfei Chang , April 2023. +*/ + +#include "nrf52840.h" +#include "board_info.h" +#include "debugpins.h" + +//=========================== defines ========================================= + +// board debug PINS defines + +#define DEBUGPIN_FRAME NRF_GPIO_PIN_MAP(0,26) +#define DEBUGPIN_SLOT NRF_GPIO_PIN_MAP(0,27) +#define DEBUGPIN_FSM NRF_GPIO_PIN_MAP(0,28) +#define DEBUGPIN_TASK NRF_GPIO_PIN_MAP(0,29) +#define DEBUGPIN_ISR NRF_GPIO_PIN_MAP(0,30) +#define DEBUGPIN_RADIO NRF_GPIO_PIN_MAP(0,31) + +//=========================== variables ======================================= + +//=========================== prototypes ====================================== + +//=========================== public ========================================== + +void debugpins_init(void) { + + NRF_P0->DIRSET = 1<DIRSET = 1<DIRSET = 1<DIRSET = 1<DIRSET = 1<DIRSET = 1<OUTSET = 1<OUTCLR = 1<OUT & (1<OUTCLR = 1<OUTSET = 1<OUTSET = 1<OUTCLR = 1<OUT & (1<OUTCLR = 1<OUTSET = 1<OUTSET = 1<OUTCLR = 1<OUT & (1<OUTCLR = 1<OUTSET = 1<OUTSET = 1<OUTCLR = 1<OUT & (1<OUTCLR = 1<OUTSET = 1<OUTSET = 1<OUTCLR = 1<OUT & (1<OUTCLR = 1<OUTSET = 1<OUTSET = 1<OUTCLR = 1<OUT & (1<OUTCLR = 1<OUTSET = 1< +#include "eui64.h" //=========================== defines ========================================= //=========================== variables ======================================= -static uint32_t m_deviceID[2]= {0}; ///< this will be filled with the HW-unique serial number -static bool m_deviceIDRead= false; ///< will become true once the device ID has been read from the chip - //=========================== prototypes ====================================== //=========================== public ========================================== void eui64_get(uint8_t* addressToWrite) { - if (!m_deviceIDRead) { - // get ID from Nordic chip - m_deviceID[0]= NRF_FICR->DEVICEID[0]; - m_deviceID[1]= NRF_FICR->DEVICEID[1]; - m_deviceIDRead= true; - } + uint32_t tmp; + uint8_t i; - if (addressToWrite) { - memcpy(addressToWrite, m_deviceID, 2*sizeof(uint32_t)); + i = 0; + + // get ID from Nordic chip + tmp = NRF_FICR->DEVICEID[0]; + for (i=0;i<4;i++) { + addressToWrite[i] = (uint8_t)((tmp >> (i*8)) & 0x000000ff); + } + tmp = NRF_FICR->DEVICEID[1]; + for (i=0;i<4;i++) { + addressToWrite[i+4] = (uint8_t)((tmp >> (i*8)) & 0x000000ff); } } diff --git a/bsp/boards/nrf52840_dk/i2c.c b/bsp/boards/nrf52840_dk/i2c.c new file mode 100644 index 0000000000..ca39d40a7e --- /dev/null +++ b/bsp/boards/nrf52840_dk/i2c.c @@ -0,0 +1,183 @@ +/** +\brief nRF52840-specific definition of the "i2c" bsp module. + +\author Tengfei Chang , Nov 2021. +*/ + + +#include "nrf52840.h" +#include "nrf52840_bitfields.h" +#include "opendefs.h" +#include "i2c.h" + +//=========================== define ========================================== + +#define NRF_GPIO_PIN_MAP(port, pin) (((port) << 5) | ((pin) & 0x1F)) + +#define DOF10_SCL_PIN NRF_GPIO_PIN_MAP(1,0) // SCL signal pin P1.00 +#define DOF10_SDA_PIN NRF_GPIO_PIN_MAP(0,24) // SDA signal pin P0.24 +#define DOF10_FREQ 0x06400000 // frequency 6400000->400kbps + +#define TWIM_INTENSET_STOPPED_POS 1 +#define TWIM_INTENSET_ERROR_POS 9 +#define TWIM_INTENSET_SUSPENDED_POS 18 +#define TWIM_INTENSET_RXSTARTED_POS 19 +#define TWIM_INTENSET_TXSTARTED_POS 20 +#define TWIM_INTENSET_LASTRX_POS 23 +#define TWIM_INTENSET_LASTTX_POS 24 + +#define TWI_INT_ENABLED 0 + +//=========================== variables ======================================= + +typedef struct { + uint8_t i2c_addr; + +} i2c_vars_t; + +//=========================== prototypes ====================================== + +void nrf_gpio_cfg_input(uint32_t pin_number); + +//=========================== public ========================================== + +void i2c_init(void) { + + nrf_gpio_cfg_input(DOF10_SCL_PIN); + nrf_gpio_cfg_input(DOF10_SDA_PIN); + + // make sure TWIM0 is disabled before configuring the GPIO pins + NRF_TWIM0->ENABLE = (TWIM_ENABLE_ENABLE_Disabled << TWIM_ENABLE_ENABLE_Pos); + + NRF_TWIM0->PSEL.SCL = DOF10_SCL_PIN; + NRF_TWIM0->PSEL.SDA = DOF10_SDA_PIN; + + NRF_TWIM0->FREQUENCY = DOF10_FREQ; + + NRF_TWIM0->SHORTS = \ + TWIM_SHORTS_LASTTX_STOP_Msk | TWIM_SHORTS_LASTRX_STOP_Msk; + +#if TWI_INT_ENABLED == 1 + + NRF_TWIM0->INTENSET = + (((uint32_t)0) << TWIM_INTENSET_STOPPED_POS) + | (((uint32_t)0) << TWIM_INTENSET_ERROR_POS) + | (((uint32_t)0) << TWIM_INTENSET_SUSPENDED_POS) + | (((uint32_t)0) << TWIM_INTENSET_RXSTARTED_POS) + | (((uint32_t)0) << TWIM_INTENSET_TXSTARTED_POS) + | (((uint32_t)0) << TWIM_INTENSET_LASTRX_POS) + | (((uint32_t)0) << TWIM_INTENSET_LASTTX_POS); + + // set priority and enable interrupt in NVIC + NVIC->IP[((uint32_t)SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn)] = + (uint8_t)( + ( + I2C_PRIORITY << (8 - __NVIC_PRIO_BITS) + ) & (uint32_t)0xff + ); + NVIC->ISER[((uint32_t)SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn)>>5] = + ((uint32_t)1) << ( ((uint32_t)SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn) & 0x1f); + +#endif + + NRF_TWIM0->ENABLE = (TWIM_ENABLE_ENABLE_Enabled << TWIM_ENABLE_ENABLE_Pos); +} + +void i2c_set_addr(uint8_t address) { + + NRF_TWIM0->ADDRESS = address; +} + + +uint32_t i2c_read_bytes(uint8_t address, uint8_t* buffer, uint32_t length) { + + uint8_t tx_buffer[1]; + + // ---- write first + + // clear events + NRF_TWIM0->EVENTS_LASTTX = 0; + NRF_TWIM0->EVENTS_STOPPED = 0; + + // set tx buffer + NRF_TWIM0->TXD.PTR = (uint32_t)(&tx_buffer[0]); + NRF_TWIM0->TXD.MAXCNT = 1; + tx_buffer[0] = address; + + // start to write + NRF_TWIM0->TASKS_STARTTX = 1; + while( NRF_TWIM0->EVENTS_LASTTX==0); + while( NRF_TWIM0->EVENTS_STOPPED==0); + NRF_TWIM0->EVENTS_LASTTX = 0; + NRF_TWIM0->EVENTS_STOPPED = 0; + + // ---- reading data + + // clear events + NRF_TWIM0->EVENTS_LASTRX = 0; + NRF_TWIM0->EVENTS_STOPPED = 0; + + // set rx buffer + NRF_TWIM0->RXD.PTR = (uint32_t)(buffer); + NRF_TWIM0->RXD.MAXCNT = length; + + // start to read + NRF_TWIM0->TASKS_STARTRX = 1; + while( NRF_TWIM0->EVENTS_LASTRX==0); + while( NRF_TWIM0->EVENTS_STOPPED==0); + NRF_TWIM0->EVENTS_LASTRX = 0; + NRF_TWIM0->EVENTS_STOPPED = 0; + + // only for compatible purpose, return value has no meaning. + return 0xffffffff; +} + +uint32_t i2c_write_bytes(uint8_t address, uint8_t* buffer, uint32_t length) { + + uint8_t tx_buffer[1+length]; + + // clear events + NRF_TWIM0->EVENTS_LASTTX = 0; + NRF_TWIM0->EVENTS_STOPPED = 0; + + // set tx buffer + NRF_TWIM0->TXD.PTR = (uint32_t)(&tx_buffer[0]); + NRF_TWIM0->TXD.MAXCNT = 1+length; + tx_buffer[0] = address; + memcpy(&tx_buffer[1], buffer, length); + + // start to write + NRF_TWIM0->TASKS_STARTTX = 1; + while( NRF_TWIM0->EVENTS_LASTTX==0); + while( NRF_TWIM0->EVENTS_STOPPED==0); + NRF_TWIM0->EVENTS_LASTTX = 0; + NRF_TWIM0->EVENTS_STOPPED = 0; + + // only for compatible purpose, return value has no meaning. + return 0xffffffff; +} + +//=========================== private ========================================= + +void nrf_gpio_cfg_input(uint32_t pin_number) { + + NRF_GPIO_Type* NRF_Px_port; + uint32_t nrf_pin_number; + + if (pin_number < 32) { + + NRF_Px_port = NRF_P0; + nrf_pin_number = pin_number; + } else { + + NRF_Px_port = NRF_P1; + nrf_pin_number = pin_number & 0x1f; + } + + NRF_Px_port->PIN_CNF[nrf_pin_number] = \ + ((uint32_t)GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) + | ((uint32_t)GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) + | ((uint32_t)GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) + | ((uint32_t)GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) + | ((uint32_t)GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos); +} \ No newline at end of file diff --git a/bsp/boards/nrf52840_dk/leds.c b/bsp/boards/nrf52840_dk/leds.c new file mode 100644 index 0000000000..81cb2ea860 --- /dev/null +++ b/bsp/boards/nrf52840_dk/leds.c @@ -0,0 +1,205 @@ +/** + * Author: Tamas Harczos (tamas.harczos@imms.de) + * Date: Apr 2018 + * Description: nRF52840-specific definition of the "leds" bsp module. + */ + + #include "stdbool.h" +#include "nrf52840.h" +#include "board_info.h" +#include "leds.h" + + +//=========================== defines ========================================= + +// nrf52840-DK +#define LED_1 NRF_GPIO_PIN_MAP(0,13) +#define LED_2 NRF_GPIO_PIN_MAP(0,14) +#define LED_3 NRF_GPIO_PIN_MAP(0,15) +#define LED_4 NRF_GPIO_PIN_MAP(0,16) + +//=========================== variables ======================================= + +//=========================== prototypes ====================================== + +//=========================== public ========================================== + +void leds_init() { + + NRF_P0->DIRSET = 1<DIRSET = 1<DIRSET = 1<DIRSET = 1<OUTSET = 1<OUTCLR = 1<OUT & (1<OUTCLR = 1<OUTSET = 1<OUT & (1<OUTSET = 1<OUTCLR = 1<OUT & (1<OUTCLR = 1<OUTSET = 1<OUT & (1<OUTSET = 1<OUTCLR = 1<OUT & (1<OUTCLR = 1<OUTSET = 1<OUT & (1<OUTSET = 1<OUTCLR = 1<OUT & (1<OUTCLR = 1<OUTSET = 1<OUT & (1<OUT & 0x0001e000; + shift_bit = (NRF_P0->OUT & 0x00010000)>>3; + led_new_value = ((led_read<<1) & 0x0001e000) | shift_bit; + + NRF_P0->OUTSET = led_new_value; +} + +void leds_increment(void) { + + uint32_t led_new_value; + uint32_t led_read; + + led_read = (NRF_P0->OUT & 0x0001e000)>>13; + led_new_value = ((led_read+1) & 0x0000000f)<<13; + + NRF_P0->OUTSET = led_new_value; +} + +//=========================== private ========================================= \ No newline at end of file diff --git a/bsp/boards/nrf52840/radio.c b/bsp/boards/nrf52840_dk/radio.c similarity index 85% rename from bsp/boards/nrf52840/radio.c rename to bsp/boards/nrf52840_dk/radio.c index f3b371943a..42831faca2 100644 --- a/bsp/boards/nrf52840/radio.c +++ b/bsp/boards/nrf52840_dk/radio.c @@ -7,28 +7,13 @@ * Date: June 2018 */ -#include -#include -#include -#include - -#include "sdk/components/boards/boards.h" -#include "sdk/components/drivers_nrf/radio_config/radio_config.h" -#include "sdk/modules/nrfx/drivers/include/nrfx_systick.h" -#include "sdk/modules/nrfx/mdk/nrf52840.h" - -#include "sdk/integration/nrfx/legacy/nrf_drv_clock.h" - -#include "nrf_delay.h" - -#include "app_config.h" -#include "leds.h" -#include "radio.h" -#include "board.h" +#include "nrf52840.h" +#include "nrf52840_bitfields.h" #include "board_info.h" -#include "debugpins.h" #include "sctimer.h" -#include "radio_ble.h" +#include "debugpins.h" +#include "leds.h" +#include "radio.h" //=========================== defines ========================================= @@ -71,7 +56,7 @@ typedef struct { radio_capture_cbt endFrame_cb; radio_state_t state; uint8_t payload[1+MAX_PACKET_SIZE] __attribute__ ((aligned)); - bool hfc_started; + int8_t rssi_sample; // volatile bool event_ready; } radio_vars_t; @@ -81,7 +66,11 @@ static radio_vars_t radio_vars; static uint32_t swap_bits(uint32_t inp); static uint32_t bytewise_bitswap(uint32_t inp); -static uint8_t ble_channel_to_frequency(channel); +static uint8_t ble_channel_to_frequency(uint8_t channel); + +static void hfclock_start(void); +static void hfclock_stop(void); + //=========================== public ========================================== @@ -134,10 +123,11 @@ void radio_init(void) { // set up interrupts // disable radio interrupt NVIC_DisableIRQ(RADIO_IRQn); - NRF_RADIO->INTENSET = // RADIO_INTENSET_READY_Enabled << RADIO_INTENSET_READY_Pos | - RADIO_INTENSET_ADDRESS_Enabled << RADIO_INTENSET_ADDRESS_Pos | - RADIO_INTENSET_END_Enabled << RADIO_INTENSET_END_Pos; - NVIC_SetPriority(RADIO_IRQn, NRFX_RADIO_CONFIG_IRQ_PRIORITY); + + NRF_RADIO->INTENSET = (RADIO_INTENSET_FRAMESTART_Enabled << RADIO_INTENSET_FRAMESTART_Pos) | + (RADIO_INTENSET_END_Enabled << RADIO_INTENSET_END_Pos); + + NVIC_SetPriority(RADIO_IRQn, RADIO_PRIORITY); NVIC_ClearPendingIRQ(RADIO_IRQn); NVIC_EnableIRQ(RADIO_IRQn); @@ -283,7 +273,6 @@ void radio_txEnable(void) { NRF_RADIO->TASKS_TXEN = (uint32_t)1; while(NRF_RADIO->EVENTS_READY==0); - // wiggle debug pin debugpins_radio_set(); leds_radio_on(); @@ -360,23 +349,17 @@ void radio_getReceivedFrame(uint8_t* pBufRead, *pLenRead = len; *pLqi = radio_vars.payload[radio_vars.payload[0]-1]; - // For the RSSI calculation, see - // - // - http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52840.ps/radio.html?cp=2_0_0_5_19_11_6#ieee802154_rx and - // - https://www.metageek.com/training/resources/understanding-rssi.html - // - // Our RSSI will be in the range -91 dB (worst) to 0 dB (best) - *pRssi = (*pLqi > 91)?(0):(((int8_t) *pLqi) - 91); + *pRssi = (int8_t)(0-NRF_RADIO->RSSISAMPLE); *pCrc = (NRF_RADIO->CRCSTATUS == 1U); } -void radio_ble_getReceivedFrame(uint8_t* pBufRead, - uint8_t* pLenRead, - uint8_t maxBufLen, - int8_t* pRssi, - uint8_t* pLqi, - bool* pCrc) +void radio_ble_getReceivedFrame(uint8_t* pBufRead, + uint8_t* pLenRead, + uint8_t maxBufLen, + int8_t* pRssi, + uint8_t* pLqi, + bool* pCrc) { // check for length parameter; if too long, payload won't fit into memory uint8_t len; @@ -431,7 +414,7 @@ static uint32_t bytewise_bitswap(uint32_t inp) { | (swap_bits(inp)); } -static uint8_t ble_channel_to_frequency(channel) { +static uint8_t ble_channel_to_frequency(uint8_t channel) { uint8_t frequency; @@ -464,28 +447,71 @@ static uint8_t ble_channel_to_frequency(channel) { return frequency; } +static void hfclock_start(void) { + + NRF_CLOCK->EVENTS_HFCLKSTARTED = 0; + NRF_CLOCK->TASKS_HFCLKSTART = 1; + while (NRF_CLOCK->EVENTS_HFCLKSTARTED == 0); +} + +static void hfclock_stop(void) { + + // check clock source + if((NRF_CLOCK->HFCLKSTAT & 0x00000001) != 0) { + + // clock running? + if((NRF_CLOCK->HFCLKSTAT & 0x00010000) != 0) { + + NRF_CLOCK->TASKS_HFCLKSTOP = 1; + while((NRF_CLOCK->HFCLKSTAT & 0x00000001) != 0); + } + } +} //=========================== callbacks ======================================= -//=========================== interrupt handlers ============================== -void RADIO_IRQHandler(void) { +kick_scheduler_t radio_isr(void){ + + uint32_t time_stampe; + + time_stampe = NRF_RTC0->COUNTER; - if (NRF_RADIO->EVENTS_ADDRESS) { + // start of frame (payload) + if (NRF_RADIO->EVENTS_FRAMESTART){ - NRF_RADIO->EVENTS_ADDRESS = 0; + // start sampling rssi + NRF_RADIO->TASKS_RSSISTART = (uint32_t)1; - if (radio_vars.startFrame_cb) { - radio_vars.startFrame_cb(sctimer_readCounter()); + if (radio_vars.startFrame_cb!=NULL){ + radio_vars.startFrame_cb(time_stampe); } + + NRF_RADIO->EVENTS_FRAMESTART = (uint32_t)0; + return KICK_SCHEDULER; } + // END if (NRF_RADIO->EVENTS_END) { - NRF_RADIO->EVENTS_END = 0; - - if (radio_vars.endFrame_cb) { - radio_vars.endFrame_cb(sctimer_readCounter()); + if (radio_vars.endFrame_cb!=NULL){ + radio_vars.endFrame_cb(time_stampe); } + + NRF_RADIO->EVENTS_END = (uint32_t)0; + return KICK_SCHEDULER; } + + return DO_NOT_KICK_SCHEDULER; +} + +//=========================== interrupt handlers ============================== + +void RADIO_IRQHandler(void) { + + debugpins_isr_set(); + + radio_isr(); + + debugpins_isr_clr(); } diff --git a/bsp/boards/nrf52840_dk/sctimer.c b/bsp/boards/nrf52840_dk/sctimer.c new file mode 100644 index 0000000000..244294b6f5 --- /dev/null +++ b/bsp/boards/nrf52840_dk/sctimer.c @@ -0,0 +1,164 @@ +/** + * brief A timer module with only a single compare value. + * + * Authors: Tamas Harczos (1, tamas.harczos@imms.de) and Adam Sedmak (2, adam.sedmak@gmail.com) + * Company: (1) Institut fuer Mikroelektronik- und Mechatronik-Systeme gemeinnuetzige GmbH (IMMS GmbH) + * (2) Faculty of Electronics and Computing, Zagreb, Croatia + * Date: May 2018 + * + * Note: We use RTC0 peripheral with its CC0 register. +*/ + +#include "nrf52840.h" +#include "sctimer.h" +#include "debugpins.h" + +// ========================== define ========================================== + +#define LFCLKSRC_SRC_POS 0 +#define LFCLKSRC_BYPASS_POS 16 +#define LFCLKSRC_EXTERNAL_POS 17 + +#define LFCLKSTAT_SRC_POS 0 +#define LFCLKSTAT_STATE_POS 16 + +#define MINIMUM_ISR_ADVANCE 5 // nRF52840_PS_v1.7 (page 370) +#define TIMERLOOP_THRESHOLD 0xffff +#define TIMERMASK 0xffffff + +// ========================== variable ======================================== + +typedef struct { + sctimer_cbt cb; + uint8_t lastFireMode; +} sctimer_vars_t; + +sctimer_vars_t sctimer_vars= {0}; + +// ========================== prototypes======================================== + +// ========================== protocol ========================================= + +/** +\brief Initialization sctimer. +*/ +void sctimer_init(void) { + + memset(&sctimer_vars, 0, sizeof(sctimer_vars_t)); + + NVIC->IP[RTC0_IRQn] = (uint8_t)((RTC_PRIORITY << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFF); + NVIC->ISER[RTC0_IRQn>>5] = (uint32_t)(0x1 << (RTC0_IRQn & 0x1f)); + + // stop LFCLK + NRF_CLOCK->TASKS_LFCLKSTOP = 1; + while((NRF_CLOCK->LFCLKSTAT & (1<PRESCALER = 0; + + // configure the source + NRF_CLOCK->LFCLKSRC = (1<TASKS_LFCLKSTART = (uint32_t)1; + while((NRF_CLOCK->LFCLKSTAT & (1<EVENTS_COMPARE[0] = 0; + NRF_RTC0->INTENSET = 0x1<<16; + + NRF_RTC0->TASKS_START = 1; + + NVIC->IP[SWI0_EGU0_IRQn] = (uint8_t)((RTC_PRIORITY << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFF); + NVIC->ISER[SWI0_EGU0_IRQn>>5] = (uint32_t)(0x1 << (SWI0_EGU0_IRQn & 0x1f)); + + // configure egu for manually interrupts + NRF_EGU0->EVENTS_TRIGGERED[0] = 0; + NRF_EGU0->INTENSET = 1; +} + +void sctimer_set_callback(sctimer_cbt cb) { + sctimer_vars.cb= cb; +} + +/** +\brief set compare interrupt +*/ +void sctimer_setCompare(PORT_TIMER_WIDTH val) { + + uint32_t counter_current; + + counter_current = NRF_RTC0->COUNTER; + + if (((counter_current - val) & TIMERMASK) < TIMERLOOP_THRESHOLD) { + // the timer is already late, schedule the ISR right now manually + NRF_EGU0->TASKS_TRIGGER[0] = 1; + sctimer_vars.lastFireMode = 1; + } else { + if (((val - counter_current) & TIMERMASK) < MINIMUM_ISR_ADVANCE) { + // there is hardware limitation to schedule the timer within TIMERTHRESHOLD ticks + // schedule ISR right now manually + NRF_EGU0->TASKS_TRIGGER[0] = 1; + sctimer_vars.lastFireMode = 2; + } else { + // schedule the timer at val + NRF_RTC0->CC[0] = val; + sctimer_vars.lastFireMode = 0; + } + } +} + +/** +\brief Return the current value of the timer's counter. + + \returns The current value of the timer's counter. +*/ +PORT_TIMER_WIDTH sctimer_readCounter(void) { + + return NRF_RTC0->COUNTER; +} + +void sctimer_enable(void) { + + NRF_RTC0->INTENSET = (uint32_t)(1<<16); +} + +void sctimer_disable(void) { + + NRF_RTC0->INTENCLR = (uint32_t)(1<<16); +} + + +//=========================== interrupt handler =============================== + +void RTC0_IRQHandler(void) { + + debugpins_isr_set(); + + if (NRF_RTC0->EVENTS_COMPARE[0] != 0) { + NRF_RTC0->EVENTS_COMPARE[0] = 0; + + if (sctimer_vars.cb != NULL) { + sctimer_vars.cb(); + } + } + + debugpins_isr_clr(); +} + + +void SWI0_EGU0_IRQHandler(void) { + + debugpins_isr_set(); + + if (NRF_EGU0->EVENTS_TRIGGERED[0] != 0) { + NRF_EGU0->EVENTS_TRIGGERED[0] = 0; + + if (sctimer_vars.cb != NULL) { + sctimer_vars.cb(); + } + } + + debugpins_isr_clr(); +} \ No newline at end of file diff --git a/bsp/boards/nrf52840_dk/sdk/cmsis_compiler.h b/bsp/boards/nrf52840_dk/sdk/cmsis_compiler.h new file mode 100644 index 0000000000..21a2c7110d --- /dev/null +++ b/bsp/boards/nrf52840_dk/sdk/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/cmsis_armcc_V6.h b/bsp/boards/nrf52840_dk/sdk/cmsis_gcc.h similarity index 50% rename from bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/cmsis_armcc_V6.h rename to bsp/boards/nrf52840_dk/sdk/cmsis_gcc.h index d714e9b059..1e08e7e805 100644 --- a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/cmsis_armcc_V6.h +++ b/bsp/boards/nrf52840_dk/sdk/cmsis_gcc.h @@ -1,40 +1,186 @@ /**************************************************************************//** - * @file cmsis_armcc_V6.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.2.0 + * @date 08. May 2019 ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_ARMCC_V6_H -#define __CMSIS_ARMCC_V6_H +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface @@ -47,7 +193,7 @@ \details Enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +__STATIC_FORCEINLINE void __enable_irq(void) { __ASM volatile ("cpsie i" : : : "memory"); } @@ -58,7 +204,7 @@ __attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +__STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); } @@ -69,7 +215,7 @@ __attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) \details Returns the content of the Control Register. \return Control Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) { uint32_t result; @@ -78,13 +224,13 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) } -#if (__ARM_FEATURE_CMSE == 3U) +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Control Register (non-secure) \details Returns the content of the non-secure Control Register when in secure mode. \return non-secure Control Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) { uint32_t result; @@ -99,19 +245,19 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) { __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); } -#if (__ARM_FEATURE_CMSE == 3U) +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Control Register (non-secure) \details Writes the given value to the non-secure Control Register when in secure state. \param [in] control Control Register value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) { __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); } @@ -123,7 +269,7 @@ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t \details Returns the content of the IPSR Register. \return IPSR Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) { uint32_t result; @@ -132,28 +278,12 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) } -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get IPSR Register (non-secure) - \details Returns the content of the non-secure IPSR Register when in secure state. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) ); - return(result); -} -#endif - - /** \brief Get APSR Register \details Returns the content of the APSR Register. \return APSR Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +__STATIC_FORCEINLINE uint32_t __get_APSR(void) { uint32_t result; @@ -162,28 +292,12 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) } -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get APSR Register (non-secure) - \details Returns the content of the non-secure APSR Register when in secure state. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) ); - return(result); -} -#endif - - /** \brief Get xPSR Register \details Returns the content of the xPSR Register. \return xPSR Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) { uint32_t result; @@ -192,45 +306,29 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) } -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get xPSR Register (non-secure) - \details Returns the content of the non-secure xPSR Register when in secure state. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) ); - return(result); -} -#endif - - /** \brief Get Process Stack Pointer \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +__STATIC_FORCEINLINE uint32_t __get_PSP(void) { - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, psp" : "=r" (result) ); return(result); } -#if (__ARM_FEATURE_CMSE == 3U) +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer (non-secure) \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. \return PSP Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) { - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); return(result); @@ -243,21 +341,21 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) { - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); } -#if (__ARM_FEATURE_CMSE == 3U) +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. \param [in] topOfProcStack Process Stack Pointer value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) { - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp"); + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); } #endif @@ -267,24 +365,24 @@ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t top \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +__STATIC_FORCEINLINE uint32_t __get_MSP(void) { - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, msp" : "=r" (result) ); return(result); } -#if (__ARM_FEATURE_CMSE == 3U) +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer (non-secure) \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. \return MSP Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) { - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); return(result); @@ -297,21 +395,48 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) { - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); } -#if (__ARM_FEATURE_CMSE == 3U) +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer (non-secure) \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. \param [in] topOfMainStack Main Stack Pointer value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) { - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp"); + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); } #endif @@ -321,26 +446,26 @@ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t top \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; - __ASM volatile ("MRS %0, primask" : "=r" (result) ); + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); return(result); } -#if (__ARM_FEATURE_CMSE == 3U) +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Priority Mask (non-secure) \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. \return Priority Mask value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t result; - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); return(result); } #endif @@ -351,33 +476,34 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); } -#if (__ARM_FEATURE_CMSE == 3U) +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Priority Mask (non-secure) \details Assigns the given value to the non-secure Priority Mask Register when in secure state. \param [in] priMask Priority Mask */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) { __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); } #endif -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Enable FIQ \details Enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +__STATIC_FORCEINLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f" : : : "memory"); } @@ -388,7 +514,7 @@ __attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) \details Disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +__STATIC_FORCEINLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f" : : : "memory"); } @@ -399,7 +525,7 @@ __attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) \details Returns the current value of the Base Priority register. \return Base Priority register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) { uint32_t result; @@ -408,13 +534,13 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) } -#if (__ARM_FEATURE_CMSE == 3U) +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Base Priority (non-secure) \details Returns the current value of the non-secure Base Priority register when in secure state. \return Base Priority register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t result; @@ -429,21 +555,21 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) { - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); } -#if (__ARM_FEATURE_CMSE == 3U) +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Base Priority (non-secure) \details Assigns the given value to the non-secure Base Priority register when in secure state. \param [in] basePri Base Priority value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value) +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) { - __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory"); + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); } #endif @@ -454,24 +580,10 @@ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Base Priority with condition (non_secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value) +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) { - __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory"); + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); } -#endif /** @@ -479,7 +591,7 @@ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) { uint32_t result; @@ -488,13 +600,13 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) } -#if (__ARM_FEATURE_CMSE == 3U) +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Fault Mask (non-secure) \details Returns the current value of the non-secure Fault Mask register when in secure state. \return Fault Mask register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t result; @@ -509,185 +621,234 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(vo \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); } -#if (__ARM_FEATURE_CMSE == 3U) +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Fault Mask (non-secure) \details Assigns the given value to the non-secure Fault Mask register when in secure state. \param [in] faultMask Fault Mask value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) { __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); } #endif +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ -#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - -#if (__ARM_ARCH_8M__ == 1U) +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) { - register uint32_t result; - +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return(result); + return result; +#endif } - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \return PSPLIM Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) { - register uint32_t result; - +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return(result); + return result; +#endif } #endif /** \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif } -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) { +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif } #endif /** \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). \return MSPLIM Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) { - register uint32_t result; - +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - - return(result); + return result; +#endif } -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. \return MSPLIM Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) { - register uint32_t result; - +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return(result); + return result; +#endif } #endif /** \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif } -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. \param [in] MainStackPtrLimit Main Stack Pointer value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) { +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif } #endif -#endif /* (__ARM_ARCH_8M__ == 1U) */ - +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ -#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */ /** \brief Get FPSCR - \details eturns the current value of the Floating Point Status/Control register. + \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ -#define __get_FPSCR __builtin_arm_get_fpscr -#if 0 -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) { -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else uint32_t result; - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); return(result); -#else - return(0); -#endif -} #endif - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get FPSCR (non-secure) - \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state. - \return Floating Point Status/Control register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) ); - __ASM volatile (""); - return(result); #else - return(0); + return(0U); #endif } -#endif /** @@ -695,36 +856,22 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void) \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ -#define __set_FPSCR __builtin_arm_set_fpscr -#if 0 -__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) { -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); #endif - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set FPSCR (non-secure) - \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state. - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); +#else + (void)fpscr; #endif } -#endif - -#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - /*@} end of CMSIS_Core_RegAccFunctions */ @@ -741,9 +888,11 @@ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t f * Otherwise, use general registers, specified by constraint "r" */ #if defined (__thumb__) && !defined (__thumb2__) #define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) #define __CMSIS_GCC_USE_REG(r) "l" (r) #else #define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) #define __CMSIS_GCC_USE_REG(r) "r" (r) #endif @@ -751,13 +900,13 @@ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t f \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ -#define __NOP __builtin_arm_nop +#define __NOP() __ASM volatile ("nop") /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ -#define __WFI __builtin_arm_wfi +#define __WFI() __ASM volatile ("wfi") /** @@ -765,14 +914,14 @@ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t f \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ -#define __WFE __builtin_arm_wfe +#define __WFE() __ASM volatile ("wfe") /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ -#define __SEV __builtin_arm_sev +#define __SEV() __ASM volatile ("sev") /** @@ -781,14 +930,21 @@ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t f so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ -#define __ISB() __builtin_arm_isb(0xF); +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ -#define __DSB() __builtin_arm_dsb(0xF); +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} /** @@ -796,49 +952,62 @@ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t f \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ -#define __DMB() __builtin_arm_dmb(0xF); +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} /** \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ -#define __REV __builtin_bswap32 +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} /** \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ -#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ -#if 0 -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) { uint32_t result; __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); + return result; } -#endif /** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ - /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) { - int32_t result; +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); + return result; +#endif } @@ -849,8 +1018,13 @@ __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) \param [in] op2 Number of Bits to rotate \return Rotated value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } return (op1 >> op2) | (op1 << (32U - op2)); } @@ -858,9 +1032,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint /** \brief Breakpoint \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __ASM volatile ("bkpt "#value) @@ -871,18 +1045,19 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint \param [in] value Value to reverse \return Reversed value */ - /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) { uint32_t result; -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); #else - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) + for (value >>= 1U; value != 0U; value >>= 1U) { result <<= 1U; result |= value & 1U; @@ -890,7 +1065,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) } result <<= s; /* shift when v's highest bits are zero */ #endif - return(result); + return result; } @@ -900,18 +1075,49 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) \param [in] value Value to count the leading zeros \return number of leading zeros in value */ -#define __CLZ __builtin_clz - +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} /** @@ -920,7 +1126,20 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} /** @@ -929,7 +1148,13 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} /** @@ -940,7 +1165,13 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) \return 0 Function succeeded \return 1 Function failed */ -#define __STREXB (uint32_t)__builtin_arm_strex +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} /** @@ -951,7 +1182,13 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) \return 0 Function succeeded \return 1 Function failed */ -#define __STREXH (uint32_t)__builtin_arm_strex +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} /** @@ -962,25 +1199,42 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) \return 0 Function succeeded \return 1 Function failed */ -#define __STREXW (uint32_t)__builtin_arm_strex +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ -#define __CLREX __builtin_arm_clrex +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Signed Saturate \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) \return Saturated value */ -/*#define __SSAT __builtin_arm_ssat*/ #define __SSAT(ARG1,ARG2) \ +__extension__ \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ @@ -991,19 +1245,17 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) /** \brief Unsigned Saturate \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) \return Saturated value */ -#define __USAT __builtin_arm_usat -#if 0 #define __USAT(ARG1,ARG2) \ + __extension__ \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) -#endif /** @@ -1013,7 +1265,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) \param [in] value Value to rotate \return Rotated value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) { uint32_t result; @@ -1028,11 +1280,18 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) { uint32_t result; +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif return ((uint8_t) result); /* Add explicit type cast here */ } @@ -1043,11 +1302,18 @@ __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) { uint32_t result; +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif return ((uint16_t) result); /* Add explicit type cast here */ } @@ -1058,7 +1324,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_ \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) { uint32_t result; @@ -1073,7 +1339,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t \param [in] value Value to store \param [in] ptr Pointer to location */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } @@ -1085,7 +1351,7 @@ __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volat \param [in] value Value to store \param [in] ptr Pointer to location */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } @@ -1097,23 +1363,78 @@ __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, vola \param [in] value Value to store \param [in] ptr Pointer to location */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); } -#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ -#if (__ARM_ARCH_8M__ == 1U) +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Load-Acquire (8 bit) \details Executes a LDAB instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t result; @@ -1128,7 +1449,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t * \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t result; @@ -1143,7 +1464,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) { uint32_t result; @@ -1158,7 +1479,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t \param [in] value Value to store \param [in] ptr Pointer to location */ -__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } @@ -1170,7 +1491,7 @@ __attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volati \param [in] value Value to store \param [in] ptr Pointer to location */ -__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } @@ -1182,7 +1503,7 @@ __attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volat \param [in] value Value to store \param [in] ptr Pointer to location */ -__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } @@ -1194,7 +1515,13 @@ __attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volati \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} /** @@ -1203,7 +1530,13 @@ __attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volati \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} /** @@ -1212,7 +1545,13 @@ __attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volati \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} /** @@ -1223,7 +1562,13 @@ __attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volati \return 0 Function succeeded \return 1 Function failed */ -#define __STLEXB (uint32_t)__builtin_arm_stlex +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} /** @@ -1234,7 +1579,13 @@ __attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volati \return 0 Function succeeded \return 1 Function failed */ -#define __STLEXH (uint32_t)__builtin_arm_stlex +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} /** @@ -1245,9 +1596,16 @@ __attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volati \return 0 Function succeeded \return 1 Function failed */ -#define __STLEX (uint32_t)__builtin_arm_stlex +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} -#endif /* (__ARM_ARCH_8M__ == 1U) */ +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ @@ -1258,9 +1616,9 @@ __attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volati @{ */ -#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */ +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1268,7 +1626,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, ui return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1276,7 +1634,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, ui return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1284,7 +1642,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, u return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1292,7 +1650,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, ui return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1300,7 +1658,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, u return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1309,7 +1667,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, u } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1317,7 +1675,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, ui return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1325,7 +1683,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, ui return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1333,7 +1691,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, u return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1341,7 +1699,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, ui return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1349,7 +1707,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, u return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1358,7 +1716,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, u } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1366,7 +1724,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, u return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1374,7 +1732,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, u return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1382,7 +1740,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1390,7 +1748,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, u return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1398,7 +1756,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1406,7 +1764,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1414,7 +1772,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, u return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1422,7 +1780,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, u return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1430,7 +1788,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1438,7 +1796,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, u return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1446,7 +1804,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1454,7 +1812,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1462,7 +1820,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uin return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1470,7 +1828,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uin return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1478,7 +1836,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, ui return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1486,7 +1844,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uin return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1494,7 +1852,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, ui return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1502,7 +1860,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, ui return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1510,7 +1868,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uin return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1518,7 +1876,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uin return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1526,7 +1884,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, ui return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1534,7 +1892,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uin return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1542,7 +1900,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, ui return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1550,7 +1908,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, ui return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1558,7 +1916,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, ui return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; @@ -1568,7 +1926,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, u #define __SSAT16(ARG1,ARG2) \ ({ \ - uint32_t __RES, __ARG1 = (ARG1); \ + int32_t __RES, __ARG1 = (ARG1); \ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) @@ -1580,7 +1938,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, u __RES; \ }) -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) { uint32_t result; @@ -1588,7 +1946,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1596,7 +1954,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) { uint32_t result; @@ -1604,7 +1962,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -1612,7 +1970,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) { uint32_t result; @@ -1620,7 +1978,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) { uint32_t result; @@ -1628,7 +1986,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; @@ -1636,7 +1994,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, u return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; @@ -1644,7 +2002,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; @@ -1661,7 +2019,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, return(llr.w64); } -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; @@ -1678,7 +2036,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, return(llr.w64); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) { uint32_t result; @@ -1686,7 +2044,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) { uint32_t result; @@ -1694,7 +2052,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; @@ -1702,7 +2060,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, u return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; @@ -1710,7 +2068,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, return(result); } -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; @@ -1727,7 +2085,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, return(llr.w64); } -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; @@ -1744,7 +2102,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, return(llr.w64); } -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) { uint32_t result; @@ -1752,7 +2110,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, ui return(result); } -__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) { int32_t result; @@ -1760,7 +2118,7 @@ __attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, in return(result); } -__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) { int32_t result; @@ -1768,6 +2126,7 @@ __attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, in return(result); } +#if 0 #define __PKHBT(ARG1,ARG2,ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ @@ -1784,8 +2143,15 @@ __attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, in __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ __RES; \ }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; @@ -1793,8 +2159,10 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, in return(result); } -#endif /* (__ARM_FEATURE_DSP == 1U) */ +#endif /* (__ARM_FEATURE_DSP == 1) */ /*@} end of group CMSIS_SIMD_intrinsics */ -#endif /* __CMSIS_ARMCC_V6_H */ +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/boards/nrf52840_dk/sdk/cmsis_version.h b/bsp/boards/nrf52840_dk/sdk/cmsis_version.h new file mode 100644 index 0000000000..3174cf60be --- /dev/null +++ b/bsp/boards/nrf52840_dk/sdk/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.3 + * @date 24. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/compiler_abstraction.h b/bsp/boards/nrf52840_dk/sdk/compiler_abstraction.h similarity index 51% rename from bsp/boards/nrf52840/sdk/modules/nrfx/mdk/compiler_abstraction.h rename to bsp/boards/nrf52840_dk/sdk/compiler_abstraction.h index f8208f2982..061a61aff8 100644 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/compiler_abstraction.h +++ b/bsp/boards/nrf52840_dk/sdk/compiler_abstraction.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. @@ -44,6 +44,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /*lint ++flb "Enter library region" */ +#ifndef NRF_STRING_CONCATENATE_IMPL + #define NRF_STRING_CONCATENATE_IMPL(lhs, rhs) lhs ## rhs +#endif +#ifndef NRF_STRING_CONCATENATE + #define NRF_STRING_CONCATENATE(lhs, rhs) NRF_STRING_CONCATENATE_IMPL(lhs, rhs) +#endif + #if defined ( __CC_ARM ) #ifndef __ASM @@ -66,8 +73,54 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define __PACKED __packed #endif + #ifndef __UNUSED + #define __UNUSED __attribute__((unused)) + #endif + #define GET_SP() __current_sp() + #ifndef NRF_STATIC_ASSERT + #define NRF_STATIC_ASSERT(cond, msg) \ + ;enum { NRF_STRING_CONCATENATE(static_assert_on_line_, __LINE__) = 1 / (!!(cond)) } + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE __inline + #endif + + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + + #ifndef __ALIGN + #define __ALIGN(n) __attribute__((aligned(n))) + #endif + + #ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) + #endif + + #ifndef __UNUSED + #define __UNUSED __attribute__((unused)) + #endif + + #define GET_SP() __current_sp() + + #ifndef NRF_STATIC_ASSERT + #ifdef __cplusplus + #ifndef _Static_assert + #define _Static_assert static_assert + #endif + #endif + #define NRF_STATIC_ASSERT(cond, msg) _Static_assert(cond, msg) + #endif + #elif defined ( __ICCARM__ ) #ifndef __ASM @@ -82,18 +135,36 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define __WEAK __weak #endif - #ifndef __ALIGN - #define STRING_PRAGMA(x) _Pragma(#x) - #define __ALIGN(n) STRING_PRAGMA(data_alignment = n) + #if (__VER__ >= 8000000) + #ifndef __ALIGN + #define __ALIGN(n) __attribute__((aligned(x))) + #endif + + #ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) + #endif + #else + #ifndef __ALIGN + #define STRING_PRAGMA(x) _Pragma(#x) + #define __ALIGN(n) STRING_PRAGMA(data_alignment = n) + #endif + + #ifndef __PACKED + #define __PACKED __packed + #endif #endif - #ifndef __PACKED - #define __PACKED __packed + #ifndef __UNUSED + #define __UNUSED #endif #define GET_SP() __get_SP() -#elif defined ( __GNUC__ ) + #ifndef NRF_STATIC_ASSERT + #define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg) + #endif + +#elif defined ( __GNUC__ ) || defined ( __clang__ ) #ifndef __ASM #define __ASM __asm @@ -115,14 +186,28 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define __PACKED __attribute__((packed)) #endif + #ifndef __UNUSED + #define __UNUSED __attribute__((unused)) + #endif + #define GET_SP() gcc_current_sp() static inline unsigned int gcc_current_sp(void) { - register unsigned sp __ASM("sp"); - return sp; + unsigned int stack_pointer = 0; + __asm__ __volatile__ ("mov %0, sp" : "=r"(stack_pointer)); + return stack_pointer; } + #ifndef NRF_STATIC_ASSERT + #ifdef __cplusplus + #ifndef _Static_assert + #define _Static_assert static_assert + #endif + #endif + #define NRF_STATIC_ASSERT(cond, msg) _Static_assert(cond, msg) + #endif + #elif defined ( __TASKING__ ) #ifndef __ASM @@ -146,10 +231,34 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define __PACKED #endif + #ifndef __UNUSED + #define __UNUSED __attribute__((unused)) + #endif + #define GET_SP() __get_MSP() + #ifndef NRF_STATIC_ASSERT + #define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg) + #endif + #endif +#define NRF_MDK_VERSION_ASSERT_AT_LEAST(major, minor, micro) \ + NRF_STATIC_ASSERT( \ + ( \ + (major < MDK_MAJOR_VERSION) || \ + (major == MDK_MAJOR_VERSION && minor < MDK_MINOR_VERSION) || \ + (major == MDK_MAJOR_VERSION && minor == MDK_MINOR_VERSION && micro < MDK_MICRO_VERSION) \ + ), "MDK version mismatch.") + +#define NRF_MDK_VERSION_ASSERT_EXACT(major, minor, micro) \ + NRF_STATIC_ASSERT( \ + ( \ + (major != MDK_MAJOR_VERSION) || \ + (major != MDK_MAJOR_VERSION) || \ + (major != MDK_MAJOR_VERSION) \ + ), "MDK version mismatch.") + /*lint --flb "Leave library region" */ #endif diff --git a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_cm4.h b/bsp/boards/nrf52840_dk/sdk/core_cm4.h similarity index 81% rename from bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_cm4.h rename to bsp/boards/nrf52840_dk/sdk/core_cm4.h index 7002e4e522..90c2a72d72 100644 --- a/bsp/boards/nrf52840/sdk/components/toolchain/cmsis/include/core_cm4.h +++ b/bsp/boards/nrf52840_dk/sdk/core_cm4.h @@ -1,40 +1,30 @@ /**************************************************************************//** * @file core_cm4.h * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 + * @version V5.1.0 + * @date 13. March 2019 ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ #if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif @@ -70,60 +60,22 @@ @{ */ -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline +#include "cmsis_version.h" -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif +#define __CORTEX_M (4U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" @@ -133,9 +85,9 @@ #define __FPU_USED 0U #endif -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if (__FPU_PRESENT == 1) +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" @@ -147,7 +99,7 @@ #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" @@ -159,7 +111,7 @@ #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" @@ -169,9 +121,9 @@ #define __FPU_USED 0U #endif -#elif defined ( __TMS470__ ) +#elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" @@ -183,7 +135,7 @@ #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" @@ -195,7 +147,7 @@ #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) - #if (__FPU_PRESENT == 1U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" @@ -207,9 +159,8 @@ #endif -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ -#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + #ifdef __cplusplus } @@ -244,7 +195,7 @@ #endif #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4U + #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif @@ -367,11 +318,12 @@ typedef union struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ @@ -397,8 +349,8 @@ typedef union #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ @@ -406,6 +358,9 @@ typedef union #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ @@ -453,7 +408,7 @@ typedef struct __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; + uint32_t RESERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ @@ -662,6 +617,66 @@ typedef struct #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ @@ -807,10 +822,7 @@ typedef struct __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ @@ -831,7 +843,7 @@ typedef struct /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ @@ -861,18 +873,6 @@ typedef struct #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ @@ -1045,7 +1045,7 @@ typedef struct */ typedef struct { - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ @@ -1056,7 +1056,7 @@ typedef struct __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; @@ -1105,13 +1105,13 @@ typedef struct /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ @@ -1126,18 +1126,21 @@ typedef struct #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ @@ -1152,12 +1155,15 @@ typedef struct #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ @@ -1179,16 +1185,16 @@ typedef struct #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + /*@}*/ /* end of group CMSIS_TPI */ -#if (__MPU_PRESENT == 1U) +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) @@ -1214,6 +1220,8 @@ typedef struct __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; +#define MPU_TYPE_RALIASES 4U + /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ @@ -1280,10 +1288,9 @@ typedef struct #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ -#endif +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ -#if (__FPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) @@ -1302,6 +1309,7 @@ typedef struct __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ @@ -1387,8 +1395,12 @@ typedef struct #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + /*@} end of group CMSIS_FPU */ -#endif /** @@ -1506,18 +1518,18 @@ typedef struct /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. - \param[in] value Value of register. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ @@ -1529,7 +1541,7 @@ typedef struct @{ */ -/* Memory mapping of Cortex-M4 Hardware */ +/* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ @@ -1548,15 +1560,13 @@ typedef struct #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ -#if (__MPU_PRESENT == 1U) +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif -#if (__FPU_PRESENT == 1U) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ /*@} */ @@ -1584,6 +1594,48 @@ typedef struct @{ */ +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. @@ -1593,7 +1645,7 @@ typedef struct priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ @@ -1602,7 +1654,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } @@ -1612,121 +1664,180 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } } /** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } } /** \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. + \note IRQn must not be negative. */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } } /** \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } } /** \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } } /** \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. + \note IRQn must not be negative. */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } } /** \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - if ((int32_t)(IRQn) < 0) + if ((int32_t)(IRQn) >= 0) { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { - if ((int32_t)(IRQn) < 0) + if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } @@ -1783,11 +1894,43 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr } +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ -__STATIC_INLINE void NVIC_SystemReset(void) +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ @@ -1796,7 +1939,7 @@ __STATIC_INLINE void NVIC_SystemReset(void) SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ - for (;;) /* wait until reset */ + for(;;) /* wait until reset */ { __NOP(); } @@ -1805,6 +1948,50 @@ __STATIC_INLINE void NVIC_SystemReset(void) /*@} end of CMSIS_Core_NVICFunctions */ +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + /* ################################## SysTick function ############################################ */ /** @@ -1814,7 +2001,7 @@ __STATIC_INLINE void NVIC_SystemReset(void) @{ */ -#if (__Vendor_SysTickConfig == 0U) +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration @@ -1857,8 +2044,8 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) @{ */ -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** diff --git a/bsp/boards/nrf52840_dk/sdk/mpu_armv7.h b/bsp/boards/nrf52840_dk/sdk/mpu_armv7.h new file mode 100644 index 0000000000..337eb65568 --- /dev/null +++ b/bsp/boards/nrf52840_dk/sdk/mpu_armv7.h @@ -0,0 +1,272 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/boards/nrf52840_dk/sdk/nrf.h b/bsp/boards/nrf52840_dk/sdk/nrf.h new file mode 100644 index 0000000000..7c21b14fd3 --- /dev/null +++ b/bsp/boards/nrf52840_dk/sdk/nrf.h @@ -0,0 +1,198 @@ +/* + +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF_H +#define NRF_H + +/* MDK version */ +#define MDK_MAJOR_VERSION 8 +#define MDK_MINOR_VERSION 40 +#define MDK_MICRO_VERSION 3 + + +/* Define coprocessor domains */ +#if defined (NRF5340_XXAA_APPLICATION) || defined (NRF5340_XXAA_NETWORK) + #ifndef NRF5340_XXAA + #define NRF5340_XXAA + #endif +#endif +#if defined (NRF5340_XXAA_APPLICATION) + #ifndef NRF_APPLICATION + #define NRF_APPLICATION + #endif +#endif +#if defined (NRF5340_XXAA_NETWORK) + #ifndef NRF_NETWORK + #define NRF_NETWORK + #endif +#endif + +/* Apply compatibility macros for old nRF5340 macros */ +#if defined(NRF5340_XXAA) + #if defined (NRF_APPLICATION) + #ifndef NRF5340_XXAA_APPLICATION + #define NRF5340_XXAA_APPLICATION + #endif + #endif + #if defined (NRF_NETWORK) + #ifndef NRF5340_XXAA_NETWORK + #define NRF5340_XXAA_NETWORK + #endif + #endif +#endif + +/* Define NRF51_SERIES for common use in nRF51 series devices. Only if not previously defined. */ +#if defined (NRF51) ||\ + defined (NRF51422_XXAA) ||\ + defined (NRF51422_XXAB) ||\ + defined (NRF51422_XXAC) ||\ + defined (NRF51801_XXAB) ||\ + defined (NRF51802_XXAA) ||\ + defined (NRF51822_XXAA) ||\ + defined (NRF51822_XXAB) ||\ + defined (NRF51822_XXAC) ||\ + defined (NRF51824_XXAA) + #ifndef NRF51_SERIES + #define NRF51_SERIES + #endif + #ifndef NRF51 + #define NRF51 + #endif +#endif + +/* Redefine "old" too-generic name NRF52 to NRF52832_XXAA to keep backwards compatibility. */ +#if defined (NRF52) + #ifndef NRF52832_XXAA + #define NRF52832_XXAA + #endif +#endif + +/* Define NRF52_SERIES for common use in nRF52 series devices. Only if not previously defined. */ +#if defined (NRF52805_XXAA) || defined (NRF52810_XXAA) || defined (NRF52811_XXAA) || defined (NRF52820_XXAA) || defined (NRF52832_XXAA) || defined (NRF52832_XXAB) || defined (NRF52833_XXAA) || defined (NRF52840_XXAA) + #ifndef NRF52_SERIES + #define NRF52_SERIES + #endif +#endif + +/* Define NRF53_SERIES for common use in nRF53 series devices. */ +#if defined (NRF5340_XXAA) + #ifndef NRF53_SERIES + #define NRF53_SERIES + #endif +#endif + +/* Define NRF91_SERIES for common use in nRF91 series devices. */ +#if defined (NRF9160_XXAA) + #ifndef NRF91_SERIES + #define NRF91_SERIES + #endif +#endif + +/* Device selection for device includes. */ +#if defined (NRF51) + #include "nrf51.h" + #include "nrf51_bitfields.h" + #include "nrf51_deprecated.h" + +#elif defined (NRF52805_XXAA) + #include "nrf52805.h" + #include "nrf52805_bitfields.h" + #include "nrf51_to_nrf52810.h" + #include "nrf52_to_nrf52810.h" + #include "nrf52810_to_nrf52811.h" +#elif defined (NRF52810_XXAA) + #include "nrf52810.h" + #include "nrf52810_bitfields.h" + #include "nrf51_to_nrf52810.h" + #include "nrf52_to_nrf52810.h" + #include "nrf52810_name_change.h" +#elif defined (NRF52811_XXAA) + #include "nrf52811.h" + #include "nrf52811_bitfields.h" + #include "nrf51_to_nrf52810.h" + #include "nrf52_to_nrf52810.h" + #include "nrf52810_to_nrf52811.h" +#elif defined (NRF52820_XXAA) + #include "nrf52820.h" + #include "nrf52820_bitfields.h" + #include "nrf51_to_nrf52.h" + #include "nrf52_to_nrf52833.h" + #include "nrf52833_to_nrf52820.h" +#elif defined (NRF52832_XXAA) || defined (NRF52832_XXAB) + #include "nrf52.h" + #include "nrf52_bitfields.h" + #include "nrf51_to_nrf52.h" + #include "nrf52_name_change.h" +#elif defined (NRF52833_XXAA) + #include "nrf52833.h" + #include "nrf52833_bitfields.h" + #include "nrf52_to_nrf52833.h" + #include "nrf51_to_nrf52.h" +#elif defined (NRF52840_XXAA) + #include "nrf52840.h" + #include "nrf52840_bitfields.h" + #include "nrf51_to_nrf52840.h" + #include "nrf52_to_nrf52840.h" + +#elif defined (NRF5340_XXAA) + #if defined(NRF_APPLICATION) + #include "nrf5340_application.h" + #include "nrf5340_application_bitfields.h" + #include "nrf5340_application_name_change.h" + #elif defined (NRF_NETWORK) + #include "nrf5340_network.h" + #include "nrf5340_network_bitfields.h" + #include "nrf5340_network_name_change.h" + #endif + +#elif defined (NRF9160_XXAA) + #include "nrf9160.h" + #include "nrf9160_bitfields.h" + #include "nrf9160_name_change.h" + +#else + #error "Device must be defined. See nrf.h." +#endif /* NRF51, NRF52805_XXAA, NRF52810_XXAA, NRF52811_XXAA, NRF52820_XXAA, NRF52832_XXAA, NRF52832_XXAB, NRF52833_XXAA, NRF52840_XXAA, NRF5340_XXAA_APPLICATION, NRF5340_XXAA_NETWORK, NRF9160_XXAA */ + +#include "compiler_abstraction.h" + +#endif /* NRF_H */ + diff --git a/bsp/boards/nrf52840_dk/sdk/nrf51_erratas.h b/bsp/boards/nrf52840_dk/sdk/nrf51_erratas.h new file mode 100644 index 0000000000..3a7cecaae4 --- /dev/null +++ b/bsp/boards/nrf52840_dk/sdk/nrf51_erratas.h @@ -0,0 +1,4736 @@ +#ifndef NRF51_ERRATAS_H +#define NRF51_ERRATAS_H + +/* + +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#include +#include +#include "compiler_abstraction.h" + +static bool nrf51_errata_1(void) __UNUSED; +static bool nrf51_errata_2(void) __UNUSED; +static bool nrf51_errata_3(void) __UNUSED; +static bool nrf51_errata_4(void) __UNUSED; +static bool nrf51_errata_5(void) __UNUSED; +static bool nrf51_errata_6(void) __UNUSED; +static bool nrf51_errata_7(void) __UNUSED; +static bool nrf51_errata_8(void) __UNUSED; +static bool nrf51_errata_9(void) __UNUSED; +static bool nrf51_errata_10(void) __UNUSED; +static bool nrf51_errata_11(void) __UNUSED; +static bool nrf51_errata_12(void) __UNUSED; +static bool nrf51_errata_13(void) __UNUSED; +static bool nrf51_errata_14(void) __UNUSED; +static bool nrf51_errata_15(void) __UNUSED; +static bool nrf51_errata_16(void) __UNUSED; +static bool nrf51_errata_17(void) __UNUSED; +static bool nrf51_errata_18(void) __UNUSED; +static bool nrf51_errata_19(void) __UNUSED; +static bool nrf51_errata_20(void) __UNUSED; +static bool nrf51_errata_21(void) __UNUSED; +static bool nrf51_errata_22(void) __UNUSED; +static bool nrf51_errata_23(void) __UNUSED; +static bool nrf51_errata_24(void) __UNUSED; +static bool nrf51_errata_25(void) __UNUSED; +static bool nrf51_errata_26(void) __UNUSED; +static bool nrf51_errata_27(void) __UNUSED; +static bool nrf51_errata_28(void) __UNUSED; +static bool nrf51_errata_29(void) __UNUSED; +static bool nrf51_errata_30(void) __UNUSED; +static bool nrf51_errata_31(void) __UNUSED; +static bool nrf51_errata_32(void) __UNUSED; +static bool nrf51_errata_33(void) __UNUSED; +static bool nrf51_errata_34(void) __UNUSED; +static bool nrf51_errata_35(void) __UNUSED; +static bool nrf51_errata_36(void) __UNUSED; +static bool nrf51_errata_37(void) __UNUSED; +static bool nrf51_errata_38(void) __UNUSED; +static bool nrf51_errata_39(void) __UNUSED; +static bool nrf51_errata_40(void) __UNUSED; +static bool nrf51_errata_41(void) __UNUSED; +static bool nrf51_errata_42(void) __UNUSED; +static bool nrf51_errata_43(void) __UNUSED; +static bool nrf51_errata_44(void) __UNUSED; +static bool nrf51_errata_45(void) __UNUSED; +static bool nrf51_errata_46(void) __UNUSED; +static bool nrf51_errata_47(void) __UNUSED; +static bool nrf51_errata_48(void) __UNUSED; +static bool nrf51_errata_49(void) __UNUSED; +static bool nrf51_errata_50(void) __UNUSED; +static bool nrf51_errata_51(void) __UNUSED; +static bool nrf51_errata_52(void) __UNUSED; +static bool nrf51_errata_53(void) __UNUSED; +static bool nrf51_errata_54(void) __UNUSED; +static bool nrf51_errata_55(void) __UNUSED; +static bool nrf51_errata_56(void) __UNUSED; +static bool nrf51_errata_57(void) __UNUSED; +static bool nrf51_errata_58(void) __UNUSED; +static bool nrf51_errata_59(void) __UNUSED; +static bool nrf51_errata_60(void) __UNUSED; +static bool nrf51_errata_61(void) __UNUSED; +static bool nrf51_errata_62(void) __UNUSED; +static bool nrf51_errata_63(void) __UNUSED; +static bool nrf51_errata_64(void) __UNUSED; +static bool nrf51_errata_65(void) __UNUSED; +static bool nrf51_errata_66(void) __UNUSED; +static bool nrf51_errata_67(void) __UNUSED; +static bool nrf51_errata_68(void) __UNUSED; +static bool nrf51_errata_69(void) __UNUSED; +static bool nrf51_errata_70(void) __UNUSED; +static bool nrf51_errata_71(void) __UNUSED; +static bool nrf51_errata_72(void) __UNUSED; +static bool nrf51_errata_73(void) __UNUSED; +static bool nrf51_errata_74(void) __UNUSED; +static bool nrf51_errata_75(void) __UNUSED; +static bool nrf51_errata_76(void) __UNUSED; +static bool nrf51_errata_77(void) __UNUSED; +static bool nrf51_errata_78(void) __UNUSED; + +/* ========= Errata 1 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_1_PRESENT 1 +#else + #define NRF51_ERRATA_1_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_1_ENABLE_WORKAROUND + #define NRF51_ERRATA_1_ENABLE_WORKAROUND NRF51_ERRATA_1_PRESENT +#endif + +static bool nrf51_errata_1(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 2 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_2_PRESENT 1 +#else + #define NRF51_ERRATA_2_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_2_ENABLE_WORKAROUND + #define NRF51_ERRATA_2_ENABLE_WORKAROUND NRF51_ERRATA_2_PRESENT +#endif + +static bool nrf51_errata_2(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 3 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_3_PRESENT 1 +#else + #define NRF51_ERRATA_3_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_3_ENABLE_WORKAROUND + #define NRF51_ERRATA_3_ENABLE_WORKAROUND NRF51_ERRATA_3_PRESENT +#endif + +static bool nrf51_errata_3(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 4 ========= */ +#define NRF51_ERRATA_4_PRESENT 0 + +#ifndef NRF51_ERRATA_4_ENABLE_WORKAROUND + #define NRF51_ERRATA_4_ENABLE_WORKAROUND NRF51_ERRATA_4_PRESENT +#endif + +static bool nrf51_errata_4(void) +{ + #ifndef NRF51_SERIES + return false; + #else + return false; + #endif +} + +/* ========= Errata 5 ========= */ +#define NRF51_ERRATA_5_PRESENT 0 + +#ifndef NRF51_ERRATA_5_ENABLE_WORKAROUND + #define NRF51_ERRATA_5_ENABLE_WORKAROUND NRF51_ERRATA_5_PRESENT +#endif + +static bool nrf51_errata_5(void) +{ + #ifndef NRF51_SERIES + return false; + #else + return false; + #endif +} + +/* ========= Errata 6 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_6_PRESENT 1 +#else + #define NRF51_ERRATA_6_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_6_ENABLE_WORKAROUND + #define NRF51_ERRATA_6_ENABLE_WORKAROUND NRF51_ERRATA_6_PRESENT +#endif + +static bool nrf51_errata_6(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 7 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_7_PRESENT 1 +#else + #define NRF51_ERRATA_7_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_7_ENABLE_WORKAROUND + #define NRF51_ERRATA_7_ENABLE_WORKAROUND NRF51_ERRATA_7_PRESENT +#endif + +static bool nrf51_errata_7(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 8 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_8_PRESENT 1 +#else + #define NRF51_ERRATA_8_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_8_ENABLE_WORKAROUND + #define NRF51_ERRATA_8_ENABLE_WORKAROUND NRF51_ERRATA_8_PRESENT +#endif + +static bool nrf51_errata_8(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 9 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_9_PRESENT 1 +#else + #define NRF51_ERRATA_9_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_9_ENABLE_WORKAROUND + #define NRF51_ERRATA_9_ENABLE_WORKAROUND NRF51_ERRATA_9_PRESENT +#endif + +static bool nrf51_errata_9(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 10 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_10_PRESENT 1 +#else + #define NRF51_ERRATA_10_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_10_ENABLE_WORKAROUND + #define NRF51_ERRATA_10_ENABLE_WORKAROUND NRF51_ERRATA_10_PRESENT +#endif + +static bool nrf51_errata_10(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 11 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_11_PRESENT 1 +#else + #define NRF51_ERRATA_11_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_11_ENABLE_WORKAROUND + #define NRF51_ERRATA_11_ENABLE_WORKAROUND NRF51_ERRATA_11_PRESENT +#endif + +static bool nrf51_errata_11(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 12 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_12_PRESENT 1 +#else + #define NRF51_ERRATA_12_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_12_ENABLE_WORKAROUND + #define NRF51_ERRATA_12_ENABLE_WORKAROUND NRF51_ERRATA_12_PRESENT +#endif + +static bool nrf51_errata_12(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 13 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_13_PRESENT 1 +#else + #define NRF51_ERRATA_13_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_13_ENABLE_WORKAROUND + #define NRF51_ERRATA_13_ENABLE_WORKAROUND NRF51_ERRATA_13_PRESENT +#endif + +static bool nrf51_errata_13(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 14 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_14_PRESENT 1 +#else + #define NRF51_ERRATA_14_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_14_ENABLE_WORKAROUND + #define NRF51_ERRATA_14_ENABLE_WORKAROUND NRF51_ERRATA_14_PRESENT +#endif + +static bool nrf51_errata_14(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 15 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_15_PRESENT 1 +#else + #define NRF51_ERRATA_15_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_15_ENABLE_WORKAROUND + #define NRF51_ERRATA_15_ENABLE_WORKAROUND NRF51_ERRATA_15_PRESENT +#endif + +static bool nrf51_errata_15(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 16 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_16_PRESENT 1 +#else + #define NRF51_ERRATA_16_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_16_ENABLE_WORKAROUND + #define NRF51_ERRATA_16_ENABLE_WORKAROUND NRF51_ERRATA_16_PRESENT +#endif + +static bool nrf51_errata_16(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 17 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_17_PRESENT 1 +#else + #define NRF51_ERRATA_17_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_17_ENABLE_WORKAROUND + #define NRF51_ERRATA_17_ENABLE_WORKAROUND NRF51_ERRATA_17_PRESENT +#endif + +static bool nrf51_errata_17(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 18 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_18_PRESENT 1 +#else + #define NRF51_ERRATA_18_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_18_ENABLE_WORKAROUND + #define NRF51_ERRATA_18_ENABLE_WORKAROUND NRF51_ERRATA_18_PRESENT +#endif + +static bool nrf51_errata_18(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 19 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_19_PRESENT 1 +#else + #define NRF51_ERRATA_19_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_19_ENABLE_WORKAROUND + #define NRF51_ERRATA_19_ENABLE_WORKAROUND NRF51_ERRATA_19_PRESENT +#endif + +static bool nrf51_errata_19(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 20 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_20_PRESENT 1 +#else + #define NRF51_ERRATA_20_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_20_ENABLE_WORKAROUND + #define NRF51_ERRATA_20_ENABLE_WORKAROUND NRF51_ERRATA_20_PRESENT +#endif + +static bool nrf51_errata_20(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 21 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_21_PRESENT 1 +#else + #define NRF51_ERRATA_21_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_21_ENABLE_WORKAROUND + #define NRF51_ERRATA_21_ENABLE_WORKAROUND NRF51_ERRATA_21_PRESENT +#endif + +static bool nrf51_errata_21(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 22 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_22_PRESENT 1 +#else + #define NRF51_ERRATA_22_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_22_ENABLE_WORKAROUND + #define NRF51_ERRATA_22_ENABLE_WORKAROUND NRF51_ERRATA_22_PRESENT +#endif + +static bool nrf51_errata_22(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 23 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_23_PRESENT 1 +#else + #define NRF51_ERRATA_23_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_23_ENABLE_WORKAROUND + #define NRF51_ERRATA_23_ENABLE_WORKAROUND NRF51_ERRATA_23_PRESENT +#endif + +static bool nrf51_errata_23(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 24 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_24_PRESENT 1 +#else + #define NRF51_ERRATA_24_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_24_ENABLE_WORKAROUND + #define NRF51_ERRATA_24_ENABLE_WORKAROUND NRF51_ERRATA_24_PRESENT +#endif + +static bool nrf51_errata_24(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 25 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_25_PRESENT 1 +#else + #define NRF51_ERRATA_25_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_25_ENABLE_WORKAROUND + #define NRF51_ERRATA_25_ENABLE_WORKAROUND NRF51_ERRATA_25_PRESENT +#endif + +static bool nrf51_errata_25(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 26 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_26_PRESENT 1 +#else + #define NRF51_ERRATA_26_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_26_ENABLE_WORKAROUND + #define NRF51_ERRATA_26_ENABLE_WORKAROUND NRF51_ERRATA_26_PRESENT +#endif + +static bool nrf51_errata_26(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 27 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_27_PRESENT 1 +#else + #define NRF51_ERRATA_27_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_27_ENABLE_WORKAROUND + #define NRF51_ERRATA_27_ENABLE_WORKAROUND NRF51_ERRATA_27_PRESENT +#endif + +static bool nrf51_errata_27(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 28 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_28_PRESENT 1 +#else + #define NRF51_ERRATA_28_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_28_ENABLE_WORKAROUND + #define NRF51_ERRATA_28_ENABLE_WORKAROUND NRF51_ERRATA_28_PRESENT +#endif + +static bool nrf51_errata_28(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 29 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_29_PRESENT 1 +#else + #define NRF51_ERRATA_29_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_29_ENABLE_WORKAROUND + #define NRF51_ERRATA_29_ENABLE_WORKAROUND NRF51_ERRATA_29_PRESENT +#endif + +static bool nrf51_errata_29(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 30 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_30_PRESENT 1 +#else + #define NRF51_ERRATA_30_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_30_ENABLE_WORKAROUND + #define NRF51_ERRATA_30_ENABLE_WORKAROUND NRF51_ERRATA_30_PRESENT +#endif + +static bool nrf51_errata_30(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 31 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_31_PRESENT 1 +#else + #define NRF51_ERRATA_31_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_31_ENABLE_WORKAROUND + #define NRF51_ERRATA_31_ENABLE_WORKAROUND NRF51_ERRATA_31_PRESENT +#endif + +static bool nrf51_errata_31(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 32 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_32_PRESENT 1 +#else + #define NRF51_ERRATA_32_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_32_ENABLE_WORKAROUND + #define NRF51_ERRATA_32_ENABLE_WORKAROUND NRF51_ERRATA_32_PRESENT +#endif + +static bool nrf51_errata_32(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 33 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_33_PRESENT 1 +#else + #define NRF51_ERRATA_33_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_33_ENABLE_WORKAROUND + #define NRF51_ERRATA_33_ENABLE_WORKAROUND NRF51_ERRATA_33_PRESENT +#endif + +static bool nrf51_errata_33(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 34 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_34_PRESENT 1 +#else + #define NRF51_ERRATA_34_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_34_ENABLE_WORKAROUND + #define NRF51_ERRATA_34_ENABLE_WORKAROUND NRF51_ERRATA_34_PRESENT +#endif + +static bool nrf51_errata_34(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 35 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_35_PRESENT 1 +#else + #define NRF51_ERRATA_35_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_35_ENABLE_WORKAROUND + #define NRF51_ERRATA_35_ENABLE_WORKAROUND NRF51_ERRATA_35_PRESENT +#endif + +static bool nrf51_errata_35(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 36 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_36_PRESENT 1 +#else + #define NRF51_ERRATA_36_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_36_ENABLE_WORKAROUND + #define NRF51_ERRATA_36_ENABLE_WORKAROUND NRF51_ERRATA_36_PRESENT +#endif + +static bool nrf51_errata_36(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 37 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_37_PRESENT 1 +#else + #define NRF51_ERRATA_37_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_37_ENABLE_WORKAROUND + #define NRF51_ERRATA_37_ENABLE_WORKAROUND NRF51_ERRATA_37_PRESENT +#endif + +static bool nrf51_errata_37(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 38 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_38_PRESENT 1 +#else + #define NRF51_ERRATA_38_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_38_ENABLE_WORKAROUND + #define NRF51_ERRATA_38_ENABLE_WORKAROUND NRF51_ERRATA_38_PRESENT +#endif + +static bool nrf51_errata_38(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return true; + case 0x08ul: + return true; + case 0x09ul: + return true; + case 0x0Aul: + return true; + case 0x0Bul: + return true; + case 0x0Cul: + return true; + case 0x0Dul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 39 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_39_PRESENT 1 +#else + #define NRF51_ERRATA_39_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_39_ENABLE_WORKAROUND + #define NRF51_ERRATA_39_ENABLE_WORKAROUND NRF51_ERRATA_39_PRESENT +#endif + +static bool nrf51_errata_39(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 40 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_40_PRESENT 1 +#else + #define NRF51_ERRATA_40_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_40_ENABLE_WORKAROUND + #define NRF51_ERRATA_40_ENABLE_WORKAROUND NRF51_ERRATA_40_PRESENT +#endif + +static bool nrf51_errata_40(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 41 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_41_PRESENT 1 +#else + #define NRF51_ERRATA_41_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_41_ENABLE_WORKAROUND + #define NRF51_ERRATA_41_ENABLE_WORKAROUND NRF51_ERRATA_41_PRESENT +#endif + +static bool nrf51_errata_41(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 42 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_42_PRESENT 1 +#else + #define NRF51_ERRATA_42_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_42_ENABLE_WORKAROUND + #define NRF51_ERRATA_42_ENABLE_WORKAROUND NRF51_ERRATA_42_PRESENT +#endif + +static bool nrf51_errata_42(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 43 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_43_PRESENT 1 +#else + #define NRF51_ERRATA_43_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_43_ENABLE_WORKAROUND + #define NRF51_ERRATA_43_ENABLE_WORKAROUND NRF51_ERRATA_43_PRESENT +#endif + +static bool nrf51_errata_43(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 44 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_44_PRESENT 1 +#else + #define NRF51_ERRATA_44_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_44_ENABLE_WORKAROUND + #define NRF51_ERRATA_44_ENABLE_WORKAROUND NRF51_ERRATA_44_PRESENT +#endif + +static bool nrf51_errata_44(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 45 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_45_PRESENT 1 +#else + #define NRF51_ERRATA_45_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_45_ENABLE_WORKAROUND + #define NRF51_ERRATA_45_ENABLE_WORKAROUND NRF51_ERRATA_45_PRESENT +#endif + +static bool nrf51_errata_45(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 46 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_46_PRESENT 1 +#else + #define NRF51_ERRATA_46_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_46_ENABLE_WORKAROUND + #define NRF51_ERRATA_46_ENABLE_WORKAROUND NRF51_ERRATA_46_PRESENT +#endif + +static bool nrf51_errata_46(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return true; + case 0x08ul: + return true; + case 0x09ul: + return true; + case 0x0Aul: + return false; + case 0x0Bul: + return true; + case 0x0Cul: + return true; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 47 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_47_PRESENT 1 +#else + #define NRF51_ERRATA_47_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_47_ENABLE_WORKAROUND + #define NRF51_ERRATA_47_ENABLE_WORKAROUND NRF51_ERRATA_47_PRESENT +#endif + +static bool nrf51_errata_47(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 48 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_48_PRESENT 1 +#else + #define NRF51_ERRATA_48_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_48_ENABLE_WORKAROUND + #define NRF51_ERRATA_48_ENABLE_WORKAROUND NRF51_ERRATA_48_PRESENT +#endif + +static bool nrf51_errata_48(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 49 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_49_PRESENT 1 +#else + #define NRF51_ERRATA_49_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_49_ENABLE_WORKAROUND + #define NRF51_ERRATA_49_ENABLE_WORKAROUND NRF51_ERRATA_49_PRESENT +#endif + +static bool nrf51_errata_49(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 50 ========= */ +#define NRF51_ERRATA_50_PRESENT 0 + +#ifndef NRF51_ERRATA_50_ENABLE_WORKAROUND + #define NRF51_ERRATA_50_ENABLE_WORKAROUND NRF51_ERRATA_50_PRESENT +#endif + +static bool nrf51_errata_50(void) +{ + #ifndef NRF51_SERIES + return false; + #else + return false; + #endif +} + +/* ========= Errata 51 ========= */ +#define NRF51_ERRATA_51_PRESENT 0 + +#ifndef NRF51_ERRATA_51_ENABLE_WORKAROUND + #define NRF51_ERRATA_51_ENABLE_WORKAROUND NRF51_ERRATA_51_PRESENT +#endif + +static bool nrf51_errata_51(void) +{ + #ifndef NRF51_SERIES + return false; + #else + return false; + #endif +} + +/* ========= Errata 52 ========= */ +#define NRF51_ERRATA_52_PRESENT 0 + +#ifndef NRF51_ERRATA_52_ENABLE_WORKAROUND + #define NRF51_ERRATA_52_ENABLE_WORKAROUND NRF51_ERRATA_52_PRESENT +#endif + +static bool nrf51_errata_52(void) +{ + #ifndef NRF51_SERIES + return false; + #else + return false; + #endif +} + +/* ========= Errata 53 ========= */ +#define NRF51_ERRATA_53_PRESENT 0 + +#ifndef NRF51_ERRATA_53_ENABLE_WORKAROUND + #define NRF51_ERRATA_53_ENABLE_WORKAROUND NRF51_ERRATA_53_PRESENT +#endif + +static bool nrf51_errata_53(void) +{ + #ifndef NRF51_SERIES + return false; + #else + return false; + #endif +} + +/* ========= Errata 54 ========= */ +#define NRF51_ERRATA_54_PRESENT 0 + +#ifndef NRF51_ERRATA_54_ENABLE_WORKAROUND + #define NRF51_ERRATA_54_ENABLE_WORKAROUND NRF51_ERRATA_54_PRESENT +#endif + +static bool nrf51_errata_54(void) +{ + #ifndef NRF51_SERIES + return false; + #else + return false; + #endif +} + +/* ========= Errata 55 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_55_PRESENT 1 +#else + #define NRF51_ERRATA_55_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_55_ENABLE_WORKAROUND + #define NRF51_ERRATA_55_ENABLE_WORKAROUND NRF51_ERRATA_55_PRESENT +#endif + +static bool nrf51_errata_55(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 56 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_56_PRESENT 1 +#else + #define NRF51_ERRATA_56_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_56_ENABLE_WORKAROUND + #define NRF51_ERRATA_56_ENABLE_WORKAROUND NRF51_ERRATA_56_PRESENT +#endif + +static bool nrf51_errata_56(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 57 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_57_PRESENT 1 +#else + #define NRF51_ERRATA_57_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_57_ENABLE_WORKAROUND + #define NRF51_ERRATA_57_ENABLE_WORKAROUND NRF51_ERRATA_57_PRESENT +#endif + +static bool nrf51_errata_57(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 58 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_58_PRESENT 1 +#else + #define NRF51_ERRATA_58_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_58_ENABLE_WORKAROUND + #define NRF51_ERRATA_58_ENABLE_WORKAROUND NRF51_ERRATA_58_PRESENT +#endif + +static bool nrf51_errata_58(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 59 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_59_PRESENT 1 +#else + #define NRF51_ERRATA_59_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_59_ENABLE_WORKAROUND + #define NRF51_ERRATA_59_ENABLE_WORKAROUND NRF51_ERRATA_59_PRESENT +#endif + +static bool nrf51_errata_59(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 60 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_60_PRESENT 1 +#else + #define NRF51_ERRATA_60_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_60_ENABLE_WORKAROUND + #define NRF51_ERRATA_60_ENABLE_WORKAROUND NRF51_ERRATA_60_PRESENT +#endif + +static bool nrf51_errata_60(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 61 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_61_PRESENT 1 +#else + #define NRF51_ERRATA_61_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_61_ENABLE_WORKAROUND + #define NRF51_ERRATA_61_ENABLE_WORKAROUND NRF51_ERRATA_61_PRESENT +#endif + +static bool nrf51_errata_61(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return true; + case 0x08ul: + return true; + case 0x09ul: + return true; + case 0x0Aul: + return true; + case 0x0Bul: + return true; + case 0x0Cul: + return true; + case 0x0Dul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 62 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_62_PRESENT 1 +#else + #define NRF51_ERRATA_62_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_62_ENABLE_WORKAROUND + #define NRF51_ERRATA_62_ENABLE_WORKAROUND NRF51_ERRATA_62_PRESENT +#endif + +static bool nrf51_errata_62(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 63 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_63_PRESENT 1 +#else + #define NRF51_ERRATA_63_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_63_ENABLE_WORKAROUND + #define NRF51_ERRATA_63_ENABLE_WORKAROUND NRF51_ERRATA_63_PRESENT +#endif + +static bool nrf51_errata_63(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 64 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_64_PRESENT 1 +#else + #define NRF51_ERRATA_64_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_64_ENABLE_WORKAROUND + #define NRF51_ERRATA_64_ENABLE_WORKAROUND NRF51_ERRATA_64_PRESENT +#endif + +static bool nrf51_errata_64(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 65 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_65_PRESENT 1 +#else + #define NRF51_ERRATA_65_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_65_ENABLE_WORKAROUND + #define NRF51_ERRATA_65_ENABLE_WORKAROUND NRF51_ERRATA_65_PRESENT +#endif + +static bool nrf51_errata_65(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 66 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_66_PRESENT 1 +#else + #define NRF51_ERRATA_66_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_66_ENABLE_WORKAROUND + #define NRF51_ERRATA_66_ENABLE_WORKAROUND NRF51_ERRATA_66_PRESENT +#endif + +static bool nrf51_errata_66(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return true; + case 0x08ul: + return true; + case 0x09ul: + return true; + case 0x0Aul: + return false; + case 0x0Bul: + return true; + case 0x0Cul: + return true; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 67 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_67_PRESENT 1 +#else + #define NRF51_ERRATA_67_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_67_ENABLE_WORKAROUND + #define NRF51_ERRATA_67_ENABLE_WORKAROUND NRF51_ERRATA_67_PRESENT +#endif + +static bool nrf51_errata_67(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return true; + case 0x08ul: + return true; + case 0x09ul: + return true; + case 0x0Aul: + return true; + case 0x0Bul: + return true; + case 0x0Cul: + return true; + case 0x0Dul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 68 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_68_PRESENT 1 +#else + #define NRF51_ERRATA_68_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_68_ENABLE_WORKAROUND + #define NRF51_ERRATA_68_ENABLE_WORKAROUND NRF51_ERRATA_68_PRESENT +#endif + +static bool nrf51_errata_68(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 69 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_69_PRESENT 1 +#else + #define NRF51_ERRATA_69_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_69_ENABLE_WORKAROUND + #define NRF51_ERRATA_69_ENABLE_WORKAROUND NRF51_ERRATA_69_PRESENT +#endif + +static bool nrf51_errata_69(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x07ul: + return true; + case 0x08ul: + return true; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return true; + case 0x0Cul: + return true; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 70 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_70_PRESENT 1 +#else + #define NRF51_ERRATA_70_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_70_ENABLE_WORKAROUND + #define NRF51_ERRATA_70_ENABLE_WORKAROUND NRF51_ERRATA_70_PRESENT +#endif + +static bool nrf51_errata_70(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return true; + case 0x08ul: + return true; + case 0x09ul: + return true; + case 0x0Aul: + return true; + case 0x0Bul: + return true; + case 0x0Cul: + return true; + case 0x0Dul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 71 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_71_PRESENT 1 +#else + #define NRF51_ERRATA_71_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_71_ENABLE_WORKAROUND + #define NRF51_ERRATA_71_ENABLE_WORKAROUND NRF51_ERRATA_71_PRESENT +#endif + +static bool nrf51_errata_71(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x07ul: + return true; + case 0x08ul: + return true; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return true; + case 0x0Cul: + return true; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 72 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_72_PRESENT 1 +#else + #define NRF51_ERRATA_72_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_72_ENABLE_WORKAROUND + #define NRF51_ERRATA_72_ENABLE_WORKAROUND NRF51_ERRATA_72_PRESENT +#endif + +static bool nrf51_errata_72(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return true; + case 0x08ul: + return true; + case 0x09ul: + return true; + case 0x0Aul: + return true; + case 0x0Bul: + return true; + case 0x0Cul: + return true; + case 0x0Dul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 73 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_73_PRESENT 1 +#else + #define NRF51_ERRATA_73_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_73_ENABLE_WORKAROUND + #define NRF51_ERRATA_73_ENABLE_WORKAROUND NRF51_ERRATA_73_PRESENT +#endif + +static bool nrf51_errata_73(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x07ul: + return true; + case 0x08ul: + return true; + case 0x09ul: + return true; + case 0x0Aul: + return false; + case 0x0Bul: + return true; + case 0x0Cul: + return true; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 74 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_74_PRESENT 1 +#else + #define NRF51_ERRATA_74_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_74_ENABLE_WORKAROUND + #define NRF51_ERRATA_74_ENABLE_WORKAROUND NRF51_ERRATA_74_PRESENT +#endif + +static bool nrf51_errata_74(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return true; + case 0x08ul: + return true; + case 0x09ul: + return true; + case 0x0Aul: + return false; + case 0x0Bul: + return true; + case 0x0Cul: + return true; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 75 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_75_PRESENT 1 +#else + #define NRF51_ERRATA_75_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_75_ENABLE_WORKAROUND + #define NRF51_ERRATA_75_ENABLE_WORKAROUND NRF51_ERRATA_75_PRESENT +#endif + +static bool nrf51_errata_75(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return true; + case 0x08ul: + return true; + case 0x09ul: + return true; + case 0x0Aul: + return true; + case 0x0Bul: + return true; + case 0x0Cul: + return true; + case 0x0Dul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 76 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_76_PRESENT 1 +#else + #define NRF51_ERRATA_76_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_76_ENABLE_WORKAROUND + #define NRF51_ERRATA_76_ENABLE_WORKAROUND NRF51_ERRATA_76_PRESENT +#endif + +static bool nrf51_errata_76(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return true; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 77 ========= */ +#define NRF51_ERRATA_77_PRESENT 0 + +#ifndef NRF51_ERRATA_77_ENABLE_WORKAROUND + #define NRF51_ERRATA_77_ENABLE_WORKAROUND NRF51_ERRATA_77_PRESENT +#endif + +static bool nrf51_errata_77(void) +{ + #ifndef NRF51_SERIES + return false; + #else + return false; + #endif +} + +/* ========= Errata 78 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_78_PRESENT 1 +#else + #define NRF51_ERRATA_78_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_78_ENABLE_WORKAROUND + #define NRF51_ERRATA_78_ENABLE_WORKAROUND NRF51_ERRATA_78_PRESENT +#endif + +static bool nrf51_errata_78(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return true; + case 0x08ul: + return true; + case 0x09ul: + return true; + case 0x0Aul: + return false; + case 0x0Bul: + return true; + case 0x0Cul: + return true; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +#endif /* NRF51_ERRATAS_H */ diff --git a/bsp/boards/nrf52840_dk/sdk/nrf51_to_nrf52840.h b/bsp/boards/nrf52840_dk/sdk/nrf51_to_nrf52840.h new file mode 100644 index 0000000000..6352e848b3 --- /dev/null +++ b/bsp/boards/nrf52840_dk/sdk/nrf51_to_nrf52840.h @@ -0,0 +1,1342 @@ +/* + +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF51_TO_NRF52840_H +#define NRF51_TO_NRF52840_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52840 devices. + * It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the + * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros + * from the nrf51_deprecated.h file. */ + + +/* IRQ */ +/* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */ +#ifndef UART0_IRQHandler + #define UART0_IRQHandler UARTE0_UART0_IRQHandler +#endif +#ifndef SPI0_TWI0_IRQHandler + #define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#endif +#ifndef SPI1_TWI1_IRQHandler + #define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#endif +#ifndef ADC_IRQHandler + #define ADC_IRQHandler SAADC_IRQHandler +#endif +#ifndef LPCOMP_IRQHandler + #define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler +#endif +#ifndef SWI0_IRQHandler + #define SWI0_IRQHandler SWI0_EGU0_IRQHandler +#endif +#ifndef SWI1_IRQHandler + #define SWI1_IRQHandler SWI1_EGU1_IRQHandler +#endif +#ifndef SWI2_IRQHandler + #define SWI2_IRQHandler SWI2_EGU2_IRQHandler +#endif +#ifndef SWI3_IRQHandler + #define SWI3_IRQHandler SWI3_EGU3_IRQHandler +#endif +#ifndef SWI4_IRQHandler + #define SWI4_IRQHandler SWI4_EGU4_IRQHandler +#endif +#ifndef SWI5_IRQHandler + #define SWI5_IRQHandler SWI5_EGU5_IRQHandler +#endif + +#ifndef UART0_IRQn + #define UART0_IRQn UARTE0_UART0_IRQn +#endif +#ifndef SPI0_TWI0_IRQn + #define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn +#endif +#ifndef SPI1_TWI1_IRQn + #define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn +#endif +#ifndef ADC_IRQn + #define ADC_IRQn SAADC_IRQn +#endif +#ifndef LPCOMP_IRQn + #define LPCOMP_IRQn COMP_LPCOMP_IRQn +#endif +#ifndef SWI0_IRQn + #define SWI0_IRQn SWI0_EGU0_IRQn +#endif +#ifndef SWI1_IRQn + #define SWI1_IRQn SWI1_EGU1_IRQn +#endif +#ifndef SWI2_IRQn + #define SWI2_IRQn SWI2_EGU2_IRQn +#endif +#ifndef SWI3_IRQn + #define SWI3_IRQn SWI3_EGU3_IRQn +#endif +#ifndef SWI4_IRQn + #define SWI4_IRQn SWI4_EGU4_IRQn +#endif +#ifndef SWI5_IRQn + #define SWI5_IRQn SWI5_EGU5_IRQn +#endif + + +/* UICR */ +/* Register RBPCONF was renamed to APPROTECT. */ +#ifndef RBPCONF + #define RBPCONF APPROTECT +#endif + +#ifndef UICR_RBPCONF_PALL_Pos + #define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos +#endif +#ifndef UICR_RBPCONF_PALL_Msk + #define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk +#endif +#ifndef UICR_RBPCONF_PALL_Enabled + #define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled +#endif +#ifndef UICR_RBPCONF_PALL_Disabled + #define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled +#endif + + +/* GPIO */ +/* GPIO port was renamed to P0. */ +#ifndef NRF_GPIO + #define NRF_GPIO NRF_P0 +#endif +#ifndef NRF_GPIO_BASE + #define NRF_GPIO_BASE NRF_P0_BASE +#endif + + +/* QDEC */ +/* The registers PSELA, PSELB and PSELLED were restructured into a struct. */ +#ifndef PSELLED + #define PSELLED PSEL.LED +#endif +#ifndef PSELA + #define PSELA PSEL.A +#endif +#ifndef PSELB + #define PSELB PSEL.B +#endif + + +/* SPIS */ +/* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */ +#ifndef PSELSCK + #define PSELSCK PSEL.SCK +#endif +#ifndef PSELMISO + #define PSELMISO PSEL.MISO +#endif +#ifndef PSELMOSI + #define PSELMOSI PSEL.MOSI +#endif +#ifndef PSELCSN + #define PSELCSN PSEL.CSN +#endif + +/* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */ +#ifndef RXDPTR + #define RXDPTR RXD.PTR +#endif +#ifndef MAXRX + #define MAXRX RXD.MAXCNT +#endif +#ifndef AMOUNTRX + #define AMOUNTRX RXD.AMOUNT +#endif + +#ifndef SPIS_MAXRX_MAXRX_Pos + #define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos +#endif +#ifndef SPIS_MAXRX_MAXRX_Msk + #define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk +#endif + +#ifndef SPIS_AMOUNTRX_AMOUNTRX_Pos + #define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos +#endif +#ifndef SPIS_AMOUNTRX_AMOUNTRX_Msk + #define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk +#endif + +/* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */ +#ifndef TXDPTR + #define TXDPTR TXD.PTR +#endif +#ifndef MAXTX + #define MAXTX TXD.MAXCNT +#endif +#ifndef AMOUNTTX + #define AMOUNTTX TXD.AMOUNT +#endif + +#ifndef SPIS_MAXTX_MAXTX_Pos + #define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos +#endif +#ifndef SPIS_MAXTX_MAXTX_Msk + #define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk +#endif + +#ifndef SPIS_AMOUNTTX_AMOUNTTX_Pos + #define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos +#endif +#ifndef SPIS_AMOUNTTX_AMOUNTTX_Msk + #define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk +#endif + + +/* UART */ +/* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */ +#ifndef PSELRTS + #define PSELRTS PSEL.RTS +#endif +#ifndef PSELTXD + #define PSELTXD PSEL.TXD +#endif +#ifndef PSELCTS + #define PSELCTS PSEL.CTS +#endif +#ifndef PSELRXD + #define PSELRXD PSEL.RXD +#endif + +/* TWI */ +/* The registers PSELSCL, PSELSDA were restructured into a struct. */ +#ifndef PSELSCL + #define PSELSCL PSEL.SCL +#endif +#ifndef PSELSDA + #define PSELSDA PSEL.SDA +#endif + + +/* From nrf51_deprecated.h */ + +/* NVMC */ +/* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */ +#ifndef ERASEPROTECTEDPAGE + #define ERASEPROTECTEDPAGE ERASEPCR0 +#endif + + +/* IRQ */ +/* COMP module was eliminated. Adapted to nrf52840 headers. */ +#ifndef LPCOMP_COMP_IRQHandler + #define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler +#endif +#ifndef LPCOMP_COMP_IRQn + #define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn +#endif + + +/* REFSEL register redefined enumerated values and added some more. */ +#ifndef LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling LPCOMP_REFSEL_REFSEL_Ref1_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref2_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref3_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref4_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref5_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref6_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref7_8Vdd +#endif + + +/* RADIO */ +/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ +#ifndef RADIO_CRCCNF_SKIP_ADDR_Pos + #define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos +#endif +#ifndef RADIO_CRCCNF_SKIP_ADDR_Msk + #define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk +#endif +#ifndef RADIO_CRCCNF_SKIP_ADDR_Include + #define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include +#endif +#ifndef RADIO_CRCCNF_SKIP_ADDR_Skip + #define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip +#endif + + +/* FICR */ +/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ +#ifndef DEVICEID0 + #define DEVICEID0 DEVICEID[0] +#endif +#ifndef DEVICEID1 + #define DEVICEID1 DEVICEID[1] +#endif + +/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ +#ifndef ER0 + #define ER0 ER[0] +#endif +#ifndef ER1 + #define ER1 ER[1] +#endif +#ifndef ER2 + #define ER2 ER[2] +#endif +#ifndef ER3 + #define ER3 ER[3] +#endif + +/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ +#ifndef IR0 + #define IR0 IR[0] +#endif +#ifndef IR1 + #define IR1 IR[1] +#endif +#ifndef IR2 + #define IR2 IR[2] +#endif +#ifndef IR3 + #define IR3 IR[3] +#endif + +/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ +#ifndef DEVICEADDR0 + #define DEVICEADDR0 DEVICEADDR[0] +#endif +#ifndef DEVICEADDR1 + #define DEVICEADDR1 DEVICEADDR[1] +#endif + + +/* PPI */ +/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ +#ifndef TASKS_CHG0EN + #define TASKS_CHG0EN TASKS_CHG[0].EN +#endif +#ifndef TASKS_CHG0DIS + #define TASKS_CHG0DIS TASKS_CHG[0].DIS +#endif +#ifndef TASKS_CHG1EN + #define TASKS_CHG1EN TASKS_CHG[1].EN +#endif +#ifndef TASKS_CHG1DIS + #define TASKS_CHG1DIS TASKS_CHG[1].DIS +#endif +#ifndef TASKS_CHG2EN + #define TASKS_CHG2EN TASKS_CHG[2].EN +#endif +#ifndef TASKS_CHG2DIS + #define TASKS_CHG2DIS TASKS_CHG[2].DIS +#endif +#ifndef TASKS_CHG3EN + #define TASKS_CHG3EN TASKS_CHG[3].EN +#endif +#ifndef TASKS_CHG3DIS + #define TASKS_CHG3DIS TASKS_CHG[3].DIS +#endif + +/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ +#ifndef CH0_EEP + #define CH0_EEP CH[0].EEP +#endif +#ifndef CH0_TEP + #define CH0_TEP CH[0].TEP +#endif +#ifndef CH1_EEP + #define CH1_EEP CH[1].EEP +#endif +#ifndef CH1_TEP + #define CH1_TEP CH[1].TEP +#endif +#ifndef CH2_EEP + #define CH2_EEP CH[2].EEP +#endif +#ifndef CH2_TEP + #define CH2_TEP CH[2].TEP +#endif +#ifndef CH3_EEP + #define CH3_EEP CH[3].EEP +#endif +#ifndef CH3_TEP + #define CH3_TEP CH[3].TEP +#endif +#ifndef CH4_EEP + #define CH4_EEP CH[4].EEP +#endif +#ifndef CH4_TEP + #define CH4_TEP CH[4].TEP +#endif +#ifndef CH5_EEP + #define CH5_EEP CH[5].EEP +#endif +#ifndef CH5_TEP + #define CH5_TEP CH[5].TEP +#endif +#ifndef CH6_EEP + #define CH6_EEP CH[6].EEP +#endif +#ifndef CH6_TEP + #define CH6_TEP CH[6].TEP +#endif +#ifndef CH7_EEP + #define CH7_EEP CH[7].EEP +#endif +#ifndef CH7_TEP + #define CH7_TEP CH[7].TEP +#endif +#ifndef CH8_EEP + #define CH8_EEP CH[8].EEP +#endif +#ifndef CH8_TEP + #define CH8_TEP CH[8].TEP +#endif +#ifndef CH9_EEP + #define CH9_EEP CH[9].EEP +#endif +#ifndef CH9_TEP + #define CH9_TEP CH[9].TEP +#endif +#ifndef CH10_EEP + #define CH10_EEP CH[10].EEP +#endif +#ifndef CH10_TEP + #define CH10_TEP CH[10].TEP +#endif +#ifndef CH11_EEP + #define CH11_EEP CH[11].EEP +#endif +#ifndef CH11_TEP + #define CH11_TEP CH[11].TEP +#endif +#ifndef CH12_EEP + #define CH12_EEP CH[12].EEP +#endif +#ifndef CH12_TEP + #define CH12_TEP CH[12].TEP +#endif +#ifndef CH13_EEP + #define CH13_EEP CH[13].EEP +#endif +#ifndef CH13_TEP + #define CH13_TEP CH[13].TEP +#endif +#ifndef CH14_EEP + #define CH14_EEP CH[14].EEP +#endif +#ifndef CH14_TEP + #define CH14_TEP CH[14].TEP +#endif +#ifndef CH15_EEP + #define CH15_EEP CH[15].EEP +#endif +#ifndef CH15_TEP + #define CH15_TEP CH[15].TEP +#endif + +/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ +#ifndef CHG0 + #define CHG0 CHG[0] +#endif +#ifndef CHG1 + #define CHG1 CHG[1] +#endif +#ifndef CHG2 + #define CHG2 CHG[2] +#endif +#ifndef CHG3 + #define CHG3 CHG[3] +#endif + +/* All bitfield macros for the CHGx registers therefore changed name. */ +#ifndef PPI_CHG0_CH15_Pos + #define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG0_CH15_Msk + #define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG0_CH15_Excluded + #define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG0_CH15_Included + #define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG0_CH14_Pos + #define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG0_CH14_Msk + #define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG0_CH14_Excluded + #define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG0_CH14_Included + #define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG0_CH13_Pos + #define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG0_CH13_Msk + #define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG0_CH13_Excluded + #define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG0_CH13_Included + #define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG0_CH12_Pos + #define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG0_CH12_Msk + #define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG0_CH12_Excluded + #define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG0_CH12_Included + #define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG0_CH11_Pos + #define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG0_CH11_Msk + #define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG0_CH11_Excluded + #define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG0_CH11_Included + #define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG0_CH10_Pos + #define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG0_CH10_Msk + #define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG0_CH10_Excluded + #define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG0_CH10_Included + #define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG0_CH9_Pos + #define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG0_CH9_Msk + #define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG0_CH9_Excluded + #define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG0_CH9_Included + #define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG0_CH8_Pos + #define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG0_CH8_Msk + #define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG0_CH8_Excluded + #define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG0_CH8_Included + #define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG0_CH7_Pos + #define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG0_CH7_Msk + #define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG0_CH7_Excluded + #define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG0_CH7_Included + #define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG0_CH6_Pos + #define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG0_CH6_Msk + #define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG0_CH6_Excluded + #define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG0_CH6_Included + #define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG0_CH5_Pos + #define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG0_CH5_Msk + #define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG0_CH5_Excluded + #define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG0_CH5_Included + #define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG0_CH4_Pos + #define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG0_CH4_Msk + #define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG0_CH4_Excluded + #define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG0_CH4_Included + #define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG0_CH3_Pos + #define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG0_CH3_Msk + #define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG0_CH3_Excluded + #define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG0_CH3_Included + #define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG0_CH2_Pos + #define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG0_CH2_Msk + #define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG0_CH2_Excluded + #define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG0_CH2_Included + #define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG0_CH1_Pos + #define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG0_CH1_Msk + #define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG0_CH1_Excluded + #define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG0_CH1_Included + #define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG0_CH0_Pos + #define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG0_CH0_Msk + #define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG0_CH0_Excluded + #define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG0_CH0_Included + #define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included +#endif + +#ifndef PPI_CHG1_CH15_Pos + #define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG1_CH15_Msk + #define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG1_CH15_Excluded + #define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG1_CH15_Included + #define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG1_CH14_Pos + #define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG1_CH14_Msk + #define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG1_CH14_Excluded + #define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG1_CH14_Included + #define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG1_CH13_Pos + #define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG1_CH13_Msk + #define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG1_CH13_Excluded + #define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG1_CH13_Included + #define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG1_CH12_Pos + #define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG1_CH12_Msk + #define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG1_CH12_Excluded + #define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG1_CH12_Included + #define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG1_CH11_Pos + #define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG1_CH11_Msk + #define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG1_CH11_Excluded + #define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG1_CH11_Included + #define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG1_CH10_Pos + #define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG1_CH10_Msk + #define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG1_CH10_Excluded + #define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG1_CH10_Included + #define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG1_CH9_Pos + #define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG1_CH9_Msk + #define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG1_CH9_Excluded + #define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG1_CH9_Included + #define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG1_CH8_Pos + #define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG1_CH8_Msk + #define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG1_CH8_Excluded + #define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG1_CH8_Included + #define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG1_CH7_Pos + #define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG1_CH7_Msk + #define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG1_CH7_Excluded + #define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG1_CH7_Included + #define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG1_CH6_Pos + #define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG1_CH6_Msk + #define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG1_CH6_Excluded + #define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG1_CH6_Included + #define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG1_CH5_Pos + #define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG1_CH5_Msk + #define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG1_CH5_Excluded + #define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG1_CH5_Included + #define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG1_CH4_Pos + #define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG1_CH4_Msk + #define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG1_CH4_Excluded + #define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG1_CH4_Included + #define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG1_CH3_Pos + #define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG1_CH3_Msk + #define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG1_CH3_Excluded + #define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG1_CH3_Included + #define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG1_CH2_Pos + #define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG1_CH2_Msk + #define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG1_CH2_Excluded + #define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG1_CH2_Included + #define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG1_CH1_Pos + #define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG1_CH1_Msk + #define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG1_CH1_Excluded + #define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG1_CH1_Included + #define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG1_CH0_Pos + #define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG1_CH0_Msk + #define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG1_CH0_Excluded + #define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG1_CH0_Included + #define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included +#endif + +#ifndef PPI_CHG2_CH15_Pos + #define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG2_CH15_Msk + #define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG2_CH15_Excluded + #define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG2_CH15_Included + #define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG2_CH14_Pos + #define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG2_CH14_Msk + #define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG2_CH14_Excluded + #define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG2_CH14_Included + #define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG2_CH13_Pos + #define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG2_CH13_Msk + #define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG2_CH13_Excluded + #define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG2_CH13_Included + #define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG2_CH12_Pos + #define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG2_CH12_Msk + #define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG2_CH12_Excluded + #define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG2_CH12_Included + #define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG2_CH11_Pos + #define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG2_CH11_Msk + #define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG2_CH11_Excluded + #define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG2_CH11_Included + #define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG2_CH10_Pos + #define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG2_CH10_Msk + #define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG2_CH10_Excluded + #define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG2_CH10_Included + #define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG2_CH9_Pos + #define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG2_CH9_Msk + #define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG2_CH9_Excluded + #define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG2_CH9_Included + #define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG2_CH8_Pos + #define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG2_CH8_Msk + #define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG2_CH8_Excluded + #define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG2_CH8_Included + #define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG2_CH7_Pos + #define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG2_CH7_Msk + #define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG2_CH7_Excluded + #define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG2_CH7_Included + #define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG2_CH6_Pos + #define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG2_CH6_Msk + #define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG2_CH6_Excluded + #define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG2_CH6_Included + #define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG2_CH5_Pos + #define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG2_CH5_Msk + #define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG2_CH5_Excluded + #define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG2_CH5_Included + #define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG2_CH4_Pos + #define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG2_CH4_Msk + #define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG2_CH4_Excluded + #define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG2_CH4_Included + #define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG2_CH3_Pos + #define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG2_CH3_Msk + #define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG2_CH3_Excluded + #define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG2_CH3_Included + #define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG2_CH2_Pos + #define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG2_CH2_Msk + #define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG2_CH2_Excluded + #define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG2_CH2_Included + #define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG2_CH1_Pos + #define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG2_CH1_Msk + #define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG2_CH1_Excluded + #define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG2_CH1_Included + #define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG2_CH0_Pos + #define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG2_CH0_Msk + #define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG2_CH0_Excluded + #define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG2_CH0_Included + #define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included +#endif + +#ifndef PPI_CHG3_CH15_Pos + #define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG3_CH15_Msk + #define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG3_CH15_Excluded + #define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG3_CH15_Included + #define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG3_CH14_Pos + #define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG3_CH14_Msk + #define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG3_CH14_Excluded + #define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG3_CH14_Included + #define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG3_CH13_Pos + #define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG3_CH13_Msk + #define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG3_CH13_Excluded + #define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG3_CH13_Included + #define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG3_CH12_Pos + #define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG3_CH12_Msk + #define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG3_CH12_Excluded + #define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG3_CH12_Included + #define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG3_CH11_Pos + #define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG3_CH11_Msk + #define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG3_CH11_Excluded + #define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG3_CH11_Included + #define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG3_CH10_Pos + #define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG3_CH10_Msk + #define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG3_CH10_Excluded + #define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG3_CH10_Included + #define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG3_CH9_Pos + #define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG3_CH9_Msk + #define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG3_CH9_Excluded + #define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG3_CH9_Included + #define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG3_CH8_Pos + #define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG3_CH8_Msk + #define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG3_CH8_Excluded + #define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG3_CH8_Included + #define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG3_CH7_Pos + #define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG3_CH7_Msk + #define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG3_CH7_Excluded + #define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG3_CH7_Included + #define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG3_CH6_Pos + #define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG3_CH6_Msk + #define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG3_CH6_Excluded + #define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG3_CH6_Included + #define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG3_CH5_Pos + #define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG3_CH5_Msk + #define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG3_CH5_Excluded + #define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG3_CH5_Included + #define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG3_CH4_Pos + #define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG3_CH4_Msk + #define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG3_CH4_Excluded + #define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG3_CH4_Included + #define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG3_CH3_Pos + #define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG3_CH3_Msk + #define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG3_CH3_Excluded + #define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG3_CH3_Included + #define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG3_CH2_Pos + #define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG3_CH2_Msk + #define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG3_CH2_Excluded + #define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG3_CH2_Included + #define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG3_CH1_Pos + #define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG3_CH1_Msk + #define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG3_CH1_Excluded + #define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG3_CH1_Included + #define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG3_CH0_Pos + #define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG3_CH0_Msk + #define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG3_CH0_Excluded + #define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG3_CH0_Included + #define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included +#endif + + + + + +/*lint --flb "Leave library region" */ + +#endif /* NRF51_TO_NRF52840_H */ + diff --git a/bsp/boards/nrf52840_dk/sdk/nrf52840.h b/bsp/boards/nrf52840_dk/sdk/nrf52840.h new file mode 100644 index 0000000000..9919f1b304 --- /dev/null +++ b/bsp/boards/nrf52840_dk/sdk/nrf52840.h @@ -0,0 +1,2958 @@ +/* + * Copyright (c) 2010 - 2021, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @file nrf52840.h + * @brief CMSIS HeaderFile + * @version 1 + * @date 14. May 2021 + * @note Generated by SVDConv V3.3.35 on Friday, 14.05.2021 15:32:44 + * from File 'nrf52840.svd', + * last modified on Friday, 14.05.2021 13:32:37 + */ + + + +/** @addtogroup Nordic Semiconductor + * @{ + */ + + +/** @addtogroup nrf52840 + * @{ + */ + + +#ifndef NRF52840_H +#define NRF52840_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ========================================== nrf52840 Specific Interrupt Numbers ========================================== */ + POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ + RADIO_IRQn = 1, /*!< 1 RADIO */ + UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ + NFCT_IRQn = 5, /*!< 5 NFCT */ + GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ + SAADC_IRQn = 7, /*!< 7 SAADC */ + TIMER0_IRQn = 8, /*!< 8 TIMER0 */ + TIMER1_IRQn = 9, /*!< 9 TIMER1 */ + TIMER2_IRQn = 10, /*!< 10 TIMER2 */ + RTC0_IRQn = 11, /*!< 11 RTC0 */ + TEMP_IRQn = 12, /*!< 12 TEMP */ + RNG_IRQn = 13, /*!< 13 RNG */ + ECB_IRQn = 14, /*!< 14 ECB */ + CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ + WDT_IRQn = 16, /*!< 16 WDT */ + RTC1_IRQn = 17, /*!< 17 RTC1 */ + QDEC_IRQn = 18, /*!< 18 QDEC */ + COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */ + SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ + SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ + SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ + SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ + SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ + SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ + TIMER3_IRQn = 26, /*!< 26 TIMER3 */ + TIMER4_IRQn = 27, /*!< 27 TIMER4 */ + PWM0_IRQn = 28, /*!< 28 PWM0 */ + PDM_IRQn = 29, /*!< 29 PDM */ + MWU_IRQn = 32, /*!< 32 MWU */ + PWM1_IRQn = 33, /*!< 33 PWM1 */ + PWM2_IRQn = 34, /*!< 34 PWM2 */ + SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */ + RTC2_IRQn = 36, /*!< 36 RTC2 */ + I2S_IRQn = 37, /*!< 37 I2S */ + FPU_IRQn = 38, /*!< 38 FPU */ + USBD_IRQn = 39, /*!< 39 USBD */ + UARTE1_IRQn = 40, /*!< 40 UARTE1 */ + QSPI_IRQn = 41, /*!< 41 QSPI */ + CRYPTOCELL_IRQn = 42, /*!< 42 CRYPTOCELL */ + PWM3_IRQn = 45, /*!< 45 PWM3 */ + SPIM3_IRQn = 47 /*!< 47 SPIM3 */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __DSP_PRESENT 1 /*!< DSP present or not */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /*!< MPU present */ +#define __FPU_PRESENT 1 /*!< FPU present */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ +#include "system_nrf52840.h" /*!< nrf52840 System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + + +/** + * @brief FICR_INFO [INFO] (Device info) + */ +typedef struct { + __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ + __IM uint32_t VARIANT; /*!< (@ 0x00000004) Build code (hardware version and production configuration) */ + __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ + __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ + __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ +} FICR_INFO_Type; /*!< Size = 20 (0x14) */ + + +/** + * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) + */ +typedef struct { + __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0 */ + __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1 */ + __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2 */ + __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3 */ + __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4 */ + __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5 */ + __IM uint32_t B0; /*!< (@ 0x00000018) Y-intercept B0 */ + __IM uint32_t B1; /*!< (@ 0x0000001C) Y-intercept B1 */ + __IM uint32_t B2; /*!< (@ 0x00000020) Y-intercept B2 */ + __IM uint32_t B3; /*!< (@ 0x00000024) Y-intercept B3 */ + __IM uint32_t B4; /*!< (@ 0x00000028) Y-intercept B4 */ + __IM uint32_t B5; /*!< (@ 0x0000002C) Y-intercept B5 */ + __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0 */ + __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1 */ + __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2 */ + __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3 */ + __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4 */ +} FICR_TEMP_Type; /*!< Size = 68 (0x44) */ + + +/** + * @brief FICR_NFC [NFC] (Unspecified) + */ +typedef struct { + __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST, and NFCID1_LAST. */ + __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST, and NFCID1_LAST. */ + __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST, and NFCID1_LAST. */ + __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST, and NFCID1_LAST. */ +} FICR_NFC_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief FICR_TRNG90B [TRNG90B] (NIST800-90B RNG calibration data) + */ +typedef struct { + __IM uint32_t BYTES; /*!< (@ 0x00000000) Amount of bytes for the required entropy bits */ + __IM uint32_t RCCUTOFF; /*!< (@ 0x00000004) Repetition counter cutoff */ + __IM uint32_t APCUTOFF; /*!< (@ 0x00000008) Adaptive proportion cutoff */ + __IM uint32_t STARTUP; /*!< (@ 0x0000000C) Amount of bytes for the startup tests */ + __IM uint32_t ROSC1; /*!< (@ 0x00000010) Sample count for ring oscillator 1 */ + __IM uint32_t ROSC2; /*!< (@ 0x00000014) Sample count for ring oscillator 2 */ + __IM uint32_t ROSC3; /*!< (@ 0x00000018) Sample count for ring oscillator 3 */ + __IM uint32_t ROSC4; /*!< (@ 0x0000001C) Sample count for ring oscillator 4 */ +} FICR_TRNG90B_Type; /*!< Size = 32 (0x20) */ + + +/** + * @brief POWER_RAM [RAM] (Unspecified) + */ +typedef struct { + __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register */ + __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */ + __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear + register */ + __IM uint32_t RESERVED; +} POWER_RAM_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief UART_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS */ + __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD */ + __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS */ + __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD */ +} UART_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief UARTE_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ + __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ + __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ + __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ +} UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} UARTE_RXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} UARTE_TXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SPI_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ + __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ +} SPI_PSEL_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SPIM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ + __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ + __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN */ +} SPIM_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIM_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIM_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIM_IFTIMING [IFTIMING] (Unspecified) + */ +typedef struct { + __IOM uint32_t RXDELAY; /*!< (@ 0x00000000) Sample delay for input serial data on MISO */ + __IOM uint32_t CSNDUR; /*!< (@ 0x00000004) Minimum duration between edge of CSN and edge + of SCK and minimum duration CSN must stay + high between transactions */ +} SPIM_IFTIMING_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief SPIS_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ + __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ + __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ +} SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIS_RXD [RXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIS_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIS_TXD [TXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIS_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWI_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA */ +} TWI_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief TWIM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ +} TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIM_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIM_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWIS_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ +} TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIS_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIS_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief NFCT_FRAMESTATUS [FRAMESTATUS] (Unspecified) + */ +typedef struct { + __IOM uint32_t RX; /*!< (@ 0x00000000) Result of last incoming frame */ +} NFCT_FRAMESTATUS_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief NFCT_TXD [TXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of outgoing frames */ + __IOM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of outgoing frame */ +} NFCT_TXD_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief NFCT_RXD [RXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of incoming frames */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of last incoming frame */ +} NFCT_RXD_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.) + */ +typedef struct { + __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last result is equal or + above CH[n].LIMIT.HIGH */ + __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last result is equal or + below CH[n].LIMIT.LOW */ +} SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief SAADC_CH [CH] (Unspecified) + */ +typedef struct { + __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection + for CH[n] */ + __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection + for CH[n] */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for + CH[n] */ + __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event + monitoring of a channel */ +} SAADC_CH_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of 16-bit samples to be written + to output RAM buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of 16-bit samples written to output RAM + buffer since the previous START task */ +} SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief QDEC_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ + __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ + __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ +} QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief PWM_SEQ [SEQ] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in RAM + of this sequence */ + __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Number of values (duty cycles) + in this sequence */ + __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of additional PWM + periods between samples loaded into compare + register */ + __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */ + __IM uint32_t RESERVED[4]; +} PWM_SEQ_Type; /*!< Size = 32 (0x20) */ + + +/** + * @brief PWM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for + PWM channel n */ +} PWM_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief PDM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ + __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ +} PDM_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PDM_SAMPLE [SAMPLE] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with + EasyDMA */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA + mode */ +} PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief ACL_ACL [ACL] (Unspecified) + */ +typedef struct { + __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Start address of region + to protect. The start address must be word-aligned. */ + __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Size of region to protect + counting from address ACL[n].ADDR. Write + '0' as no effect. */ + __IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster: Access permissions for region + n as defined by start address ACL[n].ADDR + and size ACL[n].SIZE */ + __IM uint32_t RESERVED; +} ACL_ACL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) + */ +typedef struct { + __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ + __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ +} PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PPI_CH [CH] (PPI Channel) + */ +typedef struct { + __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event endpoint */ + __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task endpoint */ +} PPI_CH_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PPI_FORK [FORK] (Fork) + */ +typedef struct { + __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task endpoint */ +} PPI_FORK_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Peripheral events.) + */ +typedef struct { + __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster: Write access to region n + detected */ + __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access to region n + detected */ +} MWU_EVENTS_REGION_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Peripheral events.) + */ +typedef struct { + __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster: Write access to peripheral + region n detected */ + __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access to peripheral + region n detected */ +} MWU_EVENTS_PREGION_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief MWU_PERREGION [PERREGION] (Unspecified) + */ +typedef struct { + __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster: Source of event/interrupt + in region n, write access detected while + corresponding subregion was enabled for + watching */ + __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster: Source of event/interrupt + in region n, read access detected while + corresponding subregion was enabled for + watching */ +} MWU_PERREGION_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief MWU_REGION [REGION] (Unspecified) + */ +typedef struct { + __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster: Start address for region + n */ + __IOM uint32_t END; /*!< (@ 0x00000004) Description cluster: End address of region n */ + __IM uint32_t RESERVED[2]; +} MWU_REGION_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief MWU_PREGION [PREGION] (Unspecified) + */ +typedef struct { + __IM uint32_t START; /*!< (@ 0x00000000) Description cluster: Reserved for future use */ + __IM uint32_t END; /*!< (@ 0x00000004) Description cluster: Reserved for future use */ + __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster: Subregions of region n */ + __IM uint32_t RESERVED; +} MWU_PREGION_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief I2S_CONFIG [CONFIG] (Unspecified) + */ +typedef struct { + __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */ + __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */ + __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */ + __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */ + __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */ + __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */ + __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */ + __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */ + __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */ + __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */ +} I2S_CONFIG_Type; /*!< Size = 40 (0x28) */ + + +/** + * @brief I2S_RXD [RXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ +} I2S_RXD_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief I2S_TXD [TXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */ +} I2S_TXD_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief I2S_RXTXD [RXTXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */ +} I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief I2S_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */ + __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */ + __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */ + __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */ + __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */ +} I2S_PSEL_Type; /*!< Size = 20 (0x14) */ + + +/** + * @brief USBD_HALTED [HALTED] (Unspecified) + */ +typedef struct { + __IM uint32_t EPIN[8]; /*!< (@ 0x00000000) Description collection: IN endpoint halted status. + Can be used as is as response to a GetStatus() + request to endpoint. */ + __IM uint32_t RESERVED; + __IM uint32_t EPOUT[8]; /*!< (@ 0x00000024) Description collection: OUT endpoint halted status. + Can be used as is as response to a GetStatus() + request to endpoint. */ +} USBD_HALTED_Type; /*!< Size = 68 (0x44) */ + + +/** + * @brief USBD_SIZE [SIZE] (Unspecified) + */ +typedef struct { + __IOM uint32_t EPOUT[8]; /*!< (@ 0x00000000) Description collection: Number of bytes received + last in the data stage of this OUT endpoint */ + __IM uint32_t ISOOUT; /*!< (@ 0x00000020) Number of bytes received last on this ISO OUT + data endpoint */ +} USBD_SIZE_Type; /*!< Size = 36 (0x24) */ + + +/** + * @brief USBD_EPIN [EPIN] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes + to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred + in the last transaction */ + __IM uint32_t RESERVED[2]; +} USBD_EPIN_Type; /*!< Size = 20 (0x14) */ + + +/** + * @brief USBD_ISOIN [ISOIN] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} USBD_ISOIN_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief USBD_EPOUT [EPOUT] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes + to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred + in the last transaction */ + __IM uint32_t RESERVED[2]; +} USBD_EPOUT_Type; /*!< Size = 20 (0x14) */ + + +/** + * @brief USBD_ISOOUT [ISOOUT] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} USBD_ISOOUT_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief QSPI_READ [READ] (Unspecified) + */ +typedef struct { + __IOM uint32_t SRC; /*!< (@ 0x00000000) Flash memory source address */ + __IOM uint32_t DST; /*!< (@ 0x00000004) RAM destination address */ + __IOM uint32_t CNT; /*!< (@ 0x00000008) Read transfer length */ +} QSPI_READ_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief QSPI_WRITE [WRITE] (Unspecified) + */ +typedef struct { + __IOM uint32_t DST; /*!< (@ 0x00000000) Flash destination address */ + __IOM uint32_t SRC; /*!< (@ 0x00000004) RAM source address */ + __IOM uint32_t CNT; /*!< (@ 0x00000008) Write transfer length */ +} QSPI_WRITE_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief QSPI_ERASE [ERASE] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Start address of flash block to be erased */ + __IOM uint32_t LEN; /*!< (@ 0x00000004) Size of block to be erased. */ +} QSPI_ERASE_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief QSPI_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for serial clock SCK */ + __IOM uint32_t CSN; /*!< (@ 0x00000004) Pin select for chip select signal CSN. */ + __IM uint32_t RESERVED; + __IOM uint32_t IO0; /*!< (@ 0x0000000C) Pin select for serial data MOSI/IO0. */ + __IOM uint32_t IO1; /*!< (@ 0x00000010) Pin select for serial data MISO/IO1. */ + __IOM uint32_t IO2; /*!< (@ 0x00000014) Pin select for serial data IO2. */ + __IOM uint32_t IO3; /*!< (@ 0x00000018) Pin select for serial data IO3. */ +} QSPI_PSEL_Type; /*!< Size = 28 (0x1c) */ + + +/** @} */ /* End of group Device_Peripheral_clusters */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ FICR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Factory information configuration registers (FICR) + */ + +typedef struct { /*!< (@ 0x10000000) FICR Structure */ + __IM uint32_t RESERVED[4]; + __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ + __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ + __IM uint32_t RESERVED1[18]; + __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection: Device identifier */ + __IM uint32_t RESERVED2[6]; + __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection: Encryption root, word + n */ + __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection: Identity Root, word n */ + __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ + __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection: Device address n */ + __IM uint32_t RESERVED3[21]; + __IM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ + __IM uint32_t RESERVED4[143]; + __IM uint32_t PRODTEST[3]; /*!< (@ 0x00000350) Description collection: Production test signature + n */ + __IM uint32_t RESERVED5[42]; + __IM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization + coefficients */ + __IM uint32_t RESERVED6[2]; + __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */ + __IM uint32_t RESERVED7[488]; + __IOM FICR_TRNG90B_Type TRNG90B; /*!< (@ 0x00000C00) NIST800-90B RNG calibration data */ +} NRF_FICR_Type; /*!< Size = 3104 (0xc20) */ + + + +/* =========================================================================================================================== */ +/* ================ UICR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief User information configuration registers (UICR) + */ + +typedef struct { /*!< (@ 0x10001000) UICR Structure */ + __IM uint32_t RESERVED[5]; + __IOM uint32_t NRFFW[13]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware + design */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware + design */ + __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET + function (see POWER chapter for details) */ + __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ + __IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality: + NFC antenna or GPIO */ + __IOM uint32_t DEBUGCTRL; /*!< (@ 0x00000210) Processor debug control */ + __IM uint32_t RESERVED3[60]; + __IOM uint32_t REGOUT0; /*!< (@ 0x00000304) Output voltage from REG0 regulator stage. The + maximum output voltage from this stage is + given as VDDH - V_VDDH-VDD. */ +} NRF_UICR_Type; /*!< Size = 776 (0x308) */ + + + +/* =========================================================================================================================== */ +/* ================ APPROTECT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Access Port Protection (APPROTECT) + */ + +typedef struct { /*!< (@ 0x40000000) APPROTECT Structure */ + __IM uint32_t RESERVED[340]; + __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000550) Software force enable APPROTECT mechanism until + next reset. */ + __IM uint32_t RESERVED1; + __IOM uint32_t DISABLE; /*!< (@ 0x00000558) Software disable APPROTECT mechanism */ +} NRF_APPROTECT_Type; /*!< Size = 1372 (0x55c) */ + + + +/* =========================================================================================================================== */ +/* ================ CLOCK ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Clock control (CLOCK) + */ + +typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ + __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFXO crystal oscillator */ + __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFXO crystal oscillator */ + __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK */ + __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK */ + __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC */ + __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ + __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ + __IM uint32_t RESERVED[57]; + __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFXO crystal oscillator started */ + __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ + __IM uint32_t RESERVED1; + __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFRC completed */ + __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ + __IM uint32_t RESERVED2[5]; + __IOM uint32_t EVENTS_CTSTARTED; /*!< (@ 0x00000128) Calibration timer has been started and is ready + to process new tasks */ + __IOM uint32_t EVENTS_CTSTOPPED; /*!< (@ 0x0000012C) Calibration timer has been stopped and is ready + to process new tasks */ + __IM uint32_t RESERVED3[117]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[63]; + __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been + triggered */ + __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ + __IM uint32_t RESERVED5; + __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been + triggered */ + __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ + __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART + task was triggered */ + __IM uint32_t RESERVED6[62]; + __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ + __IM uint32_t RESERVED7[3]; + __IOM uint32_t HFXODEBOUNCE; /*!< (@ 0x00000528) HFXO debounce time. The HFXO is started by triggering + the TASKS_HFCLKSTART task. */ + __IM uint32_t RESERVED8[3]; + __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ + __IM uint32_t RESERVED9[8]; + __IOM uint32_t TRACECONFIG; /*!< (@ 0x0000055C) Clocking options for the trace port debug interface */ + __IM uint32_t RESERVED10[21]; + __IOM uint32_t LFRCMODE; /*!< (@ 0x000005B4) LFRC mode configuration */ +} NRF_CLOCK_Type; /*!< Size = 1464 (0x5b8) */ + + + +/* =========================================================================================================================== */ +/* ================ POWER ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Power control (POWER) + */ + +typedef struct { /*!< (@ 0x40000000) POWER Structure */ + __IM uint32_t RESERVED[30]; + __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */ + __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-power mode (variable latency) */ + __IM uint32_t RESERVED1[34]; + __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ + __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ + __IOM uint32_t EVENTS_USBDETECTED; /*!< (@ 0x0000011C) Voltage supply detected on VBUS */ + __IOM uint32_t EVENTS_USBREMOVED; /*!< (@ 0x00000120) Voltage supply removed from VBUS */ + __IOM uint32_t EVENTS_USBPWRRDY; /*!< (@ 0x00000124) USB 3.3 V supply ready */ + __IM uint32_t RESERVED3[119]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[61]; + __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ + __IM uint32_t RESERVED5[9]; + __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Deprecated register - RAM status register */ + __IM uint32_t RESERVED6[3]; + __IM uint32_t USBREGSTATUS; /*!< (@ 0x00000438) USB supply status */ + __IM uint32_t RESERVED7[49]; + __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ + __IM uint32_t RESERVED8[3]; + __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power-fail comparator configuration */ + __IM uint32_t RESERVED9[2]; + __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ + __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ + __IM uint32_t RESERVED10[21]; + __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC converter for REG1 stage */ + __IM uint32_t RESERVED11; + __IOM uint32_t DCDCEN0; /*!< (@ 0x00000580) Enable DC/DC converter for REG0 stage */ + __IM uint32_t RESERVED12[47]; + __IM uint32_t MAINREGSTATUS; /*!< (@ 0x00000640) Main supply status */ + __IM uint32_t RESERVED13[175]; + __IOM POWER_RAM_Type RAM[9]; /*!< (@ 0x00000900) Unspecified */ +} NRF_POWER_Type; /*!< Size = 2448 (0x990) */ + + + +/* =========================================================================================================================== */ +/* ================ P0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPIO Port 1 (P0) + */ + +typedef struct { /*!< (@ 0x50000000) P0 Structure */ + __IM uint32_t RESERVED[321]; + __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ + __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ + __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ + __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ + __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ + __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ + __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ + __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that + have met the criteria set in the PIN_CNF[n].SENSE + registers */ + __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behavior + and LDETECT mode */ + __IM uint32_t RESERVED1[118]; + __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO + pins */ +} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ + + + +/* =========================================================================================================================== */ +/* ================ RADIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 2.4 GHz radio (RADIO) + */ + +typedef struct { /*!< (@ 0x40001000) RADIO Structure */ + __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ + __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ + __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ + __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of + the receive signal strength */ + __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ + __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ + __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ + __OM uint32_t TASKS_EDSTART; /*!< (@ 0x00000024) Start the energy detect measurement used in IEEE + 802.15.4 mode */ + __OM uint32_t TASKS_EDSTOP; /*!< (@ 0x00000028) Stop the energy detect measurement */ + __OM uint32_t TASKS_CCASTART; /*!< (@ 0x0000002C) Start the clear channel assessment used in IEEE + 802.15.4 mode */ + __OM uint32_t TASKS_CCASTOP; /*!< (@ 0x00000030) Stop the clear channel assessment */ + __IM uint32_t RESERVED[51]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ + __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ + __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ + __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ + __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received + packet */ + __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last + received packet */ + __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value */ + __IM uint32_t RESERVED2; + __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ + __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ + __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000138) IEEE 802.15.4 length field received */ + __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000013C) Sampling of energy detection complete. A new + ED sample is ready for readout from the + RADIO.EDSAMPLE register. */ + __IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000140) The sampling of energy detection has stopped */ + __IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000144) Wireless medium in idle - clear to send */ + __IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000148) Wireless medium busy - do not send */ + __IOM uint32_t EVENTS_CCASTOPPED; /*!< (@ 0x0000014C) The CCA has stopped */ + __IOM uint32_t EVENTS_RATEBOOST; /*!< (@ 0x00000150) Ble_LR CI field received, receive mode is changed + from Ble_LR125Kbit to Ble_LR500Kbit. */ + __IOM uint32_t EVENTS_TXREADY; /*!< (@ 0x00000154) RADIO has ramped up and is ready to be started + TX path */ + __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started + RX path */ + __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_SYNC; /*!< (@ 0x00000168) Preamble indicator. */ + __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated in Ble_LR125Kbit, Ble_LR500Kbit and + Ieee802154_250Kbit modes when last bit is + sent on air. */ + __IM uint32_t RESERVED4[36]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED5[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED6[61]; + __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ + __IM uint32_t RESERVED7; + __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ + __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ + __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ + __IM uint32_t PDUSTAT; /*!< (@ 0x00000414) Payload status */ + __IM uint32_t RESERVED8[59]; + __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ + __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ + __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ + __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ + __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ + __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ + __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ + __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ + __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ + __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ + __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ + __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ + __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ + __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ + __IM uint32_t RESERVED9; + __IOM uint32_t TIFS; /*!< (@ 0x00000544) Interframe spacing in us */ + __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ + __IM uint32_t RESERVED10; + __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ + __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ + __IM uint32_t RESERVED11[2]; + __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ + __IM uint32_t RESERVED12[39]; + __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment + n */ + __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix + n */ + __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ + __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000644) Search pattern configuration */ + __IOM uint32_t MHRMATCHMAS; /*!< (@ 0x00000648) Pattern mask */ + __IM uint32_t RESERVED13; + __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ + __IM uint32_t RESERVED14[3]; + __IOM uint32_t SFD; /*!< (@ 0x00000660) IEEE 802.15.4 start of frame delimiter */ + __IOM uint32_t EDCNT; /*!< (@ 0x00000664) IEEE 802.15.4 energy detect loop count */ + __IOM uint32_t EDSAMPLE; /*!< (@ 0x00000668) IEEE 802.15.4 energy detect level */ + __IOM uint32_t CCACTRL; /*!< (@ 0x0000066C) IEEE 802.15.4 clear channel assessment control */ + __IM uint32_t RESERVED15[611]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ +} NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal Asynchronous Receiver/Transmitter (UART0) + */ + +typedef struct { /*!< (@ 0x40002000) UART0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ + __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ + __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ + __IM uint32_t RESERVED[3]; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ + __IM uint32_t RESERVED1[56]; + __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ + __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ + __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ + __IM uint32_t RESERVED2[4]; + __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ + __IM uint32_t RESERVED3; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ + __IM uint32_t RESERVED5[46]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED6[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED7[93]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ + __IM uint32_t RESERVED8[31]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ + __IM uint32_t RESERVED9; + __IOM UART_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED10; + __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source + selected. */ + __IM uint32_t RESERVED11[17]; + __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ +} NRF_UART_Type; /*!< Size = 1392 (0x570) */ + + + +/* =========================================================================================================================== */ +/* ================ UARTE0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART with EasyDMA 0 (UARTE0) + */ + +typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ + __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ + __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ + __IM uint32_t RESERVED[7]; + __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ + __IM uint32_t RESERVED1[52]; + __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ + __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ + __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet + transferred to Data RAM) */ + __IM uint32_t RESERVED2; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ + __IM uint32_t RESERVED6; + __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ + __IM uint32_t RESERVED7[41]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[93]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source This register is read/write one + to clear. */ + __IM uint32_t RESERVED10[31]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ + __IM uint32_t RESERVED11; + __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[3]; + __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source + selected. */ + __IM uint32_t RESERVED13[3]; + __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IM uint32_t RESERVED14; + __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED15[7]; + __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ +} NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial Peripheral Interface 0 (SPI0) + */ + +typedef struct { /*!< (@ 0x40003000) SPI0 Structure */ + __IM uint32_t RESERVED[66]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */ + __IM uint32_t RESERVED1[126]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ + __IM uint32_t RESERVED3; + __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED4; + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED5; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED6[11]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ +} NRF_SPI_Type; /*!< Size = 1368 (0x558) */ + + + +/* =========================================================================================================================== */ +/* ================ SPIM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0) + */ + +typedef struct { /*!< (@ 0x40003000) SPIM0 Structure */ + __IM uint32_t RESERVED[4]; + __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ + __IM uint32_t RESERVED2[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ + __IM uint32_t RESERVED4; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ + __IM uint32_t RESERVED6[10]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ + __IM uint32_t RESERVED7[44]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED8[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[61]; + __IOM uint32_t STALLSTAT; /*!< (@ 0x00000400) Stall status for EasyDMA RAM accesses. The fields + in this register are set to STALL by hardware + whenever a stall occurs and can be cleared + (set to NOSTALL) by the CPU. */ + __IM uint32_t RESERVED10[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ + __IM uint32_t RESERVED11; + __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[3]; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED13[3]; + __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ + __IM uint32_t RESERVED14[2]; + __IOM SPIM_IFTIMING_Type IFTIMING; /*!< (@ 0x00000560) Unspecified */ + __IOM uint32_t CSNPOL; /*!< (@ 0x00000568) Polarity of CSN output */ + __IOM uint32_t PSELDCX; /*!< (@ 0x0000056C) Pin select for DCX signal */ + __IOM uint32_t DCXCNT; /*!< (@ 0x00000570) DCX configuration */ + __IM uint32_t RESERVED15[19]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Byte transmitted after TXD.MAXCNT bytes have + been transmitted in the case when RXD.MAXCNT + is greater than TXD.MAXCNT */ +} NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ SPIS0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI Slave 0 (SPIS0) + */ + +typedef struct { /*!< (@ 0x40003000) SPIS0 Structure */ + __IM uint32_t RESERVED[9]; + __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ + __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave + to acquire it */ + __IM uint32_t RESERVED1[54]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ + __IM uint32_t RESERVED4[53]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED5[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED6[61]; + __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ + __IM uint32_t RESERVED7[15]; + __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ + __IM uint32_t RESERVED8[47]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ + __IM uint32_t RESERVED9; + __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED10[7]; + __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ + __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ + __IM uint32_t RESERVED11; + __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case + of an ignored transaction. */ + __IM uint32_t RESERVED12[24]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ +} NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ TWI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Interface 0 (TWI0) + */ + +typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ + __IM uint32_t RESERVED1[2]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ + __IM uint32_t RESERVED2; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED3[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */ + __IM uint32_t RESERVED4[4]; + __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED6[4]; + __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte + that is sent or received */ + __IM uint32_t RESERVED7[3]; + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ + __IM uint32_t RESERVED8[45]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED9[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED10[110]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ + __IM uint32_t RESERVED11[14]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */ + __IM uint32_t RESERVED12; + __IOM TWI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED13[2]; + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED14; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED15[24]; + __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ +} NRF_TWI_Type; /*!< Size = 1420 (0x58c) */ + + + +/* =========================================================================================================================== */ +/* ================ TWIM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0) + */ + +typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ + __IM uint32_t RESERVED1[2]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the + TWI master is not suspended. */ + __IM uint32_t RESERVED2; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED3[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED5[8]; + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is + now suspended. */ + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ + __IM uint32_t RESERVED6[2]; + __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ + __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last + byte */ + __IM uint32_t RESERVED7[39]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[110]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ + __IM uint32_t RESERVED10[14]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ + __IM uint32_t RESERVED11; + __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[5]; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED13[3]; + __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED14[13]; + __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ +} NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ + + + +/* =========================================================================================================================== */ +/* ================ TWIS0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0) + */ + +typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ + __IM uint32_t RESERVED[5]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED2[3]; + __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ + __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ + __IM uint32_t RESERVED3[51]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED5[9]; + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ + __IM uint32_t RESERVED6[4]; + __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ + __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ + __IM uint32_t RESERVED7[37]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[113]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ + __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had + a match */ + __IM uint32_t RESERVED10[10]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ + __IM uint32_t RESERVED11; + __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[9]; + __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED13[13]; + __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ + __IM uint32_t RESERVED14; + __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match + mechanism */ + __IM uint32_t RESERVED15[10]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case + of an over-read of the transmit buffer. */ +} NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ NFCT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief NFC-A compatible radio (NFCT) + */ + +typedef struct { /*!< (@ 0x40005000) NFCT Structure */ + __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate NFCT peripheral for incoming and outgoing + frames, change state to activated */ + __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000004) Disable NFCT peripheral */ + __OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, change state to + sense mode */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x0000000C) Start transmission of an outgoing frame, change + state to transmit */ + __IM uint32_t RESERVED[3]; + __OM uint32_t TASKS_ENABLERXDATA; /*!< (@ 0x0000001C) Initializes the EasyDMA for receive. */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_GOIDLE; /*!< (@ 0x00000024) Force state machine to IDLE state */ + __OM uint32_t TASKS_GOSLEEP; /*!< (@ 0x00000028) Force state machine to SLEEP_A state */ + __IM uint32_t RESERVED2[53]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) The NFCT peripheral is ready to receive and send + frames */ + __IOM uint32_t EVENTS_FIELDDETECTED; /*!< (@ 0x00000104) Remote NFC field detected */ + __IOM uint32_t EVENTS_FIELDLOST; /*!< (@ 0x00000108) Remote NFC field lost */ + __IOM uint32_t EVENTS_TXFRAMESTART; /*!< (@ 0x0000010C) Marks the start of the first symbol of a transmitted + frame */ + __IOM uint32_t EVENTS_TXFRAMEEND; /*!< (@ 0x00000110) Marks the end of the last transmitted on-air + symbol of a frame */ + __IOM uint32_t EVENTS_RXFRAMESTART; /*!< (@ 0x00000114) Marks the end of the first symbol of a received + frame */ + __IOM uint32_t EVENTS_RXFRAMEEND; /*!< (@ 0x00000118) Received data has been checked (CRC, parity) + and transferred to RAM, and EasyDMA has + ended accessing the RX buffer */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x0000011C) NFC error reported. The ERRORSTATUS register + contains details on the source of the error. */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_RXERROR; /*!< (@ 0x00000128) NFC RX frame error reported. The FRAMESTATUS.RX + register contains details on the source + of the error. */ + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x0000012C) RX buffer (as defined by PACKETPTR and MAXLEN) + in Data RAM full. */ + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000130) Transmission of data in RAM has ended, and EasyDMA + has ended accessing the TX buffer */ + __IM uint32_t RESERVED4; + __IOM uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< (@ 0x00000138) Auto collision resolution process has started */ + __IM uint32_t RESERVED5[3]; + __IOM uint32_t EVENTS_COLLISION; /*!< (@ 0x00000148) NFC auto collision resolution error reported. */ + __IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC auto collision resolution successfully completed */ + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */ + __IM uint32_t RESERVED6[43]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED7[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED8[62]; + __IOM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) NFC Error Status register */ + __IM uint32_t RESERVED9; + __IOM NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< (@ 0x0000040C) Unspecified */ + __IM uint32_t NFCTAGSTATE; /*!< (@ 0x00000410) NfcTag state register */ + __IM uint32_t RESERVED10[3]; + __IM uint32_t SLEEPSTATE; /*!< (@ 0x00000420) Sleep state during automatic collision resolution */ + __IM uint32_t RESERVED11[6]; + __IM uint32_t FIELDPRESENT; /*!< (@ 0x0000043C) Indicates the presence or not of a valid field */ + __IM uint32_t RESERVED12[49]; + __IOM uint32_t FRAMEDELAYMIN; /*!< (@ 0x00000504) Minimum frame delay */ + __IOM uint32_t FRAMEDELAYMAX; /*!< (@ 0x00000508) Maximum frame delay */ + __IOM uint32_t FRAMEDELAYMODE; /*!< (@ 0x0000050C) Configuration register for the Frame Delay Timer */ + __IOM uint32_t PACKETPTR; /*!< (@ 0x00000510) Packet pointer for TXD and RXD data storage in + Data RAM */ + __IOM uint32_t MAXLEN; /*!< (@ 0x00000514) Size of the RAM buffer allocated to TXD and RXD + data storage each */ + __IOM NFCT_TXD_Type TXD; /*!< (@ 0x00000518) Unspecified */ + __IOM NFCT_RXD_Type RXD; /*!< (@ 0x00000520) Unspecified */ + __IM uint32_t RESERVED13[26]; + __IOM uint32_t NFCID1_LAST; /*!< (@ 0x00000590) Last NFCID1 part (4, 7 or 10 bytes ID) */ + __IOM uint32_t NFCID1_2ND_LAST; /*!< (@ 0x00000594) Second last NFCID1 part (7 or 10 bytes ID) */ + __IOM uint32_t NFCID1_3RD_LAST; /*!< (@ 0x00000598) Third last NFCID1 part (10 bytes ID) */ + __IOM uint32_t AUTOCOLRESCONFIG; /*!< (@ 0x0000059C) Controls the auto collision resolution function. + This setting must be done before the NFCT + peripheral is activated. */ + __IOM uint32_t SENSRES; /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings */ + __IOM uint32_t SELRES; /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings */ +} NRF_NFCT_Type; /*!< Size = 1448 (0x5a8) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIOTE ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPIO Tasks and Events (GPIOTE) + */ + +typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ + __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin + specified in CONFIG[n].PSEL. Action on pin + is configured in CONFIG[n].POLARITY. */ + __IM uint32_t RESERVED[4]; + __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin + specified in CONFIG[n].PSEL. Action on pin + is to set it high. */ + __IM uint32_t RESERVED1[4]; + __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin + specified in CONFIG[n].PSEL. Action on pin + is to set it low. */ + __IM uint32_t RESERVED2[32]; + __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from + pin specified in CONFIG[n].PSEL */ + __IM uint32_t RESERVED3[23]; + __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins + with SENSE mechanism enabled */ + __IM uint32_t RESERVED4[97]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED5[129]; + __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], + SET[n], and CLR[n] tasks and IN[n] event */ +} NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ + + + +/* =========================================================================================================================== */ +/* ================ SAADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Successive approximation register (SAR) analog-to-digital converter (SAADC) + */ + +typedef struct { /*!< (@ 0x40007000) SAADC Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts the SAADC and prepares the result buffer + in RAM */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Takes one SAADC sample */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stops the SAADC and terminates all on-going conversions */ + __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The SAADC has started */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The SAADC has filled up the result buffer */ + __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending + on the configuration, multiple conversions + might be needed for a result to be transferred + to RAM. */ + __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) Result ready for transfer to RAM */ + __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The SAADC has stopped */ + __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ + __IM uint32_t RESERVED1[106]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[61]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable SAADC */ + __IM uint32_t RESERVED4[3]; + __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ + __IM uint32_t RESERVED5[24]; + __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ + __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. The RESOLUTION is + applied before averaging, thus for high + OVERSAMPLE a higher RESOLUTION should be + used. */ + __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ + __IM uint32_t RESERVED6[12]; + __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ +} NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ + + + +/* =========================================================================================================================== */ +/* ================ TIMER0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Timer/Counter 0 (TIMER0) + */ + +typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ + __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ + __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ + __IM uint32_t RESERVED[11]; + __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to + CC[n] register */ + __IM uint32_t RESERVED1[58]; + __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] + match */ + __IM uint32_t RESERVED2[42]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED3[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[126]; + __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ + __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ + __IM uint32_t RESERVED5; + __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ + __IM uint32_t RESERVED6[11]; + __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register + n */ +} NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ + + + +/* =========================================================================================================================== */ +/* ================ RTC0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Real time counter 0 (RTC0) + */ + +typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ + __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ + __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ + __IM uint32_t RESERVED1[14]; + __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] + match */ + __IM uint32_t RESERVED2[109]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[13]; + __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ + __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ + __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ + __IM uint32_t RESERVED4[110]; + __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ + __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). + Must be written when RTC is stopped. */ + __IM uint32_t RESERVED5[13]; + __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ +} NRF_RTC_Type; /*!< Size = 1360 (0x550) */ + + + +/* =========================================================================================================================== */ +/* ================ TEMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Temperature Sensor (TEMP) + */ + +typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ + __IM uint32_t RESERVED1[128]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[127]; + __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of first piecewise linear function */ + __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of second piecewise linear function */ + __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of third piecewise linear function */ + __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of fourth piecewise linear function */ + __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of fifth piecewise linear function */ + __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of sixth piecewise linear function */ + __IM uint32_t RESERVED4[2]; + __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of first piecewise linear function */ + __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of second piecewise linear function */ + __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of third piecewise linear function */ + __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of fourth piecewise linear function */ + __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of fifth piecewise linear function */ + __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of sixth piecewise linear function */ + __IM uint32_t RESERVED5[2]; + __IOM uint32_t T0; /*!< (@ 0x00000560) End point of first piecewise linear function */ + __IOM uint32_t T1; /*!< (@ 0x00000564) End point of second piecewise linear function */ + __IOM uint32_t T2; /*!< (@ 0x00000568) End point of third piecewise linear function */ + __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of fourth piecewise linear function */ + __IOM uint32_t T4; /*!< (@ 0x00000570) End point of fifth piecewise linear function */ +} NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ + + + +/* =========================================================================================================================== */ +/* ================ RNG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Random Number Generator (RNG) + */ + +typedef struct { /*!< (@ 0x4000D000) RNG Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number + written to the VALUE register */ + __IM uint32_t RESERVED1[63]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[126]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ + __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ +} NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ + + + +/* =========================================================================================================================== */ +/* ================ ECB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief AES ECB Mode Encryption (ECB) + */ + +typedef struct { /*!< (@ 0x4000E000) ECB Structure */ + __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ + __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ + __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB + task or due to an error */ + __IM uint32_t RESERVED1[127]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[126]; + __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ +} NRF_ECB_Type; /*!< Size = 1288 (0x508) */ + + + +/* =========================================================================================================================== */ +/* ================ AAR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Accelerated Address Resolver (AAR) + */ + +typedef struct { /*!< (@ 0x4000F000) AAR Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified + in the IRK data structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ + __IM uint32_t RESERVED1[61]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ + __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ + __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ + __IM uint32_t RESERVED2[126]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ + __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ + __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ + __IM uint32_t RESERVED5; + __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ + __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ +} NRF_AAR_Type; /*!< Size = 1304 (0x518) */ + + + +/* =========================================================================================================================== */ +/* ================ CCM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief AES CCM Mode Encryption (CCM) + */ + +typedef struct { /*!< (@ 0x4000F000) CCM Structure */ + __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of keystream. This operation + will stop by itself when completed. */ + __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will + stop by itself when completed. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ + __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with + the contents of the RATEOVERRIDE register + for any ongoing encryption/decryption */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Keystream generation complete */ + __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ + __IM uint32_t RESERVED1[61]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ + __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ + __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and + NONCE vector */ + __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ + __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ + __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ + __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of keystream generated when MODE.LENGTH + = Extended. */ + __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ +} NRF_CCM_Type; /*!< Size = 1312 (0x520) */ + + + +/* =========================================================================================================================== */ +/* ================ WDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Watchdog Timer (WDT) + */ + +typedef struct { /*!< (@ 0x40010000) WDT Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ + __IM uint32_t RESERVED[63]; + __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ + __IM uint32_t RESERVED1[128]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[61]; + __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ + __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ + __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ + __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ + __IM uint32_t RESERVED4[60]; + __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ +} NRF_WDT_Type; /*!< Size = 1568 (0x620) */ + + + +/* =========================================================================================================================== */ +/* ================ QDEC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Quadrature Decoder (QDEC) + */ + +typedef struct { /*!< (@ 0x40012000) QDEC Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ + __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ + __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ + __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ + __IM uint32_t RESERVED[59]; + __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value + written to the SAMPLE register */ + __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ + __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ + __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ + __IM uint32_t RESERVED1[59]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ + __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ + __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ + __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ + __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY + and DBLRDY events can be generated */ + __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ + __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the + READCLRACC or RDCLRACC task */ + __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ + __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ + __IM uint32_t RESERVED4[5]; + __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ + __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected + double transitions */ + __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC + or RDCLRDBL task */ +} NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ + + + +/* =========================================================================================================================== */ +/* ================ COMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Comparator (COMP) + */ + +typedef struct { /*!< (@ 0x40013000) COMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ + __IM uint32_t RESERVED[61]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ + __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ + __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ + __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED2[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ + __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ + __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ + __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ + __IM uint32_t RESERVED5[8]; + __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ + __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ + __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ +} NRF_COMP_Type; /*!< Size = 1340 (0x53c) */ + + + +/* =========================================================================================================================== */ +/* ================ LPCOMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Low-power comparator (LPCOMP) + */ + +typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ + __IM uint32_t RESERVED[61]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid */ + __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ + __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ + __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable LPCOMP */ + __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select */ + __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select */ + __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ + __IM uint32_t RESERVED5[4]; + __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration */ + __IM uint32_t RESERVED6[5]; + __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ +} NRF_LPCOMP_Type; /*!< Size = 1340 (0x53c) */ + + + +/* =========================================================================================================================== */ +/* ================ EGU0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Event generator unit 0 (EGU0) + */ + +typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ + __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering + the corresponding TRIGGERED[n] event */ + __IM uint32_t RESERVED[48]; + __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated + by triggering the corresponding TRIGGER[n] + task */ + __IM uint32_t RESERVED1[112]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ +} NRF_EGU_Type; /*!< Size = 780 (0x30c) */ + + + +/* =========================================================================================================================== */ +/* ================ SWI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Software interrupt 0 (SWI0) + */ + +typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ + __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ +} NRF_SWI_Type; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ PWM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Pulse width modulation unit 0 (PWM0) + */ + +typedef struct { /*!< (@ 0x4001C000) PWM0 Structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at + the end of current PWM period, and stops + sequence playback */ + __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value + on all enabled channels from sequence n, + and starts playing that sequence at the + rate defined in SEQ[n]REFRESH and/or DECODER.MODE. + Causes PWM generation to start if not running. */ + __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on + all enabled channels if DECODER.MODE=NextStep. + Does not cause PWM generation to start if + not running. */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses + are no longer generated */ + __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started + on sequence n */ + __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every + sequence n, when last value from RAM has + been applied to wave counter */ + __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ + __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount + of times defined in LOOP.CNT */ + __IM uint32_t RESERVED2[56]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ + __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ + __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter + counts */ + __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ + __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ + __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ + __IM uint32_t RESERVED5[2]; + __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ + __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ +} NRF_PWM_Type; /*!< Size = 1392 (0x570) */ + + + +/* =========================================================================================================================== */ +/* ================ PDM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) + */ + +typedef struct { /*!< (@ 0x4001D000) PDM Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified + by SAMPLE.MAXCNT (or the last sample after + a STOP task has been received) to Data RAM */ + __IM uint32_t RESERVED1[125]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ + __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ + __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' + signals */ + __IM uint32_t RESERVED3[3]; + __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ + __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ + __IOM uint32_t RATIO; /*!< (@ 0x00000520) Selects the ratio between PDM_CLK and output + sample rate. Change PDMCLKCTRL accordingly. */ + __IM uint32_t RESERVED4[7]; + __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ + __IM uint32_t RESERVED5[6]; + __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ +} NRF_PDM_Type; /*!< Size = 1384 (0x568) */ + + + +/* =========================================================================================================================== */ +/* ================ ACL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Access control lists (ACL) + */ + +typedef struct { /*!< (@ 0x4001E000) ACL Structure */ + __IM uint32_t RESERVED[512]; + __IOM ACL_ACL_Type ACL[8]; /*!< (@ 0x00000800) Unspecified */ +} NRF_ACL_Type; /*!< Size = 2176 (0x880) */ + + + +/* =========================================================================================================================== */ +/* ================ NVMC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Non Volatile Memory Controller (NVMC) + */ + +typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ + __IM uint32_t RESERVED[256]; + __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ + __IM uint32_t RESERVED1; + __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */ + __IM uint32_t RESERVED2[62]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ + + union { + __OM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */ + __OM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a + page in code area, equivalent to ERASEPAGE */ + }; + __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ + __OM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a + page in code area, equivalent to ERASEPAGE */ + __OM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration + registers */ + __OM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code + area */ + __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ + __IM uint32_t RESERVED3[8]; + __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-code cache configuration register */ + __IM uint32_t RESERVED4; + __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-code cache hit counter */ + __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter */ +} NRF_NVMC_Type; /*!< Size = 1360 (0x550) */ + + + +/* =========================================================================================================================== */ +/* ================ PPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Programmable Peripheral Interconnect (PPI) + */ + +typedef struct { /*!< (@ 0x4001F000) PPI Structure */ + __OM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ + __IM uint32_t RESERVED[308]; + __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ + __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ + __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ + __IM uint32_t RESERVED1; + __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ + __IM uint32_t RESERVED2[148]; + __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n */ + __IM uint32_t RESERVED3[62]; + __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ +} NRF_PPI_Type; /*!< Size = 2448 (0x990) */ + + + +/* =========================================================================================================================== */ +/* ================ MWU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Memory Watch Unit (MWU) + */ + +typedef struct { /*!< (@ 0x40020000) MWU Structure */ + __IM uint32_t RESERVED[64]; + __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Peripheral events. */ + __IM uint32_t RESERVED1[16]; + __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Peripheral events. */ + __IM uint32_t RESERVED2[100]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable interrupt */ + __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable interrupt */ + __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable interrupt */ + __IM uint32_t RESERVED4[53]; + __IOM MWU_PERREGION_Type PERREGION[2]; /*!< (@ 0x00000400) Unspecified */ + __IM uint32_t RESERVED5[64]; + __IOM uint32_t REGIONEN; /*!< (@ 0x00000510) Enable/disable regions watch */ + __IOM uint32_t REGIONENSET; /*!< (@ 0x00000514) Enable regions watch */ + __IOM uint32_t REGIONENCLR; /*!< (@ 0x00000518) Disable regions watch */ + __IM uint32_t RESERVED6[57]; + __IOM MWU_REGION_Type REGION[4]; /*!< (@ 0x00000600) Unspecified */ + __IM uint32_t RESERVED7[32]; + __IOM MWU_PREGION_Type PREGION[2]; /*!< (@ 0x000006C0) Unspecified */ +} NRF_MWU_Type; /*!< Size = 1760 (0x6e0) */ + + + +/* =========================================================================================================================== */ +/* ================ I2S ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Inter-IC Sound (I2S) + */ + +typedef struct { /*!< (@ 0x40025000) I2S Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK + generator when this is enabled. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. + Triggering this task will cause the STOPPED + event to be generated. */ + __IM uint32_t RESERVED[63]; + __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal + double-buffers. When the I2S module is started + and RX is enabled, this event will be generated + for every RXTXD.MAXCNT words that are received + on the SDIN pin. */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal + double-buffers. When the I2S module is started + and TX is enabled, this event will be generated + for every RXTXD.MAXCNT words that are sent + on the SDOUT pin. */ + __IM uint32_t RESERVED2[122]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */ + __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ + __IM uint32_t RESERVED4[3]; + __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ + __IM uint32_t RESERVED5; + __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ + __IM uint32_t RESERVED6[3]; + __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ + __IM uint32_t RESERVED7[3]; + __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ +} NRF_I2S_Type; /*!< Size = 1396 (0x574) */ + + + +/* =========================================================================================================================== */ +/* ================ FPU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief FPU (FPU) + */ + +typedef struct { /*!< (@ 0x40026000) FPU Structure */ + __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ +} NRF_FPU_Type; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ USBD ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal serial bus device (USBD) + */ + +typedef struct { /*!< (@ 0x40027000) USBD Structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STARTEPIN[8]; /*!< (@ 0x00000004) Description collection: Captures the EPIN[n].PTR + and EPIN[n].MAXCNT registers values, and + enables endpoint IN n to respond to traffic + from host */ + __OM uint32_t TASKS_STARTISOIN; /*!< (@ 0x00000024) Captures the ISOIN.PTR and ISOIN.MAXCNT registers + values, and enables sending data on ISO + endpoint */ + __OM uint32_t TASKS_STARTEPOUT[8]; /*!< (@ 0x00000028) Description collection: Captures the EPOUT[n].PTR + and EPOUT[n].MAXCNT registers values, and + enables endpoint n to respond to traffic + from host */ + __OM uint32_t TASKS_STARTISOOUT; /*!< (@ 0x00000048) Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers + values, and enables receiving of data on + ISO endpoint */ + __OM uint32_t TASKS_EP0RCVOUT; /*!< (@ 0x0000004C) Allows OUT data stage on control endpoint 0 */ + __OM uint32_t TASKS_EP0STATUS; /*!< (@ 0x00000050) Allows status stage on control endpoint 0 */ + __OM uint32_t TASKS_EP0STALL; /*!< (@ 0x00000054) Stalls data and status stage on control endpoint + 0 */ + __OM uint32_t TASKS_DPDMDRIVE; /*!< (@ 0x00000058) Forces D+ and D- lines into the state defined + in the DPDMVALUE register */ + __OM uint32_t TASKS_DPDMNODRIVE; /*!< (@ 0x0000005C) Stops forcing D+ and D- lines into any state + (USB engine takes control) */ + __IM uint32_t RESERVED1[40]; + __IOM uint32_t EVENTS_USBRESET; /*!< (@ 0x00000100) Signals that a USB reset condition has been detected + on USB lines */ + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000104) Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, + or EPOUT[n].PTR and EPOUT[n].MAXCNT registers + have been captured on all endpoints reported + in the EPSTATUS register */ + __IOM uint32_t EVENTS_ENDEPIN[8]; /*!< (@ 0x00000108) Description collection: The whole EPIN[n] buffer + has been consumed. The buffer can be accessed + safely by software. */ + __IOM uint32_t EVENTS_EP0DATADONE; /*!< (@ 0x00000128) An acknowledged data transfer has taken place + on the control endpoint */ + __IOM uint32_t EVENTS_ENDISOIN; /*!< (@ 0x0000012C) The whole ISOIN buffer has been consumed. The + buffer can be accessed safely by software. */ + __IOM uint32_t EVENTS_ENDEPOUT[8]; /*!< (@ 0x00000130) Description collection: The whole EPOUT[n] buffer + has been consumed. The buffer can be accessed + safely by software. */ + __IOM uint32_t EVENTS_ENDISOOUT; /*!< (@ 0x00000150) The whole ISOOUT buffer has been consumed. The + buffer can be accessed safely by software. */ + __IOM uint32_t EVENTS_SOF; /*!< (@ 0x00000154) Signals that a SOF (start of frame) condition + has been detected on USB lines */ + __IOM uint32_t EVENTS_USBEVENT; /*!< (@ 0x00000158) An event or an error not covered by specific + events has occurred. Check EVENTCAUSE register + to find the cause. */ + __IOM uint32_t EVENTS_EP0SETUP; /*!< (@ 0x0000015C) A valid SETUP token has been received (and acknowledged) + on the control endpoint */ + __IOM uint32_t EVENTS_EPDATA; /*!< (@ 0x00000160) A data transfer has occurred on a data endpoint, + indicated by the EPDATASTATUS register */ + __IM uint32_t RESERVED2[39]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[61]; + __IOM uint32_t EVENTCAUSE; /*!< (@ 0x00000400) Details on what caused the USBEVENT event */ + __IM uint32_t RESERVED5[7]; + __IOM USBD_HALTED_Type HALTED; /*!< (@ 0x00000420) Unspecified */ + __IM uint32_t RESERVED6; + __IOM uint32_t EPSTATUS; /*!< (@ 0x00000468) Provides information on which endpoint's EasyDMA + registers have been captured */ + __IOM uint32_t EPDATASTATUS; /*!< (@ 0x0000046C) Provides information on which endpoint(s) an + acknowledged data transfer has occurred + (EPDATA event) */ + __IM uint32_t USBADDR; /*!< (@ 0x00000470) Device USB address */ + __IM uint32_t RESERVED7[3]; + __IM uint32_t BMREQUESTTYPE; /*!< (@ 0x00000480) SETUP data, byte 0, bmRequestType */ + __IM uint32_t BREQUEST; /*!< (@ 0x00000484) SETUP data, byte 1, bRequest */ + __IM uint32_t WVALUEL; /*!< (@ 0x00000488) SETUP data, byte 2, LSB of wValue */ + __IM uint32_t WVALUEH; /*!< (@ 0x0000048C) SETUP data, byte 3, MSB of wValue */ + __IM uint32_t WINDEXL; /*!< (@ 0x00000490) SETUP data, byte 4, LSB of wIndex */ + __IM uint32_t WINDEXH; /*!< (@ 0x00000494) SETUP data, byte 5, MSB of wIndex */ + __IM uint32_t WLENGTHL; /*!< (@ 0x00000498) SETUP data, byte 6, LSB of wLength */ + __IM uint32_t WLENGTHH; /*!< (@ 0x0000049C) SETUP data, byte 7, MSB of wLength */ + __IOM USBD_SIZE_Type SIZE; /*!< (@ 0x000004A0) Unspecified */ + __IM uint32_t RESERVED8[15]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable USB */ + __IOM uint32_t USBPULLUP; /*!< (@ 0x00000504) Control of the USB pull-up */ + __IOM uint32_t DPDMVALUE; /*!< (@ 0x00000508) State D+ and D- lines will be forced into by + the DPDMDRIVE task. The DPDMNODRIVE task + reverts the control of the lines to MAC + IP (no forcing). */ + __IOM uint32_t DTOGGLE; /*!< (@ 0x0000050C) Data toggle control and status */ + __IOM uint32_t EPINEN; /*!< (@ 0x00000510) Endpoint IN enable */ + __IOM uint32_t EPOUTEN; /*!< (@ 0x00000514) Endpoint OUT enable */ + __OM uint32_t EPSTALL; /*!< (@ 0x00000518) STALL endpoints */ + __IOM uint32_t ISOSPLIT; /*!< (@ 0x0000051C) Controls the split of ISO buffers */ + __IM uint32_t FRAMECNTR; /*!< (@ 0x00000520) Returns the current value of the start of frame + counter */ + __IM uint32_t RESERVED9[2]; + __IOM uint32_t LOWPOWER; /*!< (@ 0x0000052C) Controls USBD peripheral low power mode during + USB suspend */ + __IOM uint32_t ISOINCONFIG; /*!< (@ 0x00000530) Controls the response of the ISO IN endpoint + to an IN token when no data is ready to + be sent */ + __IM uint32_t RESERVED10[51]; + __IOM USBD_EPIN_Type EPIN[8]; /*!< (@ 0x00000600) Unspecified */ + __IOM USBD_ISOIN_Type ISOIN; /*!< (@ 0x000006A0) Unspecified */ + __IM uint32_t RESERVED11[21]; + __IOM USBD_EPOUT_Type EPOUT[8]; /*!< (@ 0x00000700) Unspecified */ + __IOM USBD_ISOOUT_Type ISOOUT; /*!< (@ 0x000007A0) Unspecified */ +} NRF_USBD_Type; /*!< Size = 1964 (0x7ac) */ + + + +/* =========================================================================================================================== */ +/* ================ QSPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief External flash interface (QSPI) + */ + +typedef struct { /*!< (@ 0x40029000) QSPI Structure */ + __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate QSPI interface */ + __OM uint32_t TASKS_READSTART; /*!< (@ 0x00000004) Start transfer from external flash memory to + internal RAM */ + __OM uint32_t TASKS_WRITESTART; /*!< (@ 0x00000008) Start transfer from internal RAM to external + flash memory */ + __OM uint32_t TASKS_ERASESTART; /*!< (@ 0x0000000C) Start external flash memory erase operation */ + __OM uint32_t TASKS_DEACTIVATE; /*!< (@ 0x00000010) Deactivate QSPI interface */ + __IM uint32_t RESERVED[59]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) QSPI peripheral is ready. This event will be + generated as a response to any QSPI task. */ + __IM uint32_t RESERVED1[127]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable QSPI peripheral and acquire the pins selected + in PSELn registers */ + __IOM QSPI_READ_Type READ; /*!< (@ 0x00000504) Unspecified */ + __IOM QSPI_WRITE_Type WRITE; /*!< (@ 0x00000510) Unspecified */ + __IOM QSPI_ERASE_Type ERASE; /*!< (@ 0x0000051C) Unspecified */ + __IOM QSPI_PSEL_Type PSEL; /*!< (@ 0x00000524) Unspecified */ + __IOM uint32_t XIPOFFSET; /*!< (@ 0x00000540) Address offset into the external memory for Execute + in Place operation. */ + __IOM uint32_t IFCONFIG0; /*!< (@ 0x00000544) Interface configuration. */ + __IM uint32_t RESERVED3[46]; + __IOM uint32_t IFCONFIG1; /*!< (@ 0x00000600) Interface configuration. */ + __IM uint32_t STATUS; /*!< (@ 0x00000604) Status register. */ + __IM uint32_t RESERVED4[3]; + __IOM uint32_t DPMDUR; /*!< (@ 0x00000614) Set the duration required to enter/exit deep + power-down mode (DPM). */ + __IM uint32_t RESERVED5[3]; + __IOM uint32_t ADDRCONF; /*!< (@ 0x00000624) Extended address configuration. */ + __IM uint32_t RESERVED6[3]; + __IOM uint32_t CINSTRCONF; /*!< (@ 0x00000634) Custom instruction configuration register. */ + __IOM uint32_t CINSTRDAT0; /*!< (@ 0x00000638) Custom instruction data register 0. */ + __IOM uint32_t CINSTRDAT1; /*!< (@ 0x0000063C) Custom instruction data register 1. */ + __IOM uint32_t IFTIMING; /*!< (@ 0x00000640) SPI interface timing. */ +} NRF_QSPI_Type; /*!< Size = 1604 (0x644) */ + + + +/* =========================================================================================================================== */ +/* ================ CC_HOST_RGF ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief CRYPTOCELL HOST_RGF interface (CC_HOST_RGF) + */ + +typedef struct { /*!< (@ 0x5002A000) CC_HOST_RGF Structure */ + __IM uint32_t RESERVED[1678]; + __IOM uint32_t HOST_CRYPTOKEY_SEL; /*!< (@ 0x00001A38) AES hardware key select */ + __IM uint32_t RESERVED1[4]; + __IOM uint32_t HOST_IOT_KPRTL_LOCK; /*!< (@ 0x00001A4C) This write-once register is the K_PRTL lock register. + When this register is set, K_PRTL cannot + be used and a zeroed key will be used instead. + The value of this register is saved in the + CRYPTOCELL AO power domain. */ + __IOM uint32_t HOST_IOT_KDR0; /*!< (@ 0x00001A50) This register holds bits 31:0 of K_DR. The value + of this register is saved in the CRYPTOCELL + AO power domain. Reading from this address + returns the K_DR valid status indicating + if K_DR is successfully retained. */ + __OM uint32_t HOST_IOT_KDR1; /*!< (@ 0x00001A54) This register holds bits 63:32 of K_DR. The value + of this register is saved in the CRYPTOCELL + AO power domain. */ + __OM uint32_t HOST_IOT_KDR2; /*!< (@ 0x00001A58) This register holds bits 95:64 of K_DR. The value + of this register is saved in the CRYPTOCELL + AO power domain. */ + __OM uint32_t HOST_IOT_KDR3; /*!< (@ 0x00001A5C) This register holds bits 127:96 of K_DR. The + value of this register is saved in the CRYPTOCELL + AO power domain. */ + __IOM uint32_t HOST_IOT_LCS; /*!< (@ 0x00001A60) Controls lifecycle state (LCS) for CRYPTOCELL + subsystem */ +} NRF_CC_HOST_RGF_Type; /*!< Size = 6756 (0x1a64) */ + + + +/* =========================================================================================================================== */ +/* ================ CRYPTOCELL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief ARM TrustZone CryptoCell register interface (CRYPTOCELL) + */ + +typedef struct { /*!< (@ 0x5002A000) CRYPTOCELL Structure */ + __IM uint32_t RESERVED[320]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable CRYPTOCELL subsystem */ +} NRF_CRYPTOCELL_Type; /*!< Size = 1284 (0x504) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define NRF_FICR_BASE 0x10000000UL +#define NRF_UICR_BASE 0x10001000UL +#define NRF_APPROTECT_BASE 0x40000000UL +#define NRF_CLOCK_BASE 0x40000000UL +#define NRF_POWER_BASE 0x40000000UL +#define NRF_P0_BASE 0x50000000UL +#define NRF_P1_BASE 0x50000300UL +#define NRF_RADIO_BASE 0x40001000UL +#define NRF_UART0_BASE 0x40002000UL +#define NRF_UARTE0_BASE 0x40002000UL +#define NRF_SPI0_BASE 0x40003000UL +#define NRF_SPIM0_BASE 0x40003000UL +#define NRF_SPIS0_BASE 0x40003000UL +#define NRF_TWI0_BASE 0x40003000UL +#define NRF_TWIM0_BASE 0x40003000UL +#define NRF_TWIS0_BASE 0x40003000UL +#define NRF_SPI1_BASE 0x40004000UL +#define NRF_SPIM1_BASE 0x40004000UL +#define NRF_SPIS1_BASE 0x40004000UL +#define NRF_TWI1_BASE 0x40004000UL +#define NRF_TWIM1_BASE 0x40004000UL +#define NRF_TWIS1_BASE 0x40004000UL +#define NRF_NFCT_BASE 0x40005000UL +#define NRF_GPIOTE_BASE 0x40006000UL +#define NRF_SAADC_BASE 0x40007000UL +#define NRF_TIMER0_BASE 0x40008000UL +#define NRF_TIMER1_BASE 0x40009000UL +#define NRF_TIMER2_BASE 0x4000A000UL +#define NRF_RTC0_BASE 0x4000B000UL +#define NRF_TEMP_BASE 0x4000C000UL +#define NRF_RNG_BASE 0x4000D000UL +#define NRF_ECB_BASE 0x4000E000UL +#define NRF_AAR_BASE 0x4000F000UL +#define NRF_CCM_BASE 0x4000F000UL +#define NRF_WDT_BASE 0x40010000UL +#define NRF_RTC1_BASE 0x40011000UL +#define NRF_QDEC_BASE 0x40012000UL +#define NRF_COMP_BASE 0x40013000UL +#define NRF_LPCOMP_BASE 0x40013000UL +#define NRF_EGU0_BASE 0x40014000UL +#define NRF_SWI0_BASE 0x40014000UL +#define NRF_EGU1_BASE 0x40015000UL +#define NRF_SWI1_BASE 0x40015000UL +#define NRF_EGU2_BASE 0x40016000UL +#define NRF_SWI2_BASE 0x40016000UL +#define NRF_EGU3_BASE 0x40017000UL +#define NRF_SWI3_BASE 0x40017000UL +#define NRF_EGU4_BASE 0x40018000UL +#define NRF_SWI4_BASE 0x40018000UL +#define NRF_EGU5_BASE 0x40019000UL +#define NRF_SWI5_BASE 0x40019000UL +#define NRF_TIMER3_BASE 0x4001A000UL +#define NRF_TIMER4_BASE 0x4001B000UL +#define NRF_PWM0_BASE 0x4001C000UL +#define NRF_PDM_BASE 0x4001D000UL +#define NRF_ACL_BASE 0x4001E000UL +#define NRF_NVMC_BASE 0x4001E000UL +#define NRF_PPI_BASE 0x4001F000UL +#define NRF_MWU_BASE 0x40020000UL +#define NRF_PWM1_BASE 0x40021000UL +#define NRF_PWM2_BASE 0x40022000UL +#define NRF_SPI2_BASE 0x40023000UL +#define NRF_SPIM2_BASE 0x40023000UL +#define NRF_SPIS2_BASE 0x40023000UL +#define NRF_RTC2_BASE 0x40024000UL +#define NRF_I2S_BASE 0x40025000UL +#define NRF_FPU_BASE 0x40026000UL +#define NRF_USBD_BASE 0x40027000UL +#define NRF_UARTE1_BASE 0x40028000UL +#define NRF_QSPI_BASE 0x40029000UL +#define NRF_CC_HOST_RGF_BASE 0x5002A000UL +#define NRF_CRYPTOCELL_BASE 0x5002A000UL +#define NRF_PWM3_BASE 0x4002D000UL +#define NRF_SPIM3_BASE 0x4002F000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) +#define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) +#define NRF_APPROTECT ((NRF_APPROTECT_Type*) NRF_APPROTECT_BASE) +#define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) +#define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) +#define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) +#define NRF_P1 ((NRF_GPIO_Type*) NRF_P1_BASE) +#define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) +#define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) +#define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) +#define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) +#define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) +#define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) +#define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) +#define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) +#define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) +#define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) +#define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE) +#define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) +#define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE) +#define NRF_TWIM1 ((NRF_TWIM_Type*) NRF_TWIM1_BASE) +#define NRF_TWIS1 ((NRF_TWIS_Type*) NRF_TWIS1_BASE) +#define NRF_NFCT ((NRF_NFCT_Type*) NRF_NFCT_BASE) +#define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) +#define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) +#define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) +#define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) +#define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) +#define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) +#define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) +#define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) +#define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) +#define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) +#define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) +#define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) +#define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) +#define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) +#define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) +#define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE) +#define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) +#define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) +#define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) +#define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) +#define NRF_EGU2 ((NRF_EGU_Type*) NRF_EGU2_BASE) +#define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) +#define NRF_EGU3 ((NRF_EGU_Type*) NRF_EGU3_BASE) +#define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) +#define NRF_EGU4 ((NRF_EGU_Type*) NRF_EGU4_BASE) +#define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) +#define NRF_EGU5 ((NRF_EGU_Type*) NRF_EGU5_BASE) +#define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) +#define NRF_TIMER3 ((NRF_TIMER_Type*) NRF_TIMER3_BASE) +#define NRF_TIMER4 ((NRF_TIMER_Type*) NRF_TIMER4_BASE) +#define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE) +#define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE) +#define NRF_ACL ((NRF_ACL_Type*) NRF_ACL_BASE) +#define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) +#define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) +#define NRF_MWU ((NRF_MWU_Type*) NRF_MWU_BASE) +#define NRF_PWM1 ((NRF_PWM_Type*) NRF_PWM1_BASE) +#define NRF_PWM2 ((NRF_PWM_Type*) NRF_PWM2_BASE) +#define NRF_SPI2 ((NRF_SPI_Type*) NRF_SPI2_BASE) +#define NRF_SPIM2 ((NRF_SPIM_Type*) NRF_SPIM2_BASE) +#define NRF_SPIS2 ((NRF_SPIS_Type*) NRF_SPIS2_BASE) +#define NRF_RTC2 ((NRF_RTC_Type*) NRF_RTC2_BASE) +#define NRF_I2S ((NRF_I2S_Type*) NRF_I2S_BASE) +#define NRF_FPU ((NRF_FPU_Type*) NRF_FPU_BASE) +#define NRF_USBD ((NRF_USBD_Type*) NRF_USBD_BASE) +#define NRF_UARTE1 ((NRF_UARTE_Type*) NRF_UARTE1_BASE) +#define NRF_QSPI ((NRF_QSPI_Type*) NRF_QSPI_BASE) +#define NRF_CC_HOST_RGF ((NRF_CC_HOST_RGF_Type*) NRF_CC_HOST_RGF_BASE) +#define NRF_CRYPTOCELL ((NRF_CRYPTOCELL_Type*) NRF_CRYPTOCELL_BASE) +#define NRF_PWM3 ((NRF_PWM_Type*) NRF_PWM3_BASE) +#define NRF_SPIM3 ((NRF_SPIM_Type*) NRF_SPIM3_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* NRF52840_H */ + + +/** @} */ /* End of group nrf52840 */ + +/** @} */ /* End of group Nordic Semiconductor */ diff --git a/bsp/boards/nrf52840_dk/sdk/nrf52840.svd b/bsp/boards/nrf52840_dk/sdk/nrf52840.svd new file mode 100644 index 0000000000..a1e623408d --- /dev/null +++ b/bsp/boards/nrf52840_dk/sdk/nrf52840.svd @@ -0,0 +1,54973 @@ + + + + Nordic Semiconductor + Nordic + nrf52840 + nrf52 + 1 + nRF52840 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller + +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA\n +\n +All rights reserved.\n +\n +Redistribution and use in source and binary forms, with or without modification,\n +are permitted provided that the following conditions are met:\n +\n +1. Redistributions of source code must retain the above copyright notice, this\n + list of conditions and the following disclaimer.\n +\n +2. Redistributions in binary form, except as embedded into a Nordic\n + Semiconductor ASA integrated circuit in a product or a software update for\n + such product, must reproduce the above copyright notice, this list of\n + conditions and the following disclaimer in the documentation and/or other\n + materials provided with the distribution.\n +\n +3. Neither the name of Nordic Semiconductor ASA nor the names of its\n + contributors may be used to endorse or promote products derived from this\n + software without specific prior written permission.\n +\n +4. This software, with or without modification, must only be used with a\n + Nordic Semiconductor ASA integrated circuit.\n +\n +5. Any software provided in binary form under this license must not be reverse\n + engineered, decompiled, modified and/or disassembled.\n +\n +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS\n +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\n +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE\n +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\n +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\n +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n + + 8 + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + CM4 + r0p1 + little + 1 + 1 + 3 + 0 + + system_nrf52840 + NRF_ + + 2048 + 2048 + 112 + + + + FICR + Factory information configuration registers + 0x10000000 + + 0 + 0x1000 + registers + + FICR + 0x20 + + + CODEPAGESIZE + Code memory page size + 0x010 + read-only + 0xFFFFFFFF + + + CODEPAGESIZE + Code memory page size + 0 + 31 + + + + + CODESIZE + Code memory size + 0x014 + read-only + 0xFFFFFFFF + + + CODESIZE + Code memory size in number of pages + 0 + 31 + + + + + 0x2 + 0x4 + DEVICEID[%s] + Description collection: Device identifier + 0x060 + read-only + 0xFFFFFFFF + + + DEVICEID + 64 bit unique device identifier + 0 + 31 + + + + + 0x4 + 0x4 + ER[%s] + Description collection: Encryption root, word n + 0x080 + read-only + 0xFFFFFFFF + + + ER + Encryption root, word n + 0 + 31 + + + + + 0x4 + 0x4 + IR[%s] + Description collection: Identity Root, word n + 0x090 + read-only + 0xFFFFFFFF + + + IR + Identity Root, word n + 0 + 31 + + + + + DEVICEADDRTYPE + Device address type + 0x0A0 + read-only + 0xFFFFFFFF + + + DEVICEADDRTYPE + Device address type + 0 + 0 + + + Public + Public address + 0 + + + Random + Random address + 1 + + + + + + + 0x2 + 0x4 + DEVICEADDR[%s] + Description collection: Device address n + 0x0A4 + read-only + 0xFFFFFFFF + + + DEVICEADDR + 48 bit device address + 0 + 31 + + + + + INFO + Device info + FICR_INFO + read-only + 0x100 + + PART + Part code + 0x000 + read-only + 0x00052840 + + + PART + Part code + 0 + 31 + + + N52820 + nRF52820 + 0x52820 + + + N52833 + nRF52833 + 0x52833 + + + N52840 + nRF52840 + 0x52840 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + VARIANT + Build code (hardware version and production configuration) + 0x004 + read-only + 0xFFFFFFFF + + + VARIANT + Build code (hardware version and production configuration). Encoded as ASCII. + 0 + 31 + + + AAAA + AAAA + 0x41414141 + + + BAAA + BAAA + 0x42414141 + + + CAAA + CAAA + 0x43414141 + + + AABA + AABA + 0x41414241 + + + AABB + AABB + 0x41414242 + + + AACA + AACA + 0x41414341 + + + AAAB + AAAB + 0x41414142 + + + AAC0 + AAC0 + 0x41414330 + + + AADA + AADA + 0x41414441 + + + AAD0 + AAD0 + 0x41414430 + + + AAD1 + AAD1 + 0x41414431 + + + AAEA + AAEA + 0x41414541 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + PACKAGE + Package option + 0x008 + read-only + 0xFFFFFFFF + + + PACKAGE + Package option + 0 + 31 + + + QI + QIxx - 7x7 73-pin aQFN + 0x2004 + + + CK + CKxx - 3.544 x 3.607 WLCSP + 0x2005 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + RAM + RAM variant + 0x00C + read-only + 0xFFFFFFFF + + + RAM + RAM variant + 0 + 31 + + + K16 + 16 kByte RAM + 0x10 + + + K32 + 32 kByte RAM + 0x20 + + + K64 + 64 kByte RAM + 0x40 + + + K128 + 128 kByte RAM + 0x80 + + + K256 + 256 kByte RAM + 0x100 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + FLASH + Flash variant + 0x010 + read-only + 0xFFFFFFFF + + + FLASH + Flash variant + 0 + 31 + + + K128 + 128 kByte FLASH + 0x80 + + + K256 + 256 kByte FLASH + 0x100 + + + K512 + 512 kByte FLASH + 0x200 + + + K1024 + 1 MByte FLASH + 0x400 + + + K2048 + 2 MByte FLASH + 0x800 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + + 0x3 + 0x4 + PRODTEST[%s] + Description collection: Production test signature n + 0x350 + read-only + 0xFFFFFFFF + + + PRODTEST + Production test signature n + 0 + 31 + + + Done + Production tests done + 0xBB42319F + + + NotDone + Production tests not done + 0xFFFFFFFF + + + + + + + TEMP + Registers storing factory TEMP module linearization coefficients + FICR_TEMP + read-only + 0x404 + + A0 + Slope definition A0 + 0x000 + read-only + 0xFFFFFFFF + + + A + A (slope definition) register. + 0 + 11 + + + + + A1 + Slope definition A1 + 0x004 + read-only + 0xFFFFFFFF + + + A + A (slope definition) register. + 0 + 11 + + + + + A2 + Slope definition A2 + 0x008 + read-only + 0xFFFFFFFF + + + A + A (slope definition) register. + 0 + 11 + + + + + A3 + Slope definition A3 + 0x00C + read-only + 0xFFFFFFFF + + + A + A (slope definition) register. + 0 + 11 + + + + + A4 + Slope definition A4 + 0x010 + read-only + 0xFFFFFFFF + + + A + A (slope definition) register. + 0 + 11 + + + + + A5 + Slope definition A5 + 0x014 + read-only + 0xFFFFFFFF + + + A + A (slope definition) register. + 0 + 11 + + + + + B0 + Y-intercept B0 + 0x018 + read-only + 0xFFFFFFFF + + + B + B (y-intercept) + 0 + 13 + + + + + B1 + Y-intercept B1 + 0x01C + read-only + 0xFFFFFFFF + + + B + B (y-intercept) + 0 + 13 + + + + + B2 + Y-intercept B2 + 0x020 + read-only + 0xFFFFFFFF + + + B + B (y-intercept) + 0 + 13 + + + + + B3 + Y-intercept B3 + 0x024 + read-only + 0xFFFFFFFF + + + B + B (y-intercept) + 0 + 13 + + + + + B4 + Y-intercept B4 + 0x028 + read-only + 0xFFFFFFFF + + + B + B (y-intercept) + 0 + 13 + + + + + B5 + Y-intercept B5 + 0x02C + read-only + 0xFFFFFFFF + + + B + B (y-intercept) + 0 + 13 + + + + + T0 + Segment end T0 + 0x030 + read-only + 0xFFFFFFFF + + + T + T (segment end) register + 0 + 7 + + + + + T1 + Segment end T1 + 0x034 + read-only + 0xFFFFFFFF + + + T + T (segment end) register + 0 + 7 + + + + + T2 + Segment end T2 + 0x038 + read-only + 0xFFFFFFFF + + + T + T (segment end) register + 0 + 7 + + + + + T3 + Segment end T3 + 0x03C + read-only + 0xFFFFFFFF + + + T + T (segment end) register + 0 + 7 + + + + + T4 + Segment end T4 + 0x040 + read-only + 0xFFFFFFFF + + + T + T (segment end) register + 0 + 7 + + + + + + NFC + Unspecified + FICR_NFC + read-write + 0x450 + + TAGHEADER0 + Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. + 0x000 + read-only + 0xFFFFFF5F + + + MFGID + Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F + 0 + 7 + + + UD1 + Unique identifier byte 1 + 8 + 15 + + + UD2 + Unique identifier byte 2 + 16 + 23 + + + UD3 + Unique identifier byte 3 + 24 + 31 + + + + + TAGHEADER1 + Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. + 0x004 + read-only + 0xFFFFFFFF + + + UD4 + Unique identifier byte 4 + 0 + 7 + + + UD5 + Unique identifier byte 5 + 8 + 15 + + + UD6 + Unique identifier byte 6 + 16 + 23 + + + UD7 + Unique identifier byte 7 + 24 + 31 + + + + + TAGHEADER2 + Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. + 0x008 + read-only + 0xFFFFFFFF + + + UD8 + Unique identifier byte 8 + 0 + 7 + + + UD9 + Unique identifier byte 9 + 8 + 15 + + + UD10 + Unique identifier byte 10 + 16 + 23 + + + UD11 + Unique identifier byte 11 + 24 + 31 + + + + + TAGHEADER3 + Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. + 0x00C + read-only + 0xFFFFFFFF + + + UD12 + Unique identifier byte 12 + 0 + 7 + + + UD13 + Unique identifier byte 13 + 8 + 15 + + + UD14 + Unique identifier byte 14 + 16 + 23 + + + UD15 + Unique identifier byte 15 + 24 + 31 + + + + + + TRNG90B + NIST800-90B RNG calibration data + FICR_TRNG90B + read-write + 0xC00 + + BYTES + Amount of bytes for the required entropy bits + 0x000 + read-only + 0xFFFFFFFF + + + BYTES + Amount of bytes for the required entropy bits + 0 + 31 + + + + + RCCUTOFF + Repetition counter cutoff + 0x004 + read-only + 0xFFFFFFFF + + + RCCUTOFF + Repetition counter cutoff + 0 + 31 + + + + + APCUTOFF + Adaptive proportion cutoff + 0x008 + read-only + 0xFFFFFFFF + + + APCUTOFF + Adaptive proportion cutoff + 0 + 31 + + + + + STARTUP + Amount of bytes for the startup tests + 0x00C + read-only + 0xFFFFFFFF + + + STARTUP + Amount of bytes for the startup tests + 0 + 31 + + + + + ROSC1 + Sample count for ring oscillator 1 + 0x010 + read-only + 0xFFFFFFFF + + + ROSC1 + Sample count for ring oscillator 1 + 0 + 31 + + + + + ROSC2 + Sample count for ring oscillator 2 + 0x014 + read-only + 0xFFFFFFFF + + + ROSC2 + Sample count for ring oscillator 2 + 0 + 31 + + + + + ROSC3 + Sample count for ring oscillator 3 + 0x018 + read-only + 0xFFFFFFFF + + + ROSC3 + Sample count for ring oscillator 3 + 0 + 31 + + + + + ROSC4 + Sample count for ring oscillator 4 + 0x01C + read-only + 0xFFFFFFFF + + + ROSC4 + Sample count for ring oscillator 4 + 0 + 31 + + + + + + + + UICR + User information configuration registers + 0x10001000 + + 0 + 0x1000 + registers + + UICR + 0x20 + + + 0xD + 0x4 + NRFFW[%s] + Description collection: Reserved for Nordic firmware design + 0x014 + read-write + 0xFFFFFFFF + + + NRFFW + Reserved for Nordic firmware design + 0 + 31 + + + + + 0xC + 0x4 + NRFHW[%s] + Description collection: Reserved for Nordic hardware design + 0x050 + read-write + 0xFFFFFFFF + + + NRFHW + Reserved for Nordic hardware design + 0 + 31 + + + + + 0x20 + 0x4 + CUSTOMER[%s] + Description collection: Reserved for customer + 0x080 + read-write + 0xFFFFFFFF + + + CUSTOMER + Reserved for customer + 0 + 31 + + + + + 0x2 + 0x4 + PSELRESET[%s] + Description collection: Mapping of the nRESET function (see POWER chapter for details) + 0x200 + read-write + 0xFFFFFFFF + + + PIN + GPIO pin number onto which nRESET is exposed + 0 + 4 + + + PORT + Port number onto which nRESET is exposed + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + APPROTECT + Access port protection + 0x208 + read-write + 0xFFFFFFFF + + + PALL + Enable or disable access port protection. + 0 + 7 + + + Disabled + Hardware disable of access port protection for devices where access port protection is controlled by hardware + 0xFF + + + HwDisabled + Hardware disable of access port protection for devices where access port protection is controlled by hardware and software + 0x5A + + + Enabled + Enable + 0x00 + + + + + + + NFCPINS + Setting of pins dedicated to NFC functionality: NFC antenna or GPIO + 0x20C + read-write + 0xFFFFFFFF + + + PROTECT + Setting of pins dedicated to NFC functionality + 0 + 0 + + + Disabled + Operation as GPIO pins. Same protection as normal GPIO pins. + 0 + + + NFC + Operation as NFC antenna pins. Configures the protection for NFC operation. + 1 + + + + + + + DEBUGCTRL + Processor debug control + 0x210 + read-write + 0xFFFFFFFF + + + CPUNIDEN + Configure CPU non-intrusive debug features + 0 + 7 + + + Enabled + Enable CPU ITM and ETM functionality (default behavior) + 0xFF + + + Disabled + Disable CPU ITM and ETM functionality + 0x00 + + + + + CPUFPBEN + Configure CPU flash patch and breakpoint (FPB) unit behavior + 8 + 15 + + + Enabled + Enable CPU FPB unit (default behavior) + 0xFF + + + Disabled + Disable CPU FPB unit. Writes into the FPB registers will be ignored. + 0x00 + + + + + + + REGOUT0 + Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - V_VDDH-VDD. + 0x304 + read-write + 0xFFFFFFFF + + + VOUT + Output voltage from REG0 regulator stage. + 0 + 2 + + + 1V8 + 1.8 V + 0 + + + 2V1 + 2.1 V + 1 + + + 2V4 + 2.4 V + 2 + + + 2V7 + 2.7 V + 3 + + + 3V0 + 3.0 V + 4 + + + 3V3 + 3.3 V + 5 + + + DEFAULT + Default voltage: 1.8 V + 7 + + + + + + + + + APPROTECT + Access Port Protection + 0x40000000 + + 0 + 0x1000 + registers + + APPROTECT + 0x20 + + + FORCEPROTECT + Software force enable APPROTECT mechanism until next reset. + 0x550 + read-writeonce + 0xFFFFFFFF + + + FORCEPROTECT + Write 0x0 to force enable APPROTECT mechanism + 0 + 7 + + write + + Force + Software force enable APPROTECT mechanism + 0x0 + + + + + + + DISABLE + Software disable APPROTECT mechanism + 0x558 + read-write + 0x00000000 + + + DISABLE + Software disable APPROTECT mechanism + 0 + 7 + + + SwDisable + Software disable APPROTECT mechanism + 0x5A + + + + + + + + + CLOCK + Clock control + 0x40000000 + APPROTECT + + 0 + 0x1000 + registers + + + POWER_CLOCK + 0 + + CLOCK + 0x20 + + + TASKS_HFCLKSTART + Start HFXO crystal oscillator + 0x000 + write-only + + + TASKS_HFCLKSTART + Start HFXO crystal oscillator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_HFCLKSTOP + Stop HFXO crystal oscillator + 0x004 + write-only + + + TASKS_HFCLKSTOP + Stop HFXO crystal oscillator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LFCLKSTART + Start LFCLK + 0x008 + write-only + + + TASKS_LFCLKSTART + Start LFCLK + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LFCLKSTOP + Stop LFCLK + 0x00C + write-only + + + TASKS_LFCLKSTOP + Stop LFCLK + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CAL + Start calibration of LFRC + 0x010 + write-only + + + TASKS_CAL + Start calibration of LFRC + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CTSTART + Start calibration timer + 0x014 + write-only + + + TASKS_CTSTART + Start calibration timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CTSTOP + Stop calibration timer + 0x018 + write-only + + + TASKS_CTSTOP + Stop calibration timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_HFCLKSTARTED + HFXO crystal oscillator started + 0x100 + read-write + + + EVENTS_HFCLKSTARTED + HFXO crystal oscillator started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LFCLKSTARTED + LFCLK started + 0x104 + read-write + + + EVENTS_LFCLKSTARTED + LFCLK started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DONE + Calibration of LFRC completed + 0x10C + read-write + + + EVENTS_DONE + Calibration of LFRC completed + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CTTO + Calibration timer timeout + 0x110 + read-write + + + EVENTS_CTTO + Calibration timer timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CTSTARTED + Calibration timer has been started and is ready to process new tasks + 0x128 + read-write + + + EVENTS_CTSTARTED + Calibration timer has been started and is ready to process new tasks + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CTSTOPPED + Calibration timer has been stopped and is ready to process new tasks + 0x12C + read-write + + + EVENTS_CTSTOPPED + Calibration timer has been stopped and is ready to process new tasks + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + HFCLKSTARTED + Write '1' to enable interrupt for event HFCLKSTARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LFCLKSTARTED + Write '1' to enable interrupt for event LFCLKSTARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DONE + Write '1' to enable interrupt for event DONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CTTO + Write '1' to enable interrupt for event CTTO + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CTSTARTED + Write '1' to enable interrupt for event CTSTARTED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CTSTOPPED + Write '1' to enable interrupt for event CTSTOPPED + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + HFCLKSTARTED + Write '1' to disable interrupt for event HFCLKSTARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LFCLKSTARTED + Write '1' to disable interrupt for event LFCLKSTARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DONE + Write '1' to disable interrupt for event DONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CTTO + Write '1' to disable interrupt for event CTTO + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CTSTARTED + Write '1' to disable interrupt for event CTSTARTED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CTSTOPPED + Write '1' to disable interrupt for event CTSTOPPED + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + HFCLKRUN + Status indicating that HFCLKSTART task has been triggered + 0x408 + read-only + + + STATUS + HFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + HFCLKSTAT + HFCLK status + 0x40C + read-only + + + SRC + Source of HFCLK + 0 + 0 + + + RC + 64 MHz internal oscillator (HFINT) + 0 + + + Xtal + 64 MHz crystal oscillator (HFXO) + 1 + + + + + STATE + HFCLK state + 16 + 16 + + + NotRunning + HFCLK not running + 0 + + + Running + HFCLK running + 1 + + + + + + + LFCLKRUN + Status indicating that LFCLKSTART task has been triggered + 0x414 + read-only + + + STATUS + LFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + LFCLKSTAT + LFCLK status + 0x418 + read-only + + + SRC + Source of LFCLK + 0 + 1 + + + RC + 32.768 kHz RC oscillator (LFRC) + 0 + + + Xtal + 32.768 kHz crystal oscillator (LFXO) + 1 + + + Synth + 32.768 kHz synthesized from HFCLK (LFSYNT) + 2 + + + + + STATE + LFCLK state + 16 + 16 + + + NotRunning + LFCLK not running + 0 + + + Running + LFCLK running + 1 + + + + + + + LFCLKSRCCOPY + Copy of LFCLKSRC register, set when LFCLKSTART task was triggered + 0x41C + read-only + + + SRC + Clock source + 0 + 1 + + + RC + 32.768 kHz RC oscillator (LFRC) + 0 + + + Xtal + 32.768 kHz crystal oscillator (LFXO) + 1 + + + Synth + 32.768 kHz synthesized from HFCLK (LFSYNT) + 2 + + + + + + + LFCLKSRC + Clock source for the LFCLK + 0x518 + read-write + + + SRC + Clock source + 0 + 1 + + + RC + 32.768 kHz RC oscillator (LFRC) + 0 + + + Xtal + 32.768 kHz crystal oscillator (LFXO) + 1 + + + Synth + 32.768 kHz synthesized from HFCLK (LFSYNT) + 2 + + + + + BYPASS + Enable or disable bypass of LFCLK crystal oscillator with external clock source + 16 + 16 + + + Disabled + Disable (use with Xtal or low-swing external source) + 0 + + + Enabled + Enable (use with rail-to-rail external source) + 1 + + + + + EXTERNAL + Enable or disable external source for LFCLK + 17 + 17 + + + Disabled + Disable external source (use with Xtal) + 0 + + + Enabled + Enable use of external source instead of Xtal (SRC needs to be set to Xtal) + 1 + + + + + + + HFXODEBOUNCE + HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task. + 0x528 + read-write + 0x00000010 + + + HFXODEBOUNCE + HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us. + 0 + 7 + + + Db256us + 256 us debounce time. Recommended for TSX-3225, FA-20H and FA-128 crystals. + 0x10 + + + Db1024us + 1024 us debounce time. Recommended for NX1612AA and NX1210AB crystals. + 0x40 + + + + + + + CTIV + Calibration timer interval + 0x538 + read-write + + + CTIV + Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. + 0 + 6 + + + + + TRACECONFIG + Clocking options for the trace port debug interface + 0x55C + read-write + 0x00000000 + + + TRACEPORTSPEED + Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two. + 0 + 1 + + + 32MHz + 32 MHz trace port clock (TRACECLK = 16 MHz) + 0 + + + 16MHz + 16 MHz trace port clock (TRACECLK = 8 MHz) + 1 + + + 8MHz + 8 MHz trace port clock (TRACECLK = 4 MHz) + 2 + + + 4MHz + 4 MHz trace port clock (TRACECLK = 2 MHz) + 3 + + + + + TRACEMUX + Pin multiplexing of trace signals. See pin assignment chapter for more details. + 16 + 17 + + + GPIO + No trace signals routed to pins. All pins can be used as regular GPIOs. + 0 + + + Serial + SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs. + 1 + + + Parallel + All trace signals (TRACECLK and TRACEDATA[n]) routed to pins. + 2 + + + + + + + LFRCMODE + LFRC mode configuration + 0x5B4 + read-write + 0x00000000 + + + MODE + Set LFRC mode + 0 + 0 + + + Normal + Normal mode + 0 + + + ULP + Ultra-low power mode (ULP) + 1 + + + + + STATUS + Active LFRC mode. This field is read only. + 16 + 16 + + + Normal + Normal mode + 0 + + + ULP + Ultra-low power mode (ULP) + 1 + + + + + + + + + POWER + Power control + 0x40000000 + APPROTECT + + 0 + 0x1000 + registers + + + POWER_CLOCK + 0 + + POWER + 0x20 + + + TASKS_CONSTLAT + Enable Constant Latency mode + 0x78 + write-only + + + TASKS_CONSTLAT + Enable Constant Latency mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LOWPWR + Enable Low-power mode (variable latency) + 0x7C + write-only + + + TASKS_LOWPWR + Enable Low-power mode (variable latency) + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_POFWARN + Power failure warning + 0x108 + read-write + + + EVENTS_POFWARN + Power failure warning + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep + 0x114 + read-write + + + EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep + 0x118 + read-write + + + EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_USBDETECTED + Voltage supply detected on VBUS + 0x11C + read-write + + + EVENTS_USBDETECTED + Voltage supply detected on VBUS + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_USBREMOVED + Voltage supply removed from VBUS + 0x120 + read-write + + + EVENTS_USBREMOVED + Voltage supply removed from VBUS + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_USBPWRRDY + USB 3.3 V supply ready + 0x124 + read-write + + + EVENTS_USBPWRRDY + USB 3.3 V supply ready + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + POFWARN + Write '1' to enable interrupt for event POFWARN + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SLEEPENTER + Write '1' to enable interrupt for event SLEEPENTER + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SLEEPEXIT + Write '1' to enable interrupt for event SLEEPEXIT + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + USBDETECTED + Write '1' to enable interrupt for event USBDETECTED + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + USBREMOVED + Write '1' to enable interrupt for event USBREMOVED + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + USBPWRRDY + Write '1' to enable interrupt for event USBPWRRDY + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + POFWARN + Write '1' to disable interrupt for event POFWARN + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SLEEPENTER + Write '1' to disable interrupt for event SLEEPENTER + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SLEEPEXIT + Write '1' to disable interrupt for event SLEEPEXIT + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + USBDETECTED + Write '1' to disable interrupt for event USBDETECTED + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + USBREMOVED + Write '1' to disable interrupt for event USBREMOVED + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + USBPWRRDY + Write '1' to disable interrupt for event USBPWRRDY + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RESETREAS + Reset reason + 0x400 + read-write + + + RESETPIN + Reset from pin-reset detected + 0 + 0 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + DOG + Reset from watchdog detected + 1 + 1 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + SREQ + Reset from soft reset detected + 2 + 2 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + LOCKUP + Reset from CPU lock-up detected + 3 + 3 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + OFF + Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO + 16 + 16 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + LPCOMP + Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP + 17 + 17 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + DIF + Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode + 18 + 18 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + NFC + Reset due to wake up from System OFF mode by NFC field detect + 19 + 19 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + VBUS + Reset due to wake up from System OFF mode by VBUS rising into valid range + 20 + 20 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + + + RAMSTATUS + Deprecated register - RAM status register + 0x428 + read-only + 0x00000000 + + + RAMBLOCK0 + RAM block 0 is on or off/powering up + 0 + 0 + + + Off + Off + 0 + + + On + On + 1 + + + + + RAMBLOCK1 + RAM block 1 is on or off/powering up + 1 + 1 + + + Off + Off + 0 + + + On + On + 1 + + + + + RAMBLOCK2 + RAM block 2 is on or off/powering up + 2 + 2 + + + Off + Off + 0 + + + On + On + 1 + + + + + RAMBLOCK3 + RAM block 3 is on or off/powering up + 3 + 3 + + + Off + Off + 0 + + + On + On + 1 + + + + + + + USBREGSTATUS + USB supply status + 0x438 + read-only + 0x00000000 + + + VBUSDETECT + VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information) + 0 + 0 + + + NoVbus + VBUS voltage below valid threshold + 0 + + + VbusPresent + VBUS voltage above valid threshold + 1 + + + + + OUTPUTRDY + USB supply output settling time elapsed + 1 + 1 + + + NotReady + USBREG output settling time not elapsed + 0 + + + Ready + USBREG output settling time elapsed (same information as USBPWRRDY event) + 1 + + + + + + + SYSTEMOFF + System OFF register + 0x500 + write-only + + + SYSTEMOFF + Enable System OFF mode + 0 + 0 + + + Enter + Enable System OFF mode + 1 + + + + + + + POFCON + Power-fail comparator configuration + 0x510 + read-write + + + POF + Enable or disable power failure warning + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + THRESHOLD + Power-fail comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). Values 0-3 set threshold below 1.7 V and should not be used as brown out detection will be activated before power failure warning on such low voltages. + 1 + 4 + + + V17 + Set threshold to 1.7 V + 4 + + + V18 + Set threshold to 1.8 V + 5 + + + V19 + Set threshold to 1.9 V + 6 + + + V20 + Set threshold to 2.0 V + 7 + + + V21 + Set threshold to 2.1 V + 8 + + + V22 + Set threshold to 2.2 V + 9 + + + V23 + Set threshold to 2.3 V + 10 + + + V24 + Set threshold to 2.4 V + 11 + + + V25 + Set threshold to 2.5 V + 12 + + + V26 + Set threshold to 2.6 V + 13 + + + V27 + Set threshold to 2.7 V + 14 + + + V28 + Set threshold to 2.8 V + 15 + + + + + THRESHOLDVDDH + Power-fail comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH). + 8 + 11 + + + V27 + Set threshold to 2.7 V + 0 + + + V28 + Set threshold to 2.8 V + 1 + + + V29 + Set threshold to 2.9 V + 2 + + + V30 + Set threshold to 3.0 V + 3 + + + V31 + Set threshold to 3.1 V + 4 + + + V32 + Set threshold to 3.2 V + 5 + + + V33 + Set threshold to 3.3 V + 6 + + + V34 + Set threshold to 3.4 V + 7 + + + V35 + Set threshold to 3.5 V + 8 + + + V36 + Set threshold to 3.6 V + 9 + + + V37 + Set threshold to 3.7 V + 10 + + + V38 + Set threshold to 3.8 V + 11 + + + V39 + Set threshold to 3.9 V + 12 + + + V40 + Set threshold to 4.0 V + 13 + + + V41 + Set threshold to 4.1 V + 14 + + + V42 + Set threshold to 4.2 V + 15 + + + + + + + GPREGRET + General purpose retention register + 0x51C + read-write + + + GPREGRET + General purpose retention register + 0 + 7 + + + + + GPREGRET2 + General purpose retention register + 0x520 + read-write + + + GPREGRET + General purpose retention register + 0 + 7 + + + + + DCDCEN + Enable DC/DC converter for REG1 stage + 0x578 + read-write + + + DCDCEN + Enable DC/DC converter for REG1 stage. + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + DCDCEN0 + Enable DC/DC converter for REG0 stage + 0x580 + read-write + + + DCDCEN + Enable DC/DC converter for REG0 stage. + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + MAINREGSTATUS + Main supply status + 0x640 + read-only + 0x00000000 + + + MAINREGSTATUS + Main supply status + 0 + 0 + + + Normal + Normal voltage mode. Voltage supplied on VDD. + 0 + + + High + High voltage mode. Voltage supplied on VDDH. + 1 + + + + + + + 9 + 0x010 + RAM[%s] + Unspecified + POWER_RAM + read-write + 0x900 + + POWER + Description cluster: RAMn power control register + 0x000 + read-write + 0x0000FFFF + + + S0POWER + Keep RAM section S0 on or off in System ON mode. + 0 + 0 + + + Off + Off + 0 + + + On + On + 1 + + + + + S1POWER + Keep RAM section S1 on or off in System ON mode. + 1 + 1 + + + Off + Off + 0 + + + On + On + 1 + + + + + S2POWER + Keep RAM section S2 on or off in System ON mode. + 2 + 2 + + + Off + Off + 0 + + + On + On + 1 + + + + + S3POWER + Keep RAM section S3 on or off in System ON mode. + 3 + 3 + + + Off + Off + 0 + + + On + On + 1 + + + + + S4POWER + Keep RAM section S4 on or off in System ON mode. + 4 + 4 + + + Off + Off + 0 + + + On + On + 1 + + + + + S5POWER + Keep RAM section S5 on or off in System ON mode. + 5 + 5 + + + Off + Off + 0 + + + On + On + 1 + + + + + S6POWER + Keep RAM section S6 on or off in System ON mode. + 6 + 6 + + + Off + Off + 0 + + + On + On + 1 + + + + + S7POWER + Keep RAM section S7 on or off in System ON mode. + 7 + 7 + + + Off + Off + 0 + + + On + On + 1 + + + + + S8POWER + Keep RAM section S8 on or off in System ON mode. + 8 + 8 + + + Off + Off + 0 + + + On + On + 1 + + + + + S9POWER + Keep RAM section S9 on or off in System ON mode. + 9 + 9 + + + Off + Off + 0 + + + On + On + 1 + + + + + S10POWER + Keep RAM section S10 on or off in System ON mode. + 10 + 10 + + + Off + Off + 0 + + + On + On + 1 + + + + + S11POWER + Keep RAM section S11 on or off in System ON mode. + 11 + 11 + + + Off + Off + 0 + + + On + On + 1 + + + + + S12POWER + Keep RAM section S12 on or off in System ON mode. + 12 + 12 + + + Off + Off + 0 + + + On + On + 1 + + + + + S13POWER + Keep RAM section S13 on or off in System ON mode. + 13 + 13 + + + Off + Off + 0 + + + On + On + 1 + + + + + S14POWER + Keep RAM section S14 on or off in System ON mode. + 14 + 14 + + + Off + Off + 0 + + + On + On + 1 + + + + + S15POWER + Keep RAM section S15 on or off in System ON mode. + 15 + 15 + + + Off + Off + 0 + + + On + On + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 when RAM section is off + 16 + 16 + + + Off + Off + 0 + + + On + On + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 when RAM section is off + 17 + 17 + + + Off + Off + 0 + + + On + On + 1 + + + + + S2RETENTION + Keep retention on RAM section S2 when RAM section is off + 18 + 18 + + + Off + Off + 0 + + + On + On + 1 + + + + + S3RETENTION + Keep retention on RAM section S3 when RAM section is off + 19 + 19 + + + Off + Off + 0 + + + On + On + 1 + + + + + S4RETENTION + Keep retention on RAM section S4 when RAM section is off + 20 + 20 + + + Off + Off + 0 + + + On + On + 1 + + + + + S5RETENTION + Keep retention on RAM section S5 when RAM section is off + 21 + 21 + + + Off + Off + 0 + + + On + On + 1 + + + + + S6RETENTION + Keep retention on RAM section S6 when RAM section is off + 22 + 22 + + + Off + Off + 0 + + + On + On + 1 + + + + + S7RETENTION + Keep retention on RAM section S7 when RAM section is off + 23 + 23 + + + Off + Off + 0 + + + On + On + 1 + + + + + S8RETENTION + Keep retention on RAM section S8 when RAM section is off + 24 + 24 + + + Off + Off + 0 + + + On + On + 1 + + + + + S9RETENTION + Keep retention on RAM section S9 when RAM section is off + 25 + 25 + + + Off + Off + 0 + + + On + On + 1 + + + + + S10RETENTION + Keep retention on RAM section S10 when RAM section is off + 26 + 26 + + + Off + Off + 0 + + + On + On + 1 + + + + + S11RETENTION + Keep retention on RAM section S11 when RAM section is off + 27 + 27 + + + Off + Off + 0 + + + On + On + 1 + + + + + S12RETENTION + Keep retention on RAM section S12 when RAM section is off + 28 + 28 + + + Off + Off + 0 + + + On + On + 1 + + + + + S13RETENTION + Keep retention on RAM section S13 when RAM section is off + 29 + 29 + + + Off + Off + 0 + + + On + On + 1 + + + + + S14RETENTION + Keep retention on RAM section S14 when RAM section is off + 30 + 30 + + + Off + Off + 0 + + + On + On + 1 + + + + + S15RETENTION + Keep retention on RAM section S15 when RAM section is off + 31 + 31 + + + Off + Off + 0 + + + On + On + 1 + + + + + + + POWERSET + Description cluster: RAMn power control set register + 0x004 + write-only + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAMn on or off in System ON mode + 0 + 0 + + + On + On + 1 + + + + + S1POWER + Keep RAM section S1 of RAMn on or off in System ON mode + 1 + 1 + + + On + On + 1 + + + + + S2POWER + Keep RAM section S2 of RAMn on or off in System ON mode + 2 + 2 + + + On + On + 1 + + + + + S3POWER + Keep RAM section S3 of RAMn on or off in System ON mode + 3 + 3 + + + On + On + 1 + + + + + S4POWER + Keep RAM section S4 of RAMn on or off in System ON mode + 4 + 4 + + + On + On + 1 + + + + + S5POWER + Keep RAM section S5 of RAMn on or off in System ON mode + 5 + 5 + + + On + On + 1 + + + + + S6POWER + Keep RAM section S6 of RAMn on or off in System ON mode + 6 + 6 + + + On + On + 1 + + + + + S7POWER + Keep RAM section S7 of RAMn on or off in System ON mode + 7 + 7 + + + On + On + 1 + + + + + S8POWER + Keep RAM section S8 of RAMn on or off in System ON mode + 8 + 8 + + + On + On + 1 + + + + + S9POWER + Keep RAM section S9 of RAMn on or off in System ON mode + 9 + 9 + + + On + On + 1 + + + + + S10POWER + Keep RAM section S10 of RAMn on or off in System ON mode + 10 + 10 + + + On + On + 1 + + + + + S11POWER + Keep RAM section S11 of RAMn on or off in System ON mode + 11 + 11 + + + On + On + 1 + + + + + S12POWER + Keep RAM section S12 of RAMn on or off in System ON mode + 12 + 12 + + + On + On + 1 + + + + + S13POWER + Keep RAM section S13 of RAMn on or off in System ON mode + 13 + 13 + + + On + On + 1 + + + + + S14POWER + Keep RAM section S14 of RAMn on or off in System ON mode + 14 + 14 + + + On + On + 1 + + + + + S15POWER + Keep RAM section S15 of RAMn on or off in System ON mode + 15 + 15 + + + On + On + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 when RAM section is switched off + 16 + 16 + + + On + On + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 when RAM section is switched off + 17 + 17 + + + On + On + 1 + + + + + S2RETENTION + Keep retention on RAM section S2 when RAM section is switched off + 18 + 18 + + + On + On + 1 + + + + + S3RETENTION + Keep retention on RAM section S3 when RAM section is switched off + 19 + 19 + + + On + On + 1 + + + + + S4RETENTION + Keep retention on RAM section S4 when RAM section is switched off + 20 + 20 + + + On + On + 1 + + + + + S5RETENTION + Keep retention on RAM section S5 when RAM section is switched off + 21 + 21 + + + On + On + 1 + + + + + S6RETENTION + Keep retention on RAM section S6 when RAM section is switched off + 22 + 22 + + + On + On + 1 + + + + + S7RETENTION + Keep retention on RAM section S7 when RAM section is switched off + 23 + 23 + + + On + On + 1 + + + + + S8RETENTION + Keep retention on RAM section S8 when RAM section is switched off + 24 + 24 + + + On + On + 1 + + + + + S9RETENTION + Keep retention on RAM section S9 when RAM section is switched off + 25 + 25 + + + On + On + 1 + + + + + S10RETENTION + Keep retention on RAM section S10 when RAM section is switched off + 26 + 26 + + + On + On + 1 + + + + + S11RETENTION + Keep retention on RAM section S11 when RAM section is switched off + 27 + 27 + + + On + On + 1 + + + + + S12RETENTION + Keep retention on RAM section S12 when RAM section is switched off + 28 + 28 + + + On + On + 1 + + + + + S13RETENTION + Keep retention on RAM section S13 when RAM section is switched off + 29 + 29 + + + On + On + 1 + + + + + S14RETENTION + Keep retention on RAM section S14 when RAM section is switched off + 30 + 30 + + + On + On + 1 + + + + + S15RETENTION + Keep retention on RAM section S15 when RAM section is switched off + 31 + 31 + + + On + On + 1 + + + + + + + POWERCLR + Description cluster: RAMn power control clear register + 0x008 + write-only + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAMn on or off in System ON mode + 0 + 0 + + + Off + Off + 1 + + + + + S1POWER + Keep RAM section S1 of RAMn on or off in System ON mode + 1 + 1 + + + Off + Off + 1 + + + + + S2POWER + Keep RAM section S2 of RAMn on or off in System ON mode + 2 + 2 + + + Off + Off + 1 + + + + + S3POWER + Keep RAM section S3 of RAMn on or off in System ON mode + 3 + 3 + + + Off + Off + 1 + + + + + S4POWER + Keep RAM section S4 of RAMn on or off in System ON mode + 4 + 4 + + + Off + Off + 1 + + + + + S5POWER + Keep RAM section S5 of RAMn on or off in System ON mode + 5 + 5 + + + Off + Off + 1 + + + + + S6POWER + Keep RAM section S6 of RAMn on or off in System ON mode + 6 + 6 + + + Off + Off + 1 + + + + + S7POWER + Keep RAM section S7 of RAMn on or off in System ON mode + 7 + 7 + + + Off + Off + 1 + + + + + S8POWER + Keep RAM section S8 of RAMn on or off in System ON mode + 8 + 8 + + + Off + Off + 1 + + + + + S9POWER + Keep RAM section S9 of RAMn on or off in System ON mode + 9 + 9 + + + Off + Off + 1 + + + + + S10POWER + Keep RAM section S10 of RAMn on or off in System ON mode + 10 + 10 + + + Off + Off + 1 + + + + + S11POWER + Keep RAM section S11 of RAMn on or off in System ON mode + 11 + 11 + + + Off + Off + 1 + + + + + S12POWER + Keep RAM section S12 of RAMn on or off in System ON mode + 12 + 12 + + + Off + Off + 1 + + + + + S13POWER + Keep RAM section S13 of RAMn on or off in System ON mode + 13 + 13 + + + Off + Off + 1 + + + + + S14POWER + Keep RAM section S14 of RAMn on or off in System ON mode + 14 + 14 + + + Off + Off + 1 + + + + + S15POWER + Keep RAM section S15 of RAMn on or off in System ON mode + 15 + 15 + + + Off + Off + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 when RAM section is switched off + 16 + 16 + + + Off + Off + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 when RAM section is switched off + 17 + 17 + + + Off + Off + 1 + + + + + S2RETENTION + Keep retention on RAM section S2 when RAM section is switched off + 18 + 18 + + + Off + Off + 1 + + + + + S3RETENTION + Keep retention on RAM section S3 when RAM section is switched off + 19 + 19 + + + Off + Off + 1 + + + + + S4RETENTION + Keep retention on RAM section S4 when RAM section is switched off + 20 + 20 + + + Off + Off + 1 + + + + + S5RETENTION + Keep retention on RAM section S5 when RAM section is switched off + 21 + 21 + + + Off + Off + 1 + + + + + S6RETENTION + Keep retention on RAM section S6 when RAM section is switched off + 22 + 22 + + + Off + Off + 1 + + + + + S7RETENTION + Keep retention on RAM section S7 when RAM section is switched off + 23 + 23 + + + Off + Off + 1 + + + + + S8RETENTION + Keep retention on RAM section S8 when RAM section is switched off + 24 + 24 + + + Off + Off + 1 + + + + + S9RETENTION + Keep retention on RAM section S9 when RAM section is switched off + 25 + 25 + + + Off + Off + 1 + + + + + S10RETENTION + Keep retention on RAM section S10 when RAM section is switched off + 26 + 26 + + + Off + Off + 1 + + + + + S11RETENTION + Keep retention on RAM section S11 when RAM section is switched off + 27 + 27 + + + Off + Off + 1 + + + + + S12RETENTION + Keep retention on RAM section S12 when RAM section is switched off + 28 + 28 + + + Off + Off + 1 + + + + + S13RETENTION + Keep retention on RAM section S13 when RAM section is switched off + 29 + 29 + + + Off + Off + 1 + + + + + S14RETENTION + Keep retention on RAM section S14 when RAM section is switched off + 30 + 30 + + + Off + Off + 1 + + + + + S15RETENTION + Keep retention on RAM section S15 when RAM section is switched off + 31 + 31 + + + Off + Off + 1 + + + + + + + + + + P0 + GPIO Port 1 + 0x50000000 + GPIO + + 0 + 0x1000 + registers + + GPIO + 0x20 + + + OUT + Write GPIO port + 0x504 + read-write + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + + + OUTSET + Set individual bits in GPIO port + 0x508 + read-write + oneToSet + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + 1 + Write: a '1' sets the pin high; a '0' has no effect + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: a '1' sets the pin high; a '0' has no effect + 1 + + + + + + + OUTCLR + Clear individual bits in GPIO port + 0x50C + read-write + oneToClear + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: a '1' sets the pin low; a '0' has no effect + 1 + + + + + + + IN + Read GPIO port + 0x510 + read-only + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + + + DIR + Direction of GPIO pins + 0x514 + read-write + + + PIN0 + Pin 0 + 0 + 0 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + + + DIRSET + DIR set register + 0x518 + read-write + oneToSet + + + PIN0 + Set as output pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN1 + Set as output pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN2 + Set as output pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN3 + Set as output pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN4 + Set as output pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN5 + Set as output pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN6 + Set as output pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN7 + Set as output pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN8 + Set as output pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN9 + Set as output pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN10 + Set as output pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN11 + Set as output pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN12 + Set as output pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN13 + Set as output pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN14 + Set as output pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN15 + Set as output pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN16 + Set as output pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN17 + Set as output pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN18 + Set as output pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN19 + Set as output pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN20 + Set as output pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN21 + Set as output pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN22 + Set as output pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN23 + Set as output pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN24 + Set as output pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN25 + Set as output pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN26 + Set as output pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN27 + Set as output pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN28 + Set as output pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN29 + Set as output pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN30 + Set as output pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + PIN31 + Set as output pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: a '1' sets pin to output; a '0' has no effect + 1 + + + + + + + DIRCLR + DIR clear register + 0x51C + read-write + oneToClear + + + PIN0 + Set as input pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN1 + Set as input pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN2 + Set as input pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN3 + Set as input pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN4 + Set as input pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN5 + Set as input pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN6 + Set as input pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN7 + Set as input pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN8 + Set as input pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN9 + Set as input pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN10 + Set as input pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN11 + Set as input pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN12 + Set as input pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN13 + Set as input pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN14 + Set as input pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN15 + Set as input pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN16 + Set as input pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN17 + Set as input pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN18 + Set as input pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN19 + Set as input pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN20 + Set as input pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN21 + Set as input pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN22 + Set as input pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN23 + Set as input pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN24 + Set as input pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN25 + Set as input pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN26 + Set as input pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN27 + Set as input pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN28 + Set as input pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN29 + Set as input pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN30 + Set as input pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + PIN31 + Set as input pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: a '1' sets pin to input; a '0' has no effect + 1 + + + + + + + LATCH + Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers + 0x520 + read-write + + + PIN0 + Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. + 0 + 0 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN1 + Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. + 1 + 1 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN2 + Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. + 2 + 2 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN3 + Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. + 3 + 3 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN4 + Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. + 4 + 4 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN5 + Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. + 5 + 5 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN6 + Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. + 6 + 6 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN7 + Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. + 7 + 7 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN8 + Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. + 8 + 8 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN9 + Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. + 9 + 9 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN10 + Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. + 10 + 10 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN11 + Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. + 11 + 11 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN12 + Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. + 12 + 12 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN13 + Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. + 13 + 13 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN14 + Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. + 14 + 14 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN15 + Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. + 15 + 15 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN16 + Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. + 16 + 16 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN17 + Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. + 17 + 17 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN18 + Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. + 18 + 18 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN19 + Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. + 19 + 19 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN20 + Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. + 20 + 20 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN21 + Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. + 21 + 21 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN22 + Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. + 22 + 22 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN23 + Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. + 23 + 23 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN24 + Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. + 24 + 24 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN25 + Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. + 25 + 25 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN26 + Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. + 26 + 26 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN27 + Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. + 27 + 27 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN28 + Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. + 28 + 28 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN29 + Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. + 29 + 29 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN30 + Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. + 30 + 30 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN31 + Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. + 31 + 31 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0x524 + read-write + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0 + 0 + + + Default + DETECT directly connected to PIN DETECT signals + 0 + + + LDETECT + Use the latched LDETECT behavior + 1 + + + + + + + 0x20 + 0x4 + PIN_CNF[%s] + Description collection: Configuration of GPIO pins + 0x700 + read-write + 0x00000002 + + + DIR + Pin direction. Same physical register as DIR register + 0 + 0 + + + Input + Configure pin as an input pin + 0 + + + Output + Configure pin as an output pin + 1 + + + + + INPUT + Connect or disconnect input buffer + 1 + 1 + + + Connect + Connect input buffer + 0 + + + Disconnect + Disconnect input buffer + 1 + + + + + PULL + Pull configuration + 2 + 3 + + + Disabled + No pull + 0 + + + Pulldown + Pull down on pin + 1 + + + Pullup + Pull up on pin + 3 + + + + + DRIVE + Drive configuration + 8 + 10 + + + S0S1 + Standard '0', standard '1' + 0 + + + H0S1 + High drive '0', standard '1' + 1 + + + S0H1 + Standard '0', high drive '1' + 2 + + + H0H1 + High drive '0', high 'drive '1'' + 3 + + + D0S1 + Disconnect '0' standard '1' (normally used for wired-or connections) + 4 + + + D0H1 + Disconnect '0', high drive '1' (normally used for wired-or connections) + 5 + + + S0D1 + Standard '0'. disconnect '1' (normally used for wired-and connections) + 6 + + + H0D1 + High drive '0', disconnect '1' (normally used for wired-and connections) + 7 + + + + + SENSE + Pin sensing mechanism + 16 + 17 + + + Disabled + Disabled + 0 + + + High + Sense for high level + 2 + + + Low + Sense for low level + 3 + + + + + + + + + P1 + GPIO Port 2 + 0x50000300 + P0 + + + RADIO + 2.4 GHz radio + 0x40001000 + + 0 + 0x1000 + registers + + + RADIO + 1 + + RADIO + 0x20 + + + TASKS_TXEN + Enable RADIO in TX mode + 0x000 + write-only + + + TASKS_TXEN + Enable RADIO in TX mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RXEN + Enable RADIO in RX mode + 0x004 + write-only + + + TASKS_RXEN + Enable RADIO in RX mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_START + Start RADIO + 0x008 + write-only + + + TASKS_START + Start RADIO + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop RADIO + 0x00C + write-only + + + TASKS_STOP + Stop RADIO + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_DISABLE + Disable RADIO + 0x010 + write-only + + + TASKS_DISABLE + Disable RADIO + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RSSISTART + Start the RSSI and take one single sample of the receive signal strength + 0x014 + write-only + + + TASKS_RSSISTART + Start the RSSI and take one single sample of the receive signal strength + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RSSISTOP + Stop the RSSI measurement + 0x018 + write-only + + + TASKS_RSSISTOP + Stop the RSSI measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_BCSTART + Start the bit counter + 0x01C + write-only + + + TASKS_BCSTART + Start the bit counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_BCSTOP + Stop the bit counter + 0x020 + write-only + + + TASKS_BCSTOP + Stop the bit counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_EDSTART + Start the energy detect measurement used in IEEE 802.15.4 mode + 0x024 + write-only + + + TASKS_EDSTART + Start the energy detect measurement used in IEEE 802.15.4 mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_EDSTOP + Stop the energy detect measurement + 0x028 + write-only + + + TASKS_EDSTOP + Stop the energy detect measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CCASTART + Start the clear channel assessment used in IEEE 802.15.4 mode + 0x02C + write-only + + + TASKS_CCASTART + Start the clear channel assessment used in IEEE 802.15.4 mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CCASTOP + Stop the clear channel assessment + 0x030 + write-only + + + TASKS_CCASTOP + Stop the clear channel assessment + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_READY + RADIO has ramped up and is ready to be started + 0x100 + read-write + + + EVENTS_READY + RADIO has ramped up and is ready to be started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ADDRESS + Address sent or received + 0x104 + read-write + + + EVENTS_ADDRESS + Address sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PAYLOAD + Packet payload sent or received + 0x108 + read-write + + + EVENTS_PAYLOAD + Packet payload sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + Packet sent or received + 0x10C + read-write + + + EVENTS_END + Packet sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DISABLED + RADIO has been disabled + 0x110 + read-write + + + EVENTS_DISABLED + RADIO has been disabled + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DEVMATCH + A device address match occurred on the last received packet + 0x114 + read-write + + + EVENTS_DEVMATCH + A device address match occurred on the last received packet + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DEVMISS + No device address match occurred on the last received packet + 0x118 + read-write + + + EVENTS_DEVMISS + No device address match occurred on the last received packet + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RSSIEND + Sampling of receive signal strength complete + 0x11C + read-write + + + EVENTS_RSSIEND + Sampling of receive signal strength complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_BCMATCH + Bit counter reached bit count value + 0x128 + read-write + + + EVENTS_BCMATCH + Bit counter reached bit count value + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CRCOK + Packet received with CRC ok + 0x130 + read-write + + + EVENTS_CRCOK + Packet received with CRC ok + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CRCERROR + Packet received with CRC error + 0x134 + read-write + + + EVENTS_CRCERROR + Packet received with CRC error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_FRAMESTART + IEEE 802.15.4 length field received + 0x138 + read-write + + + EVENTS_FRAMESTART + IEEE 802.15.4 length field received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_EDEND + Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. + 0x13C + read-write + + + EVENTS_EDEND + Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_EDSTOPPED + The sampling of energy detection has stopped + 0x140 + read-write + + + EVENTS_EDSTOPPED + The sampling of energy detection has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CCAIDLE + Wireless medium in idle - clear to send + 0x144 + read-write + + + EVENTS_CCAIDLE + Wireless medium in idle - clear to send + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CCABUSY + Wireless medium busy - do not send + 0x148 + read-write + + + EVENTS_CCABUSY + Wireless medium busy - do not send + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CCASTOPPED + The CCA has stopped + 0x14C + read-write + + + EVENTS_CCASTOPPED + The CCA has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RATEBOOST + Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. + 0x150 + read-write + + + EVENTS_RATEBOOST + Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXREADY + RADIO has ramped up and is ready to be started TX path + 0x154 + read-write + + + EVENTS_TXREADY + RADIO has ramped up and is ready to be started TX path + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXREADY + RADIO has ramped up and is ready to be started RX path + 0x158 + read-write + + + EVENTS_RXREADY + RADIO has ramped up and is ready to be started RX path + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_MHRMATCH + MAC header match found + 0x15C + read-write + + + EVENTS_MHRMATCH + MAC header match found + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SYNC + Preamble indicator. + 0x168 + read-write + + + EVENTS_SYNC + Preamble indicator. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PHYEND + Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. + 0x16C + read-write + + + EVENTS_PHYEND + Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + READY_START + Shortcut between event READY and task START + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + END_DISABLE + Shortcut between event END and task DISABLE + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DISABLED_TXEN + Shortcut between event DISABLED and task TXEN + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DISABLED_RXEN + Shortcut between event DISABLED and task RXEN + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ADDRESS_RSSISTART + Shortcut between event ADDRESS and task RSSISTART + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + END_START + Shortcut between event END and task START + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ADDRESS_BCSTART + Shortcut between event ADDRESS and task BCSTART + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DISABLED_RSSISTOP + Shortcut between event DISABLED and task RSSISTOP + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + RXREADY_CCASTART + Shortcut between event RXREADY and task CCASTART + 11 + 11 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CCAIDLE_TXEN + Shortcut between event CCAIDLE and task TXEN + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CCABUSY_DISABLE + Shortcut between event CCABUSY and task DISABLE + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + FRAMESTART_BCSTART + Shortcut between event FRAMESTART and task BCSTART + 14 + 14 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READY_EDSTART + Shortcut between event READY and task EDSTART + 15 + 15 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + EDEND_DISABLE + Shortcut between event EDEND and task DISABLE + 16 + 16 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CCAIDLE_STOP + Shortcut between event CCAIDLE and task STOP + 17 + 17 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + TXREADY_START + Shortcut between event TXREADY and task START + 18 + 18 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + RXREADY_START + Shortcut between event RXREADY and task START + 19 + 19 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + PHYEND_DISABLE + Shortcut between event PHYEND and task DISABLE + 20 + 20 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + PHYEND_START + Shortcut between event PHYEND and task START + 21 + 21 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ADDRESS + Write '1' to enable interrupt for event ADDRESS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PAYLOAD + Write '1' to enable interrupt for event PAYLOAD + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DISABLED + Write '1' to enable interrupt for event DISABLED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DEVMATCH + Write '1' to enable interrupt for event DEVMATCH + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DEVMISS + Write '1' to enable interrupt for event DEVMISS + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RSSIEND + Write '1' to enable interrupt for event RSSIEND + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + BCMATCH + Write '1' to enable interrupt for event BCMATCH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CRCOK + Write '1' to enable interrupt for event CRCOK + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CRCERROR + Write '1' to enable interrupt for event CRCERROR + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + FRAMESTART + Write '1' to enable interrupt for event FRAMESTART + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EDEND + Write '1' to enable interrupt for event EDEND + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EDSTOPPED + Write '1' to enable interrupt for event EDSTOPPED + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CCAIDLE + Write '1' to enable interrupt for event CCAIDLE + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CCABUSY + Write '1' to enable interrupt for event CCABUSY + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CCASTOPPED + Write '1' to enable interrupt for event CCASTOPPED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RATEBOOST + Write '1' to enable interrupt for event RATEBOOST + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXREADY + Write '1' to enable interrupt for event TXREADY + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXREADY + Write '1' to enable interrupt for event RXREADY + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + MHRMATCH + Write '1' to enable interrupt for event MHRMATCH + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SYNC + Write '1' to enable interrupt for event SYNC + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PHYEND + Write '1' to enable interrupt for event PHYEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ADDRESS + Write '1' to disable interrupt for event ADDRESS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PAYLOAD + Write '1' to disable interrupt for event PAYLOAD + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DISABLED + Write '1' to disable interrupt for event DISABLED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DEVMATCH + Write '1' to disable interrupt for event DEVMATCH + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DEVMISS + Write '1' to disable interrupt for event DEVMISS + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RSSIEND + Write '1' to disable interrupt for event RSSIEND + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + BCMATCH + Write '1' to disable interrupt for event BCMATCH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CRCOK + Write '1' to disable interrupt for event CRCOK + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CRCERROR + Write '1' to disable interrupt for event CRCERROR + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + FRAMESTART + Write '1' to disable interrupt for event FRAMESTART + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + EDEND + Write '1' to disable interrupt for event EDEND + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + EDSTOPPED + Write '1' to disable interrupt for event EDSTOPPED + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CCAIDLE + Write '1' to disable interrupt for event CCAIDLE + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CCABUSY + Write '1' to disable interrupt for event CCABUSY + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CCASTOPPED + Write '1' to disable interrupt for event CCASTOPPED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RATEBOOST + Write '1' to disable interrupt for event RATEBOOST + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXREADY + Write '1' to disable interrupt for event TXREADY + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXREADY + Write '1' to disable interrupt for event RXREADY + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + MHRMATCH + Write '1' to disable interrupt for event MHRMATCH + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SYNC + Write '1' to disable interrupt for event SYNC + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PHYEND + Write '1' to disable interrupt for event PHYEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + CRCSTATUS + CRC status + 0x400 + read-only + + + CRCSTATUS + CRC status of packet received + 0 + 0 + + + CRCError + Packet received with CRC error + 0 + + + CRCOk + Packet received with CRC ok + 1 + + + + + + + RXMATCH + Received address + 0x408 + read-only + + + RXMATCH + Received address + 0 + 2 + + + + + RXCRC + CRC field of previously received packet + 0x40C + read-only + + + RXCRC + CRC field of previously received packet + 0 + 23 + + + + + DAI + Device address match index + 0x410 + read-only + + + DAI + Device address match index + 0 + 2 + + + + + PDUSTAT + Payload status + 0x414 + read-only + + + PDUSTAT + Status on payload length vs. PCNF1.MAXLEN + 0 + 0 + + + LessThan + Payload less than PCNF1.MAXLEN + 0 + + + GreaterThan + Payload greater than PCNF1.MAXLEN + 1 + + + + + CISTAT + Status on what rate packet is received with in Long Range + 1 + 2 + + + LR125kbit + Frame is received at 125kbps + 0 + + + LR500kbit + Frame is received at 500kbps + 1 + + + + + + + PACKETPTR + Packet pointer + 0x504 + read-write + + + PACKETPTR + Packet pointer + 0 + 31 + + + + + FREQUENCY + Frequency + 0x508 + read-write + 0x00000002 + + + FREQUENCY + Radio channel frequency + 0 + 6 + + + MAP + Channel map selection. + 8 + 8 + + + Default + Channel map between 2400 MHZ .. 2500 MHz + 0 + + + Low + Channel map between 2360 MHZ .. 2460 MHz + 1 + + + + + + + TXPOWER + Output power + 0x50C + read-write + + + TXPOWER + RADIO output power + 0 + 7 + + + Pos8dBm + +8 dBm + 0x8 + + + Pos7dBm + +7 dBm + 0x7 + + + Pos6dBm + +6 dBm + 0x6 + + + Pos5dBm + +5 dBm + 0x5 + + + Pos4dBm + +4 dBm + 0x4 + + + Pos3dBm + +3 dBm + 0x3 + + + Pos2dBm + +2 dBm + 0x2 + + + 0dBm + 0 dBm + 0x0 + + + Neg4dBm + -4 dBm + 0xFC + + + Neg8dBm + -8 dBm + 0xF8 + + + Neg12dBm + -12 dBm + 0xF4 + + + Neg16dBm + -16 dBm + 0xF0 + + + Neg20dBm + -20 dBm + 0xEC + + + Neg30dBm + Deprecated enumerator - -40 dBm + 0xE2 + + + Neg40dBm + -40 dBm + 0xD8 + + + + + + + MODE + Data rate and modulation + 0x510 + read-write + + + MODE + Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. + 0 + 3 + + + Nrf_1Mbit + 1 Mbit/s Nordic proprietary radio mode + 0 + + + Nrf_2Mbit + 2 Mbit/s Nordic proprietary radio mode + 1 + + + Ble_1Mbit + 1 Mbit/s BLE + 3 + + + Ble_2Mbit + 2 Mbit/s BLE + 4 + + + Ble_LR125Kbit + Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX + 5 + + + Ble_LR500Kbit + Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX + 6 + + + Ieee802154_250Kbit + IEEE 802.15.4-2006 250 kbit/s + 15 + + + + + + + PCNF0 + Packet configuration register 0 + 0x514 + read-write + + + LFLEN + Length on air of LENGTH field in number of bits. + 0 + 3 + + + S0LEN + Length on air of S0 field in number of bytes. + 8 + 8 + + + S1LEN + Length on air of S1 field in number of bits. + 16 + 19 + + + S1INCL + Include or exclude S1 field in RAM + 20 + 20 + + + Automatic + Include S1 field in RAM only if S1LEN &gt; 0 + 0 + + + Include + Always include S1 field in RAM independent of S1LEN + 1 + + + + + CILEN + Length of code indicator - long range + 22 + 23 + + + PLEN + Length of preamble on air. Decision point: TASKS_START task + 24 + 25 + + + 8bit + 8-bit preamble + 0 + + + 16bit + 16-bit preamble + 1 + + + 32bitZero + 32-bit zero preamble - used for IEEE 802.15.4 + 2 + + + LongRange + Preamble - used for BLE long range + 3 + + + + + CRCINC + Indicates if LENGTH field contains CRC or not + 26 + 26 + + + Exclude + LENGTH does not contain CRC + 0 + + + Include + LENGTH includes CRC + 1 + + + + + TERMLEN + Length of TERM field in Long Range operation + 29 + 30 + + + + + PCNF1 + Packet configuration register 1 + 0x518 + read-write + + + MAXLEN + Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. + 0 + 7 + + + STATLEN + Static length in number of bytes + 8 + 15 + + + BALEN + Base address length in number of bytes + 16 + 18 + + + ENDIAN + On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. + 24 + 24 + + + Little + Least significant bit on air first + 0 + + + Big + Most significant bit on air first + 1 + + + + + WHITEEN + Enable or disable packet whitening + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + BASE0 + Base address 0 + 0x51C + read-write + + + BASE0 + Base address 0 + 0 + 31 + + + + + BASE1 + Base address 1 + 0x520 + read-write + + + BASE1 + Base address 1 + 0 + 31 + + + + + PREFIX0 + Prefixes bytes for logical addresses 0-3 + 0x524 + read-write + + + AP0 + Address prefix 0. + 0 + 7 + + + AP1 + Address prefix 1. + 8 + 15 + + + AP2 + Address prefix 2. + 16 + 23 + + + AP3 + Address prefix 3. + 24 + 31 + + + + + PREFIX1 + Prefixes bytes for logical addresses 4-7 + 0x528 + read-write + + + AP4 + Address prefix 4. + 0 + 7 + + + AP5 + Address prefix 5. + 8 + 15 + + + AP6 + Address prefix 6. + 16 + 23 + + + AP7 + Address prefix 7. + 24 + 31 + + + + + TXADDRESS + Transmit address select + 0x52C + read-write + + + TXADDRESS + Transmit address select + 0 + 2 + + + + + RXADDRESSES + Receive address select + 0x530 + read-write + + + ADDR0 + Enable or disable reception on logical address 0. + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR1 + Enable or disable reception on logical address 1. + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR2 + Enable or disable reception on logical address 2. + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR3 + Enable or disable reception on logical address 3. + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR4 + Enable or disable reception on logical address 4. + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR5 + Enable or disable reception on logical address 5. + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR6 + Enable or disable reception on logical address 6. + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR7 + Enable or disable reception on logical address 7. + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + CRCCNF + CRC configuration + 0x534 + read-write + + + LEN + CRC length in number of bytes. + 0 + 1 + + + Disabled + CRC length is zero and CRC calculation is disabled + 0 + + + One + CRC length is one byte and CRC calculation is enabled + 1 + + + Two + CRC length is two bytes and CRC calculation is enabled + 2 + + + Three + CRC length is three bytes and CRC calculation is enabled + 3 + + + + + SKIPADDR + Include or exclude packet address field out of CRC calculation. + 8 + 9 + + + Include + CRC calculation includes address field + 0 + + + Skip + CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. + 1 + + + Ieee802154 + CRC calculation as per 802.15.4 standard. Starting at first byte after length field. + 2 + + + + + + + CRCPOLY + CRC polynomial + 0x538 + read-write + 0x00000000 + + + CRCPOLY + CRC polynomial + 0 + 23 + + + + + CRCINIT + CRC initial value + 0x53C + read-write + + + CRCINIT + CRC initial value + 0 + 23 + + + + + TIFS + Interframe spacing in us + 0x544 + read-write + + + TIFS + Interframe spacing in us + 0 + 9 + + + + + RSSISAMPLE + RSSI sample + 0x548 + read-only + + + RSSISAMPLE + RSSI sample + 0 + 6 + + + + + STATE + Current radio state + 0x550 + read-only + + + STATE + Current radio state + 0 + 3 + + + Disabled + RADIO is in the Disabled state + 0 + + + RxRu + RADIO is in the RXRU state + 1 + + + RxIdle + RADIO is in the RXIDLE state + 2 + + + Rx + RADIO is in the RX state + 3 + + + RxDisable + RADIO is in the RXDISABLED state + 4 + + + TxRu + RADIO is in the TXRU state + 9 + + + TxIdle + RADIO is in the TXIDLE state + 10 + + + Tx + RADIO is in the TX state + 11 + + + TxDisable + RADIO is in the TXDISABLED state + 12 + + + + + + + DATAWHITEIV + Data whitening initial value + 0x554 + read-write + 0x00000040 + + + DATAWHITEIV + Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. + 0 + 6 + + + + + BCC + Bit counter compare + 0x560 + read-write + + + BCC + Bit counter compare + 0 + 31 + + + + + 0x8 + 0x4 + DAB[%s] + Description collection: Device address base segment n + 0x600 + read-write + + + DAB + Device address base segment n + 0 + 31 + + + + + 0x8 + 0x4 + DAP[%s] + Description collection: Device address prefix n + 0x620 + read-write + + + DAP + Device address prefix n + 0 + 15 + + + + + DACNF + Device address match configuration + 0x640 + read-write + + + ENA0 + Enable or disable device address matching using device address 0 + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA1 + Enable or disable device address matching using device address 1 + 1 + 1 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA2 + Enable or disable device address matching using device address 2 + 2 + 2 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA3 + Enable or disable device address matching using device address 3 + 3 + 3 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA4 + Enable or disable device address matching using device address 4 + 4 + 4 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA5 + Enable or disable device address matching using device address 5 + 5 + 5 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA6 + Enable or disable device address matching using device address 6 + 6 + 6 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA7 + Enable or disable device address matching using device address 7 + 7 + 7 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + TXADD0 + TxAdd for device address 0 + 8 + 8 + + + TXADD1 + TxAdd for device address 1 + 9 + 9 + + + TXADD2 + TxAdd for device address 2 + 10 + 10 + + + TXADD3 + TxAdd for device address 3 + 11 + 11 + + + TXADD4 + TxAdd for device address 4 + 12 + 12 + + + TXADD5 + TxAdd for device address 5 + 13 + 13 + + + TXADD6 + TxAdd for device address 6 + 14 + 14 + + + TXADD7 + TxAdd for device address 7 + 15 + 15 + + + + + MHRMATCHCONF + Search pattern configuration + 0x644 + read-write + + + MHRMATCHCONF + Search pattern configuration + 0 + 31 + + + + + MHRMATCHMAS + Pattern mask + 0x648 + read-write + + + MHRMATCHMAS + Pattern mask + 0 + 31 + + + + + MODECNF0 + Radio mode configuration register 0 + 0x650 + read-write + 0x00000200 + + + RU + Radio ramp-up time + 0 + 0 + + + Default + Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 + 0 + + + Fast + Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information + 1 + + + + + DTX + Default TX value + 8 + 9 + + + B1 + Transmit '1' + 0 + + + B0 + Transmit '0' + 1 + + + Center + Transmit center frequency + 2 + + + + + + + SFD + IEEE 802.15.4 start of frame delimiter + 0x660 + read-write + 0x000000A7 + + + SFD + IEEE 802.15.4 start of frame delimiter + 0 + 7 + + + + + EDCNT + IEEE 802.15.4 energy detect loop count + 0x664 + read-write + 0x00000000 + + + EDCNT + IEEE 802.15.4 energy detect loop count + 0 + 20 + + + + + EDSAMPLE + IEEE 802.15.4 energy detect level + 0x668 + read-write + 0x00000000 + + + EDLVL + IEEE 802.15.4 energy detect level + 0 + 7 + + + + + CCACTRL + IEEE 802.15.4 clear channel assessment control + 0x66C + read-write + 0x052D0000 + + + CCAMODE + CCA mode of operation + 0 + 2 + + + EdMode + Energy above threshold + 0 + + + CarrierMode + Carrier seen + 1 + + + CarrierAndEdMode + Energy above threshold AND carrier seen + 2 + + + CarrierOrEdMode + Energy above threshold OR carrier seen + 3 + + + EdModeTest1 + Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. + 4 + + + + + CCAEDTHRES + CCA energy busy threshold. Used in all the CCA modes except CarrierMode. + 8 + 15 + + + CCACORRTHRES + CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode. + 16 + 23 + + + CCACORRCNT + Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. + 24 + 31 + + + + + POWER + Peripheral power control + 0xFFC + read-write + 0x00000001 + + + POWER + Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. + 0 + 0 + + + Disabled + Peripheral is powered off + 0 + + + Enabled + Peripheral is powered on + 1 + + + + + + + + + UART0 + Universal Asynchronous Receiver/Transmitter + 0x40002000 + UART + + 0 + 0x1000 + registers + + + UARTE0_UART0 + 2 + + UART + 0x20 + + + TASKS_STARTRX + Start UART receiver + 0x000 + write-only + + + TASKS_STARTRX + Start UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPRX + Stop UART receiver + 0x004 + write-only + + + TASKS_STOPRX + Stop UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start UART transmitter + 0x008 + write-only + + + TASKS_STARTTX + Start UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPTX + Stop UART transmitter + 0x00C + write-only + + + TASKS_STOPTX + Stop UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend UART + 0x01C + write-only + + + TASKS_SUSPEND + Suspend UART + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXDRDY + Data received in RXD + 0x108 + read-write + + + EVENTS_RXDRDY + Data received in RXD + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x11C + read-write + + + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + Error detected + 0x124 + read-write + + + EVENTS_ERROR + Error detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXTO + Receiver timeout + 0x144 + read-write + + + EVENTS_RXTO + Receiver timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + CTS_STARTRX + Shortcut between event CTS and task STARTRX + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + NCTS_STOPRX + Shortcut between event NCTS and task STOPRX + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + CTS + Write '1' to enable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NCTS + Write '1' to enable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDRDY + Write '1' to enable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXTO + Write '1' to enable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXTO + Write '1' to disable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x480 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + + + ENABLE + Enable or disable UART + 0 + 3 + + + Disabled + Disable UART + 0 + + + Enabled + Enable UART + 4 + + + + + + + PSEL + Unspecified + UART_PSEL + read-write + 0x508 + + RTS + Pin select for RTS + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TXD + Pin select for TXD + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CTS + Pin select for CTS + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + RXD + Pin select for RXD + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD register + 0x518 + read-only + modifyExternal + + + RXD + RX data received in previous transfers, double buffered + 0 + 7 + + + + + TXD + TXD register + 0x51C + write-only + + + TXD + TX data to be transferred + 0 + 7 + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14414) + 0x003B0000 + + + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28829) + 0x0075F000 + + + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38462) + 0x009D5000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57762) + 0x00EBF000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115942) + 0x01D7E000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03AFB000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 470588) + 0x075F7000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0EBED000 + + + Baud1M + 1Mega baud + 0x10000000 + + + + + + + CONFIG + Configuration of parity and hardware flow control + 0x56C + read-write + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include parity bit + 0x7 + + + + + STOP + Stop bits + 4 + 4 + + + One + One stop bit + 0 + + + Two + Two stop bits + 1 + + + + + + + + + UARTE0 + UART with EasyDMA 0 + 0x40002000 + UART0 + UARTE + + 0 + 0x1000 + registers + + + UARTE0_UART0 + 2 + + UARTE + 0x20 + + + TASKS_STARTRX + Start UART receiver + 0x000 + write-only + + + TASKS_STARTRX + Start UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPRX + Stop UART receiver + 0x004 + write-only + + + TASKS_STOPRX + Stop UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start UART transmitter + 0x008 + write-only + + + TASKS_STARTTX + Start UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPTX + Stop UART transmitter + 0x00C + write-only + + + TASKS_STOPTX + Stop UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0x02C + write-only + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0x108 + read-write + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + Receive buffer is filled up + 0x110 + read-write + + + EVENTS_ENDRX + Receive buffer is filled up + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x11C + read-write + + + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + Last TX byte transmitted + 0x120 + read-write + + + EVENTS_ENDTX + Last TX byte transmitted + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + Error detected + 0x124 + read-write + + + EVENTS_ERROR + Error detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXTO + Receiver timeout + 0x144 + read-write + + + EVENTS_RXTO + Receiver timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + UART receiver has started + 0x14C + read-write + + + EVENTS_RXSTARTED + UART receiver has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + UART transmitter has started + 0x150 + read-write + + + EVENTS_TXSTARTED + UART transmitter has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTOPPED + Transmitter stopped + 0x158 + read-write + + + EVENTS_TXSTOPPED + Transmitter stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + ENDRX_STARTRX + Shortcut between event ENDRX and task STARTRX + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ENDRX_STOPRX + Shortcut between event ENDRX and task STOPRX + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + CTS + Enable or disable interrupt for event CTS + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + NCTS + Enable or disable interrupt for event NCTS + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXDRDY + Enable or disable interrupt for event RXDRDY + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDRX + Enable or disable interrupt for event ENDRX + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXDRDY + Enable or disable interrupt for event TXDRDY + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDTX + Enable or disable interrupt for event ENDTX + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXTO + Enable or disable interrupt for event RXTO + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTOPPED + Enable or disable interrupt for event TXSTOPPED + 22 + 22 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + CTS + Write '1' to enable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NCTS + Write '1' to enable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDRDY + Write '1' to enable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXTO + Write '1' to enable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTOPPED + Write '1' to enable interrupt for event TXSTOPPED + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXTO + Write '1' to disable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTOPPED + Write '1' to disable interrupt for event TXSTOPPED + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source This register is read/write one to clear. + 0x480 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + + + ENABLE + Enable or disable UARTE + 0 + 3 + + + Disabled + Disable UARTE + 0 + + + Enabled + Enable UARTE + 8 + + + + + + + PSEL + Unspecified + UARTE_PSEL + read-write + 0x508 + + RTS + Pin select for RTS signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TXD + Pin select for TXD signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CTS + Pin select for CTS signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + RXD + Pin select for RXD signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14401) + 0x003AF000 + + + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28777) + 0x0075C000 + + + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38369) + 0x009D0000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57554) + 0x00EB0000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115108) + 0x01D60000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03B00000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 457143) + 0x07400000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0F000000 + + + Baud1M + 1 megabaud + 0x10000000 + + + + + + + RXD + RXD EasyDMA channel + UARTE_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + + TXD + TXD EasyDMA channel + UARTE_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + + CONFIG + Configuration of parity and hardware flow control + 0x56C + read-write + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include even parity bit + 0x7 + + + + + STOP + Stop bits + 4 + 4 + + + One + One stop bit + 0 + + + Two + Two stop bits + 1 + + + + + + + + + SPI0 + Serial Peripheral Interface 0 + 0x40003000 + SPI + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + SPI + 0x20 + + + EVENTS_READY + TXD byte sent and RXD byte received + 0x108 + read-write + + + EVENTS_READY + TXD byte sent and RXD byte received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable SPI + 0x500 + read-write + + + ENABLE + Enable or disable SPI + 0 + 3 + + + Disabled + Disable SPI + 0 + + + Enabled + Enable SPI + 1 + + + + + + + PSEL + Unspecified + SPI_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD register + 0x518 + read-only + modifyExternal + + + RXD + RX data received. Double buffered + 0 + 7 + + + + + TXD + TXD register + 0x51C + read-write + + + TXD + TX data to send. Double buffered. + 0 + 7 + + + + + FREQUENCY + SPI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + SPI master data rate + 0 + 31 + + + K125 + 125 kbps + 0x02000000 + + + K250 + 250 kbps + 0x04000000 + + + K500 + 500 kbps + 0x08000000 + + + M1 + 1 Mbps + 0x10000000 + + + M2 + 2 Mbps + 0x20000000 + + + M4 + 4 Mbps + 0x40000000 + + + M8 + 8 Mbps + 0x80000000 + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + + + SPIM0 + Serial Peripheral Interface Master with EasyDMA 0 + 0x40003000 + SPI0 + SPIM + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + SPIM + 0x20 + + + TASKS_START + Start SPI transaction + 0x010 + write-only + + + TASKS_START + Start SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop SPI transaction + 0x014 + write-only + + + TASKS_STOP + Stop SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend SPI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume SPI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + SPI transaction has stopped + 0x104 + read-write + + + EVENTS_STOPPED + SPI transaction has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + + + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0x118 + read-write + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + End of TXD buffer reached + 0x120 + read-write + + + EVENTS_ENDTX + End of TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STARTED + Transaction started + 0x14C + read-write + + + EVENTS_STARTED + Transaction started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + END_START + Shortcut between event END and task START + 17 + 17 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + STALLSTAT + Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurs and can be cleared (set to NOSTALL) by the CPU. + 0x400 + read-write + 0x00000000 + + + TX + Stall status for EasyDMA RAM reads + 0 + 0 + + + NOSTALL + No stall + 0 + + + STALL + A stall has occurred + 1 + + + + + RX + Stall status for EasyDMA RAM writes + 1 + 1 + + + NOSTALL + No stall + 0 + + + STALL + A stall has occurred + 1 + + + + + + + ENABLE + Enable SPIM + 0x500 + read-write + + + ENABLE + Enable or disable SPIM + 0 + 3 + + + Disabled + Disable SPIM + 0 + + + Enabled + Enable SPIM + 7 + + + + + + + PSEL + Unspecified + SPIM_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CSN + Pin select for CSN + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + FREQUENCY + SPI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + SPI master data rate + 0 + 31 + + + K125 + 125 kbps + 0x02000000 + + + K250 + 250 kbps + 0x04000000 + + + K500 + 500 kbps + 0x08000000 + + + M1 + 1 Mbps + 0x10000000 + + + M2 + 2 Mbps + 0x20000000 + + + M4 + 4 Mbps + 0x40000000 + + + M8 + 8 Mbps + 0x80000000 + + + M16 + 16 Mbps + 0x0A000000 + + + M32 + 32 Mbps + 0x14000000 + + + + + + + RXD + RXD EasyDMA channel + SPIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + SPIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + IFTIMING + Unspecified + SPIM_IFTIMING + read-write + 0x560 + + RXDELAY + Sample delay for input serial data on MISO + 0x000 + read-write + 0x00000002 + + + RXDELAY + Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. + 0 + 2 + + + + + CSNDUR + Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions + 0x004 + read-write + 0x00000002 + + + CSNDUR + Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). + 0 + 7 + + + + + + CSNPOL + Polarity of CSN output + 0x568 + read-write + 0x00000000 + + + CSNPOL + Polarity of CSN output + 0 + 0 + + + LOW + Active low (idle state high) + 0 + + + HIGH + Active high (idle state low) + 1 + + + + + + + PSELDCX + Pin select for DCX signal + 0x56C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + DCXCNT + DCX configuration + 0x570 + read-write + + + DCXCNT + This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. + 0 + 3 + + + + + ORC + Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT + 0x5C0 + read-write + + + ORC + Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. + 0 + 7 + + + + + + + SPIS0 + SPI Slave 0 + 0x40003000 + SPI0 + SPIS + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + SPIS + 0x20 + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0x024 + write-only + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0x028 + write-only + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_END + Granted transaction completed + 0x104 + read-write + + + EVENTS_END + Granted transaction completed + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + + + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ACQUIRED + Semaphore acquired + 0x128 + read-write + + + EVENTS_ACQUIRED + Semaphore acquired + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + END_ACQUIRE + Shortcut between event END and task ACQUIRE + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ACQUIRED + Write '1' to enable interrupt for event ACQUIRED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ACQUIRED + Write '1' to disable interrupt for event ACQUIRED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + SEMSTAT + Semaphore status register + 0x400 + read-only + 0x00000001 + + + SEMSTAT + Semaphore status + 0 + 1 + + + Free + Semaphore is free + 0 + + + CPU + Semaphore is assigned to CPU + 1 + + + SPIS + Semaphore is assigned to SPI slave + 2 + + + CPUPending + Semaphore is assigned to SPI but a handover to the CPU is pending + 3 + + + + + + + STATUS + Status from last transaction + 0x440 + read-write + + + OVERREAD + TX buffer over-read detected, and prevented + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + OVERFLOW + RX buffer overflow detected, and prevented + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + + + ENABLE + Enable SPI slave + 0x500 + read-write + + + ENABLE + Enable or disable SPI slave + 0 + 3 + + + Disabled + Disable SPI slave + 0 + + + Enabled + Enable SPI slave + 2 + + + + + + + PSEL + Unspecified + SPIS_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CSN + Pin select for CSN signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + Unspecified + SPIS_RXD + read-write + 0x534 + + PTR + RXD data pointer + 0x000 + read-write + + + PTR + RXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes received in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes received in the last granted transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + Unspecified + SPIS_TXD + read-write + 0x544 + + PTR + TXD data pointer + 0x000 + read-write + + + PTR + TXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0x55C + read-write + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0 + 7 + + + + + ORC + Over-read character + 0x5C0 + read-write + + + ORC + Over-read character. Character clocked out after an over-read of the transmit buffer. + 0 + 7 + + + + + + + TWI0 + I2C compatible Two-Wire Interface 0 + 0x40003000 + SPI0 + TWI + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + TWI + 0x20 + + + TASKS_STARTRX + Start TWI receive sequence + 0x000 + write-only + + + TASKS_STARTRX + Start TWI receive sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start TWI transmit sequence + 0x008 + write-only + + + TASKS_STARTTX + Start TWI transmit sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop TWI transaction + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXDREADY + TWI RXD byte received + 0x108 + read-write + + + EVENTS_RXDREADY + TWI RXD byte received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXDSENT + TWI TXD byte sent + 0x11C + read-write + + + EVENTS_TXDSENT + TWI TXD byte sent + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_BB + TWI byte boundary, generated before each byte that is sent or received + 0x138 + read-write + + + EVENTS_BB + TWI byte boundary, generated before each byte that is sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SUSPENDED + TWI entered the suspended state + 0x148 + read-write + + + EVENTS_SUSPENDED + TWI entered the suspended state + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + BB_SUSPEND + Shortcut between event BB and task SUSPEND + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + BB_STOP + Shortcut between event BB and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDREADY + Write '1' to enable interrupt for event RXDREADY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDSENT + Write '1' to enable interrupt for event TXDSENT + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + BB + Write '1' to enable interrupt for event BB + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDREADY + Write '1' to disable interrupt for event RXDREADY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDSENT + Write '1' to disable interrupt for event TXDSENT + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + BB + Write '1' to disable interrupt for event BB + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4C4 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: no overrun occured + 0 + + + Present + Read: overrun occured + 1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable TWI + 0x500 + read-write + + + ENABLE + Enable or disable TWI + 0 + 3 + + + Disabled + Disable TWI + 0 + + + Enabled + Enable TWI + 5 + + + + + + + PSEL + Unspecified + TWI_PSEL + read-write + 0x508 + + SCL + Pin select for SCL + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD register + 0x518 + read-only + modifyExternal + + + RXD + RXD register + 0 + 7 + + + + + TXD + TXD register + 0x51C + read-write + + + TXD + TXD register + 0 + 7 + + + + + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps (actual rate 410.256 kbps) + 0x06680000 + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + + + TWIM0 + I2C compatible Two-Wire Master Interface with EasyDMA 0 + 0x40003000 + SPI0 + TWIM + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + TWIM + 0x20 + + + TASKS_STARTRX + Start TWI receive sequence + 0x000 + write-only + + + TASKS_STARTRX + Start TWI receive sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start TWI transmit sequence + 0x008 + write-only + + + TASKS_STARTTX + Start TWI transmit sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0x148 + read-write + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + + + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0x15C + read-write + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0x160 + read-write + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + LASTTX_STARTRX + Shortcut between event LASTTX and task STARTRX + 7 + 7 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTTX_SUSPEND + Shortcut between event LASTTX and task SUSPEND + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTTX_STOP + Shortcut between event LASTTX and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STARTTX + Shortcut between event LASTRX and task STARTTX + 10 + 10 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_SUSPEND + Shortcut between event LASTRX and task SUSPEND + 11 + 11 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STOP + Shortcut between event LASTRX and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SUSPENDED + Enable or disable interrupt for event SUSPENDED + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTRX + Enable or disable interrupt for event LASTRX + 23 + 23 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTTX + Enable or disable interrupt for event LASTTX + 24 + 24 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LASTRX + Write '1' to enable interrupt for event LASTRX + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LASTTX + Write '1' to enable interrupt for event LASTTX + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LASTRX + Write '1' to disable interrupt for event LASTRX + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LASTTX + Write '1' to disable interrupt for event LASTTX + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4C4 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + + + ENABLE + Enable TWIM + 0x500 + read-write + + + ENABLE + Enable or disable TWIM + 0 + 3 + + + Disabled + Disable TWIM + 0 + + + Enabled + Enable TWIM + 6 + + + + + + + PSEL + Unspecified + TWIM_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps + 0x06400000 + + + + + + + RXD + RXD EasyDMA channel + TWIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + TWIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + + + TWIS0 + I2C compatible Two-Wire Slave Interface with EasyDMA 0 + 0x40003000 + SPI0 + TWIS + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + TWIS + 0x20 + + + TASKS_STOP + Stop TWI transaction + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0x030 + write-only + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0x034 + write-only + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + + + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_WRITE + Write command received + 0x164 + read-write + + + EVENTS_WRITE + Write command received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_READ + Read command received + 0x168 + read-write + + + EVENTS_READ + Read command received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + WRITE_SUSPEND + Shortcut between event WRITE and task SUSPEND + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READ_SUSPEND + Shortcut between event READ and task SUSPEND + 14 + 14 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + WRITE + Enable or disable interrupt for event WRITE + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + READ + Enable or disable interrupt for event READ + 26 + 26 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + WRITE + Write '1' to enable interrupt for event WRITE + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + READ + Write '1' to enable interrupt for event READ + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + WRITE + Write '1' to disable interrupt for event WRITE + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + READ + Write '1' to disable interrupt for event READ + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4D0 + read-write + oneToClear + + + OVERFLOW + RX buffer overflow detected, and prevented + 0 + 0 + + + NotDetected + Error did not occur + 0 + + + Detected + Error occurred + 1 + + + + + DNACK + NACK sent after receiving a data byte + 2 + 2 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + OVERREAD + TX buffer over-read detected, and prevented + 3 + 3 + + + NotDetected + Error did not occur + 0 + + + Detected + Error occurred + 1 + + + + + + + MATCH + Status register indicating which address had a match + 0x4D4 + read-only + + + MATCH + Indication of which address in {ADDRESS} that matched the incoming address + 0 + 0 + + + + + ENABLE + Enable TWIS + 0x500 + read-write + + + ENABLE + Enable or disable TWIS + 0 + 3 + + + Disabled + Disable TWIS + 0 + + + Enabled + Enable TWIS + 9 + + + + + + + PSEL + Unspecified + TWIS_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD EasyDMA channel + TWIS_RXD + read-write + 0x534 + + PTR + RXD Data pointer + 0x000 + read-write + + + PTR + RXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in RXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in RXD buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + TWIS_TXD + read-write + 0x544 + + PTR + TXD Data pointer + 0x000 + read-write + + + PTR + TXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in TXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in TXD buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + 0x2 + 0x4 + ADDRESS[%s] + Description collection: TWI slave address n + 0x588 + read-write + + + ADDRESS + TWI slave address + 0 + 6 + + + + + CONFIG + Configuration register for the address match mechanism + 0x594 + read-write + 0x00000001 + + + ADDRESS0 + Enable or disable address matching on ADDRESS[0] + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ADDRESS1 + Enable or disable address matching on ADDRESS[1] + 1 + 1 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0x5C0 + read-write + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0 + 7 + + + + + + + SPI1 + Serial Peripheral Interface 1 + 0x40004000 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + SPIM1 + Serial Peripheral Interface Master with EasyDMA 1 + 0x40004000 + SPI1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + SPIS1 + SPI Slave 1 + 0x40004000 + SPI1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + TWI1 + I2C compatible Two-Wire Interface 1 + 0x40004000 + SPI1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + TWIM1 + I2C compatible Two-Wire Master Interface with EasyDMA 1 + 0x40004000 + SPI1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + TWIS1 + I2C compatible Two-Wire Slave Interface with EasyDMA 1 + 0x40004000 + SPI1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + NFCT + NFC-A compatible radio + 0x40005000 + + 0 + 0x1000 + registers + + + NFCT + 5 + + NFCT + 0x20 + + + TASKS_ACTIVATE + Activate NFCT peripheral for incoming and outgoing frames, change state to activated + 0x000 + write-only + + + TASKS_ACTIVATE + Activate NFCT peripheral for incoming and outgoing frames, change state to activated + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_DISABLE + Disable NFCT peripheral + 0x004 + write-only + + + TASKS_DISABLE + Disable NFCT peripheral + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SENSE + Enable NFC sense field mode, change state to sense mode + 0x008 + write-only + + + TASKS_SENSE + Enable NFC sense field mode, change state to sense mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start transmission of an outgoing frame, change state to transmit + 0x00C + write-only + + + TASKS_STARTTX + Start transmission of an outgoing frame, change state to transmit + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_ENABLERXDATA + Initializes the EasyDMA for receive. + 0x01C + write-only + + + TASKS_ENABLERXDATA + Initializes the EasyDMA for receive. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_GOIDLE + Force state machine to IDLE state + 0x024 + write-only + + + TASKS_GOIDLE + Force state machine to IDLE state + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_GOSLEEP + Force state machine to SLEEP_A state + 0x028 + write-only + + + TASKS_GOSLEEP + Force state machine to SLEEP_A state + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_READY + The NFCT peripheral is ready to receive and send frames + 0x100 + read-write + + + EVENTS_READY + The NFCT peripheral is ready to receive and send frames + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_FIELDDETECTED + Remote NFC field detected + 0x104 + read-write + + + EVENTS_FIELDDETECTED + Remote NFC field detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_FIELDLOST + Remote NFC field lost + 0x108 + read-write + + + EVENTS_FIELDLOST + Remote NFC field lost + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXFRAMESTART + Marks the start of the first symbol of a transmitted frame + 0x10C + read-write + + + EVENTS_TXFRAMESTART + Marks the start of the first symbol of a transmitted frame + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXFRAMEEND + Marks the end of the last transmitted on-air symbol of a frame + 0x110 + read-write + + + EVENTS_TXFRAMEEND + Marks the end of the last transmitted on-air symbol of a frame + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXFRAMESTART + Marks the end of the first symbol of a received frame + 0x114 + read-write + + + EVENTS_RXFRAMESTART + Marks the end of the first symbol of a received frame + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXFRAMEEND + Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer + 0x118 + read-write + + + EVENTS_RXFRAMEEND + Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + NFC error reported. The ERRORSTATUS register contains details on the source of the error. + 0x11C + read-write + + + EVENTS_ERROR + NFC error reported. The ERRORSTATUS register contains details on the source of the error. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXERROR + NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. + 0x128 + read-write + + + EVENTS_RXERROR + NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. + 0x12C + read-write + + + EVENTS_ENDRX + RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer + 0x130 + read-write + + + EVENTS_ENDTX + Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_AUTOCOLRESSTARTED + Auto collision resolution process has started + 0x138 + read-write + + + EVENTS_AUTOCOLRESSTARTED + Auto collision resolution process has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_COLLISION + NFC auto collision resolution error reported. + 0x148 + read-write + + + EVENTS_COLLISION + NFC auto collision resolution error reported. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SELECTED + NFC auto collision resolution successfully completed + 0x14C + read-write + + + EVENTS_SELECTED + NFC auto collision resolution successfully completed + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STARTED + EasyDMA is ready to receive or send frames. + 0x150 + read-write + + + EVENTS_STARTED + EasyDMA is ready to receive or send frames. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + FIELDDETECTED_ACTIVATE + Shortcut between event FIELDDETECTED and task ACTIVATE + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + FIELDLOST_SENSE + Shortcut between event FIELDLOST and task SENSE + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + TXFRAMEEND_ENABLERXDATA + Shortcut between event TXFRAMEEND and task ENABLERXDATA + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + FIELDDETECTED + Enable or disable interrupt for event FIELDDETECTED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + FIELDLOST + Enable or disable interrupt for event FIELDLOST + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXFRAMESTART + Enable or disable interrupt for event TXFRAMESTART + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXFRAMEEND + Enable or disable interrupt for event TXFRAMEEND + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXFRAMESTART + Enable or disable interrupt for event RXFRAMESTART + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXFRAMEEND + Enable or disable interrupt for event RXFRAMEEND + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXERROR + Enable or disable interrupt for event RXERROR + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDRX + Enable or disable interrupt for event ENDRX + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDTX + Enable or disable interrupt for event ENDTX + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + AUTOCOLRESSTARTED + Enable or disable interrupt for event AUTOCOLRESSTARTED + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COLLISION + Enable or disable interrupt for event COLLISION + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SELECTED + Enable or disable interrupt for event SELECTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STARTED + Enable or disable interrupt for event STARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + FIELDDETECTED + Write '1' to enable interrupt for event FIELDDETECTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + FIELDLOST + Write '1' to enable interrupt for event FIELDLOST + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXFRAMESTART + Write '1' to enable interrupt for event TXFRAMESTART + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXFRAMEEND + Write '1' to enable interrupt for event TXFRAMEEND + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXFRAMESTART + Write '1' to enable interrupt for event RXFRAMESTART + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXFRAMEEND + Write '1' to enable interrupt for event RXFRAMEEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXERROR + Write '1' to enable interrupt for event RXERROR + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + AUTOCOLRESSTARTED + Write '1' to enable interrupt for event AUTOCOLRESSTARTED + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COLLISION + Write '1' to enable interrupt for event COLLISION + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SELECTED + Write '1' to enable interrupt for event SELECTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + FIELDDETECTED + Write '1' to disable interrupt for event FIELDDETECTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + FIELDLOST + Write '1' to disable interrupt for event FIELDLOST + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXFRAMESTART + Write '1' to disable interrupt for event TXFRAMESTART + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXFRAMEEND + Write '1' to disable interrupt for event TXFRAMEEND + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXFRAMESTART + Write '1' to disable interrupt for event RXFRAMESTART + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXFRAMEEND + Write '1' to disable interrupt for event RXFRAMEEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXERROR + Write '1' to disable interrupt for event RXERROR + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + AUTOCOLRESSTARTED + Write '1' to disable interrupt for event AUTOCOLRESSTARTED + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COLLISION + Write '1' to disable interrupt for event COLLISION + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SELECTED + Write '1' to disable interrupt for event SELECTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSTATUS + NFC Error Status register + 0x404 + read-write + oneToClear + + + FRAMEDELAYTIMEOUT + No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX + 0 + 0 + + + + + FRAMESTATUS + Unspecified + NFCT_FRAMESTATUS + read-write + 0x40C + + RX + Result of last incoming frame + 0x000 + read-write + oneToClear + + + CRCERROR + No valid end of frame (EoF) detected + 0 + 0 + + + CRCCorrect + Valid CRC detected + 0 + + + CRCError + CRC received does not match local check + 1 + + + + + PARITYSTATUS + Parity status of received frame + 2 + 2 + + + ParityOK + Frame received with parity OK + 0 + + + ParityError + Frame received with parity error + 1 + + + + + OVERRUN + Overrun detected + 3 + 3 + + + NoOverrun + No overrun detected + 0 + + + Overrun + Overrun error + 1 + + + + + + + + NFCTAGSTATE + NfcTag state register + 0x410 + read-only + + + NFCTAGSTATE + NfcTag state + 0 + 2 + + + Disabled + Disabled or sense + 0 + + + RampUp + RampUp + 2 + + + Idle + Idle + 3 + + + Receive + Receive + 4 + + + FrameDelay + FrameDelay + 5 + + + Transmit + Transmit + 6 + + + + + + + SLEEPSTATE + Sleep state during automatic collision resolution + 0x420 + read-only + 0x00000000 + + + SLEEPSTATE + Reflects the sleep state during automatic collision resolution. Set to IDLE + by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a + GOSLEEP task. + 0 + 0 + + + Idle + State is IDLE. + 0 + + + SleepA + State is SLEEP_A. + 1 + + + + + + + FIELDPRESENT + Indicates the presence or not of a valid field + 0x43C + read-only + + + FIELDPRESENT + Indicates if a valid field is present. Available only in the activated state. + 0 + 0 + + + NoField + No valid field detected + 0 + + + FieldPresent + Valid field detected + 1 + + + + + LOCKDETECT + Indicates if the low level has locked to the field + 1 + 1 + + + NotLocked + Not locked to field + 0 + + + Locked + Locked to field + 1 + + + + + + + FRAMEDELAYMIN + Minimum frame delay + 0x504 + read-write + 0x00000480 + + + FRAMEDELAYMIN + Minimum frame delay in number of 13.56 MHz clocks + 0 + 15 + + + + + FRAMEDELAYMAX + Maximum frame delay + 0x508 + read-write + 0x00001000 + + + FRAMEDELAYMAX + Maximum frame delay in number of 13.56 MHz clocks + 0 + 19 + + + + + FRAMEDELAYMODE + Configuration register for the Frame Delay Timer + 0x50C + read-write + 0x00000001 + + + FRAMEDELAYMODE + Configuration register for the Frame Delay Timer + 0 + 1 + + + FreeRun + Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. + 0 + + + Window + Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX + 1 + + + ExactVal + Frame is transmitted exactly at FRAMEDELAYMAX + 2 + + + WindowGrid + Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX + 3 + + + + + + + PACKETPTR + Packet pointer for TXD and RXD data storage in Data RAM + 0x510 + read-write + 0x00000000 + + + PTR + Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. + 0 + 31 + + + + + MAXLEN + Size of the RAM buffer allocated to TXD and RXD data storage each + 0x514 + read-write + + + MAXLEN + Size of the RAM buffer allocated to TXD and RXD data storage each + 0 + 8 + + + + + TXD + Unspecified + NFCT_TXD + read-write + 0x518 + + FRAMECONFIG + Configuration of outgoing frames + 0x000 + read-write + 0x00000017 + + + PARITY + Indicates if parity is added to the frame + 0 + 0 + + + NoParity + Parity is not added to TX frames + 0 + + + Parity + Parity is added to TX frames + 1 + + + + + DISCARDMODE + Discarding unused bits at start or end of a frame + 1 + 1 + + + DiscardEnd + Unused bits are discarded at end of frame (EoF) + 0 + + + DiscardStart + Unused bits are discarded at start of frame (SoF) + 1 + + + + + SOF + Adding SoF or not in TX frames + 2 + 2 + + + NoSoF + SoF symbol not added + 0 + + + SoF + SoF symbol added + 1 + + + + + CRCMODETX + CRC mode for outgoing frames + 4 + 4 + + + NoCRCTX + CRC is not added to the frame + 0 + + + CRC16TX + 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame + 1 + + + + + + + AMOUNT + Size of outgoing frame + 0x004 + read-write + + + TXDATABITS + Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). + 0 + 2 + + + TXDATABYTES + Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing + 3 + 11 + + + + + + RXD + Unspecified + NFCT_RXD + read-write + 0x520 + + FRAMECONFIG + Configuration of incoming frames + 0x000 + read-write + 0x00000015 + + + PARITY + Indicates if parity expected in RX frame + 0 + 0 + + + NoParity + Parity is not expected in RX frames + 0 + + + Parity + Parity is expected in RX frames + 1 + + + + + SOF + SoF expected or not in RX frames + 2 + 2 + + + NoSoF + SoF symbol is not expected in RX frames + 0 + + + SoF + SoF symbol is expected in RX frames + 1 + + + + + CRCMODERX + CRC mode for incoming frames + 4 + 4 + + + NoCRCRX + CRC is not expected in RX frames + 0 + + + CRC16RX + Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated + 1 + + + + + + + AMOUNT + Size of last incoming frame + 0x004 + read-only + + + RXDATABITS + Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). + 0 + 2 + + + RXDATABYTES + Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) + 3 + 11 + + + + + + NFCID1_LAST + Last NFCID1 part (4, 7 or 10 bytes ID) + 0x590 + read-write + 0x00006363 + + + NFCID1_Z + NFCID1 byte Z (very last byte sent) + 0 + 7 + + + NFCID1_Y + NFCID1 byte Y + 8 + 15 + + + NFCID1_X + NFCID1 byte X + 16 + 23 + + + NFCID1_W + NFCID1 byte W + 24 + 31 + + + + + NFCID1_2ND_LAST + Second last NFCID1 part (7 or 10 bytes ID) + 0x594 + read-write + + + NFCID1_V + NFCID1 byte V + 0 + 7 + + + NFCID1_U + NFCID1 byte U + 8 + 15 + + + NFCID1_T + NFCID1 byte T + 16 + 23 + + + + + NFCID1_3RD_LAST + Third last NFCID1 part (10 bytes ID) + 0x598 + read-write + + + NFCID1_S + NFCID1 byte S + 0 + 7 + + + NFCID1_R + NFCID1 byte R + 8 + 15 + + + NFCID1_Q + NFCID1 byte Q + 16 + 23 + + + + + AUTOCOLRESCONFIG + Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is activated. + 0x59C + read-write + 0x00000002 + + + MODE + Enables/disables auto collision resolution + 0 + 0 + + + Enabled + Auto collision resolution enabled + 0 + + + Disabled + Auto collision resolution disabled + 1 + + + + + + + SENSRES + NFC-A SENS_RES auto-response settings + 0x5A0 + read-write + 0x00000001 + + + BITFRAMESDD + Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 0 + 4 + + + SDD00000 + SDD pattern 00000 + 0 + + + SDD00001 + SDD pattern 00001 + 1 + + + SDD00010 + SDD pattern 00010 + 2 + + + SDD00100 + SDD pattern 00100 + 4 + + + SDD01000 + SDD pattern 01000 + 8 + + + SDD10000 + SDD pattern 10000 + 16 + + + + + RFU5 + Reserved for future use. Shall be 0. + 5 + 5 + + + NFCIDSIZE + NFCID1 size. This value is used by the auto collision resolution engine. + 6 + 7 + + + NFCID1Single + NFCID1 size: single (4 bytes) + 0 + + + NFCID1Double + NFCID1 size: double (7 bytes) + 1 + + + NFCID1Triple + NFCID1 size: triple (10 bytes) + 2 + + + + + PLATFCONFIG + Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 8 + 11 + + + RFU74 + Reserved for future use. Shall be 0. + 12 + 15 + + + + + SELRES + NFC-A SEL_RES auto-response settings + 0x5A4 + read-write + + + RFU10 + Reserved for future use. Shall be 0. + 0 + 1 + + + CASCADE + Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) + 2 + 2 + + + RFU43 + Reserved for future use. Shall be 0. + 3 + 4 + + + PROTOCOL + Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 5 + 6 + + + RFU7 + Reserved for future use. Shall be 0. + 7 + 7 + + + + + + + GPIOTE + GPIO Tasks and Events + 0x40006000 + + 0 + 0x1000 + registers + + + GPIOTE + 6 + + GPIOTE + 0x20 + + + 0x8 + 0x4 + TASKS_OUT[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0x000 + write-only + + + TASKS_OUT + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_SET[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0x030 + write-only + + + TASKS_SET + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_CLR[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0x060 + write-only + + + TASKS_CLR + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + EVENTS_IN[%s] + Description collection: Event generated from pin specified in CONFIG[n].PSEL + 0x100 + read-write + + + EVENTS_IN + Event generated from pin specified in CONFIG[n].PSEL + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0x17C + read-write + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + IN0 + Write '1' to enable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN1 + Write '1' to enable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN2 + Write '1' to enable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN3 + Write '1' to enable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN4 + Write '1' to enable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN5 + Write '1' to enable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN6 + Write '1' to enable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN7 + Write '1' to enable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PORT + Write '1' to enable interrupt for event PORT + 31 + 31 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + IN0 + Write '1' to disable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN1 + Write '1' to disable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN2 + Write '1' to disable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN3 + Write '1' to disable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN4 + Write '1' to disable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN5 + Write '1' to disable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN6 + Write '1' to disable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN7 + Write '1' to disable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PORT + Write '1' to disable interrupt for event PORT + 31 + 31 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + 0x8 + 0x4 + CONFIG[%s] + Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event + 0x510 + read-write + + + MODE + Mode + 0 + 1 + + + Disabled + Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. + 0 + + + Event + Event mode + 1 + + + Task + Task mode + 3 + + + + + PSEL + GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event + 8 + 12 + + + PORT + Port number + 13 + 13 + + + POLARITY + When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. + 16 + 17 + + + None + Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. + 0 + + + LoToHi + Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. + 1 + + + HiToLo + Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. + 2 + + + Toggle + Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. + 3 + + + + + OUTINIT + When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. + 20 + 20 + + + Low + Task mode: Initial value of pin before task triggering is low + 0 + + + High + Task mode: Initial value of pin before task triggering is high + 1 + + + + + + + + + SAADC + Successive approximation register (SAR) analog-to-digital converter + 0x40007000 + + 0 + 0x1000 + registers + + + SAADC + 7 + + SAADC + 0x20 + + + TASKS_START + Starts the SAADC and prepares the result buffer in RAM + 0x000 + write-only + + + TASKS_START + Starts the SAADC and prepares the result buffer in RAM + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SAMPLE + Takes one SAADC sample + 0x004 + write-only + + + TASKS_SAMPLE + Takes one SAADC sample + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stops the SAADC and terminates all on-going conversions + 0x008 + write-only + + + TASKS_STOP + Stops the SAADC and terminates all on-going conversions + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0x00C + write-only + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STARTED + The SAADC has started + 0x100 + read-write + + + EVENTS_STARTED + The SAADC has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + The SAADC has filled up the result buffer + 0x104 + read-write + + + EVENTS_END + The SAADC has filled up the result buffer + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DONE + A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. + 0x108 + read-write + + + EVENTS_DONE + A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RESULTDONE + Result ready for transfer to RAM + 0x10C + read-write + + + EVENTS_RESULTDONE + Result ready for transfer to RAM + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0x110 + read-write + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + The SAADC has stopped + 0x114 + read-write + + + EVENTS_STOPPED + The SAADC has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 8 + 0x008 + EVENTS_CH[%s] + Peripheral events. + SAADC_EVENTS_CH + read-write + 0x118 + + LIMITH + Description cluster: Last result is equal or above CH[n].LIMIT.HIGH + 0x000 + read-write + + + LIMITH + Last result is equal or above CH[n].LIMIT.HIGH + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + LIMITL + Description cluster: Last result is equal or below CH[n].LIMIT.LOW + 0x004 + read-write + + + LIMITL + Last result is equal or below CH[n].LIMIT.LOW + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + END + Enable or disable interrupt for event END + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DONE + Enable or disable interrupt for event DONE + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RESULTDONE + Enable or disable interrupt for event RESULTDONE + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CALIBRATEDONE + Enable or disable interrupt for event CALIBRATEDONE + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH0LIMITH + Enable or disable interrupt for event CH0LIMITH + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH0LIMITL + Enable or disable interrupt for event CH0LIMITL + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH1LIMITH + Enable or disable interrupt for event CH1LIMITH + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH1LIMITL + Enable or disable interrupt for event CH1LIMITL + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH2LIMITH + Enable or disable interrupt for event CH2LIMITH + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH2LIMITL + Enable or disable interrupt for event CH2LIMITL + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH3LIMITH + Enable or disable interrupt for event CH3LIMITH + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH3LIMITL + Enable or disable interrupt for event CH3LIMITL + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH4LIMITH + Enable or disable interrupt for event CH4LIMITH + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH4LIMITL + Enable or disable interrupt for event CH4LIMITL + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH5LIMITH + Enable or disable interrupt for event CH5LIMITH + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH5LIMITL + Enable or disable interrupt for event CH5LIMITL + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH6LIMITH + Enable or disable interrupt for event CH6LIMITH + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH6LIMITL + Enable or disable interrupt for event CH6LIMITL + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH7LIMITH + Enable or disable interrupt for event CH7LIMITH + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH7LIMITL + Enable or disable interrupt for event CH7LIMITL + 21 + 21 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DONE + Write '1' to enable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RESULTDONE + Write '1' to enable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CALIBRATEDONE + Write '1' to enable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH0LIMITH + Write '1' to enable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH0LIMITL + Write '1' to enable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH1LIMITH + Write '1' to enable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH1LIMITL + Write '1' to enable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH2LIMITH + Write '1' to enable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH2LIMITL + Write '1' to enable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH3LIMITH + Write '1' to enable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH3LIMITL + Write '1' to enable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH4LIMITH + Write '1' to enable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH4LIMITL + Write '1' to enable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH5LIMITH + Write '1' to enable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH5LIMITL + Write '1' to enable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH6LIMITH + Write '1' to enable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH6LIMITL + Write '1' to enable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH7LIMITH + Write '1' to enable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH7LIMITL + Write '1' to enable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DONE + Write '1' to disable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RESULTDONE + Write '1' to disable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CALIBRATEDONE + Write '1' to disable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH0LIMITH + Write '1' to disable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH0LIMITL + Write '1' to disable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH1LIMITH + Write '1' to disable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH1LIMITL + Write '1' to disable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH2LIMITH + Write '1' to disable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH2LIMITL + Write '1' to disable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH3LIMITH + Write '1' to disable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH3LIMITL + Write '1' to disable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH4LIMITH + Write '1' to disable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH4LIMITL + Write '1' to disable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH5LIMITH + Write '1' to disable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH5LIMITL + Write '1' to disable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH6LIMITH + Write '1' to disable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH6LIMITL + Write '1' to disable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH7LIMITH + Write '1' to disable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH7LIMITL + Write '1' to disable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + STATUS + Status + 0x400 + read-only + + + STATUS + Status + 0 + 0 + + + Ready + SAADC is ready. No on-going conversions. + 0 + + + Busy + SAADC is busy. Conversion in progress. + 1 + + + + + + + ENABLE + Enable or disable SAADC + 0x500 + read-write + + + ENABLE + Enable or disable SAADC + 0 + 0 + + + Disabled + Disable SAADC + 0 + + + Enabled + Enable SAADC + 1 + + + + + + + 8 + 0x010 + CH[%s] + Unspecified + SAADC_CH + read-write + 0x510 + + PSELP + Description cluster: Input positive pin selection for CH[n] + 0x000 + read-write + 0x00000000 + + + PSELP + Analog positive input channel + 0 + 4 + + + NC + Not connected + 0 + + + AnalogInput0 + AIN0 + 1 + + + AnalogInput1 + AIN1 + 2 + + + AnalogInput2 + AIN2 + 3 + + + AnalogInput3 + AIN3 + 4 + + + AnalogInput4 + AIN4 + 5 + + + AnalogInput5 + AIN5 + 6 + + + AnalogInput6 + AIN6 + 7 + + + AnalogInput7 + AIN7 + 8 + + + VDD + VDD + 9 + + + VDDHDIV5 + VDDH/5 + 0x0D + + + + + + + PSELN + Description cluster: Input negative pin selection for CH[n] + 0x004 + read-write + 0x00000000 + + + PSELN + Analog negative input, enables differential channel + 0 + 4 + + + NC + Not connected + 0 + + + AnalogInput0 + AIN0 + 1 + + + AnalogInput1 + AIN1 + 2 + + + AnalogInput2 + AIN2 + 3 + + + AnalogInput3 + AIN3 + 4 + + + AnalogInput4 + AIN4 + 5 + + + AnalogInput5 + AIN5 + 6 + + + AnalogInput6 + AIN6 + 7 + + + AnalogInput7 + AIN7 + 8 + + + VDD + VDD + 9 + + + VDDHDIV5 + VDDH/5 + 0x0D + + + + + + + CONFIG + Description cluster: Input configuration for CH[n] + 0x008 + read-write + 0x00020000 + + + RESP + Positive channel resistor control + 0 + 1 + + + Bypass + Bypass resistor ladder + 0 + + + Pulldown + Pull-down to GND + 1 + + + Pullup + Pull-up to VDD + 2 + + + VDD1_2 + Set input at VDD/2 + 3 + + + + + RESN + Negative channel resistor control + 4 + 5 + + + Bypass + Bypass resistor ladder + 0 + + + Pulldown + Pull-down to GND + 1 + + + Pullup + Pull-up to VDD + 2 + + + VDD1_2 + Set input at VDD/2 + 3 + + + + + GAIN + Gain control + 8 + 10 + + + Gain1_6 + 1/6 + 0 + + + Gain1_5 + 1/5 + 1 + + + Gain1_4 + 1/4 + 2 + + + Gain1_3 + 1/3 + 3 + + + Gain1_2 + 1/2 + 4 + + + Gain1 + 1 + 5 + + + Gain2 + 2 + 6 + + + Gain4 + 4 + 7 + + + + + REFSEL + Reference control + 12 + 12 + + + Internal + Internal reference (0.6 V) + 0 + + + VDD1_4 + VDD/4 as reference + 1 + + + + + TACQ + Acquisition time, the time the SAADC uses to sample the input voltage + 16 + 18 + + + 3us + 3 us + 0 + + + 5us + 5 us + 1 + + + 10us + 10 us + 2 + + + 15us + 15 us + 3 + + + 20us + 20 us + 4 + + + 40us + 40 us + 5 + + + + + MODE + Enable differential mode + 20 + 20 + + + SE + Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND + 0 + + + Diff + Differential + 1 + + + + + BURST + Enable burst mode + 24 + 24 + + + Disabled + Burst mode is disabled (normal operation) + 0 + + + Enabled + Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. + 1 + + + + + + + LIMIT + Description cluster: High/low limits for event monitoring of a channel + 0x00C + read-write + 0x7FFF8000 + + + LOW + Low level limit + 0 + 15 + + + HIGH + High level limit + 16 + 31 + + + + + + RESOLUTION + Resolution configuration + 0x5F0 + read-write + 0x00000001 + + + VAL + Set the resolution + 0 + 2 + + + 8bit + 8 bits + 0 + + + 10bit + 10 bits + 1 + + + 12bit + 12 bits + 2 + + + 14bit + 14 bits + 3 + + + + + + + OVERSAMPLE + Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. + 0x5F4 + read-write + + + OVERSAMPLE + Oversample control + 0 + 3 + + + Bypass + Bypass oversampling + 0 + + + Over2x + Oversample 2x + 1 + + + Over4x + Oversample 4x + 2 + + + Over8x + Oversample 8x + 3 + + + Over16x + Oversample 16x + 4 + + + Over32x + Oversample 32x + 5 + + + Over64x + Oversample 64x + 6 + + + Over128x + Oversample 128x + 7 + + + Over256x + Oversample 256x + 8 + + + + + + + SAMPLERATE + Controls normal or continuous sample rate + 0x5F8 + read-write + + + CC + Capture and compare value. Sample rate is 16 MHz/CC + 0 + 10 + + + MODE + Select mode for sample rate control + 12 + 12 + + + Task + Rate is controlled from SAMPLE task + 0 + + + Timers + Rate is controlled from local timer (use CC to control the rate) + 1 + + + + + + + RESULT + RESULT EasyDMA channel + SAADC_RESULT + read-write + 0x62C + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of 16-bit samples to be written to output RAM buffer + 0x004 + read-write + + + MAXCNT + Maximum number of 16-bit samples to be written to output RAM buffer + 0 + 14 + + + + + AMOUNT + Number of 16-bit samples written to output RAM buffer since the previous START task + 0x008 + read-only + + + AMOUNT + Number of 16-bit samples written to output RAM buffer since the previous START task. This register can be read after an END or STOPPED event. + 0 + 14 + + + + + + + + TIMER0 + Timer/Counter 0 + 0x40008000 + TIMER + + 0 + 0x1000 + registers + + + TIMER0 + 8 + + TIMER + 0x20 + + + TASKS_START + Start Timer + 0x000 + write-only + + + TASKS_START + Start Timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop Timer + 0x004 + write-only + + + TASKS_STOP + Stop Timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0x008 + write-only + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CLEAR + Clear time + 0x00C + write-only + + + TASKS_CLEAR + Clear time + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SHUTDOWN + Deprecated register - Shut down timer + 0x010 + write-only + + + TASKS_SHUTDOWN + Deprecated field - Shut down timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x6 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture Timer value to CC[n] register + 0x040 + write-only + + + TASKS_CAPTURE + Capture Timer value to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x6 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE4_CLEAR + Shortcut between event COMPARE[4] and task CLEAR + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_CLEAR + Shortcut between event COMPARE[5] and task CLEAR + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE0_STOP + Shortcut between event COMPARE[0] and task STOP + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_STOP + Shortcut between event COMPARE[1] and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_STOP + Shortcut between event COMPARE[2] and task STOP + 10 + 10 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_STOP + Shortcut between event COMPARE[3] and task STOP + 11 + 11 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE4_STOP + Shortcut between event COMPARE[4] and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_STOP + Shortcut between event COMPARE[5] and task STOP + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + MODE + Timer mode selection + 0x504 + read-write + + + MODE + Timer mode + 0 + 1 + + + Timer + Select Timer mode + 0 + + + Counter + Deprecated enumerator - Select Counter mode + 1 + + + LowPowerCounter + Select Low Power Counter mode + 2 + + + + + + + BITMODE + Configure the number of bits used by the TIMER + 0x508 + read-write + + + BITMODE + Timer bit width + 0 + 1 + + + 16Bit + 16 bit timer bit width + 0 + + + 08Bit + 8 bit timer bit width + 1 + + + 24Bit + 24 bit timer bit width + 2 + + + 32Bit + 32 bit timer bit width + 3 + + + + + + + PRESCALER + Timer prescaler register + 0x510 + read-write + 0x00000004 + + + PRESCALER + Prescaler value + 0 + 3 + + + + + 0x6 + 0x4 + CC[%s] + Description collection: Capture/Compare register n + 0x540 + read-write + + + CC + Capture/Compare value + 0 + 31 + + + + + + + TIMER1 + Timer/Counter 1 + 0x40009000 + + TIMER1 + 9 + + + + TIMER2 + Timer/Counter 2 + 0x4000A000 + + TIMER2 + 10 + + + + RTC0 + Real time counter 0 + 0x4000B000 + RTC + + 0 + 0x1000 + registers + + + RTC0 + 11 + + RTC + 0x20 + + + TASKS_START + Start RTC COUNTER + 0x000 + write-only + + + TASKS_START + Start RTC COUNTER + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop RTC COUNTER + 0x004 + write-only + + + TASKS_STOP + Stop RTC COUNTER + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CLEAR + Clear RTC COUNTER + 0x008 + write-only + + + TASKS_CLEAR + Clear RTC COUNTER + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_TRIGOVRFLW + Set COUNTER to 0xFFFFF0 + 0x00C + write-only + + + TASKS_TRIGOVRFLW + Set COUNTER to 0xFFFFF0 + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_TICK + Event on COUNTER increment + 0x100 + read-write + + + EVENTS_TICK + Event on COUNTER increment + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_OVRFLW + Event on COUNTER overflow + 0x104 + read-write + + + EVENTS_OVRFLW + Event on COUNTER overflow + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x4 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TICK + Write '1' to enable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + OVRFLW + Write '1' to enable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TICK + Write '1' to disable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + OVRFLW + Write '1' to disable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + EVTEN + Enable or disable event routing + 0x340 + read-write + + + TICK + Enable or disable event routing for event TICK + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + OVRFLW + Enable or disable event routing for event OVRFLW + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + COMPARE0 + Enable or disable event routing for event COMPARE[0] + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + COMPARE1 + Enable or disable event routing for event COMPARE[1] + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + COMPARE2 + Enable or disable event routing for event COMPARE[2] + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + COMPARE3 + Enable or disable event routing for event COMPARE[3] + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + + + EVTENSET + Enable event routing + 0x344 + read-write + + + TICK + Write '1' to enable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + OVRFLW + Write '1' to enable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE0 + Write '1' to enable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + EVTENCLR + Disable event routing + 0x348 + read-write + + + TICK + Write '1' to disable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + OVRFLW + Write '1' to disable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE0 + Write '1' to disable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + COUNTER + Current COUNTER value + 0x504 + read-only + + + COUNTER + Counter value + 0 + 23 + + + + + PRESCALER + 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. + 0x508 + read-write + + + PRESCALER + Prescaler value + 0 + 11 + + + + + 0x4 + 0x4 + CC[%s] + Description collection: Compare register n + 0x540 + read-write + + + COMPARE + Compare value + 0 + 23 + + + + + + + TEMP + Temperature Sensor + 0x4000C000 + + 0 + 0x1000 + registers + + + TEMP + 12 + + TEMP + 0x20 + + + TASKS_START + Start temperature measurement + 0x000 + write-only + + + TASKS_START + Start temperature measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop temperature measurement + 0x004 + write-only + + + TASKS_STOP + Stop temperature measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0x100 + read-write + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + DATARDY + Write '1' to enable interrupt for event DATARDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + DATARDY + Write '1' to disable interrupt for event DATARDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + TEMP + Temperature in degC (0.25deg steps) + 0x508 + read-only + int32_t + + + TEMP + Temperature in degC (0.25deg steps) + 0 + 31 + + + + + A0 + Slope of first piecewise linear function + 0x520 + read-write + 0x00000326 + + + A0 + Slope of first piecewise linear function + 0 + 11 + + + + + A1 + Slope of second piecewise linear function + 0x524 + read-write + 0x00000348 + + + A1 + Slope of second piecewise linear function + 0 + 11 + + + + + A2 + Slope of third piecewise linear function + 0x528 + read-write + 0x000003AA + + + A2 + Slope of third piecewise linear function + 0 + 11 + + + + + A3 + Slope of fourth piecewise linear function + 0x52C + read-write + 0x0000040E + + + A3 + Slope of fourth piecewise linear function + 0 + 11 + + + + + A4 + Slope of fifth piecewise linear function + 0x530 + read-write + 0x000004BD + + + A4 + Slope of fifth piecewise linear function + 0 + 11 + + + + + A5 + Slope of sixth piecewise linear function + 0x534 + read-write + 0x000005A3 + + + A5 + Slope of sixth piecewise linear function + 0 + 11 + + + + + B0 + y-intercept of first piecewise linear function + 0x540 + read-write + 0x00003FEF + + + B0 + y-intercept of first piecewise linear function + 0 + 13 + + + + + B1 + y-intercept of second piecewise linear function + 0x544 + read-write + 0x00003FBE + + + B1 + y-intercept of second piecewise linear function + 0 + 13 + + + + + B2 + y-intercept of third piecewise linear function + 0x548 + read-write + 0x00003FBE + + + B2 + y-intercept of third piecewise linear function + 0 + 13 + + + + + B3 + y-intercept of fourth piecewise linear function + 0x54C + read-write + 0x00000012 + + + B3 + y-intercept of fourth piecewise linear function + 0 + 13 + + + + + B4 + y-intercept of fifth piecewise linear function + 0x550 + read-write + 0x00000124 + + + B4 + y-intercept of fifth piecewise linear function + 0 + 13 + + + + + B5 + y-intercept of sixth piecewise linear function + 0x554 + read-write + 0x0000027C + + + B5 + y-intercept of sixth piecewise linear function + 0 + 13 + + + + + T0 + End point of first piecewise linear function + 0x560 + read-write + 0x000000E2 + + + T0 + End point of first piecewise linear function + 0 + 7 + + + + + T1 + End point of second piecewise linear function + 0x564 + read-write + 0x00000000 + + + T1 + End point of second piecewise linear function + 0 + 7 + + + + + T2 + End point of third piecewise linear function + 0x568 + read-write + 0x00000019 + + + T2 + End point of third piecewise linear function + 0 + 7 + + + + + T3 + End point of fourth piecewise linear function + 0x56C + read-write + 0x0000003C + + + T3 + End point of fourth piecewise linear function + 0 + 7 + + + + + T4 + End point of fifth piecewise linear function + 0x570 + read-write + 0x00000050 + + + T4 + End point of fifth piecewise linear function + 0 + 7 + + + + + + + RNG + Random Number Generator + 0x4000D000 + + 0 + 0x1000 + registers + + + RNG + 13 + + RNG + 0x20 + + + TASKS_START + Task starting the random number generator + 0x000 + write-only + + + TASKS_START + Task starting the random number generator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Task stopping the random number generator + 0x004 + write-only + + + TASKS_STOP + Task stopping the random number generator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_VALRDY + Event being generated for every new random number written to the VALUE register + 0x100 + read-write + + + EVENTS_VALRDY + Event being generated for every new random number written to the VALUE register + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + VALRDY_STOP + Shortcut between event VALRDY and task STOP + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + VALRDY + Write '1' to enable interrupt for event VALRDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + VALRDY + Write '1' to disable interrupt for event VALRDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + CONFIG + Configuration register + 0x504 + read-write + + + DERCEN + Bias correction + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + + + VALUE + Output random number + 0x508 + read-only + + + VALUE + Generated random number + 0 + 7 + + + + + + + ECB + AES ECB Mode Encryption + 0x4000E000 + + 0 + 0x1000 + registers + + + ECB + 14 + + ECB + 0x20 + + + TASKS_STARTECB + Start ECB block encrypt + 0x000 + write-only + + + TASKS_STARTECB + Start ECB block encrypt + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPECB + Abort a possible executing ECB operation + 0x004 + write-only + + + TASKS_STOPECB + Abort a possible executing ECB operation + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_ENDECB + ECB block encrypt complete + 0x100 + read-write + + + EVENTS_ENDECB + ECB block encrypt complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERRORECB + ECB block encrypt aborted because of a STOPECB task or due to an error + 0x104 + read-write + + + EVENTS_ERRORECB + ECB block encrypt aborted because of a STOPECB task or due to an error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + ENDECB + Write '1' to enable interrupt for event ENDECB + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERRORECB + Write '1' to enable interrupt for event ERRORECB + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + ENDECB + Write '1' to disable interrupt for event ENDECB + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERRORECB + Write '1' to disable interrupt for event ERRORECB + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ECBDATAPTR + ECB block encrypt memory pointers + 0x504 + read-write + + + ECBDATAPTR + Pointer to the ECB data structure (see Table 1 ECB data structure overview) + 0 + 31 + + + + + + + AAR + Accelerated Address Resolver + 0x4000F000 + + 0 + 0x1000 + registers + + + CCM_AAR + 15 + + AAR + 0x20 + + + TASKS_START + Start resolving addresses based on IRKs specified in the IRK data structure + 0x000 + write-only + + + TASKS_START + Start resolving addresses based on IRKs specified in the IRK data structure + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop resolving addresses + 0x008 + write-only + + + TASKS_STOP + Stop resolving addresses + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_END + Address resolution procedure complete + 0x100 + read-write + + + EVENTS_END + Address resolution procedure complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RESOLVED + Address resolved + 0x104 + read-write + + + EVENTS_RESOLVED + Address resolved + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_NOTRESOLVED + Address not resolved + 0x108 + read-write + + + EVENTS_NOTRESOLVED + Address not resolved + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + END + Write '1' to enable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RESOLVED + Write '1' to enable interrupt for event RESOLVED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NOTRESOLVED + Write '1' to enable interrupt for event NOTRESOLVED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + END + Write '1' to disable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RESOLVED + Write '1' to disable interrupt for event RESOLVED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NOTRESOLVED + Write '1' to disable interrupt for event NOTRESOLVED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + STATUS + Resolution status + 0x400 + read-only + + + STATUS + The IRK that was used last time an address was resolved + 0 + 3 + + + + + ENABLE + Enable AAR + 0x500 + read-write + + + ENABLE + Enable or disable AAR + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 3 + + + + + + + NIRK + Number of IRKs + 0x504 + read-write + 0x00000001 + + + NIRK + Number of Identity Root Keys available in the IRK data structure + 0 + 4 + + + + + IRKPTR + Pointer to IRK data structure + 0x508 + read-write + + + IRKPTR + Pointer to the IRK data structure + 0 + 31 + + + + + ADDRPTR + Pointer to the resolvable address + 0x510 + read-write + + + ADDRPTR + Pointer to the resolvable address (6-bytes) + 0 + 31 + + + + + SCRATCHPTR + Pointer to data area used for temporary storage + 0x514 + read-write + + + SCRATCHPTR + Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. + 0 + 31 + + + + + + + CCM + AES CCM Mode Encryption + 0x4000F000 + AAR + + 0 + 0x1000 + registers + + + CCM_AAR + 15 + + CCM + 0x20 + + + TASKS_KSGEN + Start generation of keystream. This operation will stop by itself when completed. + 0x000 + write-only + + + TASKS_KSGEN + Start generation of keystream. This operation will stop by itself when completed. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CRYPT + Start encryption/decryption. This operation will stop by itself when completed. + 0x004 + write-only + + + TASKS_CRYPT + Start encryption/decryption. This operation will stop by itself when completed. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop encryption/decryption + 0x008 + write-only + + + TASKS_STOP + Stop encryption/decryption + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RATEOVERRIDE + Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption + 0x00C + write-only + + + TASKS_RATEOVERRIDE + Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_ENDKSGEN + Keystream generation complete + 0x100 + read-write + + + EVENTS_ENDKSGEN + Keystream generation complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDCRYPT + Encrypt/decrypt complete + 0x104 + read-write + + + EVENTS_ENDCRYPT + Encrypt/decrypt complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + Deprecated register - CCM error event + 0x108 + read-write + + + EVENTS_ERROR + Deprecated field - CCM error event + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + ENDKSGEN_CRYPT + Shortcut between event ENDKSGEN and task CRYPT + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + ENDKSGEN + Write '1' to enable interrupt for event ENDKSGEN + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDCRYPT + Write '1' to enable interrupt for event ENDCRYPT + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Deprecated intsetfield - Write '1' to enable interrupt for event ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + ENDKSGEN + Write '1' to disable interrupt for event ENDKSGEN + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDCRYPT + Write '1' to disable interrupt for event ENDCRYPT + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Deprecated intclrfield - Write '1' to disable interrupt for event ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + MICSTATUS + MIC check result + 0x400 + read-only + + + MICSTATUS + The result of the MIC check performed during the previous decryption operation + 0 + 0 + + + CheckFailed + MIC check failed + 0 + + + CheckPassed + MIC check passed + 1 + + + + + + + ENABLE + Enable + 0x500 + read-write + + + ENABLE + Enable or disable CCM + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 2 + + + + + + + MODE + Operation mode + 0x504 + read-write + 0x00000001 + + + MODE + The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. + 0 + 0 + + + Encryption + AES CCM packet encryption mode + 0 + + + Decryption + AES CCM packet decryption mode + 1 + + + + + DATARATE + Radio data rate that the CCM shall run synchronous with + 16 + 17 + + + 1Mbit + 1 Mbps + 0 + + + 2Mbit + 2 Mbps + 1 + + + 125Kbps + 125 Kbps + 2 + + + 500Kbps + 500 Kbps + 3 + + + + + LENGTH + Packet length configuration + 24 + 24 + + + Default + Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. + 0 + + + Extended + Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. + 1 + + + + + + + CNFPTR + Pointer to data structure holding AES key and NONCE vector + 0x508 + read-write + + + CNFPTR + Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) + 0 + 31 + + + + + INPTR + Input pointer + 0x50C + read-write + + + INPTR + Input pointer + 0 + 31 + + + + + OUTPTR + Output pointer + 0x510 + read-write + + + OUTPTR + Output pointer + 0 + 31 + + + + + SCRATCHPTR + Pointer to data area used for temporary storage + 0x514 + read-write + + + SCRATCHPTR + Pointer to a scratch data area used for temporary storage during keystream generation, + MIC generation and encryption/decryption. + 0 + 31 + + + + + MAXPACKETSIZE + Length of keystream generated when MODE.LENGTH = Extended. + 0x518 + read-write + 0x000000FB + + + MAXPACKETSIZE + Length of keystream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. + 0 + 7 + + + + + RATEOVERRIDE + Data rate override setting. + 0x51C + read-write + 0x00000000 + + + RATEOVERRIDE + Data rate override setting. + 0 + 1 + + + 1Mbit + 1 Mbps + 0 + + + 2Mbit + 2 Mbps + 1 + + + 125Kbps + 125 Kbps + 2 + + + 500Kbps + 500 Kbps + 3 + + + + + + + + + WDT + Watchdog Timer + 0x40010000 + + 0 + 0x1000 + registers + + + WDT + 16 + + WDT + 0x20 + + + TASKS_START + Start the watchdog + 0x000 + write-only + + + TASKS_START + Start the watchdog + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_TIMEOUT + Watchdog timeout + 0x100 + read-write + + + EVENTS_TIMEOUT + Watchdog timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RUNSTATUS + Run status + 0x400 + read-only + + + RUNSTATUS + Indicates whether or not the watchdog is running + 0 + 0 + + + NotRunning + Watchdog not running + 0 + + + Running + Watchdog is running + 1 + + + + + + + REQSTATUS + Request status + 0x404 + read-only + 0x00000001 + + + RR0 + Request status for RR[0] register + 0 + 0 + + + DisabledOrRequested + RR[0] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[0] register is enabled, and are not yet requesting reload + 1 + + + + + RR1 + Request status for RR[1] register + 1 + 1 + + + DisabledOrRequested + RR[1] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[1] register is enabled, and are not yet requesting reload + 1 + + + + + RR2 + Request status for RR[2] register + 2 + 2 + + + DisabledOrRequested + RR[2] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[2] register is enabled, and are not yet requesting reload + 1 + + + + + RR3 + Request status for RR[3] register + 3 + 3 + + + DisabledOrRequested + RR[3] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[3] register is enabled, and are not yet requesting reload + 1 + + + + + RR4 + Request status for RR[4] register + 4 + 4 + + + DisabledOrRequested + RR[4] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[4] register is enabled, and are not yet requesting reload + 1 + + + + + RR5 + Request status for RR[5] register + 5 + 5 + + + DisabledOrRequested + RR[5] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[5] register is enabled, and are not yet requesting reload + 1 + + + + + RR6 + Request status for RR[6] register + 6 + 6 + + + DisabledOrRequested + RR[6] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[6] register is enabled, and are not yet requesting reload + 1 + + + + + RR7 + Request status for RR[7] register + 7 + 7 + + + DisabledOrRequested + RR[7] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[7] register is enabled, and are not yet requesting reload + 1 + + + + + + + CRV + Counter reload value + 0x504 + read-write + 0xFFFFFFFF + + + CRV + Counter reload value in number of cycles of the 32.768 kHz clock + 0 + 31 + + + + + RREN + Enable register for reload request registers + 0x508 + read-write + 0x00000001 + + + RR0 + Enable or disable RR[0] register + 0 + 0 + + + Disabled + Disable RR[0] register + 0 + + + Enabled + Enable RR[0] register + 1 + + + + + RR1 + Enable or disable RR[1] register + 1 + 1 + + + Disabled + Disable RR[1] register + 0 + + + Enabled + Enable RR[1] register + 1 + + + + + RR2 + Enable or disable RR[2] register + 2 + 2 + + + Disabled + Disable RR[2] register + 0 + + + Enabled + Enable RR[2] register + 1 + + + + + RR3 + Enable or disable RR[3] register + 3 + 3 + + + Disabled + Disable RR[3] register + 0 + + + Enabled + Enable RR[3] register + 1 + + + + + RR4 + Enable or disable RR[4] register + 4 + 4 + + + Disabled + Disable RR[4] register + 0 + + + Enabled + Enable RR[4] register + 1 + + + + + RR5 + Enable or disable RR[5] register + 5 + 5 + + + Disabled + Disable RR[5] register + 0 + + + Enabled + Enable RR[5] register + 1 + + + + + RR6 + Enable or disable RR[6] register + 6 + 6 + + + Disabled + Disable RR[6] register + 0 + + + Enabled + Enable RR[6] register + 1 + + + + + RR7 + Enable or disable RR[7] register + 7 + 7 + + + Disabled + Disable RR[7] register + 0 + + + Enabled + Enable RR[7] register + 1 + + + + + + + CONFIG + Configuration register + 0x50C + read-write + 0x00000001 + + + SLEEP + Configure the watchdog to either be paused, or kept running, while the CPU is sleeping + 0 + 0 + + + Pause + Pause watchdog while the CPU is sleeping + 0 + + + Run + Keep the watchdog running while the CPU is sleeping + 1 + + + + + HALT + Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger + 3 + 3 + + + Pause + Pause watchdog while the CPU is halted by the debugger + 0 + + + Run + Keep the watchdog running while the CPU is halted by the debugger + 1 + + + + + + + 0x8 + 0x4 + RR[%s] + Description collection: Reload request n + 0x600 + write-only + + + RR + Reload request register + 0 + 31 + + + Reload + Value to request a reload of the watchdog timer + 0x6E524635 + + + + + + + + + RTC1 + Real time counter 1 + 0x40011000 + + RTC1 + 17 + + + + QDEC + Quadrature Decoder + 0x40012000 + + 0 + 0x1000 + registers + + + QDEC + 18 + + QDEC + 0x20 + + + TASKS_START + Task starting the quadrature decoder + 0x000 + write-only + + + TASKS_START + Task starting the quadrature decoder + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Task stopping the quadrature decoder + 0x004 + write-only + + + TASKS_STOP + Task stopping the quadrature decoder + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0x008 + write-only + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RDCLRACC + Read and clear ACC + 0x00C + write-only + + + TASKS_RDCLRACC + Read and clear ACC + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0x010 + write-only + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0x100 + read-write + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_REPORTRDY + Non-null report ready + 0x104 + read-write + + + EVENTS_REPORTRDY + Non-null report ready + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0x108 + read-write + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DBLRDY + Double displacement(s) detected + 0x10C + read-write + + + EVENTS_DBLRDY + Double displacement(s) detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + QDEC has been stopped + 0x110 + read-write + + + EVENTS_STOPPED + QDEC has been stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + REPORTRDY_READCLRACC + Shortcut between event REPORTRDY and task READCLRACC + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SAMPLERDY_STOP + Shortcut between event SAMPLERDY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + REPORTRDY_RDCLRACC + Shortcut between event REPORTRDY and task RDCLRACC + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + REPORTRDY_STOP + Shortcut between event REPORTRDY and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DBLRDY_RDCLRDBL + Shortcut between event DBLRDY and task RDCLRDBL + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DBLRDY_STOP + Shortcut between event DBLRDY and task STOP + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SAMPLERDY_READCLRACC + Shortcut between event SAMPLERDY and task READCLRACC + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + SAMPLERDY + Write '1' to enable interrupt for event SAMPLERDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REPORTRDY + Write '1' to enable interrupt for event REPORTRDY + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ACCOF + Write '1' to enable interrupt for event ACCOF + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DBLRDY + Write '1' to enable interrupt for event DBLRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + SAMPLERDY + Write '1' to disable interrupt for event SAMPLERDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REPORTRDY + Write '1' to disable interrupt for event REPORTRDY + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ACCOF + Write '1' to disable interrupt for event ACCOF + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DBLRDY + Write '1' to disable interrupt for event DBLRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable the quadrature decoder + 0x500 + read-write + + + ENABLE + Enable or disable the quadrature decoder + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + LEDPOL + LED output pin polarity + 0x504 + read-write + + + LEDPOL + LED output pin polarity + 0 + 0 + + + ActiveLow + Led active on output pin low + 0 + + + ActiveHigh + Led active on output pin high + 1 + + + + + + + SAMPLEPER + Sample period + 0x508 + read-write + + + SAMPLEPER + Sample period. The SAMPLE register will be updated for every new sample + 0 + 3 + + + 128us + 128 us + 0 + + + 256us + 256 us + 1 + + + 512us + 512 us + 2 + + + 1024us + 1024 us + 3 + + + 2048us + 2048 us + 4 + + + 4096us + 4096 us + 5 + + + 8192us + 8192 us + 6 + + + 16384us + 16384 us + 7 + + + 32ms + 32768 us + 8 + + + 65ms + 65536 us + 9 + + + 131ms + 131072 us + 10 + + + + + + + SAMPLE + Motion sample value + 0x50C + read-only + int32_t + + + SAMPLE + Last motion sample + 0 + 31 + + + + + REPORTPER + Number of samples to be taken before REPORTRDY and DBLRDY events can be generated + 0x510 + read-write + + + REPORTPER + Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. + 0 + 3 + + + 10Smpl + 10 samples/report + 0 + + + 40Smpl + 40 samples/report + 1 + + + 80Smpl + 80 samples/report + 2 + + + 120Smpl + 120 samples/report + 3 + + + 160Smpl + 160 samples/report + 4 + + + 200Smpl + 200 samples/report + 5 + + + 240Smpl + 240 samples/report + 6 + + + 280Smpl + 280 samples/report + 7 + + + 1Smpl + 1 sample/report + 8 + + + + + + + ACC + Register accumulating the valid transitions + 0x514 + read-only + int32_t + + + ACC + Register accumulating all valid samples (not double transition) read from the SAMPLE register. + 0 + 31 + + + + + ACCREAD + Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task + 0x518 + read-only + int32_t + + + ACCREAD + Snapshot of the ACC register. + 0 + 31 + + + + + PSEL + Unspecified + QDEC_PSEL + read-write + 0x51C + + LED + Pin select for LED signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + A + Pin select for A signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + B + Pin select for B signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + DBFEN + Enable input debounce filters + 0x528 + read-write + + + DBFEN + Enable input debounce filters + 0 + 0 + + + Disabled + Debounce input filters disabled + 0 + + + Enabled + Debounce input filters enabled + 1 + + + + + + + LEDPRE + Time period the LED is switched ON prior to sampling + 0x540 + read-write + 0x00000010 + + + LEDPRE + Period in us the LED is switched on prior to sampling + 0 + 8 + + + + + ACCDBL + Register accumulating the number of detected double transitions + 0x544 + read-only + + + ACCDBL + Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). + 0 + 3 + + + + + ACCDBLREAD + Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task + 0x548 + read-only + + + ACCDBLREAD + Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. + 0 + 3 + + + + + + + COMP + Comparator + 0x40013000 + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 19 + + COMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + + + TASKS_START + Start comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + + + TASKS_STOP + Stop comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + + + TASKS_SAMPLE + Sample comparator value + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_READY + COMP is ready and output is valid + 0x100 + read-write + + + EVENTS_READY + COMP is ready and output is valid + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + + + EVENTS_DOWN + Downward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + + + EVENTS_UP + Upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + + + EVENTS_CROSS + Downward or upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DOWN + Enable or disable interrupt for event DOWN + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + UP + Enable or disable interrupt for event UP + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CROSS + Enable or disable interrupt for event CROSS + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + UP + Write '1' to enable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DOWN + Write '1' to disable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + UP + Write '1' to disable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CROSS + Write '1' to disable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RESULT + Compare result + 0x400 + read-only + + + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 + + + Below + Input voltage is below the threshold (VIN+ &lt; VIN-) + 0 + + + Above + Input voltage is above the threshold (VIN+ &gt; VIN-) + 1 + + + + + + + ENABLE + COMP enable + 0x500 + read-write + + + ENABLE + Enable or disable COMP + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 2 + + + + + + + PSEL + Pin select + 0x504 + read-write + + + PSEL + Analog pin select + 0 + 2 + + + AnalogInput0 + AIN0 selected as analog input + 0 + + + AnalogInput1 + AIN1 selected as analog input + 1 + + + AnalogInput2 + AIN2 selected as analog input + 2 + + + AnalogInput3 + AIN3 selected as analog input + 3 + + + AnalogInput4 + AIN4 selected as analog input + 4 + + + AnalogInput5 + AIN5 selected as analog input + 5 + + + AnalogInput6 + AIN6 selected as analog input + 6 + + + AnalogInput7 + AIN7 selected as analog input + 7 + + + + + + + REFSEL + Reference source select for single-ended mode + 0x508 + read-write + 0x00000004 + + + REFSEL + Reference select + 0 + 2 + + + Int1V2 + VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) + 0 + + + Int1V8 + VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) + 1 + + + Int2V4 + VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) + 2 + + + VDD + VREF = VDD + 4 + + + ARef + VREF = AREF + 5 + + + + + + + EXTREFSEL + External reference select + 0x50C + read-write + + + EXTREFSEL + External analog reference select + 0 + 2 + + + AnalogReference0 + Use AIN0 as external analog reference + 0 + + + AnalogReference1 + Use AIN1 as external analog reference + 1 + + + AnalogReference2 + Use AIN2 as external analog reference + 2 + + + AnalogReference3 + Use AIN3 as external analog reference + 3 + + + AnalogReference4 + Use AIN4 as external analog reference + 4 + + + AnalogReference5 + Use AIN5 as external analog reference + 5 + + + AnalogReference6 + Use AIN6 as external analog reference + 6 + + + AnalogReference7 + Use AIN7 as external analog reference + 7 + + + + + + + TH + Threshold configuration for hysteresis unit + 0x530 + read-write + 0x00000000 + + + THDOWN + VDOWN = (THDOWN+1)/64*VREF + 0 + 5 + + + THUP + VUP = (THUP+1)/64*VREF + 8 + 13 + + + + + MODE + Mode configuration + 0x534 + read-write + + + SP + Speed and power modes + 0 + 1 + + + Low + Low-power mode + 0 + + + Normal + Normal mode + 1 + + + High + High-speed mode + 2 + + + + + MAIN + Main operation modes + 8 + 8 + + + SE + Single-ended mode + 0 + + + Diff + Differential mode + 1 + + + + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + + + HYST + Comparator hysteresis + 0 + 0 + + + NoHyst + Comparator hysteresis disabled + 0 + + + Hyst50mV + Comparator hysteresis enabled + 1 + + + + + + + + + LPCOMP + Low-power comparator + 0x40013000 + COMP + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 19 + + LPCOMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + + + TASKS_START + Start comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + + + TASKS_STOP + Stop comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + + + TASKS_SAMPLE + Sample comparator value + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_READY + LPCOMP is ready and output is valid + 0x100 + read-write + + + EVENTS_READY + LPCOMP is ready and output is valid + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + + + EVENTS_DOWN + Downward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + + + EVENTS_UP + Upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + + + EVENTS_CROSS + Downward or upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + UP + Write '1' to enable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DOWN + Write '1' to disable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + UP + Write '1' to disable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CROSS + Write '1' to disable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RESULT + Compare result + 0x400 + read-only + + + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 + + + Below + Input voltage is below the reference threshold (VIN+ &lt; VIN-) + 0 + + + Above + Input voltage is above the reference threshold (VIN+ &gt; VIN-) + 1 + + + + + + + ENABLE + Enable LPCOMP + 0x500 + read-write + + + ENABLE + Enable or disable LPCOMP + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + PSEL + Input pin select + 0x504 + read-write + + + PSEL + Analog pin select + 0 + 2 + + + AnalogInput0 + AIN0 selected as analog input + 0 + + + AnalogInput1 + AIN1 selected as analog input + 1 + + + AnalogInput2 + AIN2 selected as analog input + 2 + + + AnalogInput3 + AIN3 selected as analog input + 3 + + + AnalogInput4 + AIN4 selected as analog input + 4 + + + AnalogInput5 + AIN5 selected as analog input + 5 + + + AnalogInput6 + AIN6 selected as analog input + 6 + + + AnalogInput7 + AIN7 selected as analog input + 7 + + + + + + + REFSEL + Reference select + 0x508 + read-write + 0x00000004 + + + REFSEL + Reference select + 0 + 3 + + + Ref1_8Vdd + VDD * 1/8 selected as reference + 0 + + + Ref2_8Vdd + VDD * 2/8 selected as reference + 1 + + + Ref3_8Vdd + VDD * 3/8 selected as reference + 2 + + + Ref4_8Vdd + VDD * 4/8 selected as reference + 3 + + + Ref5_8Vdd + VDD * 5/8 selected as reference + 4 + + + Ref6_8Vdd + VDD * 6/8 selected as reference + 5 + + + Ref7_8Vdd + VDD * 7/8 selected as reference + 6 + + + ARef + External analog reference selected + 7 + + + Ref1_16Vdd + VDD * 1/16 selected as reference + 8 + + + Ref3_16Vdd + VDD * 3/16 selected as reference + 9 + + + Ref5_16Vdd + VDD * 5/16 selected as reference + 10 + + + Ref7_16Vdd + VDD * 7/16 selected as reference + 11 + + + Ref9_16Vdd + VDD * 9/16 selected as reference + 12 + + + Ref11_16Vdd + VDD * 11/16 selected as reference + 13 + + + Ref13_16Vdd + VDD * 13/16 selected as reference + 14 + + + Ref15_16Vdd + VDD * 15/16 selected as reference + 15 + + + + + + + EXTREFSEL + External reference select + 0x50C + read-write + + + EXTREFSEL + External analog reference select + 0 + 0 + + + AnalogReference0 + Use AIN0 as external analog reference + 0 + + + AnalogReference1 + Use AIN1 as external analog reference + 1 + + + + + + + ANADETECT + Analog detect configuration + 0x520 + read-write + + + ANADETECT + Analog detect configuration + 0 + 1 + + + Cross + Generate ANADETECT on crossing, both upward crossing and downward crossing + 0 + + + Up + Generate ANADETECT on upward crossing only + 1 + + + Down + Generate ANADETECT on downward crossing only + 2 + + + + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + + + HYST + Comparator hysteresis enable + 0 + 0 + + + Disabled + Comparator hysteresis disabled + 0 + + + Enabled + Comparator hysteresis enabled + 1 + + + + + + + + + EGU0 + Event generator unit 0 + 0x40014000 + EGU + + 0 + 0x1000 + registers + + + SWI0_EGU0 + 20 + + EGU + 0x20 + + + 0x10 + 0x4 + TASKS_TRIGGER[%s] + Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event + 0x000 + write-only + + + TASKS_TRIGGER + Trigger n for triggering the corresponding TRIGGERED[n] event + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x10 + 0x4 + EVENTS_TRIGGERED[%s] + Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task + 0x100 + read-write + + + EVENTS_TRIGGERED + Event number n generated by triggering the corresponding TRIGGER[n] task + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED13 + Write '1' to enable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED14 + Write '1' to enable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED15 + Write '1' to enable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + + + SWI0 + Software interrupt 0 + 0x40014000 + EGU0 + SWI + + 0 + 0x1000 + registers + + + SWI0_EGU0 + 20 + + SWI + 0x20 + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + EGU1 + Event generator unit 1 + 0x40015000 + + SWI1_EGU1 + 21 + + + + SWI1 + Software interrupt 1 + 0x40015000 + EGU1 + + SWI1_EGU1 + 21 + + + + EGU2 + Event generator unit 2 + 0x40016000 + + SWI2_EGU2 + 22 + + + + SWI2 + Software interrupt 2 + 0x40016000 + EGU2 + + SWI2_EGU2 + 22 + + + + EGU3 + Event generator unit 3 + 0x40017000 + + SWI3_EGU3 + 23 + + + + SWI3 + Software interrupt 3 + 0x40017000 + EGU3 + + SWI3_EGU3 + 23 + + + + EGU4 + Event generator unit 4 + 0x40018000 + + SWI4_EGU4 + 24 + + + + SWI4 + Software interrupt 4 + 0x40018000 + EGU4 + + SWI4_EGU4 + 24 + + + + EGU5 + Event generator unit 5 + 0x40019000 + + SWI5_EGU5 + 25 + + + + SWI5 + Software interrupt 5 + 0x40019000 + EGU5 + + SWI5_EGU5 + 25 + + + + TIMER3 + Timer/Counter 3 + 0x4001A000 + + TIMER3 + 26 + + + + TIMER4 + Timer/Counter 4 + 0x4001B000 + + TIMER4 + 27 + + + + PWM0 + Pulse width modulation unit 0 + 0x4001C000 + PWM + + 0 + 0x1000 + registers + + + PWM0 + 28 + + PWM + 0x20 + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0x004 + write-only + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x2 + 0x4 + TASKS_SEQSTART[%s] + Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + 0x008 + write-only + + + TASKS_SEQSTART + Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0x010 + write-only + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0x104 + read-write + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQSTARTED[%s] + Description collection: First PWM period started on sequence n + 0x108 + read-write + + + EVENTS_SEQSTARTED + First PWM period started on sequence n + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQEND[%s] + Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0x110 + read-write + + + EVENTS_SEQEND + Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0x118 + read-write + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0x11C + read-write + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + SEQEND0_STOP + Shortcut between event SEQEND[0] and task STOP + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SEQEND1_STOP + Shortcut between event SEQEND[1] and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_SEQSTART0 + Shortcut between event LOOPSDONE and task SEQSTART[0] + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_SEQSTART1 + Shortcut between event LOOPSDONE and task SEQSTART[1] + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_STOP + Shortcut between event LOOPSDONE and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQSTARTED0 + Enable or disable interrupt for event SEQSTARTED[0] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQSTARTED1 + Enable or disable interrupt for event SEQSTARTED[1] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQEND0 + Enable or disable interrupt for event SEQEND[0] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQEND1 + Enable or disable interrupt for event SEQEND[1] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LOOPSDONE + Enable or disable interrupt for event LOOPSDONE + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQSTARTED0 + Write '1' to enable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQSTARTED1 + Write '1' to enable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQEND0 + Write '1' to enable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQEND1 + Write '1' to enable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LOOPSDONE + Write '1' to enable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQSTARTED0 + Write '1' to disable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQSTARTED1 + Write '1' to disable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQEND0 + Write '1' to disable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQEND1 + Write '1' to disable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LOOPSDONE + Write '1' to disable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + PWM module enable register + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable PWM module + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enable + 1 + + + + + + + MODE + Selects operating mode of the wave counter + 0x504 + read-write + 0x00000000 + + + UPDOWN + Selects up mode or up-and-down mode for the counter + 0 + 0 + + + Up + Up counter, edge-aligned PWM duty cycle + 0 + + + UpAndDown + Up and down counter, center-aligned PWM duty cycle + 1 + + + + + + + COUNTERTOP + Value up to which the pulse generator counter counts + 0x508 + read-write + 0x000003FF + + + COUNTERTOP + Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. + 0 + 14 + + + + + PRESCALER + Configuration for PWM_CLK + 0x50C + read-write + 0x00000000 + + + PRESCALER + Prescaler of PWM_CLK + 0 + 2 + + + DIV_1 + Divide by 1 (16 MHz) + 0 + + + DIV_2 + Divide by 2 (8 MHz) + 1 + + + DIV_4 + Divide by 4 (4 MHz) + 2 + + + DIV_8 + Divide by 8 (2 MHz) + 3 + + + DIV_16 + Divide by 16 (1 MHz) + 4 + + + DIV_32 + Divide by 32 (500 kHz) + 5 + + + DIV_64 + Divide by 64 (250 kHz) + 6 + + + DIV_128 + Divide by 128 (125 kHz) + 7 + + + + + + + DECODER + Configuration of the decoder + 0x510 + read-write + 0x00000000 + + + LOAD + How a sequence is read from RAM and spread to the compare register + 0 + 1 + + + Common + 1st half word (16-bit) used in all PWM channels 0..3 + 0 + + + Grouped + 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 + 1 + + + Individual + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 + 2 + + + WaveForm + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP + 3 + + + + + MODE + Selects source for advancing the active sequence + 8 + 8 + + + RefreshCount + SEQ[n].REFRESH is used to determine loading internal compare registers + 0 + + + NextStep + NEXTSTEP task causes a new value to be loaded to internal compare registers + 1 + + + + + + + LOOP + Number of playbacks of a loop + 0x514 + read-write + 0x00000000 + + + CNT + Number of playbacks of pattern cycles + 0 + 15 + + + Disabled + Looping disabled (stop at the end of the sequence) + 0 + + + + + + + 2 + 0x020 + SEQ[%s] + Unspecified + PWM_SEQ + read-write + 0x520 + + PTR + Description cluster: Beginning address in RAM of this sequence + 0x000 + read-write + 0x00000000 + + + PTR + Beginning address in RAM of this sequence + 0 + 31 + + + + + CNT + Description cluster: Number of values (duty cycles) in this sequence + 0x004 + read-write + 0x00000000 + + + CNT + Number of values (duty cycles) in this sequence + 0 + 14 + + + Disabled + Sequence is disabled, and shall not be started as it is empty + 0 + + + + + + + REFRESH + Description cluster: Number of additional PWM periods between samples loaded into compare register + 0x008 + read-write + 0x00000001 + + + CNT + Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) + 0 + 23 + + + Continuous + Update every PWM period + 0 + + + + + + + ENDDELAY + Description cluster: Time added after the sequence + 0x00C + read-write + 0x00000000 + + + CNT + Time added after the sequence in PWM periods + 0 + 23 + + + + + + PSEL + Unspecified + PWM_PSEL + read-write + 0x560 + + 0x4 + 0x4 + OUT[%s] + Description collection: Output pin select for PWM channel n + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + + + PDM + Pulse Density Modulation (Digital Microphone) Interface + 0x4001D000 + + 0 + 0x1000 + registers + + + PDM + 29 + + PDM + 0x20 + + + TASKS_START + Starts continuous PDM transfer + 0x000 + write-only + + + TASKS_START + Starts continuous PDM transfer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stops PDM transfer + 0x004 + write-only + + + TASKS_STOP + Stops PDM transfer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STARTED + PDM transfer has started + 0x100 + read-write + + + EVENTS_STARTED + PDM transfer has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + PDM transfer has finished + 0x104 + read-write + + + EVENTS_STOPPED + PDM transfer has finished + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0x108 + read-write + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + END + Enable or disable interrupt for event END + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + PDM module enable register + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable PDM module + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + PDMCLKCTRL + PDM clock generator control + 0x504 + read-write + 0x08400000 + + + FREQ + PDM_CLK frequency configuration + 0 + 31 + + + 1000K + PDM_CLK = 32 MHz / 32 = 1.000 MHz + 0x08000000 + + + Default + PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. + 0x08400000 + + + 1067K + PDM_CLK = 32 MHz / 30 = 1.067 MHz + 0x08800000 + + + 1231K + PDM_CLK = 32 MHz / 26 = 1.231 MHz + 0x09800000 + + + 1280K + PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. + 0x0A000000 + + + 1333K + PDM_CLK = 32 MHz / 24 = 1.333 MHz + 0x0A800000 + + + + + + + MODE + Defines the routing of the connected PDM microphones' signals + 0x508 + read-write + 0x00000000 + + + OPERATION + Mono or stereo operation + 0 + 0 + + + Stereo + Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] + 0 + + + Mono + Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] + 1 + + + + + EDGE + Defines on which PDM_CLK edge left (or mono) is sampled + 1 + 1 + + + LeftFalling + Left (or mono) is sampled on falling edge of PDM_CLK + 0 + + + LeftRising + Left (or mono) is sampled on rising edge of PDM_CLK + 1 + + + + + + + GAINL + Left output gain adjustment + 0x518 + read-write + 0x00000028 + + + GAINL + Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust + 0 + 6 + + + MinGain + -20 dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0 dB gain adjustment + 0x28 + + + MaxGain + +20 dB gain adjustment (maximum) + 0x50 + + + + + + + GAINR + Right output gain adjustment + 0x51C + read-write + 0x00000028 + + + GAINR + Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + 0 + 6 + + + MinGain + -20 dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0 dB gain adjustment + 0x28 + + + MaxGain + +20 dB gain adjustment (maximum) + 0x50 + + + + + + + RATIO + Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. + 0x520 + read-write + 0x00000000 + + + RATIO + Selects the ratio between PDM_CLK and output sample rate + 0 + 0 + + + Ratio64 + Ratio of 64 + 0 + + + Ratio80 + Ratio of 80 + 1 + + + + + + + PSEL + Unspecified + PDM_PSEL + read-write + 0x540 + + CLK + Pin number configuration for PDM CLK signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + DIN + Pin number configuration for PDM DIN signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + SAMPLE + Unspecified + PDM_SAMPLE + read-write + 0x560 + + PTR + RAM address pointer to write samples to with EasyDMA + 0x000 + read-write + + + SAMPLEPTR + Address to write PDM samples to over DMA + 0 + 31 + + + + + MAXCNT + Number of samples to allocate memory for in EasyDMA mode + 0x004 + read-write + + + BUFFSIZE + Length of DMA RAM allocation in number of samples + 0 + 14 + + + + + + + + ACL + Access control lists + 0x4001E000 + + 0 + 0x1000 + registers + + ACL + 0x20 + + + 8 + 0x010 + ACL[%s] + Unspecified + ACL_ACL + read-write + 0x800 + + ADDR + Description cluster: Start address of region to protect. The start address must be word-aligned. + 0x000 + read-writeonce + 0x00000000 + + + ADDR + Start address of flash region n. The start address must point to a flash page boundary. + 0 + 31 + + + + + SIZE + Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. + 0x004 + read-writeonce + 0x00000000 + + + SIZE + Size of flash region n in bytes. Must be a multiple of the flash page size. + 0 + 31 + + + + + PERM + Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE + 0x008 + read-writeonce + 0x00000000 + + + WRITE + Configure write and erase permissions for region n. Write '0' has no effect. + 1 + 1 + + + Enable + Allow write and erase instructions to region n + 0 + + + Disable + Block write and erase instructions to region n + 1 + + + + + READ + Configure read permissions for region n. Write '0' has no effect. + 2 + 2 + + + Enable + Allow read instructions to region n + 0 + + + Disable + Block read instructions to region n + 1 + + + + + + + + + + NVMC + Non Volatile Memory Controller + 0x4001E000 + ACL + + 0 + 0x1000 + registers + + NVMC + 0x20 + + + READY + Ready flag + 0x400 + read-only + 0x00000001 + + + READY + NVMC is ready or busy + 0 + 0 + + + Busy + NVMC is busy (on-going write or erase operation) + 0 + + + Ready + NVMC is ready + 1 + + + + + + + READYNEXT + Ready flag + 0x408 + read-only + 0x00000001 + + + READYNEXT + NVMC can accept a new write operation + 0 + 0 + + + Busy + NVMC cannot accept any write operation + 0 + + + Ready + NVMC is ready + 1 + + + + + + + CONFIG + Configuration register + 0x504 + read-write + + + WEN + Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. + 0 + 1 + + + Ren + Read only access + 0 + + + Wen + Write enabled + 1 + + + Een + Erase enabled + 2 + + + + + + + ERASEPAGE + Register for erasing a page in code area + 0x508 + write-only + + + ERASEPAGE + Register for starting erase of a page in code area + 0 + 31 + + + + + ERASEPCR1 + Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE + 0x508 + write-only + ERASEPAGE + + + ERASEPCR1 + Register for erasing a page in code area, equivalent to ERASEPAGE + 0 + 31 + + + + + ERASEALL + Register for erasing all non-volatile user memory + 0x50C + write-only + + + ERASEALL + Erase all non-volatile memory including UICR registers. The erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. + 0 + 0 + + + NoOperation + No operation + 0 + + + Erase + Start chip erase + 1 + + + + + + + ERASEPCR0 + Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE + 0x510 + write-only + + + ERASEPCR0 + Register for starting erase of a page in code area, equivalent to ERASEPAGE + 0 + 31 + + + + + ERASEUICR + Register for erasing user information configuration registers + 0x514 + write-only + + + ERASEUICR + Register starting erase of all user information configuration registers. The erase must be enabled using CONFIG.WEN before the UICR can be erased. + 0 + 0 + + + NoOperation + No operation + 0 + + + Erase + Start erase of UICR + 1 + + + + + + + ERASEPAGEPARTIAL + Register for partial erase of a page in code area + 0x518 + write-only + + + ERASEPAGEPARTIAL + Register for starting partial erase of a page in code area + 0 + 31 + + + + + ERASEPAGEPARTIALCFG + Register for partial erase configuration + 0x51C + read-write + 0x0000000A + + + DURATION + Duration of the partial erase in milliseconds + 0 + 6 + + + + + ICACHECNF + I-code cache configuration register + 0x540 + read-write + 0x00000000 + + + CACHEEN + Cache enable + 0 + 0 + + + Disabled + Disable cache. Invalidates all cache entries. + 0 + + + Enabled + Enable cache + 1 + + + + + CACHEPROFEN + Cache profiling enable + 8 + 8 + + + Disabled + Disable cache profiling + 0 + + + Enabled + Enable cache profiling + 1 + + + + + + + IHIT + I-code cache hit counter + 0x548 + read-write + + + HITS + Number of cache hits. Register is writable, but only to '0'. + 0 + 31 + + + + + IMISS + I-code cache miss counter + 0x54C + read-write + + + MISSES + Number of cache misses. Register is writable, but only to '0'. + 0 + 31 + + + + + + + PPI + Programmable Peripheral Interconnect + 0x4001F000 + + 0 + 0x1000 + registers + + PPI + 0x20 + + + 6 + 0x008 + TASKS_CHG[%s] + Channel group tasks + PPI_TASKS_CHG + write-only + 0x000 + + EN + Description cluster: Enable channel group n + 0x000 + write-only + + + EN + Enable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + DIS + Description cluster: Disable channel group n + 0x004 + write-only + + + DIS + Disable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + + CHEN + Channel enable register + 0x500 + read-write + + + CH0 + Enable or disable channel 0 + 0 + 0 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH1 + Enable or disable channel 1 + 1 + 1 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH2 + Enable or disable channel 2 + 2 + 2 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH3 + Enable or disable channel 3 + 3 + 3 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH4 + Enable or disable channel 4 + 4 + 4 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH5 + Enable or disable channel 5 + 5 + 5 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH6 + Enable or disable channel 6 + 6 + 6 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH7 + Enable or disable channel 7 + 7 + 7 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH8 + Enable or disable channel 8 + 8 + 8 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH9 + Enable or disable channel 9 + 9 + 9 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH10 + Enable or disable channel 10 + 10 + 10 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH11 + Enable or disable channel 11 + 11 + 11 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH12 + Enable or disable channel 12 + 12 + 12 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH13 + Enable or disable channel 13 + 13 + 13 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH14 + Enable or disable channel 14 + 14 + 14 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH15 + Enable or disable channel 15 + 15 + 15 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH16 + Enable or disable channel 16 + 16 + 16 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH17 + Enable or disable channel 17 + 17 + 17 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH18 + Enable or disable channel 18 + 18 + 18 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH19 + Enable or disable channel 19 + 19 + 19 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH20 + Enable or disable channel 20 + 20 + 20 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH21 + Enable or disable channel 21 + 21 + 21 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH22 + Enable or disable channel 22 + 22 + 22 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH23 + Enable or disable channel 23 + 23 + 23 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH24 + Enable or disable channel 24 + 24 + 24 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH25 + Enable or disable channel 25 + 25 + 25 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH26 + Enable or disable channel 26 + 26 + 26 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH27 + Enable or disable channel 27 + 27 + 27 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH28 + Enable or disable channel 28 + 28 + 28 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH29 + Enable or disable channel 29 + 29 + 29 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH30 + Enable or disable channel 30 + 30 + 30 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH31 + Enable or disable channel 31 + 31 + 31 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + + + CHENSET + Channel enable set register + 0x504 + read-write + oneToSet + + + CH0 + Channel 0 enable set register. Writing '0' has no effect. + 0 + 0 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH1 + Channel 1 enable set register. Writing '0' has no effect. + 1 + 1 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH2 + Channel 2 enable set register. Writing '0' has no effect. + 2 + 2 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH3 + Channel 3 enable set register. Writing '0' has no effect. + 3 + 3 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH4 + Channel 4 enable set register. Writing '0' has no effect. + 4 + 4 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH5 + Channel 5 enable set register. Writing '0' has no effect. + 5 + 5 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH6 + Channel 6 enable set register. Writing '0' has no effect. + 6 + 6 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH7 + Channel 7 enable set register. Writing '0' has no effect. + 7 + 7 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH8 + Channel 8 enable set register. Writing '0' has no effect. + 8 + 8 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH9 + Channel 9 enable set register. Writing '0' has no effect. + 9 + 9 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH10 + Channel 10 enable set register. Writing '0' has no effect. + 10 + 10 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH11 + Channel 11 enable set register. Writing '0' has no effect. + 11 + 11 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH12 + Channel 12 enable set register. Writing '0' has no effect. + 12 + 12 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH13 + Channel 13 enable set register. Writing '0' has no effect. + 13 + 13 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH14 + Channel 14 enable set register. Writing '0' has no effect. + 14 + 14 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH15 + Channel 15 enable set register. Writing '0' has no effect. + 15 + 15 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH16 + Channel 16 enable set register. Writing '0' has no effect. + 16 + 16 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH17 + Channel 17 enable set register. Writing '0' has no effect. + 17 + 17 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH18 + Channel 18 enable set register. Writing '0' has no effect. + 18 + 18 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH19 + Channel 19 enable set register. Writing '0' has no effect. + 19 + 19 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH20 + Channel 20 enable set register. Writing '0' has no effect. + 20 + 20 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH21 + Channel 21 enable set register. Writing '0' has no effect. + 21 + 21 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH22 + Channel 22 enable set register. Writing '0' has no effect. + 22 + 22 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH23 + Channel 23 enable set register. Writing '0' has no effect. + 23 + 23 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH24 + Channel 24 enable set register. Writing '0' has no effect. + 24 + 24 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH25 + Channel 25 enable set register. Writing '0' has no effect. + 25 + 25 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH26 + Channel 26 enable set register. Writing '0' has no effect. + 26 + 26 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH27 + Channel 27 enable set register. Writing '0' has no effect. + 27 + 27 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH28 + Channel 28 enable set register. Writing '0' has no effect. + 28 + 28 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH29 + Channel 29 enable set register. Writing '0' has no effect. + 29 + 29 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH30 + Channel 30 enable set register. Writing '0' has no effect. + 30 + 30 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH31 + Channel 31 enable set register. Writing '0' has no effect. + 31 + 31 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + + + CHENCLR + Channel enable clear register + 0x508 + read-write + oneToClear + + + CH0 + Channel 0 enable clear register. Writing '0' has no effect. + 0 + 0 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH1 + Channel 1 enable clear register. Writing '0' has no effect. + 1 + 1 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH2 + Channel 2 enable clear register. Writing '0' has no effect. + 2 + 2 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH3 + Channel 3 enable clear register. Writing '0' has no effect. + 3 + 3 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH4 + Channel 4 enable clear register. Writing '0' has no effect. + 4 + 4 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH5 + Channel 5 enable clear register. Writing '0' has no effect. + 5 + 5 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH6 + Channel 6 enable clear register. Writing '0' has no effect. + 6 + 6 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH7 + Channel 7 enable clear register. Writing '0' has no effect. + 7 + 7 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH8 + Channel 8 enable clear register. Writing '0' has no effect. + 8 + 8 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH9 + Channel 9 enable clear register. Writing '0' has no effect. + 9 + 9 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH10 + Channel 10 enable clear register. Writing '0' has no effect. + 10 + 10 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH11 + Channel 11 enable clear register. Writing '0' has no effect. + 11 + 11 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH12 + Channel 12 enable clear register. Writing '0' has no effect. + 12 + 12 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH13 + Channel 13 enable clear register. Writing '0' has no effect. + 13 + 13 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH14 + Channel 14 enable clear register. Writing '0' has no effect. + 14 + 14 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH15 + Channel 15 enable clear register. Writing '0' has no effect. + 15 + 15 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH16 + Channel 16 enable clear register. Writing '0' has no effect. + 16 + 16 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH17 + Channel 17 enable clear register. Writing '0' has no effect. + 17 + 17 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH18 + Channel 18 enable clear register. Writing '0' has no effect. + 18 + 18 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH19 + Channel 19 enable clear register. Writing '0' has no effect. + 19 + 19 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH20 + Channel 20 enable clear register. Writing '0' has no effect. + 20 + 20 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH21 + Channel 21 enable clear register. Writing '0' has no effect. + 21 + 21 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH22 + Channel 22 enable clear register. Writing '0' has no effect. + 22 + 22 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH23 + Channel 23 enable clear register. Writing '0' has no effect. + 23 + 23 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH24 + Channel 24 enable clear register. Writing '0' has no effect. + 24 + 24 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH25 + Channel 25 enable clear register. Writing '0' has no effect. + 25 + 25 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH26 + Channel 26 enable clear register. Writing '0' has no effect. + 26 + 26 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH27 + Channel 27 enable clear register. Writing '0' has no effect. + 27 + 27 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH28 + Channel 28 enable clear register. Writing '0' has no effect. + 28 + 28 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH29 + Channel 29 enable clear register. Writing '0' has no effect. + 29 + 29 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH30 + Channel 30 enable clear register. Writing '0' has no effect. + 30 + 30 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH31 + Channel 31 enable clear register. Writing '0' has no effect. + 31 + 31 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + + + 20 + 0x008 + CH[%s] + PPI Channel + PPI_CH + read-write + 0x510 + + EEP + Description cluster: Channel n event endpoint + 0x000 + read-write + + + EEP + Pointer to event register. Accepts only addresses to registers from the Event group. + 0 + 31 + + + + + TEP + Description cluster: Channel n task endpoint + 0x004 + read-write + + + TEP + Pointer to task register. Accepts only addresses to registers from the Task group. + 0 + 31 + + + + + + 0x6 + 0x4 + CHG[%s] + Description collection: Channel group n + 0x800 + read-write + + + CH0 + Include or exclude channel 0 + 0 + 0 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH1 + Include or exclude channel 1 + 1 + 1 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH2 + Include or exclude channel 2 + 2 + 2 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH3 + Include or exclude channel 3 + 3 + 3 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH4 + Include or exclude channel 4 + 4 + 4 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH5 + Include or exclude channel 5 + 5 + 5 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH6 + Include or exclude channel 6 + 6 + 6 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH7 + Include or exclude channel 7 + 7 + 7 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH8 + Include or exclude channel 8 + 8 + 8 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH9 + Include or exclude channel 9 + 9 + 9 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH10 + Include or exclude channel 10 + 10 + 10 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH11 + Include or exclude channel 11 + 11 + 11 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH12 + Include or exclude channel 12 + 12 + 12 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH13 + Include or exclude channel 13 + 13 + 13 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH14 + Include or exclude channel 14 + 14 + 14 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH15 + Include or exclude channel 15 + 15 + 15 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH16 + Include or exclude channel 16 + 16 + 16 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH17 + Include or exclude channel 17 + 17 + 17 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH18 + Include or exclude channel 18 + 18 + 18 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH19 + Include or exclude channel 19 + 19 + 19 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH20 + Include or exclude channel 20 + 20 + 20 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH21 + Include or exclude channel 21 + 21 + 21 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH22 + Include or exclude channel 22 + 22 + 22 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH23 + Include or exclude channel 23 + 23 + 23 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH24 + Include or exclude channel 24 + 24 + 24 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH25 + Include or exclude channel 25 + 25 + 25 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH26 + Include or exclude channel 26 + 26 + 26 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH27 + Include or exclude channel 27 + 27 + 27 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH28 + Include or exclude channel 28 + 28 + 28 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH29 + Include or exclude channel 29 + 29 + 29 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH30 + Include or exclude channel 30 + 30 + 30 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH31 + Include or exclude channel 31 + 31 + 31 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + + + 32 + 0x004 + FORK[%s] + Fork + PPI_FORK + read-write + 0x910 + + TEP + Description cluster: Channel n task endpoint + 0x000 + read-write + + + TEP + Pointer to task register + 0 + 31 + + + + + + + + MWU + Memory Watch Unit + 0x40020000 + + 0 + 0x1000 + registers + + + MWU + 32 + + MWU + 0x20 + + + 4 + 0x008 + EVENTS_REGION[%s] + Peripheral events. + MWU_EVENTS_REGION + read-write + 0x100 + + WA + Description cluster: Write access to region n detected + 0x000 + read-write + + + WA + Write access to region n detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + RA + Description cluster: Read access to region n detected + 0x004 + read-write + + + RA + Read access to region n detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + + 2 + 0x008 + EVENTS_PREGION[%s] + Peripheral events. + MWU_EVENTS_PREGION + read-write + 0x160 + + WA + Description cluster: Write access to peripheral region n detected + 0x000 + read-write + + + WA + Write access to peripheral region n detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + RA + Description cluster: Read access to peripheral region n detected + 0x004 + read-write + + + RA + Read access to peripheral region n detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + REGION0WA + Enable or disable interrupt for event REGION0WA + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION0RA + Enable or disable interrupt for event REGION0RA + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION1WA + Enable or disable interrupt for event REGION1WA + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION1RA + Enable or disable interrupt for event REGION1RA + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION2WA + Enable or disable interrupt for event REGION2WA + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable 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Write '1' to enable interrupt for event REGION2RA + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION3WA + Write '1' to enable interrupt for event REGION3WA + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION3RA + Write '1' to enable interrupt for event REGION3RA + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION0WA + Write '1' to enable interrupt for event PREGION0WA + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION0RA + Write '1' to enable interrupt for event PREGION0RA + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION1WA + Write '1' to enable interrupt for event PREGION1WA + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION1RA + Write '1' to enable interrupt for event PREGION1RA + 27 + 27 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + REGION0WA + Write '1' to disable interrupt for event REGION0WA + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION0RA + Write '1' to disable interrupt for event REGION0RA + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION1WA + Write '1' to disable interrupt for event REGION1WA + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION1RA + Write '1' to disable interrupt for event REGION1RA + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION2WA + Write '1' to disable interrupt for event REGION2WA + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION2RA + Write '1' to disable interrupt for event REGION2RA + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION3WA + Write '1' to disable interrupt for event REGION3WA + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION3RA + Write '1' to disable interrupt for event REGION3RA + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION0WA + Write '1' to disable interrupt for event PREGION0WA + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION0RA + Write '1' to disable interrupt for event PREGION0RA + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION1WA + Write '1' to disable interrupt for event PREGION1WA + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION1RA + Write '1' to disable interrupt for event PREGION1RA + 27 + 27 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + NMIEN + Enable or disable interrupt + 0x320 + read-write + + + REGION0WA + Enable or disable interrupt for event REGION0WA + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION0RA + Enable or disable interrupt for event REGION0RA + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION1WA + Enable or disable interrupt for event REGION1WA + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION1RA + Enable or disable interrupt for event REGION1RA + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION2WA + Enable or disable interrupt for event REGION2WA + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION2RA + Enable or disable interrupt for event REGION2RA + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION3WA + Enable or disable interrupt for event REGION3WA + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION3RA + Enable or disable interrupt for event REGION3RA + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PREGION0WA + Enable or disable interrupt for event PREGION0WA + 24 + 24 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PREGION0RA + Enable or disable interrupt for event PREGION0RA + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PREGION1WA + Enable or disable interrupt for event PREGION1WA + 26 + 26 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PREGION1RA + Enable or disable interrupt for event PREGION1RA + 27 + 27 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + NMIENSET + Enable interrupt + 0x324 + read-write + + + REGION0WA + Write '1' to enable interrupt for event REGION0WA + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION0RA + Write '1' to enable interrupt for event REGION0RA + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION1WA + Write '1' to enable interrupt for event REGION1WA + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION1RA + Write '1' to enable interrupt for event REGION1RA + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION2WA + Write '1' to enable interrupt for event REGION2WA + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION2RA + Write '1' to enable interrupt for event REGION2RA + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION3WA + Write '1' to enable interrupt for event REGION3WA + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION3RA + Write '1' to enable interrupt for event REGION3RA + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION0WA + Write '1' to enable interrupt for event PREGION0WA + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION0RA + Write '1' to enable interrupt for event PREGION0RA + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION1WA + Write '1' to enable interrupt for event PREGION1WA + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION1RA + Write '1' to enable interrupt for event PREGION1RA + 27 + 27 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + NMIENCLR + Disable interrupt + 0x328 + read-write + + + REGION0WA + Write '1' to disable interrupt for event REGION0WA + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION0RA + Write '1' to disable interrupt for event REGION0RA + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION1WA + Write '1' to disable interrupt for event REGION1WA + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION1RA + Write '1' to disable interrupt for event REGION1RA + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION2WA + Write '1' to disable interrupt for event REGION2WA + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION2RA + Write '1' to disable interrupt for event REGION2RA + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION3WA + Write '1' to disable interrupt for event REGION3WA + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION3RA + Write '1' to disable interrupt for event REGION3RA + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION0WA + Write '1' to disable interrupt for event PREGION0WA + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION0RA + Write '1' to disable interrupt for event PREGION0RA + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION1WA + Write '1' to disable interrupt for event PREGION1WA + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION1RA + Write '1' to disable interrupt for event PREGION1RA + 27 + 27 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + 2 + 0x008 + PERREGION[%s] + Unspecified + MWU_PERREGION + read-write + 0x400 + + SUBSTATWA + Description cluster: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching + 0x000 + read-write + oneToClear + + + SR0 + Subregion 0 in region n (write '1' to clear) + 0 + 0 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR1 + Subregion 1 in region n (write '1' to clear) + 1 + 1 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR2 + Subregion 2 in region n (write '1' to clear) + 2 + 2 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR3 + Subregion 3 in region n (write '1' to clear) + 3 + 3 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR4 + Subregion 4 in region n (write '1' to clear) + 4 + 4 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR5 + Subregion 5 in region n (write '1' to clear) + 5 + 5 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR6 + Subregion 6 in region n (write '1' to clear) + 6 + 6 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR7 + Subregion 7 in region n (write '1' to clear) + 7 + 7 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR8 + Subregion 8 in region n (write '1' to clear) + 8 + 8 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR9 + Subregion 9 in region n (write '1' to clear) + 9 + 9 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR10 + Subregion 10 in region n (write '1' to clear) + 10 + 10 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR11 + Subregion 11 in region n (write '1' to clear) + 11 + 11 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR12 + Subregion 12 in region n (write '1' to clear) + 12 + 12 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR13 + Subregion 13 in region n (write '1' to clear) + 13 + 13 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR14 + Subregion 14 in region n (write '1' to clear) + 14 + 14 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR15 + Subregion 15 in region n (write '1' to clear) + 15 + 15 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR16 + Subregion 16 in region n (write '1' to clear) + 16 + 16 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR17 + Subregion 17 in region n (write '1' to clear) + 17 + 17 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR18 + Subregion 18 in region n (write '1' to clear) + 18 + 18 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR19 + Subregion 19 in region n (write '1' to clear) + 19 + 19 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR20 + Subregion 20 in region n (write '1' to clear) + 20 + 20 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR21 + Subregion 21 in region n (write '1' to clear) + 21 + 21 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR22 + Subregion 22 in region n (write '1' to clear) + 22 + 22 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR23 + Subregion 23 in region n (write '1' to clear) + 23 + 23 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR24 + Subregion 24 in region n (write '1' to clear) + 24 + 24 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR25 + Subregion 25 in region n (write '1' to clear) + 25 + 25 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR26 + Subregion 26 in region n (write '1' to clear) + 26 + 26 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR27 + Subregion 27 in region n (write '1' to clear) + 27 + 27 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR28 + Subregion 28 in region n (write '1' to clear) + 28 + 28 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR29 + Subregion 29 in region n (write '1' to clear) + 29 + 29 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR30 + Subregion 30 in region n (write '1' to clear) + 30 + 30 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR31 + Subregion 31 in region n (write '1' to clear) + 31 + 31 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + + + SUBSTATRA + Description cluster: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching + 0x004 + read-write + oneToClear + + + SR0 + Subregion 0 in region n (write '1' to clear) + 0 + 0 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR1 + Subregion 1 in region n (write '1' to clear) + 1 + 1 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR2 + Subregion 2 in region n (write '1' to clear) + 2 + 2 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR3 + Subregion 3 in region n (write '1' to clear) + 3 + 3 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR4 + Subregion 4 in region n (write '1' to clear) + 4 + 4 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR5 + Subregion 5 in region n (write '1' to clear) + 5 + 5 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR6 + Subregion 6 in region n (write '1' to clear) + 6 + 6 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR7 + Subregion 7 in region n (write '1' to clear) + 7 + 7 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR8 + Subregion 8 in region n (write '1' to clear) + 8 + 8 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR9 + Subregion 9 in region n (write '1' to clear) + 9 + 9 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR10 + Subregion 10 in region n (write '1' to clear) + 10 + 10 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR11 + Subregion 11 in region n (write '1' to clear) + 11 + 11 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR12 + Subregion 12 in region n (write '1' to clear) + 12 + 12 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR13 + Subregion 13 in region n (write '1' to clear) + 13 + 13 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR14 + Subregion 14 in region n (write '1' to clear) + 14 + 14 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR15 + Subregion 15 in region n (write '1' to clear) + 15 + 15 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR16 + Subregion 16 in region n (write '1' to clear) + 16 + 16 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR17 + Subregion 17 in region n (write '1' to clear) + 17 + 17 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR18 + Subregion 18 in region n (write '1' to clear) + 18 + 18 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR19 + Subregion 19 in region n (write '1' to clear) + 19 + 19 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR20 + Subregion 20 in region n (write '1' to clear) + 20 + 20 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR21 + Subregion 21 in region n (write '1' to clear) + 21 + 21 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR22 + Subregion 22 in region n (write '1' to clear) + 22 + 22 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR23 + Subregion 23 in region n (write '1' to clear) + 23 + 23 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR24 + Subregion 24 in region n (write '1' to clear) + 24 + 24 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR25 + Subregion 25 in region n (write '1' to clear) + 25 + 25 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR26 + Subregion 26 in region n (write '1' to clear) + 26 + 26 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR27 + Subregion 27 in region n (write '1' to clear) + 27 + 27 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR28 + Subregion 28 in region n (write '1' to clear) + 28 + 28 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR29 + Subregion 29 in region n (write '1' to clear) + 29 + 29 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR30 + Subregion 30 in region n (write '1' to clear) + 30 + 30 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR31 + Subregion 31 in region n (write '1' to clear) + 31 + 31 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + + + + REGIONEN + Enable/disable regions watch + 0x510 + read-write + + + RGN0WA + Enable/disable write access watch in region[0] + 0 + 0 + + + Disable + Disable write access watch in this region + 0 + + + Enable + Enable write access watch in this region + 1 + + + + + RGN0RA + Enable/disable read access watch in region[0] + 1 + 1 + + + Disable + Disable read access watch in this region + 0 + + + Enable + Enable read access watch in this region + 1 + + + + + RGN1WA + Enable/disable write access watch in region[1] + 2 + 2 + + + Disable + Disable write access watch in this region + 0 + + + Enable + Enable write access watch in this region + 1 + + + + + RGN1RA + Enable/disable read access watch in region[1] + 3 + 3 + + + Disable + Disable read access watch in this region + 0 + + + Enable + Enable read access watch in this region + 1 + + + + + RGN2WA + Enable/disable write access watch in region[2] + 4 + 4 + + + Disable + Disable write access watch in this region + 0 + + + Enable + Enable write access watch in this region + 1 + + + + + RGN2RA + Enable/disable read access watch in region[2] + 5 + 5 + + + Disable + Disable read access watch in this region + 0 + + + Enable + Enable read access watch in this region + 1 + + + + + RGN3WA + Enable/disable write access watch in region[3] + 6 + 6 + + + Disable + Disable write access watch in this region + 0 + + + Enable + Enable write access watch in this region + 1 + + + + + RGN3RA + Enable/disable read access watch in region[3] + 7 + 7 + + + Disable + Disable read access watch in this region + 0 + + + Enable + Enable read access watch in this region + 1 + + + + + PRGN0WA + Enable/disable write access watch in PREGION[0] + 24 + 24 + + + Disable + Disable write access watch in this PREGION + 0 + + + Enable + Enable write access watch in this PREGION + 1 + + + + + PRGN0RA + Enable/disable read access watch in PREGION[0] + 25 + 25 + + + Disable + Disable read access watch in this PREGION + 0 + + + Enable + Enable read access watch in this PREGION + 1 + + + + + PRGN1WA + Enable/disable write access watch in PREGION[1] + 26 + 26 + + + Disable + Disable write access watch in this PREGION + 0 + + + Enable + Enable write access watch in this PREGION + 1 + + + + + PRGN1RA + Enable/disable read access watch in PREGION[1] + 27 + 27 + + + Disable + Disable read access watch in this PREGION + 0 + + + Enable + Enable read access watch in this PREGION + 1 + + + + + + + REGIONENSET + Enable regions watch + 0x514 + read-write + + + RGN0WA + Enable write access watch in region[0] + 0 + 0 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Set + Enable write access watch in this region + 1 + + + + + RGN0RA + Enable read access watch in region[0] + 1 + 1 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Set + Enable read access watch in this region + 1 + + + + + RGN1WA + Enable write access watch in region[1] + 2 + 2 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Set + Enable write access watch in this region + 1 + + + + + RGN1RA + Enable read access watch in region[1] + 3 + 3 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Set + Enable read access watch in this region + 1 + + + + + RGN2WA + Enable write access watch in region[2] + 4 + 4 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Set + Enable write access watch in this region + 1 + + + + + RGN2RA + Enable read access watch in region[2] + 5 + 5 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Set + Enable read access watch in this region + 1 + + + + + RGN3WA + Enable write access watch in region[3] + 6 + 6 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Set + Enable write access watch in this region + 1 + + + + + RGN3RA + Enable read access watch in region[3] + 7 + 7 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Set + Enable read access watch in this region + 1 + + + + + PRGN0WA + Enable write access watch in PREGION[0] + 24 + 24 + + read + + Disabled + Write access watch in this PREGION is disabled + 0 + + + Enabled + Write access watch in this PREGION is enabled + 1 + + + + write + + Set + Enable write access watch in this PREGION + 1 + + + + + PRGN0RA + Enable read access watch in PREGION[0] + 25 + 25 + + read + + Disabled + Read access watch in this PREGION is disabled + 0 + + + Enabled + Read access watch in this PREGION is enabled + 1 + + + + write + + Set + Enable read access watch in this PREGION + 1 + + + + + PRGN1WA + Enable write access watch in PREGION[1] + 26 + 26 + + read + + Disabled + Write access watch in this PREGION is disabled + 0 + + + Enabled + Write access watch in this PREGION is enabled + 1 + + + + write + + Set + Enable write access watch in this PREGION + 1 + + + + + PRGN1RA + Enable read access watch in PREGION[1] + 27 + 27 + + read + + Disabled + Read access watch in this PREGION is disabled + 0 + + + Enabled + Read access watch in this PREGION is enabled + 1 + + + + write + + Set + Enable read access watch in this PREGION + 1 + + + + + + + REGIONENCLR + Disable regions watch + 0x518 + read-write + + + RGN0WA + Disable write access watch in region[0] + 0 + 0 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Clear + Disable write access watch in this region + 1 + + + + + RGN0RA + Disable read access watch in region[0] + 1 + 1 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Clear + Disable read access watch in this region + 1 + + + + + RGN1WA + Disable write access watch in region[1] + 2 + 2 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Clear + Disable write access watch in this region + 1 + + + + + RGN1RA + Disable read access watch in region[1] + 3 + 3 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Clear + Disable read access watch in this region + 1 + + + + + RGN2WA + Disable write access watch in region[2] + 4 + 4 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Clear + Disable write access watch in this region + 1 + + + + + RGN2RA + Disable read access watch in region[2] + 5 + 5 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Clear + Disable read access watch in this region + 1 + + + + + RGN3WA + Disable write access watch in region[3] + 6 + 6 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Clear + Disable write access watch in this region + 1 + + + + + RGN3RA + Disable read access watch in region[3] + 7 + 7 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Clear + Disable read access watch in this region + 1 + + + + + PRGN0WA + Disable write access watch in PREGION[0] + 24 + 24 + + read + + Disabled + Write access watch in this PREGION is disabled + 0 + + + Enabled + Write access watch in this PREGION is enabled + 1 + + + + write + + Clear + Disable write access watch in this PREGION + 1 + + + + + PRGN0RA + Disable read access watch in PREGION[0] + 25 + 25 + + read + + Disabled + Read access watch in this PREGION is disabled + 0 + + + Enabled + Read access watch in this PREGION is enabled + 1 + + + + write + + Clear + Disable read access watch in this PREGION + 1 + + + + + PRGN1WA + Disable write access watch in PREGION[1] + 26 + 26 + + read + + Disabled + Write access watch in this PREGION is disabled + 0 + + + Enabled + Write access watch in this PREGION is enabled + 1 + + + + write + + Clear + Disable write access watch in this PREGION + 1 + + + + + PRGN1RA + Disable read access watch in PREGION[1] + 27 + 27 + + read + + Disabled + Read access watch in this PREGION is disabled + 0 + + + Enabled + Read access watch in this PREGION is enabled + 1 + + + + write + + Clear + Disable read access watch in this PREGION + 1 + + + + + + + 4 + 0x010 + REGION[%s] + Unspecified + MWU_REGION + read-write + 0x600 + + START + Description cluster: Start address for region n + 0x000 + read-write + 0x00000000 + + + START + Start address for region + 0 + 31 + + + + + END + Description cluster: End address of region n + 0x004 + read-write + + + END + End address of region. + 0 + 31 + + + + + + 2 + 0x010 + PREGION[%s] + Unspecified + MWU_PREGION + read-write + 0x6C0 + + START + Description cluster: Reserved for future use + 0x000 + read-only + + + START + Reserved for future use + 0 + 31 + + + + + END + Description cluster: Reserved for future use + 0x004 + read-only + + + END + Reserved for future use + 0 + 31 + + + + + SUBS + Description cluster: Subregions of region n + 0x008 + read-write + 0x00000000 + + + SR0 + Include or exclude subregion 0 in region + 0 + 0 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR1 + Include or exclude subregion 1 in region + 1 + 1 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR2 + Include or exclude subregion 2 in region + 2 + 2 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR3 + Include or exclude subregion 3 in region + 3 + 3 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR4 + Include or exclude subregion 4 in region + 4 + 4 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR5 + Include or exclude subregion 5 in region + 5 + 5 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR6 + Include or exclude subregion 6 in region + 6 + 6 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR7 + Include or exclude subregion 7 in region + 7 + 7 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR8 + Include or exclude subregion 8 in region + 8 + 8 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR9 + Include or exclude subregion 9 in region + 9 + 9 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR10 + Include or exclude subregion 10 in region + 10 + 10 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR11 + Include or exclude subregion 11 in region + 11 + 11 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR12 + Include or exclude subregion 12 in region + 12 + 12 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR13 + Include or exclude subregion 13 in region + 13 + 13 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR14 + Include or exclude subregion 14 in region + 14 + 14 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR15 + Include or exclude subregion 15 in region + 15 + 15 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR16 + Include or exclude subregion 16 in region + 16 + 16 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR17 + Include or exclude subregion 17 in region + 17 + 17 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR18 + Include or exclude subregion 18 in region + 18 + 18 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR19 + Include or exclude subregion 19 in region + 19 + 19 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR20 + Include or exclude subregion 20 in region + 20 + 20 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR21 + Include or exclude subregion 21 in region + 21 + 21 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR22 + Include or exclude subregion 22 in region + 22 + 22 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR23 + Include or exclude subregion 23 in region + 23 + 23 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR24 + Include or exclude subregion 24 in region + 24 + 24 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR25 + Include or exclude subregion 25 in region + 25 + 25 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR26 + Include or exclude subregion 26 in region + 26 + 26 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR27 + Include or exclude subregion 27 in region + 27 + 27 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR28 + Include or exclude subregion 28 in region + 28 + 28 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR29 + Include or exclude subregion 29 in region + 29 + 29 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR30 + Include or exclude subregion 30 in region + 30 + 30 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR31 + Include or exclude subregion 31 in region + 31 + 31 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + + + + + + PWM1 + Pulse width modulation unit 1 + 0x40021000 + + PWM1 + 33 + + + + PWM2 + Pulse width modulation unit 2 + 0x40022000 + + PWM2 + 34 + + + + SPI2 + Serial Peripheral Interface 2 + 0x40023000 + + SPIM2_SPIS2_SPI2 + 35 + + + + SPIM2 + Serial Peripheral Interface Master with EasyDMA 2 + 0x40023000 + SPI2 + + SPIM2_SPIS2_SPI2 + 35 + + + + SPIS2 + SPI Slave 2 + 0x40023000 + SPI2 + + SPIM2_SPIS2_SPI2 + 35 + + + + RTC2 + Real time counter 2 + 0x40024000 + + RTC2 + 36 + + + + I2S + Inter-IC Sound + 0x40025000 + + 0 + 0x1000 + registers + + + I2S + 37 + + I2S + 0x20 + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled. + 0x000 + write-only + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. + 0x004 + write-only + + + TASKS_STOP + Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. + 0x104 + read-write + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + I2S transfer stopped. + 0x108 + read-write + + + EVENTS_STOPPED + I2S transfer stopped. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0x114 + read-write + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + RXPTRUPD + Enable or disable interrupt for event RXPTRUPD + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXPTRUPD + Enable or disable interrupt for event TXPTRUPD + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + RXPTRUPD + Write '1' to enable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXPTRUPD + Write '1' to enable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + RXPTRUPD + Write '1' to disable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXPTRUPD + Write '1' to disable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable I2S module. + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable I2S module. + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + CONFIG + Unspecified + I2S_CONFIG + read-write + 0x504 + + MODE + I2S mode. + 0x000 + read-write + 0x00000000 + + + MODE + I2S mode. + 0 + 0 + + + Master + Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. + 0 + + + Slave + Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx + 1 + + + + + + + RXEN + Reception (RX) enable. + 0x004 + read-write + 0x00000000 + + + RXEN + Reception (RX) enable. + 0 + 0 + + + Disabled + Reception disabled and now data will be written to the RXD.PTR address. + 0 + + + Enabled + Reception enabled. + 1 + + + + + + + TXEN + Transmission (TX) enable. + 0x008 + read-write + 0x00000001 + + + TXEN + Transmission (TX) enable. + 0 + 0 + + + Disabled + Transmission disabled and now data will be read from the RXD.TXD address. + 0 + + + Enabled + Transmission enabled. + 1 + + + + + + + MCKEN + Master clock generator enable. + 0x00C + read-write + 0x00000001 + + + MCKEN + Master clock generator enable. + 0 + 0 + + + Disabled + Master clock generator disabled and PSEL.MCK not connected(available as GPIO). + 0 + + + Enabled + Master clock generator running and MCK output on PSEL.MCK. + 1 + + + + + + + MCKFREQ + Master clock generator frequency. + 0x010 + read-write + 0x20000000 + + + MCKFREQ + Master clock generator frequency. + 0 + 31 + + + 32MDIV8 + 32 MHz / 8 = 4.0 MHz + 0x20000000 + + + 32MDIV10 + 32 MHz / 10 = 3.2 MHz + 0x18000000 + + + 32MDIV11 + 32 MHz / 11 = 2.9090909 MHz + 0x16000000 + + + 32MDIV15 + 32 MHz / 15 = 2.1333333 MHz + 0x11000000 + + + 32MDIV16 + 32 MHz / 16 = 2.0 MHz + 0x10000000 + + + 32MDIV21 + 32 MHz / 21 = 1.5238095 + 0x0C000000 + + + 32MDIV23 + 32 MHz / 23 = 1.3913043 MHz + 0x0B000000 + + + 32MDIV30 + 32 MHz / 30 = 1.0666667 MHz + 0x08800000 + + + 32MDIV31 + 32 MHz / 31 = 1.0322581 MHz + 0x08400000 + + + 32MDIV32 + 32 MHz / 32 = 1.0 MHz + 0x08000000 + + + 32MDIV42 + 32 MHz / 42 = 0.7619048 MHz + 0x06000000 + + + 32MDIV63 + 32 MHz / 63 = 0.5079365 MHz + 0x04100000 + + + 32MDIV125 + 32 MHz / 125 = 0.256 MHz + 0x020C0000 + + + + + + + RATIO + MCK / LRCK ratio. + 0x014 + read-write + 0x00000006 + + + RATIO + MCK / LRCK ratio. + 0 + 3 + + + 32X + LRCK = MCK / 32 + 0 + + + 48X + LRCK = MCK / 48 + 1 + + + 64X + LRCK = MCK / 64 + 2 + + + 96X + LRCK = MCK / 96 + 3 + + + 128X + LRCK = MCK / 128 + 4 + + + 192X + LRCK = MCK / 192 + 5 + + + 256X + LRCK = MCK / 256 + 6 + + + 384X + LRCK = MCK / 384 + 7 + + + 512X + LRCK = MCK / 512 + 8 + + + + + + + SWIDTH + Sample width. + 0x018 + read-write + 0x00000001 + + + SWIDTH + Sample width. + 0 + 1 + + + 8Bit + 8 bit. + 0 + + + 16Bit + 16 bit. + 1 + + + 24Bit + 24 bit. + 2 + + + + + + + ALIGN + Alignment of sample within a frame. + 0x01C + read-write + 0x00000000 + + + ALIGN + Alignment of sample within a frame. + 0 + 0 + + + Left + Left-aligned. + 0 + + + Right + Right-aligned. + 1 + + + + + + + FORMAT + Frame format. + 0x020 + read-write + 0x00000000 + + + FORMAT + Frame format. + 0 + 0 + + + I2S + Original I2S format. + 0 + + + Aligned + Alternate (left- or right-aligned) format. + 1 + + + + + + + CHANNELS + Enable channels. + 0x024 + read-write + 0x00000000 + + + CHANNELS + Enable channels. + 0 + 1 + + + Stereo + Stereo. + 0 + + + Left + Left only. + 1 + + + Right + Right only. + 2 + + + + + + + + RXD + Unspecified + I2S_RXD + read-write + 0x538 + + PTR + Receive buffer RAM start address. + 0x000 + read-write + 0x00000000 + + + PTR + Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + TXD + Unspecified + I2S_TXD + read-write + 0x540 + + PTR + Transmit buffer RAM start address. + 0x000 + read-write + 0x00000000 + + + PTR + Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + RXTXD + Unspecified + I2S_RXTXD + read-write + 0x550 + + MAXCNT + Size of RXD and TXD buffers. + 0x000 + read-write + 0x00000000 + + + MAXCNT + Size of RXD and TXD buffers in number of 32 bit words. + 0 + 13 + + + + + + PSEL + Unspecified + I2S_PSEL + read-write + 0x560 + + MCK + Pin select for MCK signal. + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SCK + Pin select for SCK signal. + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + LRCK + Pin select for LRCK signal. + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDIN + Pin select for SDIN signal. + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDOUT + Pin select for SDOUT signal. + 0x010 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + + + FPU + FPU + 0x40026000 + + 0 + 0x1000 + registers + + + FPU + 38 + + FPU + 0x20 + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + USBD + Universal serial bus device + 0x40027000 + + 0 + 0x1000 + registers + + + USBD + 39 + + USBD + 0x20 + + + 0x8 + 0x4 + TASKS_STARTEPIN[%s] + Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host + 0x004 + write-only + + + TASKS_STARTEPIN + Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTISOIN + Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint + 0x024 + write-only + + + TASKS_STARTISOIN + Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_STARTEPOUT[%s] + Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host + 0x028 + write-only + + + TASKS_STARTEPOUT + Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTISOOUT + Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint + 0x048 + write-only + + + TASKS_STARTISOOUT + Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_EP0RCVOUT + Allows OUT data stage on control endpoint 0 + 0x04C + write-only + + + TASKS_EP0RCVOUT + Allows OUT data stage on control endpoint 0 + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_EP0STATUS + Allows status stage on control endpoint 0 + 0x050 + write-only + + + TASKS_EP0STATUS + Allows status stage on control endpoint 0 + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_EP0STALL + Stalls data and status stage on control endpoint 0 + 0x054 + write-only + + + TASKS_EP0STALL + Stalls data and status stage on control endpoint 0 + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_DPDMDRIVE + Forces D+ and D- lines into the state defined in the DPDMVALUE register + 0x058 + write-only + + + TASKS_DPDMDRIVE + Forces D+ and D- lines into the state defined in the DPDMVALUE register + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_DPDMNODRIVE + Stops forcing D+ and D- lines into any state (USB engine takes control) + 0x05C + write-only + + + TASKS_DPDMNODRIVE + Stops forcing D+ and D- lines into any state (USB engine takes control) + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_USBRESET + Signals that a USB reset condition has been detected on USB lines + 0x100 + read-write + + + EVENTS_USBRESET + Signals that a USB reset condition has been detected on USB lines + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STARTED + Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register + 0x104 + read-write + + + EVENTS_STARTED + Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x8 + 0x4 + EVENTS_ENDEPIN[%s] + Description collection: The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. + 0x108 + read-write + + + EVENTS_ENDEPIN + The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_EP0DATADONE + An acknowledged data transfer has taken place on the control endpoint + 0x128 + read-write + + + EVENTS_EP0DATADONE + An acknowledged data transfer has taken place on the control endpoint + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDISOIN + The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. + 0x12C + read-write + + + EVENTS_ENDISOIN + The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x8 + 0x4 + EVENTS_ENDEPOUT[%s] + Description collection: The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. + 0x130 + read-write + + + EVENTS_ENDEPOUT + The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDISOOUT + The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. + 0x150 + read-write + + + EVENTS_ENDISOOUT + The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SOF + Signals that a SOF (start of frame) condition has been detected on USB lines + 0x154 + read-write + + + EVENTS_SOF + Signals that a SOF (start of frame) condition has been detected on USB lines + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_USBEVENT + An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. + 0x158 + read-write + + + EVENTS_USBEVENT + An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_EP0SETUP + A valid SETUP token has been received (and acknowledged) on the control endpoint + 0x15C + read-write + + + EVENTS_EP0SETUP + A valid SETUP token has been received (and acknowledged) on the control endpoint + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_EPDATA + A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register + 0x160 + read-write + + + EVENTS_EPDATA + A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + EP0DATADONE_STARTEPIN0 + Shortcut between event EP0DATADONE and task STARTEPIN[0] + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + EP0DATADONE_STARTEPOUT0 + Shortcut between event EP0DATADONE and task STARTEPOUT[0] + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + EP0DATADONE_EP0STATUS + Shortcut between event EP0DATADONE and task EP0STATUS + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ENDEPOUT0_EP0STATUS + Shortcut between event ENDEPOUT[0] and task EP0STATUS + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ENDEPOUT0_EP0RCVOUT + Shortcut between event ENDEPOUT[0] and task EP0RCVOUT + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + USBRESET + Enable or disable interrupt for event USBRESET + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STARTED + Enable or disable interrupt for event STARTED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN0 + Enable or disable interrupt for event ENDEPIN[0] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN1 + Enable or disable interrupt for event ENDEPIN[1] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN2 + Enable or disable interrupt for event ENDEPIN[2] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN3 + Enable or disable interrupt for event ENDEPIN[3] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN4 + Enable or disable interrupt for event ENDEPIN[4] + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN5 + Enable or disable interrupt for event ENDEPIN[5] + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN6 + Enable or disable interrupt for event ENDEPIN[6] + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN7 + Enable or disable interrupt for event ENDEPIN[7] + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + EP0DATADONE + Enable or disable interrupt for event EP0DATADONE + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDISOIN + Enable or disable interrupt for event ENDISOIN + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT0 + Enable or disable interrupt for event ENDEPOUT[0] + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT1 + Enable or disable interrupt for event ENDEPOUT[1] + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT2 + Enable or disable interrupt for event ENDEPOUT[2] + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT3 + Enable or disable interrupt for event ENDEPOUT[3] + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT4 + Enable or disable interrupt for event ENDEPOUT[4] + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT5 + Enable or disable interrupt for event ENDEPOUT[5] + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT6 + Enable or disable interrupt for event ENDEPOUT[6] + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT7 + Enable or disable interrupt for event ENDEPOUT[7] + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDISOOUT + Enable or disable interrupt for event ENDISOOUT + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SOF + Enable or disable interrupt for event SOF + 21 + 21 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + USBEVENT + Enable or disable interrupt for event USBEVENT + 22 + 22 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + EP0SETUP + Enable or disable interrupt for event EP0SETUP + 23 + 23 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + EPDATA + Enable or disable interrupt for event EPDATA + 24 + 24 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + USBRESET + Write '1' to enable interrupt for event USBRESET + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN0 + Write '1' to enable interrupt for event ENDEPIN[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN1 + Write '1' to enable interrupt for event ENDEPIN[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN2 + Write '1' to enable interrupt for event ENDEPIN[2] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN3 + Write '1' to enable interrupt for event ENDEPIN[3] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN4 + Write '1' to enable interrupt for event ENDEPIN[4] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN5 + Write '1' to enable interrupt for event ENDEPIN[5] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN6 + Write '1' to enable interrupt for event ENDEPIN[6] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN7 + Write '1' to enable interrupt for event ENDEPIN[7] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EP0DATADONE + Write '1' to enable interrupt for event EP0DATADONE + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDISOIN + Write '1' to enable interrupt for event ENDISOIN + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT0 + Write '1' to enable interrupt for event ENDEPOUT[0] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT1 + Write '1' to enable interrupt for event ENDEPOUT[1] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT2 + Write '1' to enable interrupt for event ENDEPOUT[2] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT3 + Write '1' to enable interrupt for event ENDEPOUT[3] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT4 + Write '1' to enable interrupt for event ENDEPOUT[4] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT5 + Write '1' to enable interrupt for event ENDEPOUT[5] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT6 + Write '1' to enable interrupt for event ENDEPOUT[6] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT7 + Write '1' to enable interrupt for event ENDEPOUT[7] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDISOOUT + Write '1' to enable interrupt for event ENDISOOUT + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SOF + Write '1' to enable interrupt for event SOF + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + USBEVENT + Write '1' to enable interrupt for event USBEVENT + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EP0SETUP + Write '1' to enable interrupt for event EP0SETUP + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EPDATA + Write '1' to enable interrupt for event EPDATA + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + USBRESET + Write '1' to disable interrupt for event USBRESET + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN0 + Write '1' to disable interrupt for event ENDEPIN[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN1 + Write '1' to disable interrupt for event ENDEPIN[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN2 + Write '1' to disable interrupt for event ENDEPIN[2] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN3 + Write '1' to disable interrupt for event ENDEPIN[3] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN4 + Write '1' to disable interrupt for event ENDEPIN[4] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN5 + Write '1' to disable interrupt for event ENDEPIN[5] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN6 + Write '1' to disable interrupt for event ENDEPIN[6] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN7 + Write '1' to disable interrupt for event ENDEPIN[7] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + EP0DATADONE + Write '1' to disable interrupt for event EP0DATADONE + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDISOIN + Write '1' to disable interrupt for event ENDISOIN + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT0 + Write '1' to disable interrupt for event ENDEPOUT[0] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT1 + Write '1' to disable interrupt for event ENDEPOUT[1] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT2 + Write '1' to disable interrupt for event ENDEPOUT[2] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT3 + Write '1' to disable interrupt for event ENDEPOUT[3] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT4 + Write '1' to disable interrupt for event ENDEPOUT[4] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT5 + Write '1' to disable interrupt for event ENDEPOUT[5] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT6 + Write '1' to disable interrupt for event ENDEPOUT[6] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT7 + Write '1' to disable interrupt for event ENDEPOUT[7] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDISOOUT + Write '1' to disable interrupt for event ENDISOOUT + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SOF + Write '1' to disable interrupt for event SOF + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + USBEVENT + Write '1' to disable interrupt for event USBEVENT + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + EP0SETUP + Write '1' to disable interrupt for event EP0SETUP + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + EPDATA + Write '1' to disable interrupt for event EPDATA + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + EVENTCAUSE + Details on what caused the USBEVENT event + 0x400 + read-write + oneToClear + + + ISOOUTCRC + CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. + 0 + 0 + + + NotDetected + No error detected + 0 + + + Detected + Error detected + 1 + + + + + SUSPEND + Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. + 8 + 8 + + + NotDetected + Suspend not detected + 0 + + + Detected + Suspend detected + 1 + + + + + RESUME + Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. + 9 + 9 + + + NotDetected + Resume not detected + 0 + + + Detected + Resume detected + 1 + + + + + USBWUALLOWED + USB MAC has been woken up and operational. Write '1' to clear. + 10 + 10 + + + NotAllowed + Wake up not allowed + 0 + + + Allowed + Wake up allowed + 1 + + + + + READY + USB device is ready for normal operation. Write '1' to clear. + 11 + 11 + + + NotDetected + USBEVENT was not issued due to USBD peripheral ready + 0 + + + Ready + USBD peripheral is ready + 1 + + + + + + + HALTED + Unspecified + USBD_HALTED + read-write + 0x420 + + 0x8 + 0x4 + EPIN[%s] + Description collection: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0x000 + read-only + + + GETSTATUS + IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0 + 15 + + + NotHalted + Endpoint is not halted + 0 + + + Halted + Endpoint is halted + 1 + + + + + + + 0x8 + 0x4 + EPOUT[%s] + Description collection: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0x024 + read-only + + + GETSTATUS + OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0 + 15 + + + NotHalted + Endpoint is not halted + 0 + + + Halted + Endpoint is halted + 1 + + + + + + + + EPSTATUS + Provides information on which endpoint's EasyDMA registers have been captured + 0x468 + read-write + oneToClear + + + EPIN0 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 0 + 0 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN1 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 1 + 1 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN2 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 2 + 2 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN3 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 3 + 3 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN4 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 4 + 4 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN5 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 5 + 5 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN6 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 6 + 6 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN7 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 7 + 7 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN8 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 8 + 8 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT0 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 16 + 16 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT1 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 17 + 17 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT2 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 18 + 18 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT3 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 19 + 19 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT4 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 20 + 20 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT5 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 21 + 21 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT6 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 22 + 22 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT7 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 23 + 23 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT8 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 24 + 24 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + + + EPDATASTATUS + Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) + 0x46C + read-write + oneToClear + + + EPIN1 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 1 + 1 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN2 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 2 + 2 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN3 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 3 + 3 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN4 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 4 + 4 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN5 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 5 + 5 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN6 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 6 + 6 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN7 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 7 + 7 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT1 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 17 + 17 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT2 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 18 + 18 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT3 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 19 + 19 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT4 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 20 + 20 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT5 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 21 + 21 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT6 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 22 + 22 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT7 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 23 + 23 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + + + USBADDR + Device USB address + 0x470 + read-only + + + ADDR + Device USB address + 0 + 6 + + + + + BMREQUESTTYPE + SETUP data, byte 0, bmRequestType + 0x480 + read-only + 0x00000000 + + + RECIPIENT + Data transfer type + 0 + 4 + + + Device + Device + 0 + + + Interface + Interface + 1 + + + Endpoint + Endpoint + 2 + + + Other + Other + 3 + + + + + TYPE + Data transfer type + 5 + 6 + + + Standard + Standard + 0 + + + Class + Class + 1 + + + Vendor + Vendor + 2 + + + + + DIRECTION + Data transfer direction + 7 + 7 + + + HostToDevice + Host-to-device + 0 + + + DeviceToHost + Device-to-host + 1 + + + + + + + BREQUEST + SETUP data, byte 1, bRequest + 0x484 + read-only + 0x00000000 + + + BREQUEST + SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values. + 0 + 7 + + + STD_GET_STATUS + Standard request GET_STATUS + 0 + + + STD_CLEAR_FEATURE + Standard request CLEAR_FEATURE + 1 + + + STD_SET_FEATURE + Standard request SET_FEATURE + 3 + + + STD_SET_ADDRESS + Standard request SET_ADDRESS + 5 + + + STD_GET_DESCRIPTOR + Standard request GET_DESCRIPTOR + 6 + + + STD_SET_DESCRIPTOR + Standard request SET_DESCRIPTOR + 7 + + + STD_GET_CONFIGURATION + Standard request GET_CONFIGURATION + 8 + + + STD_SET_CONFIGURATION + Standard request SET_CONFIGURATION + 9 + + + STD_GET_INTERFACE + Standard request GET_INTERFACE + 10 + + + STD_SET_INTERFACE + Standard request SET_INTERFACE + 11 + + + STD_SYNCH_FRAME + Standard request SYNCH_FRAME + 12 + + + + + + + WVALUEL + SETUP data, byte 2, LSB of wValue + 0x488 + read-only + 0x00000000 + + + WVALUEL + SETUP data, byte 2, LSB of wValue + 0 + 7 + + + + + WVALUEH + SETUP data, byte 3, MSB of wValue + 0x48C + read-only + 0x00000000 + + + WVALUEH + SETUP data, byte 3, MSB of wValue + 0 + 7 + + + + + WINDEXL + SETUP data, byte 4, LSB of wIndex + 0x490 + read-only + 0x00000000 + + + WINDEXL + SETUP data, byte 4, LSB of wIndex + 0 + 7 + + + + + WINDEXH + SETUP data, byte 5, MSB of wIndex + 0x494 + read-only + 0x00000000 + + + WINDEXH + SETUP data, byte 5, MSB of wIndex + 0 + 7 + + + + + WLENGTHL + SETUP data, byte 6, LSB of wLength + 0x498 + read-only + 0x00000000 + + + WLENGTHL + SETUP data, byte 6, LSB of wLength + 0 + 7 + + + + + WLENGTHH + SETUP data, byte 7, MSB of wLength + 0x49C + read-only + 0x00000000 + + + WLENGTHH + SETUP data, byte 7, MSB of wLength + 0 + 7 + + + + + SIZE + Unspecified + USBD_SIZE + read-write + 0x4A0 + + 0x8 + 0x4 + EPOUT[%s] + Description collection: Number of bytes received last in the data stage of this OUT endpoint + 0x000 + read-write + + + SIZE + Number of bytes received last in the data stage of this OUT endpoint + 0 + 6 + + + + + ISOOUT + Number of bytes received last on this ISO OUT data endpoint + 0x020 + read-only + 0x00010000 + + + SIZE + Number of bytes received last on this ISO OUT data endpoint + 0 + 9 + + + ZERO + Zero-length data packet received + 16 + 16 + + + Normal + No zero-length data received, use value in SIZE + 0 + + + ZeroData + Zero-length data received, ignore value in SIZE + 1 + + + + + + + + ENABLE + Enable USB + 0x500 + read-write + + + ENABLE + Enable USB + 0 + 0 + + + Disabled + USB peripheral is disabled + 0 + + + Enabled + USB peripheral is enabled + 1 + + + + + + + USBPULLUP + Control of the USB pull-up + 0x504 + read-write + + + CONNECT + Control of the USB pull-up on the D+ line + 0 + 0 + + + Disabled + Pull-up is disconnected + 0 + + + Enabled + Pull-up is connected to D+ + 1 + + + + + + + DPDMVALUE + State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). + 0x508 + read-write + + + STATE + State D+ and D- lines will be forced into by the DPDMDRIVE task + 0 + 4 + + + Resume + D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) + 1 + + + J + D+ forced high, D- forced low (J state) + 2 + + + K + D+ forced low, D- forced high (K state) + 4 + + + + + + + DTOGGLE + Data toggle control and status + 0x50C + read-write + 0x00000100 + + + EP + Select bulk endpoint number + 0 + 2 + + + IO + Selects IN or OUT endpoint + 7 + 7 + + + Out + Selects OUT endpoint + 0 + + + In + Selects IN endpoint + 1 + + + + + VALUE + Data toggle value + 8 + 9 + + + Nop + No action on data toggle when writing the register with this value + 0 + + + Data0 + Data toggle is DATA0 on endpoint set by EP and IO + 1 + + + Data1 + Data toggle is DATA1 on endpoint set by EP and IO + 2 + + + + + + + EPINEN + Endpoint IN enable + 0x510 + read-write + 0x00000001 + + + IN0 + Enable IN endpoint 0 + 0 + 0 + + + Disable + Disable endpoint IN 0 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 0 (response to IN tokens) + 1 + + + + + IN1 + Enable IN endpoint 1 + 1 + 1 + + + Disable + Disable endpoint IN 1 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 1 (response to IN tokens) + 1 + + + + + IN2 + Enable IN endpoint 2 + 2 + 2 + + + Disable + Disable endpoint IN 2 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 2 (response to IN tokens) + 1 + + + + + IN3 + Enable IN endpoint 3 + 3 + 3 + + + Disable + Disable endpoint IN 3 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 3 (response to IN tokens) + 1 + + + + + IN4 + Enable IN endpoint 4 + 4 + 4 + + + Disable + Disable endpoint IN 4 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 4 (response to IN tokens) + 1 + + + + + IN5 + Enable IN endpoint 5 + 5 + 5 + + + Disable + Disable endpoint IN 5 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 5 (response to IN tokens) + 1 + + + + + IN6 + Enable IN endpoint 6 + 6 + 6 + + + Disable + Disable endpoint IN 6 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 6 (response to IN tokens) + 1 + + + + + IN7 + Enable IN endpoint 7 + 7 + 7 + + + Disable + Disable endpoint IN 7 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 7 (response to IN tokens) + 1 + + + + + ISOIN + Enable ISO IN endpoint + 8 + 8 + + + Disable + Disable ISO IN endpoint 8 + 0 + + + Enable + Enable ISO IN endpoint 8 + 1 + + + + + + + EPOUTEN + Endpoint OUT enable + 0x514 + read-write + 0x00000001 + + + OUT0 + Enable OUT endpoint 0 + 0 + 0 + + + Disable + Disable endpoint OUT 0 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 0 (response to OUT tokens) + 1 + + + + + OUT1 + Enable OUT endpoint 1 + 1 + 1 + + + Disable + Disable endpoint OUT 1 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 1 (response to OUT tokens) + 1 + + + + + OUT2 + Enable OUT endpoint 2 + 2 + 2 + + + Disable + Disable endpoint OUT 2 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 2 (response to OUT tokens) + 1 + + + + + OUT3 + Enable OUT endpoint 3 + 3 + 3 + + + Disable + Disable endpoint OUT 3 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 3 (response to OUT tokens) + 1 + + + + + OUT4 + Enable OUT endpoint 4 + 4 + 4 + + + Disable + Disable endpoint OUT 4 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 4 (response to OUT tokens) + 1 + + + + + OUT5 + Enable OUT endpoint 5 + 5 + 5 + + + Disable + Disable endpoint OUT 5 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 5 (response to OUT tokens) + 1 + + + + + OUT6 + Enable OUT endpoint 6 + 6 + 6 + + + Disable + Disable endpoint OUT 6 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 6 (response to OUT tokens) + 1 + + + + + OUT7 + Enable OUT endpoint 7 + 7 + 7 + + + Disable + Disable endpoint OUT 7 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 7 (response to OUT tokens) + 1 + + + + + ISOOUT + Enable ISO OUT endpoint 8 + 8 + 8 + + + Disable + Disable ISO OUT endpoint 8 + 0 + + + Enable + Enable ISO OUT endpoint 8 + 1 + + + + + + + EPSTALL + STALL endpoints + 0x518 + write-only + 0x00000000 + modifyExternal + + + EP + Select endpoint number + 0 + 2 + + + IO + Selects IN or OUT endpoint + 7 + 7 + + + Out + Selects OUT endpoint + 0 + + + In + Selects IN endpoint + 1 + + + + + STALL + Stall selected endpoint + 8 + 8 + + + UnStall + Don't stall selected endpoint + 0 + + + Stall + Stall selected endpoint + 1 + + + + + + + ISOSPLIT + Controls the split of ISO buffers + 0x51C + read-write + + + SPLIT + Controls the split of ISO buffers + 0 + 15 + + + OneDir + Full buffer dedicated to either ISO IN or OUT + 0x0000 + + + HalfIN + Lower half for IN, upper half for OUT + 0x0080 + + + + + + + FRAMECNTR + Returns the current value of the start of frame counter + 0x520 + read-only + + + FRAMECNTR + Returns the current value of the start of frame counter + 0 + 10 + + + + + LOWPOWER + Controls USBD peripheral low power mode during USB suspend + 0x52C + read-write + 0x00000000 + + + LOWPOWER + Controls USBD peripheral low-power mode during USB suspend + 0 + 0 + + + ForceNormal + Software must write this value to exit low power mode and before performing a remote wake-up + 0 + + + LowPower + Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral + 1 + + + + + + + ISOINCONFIG + Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent + 0x530 + read-write + + + RESPONSE + Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent + 0 + 0 + + + NoResp + Endpoint does not respond in that case + 0 + + + ZeroData + Endpoint responds with a zero-length data packet in that case + 1 + + + + + + + 8 + 0x014 + EPIN[%s] + Unspecified + USBD_EPIN + read-write + 0x600 + + PTR + Description cluster: Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Description cluster: Maximum number of bytes to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes to transfer + 0 + 6 + + + + + AMOUNT + Description cluster: Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 6 + + + + + + ISOIN + Unspecified + USBD_ISOIN + read-write + 0x6A0 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes to transfer + 0 + 9 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 9 + + + + + + 8 + 0x014 + EPOUT[%s] + Unspecified + USBD_EPOUT + read-write + 0x700 + + PTR + Description cluster: Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Description cluster: Maximum number of bytes to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes to transfer + 0 + 6 + + + + + AMOUNT + Description cluster: Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 6 + + + + + + ISOOUT + Unspecified + USBD_ISOOUT + read-write + 0x7A0 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes to transfer + 0 + 9 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 9 + + + + + + + + UARTE1 + UART with EasyDMA 1 + 0x40028000 + + UARTE1 + 40 + + + + QSPI + External flash interface + 0x40029000 + + 0 + 0x1000 + registers + + + QSPI + 41 + + QSPI + 0x20 + + + TASKS_ACTIVATE + Activate QSPI interface + 0x000 + write-only + + + TASKS_ACTIVATE + Activate QSPI interface + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_READSTART + Start transfer from external flash memory to internal RAM + 0x004 + write-only + + + TASKS_READSTART + Start transfer from external flash memory to internal RAM + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_WRITESTART + Start transfer from internal RAM to external flash memory + 0x008 + write-only + + + TASKS_WRITESTART + Start transfer from internal RAM to external flash memory + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_ERASESTART + Start external flash memory erase operation + 0x00C + write-only + + + TASKS_ERASESTART + Start external flash memory erase operation + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_DEACTIVATE + Deactivate QSPI interface + 0x010 + write-only + + + TASKS_DEACTIVATE + Deactivate QSPI interface + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_READY + QSPI peripheral is ready. This event will be generated as a response to any QSPI task. + 0x100 + read-write + + + EVENTS_READY + QSPI peripheral is ready. This event will be generated as a response to any QSPI task. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable QSPI peripheral and acquire the pins selected in PSELn registers + 0x500 + read-write + + + ENABLE + Enable or disable QSPI + 0 + 0 + + + Disabled + Disable QSPI + 0 + + + Enabled + Enable QSPI + 1 + + + + + + + READ + Unspecified + QSPI_READ + read-write + 0x504 + + SRC + Flash memory source address + 0x000 + read-write + + + SRC + Word-aligned flash memory source address. + 0 + 31 + + + + + DST + RAM destination address + 0x004 + read-write + + + DST + Word-aligned RAM destination address. + 0 + 31 + + + + + CNT + Read transfer length + 0x008 + read-write + + + CNT + Read transfer length in number of bytes. The length must be a multiple of 4 bytes. + 0 + 17 + + + + + + WRITE + Unspecified + QSPI_WRITE + read-write + 0x510 + + DST + Flash destination address + 0x000 + read-write + + + DST + Word-aligned flash destination address. + 0 + 31 + + + + + SRC + RAM source address + 0x004 + read-write + + + SRC + Word-aligned RAM source address. + 0 + 31 + + + + + CNT + Write transfer length + 0x008 + read-write + + + CNT + Write transfer length in number of bytes. The length must be a multiple of 4 bytes. + 0 + 17 + + + + + + ERASE + Unspecified + QSPI_ERASE + read-write + 0x51C + + PTR + Start address of flash block to be erased + 0x000 + read-write + + + PTR + Word-aligned start address of block to be erased. + 0 + 31 + + + + + LEN + Size of block to be erased. + 0x004 + read-write + + + LEN + LEN + 0 + 1 + + + 4KB + Erase 4 kB block (flash command 0x20) + 0 + + + 64KB + Erase 64 kB block (flash command 0xD8) + 1 + + + All + Erase all (flash command 0xC7) + 2 + + + + + + + + PSEL + Unspecified + QSPI_PSEL + read-write + 0x524 + + SCK + Pin select for serial clock SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CSN + Pin select for chip select signal CSN. + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + IO0 + Pin select for serial data MOSI/IO0. + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + IO1 + Pin select for serial data MISO/IO1. + 0x010 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + IO2 + Pin select for serial data IO2. + 0x014 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + IO3 + Pin select for serial data IO3. + 0x018 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + XIPOFFSET + Address offset into the external memory for Execute in Place operation. + 0x540 + read-write + + + XIPOFFSET + Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4. + 0 + 31 + + + + + IFCONFIG0 + Interface configuration. + 0x544 + read-write + + + READOC + Configure number of data lines and opcode used for reading. + 0 + 2 + + + FASTREAD + Single data line SPI. FAST_READ (opcode 0x0B). + 0 + + + READ2O + Dual data line SPI. READ2O (opcode 0x3B). + 1 + + + READ2IO + Dual data line SPI. READ2IO (opcode 0xBB). + 2 + + + READ4O + Quad data line SPI. READ4O (opcode 0x6B). + 3 + + + READ4IO + Quad data line SPI. READ4IO (opcode 0xEB). + 4 + + + + + WRITEOC + Configure number of data lines and opcode used for writing. + 3 + 5 + + + PP + Single data line SPI. PP (opcode 0x02). + 0 + + + PP2O + Dual data line SPI. PP2O (opcode 0xA2). + 1 + + + PP4O + Quad data line SPI. PP4O (opcode 0x32). + 2 + + + PP4IO + Quad data line SPI. PP4IO (opcode 0x38). + 3 + + + + + ADDRMODE + Addressing mode. + 6 + 6 + + + 24BIT + 24-bit addressing. + 0 + + + 32BIT + 32-bit addressing. + 1 + + + + + DPMENABLE + Enable deep power-down mode (DPM) feature. + 7 + 7 + + + Disable + Disable DPM feature. + 0 + + + Enable + Enable DPM feature. + 1 + + + + + PPSIZE + Page size for commands PP, PP2O, PP4O and PP4IO. + 12 + 12 + + + 256Bytes + 256 bytes. + 0 + + + 512Bytes + 512 bytes. + 1 + + + + + + + IFCONFIG1 + Interface configuration. + 0x600 + read-write + 0x00040480 + + + SCKDELAY + Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns). + 0 + 7 + + + DPMEN + Enter/exit deep power-down mode (DPM) for external flash memory. + 24 + 24 + + + Exit + Exit DPM. + 0 + + + Enter + Enter DPM. + 1 + + + + + SPIMODE + Select SPI mode. + 25 + 25 + + + MODE0 + Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). + 0 + + + MODE3 + Mode 3: Data are captured on the clock falling edge and data is output on a rising edge. Base level of clock is 1 (CPOL=1, CPHA=1). + 1 + + + + + SCKFREQ + SCK frequency is given as 32 MHz / (SCKFREQ + 1). + 28 + 31 + + + + + STATUS + Status register. + 0x604 + read-only + + + DPM + Deep power-down mode (DPM) status of external flash. + 2 + 2 + + + Disabled + External flash is not in DPM. + 0 + + + Enabled + External flash is in DPM. + 1 + + + + + READY + Ready status. + 3 + 3 + + + READY + QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM. + 1 + + + BUSY + QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM. + 0 + + + + + SREG + Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte. + 24 + 31 + + + + + DPMDUR + Set the duration required to enter/exit deep power-down mode (DPM). + 0x614 + read-write + 0xFFFFFFFF + + + ENTER + Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns. + 0 + 15 + + + EXIT + Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns. + 16 + 31 + + + + + ADDRCONF + Extended address configuration. + 0x624 + read-write + 0x000000B7 + + + OPCODE + Opcode that enters the 32-bit addressing mode. + 0 + 7 + + + BYTE0 + Byte 0 following opcode. + 8 + 15 + + + BYTE1 + Byte 1 following byte 0. + 16 + 23 + + + MODE + Extended addressing mode. + 24 + 25 + + + NoInstr + Do not send any instruction. + 0 + + + Opcode + Send opcode. + 1 + + + OpByte0 + Send opcode, byte0. + 2 + + + All + Send opcode, byte0, byte1. + 3 + + + + + WIPWAIT + Wait for write complete before sending command. + 26 + 26 + + + Disable + No wait. + 0 + + + Enable + Wait. + 1 + + + + + WREN + Send WREN (write enable opcode 0x06) before instruction. + 27 + 27 + + + Disable + Do not send WREN. + 0 + + + Enable + Send WREN. + 1 + + + + + + + CINSTRCONF + Custom instruction configuration register. + 0x634 + read-write + 0x00002000 + + + OPCODE + Opcode of Custom instruction. + 0 + 7 + + + LENGTH + Length of custom instruction in number of bytes. + 8 + 11 + + + 1B + Send opcode only. + 1 + + + 2B + Send opcode, CINSTRDAT0.BYTE0. + 2 + + + 3B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE1. + 3 + + + 4B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE2. + 4 + + + 5B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE3. + 5 + + + 6B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE4. + 6 + + + 7B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE5. + 7 + + + 8B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE6. + 8 + + + 9B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE7. + 9 + + + + + LIO2 + Level of the IO2 pin (if connected) during transmission of custom instruction. + 12 + 12 + + + LIO3 + Level of the IO3 pin (if connected) during transmission of custom instruction. + 13 + 13 + + + WIPWAIT + Wait for write complete before sending command. + 14 + 14 + + + Disable + No wait. + 0 + + + Enable + Wait. + 1 + + + + + WREN + Send WREN (write enable opcode 0x06) before instruction. + 15 + 15 + + + Disable + Do not send WREN. + 0 + + + Enable + Send WREN. + 1 + + + + + LFEN + Enable long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field. + 16 + 16 + + + Disable + Long frame mode disabled + 0 + + + Enable + Long frame mode enabled + 1 + + + + + LFSTOP + Stop (finalize) long frame transaction + 17 + 17 + + + Stop + Stop + 1 + + + + + + + CINSTRDAT0 + Custom instruction data register 0. + 0x638 + read-write + + + BYTE0 + Data byte 0 + 0 + 7 + + + BYTE1 + Data byte 1 + 8 + 15 + + + BYTE2 + Data byte 2 + 16 + 23 + + + BYTE3 + Data byte 3 + 24 + 31 + + + + + CINSTRDAT1 + Custom instruction data register 1. + 0x63C + read-write + + + BYTE4 + Data byte 4 + 0 + 7 + + + BYTE5 + Data byte 5 + 8 + 15 + + + BYTE6 + Data byte 6 + 16 + 23 + + + BYTE7 + Data byte 7 + 24 + 31 + + + + + IFTIMING + SPI interface timing. + 0x640 + read-write + 0x00000200 + + + RXDELAY + Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. As en example, if set to 0 the input serial data is sampled on the rising edge of SCK. + 8 + 10 + + + + + + + CC_HOST_RGF + CRYPTOCELL HOST_RGF interface + 0x5002A000 + + 0 + 0x2000 + registers + + CC_HOST_RGF + 0x20 + + + HOST_CRYPTOKEY_SEL + AES hardware key select + 0x1A38 + read-write + 0x00000000 + + + HOST_CRYPTOKEY_SEL + Select the source of the HW key that is used by the AES engine + 0 + 1 + + + K_DR + Use device root key K_DR from CRYPTOCELL AO power domain + 0 + + + K_PRTL + Use hard-coded RTL key K_PRTL + 1 + + + Session + Use provided session key + 2 + + + + + + + HOST_IOT_KPRTL_LOCK + This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. + 0x1A4C + read-write + 0x00000000 + + + HOST_IOT_KPRTL_LOCK + This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. + 0 + 0 + + + Disabled + K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL + 0 + + + Enabled + K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. + 1 + + + + + + + HOST_IOT_KDR0 + This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. + 0x1A50 + read-write + 0x00000000 + + + HOST_IOT_KDR0 + Write: K_DR bits 31:0. Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain. Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain. + 0 + 31 + + + + + HOST_IOT_KDR1 + This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. + 0x1A54 + write-only + 0x00000000 + + + HOST_IOT_KDR1 + K_DR bits 63:32 + 0 + 31 + + + + + HOST_IOT_KDR2 + This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. + 0x1A58 + write-only + 0x00000000 + + + HOST_IOT_KDR2 + K_DR bits 95:64 + 0 + 31 + + + + + HOST_IOT_KDR3 + This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. + 0x1A5C + write-only + 0x00000000 + + + HOST_IOT_KDR3 + K_DR bits 127:96 + 0 + 31 + + + + + HOST_IOT_LCS + Controls lifecycle state (LCS) for CRYPTOCELL subsystem + 0x1A60 + read-write + 0x00000002 + + + LCS + Lifecycle state value. This field is write-once per reset. + 0 + 2 + + + Debug + CC310 operates in debug mode + 0 + + + Secure + CC310 operates in secure mode + 2 + + + + + LCS_IS_VALID + Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset. + 8 + 8 + + + Invalid + Valid LCS not yet retained in the CRYPTOCELL AO power domain + 0 + + + Valid + Valid LCS successfully retained in the CRYPTOCELL AO power domain + 1 + + + + + + + + + CRYPTOCELL + ARM TrustZone CryptoCell register interface + 0x5002A000 + CC_HOST_RGF + + 0 + 0x2000 + registers + + + CRYPTOCELL + 42 + + CRYPTOCELL + 0x20 + + + ENABLE + Enable CRYPTOCELL subsystem + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable the CRYPTOCELL subsystem + 0 + 0 + + + Disabled + CRYPTOCELL subsystem disabled + 0 + + + Enabled + CRYPTOCELL subsystem enabled. + 1 + + + + + + + + + PWM3 + Pulse width modulation unit 3 + 0x4002D000 + + PWM3 + 45 + + + + SPIM3 + Serial Peripheral Interface Master with EasyDMA 3 + 0x4002F000 + + SPIM3 + 47 + + + + \ No newline at end of file diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52840_bitfields.h b/bsp/boards/nrf52840_dk/sdk/nrf52840_bitfields.h similarity index 85% rename from bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52840_bitfields.h rename to bsp/boards/nrf52840_dk/sdk/nrf52840_bitfields.h index 712c25d6e5..b81d45bc53 100644 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52840_bitfields.h +++ b/bsp/boards/nrf52840_dk/sdk/nrf52840_bitfields.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. @@ -50,56 +50,64 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: AAR_TASKS_START */ /* Description: Start resolving addresses based on IRKs specified in the IRK data structure */ -/* Bit 0 : */ +/* Bit 0 : Start resolving addresses based on IRKs specified in the IRK data structure */ #define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define AAR_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: AAR_TASKS_STOP */ /* Description: Stop resolving addresses */ -/* Bit 0 : */ +/* Bit 0 : Stop resolving addresses */ #define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define AAR_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: AAR_EVENTS_END */ /* Description: Address resolution procedure complete */ -/* Bit 0 : */ +/* Bit 0 : Address resolution procedure complete */ #define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define AAR_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define AAR_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ /* Register: AAR_EVENTS_RESOLVED */ /* Description: Address resolved */ -/* Bit 0 : */ +/* Bit 0 : Address resolved */ #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */ #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESOLVED field. */ +#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0UL) /*!< Event not generated */ +#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (1UL) /*!< Event generated */ /* Register: AAR_EVENTS_NOTRESOLVED */ /* Description: Address not resolved */ -/* Bit 0 : */ +/* Bit 0 : Address not resolved */ #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */ #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTRESOLVED field. */ +#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0UL) /*!< Event not generated */ +#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (1UL) /*!< Event generated */ /* Register: AAR_INTENSET */ /* Description: Enable interrupt */ -/* Bit 2 : Write '1' to enable interrupt for NOTRESOLVED event */ +/* Bit 2 : Write '1' to enable interrupt for event NOTRESOLVED */ #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for RESOLVED event */ +/* Bit 1 : Write '1' to enable interrupt for event RESOLVED */ #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for END event */ +/* Bit 0 : Write '1' to enable interrupt for event END */ #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ @@ -109,21 +117,21 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: AAR_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 2 : Write '1' to disable interrupt for NOTRESOLVED event */ +/* Bit 2 : Write '1' to disable interrupt for event NOTRESOLVED */ #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for RESOLVED event */ +/* Bit 1 : Write '1' to disable interrupt for event RESOLVED */ #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for END event */ +/* Bit 0 : Write '1' to disable interrupt for event END */ #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ @@ -149,7 +157,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: AAR_NIRK */ /* Description: Number of IRKs */ -/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */ +/* Bits 4..0 : Number of Identity Root Keys available in the IRK data structure */ #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ @@ -170,7 +178,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: AAR_SCRATCHPTR */ /* Description: Pointer to data area used for temporary storage */ -/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */ +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. */ #define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ @@ -179,21 +187,21 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Description: Access control lists */ /* Register: ACL_ACL_ADDR */ -/* Description: Description cluster[n]: Configure the word-aligned start address of region n to protect */ +/* Description: Description cluster: Start address of region to protect. The start address must be word-aligned. */ -/* Bits 31..0 : Valid word-aligned start address of region n to protect. Address must point to a flash page boundary. */ +/* Bits 31..0 : Start address of flash region n. The start address must point to a flash page boundary. */ #define ACL_ACL_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */ #define ACL_ACL_ADDR_ADDR_Msk (0xFFFFFFFFUL << ACL_ACL_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ /* Register: ACL_ACL_SIZE */ -/* Description: Description cluster[n]: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. */ +/* Description: Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. */ -/* Bits 31..0 : Size of flash region n in bytes. Must be a multiple of the flash page size, and the maximum region size is limited to 512kB. */ +/* Bits 31..0 : Size of flash region n in bytes. Must be a multiple of the flash page size. */ #define ACL_ACL_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ #define ACL_ACL_SIZE_SIZE_Msk (0xFFFFFFFFUL << ACL_ACL_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ /* Register: ACL_ACL_PERM */ -/* Description: Description cluster[n]: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */ +/* Description: Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */ /* Bit 2 : Configure read permissions for region n. Write '0' has no effect. */ #define ACL_ACL_PERM_READ_Pos (2UL) /*!< Position of READ field. */ @@ -208,62 +216,92 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n */ +/* Peripheral: APPROTECT */ +/* Description: Access Port Protection */ + +/* Register: APPROTECT_FORCEPROTECT */ +/* Description: Software force enable APPROTECT mechanism until next reset. */ + +/* Bits 7..0 : Write 0x0 to force enable APPROTECT mechanism */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos (0UL) /*!< Position of FORCEPROTECT field. */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Msk (0xFFUL << APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos) /*!< Bit mask of FORCEPROTECT field. */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Force (0x0UL) /*!< Software force enable APPROTECT mechanism */ + +/* Register: APPROTECT_DISABLE */ +/* Description: Software disable APPROTECT mechanism */ + +/* Bits 7..0 : Software disable APPROTECT mechanism */ +#define APPROTECT_DISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */ +#define APPROTECT_DISABLE_DISABLE_Msk (0xFFUL << APPROTECT_DISABLE_DISABLE_Pos) /*!< Bit mask of DISABLE field. */ +#define APPROTECT_DISABLE_DISABLE_SwDisable (0x5AUL) /*!< Software disable APPROTECT mechanism */ + + /* Peripheral: CCM */ /* Description: AES CCM Mode Encryption */ /* Register: CCM_TASKS_KSGEN */ -/* Description: Start generation of key-stream. This operation will stop by itself when completed. */ +/* Description: Start generation of keystream. This operation will stop by itself when completed. */ -/* Bit 0 : */ +/* Bit 0 : Start generation of keystream. This operation will stop by itself when completed. */ #define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */ #define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */ +#define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */ /* Register: CCM_TASKS_CRYPT */ /* Description: Start encryption/decryption. This operation will stop by itself when completed. */ -/* Bit 0 : */ +/* Bit 0 : Start encryption/decryption. This operation will stop by itself when completed. */ #define CCM_TASKS_CRYPT_TASKS_CRYPT_Pos (0UL) /*!< Position of TASKS_CRYPT field. */ #define CCM_TASKS_CRYPT_TASKS_CRYPT_Msk (0x1UL << CCM_TASKS_CRYPT_TASKS_CRYPT_Pos) /*!< Bit mask of TASKS_CRYPT field. */ +#define CCM_TASKS_CRYPT_TASKS_CRYPT_Trigger (1UL) /*!< Trigger task */ /* Register: CCM_TASKS_STOP */ /* Description: Stop encryption/decryption */ -/* Bit 0 : */ +/* Bit 0 : Stop encryption/decryption */ #define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define CCM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: CCM_TASKS_RATEOVERRIDE */ /* Description: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ -/* Bit 0 : */ +/* Bit 0 : Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field. */ #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask of TASKS_RATEOVERRIDE field. */ +#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (1UL) /*!< Trigger task */ /* Register: CCM_EVENTS_ENDKSGEN */ -/* Description: Key-stream generation complete */ +/* Description: Keystream generation complete */ -/* Bit 0 : */ +/* Bit 0 : Keystream generation complete */ #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */ #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */ +#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */ +#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Generated (1UL) /*!< Event generated */ /* Register: CCM_EVENTS_ENDCRYPT */ /* Description: Encrypt/decrypt complete */ -/* Bit 0 : */ +/* Bit 0 : Encrypt/decrypt complete */ #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos (0UL) /*!< Position of EVENTS_ENDCRYPT field. */ #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos) /*!< Bit mask of EVENTS_ENDCRYPT field. */ +#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_NotGenerated (0UL) /*!< Event not generated */ +#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Generated (1UL) /*!< Event generated */ /* Register: CCM_EVENTS_ERROR */ /* Description: Deprecated register - CCM error event */ -/* Bit 0 : */ +/* Bit 0 : Deprecated field - CCM error event */ #define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: CCM_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */ +/* Bit 0 : Shortcut between event ENDKSGEN and task CRYPT */ #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */ @@ -272,21 +310,21 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: CCM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 2 : Write '1' to enable interrupt for ERROR event */ +/* Bit 2 : Deprecated intsetfield - Write '1' to enable interrupt for event ERROR */ #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for ENDCRYPT event */ +/* Bit 1 : Write '1' to enable interrupt for event ENDCRYPT */ #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for ENDKSGEN event */ +/* Bit 0 : Write '1' to enable interrupt for event ENDKSGEN */ #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ @@ -296,21 +334,21 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: CCM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 2 : Write '1' to disable interrupt for ERROR event */ +/* Bit 2 : Deprecated intclrfield - Write '1' to disable interrupt for event ERROR */ #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for ENDCRYPT event */ +/* Bit 1 : Write '1' to disable interrupt for event ENDCRYPT */ #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for ENDKSGEN event */ +/* Bit 0 : Write '1' to disable interrupt for event ENDKSGEN */ #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ @@ -341,8 +379,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Bit 24 : Packet length configuration */ #define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */ #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */ -#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. */ -#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. */ +#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. */ +#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. */ /* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */ #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */ @@ -382,15 +420,15 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: CCM_SCRATCHPTR */ /* Description: Pointer to data area used for temporary storage */ -/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during keystream generation, MIC generation and encryption/decryption. */ #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ /* Register: CCM_MAXPACKETSIZE */ -/* Description: Length of key-stream generated when MODE.LENGTH = Extended. */ +/* Description: Length of keystream generated when MODE.LENGTH = Extended. */ -/* Bits 7..0 : Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */ +/* Bits 7..0 : Length of keystream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */ #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */ #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */ @@ -420,9 +458,9 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Session (2UL) /*!< Use provided session key */ /* Register: CC_HOST_RGF_HOST_IOT_KPRTL_LOCK */ -/* Description: This write-once register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */ +/* Description: This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */ -/* Bit 0 : This register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */ +/* Bit 0 : This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */ #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos (0UL) /*!< Position of HOST_IOT_KPRTL_LOCK field. */ #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos) /*!< Bit mask of HOST_IOT_KPRTL_LOCK field. */ #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Disabled (0UL) /*!< K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL */ @@ -431,7 +469,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: CC_HOST_RGF_HOST_IOT_KDR0 */ /* Description: This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. */ -/* Bits 31..0 : Write: K_DR bits 31:0 Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain */ +/* Bits 31..0 : Write: K_DR bits 31:0. Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain. Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain. */ #define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos (0UL) /*!< Position of HOST_IOT_KDR0 field. */ #define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos) /*!< Bit mask of HOST_IOT_KDR0 field. */ @@ -459,11 +497,11 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: CC_HOST_RGF_HOST_IOT_LCS */ /* Description: Controls lifecycle state (LCS) for CRYPTOCELL subsystem */ -/* Bit 8 : This field is read-only and indicates if CRYPTOCELL LCS has been successfully configured since last reset */ +/* Bit 8 : Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset. */ #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos (8UL) /*!< Position of LCS_IS_VALID field. */ #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos) /*!< Bit mask of LCS_IS_VALID field. */ -#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Invalid (0UL) /*!< A valid LCS is not yet retained in the CRYPTOCELL AO power domain */ -#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Valid (1UL) /*!< A valid LCS is successfully retained in the CRYPTOCELL AO power domain */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Invalid (0UL) /*!< Valid LCS not yet retained in the CRYPTOCELL AO power domain */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Valid (1UL) /*!< Valid LCS successfully retained in the CRYPTOCELL AO power domain */ /* Bits 2..0 : Lifecycle state value. This field is write-once per reset. */ #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos (0UL) /*!< Position of LCS field. */ @@ -478,133 +516,152 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: CLOCK_TASKS_HFCLKSTART */ /* Description: Start HFXO crystal oscillator */ -/* Bit 0 : */ +/* Bit 0 : Start HFXO crystal oscillator */ #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */ #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */ +#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_HFCLKSTOP */ /* Description: Stop HFXO crystal oscillator */ -/* Bit 0 : */ +/* Bit 0 : Stop HFXO crystal oscillator */ #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */ #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */ +#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_LFCLKSTART */ /* Description: Start LFCLK */ -/* Bit 0 : */ +/* Bit 0 : Start LFCLK */ #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */ #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */ +#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_LFCLKSTOP */ /* Description: Stop LFCLK */ -/* Bit 0 : */ +/* Bit 0 : Stop LFCLK */ #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */ #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */ +#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_CAL */ /* Description: Start calibration of LFRC */ -/* Bit 0 : */ +/* Bit 0 : Start calibration of LFRC */ #define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */ #define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */ +#define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_CTSTART */ /* Description: Start calibration timer */ -/* Bit 0 : */ +/* Bit 0 : Start calibration timer */ #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos (0UL) /*!< Position of TASKS_CTSTART field. */ #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Msk (0x1UL << CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos) /*!< Bit mask of TASKS_CTSTART field. */ +#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_CTSTOP */ /* Description: Stop calibration timer */ -/* Bit 0 : */ +/* Bit 0 : Stop calibration timer */ #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos (0UL) /*!< Position of TASKS_CTSTOP field. */ #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Msk (0x1UL << CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos) /*!< Bit mask of TASKS_CTSTOP field. */ +#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_EVENTS_HFCLKSTARTED */ /* Description: HFXO crystal oscillator started */ -/* Bit 0 : */ +/* Bit 0 : HFXO crystal oscillator started */ #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */ #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */ /* Register: CLOCK_EVENTS_LFCLKSTARTED */ /* Description: LFCLK started */ -/* Bit 0 : */ +/* Bit 0 : LFCLK started */ #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */ #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */ /* Register: CLOCK_EVENTS_DONE */ /* Description: Calibration of LFRC completed */ -/* Bit 0 : */ +/* Bit 0 : Calibration of LFRC completed */ #define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ #define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ +#define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */ /* Register: CLOCK_EVENTS_CTTO */ /* Description: Calibration timer timeout */ -/* Bit 0 : */ +/* Bit 0 : Calibration timer timeout */ #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos (0UL) /*!< Position of EVENTS_CTTO field. */ #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Msk (0x1UL << CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos) /*!< Bit mask of EVENTS_CTTO field. */ +#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Generated (1UL) /*!< Event generated */ /* Register: CLOCK_EVENTS_CTSTARTED */ /* Description: Calibration timer has been started and is ready to process new tasks */ -/* Bit 0 : */ +/* Bit 0 : Calibration timer has been started and is ready to process new tasks */ #define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Pos (0UL) /*!< Position of EVENTS_CTSTARTED field. */ #define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Msk (0x1UL << CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Pos) /*!< Bit mask of EVENTS_CTSTARTED field. */ +#define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Generated (1UL) /*!< Event generated */ /* Register: CLOCK_EVENTS_CTSTOPPED */ /* Description: Calibration timer has been stopped and is ready to process new tasks */ -/* Bit 0 : */ +/* Bit 0 : Calibration timer has been stopped and is ready to process new tasks */ #define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Pos (0UL) /*!< Position of EVENTS_CTSTOPPED field. */ #define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Msk (0x1UL << CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Pos) /*!< Bit mask of EVENTS_CTSTOPPED field. */ +#define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Generated (1UL) /*!< Event generated */ /* Register: CLOCK_INTENSET */ /* Description: Enable interrupt */ -/* Bit 11 : Write '1' to enable interrupt for CTSTOPPED event */ +/* Bit 11 : Write '1' to enable interrupt for event CTSTOPPED */ #define CLOCK_INTENSET_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */ #define CLOCK_INTENSET_CTSTOPPED_Msk (0x1UL << CLOCK_INTENSET_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */ #define CLOCK_INTENSET_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENSET_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENSET_CTSTOPPED_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to enable interrupt for CTSTARTED event */ +/* Bit 10 : Write '1' to enable interrupt for event CTSTARTED */ #define CLOCK_INTENSET_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */ #define CLOCK_INTENSET_CTSTARTED_Msk (0x1UL << CLOCK_INTENSET_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */ #define CLOCK_INTENSET_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENSET_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENSET_CTSTARTED_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for CTTO event */ +/* Bit 4 : Write '1' to enable interrupt for event CTTO */ #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for DONE event */ +/* Bit 3 : Write '1' to enable interrupt for event DONE */ #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for LFCLKSTARTED event */ +/* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */ #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for HFCLKSTARTED event */ +/* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */ #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -614,42 +671,42 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: CLOCK_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 11 : Write '1' to disable interrupt for CTSTOPPED event */ +/* Bit 11 : Write '1' to disable interrupt for event CTSTOPPED */ #define CLOCK_INTENCLR_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */ #define CLOCK_INTENCLR_CTSTOPPED_Msk (0x1UL << CLOCK_INTENCLR_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */ #define CLOCK_INTENCLR_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENCLR_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENCLR_CTSTOPPED_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to disable interrupt for CTSTARTED event */ +/* Bit 10 : Write '1' to disable interrupt for event CTSTARTED */ #define CLOCK_INTENCLR_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */ #define CLOCK_INTENCLR_CTSTARTED_Msk (0x1UL << CLOCK_INTENCLR_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */ #define CLOCK_INTENCLR_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENCLR_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENCLR_CTSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for CTTO event */ +/* Bit 4 : Write '1' to disable interrupt for event CTTO */ #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for DONE event */ +/* Bit 3 : Write '1' to disable interrupt for event DONE */ #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for LFCLKSTARTED event */ +/* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */ #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for HFCLKSTARTED event */ +/* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */ #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -793,80 +850,91 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: COMP_TASKS_START */ /* Description: Start comparator */ -/* Bit 0 : */ +/* Bit 0 : Start comparator */ #define COMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define COMP_TASKS_START_TASKS_START_Msk (0x1UL << COMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define COMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: COMP_TASKS_STOP */ /* Description: Stop comparator */ -/* Bit 0 : */ +/* Bit 0 : Stop comparator */ #define COMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define COMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << COMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define COMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: COMP_TASKS_SAMPLE */ /* Description: Sample comparator value */ -/* Bit 0 : */ +/* Bit 0 : Sample comparator value */ #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ +#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */ /* Register: COMP_EVENTS_READY */ /* Description: COMP is ready and output is valid */ -/* Bit 0 : */ +/* Bit 0 : COMP is ready and output is valid */ #define COMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ #define COMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << COMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define COMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ /* Register: COMP_EVENTS_DOWN */ /* Description: Downward crossing */ -/* Bit 0 : */ +/* Bit 0 : Downward crossing */ #define COMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */ #define COMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << COMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */ +#define COMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL) /*!< Event generated */ /* Register: COMP_EVENTS_UP */ /* Description: Upward crossing */ -/* Bit 0 : */ +/* Bit 0 : Upward crossing */ #define COMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */ #define COMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << COMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */ +#define COMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_UP_EVENTS_UP_Generated (1UL) /*!< Event generated */ /* Register: COMP_EVENTS_CROSS */ /* Description: Downward or upward crossing */ -/* Bit 0 : */ +/* Bit 0 : Downward or upward crossing */ #define COMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */ #define COMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << COMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */ +#define COMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL) /*!< Event generated */ /* Register: COMP_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 4 : Shortcut between CROSS event and STOP task */ +/* Bit 4 : Shortcut between event CROSS and task STOP */ #define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ #define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ #define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between UP event and STOP task */ +/* Bit 3 : Shortcut between event UP and task STOP */ #define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ #define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ #define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between DOWN event and STOP task */ +/* Bit 2 : Shortcut between event DOWN and task STOP */ #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ #define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ #define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between READY event and STOP task */ +/* Bit 1 : Shortcut between event READY and task STOP */ #define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ #define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ #define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between READY event and SAMPLE task */ +/* Bit 0 : Shortcut between event READY and task SAMPLE */ #define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ #define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ @@ -875,25 +943,25 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: COMP_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 3 : Enable or disable interrupt for CROSS event */ +/* Bit 3 : Enable or disable interrupt for event CROSS */ #define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */ #define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */ #define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */ #define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for UP event */ +/* Bit 2 : Enable or disable interrupt for event UP */ #define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */ #define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */ #define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */ #define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for DOWN event */ +/* Bit 1 : Enable or disable interrupt for event DOWN */ #define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */ #define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */ #define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */ #define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for READY event */ +/* Bit 0 : Enable or disable interrupt for event READY */ #define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ #define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */ #define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */ @@ -902,28 +970,28 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: COMP_INTENSET */ /* Description: Enable interrupt */ -/* Bit 3 : Write '1' to enable interrupt for CROSS event */ +/* Bit 3 : Write '1' to enable interrupt for event CROSS */ #define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for UP event */ +/* Bit 2 : Write '1' to enable interrupt for event UP */ #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ #define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENSET_UP_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for DOWN event */ +/* Bit 1 : Write '1' to enable interrupt for event DOWN */ #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for READY event */ +/* Bit 0 : Write '1' to enable interrupt for event READY */ #define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -933,28 +1001,28 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: COMP_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 3 : Write '1' to disable interrupt for CROSS event */ +/* Bit 3 : Write '1' to disable interrupt for event CROSS */ #define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for UP event */ +/* Bit 2 : Write '1' to disable interrupt for event UP */ #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for DOWN event */ +/* Bit 1 : Write '1' to disable interrupt for event DOWN */ #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for READY event */ +/* Bit 0 : Write '1' to disable interrupt for event READY */ #define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -1004,7 +1072,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) */ #define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) */ #define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */ -#define COMP_REFSEL_REFSEL_ARef (5UL) /*!< VREF = AREF (VDD >= VREF >= AREFMIN) */ +#define COMP_REFSEL_REFSEL_ARef (5UL) /*!< VREF = AREF */ /* Register: COMP_EXTREFSEL */ /* Description: External reference select */ @@ -1068,7 +1136,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define CRYPTOCELL_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ #define CRYPTOCELL_ENABLE_ENABLE_Msk (0x1UL << CRYPTOCELL_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ #define CRYPTOCELL_ENABLE_ENABLE_Disabled (0UL) /*!< CRYPTOCELL subsystem disabled */ -#define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL) /*!< CRYPTOCELL subsystem enabled */ +#define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL) /*!< CRYPTOCELL subsystem enabled. */ /* Peripheral: ECB */ @@ -1077,42 +1145,48 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: ECB_TASKS_STARTECB */ /* Description: Start ECB block encrypt */ -/* Bit 0 : */ +/* Bit 0 : Start ECB block encrypt */ #define ECB_TASKS_STARTECB_TASKS_STARTECB_Pos (0UL) /*!< Position of TASKS_STARTECB field. */ #define ECB_TASKS_STARTECB_TASKS_STARTECB_Msk (0x1UL << ECB_TASKS_STARTECB_TASKS_STARTECB_Pos) /*!< Bit mask of TASKS_STARTECB field. */ +#define ECB_TASKS_STARTECB_TASKS_STARTECB_Trigger (1UL) /*!< Trigger task */ /* Register: ECB_TASKS_STOPECB */ /* Description: Abort a possible executing ECB operation */ -/* Bit 0 : */ +/* Bit 0 : Abort a possible executing ECB operation */ #define ECB_TASKS_STOPECB_TASKS_STOPECB_Pos (0UL) /*!< Position of TASKS_STOPECB field. */ #define ECB_TASKS_STOPECB_TASKS_STOPECB_Msk (0x1UL << ECB_TASKS_STOPECB_TASKS_STOPECB_Pos) /*!< Bit mask of TASKS_STOPECB field. */ +#define ECB_TASKS_STOPECB_TASKS_STOPECB_Trigger (1UL) /*!< Trigger task */ /* Register: ECB_EVENTS_ENDECB */ /* Description: ECB block encrypt complete */ -/* Bit 0 : */ +/* Bit 0 : ECB block encrypt complete */ #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos (0UL) /*!< Position of EVENTS_ENDECB field. */ #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Msk (0x1UL << ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos) /*!< Bit mask of EVENTS_ENDECB field. */ +#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_NotGenerated (0UL) /*!< Event not generated */ +#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Generated (1UL) /*!< Event generated */ /* Register: ECB_EVENTS_ERRORECB */ /* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */ -/* Bit 0 : */ +/* Bit 0 : ECB block encrypt aborted because of a STOPECB task or due to an error */ #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos (0UL) /*!< Position of EVENTS_ERRORECB field. */ #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Msk (0x1UL << ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos) /*!< Bit mask of EVENTS_ERRORECB field. */ +#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_NotGenerated (0UL) /*!< Event not generated */ +#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Generated (1UL) /*!< Event generated */ /* Register: ECB_INTENSET */ /* Description: Enable interrupt */ -/* Bit 1 : Write '1' to enable interrupt for ERRORECB event */ +/* Bit 1 : Write '1' to enable interrupt for event ERRORECB */ #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for ENDECB event */ +/* Bit 0 : Write '1' to enable interrupt for event ENDECB */ #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */ @@ -1122,14 +1196,14 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: ECB_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 1 : Write '1' to disable interrupt for ERRORECB event */ +/* Bit 1 : Write '1' to disable interrupt for event ERRORECB */ #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for ENDECB event */ +/* Bit 0 : Write '1' to disable interrupt for event ENDECB */ #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */ @@ -1145,116 +1219,119 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Peripheral: EGU */ -/* Description: Event Generator Unit 0 */ +/* Description: Event generator unit 0 */ /* Register: EGU_TASKS_TRIGGER */ -/* Description: Description collection[n]: Trigger n for triggering the corresponding TRIGGERED[n] event */ +/* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */ -/* Bit 0 : */ +/* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */ #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */ +#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */ /* Register: EGU_EVENTS_TRIGGERED */ -/* Description: Description collection[n]: Event number n generated by triggering the corresponding TRIGGER[n] task */ +/* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */ -/* Bit 0 : */ +/* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */ #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */ #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */ /* Register: EGU_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */ +/* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */ #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */ -/* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */ +/* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */ #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */ -/* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */ +/* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */ #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */ -/* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */ +/* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */ #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */ -/* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */ +/* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */ #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */ -/* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */ +/* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */ #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */ +/* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */ #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */ -/* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */ +/* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */ #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */ +/* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */ #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */ +/* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */ #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */ +/* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */ #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */ +/* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */ #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */ +/* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */ #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */ +/* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */ #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */ +/* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */ #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */ +/* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */ #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */ @@ -1263,112 +1340,112 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: EGU_INTENSET */ /* Description: Enable interrupt */ -/* Bit 15 : Write '1' to enable interrupt for TRIGGERED[15] event */ +/* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */ #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to enable interrupt for TRIGGERED[14] event */ +/* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */ #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */ -/* Bit 13 : Write '1' to enable interrupt for TRIGGERED[13] event */ +/* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */ #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to enable interrupt for TRIGGERED[12] event */ +/* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */ #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */ -/* Bit 11 : Write '1' to enable interrupt for TRIGGERED[11] event */ +/* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */ #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to enable interrupt for TRIGGERED[10] event */ +/* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */ #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for TRIGGERED[9] event */ +/* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */ #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for TRIGGERED[8] event */ +/* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */ #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for TRIGGERED[7] event */ +/* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */ #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for TRIGGERED[6] event */ +/* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */ #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for TRIGGERED[5] event */ +/* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */ #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for TRIGGERED[4] event */ +/* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */ #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for TRIGGERED[3] event */ +/* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */ #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for TRIGGERED[2] event */ +/* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */ #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for TRIGGERED[1] event */ +/* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */ #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for TRIGGERED[0] event */ +/* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */ #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ @@ -1378,112 +1455,112 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: EGU_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 15 : Write '1' to disable interrupt for TRIGGERED[15] event */ +/* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */ #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to disable interrupt for TRIGGERED[14] event */ +/* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */ #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */ -/* Bit 13 : Write '1' to disable interrupt for TRIGGERED[13] event */ +/* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */ #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to disable interrupt for TRIGGERED[12] event */ +/* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */ #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */ -/* Bit 11 : Write '1' to disable interrupt for TRIGGERED[11] event */ +/* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */ #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to disable interrupt for TRIGGERED[10] event */ +/* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */ #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for TRIGGERED[9] event */ +/* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */ #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for TRIGGERED[8] event */ +/* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */ #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for TRIGGERED[7] event */ +/* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */ #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for TRIGGERED[6] event */ +/* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */ #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for TRIGGERED[5] event */ +/* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */ #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for TRIGGERED[4] event */ +/* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */ #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for TRIGGERED[3] event */ +/* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */ #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for TRIGGERED[2] event */ +/* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */ #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for TRIGGERED[1] event */ +/* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */ #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for TRIGGERED[0] event */ +/* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */ #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ @@ -1509,21 +1586,21 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */ /* Register: FICR_DEVICEID */ -/* Description: Description collection[n]: Device identifier */ +/* Description: Description collection: Device identifier */ /* Bits 31..0 : 64 bit unique device identifier */ #define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */ #define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */ /* Register: FICR_ER */ -/* Description: Description collection[n]: Encryption root, word n */ +/* Description: Description collection: Encryption root, word n */ /* Bits 31..0 : Encryption root, word n */ #define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */ #define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */ /* Register: FICR_IR */ -/* Description: Description collection[n]: Identity Root, word n */ +/* Description: Description collection: Identity Root, word n */ /* Bits 31..0 : Identity Root, word n */ #define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */ @@ -1539,7 +1616,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */ /* Register: FICR_DEVICEADDR */ -/* Description: Description collection[n]: Device address n */ +/* Description: Description collection: Device address n */ /* Bits 31..0 : 48 bit device address */ #define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */ @@ -1551,6 +1628,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : Part code */ #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ +#define FICR_INFO_PART_PART_N52820 (0x52820UL) /*!< nRF52820 */ +#define FICR_INFO_PART_PART_N52833 (0x52833UL) /*!< nRF52833 */ #define FICR_INFO_PART_PART_N52840 (0x52840UL) /*!< nRF52840 */ #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ @@ -1564,7 +1643,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */ #define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */ #define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */ +#define FICR_INFO_VARIANT_VARIANT_AAC0 (0x41414330UL) /*!< AAC0 */ #define FICR_INFO_VARIANT_VARIANT_AACA (0x41414341UL) /*!< AACA */ +#define FICR_INFO_VARIANT_VARIANT_AAD0 (0x41414430UL) /*!< AAD0 */ +#define FICR_INFO_VARIANT_VARIANT_AAD1 (0x41414431UL) /*!< AAD1 */ +#define FICR_INFO_VARIANT_VARIANT_AADA (0x41414441UL) /*!< AADA */ +#define FICR_INFO_VARIANT_VARIANT_AAEA (0x41414541UL) /*!< AAEA */ #define FICR_INFO_VARIANT_VARIANT_BAAA (0x42414141UL) /*!< BAAA */ #define FICR_INFO_VARIANT_VARIANT_CAAA (0x43414141UL) /*!< CAAA */ #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ @@ -1575,7 +1659,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : Package option */ #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ -#define FICR_INFO_PACKAGE_PACKAGE_QI (0x2004UL) /*!< QIxx - 73-pin aQFN */ +#define FICR_INFO_PACKAGE_PACKAGE_QI (0x2004UL) /*!< QIxx - 7x7 73-pin aQFN */ +#define FICR_INFO_PACKAGE_PACKAGE_CK (0x2005UL) /*!< CKxx - 3.544 x 3.607 WLCSP */ #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_RAM */ @@ -1605,7 +1690,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_PRODTEST */ -/* Description: Description collection[n]: Production test signature n */ +/* Description: Description collection: Production test signature n */ /* Bits 31..0 : Production test signature n */ #define FICR_PRODTEST_PRODTEST_Pos (0UL) /*!< Position of PRODTEST field. */ @@ -1733,7 +1818,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */ /* Register: FICR_NFC_TAGHEADER0 */ -/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ +/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */ /* Bits 31..24 : Unique identifier byte 3 */ #define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */ @@ -1752,7 +1837,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */ /* Register: FICR_NFC_TAGHEADER1 */ -/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ +/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */ /* Bits 31..24 : Unique identifier byte 7 */ #define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */ @@ -1771,7 +1856,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */ /* Register: FICR_NFC_TAGHEADER2 */ -/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ +/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */ /* Bits 31..24 : Unique identifier byte 11 */ #define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */ @@ -1790,7 +1875,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */ /* Register: FICR_NFC_TAGHEADER3 */ -/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ +/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */ /* Bits 31..24 : Unique identifier byte 15 */ #define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */ @@ -1869,100 +1954,107 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Description: GPIO Tasks and Events */ /* Register: GPIOTE_TASKS_OUT */ -/* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ +/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ -/* Bit 0 : */ +/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */ #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */ +#define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL) /*!< Trigger task */ /* Register: GPIOTE_TASKS_SET */ -/* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ +/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ -/* Bit 0 : */ +/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */ #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */ +#define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL) /*!< Trigger task */ /* Register: GPIOTE_TASKS_CLR */ -/* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ +/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ -/* Bit 0 : */ +/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */ #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */ +#define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL) /*!< Trigger task */ /* Register: GPIOTE_EVENTS_IN */ -/* Description: Description collection[n]: Event generated from pin specified in CONFIG[n].PSEL */ +/* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */ -/* Bit 0 : */ +/* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */ #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */ #define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL) /*!< Event not generated */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL) /*!< Event generated */ /* Register: GPIOTE_EVENTS_PORT */ /* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */ -/* Bit 0 : */ +/* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */ #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */ #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL) /*!< Event not generated */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL) /*!< Event generated */ /* Register: GPIOTE_INTENSET */ /* Description: Enable interrupt */ -/* Bit 31 : Write '1' to enable interrupt for PORT event */ +/* Bit 31 : Write '1' to enable interrupt for event PORT */ #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for IN[7] event */ +/* Bit 7 : Write '1' to enable interrupt for event IN[7] */ #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */ #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */ #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for IN[6] event */ +/* Bit 6 : Write '1' to enable interrupt for event IN[6] */ #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */ #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */ #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for IN[5] event */ +/* Bit 5 : Write '1' to enable interrupt for event IN[5] */ #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */ #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */ #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for IN[4] event */ +/* Bit 4 : Write '1' to enable interrupt for event IN[4] */ #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */ #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */ #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for IN[3] event */ +/* Bit 3 : Write '1' to enable interrupt for event IN[3] */ #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for IN[2] event */ +/* Bit 2 : Write '1' to enable interrupt for event IN[2] */ #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for IN[1] event */ +/* Bit 1 : Write '1' to enable interrupt for event IN[1] */ #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for IN[0] event */ +/* Bit 0 : Write '1' to enable interrupt for event IN[0] */ #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */ @@ -1972,63 +2064,63 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: GPIOTE_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 31 : Write '1' to disable interrupt for PORT event */ +/* Bit 31 : Write '1' to disable interrupt for event PORT */ #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for IN[7] event */ +/* Bit 7 : Write '1' to disable interrupt for event IN[7] */ #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */ #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */ #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for IN[6] event */ +/* Bit 6 : Write '1' to disable interrupt for event IN[6] */ #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */ #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */ #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for IN[5] event */ +/* Bit 5 : Write '1' to disable interrupt for event IN[5] */ #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */ #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */ #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for IN[4] event */ +/* Bit 4 : Write '1' to disable interrupt for event IN[4] */ #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */ #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */ #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for IN[3] event */ +/* Bit 3 : Write '1' to disable interrupt for event IN[3] */ #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for IN[2] event */ +/* Bit 2 : Write '1' to disable interrupt for event IN[2] */ #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for IN[1] event */ +/* Bit 1 : Write '1' to disable interrupt for event IN[1] */ #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for IN[0] event */ +/* Bit 0 : Write '1' to disable interrupt for event IN[0] */ #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */ @@ -2036,7 +2128,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ /* Register: GPIOTE_CONFIG */ -/* Description: Description collection[n]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */ +/* Description: Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */ /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */ #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ @@ -2056,7 +2148,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define GPIOTE_CONFIG_PORT_Pos (13UL) /*!< Position of PORT field. */ #define GPIOTE_CONFIG_PORT_Msk (0x1UL << GPIOTE_CONFIG_PORT_Pos) /*!< Bit mask of PORT field. */ -/* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */ +/* Bits 12..8 : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event */ #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ @@ -2074,56 +2166,66 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: I2S_TASKS_START */ /* Description: Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */ -/* Bit 0 : */ +/* Bit 0 : Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */ #define I2S_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define I2S_TASKS_START_TASKS_START_Msk (0x1UL << I2S_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define I2S_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: I2S_TASKS_STOP */ -/* Description: Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the {event:STOPPED} event to be generated. */ +/* Description: Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */ -/* Bit 0 : */ +/* Bit 0 : Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */ #define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define I2S_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: I2S_EVENTS_RXPTRUPD */ /* Description: The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */ -/* Bit 0 : */ +/* Bit 0 : The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */ #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL) /*!< Position of EVENTS_RXPTRUPD field. */ #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos) /*!< Bit mask of EVENTS_RXPTRUPD field. */ +#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0UL) /*!< Event not generated */ +#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (1UL) /*!< Event generated */ /* Register: I2S_EVENTS_STOPPED */ /* Description: I2S transfer stopped. */ -/* Bit 0 : */ +/* Bit 0 : I2S transfer stopped. */ #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: I2S_EVENTS_TXPTRUPD */ /* Description: The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */ -/* Bit 0 : */ +/* Bit 0 : The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */ #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL) /*!< Position of EVENTS_TXPTRUPD field. */ #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos) /*!< Bit mask of EVENTS_TXPTRUPD field. */ +#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0UL) /*!< Event not generated */ +#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (1UL) /*!< Event generated */ /* Register: I2S_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 5 : Enable or disable interrupt for TXPTRUPD event */ +/* Bit 5 : Enable or disable interrupt for event TXPTRUPD */ #define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ #define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ #define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */ #define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for STOPPED event */ +/* Bit 2 : Enable or disable interrupt for event STOPPED */ #define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ #define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ #define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for RXPTRUPD event */ +/* Bit 1 : Enable or disable interrupt for event RXPTRUPD */ #define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ #define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ #define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */ @@ -2132,21 +2234,21 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: I2S_INTENSET */ /* Description: Enable interrupt */ -/* Bit 5 : Write '1' to enable interrupt for TXPTRUPD event */ +/* Bit 5 : Write '1' to enable interrupt for event TXPTRUPD */ #define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ #define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ #define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ #define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 2 : Write '1' to enable interrupt for event STOPPED */ #define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for RXPTRUPD event */ +/* Bit 1 : Write '1' to enable interrupt for event RXPTRUPD */ #define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ #define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ @@ -2156,21 +2258,21 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: I2S_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 5 : Write '1' to disable interrupt for TXPTRUPD event */ +/* Bit 5 : Write '1' to disable interrupt for event TXPTRUPD */ #define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ #define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ #define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 2 : Write '1' to disable interrupt for event STOPPED */ #define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for RXPTRUPD event */ +/* Bit 1 : Write '1' to disable interrupt for event RXPTRUPD */ #define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ #define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ @@ -2241,11 +2343,6 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */ #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */ #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */ /* Register: I2S_CONFIG_RATIO */ /* Description: MCK / LRCK ratio. */ @@ -2409,85 +2506,96 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Peripheral: LPCOMP */ -/* Description: Low Power Comparator */ +/* Description: Low-power comparator */ /* Register: LPCOMP_TASKS_START */ /* Description: Start comparator */ -/* Bit 0 : */ +/* Bit 0 : Start comparator */ #define LPCOMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define LPCOMP_TASKS_START_TASKS_START_Msk (0x1UL << LPCOMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define LPCOMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: LPCOMP_TASKS_STOP */ /* Description: Stop comparator */ -/* Bit 0 : */ +/* Bit 0 : Stop comparator */ #define LPCOMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define LPCOMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << LPCOMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define LPCOMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: LPCOMP_TASKS_SAMPLE */ /* Description: Sample comparator value */ -/* Bit 0 : */ +/* Bit 0 : Sample comparator value */ #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ +#define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */ /* Register: LPCOMP_EVENTS_READY */ /* Description: LPCOMP is ready and output is valid */ -/* Bit 0 : */ +/* Bit 0 : LPCOMP is ready and output is valid */ #define LPCOMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ #define LPCOMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << LPCOMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define LPCOMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define LPCOMP_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ /* Register: LPCOMP_EVENTS_DOWN */ /* Description: Downward crossing */ -/* Bit 0 : */ +/* Bit 0 : Downward crossing */ #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */ #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */ +#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL) /*!< Event not generated */ +#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL) /*!< Event generated */ /* Register: LPCOMP_EVENTS_UP */ /* Description: Upward crossing */ -/* Bit 0 : */ +/* Bit 0 : Upward crossing */ #define LPCOMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */ #define LPCOMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << LPCOMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */ +#define LPCOMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL) /*!< Event not generated */ +#define LPCOMP_EVENTS_UP_EVENTS_UP_Generated (1UL) /*!< Event generated */ /* Register: LPCOMP_EVENTS_CROSS */ /* Description: Downward or upward crossing */ -/* Bit 0 : */ +/* Bit 0 : Downward or upward crossing */ #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */ #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */ +#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL) /*!< Event not generated */ +#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL) /*!< Event generated */ /* Register: LPCOMP_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 4 : Shortcut between CROSS event and STOP task */ +/* Bit 4 : Shortcut between event CROSS and task STOP */ #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between UP event and STOP task */ +/* Bit 3 : Shortcut between event UP and task STOP */ #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between DOWN event and STOP task */ +/* Bit 2 : Shortcut between event DOWN and task STOP */ #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between READY event and STOP task */ +/* Bit 1 : Shortcut between event READY and task STOP */ #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between READY event and SAMPLE task */ +/* Bit 0 : Shortcut between event READY and task SAMPLE */ #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ @@ -2496,28 +2604,28 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: LPCOMP_INTENSET */ /* Description: Enable interrupt */ -/* Bit 3 : Write '1' to enable interrupt for CROSS event */ +/* Bit 3 : Write '1' to enable interrupt for event CROSS */ #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for UP event */ +/* Bit 2 : Write '1' to enable interrupt for event UP */ #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for DOWN event */ +/* Bit 1 : Write '1' to enable interrupt for event DOWN */ #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for READY event */ +/* Bit 0 : Write '1' to enable interrupt for event READY */ #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -2527,28 +2635,28 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: LPCOMP_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 3 : Write '1' to disable interrupt for CROSS event */ +/* Bit 3 : Write '1' to disable interrupt for event CROSS */ #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for UP event */ +/* Bit 2 : Write '1' to disable interrupt for event UP */ #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for DOWN event */ +/* Bit 1 : Write '1' to disable interrupt for event DOWN */ #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for READY event */ +/* Bit 0 : Write '1' to disable interrupt for event READY */ #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -2561,8 +2669,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Result of last compare. Decision point SAMPLE task. */ #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ -#define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ < VIN-). */ -#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ > VIN-). */ +#define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ < VIN-) */ +#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ > VIN-) */ /* Register: LPCOMP_ENABLE */ /* Description: Enable LPCOMP */ @@ -2644,103 +2752,111 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Description: Memory Watch Unit */ /* Register: MWU_EVENTS_REGION_WA */ -/* Description: Description cluster[n]: Write access to region n detected */ +/* Description: Description cluster: Write access to region n detected */ -/* Bit 0 : */ +/* Bit 0 : Write access to region n detected */ #define MWU_EVENTS_REGION_WA_WA_Pos (0UL) /*!< Position of WA field. */ #define MWU_EVENTS_REGION_WA_WA_Msk (0x1UL << MWU_EVENTS_REGION_WA_WA_Pos) /*!< Bit mask of WA field. */ +#define MWU_EVENTS_REGION_WA_WA_NotGenerated (0UL) /*!< Event not generated */ +#define MWU_EVENTS_REGION_WA_WA_Generated (1UL) /*!< Event generated */ /* Register: MWU_EVENTS_REGION_RA */ -/* Description: Description cluster[n]: Read access to region n detected */ +/* Description: Description cluster: Read access to region n detected */ -/* Bit 0 : */ +/* Bit 0 : Read access to region n detected */ #define MWU_EVENTS_REGION_RA_RA_Pos (0UL) /*!< Position of RA field. */ #define MWU_EVENTS_REGION_RA_RA_Msk (0x1UL << MWU_EVENTS_REGION_RA_RA_Pos) /*!< Bit mask of RA field. */ +#define MWU_EVENTS_REGION_RA_RA_NotGenerated (0UL) /*!< Event not generated */ +#define MWU_EVENTS_REGION_RA_RA_Generated (1UL) /*!< Event generated */ /* Register: MWU_EVENTS_PREGION_WA */ -/* Description: Description cluster[n]: Write access to peripheral region n detected */ +/* Description: Description cluster: Write access to peripheral region n detected */ -/* Bit 0 : */ +/* Bit 0 : Write access to peripheral region n detected */ #define MWU_EVENTS_PREGION_WA_WA_Pos (0UL) /*!< Position of WA field. */ #define MWU_EVENTS_PREGION_WA_WA_Msk (0x1UL << MWU_EVENTS_PREGION_WA_WA_Pos) /*!< Bit mask of WA field. */ +#define MWU_EVENTS_PREGION_WA_WA_NotGenerated (0UL) /*!< Event not generated */ +#define MWU_EVENTS_PREGION_WA_WA_Generated (1UL) /*!< Event generated */ /* Register: MWU_EVENTS_PREGION_RA */ -/* Description: Description cluster[n]: Read access to peripheral region n detected */ +/* Description: Description cluster: Read access to peripheral region n detected */ -/* Bit 0 : */ +/* Bit 0 : Read access to peripheral region n detected */ #define MWU_EVENTS_PREGION_RA_RA_Pos (0UL) /*!< Position of RA field. */ #define MWU_EVENTS_PREGION_RA_RA_Msk (0x1UL << MWU_EVENTS_PREGION_RA_RA_Pos) /*!< Bit mask of RA field. */ +#define MWU_EVENTS_PREGION_RA_RA_NotGenerated (0UL) /*!< Event not generated */ +#define MWU_EVENTS_PREGION_RA_RA_Generated (1UL) /*!< Event generated */ /* Register: MWU_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */ +/* Bit 27 : Enable or disable interrupt for event PREGION1RA */ #define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */ -/* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */ +/* Bit 26 : Enable or disable interrupt for event PREGION1WA */ #define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */ -/* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */ +/* Bit 25 : Enable or disable interrupt for event PREGION0RA */ #define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */ -/* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */ +/* Bit 24 : Enable or disable interrupt for event PREGION0WA */ #define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for REGION[3].RA event */ +/* Bit 7 : Enable or disable interrupt for event REGION3RA */ #define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for REGION[3].WA event */ +/* Bit 6 : Enable or disable interrupt for event REGION3WA */ #define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for REGION[2].RA event */ +/* Bit 5 : Enable or disable interrupt for event REGION2RA */ #define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for REGION[2].WA event */ +/* Bit 4 : Enable or disable interrupt for event REGION2WA */ #define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for REGION[1].RA event */ +/* Bit 3 : Enable or disable interrupt for event REGION1RA */ #define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for REGION[1].WA event */ +/* Bit 2 : Enable or disable interrupt for event REGION1WA */ #define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for REGION[0].RA event */ +/* Bit 1 : Enable or disable interrupt for event REGION0RA */ #define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for REGION[0].WA event */ +/* Bit 0 : Enable or disable interrupt for event REGION0WA */ #define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */ @@ -2749,84 +2865,84 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: MWU_INTENSET */ /* Description: Enable interrupt */ -/* Bit 27 : Write '1' to enable interrupt for PREGION[1].RA event */ +/* Bit 27 : Write '1' to enable interrupt for event PREGION1RA */ #define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */ -/* Bit 26 : Write '1' to enable interrupt for PREGION[1].WA event */ +/* Bit 26 : Write '1' to enable interrupt for event PREGION1WA */ #define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */ -/* Bit 25 : Write '1' to enable interrupt for PREGION[0].RA event */ +/* Bit 25 : Write '1' to enable interrupt for event PREGION0RA */ #define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */ -/* Bit 24 : Write '1' to enable interrupt for PREGION[0].WA event */ +/* Bit 24 : Write '1' to enable interrupt for event PREGION0WA */ #define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for REGION[3].RA event */ +/* Bit 7 : Write '1' to enable interrupt for event REGION3RA */ #define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for REGION[3].WA event */ +/* Bit 6 : Write '1' to enable interrupt for event REGION3WA */ #define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for REGION[2].RA event */ +/* Bit 5 : Write '1' to enable interrupt for event REGION2RA */ #define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for REGION[2].WA event */ +/* Bit 4 : Write '1' to enable interrupt for event REGION2WA */ #define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for REGION[1].RA event */ +/* Bit 3 : Write '1' to enable interrupt for event REGION1RA */ #define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for REGION[1].WA event */ +/* Bit 2 : Write '1' to enable interrupt for event REGION1WA */ #define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for REGION[0].RA event */ +/* Bit 1 : Write '1' to enable interrupt for event REGION0RA */ #define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for REGION[0].WA event */ +/* Bit 0 : Write '1' to enable interrupt for event REGION0WA */ #define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ @@ -2836,84 +2952,84 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: MWU_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 27 : Write '1' to disable interrupt for PREGION[1].RA event */ +/* Bit 27 : Write '1' to disable interrupt for event PREGION1RA */ #define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ -/* Bit 26 : Write '1' to disable interrupt for PREGION[1].WA event */ +/* Bit 26 : Write '1' to disable interrupt for event PREGION1WA */ #define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ -/* Bit 25 : Write '1' to disable interrupt for PREGION[0].RA event */ +/* Bit 25 : Write '1' to disable interrupt for event PREGION0RA */ #define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ -/* Bit 24 : Write '1' to disable interrupt for PREGION[0].WA event */ +/* Bit 24 : Write '1' to disable interrupt for event PREGION0WA */ #define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for REGION[3].RA event */ +/* Bit 7 : Write '1' to disable interrupt for event REGION3RA */ #define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for REGION[3].WA event */ +/* Bit 6 : Write '1' to disable interrupt for event REGION3WA */ #define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for REGION[2].RA event */ +/* Bit 5 : Write '1' to disable interrupt for event REGION2RA */ #define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for REGION[2].WA event */ +/* Bit 4 : Write '1' to disable interrupt for event REGION2WA */ #define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for REGION[1].RA event */ +/* Bit 3 : Write '1' to disable interrupt for event REGION1RA */ #define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for REGION[1].WA event */ +/* Bit 2 : Write '1' to disable interrupt for event REGION1WA */ #define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for REGION[0].RA event */ +/* Bit 1 : Write '1' to disable interrupt for event REGION0RA */ #define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for REGION[0].WA event */ +/* Bit 0 : Write '1' to disable interrupt for event REGION0WA */ #define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ @@ -2921,161 +3037,161 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */ /* Register: MWU_NMIEN */ -/* Description: Enable or disable non-maskable interrupt */ +/* Description: Enable or disable interrupt */ -/* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */ +/* Bit 27 : Enable or disable interrupt for event PREGION1RA */ #define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */ -/* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */ +/* Bit 26 : Enable or disable interrupt for event PREGION1WA */ #define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */ -/* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */ +/* Bit 25 : Enable or disable interrupt for event PREGION0RA */ #define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */ -/* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */ +/* Bit 24 : Enable or disable interrupt for event PREGION0WA */ #define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */ +/* Bit 7 : Enable or disable interrupt for event REGION3RA */ #define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */ +/* Bit 6 : Enable or disable interrupt for event REGION3WA */ #define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */ +/* Bit 5 : Enable or disable interrupt for event REGION2RA */ #define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */ +/* Bit 4 : Enable or disable interrupt for event REGION2WA */ #define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */ +/* Bit 3 : Enable or disable interrupt for event REGION1RA */ #define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */ +/* Bit 2 : Enable or disable interrupt for event REGION1WA */ #define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */ +/* Bit 1 : Enable or disable interrupt for event REGION0RA */ #define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */ +/* Bit 0 : Enable or disable interrupt for event REGION0WA */ #define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */ /* Register: MWU_NMIENSET */ -/* Description: Enable non-maskable interrupt */ +/* Description: Enable interrupt */ -/* Bit 27 : Write '1' to enable non-maskable interrupt for PREGION[1].RA event */ +/* Bit 27 : Write '1' to enable interrupt for event PREGION1RA */ #define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */ -/* Bit 26 : Write '1' to enable non-maskable interrupt for PREGION[1].WA event */ +/* Bit 26 : Write '1' to enable interrupt for event PREGION1WA */ #define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */ -/* Bit 25 : Write '1' to enable non-maskable interrupt for PREGION[0].RA event */ +/* Bit 25 : Write '1' to enable interrupt for event PREGION0RA */ #define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */ -/* Bit 24 : Write '1' to enable non-maskable interrupt for PREGION[0].WA event */ +/* Bit 24 : Write '1' to enable interrupt for event PREGION0WA */ #define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable non-maskable interrupt for REGION[3].RA event */ +/* Bit 7 : Write '1' to enable interrupt for event REGION3RA */ #define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable non-maskable interrupt for REGION[3].WA event */ +/* Bit 6 : Write '1' to enable interrupt for event REGION3WA */ #define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable non-maskable interrupt for REGION[2].RA event */ +/* Bit 5 : Write '1' to enable interrupt for event REGION2RA */ #define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable non-maskable interrupt for REGION[2].WA event */ +/* Bit 4 : Write '1' to enable interrupt for event REGION2WA */ #define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable non-maskable interrupt for REGION[1].RA event */ +/* Bit 3 : Write '1' to enable interrupt for event REGION1RA */ #define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable non-maskable interrupt for REGION[1].WA event */ +/* Bit 2 : Write '1' to enable interrupt for event REGION1WA */ #define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable non-maskable interrupt for REGION[0].RA event */ +/* Bit 1 : Write '1' to enable interrupt for event REGION0RA */ #define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable non-maskable interrupt for REGION[0].WA event */ +/* Bit 0 : Write '1' to enable interrupt for event REGION0WA */ #define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ @@ -3083,86 +3199,86 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */ /* Register: MWU_NMIENCLR */ -/* Description: Disable non-maskable interrupt */ +/* Description: Disable interrupt */ -/* Bit 27 : Write '1' to disable non-maskable interrupt for PREGION[1].RA event */ +/* Bit 27 : Write '1' to disable interrupt for event PREGION1RA */ #define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ -/* Bit 26 : Write '1' to disable non-maskable interrupt for PREGION[1].WA event */ +/* Bit 26 : Write '1' to disable interrupt for event PREGION1WA */ #define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ -/* Bit 25 : Write '1' to disable non-maskable interrupt for PREGION[0].RA event */ +/* Bit 25 : Write '1' to disable interrupt for event PREGION0RA */ #define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ -/* Bit 24 : Write '1' to disable non-maskable interrupt for PREGION[0].WA event */ +/* Bit 24 : Write '1' to disable interrupt for event PREGION0WA */ #define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable non-maskable interrupt for REGION[3].RA event */ +/* Bit 7 : Write '1' to disable interrupt for event REGION3RA */ #define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable non-maskable interrupt for REGION[3].WA event */ +/* Bit 6 : Write '1' to disable interrupt for event REGION3WA */ #define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable non-maskable interrupt for REGION[2].RA event */ +/* Bit 5 : Write '1' to disable interrupt for event REGION2RA */ #define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable non-maskable interrupt for REGION[2].WA event */ +/* Bit 4 : Write '1' to disable interrupt for event REGION2WA */ #define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable non-maskable interrupt for REGION[1].RA event */ +/* Bit 3 : Write '1' to disable interrupt for event REGION1RA */ #define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable non-maskable interrupt for REGION[1].WA event */ +/* Bit 2 : Write '1' to disable interrupt for event REGION1WA */ #define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable non-maskable interrupt for REGION[0].RA event */ +/* Bit 1 : Write '1' to disable interrupt for event REGION0RA */ #define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable non-maskable interrupt for REGION[0].WA event */ +/* Bit 0 : Write '1' to disable interrupt for event REGION0WA */ #define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ @@ -3170,7 +3286,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */ /* Register: MWU_PERREGION_SUBSTATWA */ -/* Description: Description cluster[n]: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching */ +/* Description: Description cluster: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching */ /* Bit 31 : Subregion 31 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */ @@ -3365,7 +3481,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */ /* Register: MWU_PERREGION_SUBSTATRA */ -/* Description: Description cluster[n]: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching */ +/* Description: Description cluster: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching */ /* Bit 31 : Subregion 31 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */ @@ -3809,35 +3925,35 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */ /* Register: MWU_REGION_START */ -/* Description: Description cluster[n]: Start address for region n */ +/* Description: Description cluster: Start address for region n */ /* Bits 31..0 : Start address for region */ #define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */ #define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */ /* Register: MWU_REGION_END */ -/* Description: Description cluster[n]: End address of region n */ +/* Description: Description cluster: End address of region n */ /* Bits 31..0 : End address of region. */ #define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */ #define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */ /* Register: MWU_PREGION_START */ -/* Description: Description cluster[n]: Reserved for future use */ +/* Description: Description cluster: Reserved for future use */ /* Bits 31..0 : Reserved for future use */ #define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */ #define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */ /* Register: MWU_PREGION_END */ -/* Description: Description cluster[n]: Reserved for future use */ +/* Description: Description cluster: Reserved for future use */ /* Bits 31..0 : Reserved for future use */ #define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */ #define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */ /* Register: MWU_PREGION_SUBS */ -/* Description: Description cluster[n]: Subregions of region n */ +/* Description: Description cluster: Subregions of region n */ /* Bit 31 : Include or exclude subregion 31 in region */ #define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */ @@ -4038,173 +4154,210 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: NFCT_TASKS_ACTIVATE */ /* Description: Activate NFCT peripheral for incoming and outgoing frames, change state to activated */ -/* Bit 0 : */ +/* Bit 0 : Activate NFCT peripheral for incoming and outgoing frames, change state to activated */ #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL) /*!< Position of TASKS_ACTIVATE field. */ #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos) /*!< Bit mask of TASKS_ACTIVATE field. */ +#define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Trigger (1UL) /*!< Trigger task */ /* Register: NFCT_TASKS_DISABLE */ /* Description: Disable NFCT peripheral */ -/* Bit 0 : */ +/* Bit 0 : Disable NFCT peripheral */ #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */ #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */ +#define NFCT_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */ /* Register: NFCT_TASKS_SENSE */ /* Description: Enable NFC sense field mode, change state to sense mode */ -/* Bit 0 : */ +/* Bit 0 : Enable NFC sense field mode, change state to sense mode */ #define NFCT_TASKS_SENSE_TASKS_SENSE_Pos (0UL) /*!< Position of TASKS_SENSE field. */ #define NFCT_TASKS_SENSE_TASKS_SENSE_Msk (0x1UL << NFCT_TASKS_SENSE_TASKS_SENSE_Pos) /*!< Bit mask of TASKS_SENSE field. */ +#define NFCT_TASKS_SENSE_TASKS_SENSE_Trigger (1UL) /*!< Trigger task */ /* Register: NFCT_TASKS_STARTTX */ /* Description: Start transmission of an outgoing frame, change state to transmit */ -/* Bit 0 : */ +/* Bit 0 : Start transmission of an outgoing frame, change state to transmit */ #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define NFCT_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ /* Register: NFCT_TASKS_ENABLERXDATA */ /* Description: Initializes the EasyDMA for receive. */ -/* Bit 0 : */ +/* Bit 0 : Initializes the EasyDMA for receive. */ #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos (0UL) /*!< Position of TASKS_ENABLERXDATA field. */ #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Msk (0x1UL << NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos) /*!< Bit mask of TASKS_ENABLERXDATA field. */ +#define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Trigger (1UL) /*!< Trigger task */ /* Register: NFCT_TASKS_GOIDLE */ /* Description: Force state machine to IDLE state */ -/* Bit 0 : */ +/* Bit 0 : Force state machine to IDLE state */ #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos (0UL) /*!< Position of TASKS_GOIDLE field. */ #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Msk (0x1UL << NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos) /*!< Bit mask of TASKS_GOIDLE field. */ +#define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Trigger (1UL) /*!< Trigger task */ /* Register: NFCT_TASKS_GOSLEEP */ /* Description: Force state machine to SLEEP_A state */ -/* Bit 0 : */ +/* Bit 0 : Force state machine to SLEEP_A state */ #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos (0UL) /*!< Position of TASKS_GOSLEEP field. */ #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Msk (0x1UL << NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos) /*!< Bit mask of TASKS_GOSLEEP field. */ +#define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Trigger (1UL) /*!< Trigger task */ /* Register: NFCT_EVENTS_READY */ /* Description: The NFCT peripheral is ready to receive and send frames */ -/* Bit 0 : */ +/* Bit 0 : The NFCT peripheral is ready to receive and send frames */ #define NFCT_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ #define NFCT_EVENTS_READY_EVENTS_READY_Msk (0x1UL << NFCT_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define NFCT_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_FIELDDETECTED */ /* Description: Remote NFC field detected */ -/* Bit 0 : */ +/* Bit 0 : Remote NFC field detected */ #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos (0UL) /*!< Position of EVENTS_FIELDDETECTED field. */ #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Msk (0x1UL << NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos) /*!< Bit mask of EVENTS_FIELDDETECTED field. */ +#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_FIELDLOST */ /* Description: Remote NFC field lost */ -/* Bit 0 : */ +/* Bit 0 : Remote NFC field lost */ #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos (0UL) /*!< Position of EVENTS_FIELDLOST field. */ #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Msk (0x1UL << NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos) /*!< Bit mask of EVENTS_FIELDLOST field. */ +#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_TXFRAMESTART */ /* Description: Marks the start of the first symbol of a transmitted frame */ -/* Bit 0 : */ +/* Bit 0 : Marks the start of the first symbol of a transmitted frame */ #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_TXFRAMESTART field. */ #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos) /*!< Bit mask of EVENTS_TXFRAMESTART field. */ +#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_TXFRAMEEND */ /* Description: Marks the end of the last transmitted on-air symbol of a frame */ -/* Bit 0 : */ +/* Bit 0 : Marks the end of the last transmitted on-air symbol of a frame */ #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_TXFRAMEEND field. */ #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos) /*!< Bit mask of EVENTS_TXFRAMEEND field. */ +#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_RXFRAMESTART */ /* Description: Marks the end of the first symbol of a received frame */ -/* Bit 0 : */ +/* Bit 0 : Marks the end of the first symbol of a received frame */ #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_RXFRAMESTART field. */ #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos) /*!< Bit mask of EVENTS_RXFRAMESTART field. */ +#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_RXFRAMEEND */ /* Description: Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer */ -/* Bit 0 : */ +/* Bit 0 : Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer */ #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_RXFRAMEEND field. */ #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos) /*!< Bit mask of EVENTS_RXFRAMEEND field. */ +#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_ERROR */ /* Description: NFC error reported. The ERRORSTATUS register contains details on the source of the error. */ -/* Bit 0 : */ +/* Bit 0 : NFC error reported. The ERRORSTATUS register contains details on the source of the error. */ #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define NFCT_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_RXERROR */ /* Description: NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */ -/* Bit 0 : */ +/* Bit 0 : NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */ #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos (0UL) /*!< Position of EVENTS_RXERROR field. */ #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Msk (0x1UL << NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos) /*!< Bit mask of EVENTS_RXERROR field. */ +#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_ENDRX */ /* Description: RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */ -/* Bit 0 : */ +/* Bit 0 : RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */ #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_ENDTX */ /* Description: Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */ -/* Bit 0 : */ +/* Bit 0 : Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */ #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ +#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_AUTOCOLRESSTARTED */ /* Description: Auto collision resolution process has started */ -/* Bit 0 : */ +/* Bit 0 : Auto collision resolution process has started */ #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos (0UL) /*!< Position of EVENTS_AUTOCOLRESSTARTED field. */ #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of EVENTS_AUTOCOLRESSTARTED field. */ +#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_COLLISION */ /* Description: NFC auto collision resolution error reported. */ -/* Bit 0 : */ +/* Bit 0 : NFC auto collision resolution error reported. */ #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos (0UL) /*!< Position of EVENTS_COLLISION field. */ #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Msk (0x1UL << NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos) /*!< Bit mask of EVENTS_COLLISION field. */ +#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_SELECTED */ /* Description: NFC auto collision resolution successfully completed */ -/* Bit 0 : */ +/* Bit 0 : NFC auto collision resolution successfully completed */ #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos (0UL) /*!< Position of EVENTS_SELECTED field. */ #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Msk (0x1UL << NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos) /*!< Bit mask of EVENTS_SELECTED field. */ +#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_STARTED */ /* Description: EasyDMA is ready to receive or send frames. */ -/* Bit 0 : */ +/* Bit 0 : EasyDMA is ready to receive or send frames. */ #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define NFCT_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ /* Register: NFCT_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 5 : Shortcut between TXFRAMEEND event and ENABLERXDATA task */ +/* Bit 5 : Shortcut between event TXFRAMEEND and task ENABLERXDATA */ #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos (5UL) /*!< Position of TXFRAMEEND_ENABLERXDATA field. */ #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Msk (0x1UL << NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos) /*!< Bit mask of TXFRAMEEND_ENABLERXDATA field. */ #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Disabled (0UL) /*!< Disable shortcut */ #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between FIELDLOST event and SENSE task */ +/* Bit 1 : Shortcut between event FIELDLOST and task SENSE */ #define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */ #define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */ #define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */ #define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between FIELDDETECTED event and ACTIVATE task */ +/* Bit 0 : Shortcut between event FIELDDETECTED and task ACTIVATE */ #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */ #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */ #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */ @@ -4213,91 +4366,91 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: NFCT_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 20 : Enable or disable interrupt for STARTED event */ +/* Bit 20 : Enable or disable interrupt for event STARTED */ #define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */ #define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for SELECTED event */ +/* Bit 19 : Enable or disable interrupt for event SELECTED */ #define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ #define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ #define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */ -/* Bit 18 : Enable or disable interrupt for COLLISION event */ +/* Bit 18 : Enable or disable interrupt for event COLLISION */ #define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ #define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ #define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */ -/* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */ +/* Bit 14 : Enable or disable interrupt for event AUTOCOLRESSTARTED */ #define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ #define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ #define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 12 : Enable or disable interrupt for ENDTX event */ +/* Bit 12 : Enable or disable interrupt for event ENDTX */ #define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ #define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ -/* Bit 11 : Enable or disable interrupt for ENDRX event */ +/* Bit 11 : Enable or disable interrupt for event ENDRX */ #define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ #define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ -/* Bit 10 : Enable or disable interrupt for RXERROR event */ +/* Bit 10 : Enable or disable interrupt for event RXERROR */ #define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ #define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ #define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for ERROR event */ +/* Bit 7 : Enable or disable interrupt for event ERROR */ #define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */ #define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */ +/* Bit 6 : Enable or disable interrupt for event RXFRAMEEND */ #define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ #define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ #define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */ +/* Bit 5 : Enable or disable interrupt for event RXFRAMESTART */ #define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ #define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ #define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */ +/* Bit 4 : Enable or disable interrupt for event TXFRAMEEND */ #define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ #define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ #define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */ +/* Bit 3 : Enable or disable interrupt for event TXFRAMESTART */ #define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ #define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ #define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for FIELDLOST event */ +/* Bit 2 : Enable or disable interrupt for event FIELDLOST */ #define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ #define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ #define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */ +/* Bit 1 : Enable or disable interrupt for event FIELDDETECTED */ #define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ #define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ #define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for READY event */ +/* Bit 0 : Enable or disable interrupt for event READY */ #define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ #define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */ #define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */ @@ -4306,105 +4459,105 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: NFCT_INTENSET */ /* Description: Enable interrupt */ -/* Bit 20 : Write '1' to enable interrupt for STARTED event */ +/* Bit 20 : Write '1' to enable interrupt for event STARTED */ #define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */ #define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for SELECTED event */ +/* Bit 19 : Write '1' to enable interrupt for event SELECTED */ #define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ #define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ #define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for COLLISION event */ +/* Bit 18 : Write '1' to enable interrupt for event COLLISION */ #define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ #define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ #define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to enable interrupt for AUTOCOLRESSTARTED event */ +/* Bit 14 : Write '1' to enable interrupt for event AUTOCOLRESSTARTED */ #define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ #define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ #define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to enable interrupt for ENDTX event */ +/* Bit 12 : Write '1' to enable interrupt for event ENDTX */ #define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ #define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */ -/* Bit 11 : Write '1' to enable interrupt for ENDRX event */ +/* Bit 11 : Write '1' to enable interrupt for event ENDRX */ #define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ #define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to enable interrupt for RXERROR event */ +/* Bit 10 : Write '1' to enable interrupt for event RXERROR */ #define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ #define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ #define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for ERROR event */ +/* Bit 7 : Write '1' to enable interrupt for event ERROR */ #define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */ #define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for RXFRAMEEND event */ +/* Bit 6 : Write '1' to enable interrupt for event RXFRAMEEND */ #define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ #define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ #define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for RXFRAMESTART event */ +/* Bit 5 : Write '1' to enable interrupt for event RXFRAMESTART */ #define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ #define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ #define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for TXFRAMEEND event */ +/* Bit 4 : Write '1' to enable interrupt for event TXFRAMEEND */ #define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ #define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ #define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for TXFRAMESTART event */ +/* Bit 3 : Write '1' to enable interrupt for event TXFRAMESTART */ #define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ #define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ #define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for FIELDLOST event */ +/* Bit 2 : Write '1' to enable interrupt for event FIELDLOST */ #define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ #define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ #define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for FIELDDETECTED event */ +/* Bit 1 : Write '1' to enable interrupt for event FIELDDETECTED */ #define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ #define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ #define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for READY event */ +/* Bit 0 : Write '1' to enable interrupt for event READY */ #define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ #define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -4414,105 +4567,105 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: NFCT_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 20 : Write '1' to disable interrupt for STARTED event */ +/* Bit 20 : Write '1' to disable interrupt for event STARTED */ #define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */ #define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for SELECTED event */ +/* Bit 19 : Write '1' to disable interrupt for event SELECTED */ #define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ #define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ #define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for COLLISION event */ +/* Bit 18 : Write '1' to disable interrupt for event COLLISION */ #define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ #define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ #define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to disable interrupt for AUTOCOLRESSTARTED event */ +/* Bit 14 : Write '1' to disable interrupt for event AUTOCOLRESSTARTED */ #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to disable interrupt for ENDTX event */ +/* Bit 12 : Write '1' to disable interrupt for event ENDTX */ #define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ #define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ -/* Bit 11 : Write '1' to disable interrupt for ENDRX event */ +/* Bit 11 : Write '1' to disable interrupt for event ENDRX */ #define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ #define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to disable interrupt for RXERROR event */ +/* Bit 10 : Write '1' to disable interrupt for event RXERROR */ #define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ #define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ #define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for ERROR event */ +/* Bit 7 : Write '1' to disable interrupt for event ERROR */ #define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */ #define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for RXFRAMEEND event */ +/* Bit 6 : Write '1' to disable interrupt for event RXFRAMEEND */ #define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ #define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ #define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for RXFRAMESTART event */ +/* Bit 5 : Write '1' to disable interrupt for event RXFRAMESTART */ #define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ #define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ #define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for TXFRAMEEND event */ +/* Bit 4 : Write '1' to disable interrupt for event TXFRAMEEND */ #define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ #define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ #define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for TXFRAMESTART event */ +/* Bit 3 : Write '1' to disable interrupt for event TXFRAMESTART */ #define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ #define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ #define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for FIELDLOST event */ +/* Bit 2 : Write '1' to disable interrupt for event FIELDLOST */ #define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ #define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ #define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for FIELDDETECTED event */ +/* Bit 1 : Write '1' to disable interrupt for event FIELDDETECTED */ #define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ #define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ #define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for READY event */ +/* Bit 0 : Write '1' to disable interrupt for event READY */ #define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ #define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -4745,7 +4898,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */ /* Register: NFCT_AUTOCOLRESCONFIG */ -/* Description: Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is enabled. */ +/* Description: Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is activated. */ /* Bit 0 : Enables/disables auto collision resolution */ #define NFCT_AUTOCOLRESCONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ @@ -4848,32 +5001,32 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */ /* Register: NVMC_ERASEPCR1 */ -/* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */ +/* Description: Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE */ -/* Bits 31..0 : Register for erasing a page in code area. Equivalent to ERASEPAGE. */ +/* Bits 31..0 : Register for erasing a page in code area, equivalent to ERASEPAGE */ #define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */ #define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */ /* Register: NVMC_ERASEALL */ /* Description: Register for erasing all non-volatile user memory */ -/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. */ +/* Bit 0 : Erase all non-volatile memory including UICR registers. The erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. */ #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */ #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */ /* Register: NVMC_ERASEPCR0 */ -/* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */ +/* Description: Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE */ -/* Bits 31..0 : Register for starting erase of a page in code area. Equivalent to ERASEPAGE. */ +/* Bits 31..0 : Register for starting erase of a page in code area, equivalent to ERASEPAGE */ #define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */ #define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */ /* Register: NVMC_ERASEUICR */ /* Description: Register for erasing user information configuration registers */ -/* Bit 0 : Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. */ +/* Bit 0 : Register starting erase of all user information configuration registers. The erase must be enabled using CONFIG.WEN before the UICR can be erased. */ #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */ #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */ #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */ @@ -4894,7 +5047,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */ /* Register: NVMC_ICACHECNF */ -/* Description: I-code cache configuration register. */ +/* Description: I-code cache configuration register */ /* Bit 8 : Cache profiling enable */ #define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */ @@ -4909,16 +5062,16 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */ /* Register: NVMC_IHIT */ -/* Description: I-code cache hit counter. */ +/* Description: I-code cache hit counter */ -/* Bits 31..0 : Number of cache hits */ +/* Bits 31..0 : Number of cache hits. Register is writable, but only to '0'. */ #define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */ #define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */ /* Register: NVMC_IMISS */ -/* Description: I-code cache miss counter. */ +/* Description: I-code cache miss counter */ -/* Bits 31..0 : Number of cache misses */ +/* Bits 31..0 : Number of cache misses. Register is writable, but only to '0'. */ #define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */ #define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */ @@ -5129,224 +5282,224 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 30 : Pin 30 */ #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 29 : Pin 29 */ #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 28 : Pin 28 */ #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 27 : Pin 27 */ #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 26 : Pin 26 */ #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 25 : Pin 25 */ #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 24 : Pin 24 */ #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 23 : Pin 23 */ #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 22 : Pin 22 */ #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 21 : Pin 21 */ #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 20 : Pin 20 */ #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 19 : Pin 19 */ #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 18 : Pin 18 */ #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 17 : Pin 17 */ #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 16 : Pin 16 */ #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 15 : Pin 15 */ #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 14 : Pin 14 */ #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 13 : Pin 13 */ #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 12 : Pin 12 */ #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 11 : Pin 11 */ #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 10 : Pin 10 */ #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 9 : Pin 9 */ #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 8 : Pin 8 */ #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 7 : Pin 7 */ #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 6 : Pin 6 */ #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 5 : Pin 5 */ #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 4 : Pin 4 */ #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 3 : Pin 3 */ #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 2 : Pin 2 */ #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 1 : Pin 1 */ #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 0 : Pin 0 */ #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Register: GPIO_OUTCLR */ /* Description: Clear individual bits in GPIO port */ @@ -5356,224 +5509,224 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 30 : Pin 30 */ #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 29 : Pin 29 */ #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 28 : Pin 28 */ #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 27 : Pin 27 */ #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 26 : Pin 26 */ #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 25 : Pin 25 */ #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 24 : Pin 24 */ #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 23 : Pin 23 */ #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 22 : Pin 22 */ #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 21 : Pin 21 */ #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 20 : Pin 20 */ #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 19 : Pin 19 */ #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 18 : Pin 18 */ #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 17 : Pin 17 */ #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 16 : Pin 16 */ #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 15 : Pin 15 */ #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 14 : Pin 14 */ #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 13 : Pin 13 */ #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 12 : Pin 12 */ #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 11 : Pin 11 */ #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 10 : Pin 10 */ #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 9 : Pin 9 */ #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 8 : Pin 8 */ #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 7 : Pin 7 */ #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 6 : Pin 6 */ #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 5 : Pin 5 */ #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 4 : Pin 4 */ #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 3 : Pin 3 */ #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 2 : Pin 2 */ #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 1 : Pin 1 */ #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 0 : Pin 0 */ #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Register: GPIO_IN */ /* Description: Read GPIO port */ @@ -5973,224 +6126,224 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 30 : Set as output pin 30 */ #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 29 : Set as output pin 29 */ #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 28 : Set as output pin 28 */ #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 27 : Set as output pin 27 */ #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 26 : Set as output pin 26 */ #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 25 : Set as output pin 25 */ #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 24 : Set as output pin 24 */ #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 23 : Set as output pin 23 */ #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 22 : Set as output pin 22 */ #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 21 : Set as output pin 21 */ #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 20 : Set as output pin 20 */ #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 19 : Set as output pin 19 */ #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 18 : Set as output pin 18 */ #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 17 : Set as output pin 17 */ #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 16 : Set as output pin 16 */ #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 15 : Set as output pin 15 */ #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 14 : Set as output pin 14 */ #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 13 : Set as output pin 13 */ #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 12 : Set as output pin 12 */ #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 11 : Set as output pin 11 */ #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 10 : Set as output pin 10 */ #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 9 : Set as output pin 9 */ #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 8 : Set as output pin 8 */ #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 7 : Set as output pin 7 */ #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 6 : Set as output pin 6 */ #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 5 : Set as output pin 5 */ #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 4 : Set as output pin 4 */ #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 3 : Set as output pin 3 */ #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 2 : Set as output pin 2 */ #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 1 : Set as output pin 1 */ #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 0 : Set as output pin 0 */ #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Register: GPIO_DIRCLR */ /* Description: DIR clear register */ @@ -6200,224 +6353,224 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 30 : Set as input pin 30 */ #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 29 : Set as input pin 29 */ #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 28 : Set as input pin 28 */ #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 27 : Set as input pin 27 */ #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 26 : Set as input pin 26 */ #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 25 : Set as input pin 25 */ #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 24 : Set as input pin 24 */ #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 23 : Set as input pin 23 */ #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 22 : Set as input pin 22 */ #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 21 : Set as input pin 21 */ #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 20 : Set as input pin 20 */ #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 19 : Set as input pin 19 */ #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 18 : Set as input pin 18 */ #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 17 : Set as input pin 17 */ #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 16 : Set as input pin 16 */ #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 15 : Set as input pin 15 */ #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 14 : Set as input pin 14 */ #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 13 : Set as input pin 13 */ #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 12 : Set as input pin 12 */ #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 11 : Set as input pin 11 */ #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 10 : Set as input pin 10 */ #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 9 : Set as input pin 9 */ #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 8 : Set as input pin 8 */ #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 7 : Set as input pin 7 */ #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 6 : Set as input pin 6 */ #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 5 : Set as input pin 5 */ #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 4 : Set as input pin 4 */ #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 3 : Set as input pin 3 */ #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 2 : Set as input pin 2 */ #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 1 : Set as input pin 1 */ #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 0 : Set as input pin 0 */ #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Register: GPIO_LATCH */ /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ @@ -6615,16 +6768,16 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */ /* Register: GPIO_DETECTMODE */ -/* Description: Select between default DETECT signal behaviour and LDETECT mode */ +/* Description: Select between default DETECT signal behavior and LDETECT mode */ -/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */ +/* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */ #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ #define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */ -#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */ +#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behavior */ /* Register: GPIO_PIN_CNF */ -/* Description: Description collection[n]: Configuration of GPIO pins */ +/* Description: Description collection: Configuration of GPIO pins */ /* Bits 17..16 : Pin sensing mechanism */ #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ @@ -6671,54 +6824,62 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: PDM_TASKS_START */ /* Description: Starts continuous PDM transfer */ -/* Bit 0 : */ +/* Bit 0 : Starts continuous PDM transfer */ #define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define PDM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: PDM_TASKS_STOP */ /* Description: Stops PDM transfer */ -/* Bit 0 : */ +/* Bit 0 : Stops PDM transfer */ #define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define PDM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: PDM_EVENTS_STARTED */ /* Description: PDM transfer has started */ -/* Bit 0 : */ +/* Bit 0 : PDM transfer has started */ #define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ #define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ /* Register: PDM_EVENTS_STOPPED */ /* Description: PDM transfer has finished */ -/* Bit 0 : */ +/* Bit 0 : PDM transfer has finished */ #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: PDM_EVENTS_END */ /* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */ -/* Bit 0 : */ +/* Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */ #define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define PDM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define PDM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ /* Register: PDM_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 2 : Enable or disable interrupt for END event */ +/* Bit 2 : Enable or disable interrupt for event END */ #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */ #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */ #define PDM_INTEN_END_Disabled (0UL) /*!< Disable */ #define PDM_INTEN_END_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for STOPPED event */ +/* Bit 1 : Enable or disable interrupt for event STOPPED */ #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ #define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for STARTED event */ +/* Bit 0 : Enable or disable interrupt for event STARTED */ #define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */ @@ -6727,21 +6888,21 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: PDM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 2 : Write '1' to enable interrupt for END event */ +/* Bit 2 : Write '1' to enable interrupt for event END */ #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */ #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ #define PDM_INTENSET_END_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for STARTED event */ +/* Bit 0 : Write '1' to enable interrupt for event STARTED */ #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -6751,21 +6912,21 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: PDM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 2 : Write '1' to disable interrupt for END event */ +/* Bit 2 : Write '1' to disable interrupt for event END */ #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */ #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for STARTED event */ +/* Bit 0 : Write '1' to disable interrupt for event STARTED */ #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -6784,7 +6945,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: PDM_PDMCLKCTRL */ /* Description: PDM clock generator control */ -/* Bits 31..0 : PDM_CLK frequency */ +/* Bits 31..0 : PDM_CLK frequency configuration */ #define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */ #define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */ #define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */ @@ -6797,7 +6958,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: PDM_MODE */ /* Description: Defines the routing of the connected PDM microphones' signals */ -/* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */ +/* Bit 1 : Defines on which PDM_CLK edge left (or mono) is sampled */ #define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */ #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */ #define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */ @@ -6806,8 +6967,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Mono or stereo operation */ #define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */ #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */ -#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */ -#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */ +#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] */ +#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] */ /* Register: PDM_GAINL */ /* Description: Left output gain adjustment */ @@ -6815,9 +6976,9 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */ #define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */ #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */ -#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ -#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment */ -#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ +#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */ +#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */ +#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */ /* Register: PDM_GAINR */ /* Description: Right output gain adjustment */ @@ -6825,9 +6986,9 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Bits 6..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */ #define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */ #define PDM_GAINR_GAINR_Msk (0x7FUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */ -#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ -#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment */ -#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ +#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */ +#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */ +#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */ /* Register: PDM_RATIO */ /* Description: Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. */ @@ -6891,100 +7052,114 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Description: Power control */ /* Register: POWER_TASKS_CONSTLAT */ -/* Description: Enable constant latency mode */ +/* Description: Enable Constant Latency mode */ -/* Bit 0 : */ +/* Bit 0 : Enable Constant Latency mode */ #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */ #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */ +#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */ /* Register: POWER_TASKS_LOWPWR */ -/* Description: Enable low power mode (variable latency) */ +/* Description: Enable Low-power mode (variable latency) */ -/* Bit 0 : */ +/* Bit 0 : Enable Low-power mode (variable latency) */ #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */ #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */ +#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */ /* Register: POWER_EVENTS_POFWARN */ /* Description: Power failure warning */ -/* Bit 0 : */ +/* Bit 0 : Power failure warning */ #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */ #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL) /*!< Event generated */ /* Register: POWER_EVENTS_SLEEPENTER */ /* Description: CPU entered WFI/WFE sleep */ -/* Bit 0 : */ +/* Bit 0 : CPU entered WFI/WFE sleep */ #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */ #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL) /*!< Event generated */ /* Register: POWER_EVENTS_SLEEPEXIT */ /* Description: CPU exited WFI/WFE sleep */ -/* Bit 0 : */ +/* Bit 0 : CPU exited WFI/WFE sleep */ #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */ #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL) /*!< Event generated */ /* Register: POWER_EVENTS_USBDETECTED */ /* Description: Voltage supply detected on VBUS */ -/* Bit 0 : */ +/* Bit 0 : Voltage supply detected on VBUS */ #define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos (0UL) /*!< Position of EVENTS_USBDETECTED field. */ #define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Msk (0x1UL << POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos) /*!< Bit mask of EVENTS_USBDETECTED field. */ +#define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Generated (1UL) /*!< Event generated */ /* Register: POWER_EVENTS_USBREMOVED */ /* Description: Voltage supply removed from VBUS */ -/* Bit 0 : */ +/* Bit 0 : Voltage supply removed from VBUS */ #define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos (0UL) /*!< Position of EVENTS_USBREMOVED field. */ #define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Msk (0x1UL << POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos) /*!< Bit mask of EVENTS_USBREMOVED field. */ +#define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Generated (1UL) /*!< Event generated */ /* Register: POWER_EVENTS_USBPWRRDY */ /* Description: USB 3.3 V supply ready */ -/* Bit 0 : */ +/* Bit 0 : USB 3.3 V supply ready */ #define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos (0UL) /*!< Position of EVENTS_USBPWRRDY field. */ #define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Msk (0x1UL << POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos) /*!< Bit mask of EVENTS_USBPWRRDY field. */ +#define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Generated (1UL) /*!< Event generated */ /* Register: POWER_INTENSET */ /* Description: Enable interrupt */ -/* Bit 9 : Write '1' to enable interrupt for USBPWRRDY event */ +/* Bit 9 : Write '1' to enable interrupt for event USBPWRRDY */ #define POWER_INTENSET_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */ #define POWER_INTENSET_USBPWRRDY_Msk (0x1UL << POWER_INTENSET_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */ #define POWER_INTENSET_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENSET_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENSET_USBPWRRDY_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for USBREMOVED event */ +/* Bit 8 : Write '1' to enable interrupt for event USBREMOVED */ #define POWER_INTENSET_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */ #define POWER_INTENSET_USBREMOVED_Msk (0x1UL << POWER_INTENSET_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */ #define POWER_INTENSET_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENSET_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENSET_USBREMOVED_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for USBDETECTED event */ +/* Bit 7 : Write '1' to enable interrupt for event USBDETECTED */ #define POWER_INTENSET_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */ #define POWER_INTENSET_USBDETECTED_Msk (0x1UL << POWER_INTENSET_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */ #define POWER_INTENSET_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENSET_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENSET_USBDETECTED_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for SLEEPEXIT event */ +/* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */ #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for SLEEPENTER event */ +/* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */ #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for POFWARN event */ +/* Bit 2 : Write '1' to enable interrupt for event POFWARN */ #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */ @@ -6994,42 +7169,42 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: POWER_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 9 : Write '1' to disable interrupt for USBPWRRDY event */ +/* Bit 9 : Write '1' to disable interrupt for event USBPWRRDY */ #define POWER_INTENCLR_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */ #define POWER_INTENCLR_USBPWRRDY_Msk (0x1UL << POWER_INTENCLR_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */ #define POWER_INTENCLR_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENCLR_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENCLR_USBPWRRDY_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for USBREMOVED event */ +/* Bit 8 : Write '1' to disable interrupt for event USBREMOVED */ #define POWER_INTENCLR_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */ #define POWER_INTENCLR_USBREMOVED_Msk (0x1UL << POWER_INTENCLR_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */ #define POWER_INTENCLR_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENCLR_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENCLR_USBREMOVED_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for USBDETECTED event */ +/* Bit 7 : Write '1' to disable interrupt for event USBDETECTED */ #define POWER_INTENCLR_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */ #define POWER_INTENCLR_USBDETECTED_Msk (0x1UL << POWER_INTENCLR_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */ #define POWER_INTENCLR_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENCLR_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENCLR_USBDETECTED_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for SLEEPEXIT event */ +/* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */ #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for SLEEPENTER event */ +/* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */ #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for POFWARN event */ +/* Bit 2 : Write '1' to disable interrupt for event POFWARN */ #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */ @@ -7203,7 +7378,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ /* Register: POWER_DCDCEN */ -/* Description: Enable DC/DC converter for REG1 stage. */ +/* Description: Enable DC/DC converter for REG1 stage */ /* Bit 0 : Enable DC/DC converter for REG1 stage. */ #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ @@ -7212,7 +7387,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */ /* Register: POWER_DCDCEN0 */ -/* Description: Enable DC/DC converter for REG0 stage. */ +/* Description: Enable DC/DC converter for REG0 stage */ /* Bit 0 : Enable DC/DC converter for REG0 stage. */ #define POWER_DCDCEN0_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ @@ -7230,7 +7405,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define POWER_MAINREGSTATUS_MAINREGSTATUS_High (1UL) /*!< High voltage mode. Voltage supplied on VDDH. */ /* Register: POWER_RAM_POWER */ -/* Description: Description cluster[n]: RAMn power control register */ +/* Description: Description cluster: RAMn power control register */ /* Bit 31 : Keep retention on RAM section S15 when RAM section is off */ #define POWER_RAM_POWER_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */ @@ -7425,7 +7600,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */ /* Register: POWER_RAM_POWERSET */ -/* Description: Description cluster[n]: RAMn power control set register */ +/* Description: Description cluster: RAMn power control set register */ /* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */ #define POWER_RAM_POWERSET_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */ @@ -7588,7 +7763,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */ /* Register: POWER_RAM_POWERCLR */ -/* Description: Description cluster[n]: RAMn power control clear register */ +/* Description: Description cluster: RAMn power control clear register */ /* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */ #define POWER_RAM_POWERCLR_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */ @@ -7755,18 +7930,20 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Description: Programmable Peripheral Interconnect */ /* Register: PPI_TASKS_CHG_EN */ -/* Description: Description cluster[n]: Enable channel group n */ +/* Description: Description cluster: Enable channel group n */ -/* Bit 0 : */ +/* Bit 0 : Enable channel group n */ #define PPI_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */ #define PPI_TASKS_CHG_EN_EN_Msk (0x1UL << PPI_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ +#define PPI_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */ /* Register: PPI_TASKS_CHG_DIS */ -/* Description: Description cluster[n]: Disable channel group n */ +/* Description: Description cluster: Disable channel group n */ -/* Bit 0 : */ +/* Bit 0 : Disable channel group n */ #define PPI_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */ #define PPI_TASKS_CHG_DIS_DIS_Msk (0x1UL << PPI_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */ +#define PPI_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */ /* Register: PPI_CHEN */ /* Description: Channel enable register */ @@ -7966,224 +8143,224 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: PPI_CHENSET */ /* Description: Channel enable set register */ -/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */ +/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */ -/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */ +/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */ -/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */ +/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */ -/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */ +/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */ -/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */ +/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */ -/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */ +/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */ -/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */ +/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */ -/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */ +/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */ -/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */ +/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */ -/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */ +/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */ -/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */ +/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */ -/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */ +/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */ -/* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */ +/* Bit 19 : Channel 19 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */ #define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */ #define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */ -/* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */ +/* Bit 18 : Channel 18 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */ #define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */ #define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */ -/* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */ +/* Bit 17 : Channel 17 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */ #define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */ #define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */ -/* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */ +/* Bit 16 : Channel 16 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */ #define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */ #define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */ -/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */ +/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */ -/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */ +/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */ -/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */ +/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */ -/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */ +/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */ -/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */ +/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */ -/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */ +/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */ -/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */ +/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */ -/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */ +/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */ -/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */ +/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */ -/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */ +/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */ -/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */ +/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */ -/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */ +/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */ -/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */ +/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */ -/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */ +/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */ -/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */ +/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */ -/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */ +/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */ @@ -8193,224 +8370,224 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: PPI_CHENCLR */ /* Description: Channel enable clear register */ -/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */ +/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */ -/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */ +/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */ -/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */ +/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */ -/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */ +/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */ -/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */ +/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */ -/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */ +/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */ -/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */ +/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */ -/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */ +/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */ -/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */ +/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */ -/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */ +/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */ -/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */ +/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */ -/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */ +/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */ -/* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */ +/* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */ #define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */ #define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */ -/* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */ +/* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */ #define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */ #define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */ -/* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */ +/* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */ #define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */ #define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */ -/* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */ +/* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */ #define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */ #define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */ -/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */ +/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */ -/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */ +/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */ -/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */ +/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */ -/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */ +/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */ -/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */ +/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */ -/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */ +/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */ -/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */ +/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */ -/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */ +/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */ -/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */ +/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */ -/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */ +/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */ -/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */ +/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */ -/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */ +/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */ -/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */ +/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */ -/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */ +/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */ -/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */ +/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */ -/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */ +/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */ @@ -8418,21 +8595,21 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */ /* Register: PPI_CH_EEP */ -/* Description: Description cluster[n]: Channel n event end-point */ +/* Description: Description cluster: Channel n event endpoint */ /* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */ #define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */ #define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */ /* Register: PPI_CH_TEP */ -/* Description: Description cluster[n]: Channel n task end-point */ +/* Description: Description cluster: Channel n task endpoint */ /* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */ #define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ #define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ /* Register: PPI_CHG */ -/* Description: Description collection[n]: Channel group n */ +/* Description: Description collection: Channel group n */ /* Bit 31 : Include or exclude channel 31 */ #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ @@ -8627,7 +8804,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define PPI_CHG_CH0_Included (1UL) /*!< Include */ /* Register: PPI_FORK_TEP */ -/* Description: Description cluster[n]: Channel n task end-point */ +/* Description: Description cluster: Channel n task endpoint */ /* Bits 31..0 : Pointer to task register */ #define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ @@ -8640,87 +8817,100 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: PWM_TASKS_STOP */ /* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ -/* Bit 0 : */ +/* Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ #define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define PWM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: PWM_TASKS_SEQSTART */ -/* Description: Description collection[n]: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ +/* Description: Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ -/* Bit 0 : */ +/* Bit 0 : Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */ #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART field. */ +#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (1UL) /*!< Trigger task */ /* Register: PWM_TASKS_NEXTSTEP */ /* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */ -/* Bit 0 : */ +/* Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */ #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */ #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP field. */ +#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (1UL) /*!< Trigger task */ /* Register: PWM_EVENTS_STOPPED */ /* Description: Response to STOP task, emitted when PWM pulses are no longer generated */ -/* Bit 0 : */ +/* Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */ #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: PWM_EVENTS_SEQSTARTED */ -/* Description: Description collection[n]: First PWM period started on sequence n */ +/* Description: Description collection: First PWM period started on sequence n */ -/* Bit 0 : */ +/* Bit 0 : First PWM period started on sequence n */ #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */ #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */ +#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (1UL) /*!< Event generated */ /* Register: PWM_EVENTS_SEQEND */ -/* Description: Description collection[n]: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ +/* Description: Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ -/* Bit 0 : */ +/* Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */ #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND field. */ +#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (1UL) /*!< Event generated */ /* Register: PWM_EVENTS_PWMPERIODEND */ /* Description: Emitted at the end of each PWM period */ -/* Bit 0 : */ +/* Bit 0 : Emitted at the end of each PWM period */ #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */ #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit mask of EVENTS_PWMPERIODEND field. */ +#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (1UL) /*!< Event generated */ /* Register: PWM_EVENTS_LOOPSDONE */ /* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */ -/* Bit 0 : */ +/* Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */ #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */ #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of EVENTS_LOOPSDONE field. */ +#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (1UL) /*!< Event generated */ /* Register: PWM_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 4 : Shortcut between LOOPSDONE event and STOP task */ +/* Bit 4 : Shortcut between event LOOPSDONE and task STOP */ #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */ #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */ #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */ #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */ +/* Bit 3 : Shortcut between event LOOPSDONE and task SEQSTART[1] */ #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */ #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */ #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */ #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */ +/* Bit 2 : Shortcut between event LOOPSDONE and task SEQSTART[0] */ #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */ #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */ #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */ #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between SEQEND[1] event and STOP task */ +/* Bit 1 : Shortcut between event SEQEND[1] and task STOP */ #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */ #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */ #define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */ #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between SEQEND[0] event and STOP task */ +/* Bit 0 : Shortcut between event SEQEND[0] and task STOP */ #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */ #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */ #define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */ @@ -8729,43 +8919,43 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: PWM_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 7 : Enable or disable interrupt for LOOPSDONE event */ +/* Bit 7 : Enable or disable interrupt for event LOOPSDONE */ #define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ #define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */ +/* Bit 6 : Enable or disable interrupt for event PWMPERIODEND */ #define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ #define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for SEQEND[1] event */ +/* Bit 5 : Enable or disable interrupt for event SEQEND[1] */ #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ #define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for SEQEND[0] event */ +/* Bit 4 : Enable or disable interrupt for event SEQEND[0] */ #define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ #define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */ +/* Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */ #define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ #define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */ +/* Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */ #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ #define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for STOPPED event */ +/* Bit 1 : Enable or disable interrupt for event STOPPED */ #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ @@ -8774,49 +8964,49 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: PWM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 7 : Write '1' to enable interrupt for LOOPSDONE event */ +/* Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */ #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for PWMPERIODEND event */ +/* Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */ #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for SEQEND[1] event */ +/* Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */ #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for SEQEND[0] event */ +/* Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */ #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for SEQSTARTED[1] event */ +/* Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */ #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for SEQSTARTED[0] event */ +/* Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */ #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -8826,49 +9016,49 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: PWM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 7 : Write '1' to disable interrupt for LOOPSDONE event */ +/* Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */ #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for PWMPERIODEND event */ +/* Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */ #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for SEQEND[1] event */ +/* Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */ #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for SEQEND[0] event */ +/* Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */ #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for SEQSTARTED[1] event */ +/* Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */ #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for SEQSTARTED[0] event */ +/* Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */ #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -8941,14 +9131,14 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */ /* Register: PWM_SEQ_PTR */ -/* Description: Description cluster[n]: Beginning address in RAM of this sequence */ +/* Description: Description cluster: Beginning address in RAM of this sequence */ /* Bits 31..0 : Beginning address in RAM of this sequence */ #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ /* Register: PWM_SEQ_CNT */ -/* Description: Description cluster[n]: Number of values (duty cycles) in this sequence */ +/* Description: Description cluster: Number of values (duty cycles) in this sequence */ /* Bits 14..0 : Number of values (duty cycles) in this sequence */ #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ @@ -8956,7 +9146,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */ /* Register: PWM_SEQ_REFRESH */ -/* Description: Description cluster[n]: Number of additional PWM periods between samples loaded into compare register */ +/* Description: Description cluster: Number of additional PWM periods between samples loaded into compare register */ /* Bits 23..0 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */ #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */ @@ -8964,14 +9154,14 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */ /* Register: PWM_SEQ_ENDDELAY */ -/* Description: Description cluster[n]: Time added after the sequence */ +/* Description: Description cluster: Time added after the sequence */ /* Bits 23..0 : Time added after the sequence in PWM periods */ #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */ #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */ /* Register: PWM_PSEL_OUT */ -/* Description: Description collection[n]: Output pin select for PWM channel n */ +/* Description: Description collection: Output pin select for PWM channel n */ /* Bit 31 : Connection */ #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ @@ -8994,113 +9184,128 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: QDEC_TASKS_START */ /* Description: Task starting the quadrature decoder */ -/* Bit 0 : */ +/* Bit 0 : Task starting the quadrature decoder */ #define QDEC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define QDEC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: QDEC_TASKS_STOP */ /* Description: Task stopping the quadrature decoder */ -/* Bit 0 : */ +/* Bit 0 : Task stopping the quadrature decoder */ #define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define QDEC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: QDEC_TASKS_READCLRACC */ /* Description: Read and clear ACC and ACCDBL */ -/* Bit 0 : */ +/* Bit 0 : Read and clear ACC and ACCDBL */ #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL) /*!< Position of TASKS_READCLRACC field. */ #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos) /*!< Bit mask of TASKS_READCLRACC field. */ +#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Trigger (1UL) /*!< Trigger task */ /* Register: QDEC_TASKS_RDCLRACC */ /* Description: Read and clear ACC */ -/* Bit 0 : */ +/* Bit 0 : Read and clear ACC */ #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL) /*!< Position of TASKS_RDCLRACC field. */ #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos) /*!< Bit mask of TASKS_RDCLRACC field. */ +#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Trigger (1UL) /*!< Trigger task */ /* Register: QDEC_TASKS_RDCLRDBL */ /* Description: Read and clear ACCDBL */ -/* Bit 0 : */ +/* Bit 0 : Read and clear ACCDBL */ #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL) /*!< Position of TASKS_RDCLRDBL field. */ #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos) /*!< Bit mask of TASKS_RDCLRDBL field. */ +#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Trigger (1UL) /*!< Trigger task */ /* Register: QDEC_EVENTS_SAMPLERDY */ /* Description: Event being generated for every new sample value written to the SAMPLE register */ -/* Bit 0 : */ +/* Bit 0 : Event being generated for every new sample value written to the SAMPLE register */ #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL) /*!< Position of EVENTS_SAMPLERDY field. */ #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos) /*!< Bit mask of EVENTS_SAMPLERDY field. */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Generated (1UL) /*!< Event generated */ /* Register: QDEC_EVENTS_REPORTRDY */ /* Description: Non-null report ready */ -/* Bit 0 : */ +/* Bit 0 : Non-null report ready */ #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL) /*!< Position of EVENTS_REPORTRDY field. */ #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos) /*!< Bit mask of EVENTS_REPORTRDY field. */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Generated (1UL) /*!< Event generated */ /* Register: QDEC_EVENTS_ACCOF */ /* Description: ACC or ACCDBL register overflow */ -/* Bit 0 : */ +/* Bit 0 : ACC or ACCDBL register overflow */ #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL) /*!< Position of EVENTS_ACCOF field. */ #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos) /*!< Bit mask of EVENTS_ACCOF field. */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Generated (1UL) /*!< Event generated */ /* Register: QDEC_EVENTS_DBLRDY */ /* Description: Double displacement(s) detected */ -/* Bit 0 : */ +/* Bit 0 : Double displacement(s) detected */ #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL) /*!< Position of EVENTS_DBLRDY field. */ #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos) /*!< Bit mask of EVENTS_DBLRDY field. */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Generated (1UL) /*!< Event generated */ /* Register: QDEC_EVENTS_STOPPED */ /* Description: QDEC has been stopped */ -/* Bit 0 : */ +/* Bit 0 : QDEC has been stopped */ #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: QDEC_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */ +/* Bit 6 : Shortcut between event SAMPLERDY and task READCLRACC */ #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */ #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */ #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 5 : Shortcut between DBLRDY event and STOP task */ +/* Bit 5 : Shortcut between event DBLRDY and task STOP */ #define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */ #define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */ #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */ +/* Bit 4 : Shortcut between event DBLRDY and task RDCLRDBL */ #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */ #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */ #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between REPORTRDY event and STOP task */ +/* Bit 3 : Shortcut between event REPORTRDY and task STOP */ #define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */ #define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */ #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */ +/* Bit 2 : Shortcut between event REPORTRDY and task RDCLRACC */ #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */ #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */ #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between SAMPLERDY event and STOP task */ +/* Bit 1 : Shortcut between event SAMPLERDY and task STOP */ #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */ +/* Bit 0 : Shortcut between event REPORTRDY and task READCLRACC */ #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ @@ -9109,35 +9314,35 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: QDEC_INTENSET */ /* Description: Enable interrupt */ -/* Bit 4 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 4 : Write '1' to enable interrupt for event STOPPED */ #define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ #define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for DBLRDY event */ +/* Bit 3 : Write '1' to enable interrupt for event DBLRDY */ #define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ #define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ #define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for ACCOF event */ +/* Bit 2 : Write '1' to enable interrupt for event ACCOF */ #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for REPORTRDY event */ +/* Bit 1 : Write '1' to enable interrupt for event REPORTRDY */ #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for SAMPLERDY event */ +/* Bit 0 : Write '1' to enable interrupt for event SAMPLERDY */ #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ @@ -9147,35 +9352,35 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: QDEC_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 4 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 4 : Write '1' to disable interrupt for event STOPPED */ #define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ #define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for DBLRDY event */ +/* Bit 3 : Write '1' to disable interrupt for event DBLRDY */ #define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ #define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ #define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for ACCOF event */ +/* Bit 2 : Write '1' to disable interrupt for event ACCOF */ #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for REPORTRDY event */ +/* Bit 1 : Write '1' to disable interrupt for event REPORTRDY */ #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for SAMPLERDY event */ +/* Bit 0 : Write '1' to disable interrupt for event SAMPLERDY */ #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ @@ -9228,23 +9433,23 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: QDEC_REPORTPER */ /* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */ -/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */ +/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. */ #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ #define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ -#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */ -#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */ -#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */ -#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */ -#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */ -#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */ -#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */ -#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */ -#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */ +#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples/report */ +#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples/report */ +#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples/report */ +#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples/report */ +#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples/report */ +#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples/report */ +#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples/report */ +#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples/report */ +#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample/report */ /* Register: QDEC_ACC */ /* Description: Register accumulating the valid transitions */ -/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */ +/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register. */ #define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */ #define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */ @@ -9343,49 +9548,56 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: QSPI_TASKS_ACTIVATE */ /* Description: Activate QSPI interface */ -/* Bit 0 : */ +/* Bit 0 : Activate QSPI interface */ #define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL) /*!< Position of TASKS_ACTIVATE field. */ #define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos) /*!< Bit mask of TASKS_ACTIVATE field. */ +#define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Trigger (1UL) /*!< Trigger task */ /* Register: QSPI_TASKS_READSTART */ /* Description: Start transfer from external flash memory to internal RAM */ -/* Bit 0 : */ +/* Bit 0 : Start transfer from external flash memory to internal RAM */ #define QSPI_TASKS_READSTART_TASKS_READSTART_Pos (0UL) /*!< Position of TASKS_READSTART field. */ #define QSPI_TASKS_READSTART_TASKS_READSTART_Msk (0x1UL << QSPI_TASKS_READSTART_TASKS_READSTART_Pos) /*!< Bit mask of TASKS_READSTART field. */ +#define QSPI_TASKS_READSTART_TASKS_READSTART_Trigger (1UL) /*!< Trigger task */ /* Register: QSPI_TASKS_WRITESTART */ /* Description: Start transfer from internal RAM to external flash memory */ -/* Bit 0 : */ +/* Bit 0 : Start transfer from internal RAM to external flash memory */ #define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Pos (0UL) /*!< Position of TASKS_WRITESTART field. */ #define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Msk (0x1UL << QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Pos) /*!< Bit mask of TASKS_WRITESTART field. */ +#define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Trigger (1UL) /*!< Trigger task */ /* Register: QSPI_TASKS_ERASESTART */ /* Description: Start external flash memory erase operation */ -/* Bit 0 : */ +/* Bit 0 : Start external flash memory erase operation */ #define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Pos (0UL) /*!< Position of TASKS_ERASESTART field. */ #define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Msk (0x1UL << QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Pos) /*!< Bit mask of TASKS_ERASESTART field. */ +#define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Trigger (1UL) /*!< Trigger task */ /* Register: QSPI_TASKS_DEACTIVATE */ /* Description: Deactivate QSPI interface */ -/* Bit 0 : */ +/* Bit 0 : Deactivate QSPI interface */ #define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Pos (0UL) /*!< Position of TASKS_DEACTIVATE field. */ #define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Msk (0x1UL << QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Pos) /*!< Bit mask of TASKS_DEACTIVATE field. */ +#define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Trigger (1UL) /*!< Trigger task */ /* Register: QSPI_EVENTS_READY */ /* Description: QSPI peripheral is ready. This event will be generated as a response to any QSPI task. */ -/* Bit 0 : */ +/* Bit 0 : QSPI peripheral is ready. This event will be generated as a response to any QSPI task. */ #define QSPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ #define QSPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << QSPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define QSPI_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define QSPI_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ /* Register: QSPI_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 0 : Enable or disable interrupt for READY event */ +/* Bit 0 : Enable or disable interrupt for event READY */ #define QSPI_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ #define QSPI_INTEN_READY_Msk (0x1UL << QSPI_INTEN_READY_Pos) /*!< Bit mask of READY field. */ #define QSPI_INTEN_READY_Disabled (0UL) /*!< Disable */ @@ -9394,7 +9606,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: QSPI_INTENSET */ /* Description: Enable interrupt */ -/* Bit 0 : Write '1' to enable interrupt for READY event */ +/* Bit 0 : Write '1' to enable interrupt for event READY */ #define QSPI_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ #define QSPI_INTENSET_READY_Msk (0x1UL << QSPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define QSPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -9404,7 +9616,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: QSPI_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 0 : Write '1' to disable interrupt for READY event */ +/* Bit 0 : Write '1' to disable interrupt for event READY */ #define QSPI_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ #define QSPI_INTENCLR_READY_Msk (0x1UL << QSPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define QSPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -9437,9 +9649,9 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: QSPI_READ_CNT */ /* Description: Read transfer length */ -/* Bits 20..0 : Read transfer length in number of bytes. The length must be a multiple of 4 bytes. */ +/* Bits 17..0 : Read transfer length in number of bytes. The length must be a multiple of 4 bytes. */ #define QSPI_READ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ -#define QSPI_READ_CNT_CNT_Msk (0x1FFFFFUL << QSPI_READ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ +#define QSPI_READ_CNT_CNT_Msk (0x3FFFFUL << QSPI_READ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ /* Register: QSPI_WRITE_DST */ /* Description: Flash destination address */ @@ -9458,9 +9670,9 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: QSPI_WRITE_CNT */ /* Description: Write transfer length */ -/* Bits 20..0 : Write transfer length in number of bytes. The length must be a multiple of 4 bytes. */ +/* Bits 17..0 : Write transfer length in number of bytes. The length must be a multiple of 4 bytes. */ #define QSPI_WRITE_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ -#define QSPI_WRITE_CNT_CNT_Msk (0x1FFFFFUL << QSPI_WRITE_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ +#define QSPI_WRITE_CNT_CNT_Msk (0x3FFFFUL << QSPI_WRITE_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ /* Register: QSPI_ERASE_PTR */ /* Description: Start address of flash block to be erased */ @@ -9817,360 +10029,426 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_TASKS_TXEN */ /* Description: Enable RADIO in TX mode */ -/* Bit 0 : */ +/* Bit 0 : Enable RADIO in TX mode */ #define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL) /*!< Position of TASKS_TXEN field. */ #define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field. */ +#define RADIO_TASKS_TXEN_TASKS_TXEN_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_RXEN */ /* Description: Enable RADIO in RX mode */ -/* Bit 0 : */ +/* Bit 0 : Enable RADIO in RX mode */ #define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL) /*!< Position of TASKS_RXEN field. */ #define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field. */ +#define RADIO_TASKS_RXEN_TASKS_RXEN_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_START */ /* Description: Start RADIO */ -/* Bit 0 : */ +/* Bit 0 : Start RADIO */ #define RADIO_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define RADIO_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_STOP */ /* Description: Stop RADIO */ -/* Bit 0 : */ +/* Bit 0 : Stop RADIO */ #define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define RADIO_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_DISABLE */ /* Description: Disable RADIO */ -/* Bit 0 : */ +/* Bit 0 : Disable RADIO */ #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */ #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */ +#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_RSSISTART */ /* Description: Start the RSSI and take one single sample of the receive signal strength */ -/* Bit 0 : */ +/* Bit 0 : Start the RSSI and take one single sample of the receive signal strength */ #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */ #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of TASKS_RSSISTART field. */ +#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_RSSISTOP */ /* Description: Stop the RSSI measurement */ -/* Bit 0 : */ +/* Bit 0 : Stop the RSSI measurement */ #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos (0UL) /*!< Position of TASKS_RSSISTOP field. */ #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Msk (0x1UL << RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos) /*!< Bit mask of TASKS_RSSISTOP field. */ +#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_BCSTART */ /* Description: Start the bit counter */ -/* Bit 0 : */ +/* Bit 0 : Start the bit counter */ #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field. */ #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART field. */ +#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_BCSTOP */ /* Description: Stop the bit counter */ -/* Bit 0 : */ +/* Bit 0 : Stop the bit counter */ #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL) /*!< Position of TASKS_BCSTOP field. */ #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP field. */ +#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_EDSTART */ /* Description: Start the energy detect measurement used in IEEE 802.15.4 mode */ -/* Bit 0 : */ +/* Bit 0 : Start the energy detect measurement used in IEEE 802.15.4 mode */ #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos (0UL) /*!< Position of TASKS_EDSTART field. */ #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Msk (0x1UL << RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos) /*!< Bit mask of TASKS_EDSTART field. */ +#define RADIO_TASKS_EDSTART_TASKS_EDSTART_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_EDSTOP */ /* Description: Stop the energy detect measurement */ -/* Bit 0 : */ +/* Bit 0 : Stop the energy detect measurement */ #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos (0UL) /*!< Position of TASKS_EDSTOP field. */ #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Msk (0x1UL << RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos) /*!< Bit mask of TASKS_EDSTOP field. */ +#define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_CCASTART */ /* Description: Start the clear channel assessment used in IEEE 802.15.4 mode */ -/* Bit 0 : */ +/* Bit 0 : Start the clear channel assessment used in IEEE 802.15.4 mode */ #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos (0UL) /*!< Position of TASKS_CCASTART field. */ #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Msk (0x1UL << RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos) /*!< Bit mask of TASKS_CCASTART field. */ +#define RADIO_TASKS_CCASTART_TASKS_CCASTART_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_CCASTOP */ /* Description: Stop the clear channel assessment */ -/* Bit 0 : */ +/* Bit 0 : Stop the clear channel assessment */ #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos (0UL) /*!< Position of TASKS_CCASTOP field. */ #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Msk (0x1UL << RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos) /*!< Bit mask of TASKS_CCASTOP field. */ +#define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_EVENTS_READY */ /* Description: RADIO has ramped up and is ready to be started */ -/* Bit 0 : */ +/* Bit 0 : RADIO has ramped up and is ready to be started */ #define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ #define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define RADIO_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_ADDRESS */ /* Description: Address sent or received */ -/* Bit 0 : */ +/* Bit 0 : Address sent or received */ #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field. */ #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of EVENTS_ADDRESS field. */ +#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_PAYLOAD */ /* Description: Packet payload sent or received */ -/* Bit 0 : */ +/* Bit 0 : Packet payload sent or received */ #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field. */ #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of EVENTS_PAYLOAD field. */ +#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_END */ /* Description: Packet sent or received */ -/* Bit 0 : */ +/* Bit 0 : Packet sent or received */ #define RADIO_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define RADIO_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_DISABLED */ /* Description: RADIO has been disabled */ -/* Bit 0 : */ +/* Bit 0 : RADIO has been disabled */ #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field. */ #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of EVENTS_DISABLED field. */ +#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_DEVMATCH */ /* Description: A device address match occurred on the last received packet */ -/* Bit 0 : */ +/* Bit 0 : A device address match occurred on the last received packet */ #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field. */ #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of EVENTS_DEVMATCH field. */ +#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_DEVMISS */ /* Description: No device address match occurred on the last received packet */ -/* Bit 0 : */ +/* Bit 0 : No device address match occurred on the last received packet */ #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field. */ #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of EVENTS_DEVMISS field. */ +#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_RSSIEND */ /* Description: Sampling of receive signal strength complete */ -/* Bit 0 : */ +/* Bit 0 : Sampling of receive signal strength complete */ #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos (0UL) /*!< Position of EVENTS_RSSIEND field. */ #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Msk (0x1UL << RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos) /*!< Bit mask of EVENTS_RSSIEND field. */ +#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_BCMATCH */ /* Description: Bit counter reached bit count value */ -/* Bit 0 : */ +/* Bit 0 : Bit counter reached bit count value */ #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */ #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of EVENTS_BCMATCH field. */ +#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_CRCOK */ /* Description: Packet received with CRC ok */ -/* Bit 0 : */ +/* Bit 0 : Packet received with CRC ok */ #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL) /*!< Position of EVENTS_CRCOK field. */ #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK field. */ +#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_CRCERROR */ /* Description: Packet received with CRC error */ -/* Bit 0 : */ +/* Bit 0 : Packet received with CRC error */ #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field. */ #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of EVENTS_CRCERROR field. */ +#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_FRAMESTART */ /* Description: IEEE 802.15.4 length field received */ -/* Bit 0 : */ +/* Bit 0 : IEEE 802.15.4 length field received */ #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL) /*!< Position of EVENTS_FRAMESTART field. */ #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos) /*!< Bit mask of EVENTS_FRAMESTART field. */ +#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_EDEND */ /* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ -/* Bit 0 : */ +/* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL) /*!< Position of EVENTS_EDEND field. */ #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND field. */ +#define RADIO_EVENTS_EDEND_EVENTS_EDEND_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_EDEND_EVENTS_EDEND_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_EDSTOPPED */ /* Description: The sampling of energy detection has stopped */ -/* Bit 0 : */ +/* Bit 0 : The sampling of energy detection has stopped */ #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos (0UL) /*!< Position of EVENTS_EDSTOPPED field. */ #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Msk (0x1UL << RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos) /*!< Bit mask of EVENTS_EDSTOPPED field. */ +#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_CCAIDLE */ /* Description: Wireless medium in idle - clear to send */ -/* Bit 0 : */ +/* Bit 0 : Wireless medium in idle - clear to send */ #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos (0UL) /*!< Position of EVENTS_CCAIDLE field. */ #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Msk (0x1UL << RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos) /*!< Bit mask of EVENTS_CCAIDLE field. */ +#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_CCABUSY */ /* Description: Wireless medium busy - do not send */ -/* Bit 0 : */ +/* Bit 0 : Wireless medium busy - do not send */ #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos (0UL) /*!< Position of EVENTS_CCABUSY field. */ #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Msk (0x1UL << RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos) /*!< Bit mask of EVENTS_CCABUSY field. */ +#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_CCASTOPPED */ /* Description: The CCA has stopped */ -/* Bit 0 : */ +/* Bit 0 : The CCA has stopped */ #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos (0UL) /*!< Position of EVENTS_CCASTOPPED field. */ #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Msk (0x1UL << RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos) /*!< Bit mask of EVENTS_CCASTOPPED field. */ +#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_RATEBOOST */ /* Description: Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */ -/* Bit 0 : */ +/* Bit 0 : Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */ #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos (0UL) /*!< Position of EVENTS_RATEBOOST field. */ #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Msk (0x1UL << RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos) /*!< Bit mask of EVENTS_RATEBOOST field. */ +#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_TXREADY */ /* Description: RADIO has ramped up and is ready to be started TX path */ -/* Bit 0 : */ +/* Bit 0 : RADIO has ramped up and is ready to be started TX path */ #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos (0UL) /*!< Position of EVENTS_TXREADY field. */ #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Msk (0x1UL << RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos) /*!< Bit mask of EVENTS_TXREADY field. */ +#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_RXREADY */ /* Description: RADIO has ramped up and is ready to be started RX path */ -/* Bit 0 : */ +/* Bit 0 : RADIO has ramped up and is ready to be started RX path */ #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL) /*!< Position of EVENTS_RXREADY field. */ #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of EVENTS_RXREADY field. */ +#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_MHRMATCH */ /* Description: MAC header match found */ -/* Bit 0 : */ +/* Bit 0 : MAC header match found */ #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos (0UL) /*!< Position of EVENTS_MHRMATCH field. */ #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Msk (0x1UL << RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos) /*!< Bit mask of EVENTS_MHRMATCH field. */ +#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_SYNC */ +/* Description: Preamble indicator. */ + +/* Bit 0 : Preamble indicator. */ +#define RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos (0UL) /*!< Position of EVENTS_SYNC field. */ +#define RADIO_EVENTS_SYNC_EVENTS_SYNC_Msk (0x1UL << RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos) /*!< Bit mask of EVENTS_SYNC field. */ +#define RADIO_EVENTS_SYNC_EVENTS_SYNC_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_SYNC_EVENTS_SYNC_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_PHYEND */ -/* Description: Generated in Ble_LR125Kbit, Ble_LR500Kbit and BleIeee802154_250Kbit modes when last bit is sent on air. */ +/* Description: Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. */ -/* Bit 0 : */ +/* Bit 0 : Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. */ #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL) /*!< Position of EVENTS_PHYEND field. */ #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos) /*!< Bit mask of EVENTS_PHYEND field. */ +#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Generated (1UL) /*!< Event generated */ /* Register: RADIO_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 21 : Shortcut between PHYEND event and START task */ +/* Bit 21 : Shortcut between event PHYEND and task START */ #define RADIO_SHORTS_PHYEND_START_Pos (21UL) /*!< Position of PHYEND_START field. */ #define RADIO_SHORTS_PHYEND_START_Msk (0x1UL << RADIO_SHORTS_PHYEND_START_Pos) /*!< Bit mask of PHYEND_START field. */ #define RADIO_SHORTS_PHYEND_START_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_PHYEND_START_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 20 : Shortcut between PHYEND event and DISABLE task */ +/* Bit 20 : Shortcut between event PHYEND and task DISABLE */ #define RADIO_SHORTS_PHYEND_DISABLE_Pos (20UL) /*!< Position of PHYEND_DISABLE field. */ #define RADIO_SHORTS_PHYEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_PHYEND_DISABLE_Pos) /*!< Bit mask of PHYEND_DISABLE field. */ #define RADIO_SHORTS_PHYEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_PHYEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 19 : Shortcut between RXREADY event and START task */ +/* Bit 19 : Shortcut between event RXREADY and task START */ #define RADIO_SHORTS_RXREADY_START_Pos (19UL) /*!< Position of RXREADY_START field. */ #define RADIO_SHORTS_RXREADY_START_Msk (0x1UL << RADIO_SHORTS_RXREADY_START_Pos) /*!< Bit mask of RXREADY_START field. */ #define RADIO_SHORTS_RXREADY_START_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_RXREADY_START_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 18 : Shortcut between TXREADY event and START task */ +/* Bit 18 : Shortcut between event TXREADY and task START */ #define RADIO_SHORTS_TXREADY_START_Pos (18UL) /*!< Position of TXREADY_START field. */ #define RADIO_SHORTS_TXREADY_START_Msk (0x1UL << RADIO_SHORTS_TXREADY_START_Pos) /*!< Bit mask of TXREADY_START field. */ #define RADIO_SHORTS_TXREADY_START_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_TXREADY_START_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 17 : Shortcut between CCAIDLE event and STOP task */ +/* Bit 17 : Shortcut between event CCAIDLE and task STOP */ #define RADIO_SHORTS_CCAIDLE_STOP_Pos (17UL) /*!< Position of CCAIDLE_STOP field. */ #define RADIO_SHORTS_CCAIDLE_STOP_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_STOP_Pos) /*!< Bit mask of CCAIDLE_STOP field. */ #define RADIO_SHORTS_CCAIDLE_STOP_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_CCAIDLE_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 16 : Shortcut between EDEND event and DISABLE task */ +/* Bit 16 : Shortcut between event EDEND and task DISABLE */ #define RADIO_SHORTS_EDEND_DISABLE_Pos (16UL) /*!< Position of EDEND_DISABLE field. */ #define RADIO_SHORTS_EDEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_EDEND_DISABLE_Pos) /*!< Bit mask of EDEND_DISABLE field. */ #define RADIO_SHORTS_EDEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_EDEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 15 : Shortcut between READY event and EDSTART task */ +/* Bit 15 : Shortcut between event READY and task EDSTART */ #define RADIO_SHORTS_READY_EDSTART_Pos (15UL) /*!< Position of READY_EDSTART field. */ #define RADIO_SHORTS_READY_EDSTART_Msk (0x1UL << RADIO_SHORTS_READY_EDSTART_Pos) /*!< Bit mask of READY_EDSTART field. */ #define RADIO_SHORTS_READY_EDSTART_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_READY_EDSTART_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 14 : Shortcut between FRAMESTART event and BCSTART task */ +/* Bit 14 : Shortcut between event FRAMESTART and task BCSTART */ #define RADIO_SHORTS_FRAMESTART_BCSTART_Pos (14UL) /*!< Position of FRAMESTART_BCSTART field. */ #define RADIO_SHORTS_FRAMESTART_BCSTART_Msk (0x1UL << RADIO_SHORTS_FRAMESTART_BCSTART_Pos) /*!< Bit mask of FRAMESTART_BCSTART field. */ #define RADIO_SHORTS_FRAMESTART_BCSTART_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_FRAMESTART_BCSTART_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 13 : Shortcut between CCABUSY event and DISABLE task */ +/* Bit 13 : Shortcut between event CCABUSY and task DISABLE */ #define RADIO_SHORTS_CCABUSY_DISABLE_Pos (13UL) /*!< Position of CCABUSY_DISABLE field. */ #define RADIO_SHORTS_CCABUSY_DISABLE_Msk (0x1UL << RADIO_SHORTS_CCABUSY_DISABLE_Pos) /*!< Bit mask of CCABUSY_DISABLE field. */ #define RADIO_SHORTS_CCABUSY_DISABLE_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_CCABUSY_DISABLE_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 12 : Shortcut between CCAIDLE event and TXEN task */ +/* Bit 12 : Shortcut between event CCAIDLE and task TXEN */ #define RADIO_SHORTS_CCAIDLE_TXEN_Pos (12UL) /*!< Position of CCAIDLE_TXEN field. */ #define RADIO_SHORTS_CCAIDLE_TXEN_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_TXEN_Pos) /*!< Bit mask of CCAIDLE_TXEN field. */ #define RADIO_SHORTS_CCAIDLE_TXEN_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_CCAIDLE_TXEN_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 11 : Shortcut between RXREADY event and CCASTART task */ +/* Bit 11 : Shortcut between event RXREADY and task CCASTART */ #define RADIO_SHORTS_RXREADY_CCASTART_Pos (11UL) /*!< Position of RXREADY_CCASTART field. */ #define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos) /*!< Bit mask of RXREADY_CCASTART field. */ #define RADIO_SHORTS_RXREADY_CCASTART_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_RXREADY_CCASTART_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */ +/* Bit 8 : Shortcut between event DISABLED and task RSSISTOP */ #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 6 : Shortcut between ADDRESS event and BCSTART task */ +/* Bit 6 : Shortcut between event ADDRESS and task BCSTART */ #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 5 : Shortcut between END event and START task */ +/* Bit 5 : Shortcut between event END and task START */ #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */ +/* Bit 4 : Shortcut between event ADDRESS and task RSSISTART */ #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between DISABLED event and RXEN task */ +/* Bit 3 : Shortcut between event DISABLED and task RXEN */ #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between DISABLED event and TXEN task */ +/* Bit 2 : Shortcut between event DISABLED and task TXEN */ #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between END event and DISABLE task */ +/* Bit 1 : Shortcut between event END and task DISABLE */ #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between READY event and START task */ +/* Bit 0 : Shortcut between event READY and task START */ #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */ @@ -10179,154 +10457,161 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_INTENSET */ /* Description: Enable interrupt */ -/* Bit 27 : Write '1' to enable interrupt for PHYEND event */ +/* Bit 27 : Write '1' to enable interrupt for event PHYEND */ #define RADIO_INTENSET_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */ #define RADIO_INTENSET_PHYEND_Msk (0x1UL << RADIO_INTENSET_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ #define RADIO_INTENSET_PHYEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_PHYEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_PHYEND_Set (1UL) /*!< Enable */ -/* Bit 23 : Write '1' to enable interrupt for MHRMATCH event */ +/* Bit 26 : Write '1' to enable interrupt for event SYNC */ +#define RADIO_INTENSET_SYNC_Pos (26UL) /*!< Position of SYNC field. */ +#define RADIO_INTENSET_SYNC_Msk (0x1UL << RADIO_INTENSET_SYNC_Pos) /*!< Bit mask of SYNC field. */ +#define RADIO_INTENSET_SYNC_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_SYNC_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_SYNC_Set (1UL) /*!< Enable */ + +/* Bit 23 : Write '1' to enable interrupt for event MHRMATCH */ #define RADIO_INTENSET_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ #define RADIO_INTENSET_MHRMATCH_Msk (0x1UL << RADIO_INTENSET_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ #define RADIO_INTENSET_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_MHRMATCH_Set (1UL) /*!< Enable */ -/* Bit 22 : Write '1' to enable interrupt for RXREADY event */ +/* Bit 22 : Write '1' to enable interrupt for event RXREADY */ #define RADIO_INTENSET_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ #define RADIO_INTENSET_RXREADY_Msk (0x1UL << RADIO_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ #define RADIO_INTENSET_RXREADY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_RXREADY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_RXREADY_Set (1UL) /*!< Enable */ -/* Bit 21 : Write '1' to enable interrupt for TXREADY event */ +/* Bit 21 : Write '1' to enable interrupt for event TXREADY */ #define RADIO_INTENSET_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */ #define RADIO_INTENSET_TXREADY_Msk (0x1UL << RADIO_INTENSET_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ #define RADIO_INTENSET_TXREADY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_TXREADY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_TXREADY_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for RATEBOOST event */ +/* Bit 20 : Write '1' to enable interrupt for event RATEBOOST */ #define RADIO_INTENSET_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ #define RADIO_INTENSET_RATEBOOST_Msk (0x1UL << RADIO_INTENSET_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ #define RADIO_INTENSET_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_RATEBOOST_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for CCASTOPPED event */ +/* Bit 19 : Write '1' to enable interrupt for event CCASTOPPED */ #define RADIO_INTENSET_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ #define RADIO_INTENSET_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ #define RADIO_INTENSET_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_CCASTOPPED_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for CCABUSY event */ +/* Bit 18 : Write '1' to enable interrupt for event CCABUSY */ #define RADIO_INTENSET_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ #define RADIO_INTENSET_CCABUSY_Msk (0x1UL << RADIO_INTENSET_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ #define RADIO_INTENSET_CCABUSY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_CCABUSY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_CCABUSY_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for CCAIDLE event */ +/* Bit 17 : Write '1' to enable interrupt for event CCAIDLE */ #define RADIO_INTENSET_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ #define RADIO_INTENSET_CCAIDLE_Msk (0x1UL << RADIO_INTENSET_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ #define RADIO_INTENSET_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_CCAIDLE_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable interrupt for EDSTOPPED event */ +/* Bit 16 : Write '1' to enable interrupt for event EDSTOPPED */ #define RADIO_INTENSET_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ #define RADIO_INTENSET_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ #define RADIO_INTENSET_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_EDSTOPPED_Set (1UL) /*!< Enable */ -/* Bit 15 : Write '1' to enable interrupt for EDEND event */ +/* Bit 15 : Write '1' to enable interrupt for event EDEND */ #define RADIO_INTENSET_EDEND_Pos (15UL) /*!< Position of EDEND field. */ #define RADIO_INTENSET_EDEND_Msk (0x1UL << RADIO_INTENSET_EDEND_Pos) /*!< Bit mask of EDEND field. */ #define RADIO_INTENSET_EDEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_EDEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_EDEND_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to enable interrupt for FRAMESTART event */ +/* Bit 14 : Write '1' to enable interrupt for event FRAMESTART */ #define RADIO_INTENSET_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */ #define RADIO_INTENSET_FRAMESTART_Msk (0x1UL << RADIO_INTENSET_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ #define RADIO_INTENSET_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_FRAMESTART_Set (1UL) /*!< Enable */ -/* Bit 13 : Write '1' to enable interrupt for CRCERROR event */ +/* Bit 13 : Write '1' to enable interrupt for event CRCERROR */ #define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ #define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to enable interrupt for CRCOK event */ +/* Bit 12 : Write '1' to enable interrupt for event CRCOK */ #define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ #define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to enable interrupt for BCMATCH event */ +/* Bit 10 : Write '1' to enable interrupt for event BCMATCH */ #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for RSSIEND event */ +/* Bit 7 : Write '1' to enable interrupt for event RSSIEND */ #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for DEVMISS event */ +/* Bit 6 : Write '1' to enable interrupt for event DEVMISS */ #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for DEVMATCH event */ +/* Bit 5 : Write '1' to enable interrupt for event DEVMATCH */ #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for DISABLED event */ +/* Bit 4 : Write '1' to enable interrupt for event DISABLED */ #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for END event */ +/* Bit 3 : Write '1' to enable interrupt for event END */ #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for PAYLOAD event */ +/* Bit 2 : Write '1' to enable interrupt for event PAYLOAD */ #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for ADDRESS event */ +/* Bit 1 : Write '1' to enable interrupt for event ADDRESS */ #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for READY event */ +/* Bit 0 : Write '1' to enable interrupt for event READY */ #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -10336,154 +10621,161 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 27 : Write '1' to disable interrupt for PHYEND event */ +/* Bit 27 : Write '1' to disable interrupt for event PHYEND */ #define RADIO_INTENCLR_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */ #define RADIO_INTENCLR_PHYEND_Msk (0x1UL << RADIO_INTENCLR_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ #define RADIO_INTENCLR_PHYEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_PHYEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_PHYEND_Clear (1UL) /*!< Disable */ -/* Bit 23 : Write '1' to disable interrupt for MHRMATCH event */ +/* Bit 26 : Write '1' to disable interrupt for event SYNC */ +#define RADIO_INTENCLR_SYNC_Pos (26UL) /*!< Position of SYNC field. */ +#define RADIO_INTENCLR_SYNC_Msk (0x1UL << RADIO_INTENCLR_SYNC_Pos) /*!< Bit mask of SYNC field. */ +#define RADIO_INTENCLR_SYNC_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_SYNC_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_SYNC_Clear (1UL) /*!< Disable */ + +/* Bit 23 : Write '1' to disable interrupt for event MHRMATCH */ #define RADIO_INTENCLR_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ #define RADIO_INTENCLR_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ #define RADIO_INTENCLR_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_MHRMATCH_Clear (1UL) /*!< Disable */ -/* Bit 22 : Write '1' to disable interrupt for RXREADY event */ +/* Bit 22 : Write '1' to disable interrupt for event RXREADY */ #define RADIO_INTENCLR_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ #define RADIO_INTENCLR_RXREADY_Msk (0x1UL << RADIO_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ #define RADIO_INTENCLR_RXREADY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_RXREADY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_RXREADY_Clear (1UL) /*!< Disable */ -/* Bit 21 : Write '1' to disable interrupt for TXREADY event */ +/* Bit 21 : Write '1' to disable interrupt for event TXREADY */ #define RADIO_INTENCLR_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */ #define RADIO_INTENCLR_TXREADY_Msk (0x1UL << RADIO_INTENCLR_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ #define RADIO_INTENCLR_TXREADY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_TXREADY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_TXREADY_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for RATEBOOST event */ +/* Bit 20 : Write '1' to disable interrupt for event RATEBOOST */ #define RADIO_INTENCLR_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ #define RADIO_INTENCLR_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ #define RADIO_INTENCLR_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_RATEBOOST_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for CCASTOPPED event */ +/* Bit 19 : Write '1' to disable interrupt for event CCASTOPPED */ #define RADIO_INTENCLR_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ #define RADIO_INTENCLR_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ #define RADIO_INTENCLR_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_CCASTOPPED_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for CCABUSY event */ +/* Bit 18 : Write '1' to disable interrupt for event CCABUSY */ #define RADIO_INTENCLR_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ #define RADIO_INTENCLR_CCABUSY_Msk (0x1UL << RADIO_INTENCLR_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ #define RADIO_INTENCLR_CCABUSY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_CCABUSY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_CCABUSY_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for CCAIDLE event */ +/* Bit 17 : Write '1' to disable interrupt for event CCAIDLE */ #define RADIO_INTENCLR_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ #define RADIO_INTENCLR_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ #define RADIO_INTENCLR_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_CCAIDLE_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable interrupt for EDSTOPPED event */ +/* Bit 16 : Write '1' to disable interrupt for event EDSTOPPED */ #define RADIO_INTENCLR_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ #define RADIO_INTENCLR_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ #define RADIO_INTENCLR_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_EDSTOPPED_Clear (1UL) /*!< Disable */ -/* Bit 15 : Write '1' to disable interrupt for EDEND event */ +/* Bit 15 : Write '1' to disable interrupt for event EDEND */ #define RADIO_INTENCLR_EDEND_Pos (15UL) /*!< Position of EDEND field. */ #define RADIO_INTENCLR_EDEND_Msk (0x1UL << RADIO_INTENCLR_EDEND_Pos) /*!< Bit mask of EDEND field. */ #define RADIO_INTENCLR_EDEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_EDEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_EDEND_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to disable interrupt for FRAMESTART event */ +/* Bit 14 : Write '1' to disable interrupt for event FRAMESTART */ #define RADIO_INTENCLR_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */ #define RADIO_INTENCLR_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ #define RADIO_INTENCLR_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_FRAMESTART_Clear (1UL) /*!< Disable */ -/* Bit 13 : Write '1' to disable interrupt for CRCERROR event */ +/* Bit 13 : Write '1' to disable interrupt for event CRCERROR */ #define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ #define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to disable interrupt for CRCOK event */ +/* Bit 12 : Write '1' to disable interrupt for event CRCOK */ #define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ #define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to disable interrupt for BCMATCH event */ +/* Bit 10 : Write '1' to disable interrupt for event BCMATCH */ #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for RSSIEND event */ +/* Bit 7 : Write '1' to disable interrupt for event RSSIEND */ #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for DEVMISS event */ +/* Bit 6 : Write '1' to disable interrupt for event DEVMISS */ #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for DEVMATCH event */ +/* Bit 5 : Write '1' to disable interrupt for event DEVMATCH */ #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for DISABLED event */ +/* Bit 4 : Write '1' to disable interrupt for event DISABLED */ #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for END event */ +/* Bit 3 : Write '1' to disable interrupt for event END */ #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for PAYLOAD event */ +/* Bit 2 : Write '1' to disable interrupt for event PAYLOAD */ #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for ADDRESS event */ +/* Bit 1 : Write '1' to disable interrupt for event ADDRESS */ #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for READY event */ +/* Bit 0 : Write '1' to disable interrupt for event READY */ #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -10570,12 +10862,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define RADIO_TXPOWER_TXPOWER_Pos7dBm (0x7UL) /*!< +7 dBm */ #define RADIO_TXPOWER_TXPOWER_Pos8dBm (0x8UL) /*!< +8 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xE2UL) /*!< Deprecated enumerator - -40 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */ -#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xFFUL) /*!< Deprecated enumerator - -40 dBm */ /* Register: RADIO_MODE */ /* Description: Data rate and modulation */ @@ -10848,14 +11140,14 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */ /* Register: RADIO_DAB */ -/* Description: Description collection[n]: Device address base segment n */ +/* Description: Description collection: Device address base segment n */ /* Bits 31..0 : Device address base segment n */ #define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */ #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */ /* Register: RADIO_DAP */ -/* Description: Description collection[n]: Device address prefix n */ +/* Description: Description collection: Device address prefix n */ /* Bits 15..0 : Device address prefix n */ #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ @@ -10944,6 +11236,20 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */ #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */ +/* Register: RADIO_MHRMATCHCONF */ +/* Description: Search pattern configuration */ + +/* Bits 31..0 : Search pattern configuration */ +#define RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos (0UL) /*!< Position of MHRMATCHCONF field. */ +#define RADIO_MHRMATCHCONF_MHRMATCHCONF_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos) /*!< Bit mask of MHRMATCHCONF field. */ + +/* Register: RADIO_MHRMATCHMAS */ +/* Description: Pattern mask */ + +/* Bits 31..0 : Pattern mask */ +#define RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos (0UL) /*!< Position of MHRMATCHMAS field. */ +#define RADIO_MHRMATCHMAS_MHRMATCHMAS_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos) /*!< Bit mask of MHRMATCHMAS field. */ + /* Register: RADIO_MODECNF0 */ /* Description: Radio mode configuration register 0 */ @@ -10957,8 +11263,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Radio ramp-up time */ #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */ #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */ -#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */ -#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */ +#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 */ +#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information */ /* Register: RADIO_SFD */ /* Description: IEEE 802.15.4 start of frame delimiter */ @@ -11021,28 +11327,32 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: RNG_TASKS_START */ /* Description: Task starting the random number generator */ -/* Bit 0 : */ +/* Bit 0 : Task starting the random number generator */ #define RNG_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define RNG_TASKS_START_TASKS_START_Msk (0x1UL << RNG_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define RNG_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: RNG_TASKS_STOP */ /* Description: Task stopping the random number generator */ -/* Bit 0 : */ +/* Bit 0 : Task stopping the random number generator */ #define RNG_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define RNG_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RNG_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define RNG_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: RNG_EVENTS_VALRDY */ /* Description: Event being generated for every new random number written to the VALUE register */ -/* Bit 0 : */ +/* Bit 0 : Event being generated for every new random number written to the VALUE register */ #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos (0UL) /*!< Position of EVENTS_VALRDY field. */ #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Msk (0x1UL << RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos) /*!< Bit mask of EVENTS_VALRDY field. */ +#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_NotGenerated (0UL) /*!< Event not generated */ +#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Generated (1UL) /*!< Event generated */ /* Register: RNG_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 0 : Shortcut between VALRDY event and STOP task */ +/* Bit 0 : Shortcut between event VALRDY and task STOP */ #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ @@ -11051,7 +11361,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: RNG_INTENSET */ /* Description: Enable interrupt */ -/* Bit 0 : Write '1' to enable interrupt for VALRDY event */ +/* Bit 0 : Write '1' to enable interrupt for event VALRDY */ #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */ @@ -11061,7 +11371,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: RNG_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 0 : Write '1' to disable interrupt for VALRDY event */ +/* Bit 0 : Write '1' to disable interrupt for event VALRDY */ #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */ @@ -11091,91 +11401,101 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: RTC_TASKS_START */ /* Description: Start RTC COUNTER */ -/* Bit 0 : */ +/* Bit 0 : Start RTC COUNTER */ #define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: RTC_TASKS_STOP */ /* Description: Stop RTC COUNTER */ -/* Bit 0 : */ +/* Bit 0 : Stop RTC COUNTER */ #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: RTC_TASKS_CLEAR */ /* Description: Clear RTC COUNTER */ -/* Bit 0 : */ +/* Bit 0 : Clear RTC COUNTER */ #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ +#define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ /* Register: RTC_TASKS_TRIGOVRFLW */ /* Description: Set COUNTER to 0xFFFFF0 */ -/* Bit 0 : */ +/* Bit 0 : Set COUNTER to 0xFFFFF0 */ #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */ #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */ +#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */ /* Register: RTC_EVENTS_TICK */ /* Description: Event on COUNTER increment */ -/* Bit 0 : */ +/* Bit 0 : Event on COUNTER increment */ #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */ #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */ +#define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */ +#define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */ /* Register: RTC_EVENTS_OVRFLW */ /* Description: Event on COUNTER overflow */ -/* Bit 0 : */ +/* Bit 0 : Event on COUNTER overflow */ #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */ #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */ /* Register: RTC_EVENTS_COMPARE */ -/* Description: Description collection[n]: Compare event on CC[n] match */ +/* Description: Description collection: Compare event on CC[n] match */ -/* Bit 0 : */ +/* Bit 0 : Compare event on CC[n] match */ #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ /* Register: RTC_INTENSET */ /* Description: Enable interrupt */ -/* Bit 19 : Write '1' to enable interrupt for COMPARE[3] event */ +/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */ +/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for COMPARE[1] event */ +/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable interrupt for COMPARE[0] event */ +/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for OVRFLW event */ +/* Bit 1 : Write '1' to enable interrupt for event OVRFLW */ #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for TICK event */ +/* Bit 0 : Write '1' to enable interrupt for event TICK */ #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ @@ -11185,42 +11505,42 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: RTC_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 19 : Write '1' to disable interrupt for COMPARE[3] event */ +/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */ +/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for COMPARE[1] event */ +/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable interrupt for COMPARE[0] event */ +/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for OVRFLW event */ +/* Bit 1 : Write '1' to disable interrupt for event OVRFLW */ #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for TICK event */ +/* Bit 0 : Write '1' to disable interrupt for event TICK */ #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ @@ -11230,81 +11550,81 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: RTC_EVTEN */ /* Description: Enable or disable event routing */ -/* Bit 19 : Enable or disable event routing for COMPARE[3] event */ +/* Bit 19 : Enable or disable event routing for event COMPARE[3] */ #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Disable */ -/* Bit 18 : Enable or disable event routing for COMPARE[2] event */ +/* Bit 18 : Enable or disable event routing for event COMPARE[2] */ #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Disable */ -/* Bit 17 : Enable or disable event routing for COMPARE[1] event */ +/* Bit 17 : Enable or disable event routing for event COMPARE[1] */ #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Disable */ -/* Bit 16 : Enable or disable event routing for COMPARE[0] event */ +/* Bit 16 : Enable or disable event routing for event COMPARE[0] */ #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Disable */ -/* Bit 1 : Enable or disable event routing for OVRFLW event */ +/* Bit 1 : Enable or disable event routing for event OVRFLW */ #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Disable */ -/* Bit 0 : Enable or disable event routing for TICK event */ +/* Bit 0 : Enable or disable event routing for event TICK */ #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Disable */ /* Register: RTC_EVTENSET */ /* Description: Enable event routing */ -/* Bit 19 : Write '1' to enable event routing for COMPARE[3] event */ +/* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */ #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable event routing for COMPARE[2] event */ +/* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */ #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable event routing for COMPARE[1] event */ +/* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */ #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable event routing for COMPARE[0] event */ +/* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */ #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable event routing for OVRFLW event */ +/* Bit 1 : Write '1' to enable event routing for event OVRFLW */ #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable event routing for TICK event */ +/* Bit 0 : Write '1' to enable event routing for event TICK */ #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ @@ -11314,42 +11634,42 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: RTC_EVTENCLR */ /* Description: Disable event routing */ -/* Bit 19 : Write '1' to disable event routing for COMPARE[3] event */ +/* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */ #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable event routing for COMPARE[2] event */ +/* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */ #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable event routing for COMPARE[1] event */ +/* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */ #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable event routing for COMPARE[0] event */ +/* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */ #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable event routing for OVRFLW event */ +/* Bit 1 : Write '1' to disable event routing for event OVRFLW */ #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable event routing for TICK event */ +/* Bit 0 : Write '1' to disable event routing for event TICK */ #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ @@ -11364,14 +11684,14 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ /* Register: RTC_PRESCALER */ -/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */ +/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. */ /* Bits 11..0 : Prescaler value */ #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ /* Register: RTC_CC */ -/* Description: Description collection[n]: Compare register n */ +/* Description: Description collection: Compare register n */ /* Bits 23..0 : Compare value */ #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ @@ -11384,217 +11704,237 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: SAADC_TASKS_START */ /* Description: Starts the SAADC and prepares the result buffer in RAM */ -/* Bit 0 : */ +/* Bit 0 : Starts the SAADC and prepares the result buffer in RAM */ #define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define SAADC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: SAADC_TASKS_SAMPLE */ /* Description: Takes one SAADC sample */ -/* Bit 0 : */ +/* Bit 0 : Takes one SAADC sample */ #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ +#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */ /* Register: SAADC_TASKS_STOP */ /* Description: Stops the SAADC and terminates all on-going conversions */ -/* Bit 0 : */ +/* Bit 0 : Stops the SAADC and terminates all on-going conversions */ #define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define SAADC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: SAADC_TASKS_CALIBRATEOFFSET */ /* Description: Starts offset auto-calibration */ -/* Bit 0 : */ +/* Bit 0 : Starts offset auto-calibration */ #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */ #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */ +#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (1UL) /*!< Trigger task */ /* Register: SAADC_EVENTS_STARTED */ /* Description: The SAADC has started */ -/* Bit 0 : */ +/* Bit 0 : The SAADC has started */ #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_END */ /* Description: The SAADC has filled up the result buffer */ -/* Bit 0 : */ +/* Bit 0 : The SAADC has filled up the result buffer */ #define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_DONE */ /* Description: A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. */ -/* Bit 0 : */ +/* Bit 0 : A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. */ #define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ #define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ +#define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_RESULTDONE */ /* Description: Result ready for transfer to RAM */ -/* Bit 0 : */ +/* Bit 0 : Result ready for transfer to RAM */ #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */ #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */ +#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_CALIBRATEDONE */ /* Description: Calibration is complete */ -/* Bit 0 : */ +/* Bit 0 : Calibration is complete */ #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */ #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */ +#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_STOPPED */ /* Description: The SAADC has stopped */ -/* Bit 0 : */ +/* Bit 0 : The SAADC has stopped */ #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_CH_LIMITH */ -/* Description: Description cluster[n]: Last result is equal or above CH[n].LIMIT.HIGH */ +/* Description: Description cluster: Last result is equal or above CH[n].LIMIT.HIGH */ -/* Bit 0 : */ +/* Bit 0 : Last result is equal or above CH[n].LIMIT.HIGH */ #define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */ #define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */ +#define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_CH_LIMITL */ -/* Description: Description cluster[n]: Last result is equal or below CH[n].LIMIT.LOW */ +/* Description: Description cluster: Last result is equal or below CH[n].LIMIT.LOW */ -/* Bit 0 : */ +/* Bit 0 : Last result is equal or below CH[n].LIMIT.LOW */ #define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */ #define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */ +#define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (1UL) /*!< Event generated */ /* Register: SAADC_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */ +/* Bit 21 : Enable or disable interrupt for event CH7LIMITL */ #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ #define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */ +/* Bit 20 : Enable or disable interrupt for event CH7LIMITH */ #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ #define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */ +/* Bit 19 : Enable or disable interrupt for event CH6LIMITL */ #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ #define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */ +/* Bit 18 : Enable or disable interrupt for event CH6LIMITH */ #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ #define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */ +/* Bit 17 : Enable or disable interrupt for event CH5LIMITL */ #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ #define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */ +/* Bit 16 : Enable or disable interrupt for event CH5LIMITH */ #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ #define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */ +/* Bit 15 : Enable or disable interrupt for event CH4LIMITL */ #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ #define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */ +/* Bit 14 : Enable or disable interrupt for event CH4LIMITH */ #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ #define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */ +/* Bit 13 : Enable or disable interrupt for event CH3LIMITL */ #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ #define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */ +/* Bit 12 : Enable or disable interrupt for event CH3LIMITH */ #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ #define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */ +/* Bit 11 : Enable or disable interrupt for event CH2LIMITL */ #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ #define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */ +/* Bit 10 : Enable or disable interrupt for event CH2LIMITH */ #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ #define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */ +/* Bit 9 : Enable or disable interrupt for event CH1LIMITL */ #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ #define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */ +/* Bit 8 : Enable or disable interrupt for event CH1LIMITH */ #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ #define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */ +/* Bit 7 : Enable or disable interrupt for event CH0LIMITL */ #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ #define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */ +/* Bit 6 : Enable or disable interrupt for event CH0LIMITH */ #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ #define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for STOPPED event */ +/* Bit 5 : Enable or disable interrupt for event STOPPED */ #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */ +/* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */ #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for RESULTDONE event */ +/* Bit 3 : Enable or disable interrupt for event RESULTDONE */ #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ #define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for DONE event */ +/* Bit 2 : Enable or disable interrupt for event DONE */ #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */ #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ #define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for END event */ +/* Bit 1 : Enable or disable interrupt for event END */ #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */ #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */ #define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for STARTED event */ +/* Bit 0 : Enable or disable interrupt for event STARTED */ #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */ @@ -11603,154 +11943,154 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: SAADC_INTENSET */ /* Description: Enable interrupt */ -/* Bit 21 : Write '1' to enable interrupt for CH[7].LIMITL event */ +/* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */ #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for CH[7].LIMITH event */ +/* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */ #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for CH[6].LIMITL event */ +/* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */ #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for CH[6].LIMITH event */ +/* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */ #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for CH[5].LIMITL event */ +/* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */ #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable interrupt for CH[5].LIMITH event */ +/* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */ #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */ -/* Bit 15 : Write '1' to enable interrupt for CH[4].LIMITL event */ +/* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */ #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to enable interrupt for CH[4].LIMITH event */ +/* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */ #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */ -/* Bit 13 : Write '1' to enable interrupt for CH[3].LIMITL event */ +/* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */ #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to enable interrupt for CH[3].LIMITH event */ +/* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */ #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */ -/* Bit 11 : Write '1' to enable interrupt for CH[2].LIMITL event */ +/* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */ #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to enable interrupt for CH[2].LIMITH event */ +/* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */ #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for CH[1].LIMITL event */ +/* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */ #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for CH[1].LIMITH event */ +/* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */ #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for CH[0].LIMITL event */ +/* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */ #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for CH[0].LIMITH event */ +/* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */ #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 5 : Write '1' to enable interrupt for event STOPPED */ #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for CALIBRATEDONE event */ +/* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */ #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for RESULTDONE event */ +/* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */ #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for DONE event */ +/* Bit 2 : Write '1' to enable interrupt for event DONE */ #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */ #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for END event */ +/* Bit 1 : Write '1' to enable interrupt for event END */ #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */ #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for STARTED event */ +/* Bit 0 : Write '1' to enable interrupt for event STARTED */ #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -11760,154 +12100,154 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: SAADC_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 21 : Write '1' to disable interrupt for CH[7].LIMITL event */ +/* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */ #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for CH[7].LIMITH event */ +/* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */ #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for CH[6].LIMITL event */ +/* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */ #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for CH[6].LIMITH event */ +/* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */ #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for CH[5].LIMITL event */ +/* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */ #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable interrupt for CH[5].LIMITH event */ +/* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */ #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 15 : Write '1' to disable interrupt for CH[4].LIMITL event */ +/* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */ #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to disable interrupt for CH[4].LIMITH event */ +/* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */ #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 13 : Write '1' to disable interrupt for CH[3].LIMITL event */ +/* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */ #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to disable interrupt for CH[3].LIMITH event */ +/* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */ #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 11 : Write '1' to disable interrupt for CH[2].LIMITL event */ +/* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */ #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to disable interrupt for CH[2].LIMITH event */ +/* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */ #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for CH[1].LIMITL event */ +/* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */ #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for CH[1].LIMITH event */ +/* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */ #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for CH[0].LIMITL event */ +/* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */ #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for CH[0].LIMITH event */ +/* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */ #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 5 : Write '1' to disable interrupt for event STOPPED */ #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for CALIBRATEDONE event */ +/* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */ #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for RESULTDONE event */ +/* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */ #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for DONE event */ +/* Bit 2 : Write '1' to disable interrupt for event DONE */ #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */ #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for END event */ +/* Bit 1 : Write '1' to disable interrupt for event END */ #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for STARTED event */ +/* Bit 0 : Write '1' to disable interrupt for event STARTED */ #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -11933,7 +12273,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SAADC */ /* Register: SAADC_CH_PSELP */ -/* Description: Description cluster[n]: Input positive pin selection for CH[n] */ +/* Description: Description cluster: Input positive pin selection for CH[n] */ /* Bits 4..0 : Analog positive input channel */ #define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */ @@ -11951,7 +12291,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define SAADC_CH_PSELP_PSELP_VDDHDIV5 (0x0DUL) /*!< VDDH/5 */ /* Register: SAADC_CH_PSELN */ -/* Description: Description cluster[n]: Input negative pin selection for CH[n] */ +/* Description: Description cluster: Input negative pin selection for CH[n] */ /* Bits 4..0 : Analog negative input, enables differential channel */ #define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */ @@ -11969,7 +12309,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define SAADC_CH_PSELN_PSELN_VDDHDIV5 (0x0DUL) /*!< VDDH/5 */ /* Register: SAADC_CH_CONFIG */ -/* Description: Description cluster[n]: Input configuration for CH[n] */ +/* Description: Description cluster: Input configuration for CH[n] */ /* Bit 24 : Enable burst mode */ #define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */ @@ -12028,7 +12368,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */ /* Register: SAADC_CH_LIMIT */ -/* Description: Description cluster[n]: High/low limits for event monitoring of a channel */ +/* Description: Description cluster: High/low limits for event monitoring of a channel */ /* Bits 31..16 : High level limit */ #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */ @@ -12106,14 +12446,16 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: SPI_EVENTS_READY */ /* Description: TXD byte sent and RXD byte received */ -/* Bit 0 : */ +/* Bit 0 : TXD byte sent and RXD byte received */ #define SPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ #define SPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << SPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define SPI_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define SPI_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ /* Register: SPI_INTENSET */ /* Description: Enable interrupt */ -/* Bit 2 : Write '1' to enable interrupt for READY event */ +/* Bit 2 : Write '1' to enable interrupt for event READY */ #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -12123,7 +12465,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: SPI_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 2 : Write '1' to disable interrupt for READY event */ +/* Bit 2 : Write '1' to disable interrupt for event READY */ #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -12200,7 +12542,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: SPI_TXD */ /* Description: TXD register */ -/* Bits 7..0 : TX data to send. Double buffered */ +/* Bits 7..0 : TX data to send. Double buffered. */ #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ @@ -12246,70 +12588,84 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: SPIM_TASKS_START */ /* Description: Start SPI transaction */ -/* Bit 0 : */ +/* Bit 0 : Start SPI transaction */ #define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define SPIM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: SPIM_TASKS_STOP */ /* Description: Stop SPI transaction */ -/* Bit 0 : */ +/* Bit 0 : Stop SPI transaction */ #define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: SPIM_TASKS_SUSPEND */ /* Description: Suspend SPI transaction */ -/* Bit 0 : */ +/* Bit 0 : Suspend SPI transaction */ #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ /* Register: SPIM_TASKS_RESUME */ /* Description: Resume SPI transaction */ -/* Bit 0 : */ +/* Bit 0 : Resume SPI transaction */ #define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ #define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ /* Register: SPIM_EVENTS_STOPPED */ /* Description: SPI transaction has stopped */ -/* Bit 0 : */ +/* Bit 0 : SPI transaction has stopped */ #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: SPIM_EVENTS_ENDRX */ /* Description: End of RXD buffer reached */ -/* Bit 0 : */ +/* Bit 0 : End of RXD buffer reached */ #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ /* Register: SPIM_EVENTS_END */ /* Description: End of RXD buffer and TXD buffer reached */ -/* Bit 0 : */ +/* Bit 0 : End of RXD buffer and TXD buffer reached */ #define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ /* Register: SPIM_EVENTS_ENDTX */ /* Description: End of TXD buffer reached */ -/* Bit 0 : */ +/* Bit 0 : End of TXD buffer reached */ #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ /* Register: SPIM_EVENTS_STARTED */ /* Description: Transaction started */ -/* Bit 0 : */ +/* Bit 0 : Transaction started */ #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ /* Register: SPIM_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 17 : Shortcut between END event and START task */ +/* Bit 17 : Shortcut between event END and task START */ #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ @@ -12318,35 +12674,35 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: SPIM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 19 : Write '1' to enable interrupt for STARTED event */ +/* Bit 19 : Write '1' to enable interrupt for event STARTED */ #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for ENDTX event */ +/* Bit 8 : Write '1' to enable interrupt for event ENDTX */ #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for END event */ +/* Bit 6 : Write '1' to enable interrupt for event END */ #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to enable interrupt for event ENDRX */ #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -12356,35 +12712,35 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: SPIM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 19 : Write '1' to disable interrupt for STARTED event */ +/* Bit 19 : Write '1' to disable interrupt for event STARTED */ #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for ENDTX event */ +/* Bit 8 : Write '1' to disable interrupt for event ENDTX */ #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for END event */ +/* Bit 6 : Write '1' to disable interrupt for event END */ #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to disable interrupt for event ENDRX */ #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -12392,7 +12748,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ /* Register: SPIM_STALLSTAT */ -/* Description: Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. */ +/* Description: Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurs and can be cleared (set to NOSTALL) by the CPU. */ /* Bit 1 : Stall status for EasyDMA RAM writes */ #define SPIM_STALLSTAT_RX_Pos (1UL) /*!< Position of RX field. */ @@ -12641,42 +12997,50 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: SPIS_TASKS_ACQUIRE */ /* Description: Acquire SPI semaphore */ -/* Bit 0 : */ +/* Bit 0 : Acquire SPI semaphore */ #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */ #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */ +#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL) /*!< Trigger task */ /* Register: SPIS_TASKS_RELEASE */ /* Description: Release SPI semaphore, enabling the SPI slave to acquire it */ -/* Bit 0 : */ +/* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */ #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */ #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */ +#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL) /*!< Trigger task */ /* Register: SPIS_EVENTS_END */ /* Description: Granted transaction completed */ -/* Bit 0 : */ +/* Bit 0 : Granted transaction completed */ #define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define SPIS_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ /* Register: SPIS_EVENTS_ENDRX */ /* Description: End of RXD buffer reached */ -/* Bit 0 : */ +/* Bit 0 : End of RXD buffer reached */ #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ /* Register: SPIS_EVENTS_ACQUIRED */ /* Description: Semaphore acquired */ -/* Bit 0 : */ +/* Bit 0 : Semaphore acquired */ #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */ #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL) /*!< Event not generated */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL) /*!< Event generated */ /* Register: SPIS_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 2 : Shortcut between END event and ACQUIRE task */ +/* Bit 2 : Shortcut between event END and task ACQUIRE */ #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */ @@ -12685,21 +13049,21 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: SPIS_INTENSET */ /* Description: Enable interrupt */ -/* Bit 10 : Write '1' to enable interrupt for ACQUIRED event */ +/* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */ #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to enable interrupt for event ENDRX */ #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for END event */ +/* Bit 1 : Write '1' to enable interrupt for event END */ #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ @@ -12709,21 +13073,21 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: SPIS_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 10 : Write '1' to disable interrupt for ACQUIRED event */ +/* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */ #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to disable interrupt for event ENDRX */ #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for END event */ +/* Bit 1 : Write '1' to disable interrupt for event END */ #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ @@ -12856,6 +13220,15 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ +/* Register: SPIS_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + /* Register: SPIS_TXD_PTR */ /* Description: TXD data pointer */ @@ -12877,6 +13250,15 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ +/* Register: SPIS_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + /* Register: SPIS_CONFIG */ /* Description: Configuration register */ @@ -12919,28 +13301,32 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: TEMP_TASKS_START */ /* Description: Start temperature measurement */ -/* Bit 0 : */ +/* Bit 0 : Start temperature measurement */ #define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define TEMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: TEMP_TASKS_STOP */ /* Description: Stop temperature measurement */ -/* Bit 0 : */ +/* Bit 0 : Stop temperature measurement */ #define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TEMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: TEMP_EVENTS_DATARDY */ /* Description: Temperature measurement complete, data ready */ -/* Bit 0 : */ +/* Bit 0 : Temperature measurement complete, data ready */ #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */ #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of EVENTS_DATARDY field. */ +#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0UL) /*!< Event not generated */ +#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (1UL) /*!< Event generated */ /* Register: TEMP_INTENSET */ /* Description: Enable interrupt */ -/* Bit 0 : Write '1' to enable interrupt for DATARDY event */ +/* Bit 0 : Write '1' to enable interrupt for event DATARDY */ #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */ @@ -12950,7 +13336,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: TEMP_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 0 : Write '1' to disable interrupt for DATARDY event */ +/* Bit 0 : Write '1' to disable interrupt for event DATARDY */ #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */ @@ -12965,121 +13351,121 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */ /* Register: TEMP_A0 */ -/* Description: Slope of 1st piece wise linear function */ +/* Description: Slope of first piecewise linear function */ -/* Bits 11..0 : Slope of 1st piece wise linear function */ +/* Bits 11..0 : Slope of first piecewise linear function */ #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */ #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */ /* Register: TEMP_A1 */ -/* Description: Slope of 2nd piece wise linear function */ +/* Description: Slope of second piecewise linear function */ -/* Bits 11..0 : Slope of 2nd piece wise linear function */ +/* Bits 11..0 : Slope of second piecewise linear function */ #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */ #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */ /* Register: TEMP_A2 */ -/* Description: Slope of 3rd piece wise linear function */ +/* Description: Slope of third piecewise linear function */ -/* Bits 11..0 : Slope of 3rd piece wise linear function */ +/* Bits 11..0 : Slope of third piecewise linear function */ #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */ #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */ /* Register: TEMP_A3 */ -/* Description: Slope of 4th piece wise linear function */ +/* Description: Slope of fourth piecewise linear function */ -/* Bits 11..0 : Slope of 4th piece wise linear function */ +/* Bits 11..0 : Slope of fourth piecewise linear function */ #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */ #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */ /* Register: TEMP_A4 */ -/* Description: Slope of 5th piece wise linear function */ +/* Description: Slope of fifth piecewise linear function */ -/* Bits 11..0 : Slope of 5th piece wise linear function */ +/* Bits 11..0 : Slope of fifth piecewise linear function */ #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */ #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */ /* Register: TEMP_A5 */ -/* Description: Slope of 6th piece wise linear function */ +/* Description: Slope of sixth piecewise linear function */ -/* Bits 11..0 : Slope of 6th piece wise linear function */ +/* Bits 11..0 : Slope of sixth piecewise linear function */ #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */ #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */ /* Register: TEMP_B0 */ -/* Description: y-intercept of 1st piece wise linear function */ +/* Description: y-intercept of first piecewise linear function */ -/* Bits 13..0 : y-intercept of 1st piece wise linear function */ +/* Bits 13..0 : y-intercept of first piecewise linear function */ #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */ #define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */ /* Register: TEMP_B1 */ -/* Description: y-intercept of 2nd piece wise linear function */ +/* Description: y-intercept of second piecewise linear function */ -/* Bits 13..0 : y-intercept of 2nd piece wise linear function */ +/* Bits 13..0 : y-intercept of second piecewise linear function */ #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */ #define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */ /* Register: TEMP_B2 */ -/* Description: y-intercept of 3rd piece wise linear function */ +/* Description: y-intercept of third piecewise linear function */ -/* Bits 13..0 : y-intercept of 3rd piece wise linear function */ +/* Bits 13..0 : y-intercept of third piecewise linear function */ #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */ #define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */ /* Register: TEMP_B3 */ -/* Description: y-intercept of 4th piece wise linear function */ +/* Description: y-intercept of fourth piecewise linear function */ -/* Bits 13..0 : y-intercept of 4th piece wise linear function */ +/* Bits 13..0 : y-intercept of fourth piecewise linear function */ #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */ #define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */ /* Register: TEMP_B4 */ -/* Description: y-intercept of 5th piece wise linear function */ +/* Description: y-intercept of fifth piecewise linear function */ -/* Bits 13..0 : y-intercept of 5th piece wise linear function */ +/* Bits 13..0 : y-intercept of fifth piecewise linear function */ #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */ #define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */ /* Register: TEMP_B5 */ -/* Description: y-intercept of 6th piece wise linear function */ +/* Description: y-intercept of sixth piecewise linear function */ -/* Bits 13..0 : y-intercept of 6th piece wise linear function */ +/* Bits 13..0 : y-intercept of sixth piecewise linear function */ #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */ #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ /* Register: TEMP_T0 */ -/* Description: End point of 1st piece wise linear function */ +/* Description: End point of first piecewise linear function */ -/* Bits 7..0 : End point of 1st piece wise linear function */ +/* Bits 7..0 : End point of first piecewise linear function */ #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */ #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */ /* Register: TEMP_T1 */ -/* Description: End point of 2nd piece wise linear function */ +/* Description: End point of second piecewise linear function */ -/* Bits 7..0 : End point of 2nd piece wise linear function */ +/* Bits 7..0 : End point of second piecewise linear function */ #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */ /* Register: TEMP_T2 */ -/* Description: End point of 3rd piece wise linear function */ +/* Description: End point of third piecewise linear function */ -/* Bits 7..0 : End point of 3rd piece wise linear function */ +/* Bits 7..0 : End point of third piecewise linear function */ #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */ #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */ /* Register: TEMP_T3 */ -/* Description: End point of 4th piece wise linear function */ +/* Description: End point of fourth piecewise linear function */ -/* Bits 7..0 : End point of 4th piece wise linear function */ +/* Bits 7..0 : End point of fourth piecewise linear function */ #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */ #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */ /* Register: TEMP_T4 */ -/* Description: End point of 5th piece wise linear function */ +/* Description: End point of fifth piecewise linear function */ -/* Bits 7..0 : End point of 5th piece wise linear function */ +/* Bits 7..0 : End point of fifth piecewise linear function */ #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */ #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */ @@ -13090,122 +13476,130 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: TIMER_TASKS_START */ /* Description: Start Timer */ -/* Bit 0 : */ +/* Bit 0 : Start Timer */ #define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: TIMER_TASKS_STOP */ /* Description: Stop Timer */ -/* Bit 0 : */ +/* Bit 0 : Stop Timer */ #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: TIMER_TASKS_COUNT */ /* Description: Increment Timer (Counter mode only) */ -/* Bit 0 : */ +/* Bit 0 : Increment Timer (Counter mode only) */ #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */ #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */ +#define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */ /* Register: TIMER_TASKS_CLEAR */ /* Description: Clear time */ -/* Bit 0 : */ +/* Bit 0 : Clear time */ #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ +#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ /* Register: TIMER_TASKS_SHUTDOWN */ /* Description: Deprecated register - Shut down timer */ -/* Bit 0 : */ +/* Bit 0 : Deprecated field - Shut down timer */ #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */ #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */ +#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */ /* Register: TIMER_TASKS_CAPTURE */ -/* Description: Description collection[n]: Capture Timer value to CC[n] register */ +/* Description: Description collection: Capture Timer value to CC[n] register */ -/* Bit 0 : */ +/* Bit 0 : Capture Timer value to CC[n] register */ #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */ #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */ +#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */ /* Register: TIMER_EVENTS_COMPARE */ -/* Description: Description collection[n]: Compare event on CC[n] match */ +/* Description: Description collection: Compare event on CC[n] match */ -/* Bit 0 : */ +/* Bit 0 : Compare event on CC[n] match */ #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ /* Register: TIMER_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 13 : Shortcut between COMPARE[5] event and STOP task */ +/* Bit 13 : Shortcut between event COMPARE[5] and task STOP */ #define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */ #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */ #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 12 : Shortcut between COMPARE[4] event and STOP task */ +/* Bit 12 : Shortcut between event COMPARE[4] and task STOP */ #define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */ #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */ #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 11 : Shortcut between COMPARE[3] event and STOP task */ +/* Bit 11 : Shortcut between event COMPARE[3] and task STOP */ #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 10 : Shortcut between COMPARE[2] event and STOP task */ +/* Bit 10 : Shortcut between event COMPARE[2] and task STOP */ #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 9 : Shortcut between COMPARE[1] event and STOP task */ +/* Bit 9 : Shortcut between event COMPARE[1] and task STOP */ #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 8 : Shortcut between COMPARE[0] event and STOP task */ +/* Bit 8 : Shortcut between event COMPARE[0] and task STOP */ #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */ +/* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */ #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */ #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */ #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */ +/* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */ #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */ #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */ #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */ +/* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */ #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */ +/* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */ #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */ +/* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */ #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */ +/* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */ #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */ @@ -13214,42 +13608,42 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: TIMER_INTENSET */ /* Description: Enable interrupt */ -/* Bit 21 : Write '1' to enable interrupt for COMPARE[5] event */ +/* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */ #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for COMPARE[4] event */ +/* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */ #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for COMPARE[3] event */ +/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */ +/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for COMPARE[1] event */ +/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable interrupt for COMPARE[0] event */ +/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ @@ -13259,42 +13653,42 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: TIMER_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 21 : Write '1' to disable interrupt for COMPARE[5] event */ +/* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */ #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for COMPARE[4] event */ +/* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */ #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for COMPARE[3] event */ +/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */ +/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for COMPARE[1] event */ +/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable interrupt for COMPARE[0] event */ +/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ @@ -13330,7 +13724,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ /* Register: TIMER_CC */ -/* Description: Description collection[n]: Capture/Compare register n */ +/* Description: Description collection: Capture/Compare register n */ /* Bits 31..0 : Capture/Compare value */ #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */ @@ -13343,90 +13737,107 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: TWI_TASKS_STARTRX */ /* Description: Start TWI receive sequence */ -/* Bit 0 : */ +/* Bit 0 : Start TWI receive sequence */ #define TWI_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ #define TWI_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWI_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define TWI_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ /* Register: TWI_TASKS_STARTTX */ /* Description: Start TWI transmit sequence */ -/* Bit 0 : */ +/* Bit 0 : Start TWI transmit sequence */ #define TWI_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ #define TWI_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWI_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define TWI_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ /* Register: TWI_TASKS_STOP */ /* Description: Stop TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Stop TWI transaction */ #define TWI_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define TWI_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWI_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TWI_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: TWI_TASKS_SUSPEND */ /* Description: Suspend TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Suspend TWI transaction */ #define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ #define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ /* Register: TWI_TASKS_RESUME */ /* Description: Resume TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Resume TWI transaction */ #define TWI_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ #define TWI_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWI_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define TWI_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ /* Register: TWI_EVENTS_STOPPED */ /* Description: TWI stopped */ -/* Bit 0 : */ +/* Bit 0 : TWI stopped */ #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: TWI_EVENTS_RXDREADY */ /* Description: TWI RXD byte received */ -/* Bit 0 : */ +/* Bit 0 : TWI RXD byte received */ #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos (0UL) /*!< Position of EVENTS_RXDREADY field. */ #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Msk (0x1UL << TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos) /*!< Bit mask of EVENTS_RXDREADY field. */ +#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Generated (1UL) /*!< Event generated */ /* Register: TWI_EVENTS_TXDSENT */ /* Description: TWI TXD byte sent */ -/* Bit 0 : */ +/* Bit 0 : TWI TXD byte sent */ #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos (0UL) /*!< Position of EVENTS_TXDSENT field. */ #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Msk (0x1UL << TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos) /*!< Bit mask of EVENTS_TXDSENT field. */ +#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Generated (1UL) /*!< Event generated */ /* Register: TWI_EVENTS_ERROR */ /* Description: TWI error */ -/* Bit 0 : */ +/* Bit 0 : TWI error */ #define TWI_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define TWI_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWI_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define TWI_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: TWI_EVENTS_BB */ /* Description: TWI byte boundary, generated before each byte that is sent or received */ -/* Bit 0 : */ +/* Bit 0 : TWI byte boundary, generated before each byte that is sent or received */ #define TWI_EVENTS_BB_EVENTS_BB_Pos (0UL) /*!< Position of EVENTS_BB field. */ #define TWI_EVENTS_BB_EVENTS_BB_Msk (0x1UL << TWI_EVENTS_BB_EVENTS_BB_Pos) /*!< Bit mask of EVENTS_BB field. */ +#define TWI_EVENTS_BB_EVENTS_BB_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_BB_EVENTS_BB_Generated (1UL) /*!< Event generated */ /* Register: TWI_EVENTS_SUSPENDED */ /* Description: TWI entered the suspended state */ -/* Bit 0 : */ +/* Bit 0 : TWI entered the suspended state */ #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ +#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */ /* Register: TWI_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 1 : Shortcut between BB event and STOP task */ +/* Bit 1 : Shortcut between event BB and task STOP */ #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */ #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */ #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between BB event and SUSPEND task */ +/* Bit 0 : Shortcut between event BB and task SUSPEND */ #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */ #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */ #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ @@ -13435,42 +13846,42 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: TWI_INTENSET */ /* Description: Enable interrupt */ -/* Bit 18 : Write '1' to enable interrupt for SUSPENDED event */ +/* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */ #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to enable interrupt for BB event */ +/* Bit 14 : Write '1' to enable interrupt for event BB */ #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ #define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENSET_BB_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for ERROR event */ +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for TXDSENT event */ +/* Bit 7 : Write '1' to enable interrupt for event TXDSENT */ #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for RXDREADY event */ +/* Bit 2 : Write '1' to enable interrupt for event RXDREADY */ #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -13480,42 +13891,42 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: TWI_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 18 : Write '1' to disable interrupt for SUSPENDED event */ +/* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */ #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to disable interrupt for BB event */ +/* Bit 14 : Write '1' to disable interrupt for event BB */ #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for ERROR event */ +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for TXDSENT event */ +/* Bit 7 : Write '1' to disable interrupt for event TXDSENT */ #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for RXDREADY event */ +/* Bit 2 : Write '1' to disable interrupt for event RXDREADY */ #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -13624,121 +14035,140 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: TWIM_TASKS_STARTRX */ /* Description: Start TWI receive sequence */ -/* Bit 0 : */ +/* Bit 0 : Start TWI receive sequence */ #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ /* Register: TWIM_TASKS_STARTTX */ /* Description: Start TWI transmit sequence */ -/* Bit 0 : */ +/* Bit 0 : Start TWI transmit sequence */ #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ /* Register: TWIM_TASKS_STOP */ /* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */ -/* Bit 0 : */ +/* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */ #define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: TWIM_TASKS_SUSPEND */ /* Description: Suspend TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Suspend TWI transaction */ #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ /* Register: TWIM_TASKS_RESUME */ /* Description: Resume TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Resume TWI transaction */ #define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ #define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ /* Register: TWIM_EVENTS_STOPPED */ /* Description: TWI stopped */ -/* Bit 0 : */ +/* Bit 0 : TWI stopped */ #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_ERROR */ /* Description: TWI error */ -/* Bit 0 : */ +/* Bit 0 : TWI error */ #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_SUSPENDED */ -/* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ +/* Description: SUSPEND task has been issued, TWI traffic is now suspended. */ -/* Bit 0 : */ +/* Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_RXSTARTED */ /* Description: Receive sequence started */ -/* Bit 0 : */ +/* Bit 0 : Receive sequence started */ #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_TXSTARTED */ /* Description: Transmit sequence started */ -/* Bit 0 : */ +/* Bit 0 : Transmit sequence started */ #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_LASTRX */ /* Description: Byte boundary, starting to receive the last byte */ -/* Bit 0 : */ +/* Bit 0 : Byte boundary, starting to receive the last byte */ #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */ #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_LASTTX */ /* Description: Byte boundary, starting to transmit the last byte */ -/* Bit 0 : */ +/* Bit 0 : Byte boundary, starting to transmit the last byte */ #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */ #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL) /*!< Event generated */ /* Register: TWIM_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 12 : Shortcut between LASTRX event and STOP task */ +/* Bit 12 : Shortcut between event LASTRX and task STOP */ #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */ #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */ #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 11 : Shortcut between LASTRX event and SUSPEND task */ +/* Bit 11 : Shortcut between event LASTRX and task SUSPEND */ #define TWIM_SHORTS_LASTRX_SUSPEND_Pos (11UL) /*!< Position of LASTRX_SUSPEND field. */ #define TWIM_SHORTS_LASTRX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTRX_SUSPEND_Pos) /*!< Bit mask of LASTRX_SUSPEND field. */ #define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ #define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 10 : Shortcut between LASTRX event and STARTTX task */ +/* Bit 10 : Shortcut between event LASTRX and task STARTTX */ #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */ #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */ #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */ #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 9 : Shortcut between LASTTX event and STOP task */ +/* Bit 9 : Shortcut between event LASTTX and task STOP */ #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */ #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */ #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 8 : Shortcut between LASTTX event and SUSPEND task */ +/* Bit 8 : Shortcut between event LASTTX and task SUSPEND */ #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */ #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */ #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 7 : Shortcut between LASTTX event and STARTRX task */ +/* Bit 7 : Shortcut between event LASTTX and task STARTRX */ #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */ #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */ #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ @@ -13747,43 +14177,43 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: TWIM_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 24 : Enable or disable interrupt for LASTTX event */ +/* Bit 24 : Enable or disable interrupt for event LASTTX */ #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */ -/* Bit 23 : Enable or disable interrupt for LASTRX event */ +/* Bit 23 : Enable or disable interrupt for event LASTRX */ #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */ -/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +/* Bit 20 : Enable or disable interrupt for event TXSTARTED */ #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +/* Bit 19 : Enable or disable interrupt for event RXSTARTED */ #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 18 : Enable or disable interrupt for SUSPENDED event */ +/* Bit 18 : Enable or disable interrupt for event SUSPENDED */ #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for ERROR event */ +/* Bit 9 : Enable or disable interrupt for event ERROR */ #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for STOPPED event */ +/* Bit 1 : Enable or disable interrupt for event STOPPED */ #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ @@ -13792,49 +14222,49 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: TWIM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 24 : Write '1' to enable interrupt for LASTTX event */ +/* Bit 24 : Write '1' to enable interrupt for event LASTTX */ #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */ -/* Bit 23 : Write '1' to enable interrupt for LASTRX event */ +/* Bit 23 : Write '1' to enable interrupt for event LASTRX */ #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for SUSPENDED event */ +/* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */ #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for ERROR event */ +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -13844,49 +14274,49 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: TWIM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 24 : Write '1' to disable interrupt for LASTTX event */ +/* Bit 24 : Write '1' to disable interrupt for event LASTTX */ #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */ -/* Bit 23 : Write '1' to disable interrupt for LASTRX event */ +/* Bit 23 : Write '1' to disable interrupt for event LASTRX */ #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for SUSPENDED event */ +/* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */ #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for ERROR event */ +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -14041,90 +14471,107 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_TASKS_STOP */ /* Description: Stop TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Stop TWI transaction */ #define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: TWIS_TASKS_SUSPEND */ /* Description: Suspend TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Suspend TWI transaction */ #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ /* Register: TWIS_TASKS_RESUME */ /* Description: Resume TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Resume TWI transaction */ #define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ #define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ /* Register: TWIS_TASKS_PREPARERX */ /* Description: Prepare the TWI slave to respond to a write command */ -/* Bit 0 : */ +/* Bit 0 : Prepare the TWI slave to respond to a write command */ #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */ #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */ +#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL) /*!< Trigger task */ /* Register: TWIS_TASKS_PREPARETX */ /* Description: Prepare the TWI slave to respond to a read command */ -/* Bit 0 : */ +/* Bit 0 : Prepare the TWI slave to respond to a read command */ #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */ #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */ +#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL) /*!< Trigger task */ /* Register: TWIS_EVENTS_STOPPED */ /* Description: TWI stopped */ -/* Bit 0 : */ +/* Bit 0 : TWI stopped */ #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: TWIS_EVENTS_ERROR */ /* Description: TWI error */ -/* Bit 0 : */ +/* Bit 0 : TWI error */ #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: TWIS_EVENTS_RXSTARTED */ /* Description: Receive sequence started */ -/* Bit 0 : */ +/* Bit 0 : Receive sequence started */ #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ /* Register: TWIS_EVENTS_TXSTARTED */ /* Description: Transmit sequence started */ -/* Bit 0 : */ +/* Bit 0 : Transmit sequence started */ #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ /* Register: TWIS_EVENTS_WRITE */ /* Description: Write command received */ -/* Bit 0 : */ +/* Bit 0 : Write command received */ #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */ #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL) /*!< Event generated */ /* Register: TWIS_EVENTS_READ */ /* Description: Read command received */ -/* Bit 0 : */ +/* Bit 0 : Read command received */ #define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */ #define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */ +#define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL) /*!< Event generated */ /* Register: TWIS_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 14 : Shortcut between READ event and SUSPEND task */ +/* Bit 14 : Shortcut between event READ and task SUSPEND */ #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */ #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */ #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 13 : Shortcut between WRITE event and SUSPEND task */ +/* Bit 13 : Shortcut between event WRITE and task SUSPEND */ #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */ #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */ #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ @@ -14133,37 +14580,37 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 26 : Enable or disable interrupt for READ event */ +/* Bit 26 : Enable or disable interrupt for event READ */ #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */ #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */ #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */ #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */ -/* Bit 25 : Enable or disable interrupt for WRITE event */ +/* Bit 25 : Enable or disable interrupt for event WRITE */ #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */ #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */ #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */ #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */ -/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +/* Bit 20 : Enable or disable interrupt for event TXSTARTED */ #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +/* Bit 19 : Enable or disable interrupt for event RXSTARTED */ #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for ERROR event */ +/* Bit 9 : Enable or disable interrupt for event ERROR */ #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */ #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for STOPPED event */ +/* Bit 1 : Enable or disable interrupt for event STOPPED */ #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ @@ -14172,42 +14619,42 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_INTENSET */ /* Description: Enable interrupt */ -/* Bit 26 : Write '1' to enable interrupt for READ event */ +/* Bit 26 : Write '1' to enable interrupt for event READ */ #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */ #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */ #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */ -/* Bit 25 : Write '1' to enable interrupt for WRITE event */ +/* Bit 25 : Write '1' to enable interrupt for event WRITE */ #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */ #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */ #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for ERROR event */ +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -14217,42 +14664,42 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 26 : Write '1' to disable interrupt for READ event */ +/* Bit 26 : Write '1' to disable interrupt for event READ */ #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */ #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */ #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */ -/* Bit 25 : Write '1' to disable interrupt for WRITE event */ +/* Bit 25 : Write '1' to disable interrupt for event WRITE */ #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */ #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */ #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for ERROR event */ +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -14283,7 +14730,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_MATCH */ /* Description: Status register indicating which address had a match */ -/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */ +/* Bit 0 : Indication of which address in {ADDRESS} that matched the incoming address */ #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ @@ -14351,6 +14798,15 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ +/* Register: TWIS_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define TWIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + /* Register: TWIS_TXD_PTR */ /* Description: TXD Data pointer */ @@ -14372,8 +14828,17 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ +/* Register: TWIS_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define TWIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + /* Register: TWIS_ADDRESS */ -/* Description: Description collection[n]: TWI slave address n */ +/* Description: Description collection: TWI slave address n */ /* Bits 6..0 : TWI slave address */ #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ @@ -14408,90 +14873,107 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: UART_TASKS_STARTRX */ /* Description: Start UART receiver */ -/* Bit 0 : */ +/* Bit 0 : Start UART receiver */ #define UART_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ #define UART_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UART_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define UART_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ /* Register: UART_TASKS_STOPRX */ /* Description: Stop UART receiver */ -/* Bit 0 : */ +/* Bit 0 : Stop UART receiver */ #define UART_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */ #define UART_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UART_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */ +#define UART_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */ /* Register: UART_TASKS_STARTTX */ /* Description: Start UART transmitter */ -/* Bit 0 : */ +/* Bit 0 : Start UART transmitter */ #define UART_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ #define UART_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UART_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define UART_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ /* Register: UART_TASKS_STOPTX */ /* Description: Stop UART transmitter */ -/* Bit 0 : */ +/* Bit 0 : Stop UART transmitter */ #define UART_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */ #define UART_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UART_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */ +#define UART_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */ /* Register: UART_TASKS_SUSPEND */ /* Description: Suspend UART */ -/* Bit 0 : */ +/* Bit 0 : Suspend UART */ #define UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ #define UART_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ /* Register: UART_EVENTS_CTS */ /* Description: CTS is activated (set low). Clear To Send. */ -/* Bit 0 : */ +/* Bit 0 : CTS is activated (set low). Clear To Send. */ #define UART_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ #define UART_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UART_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ +#define UART_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */ /* Register: UART_EVENTS_NCTS */ /* Description: CTS is deactivated (set high). Not Clear To Send. */ -/* Bit 0 : */ +/* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */ #define UART_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ #define UART_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UART_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ +#define UART_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */ /* Register: UART_EVENTS_RXDRDY */ /* Description: Data received in RXD */ -/* Bit 0 : */ +/* Bit 0 : Data received in RXD */ #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */ +#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */ /* Register: UART_EVENTS_TXDRDY */ /* Description: Data sent from TXD */ -/* Bit 0 : */ +/* Bit 0 : Data sent from TXD */ #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */ +#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */ /* Register: UART_EVENTS_ERROR */ /* Description: Error detected */ -/* Bit 0 : */ +/* Bit 0 : Error detected */ #define UART_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define UART_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UART_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define UART_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: UART_EVENTS_RXTO */ /* Description: Receiver timeout */ -/* Bit 0 : */ +/* Bit 0 : Receiver timeout */ #define UART_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ #define UART_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UART_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ +#define UART_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */ /* Register: UART_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 4 : Shortcut between NCTS event and STOPRX task */ +/* Bit 4 : Shortcut between event NCTS and task STOPRX */ #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */ #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between CTS event and STARTRX task */ +/* Bit 3 : Shortcut between event CTS and task STARTRX */ #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */ @@ -14500,42 +14982,42 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: UART_INTENSET */ /* Description: Enable interrupt */ -/* Bit 17 : Write '1' to enable interrupt for RXTO event */ +/* Bit 17 : Write '1' to enable interrupt for event RXTO */ #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for ERROR event */ +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for TXDRDY event */ +/* Bit 7 : Write '1' to enable interrupt for event TXDRDY */ #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for RXDRDY event */ +/* Bit 2 : Write '1' to enable interrupt for event RXDRDY */ #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for NCTS event */ +/* Bit 1 : Write '1' to enable interrupt for event NCTS */ #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for CTS event */ +/* Bit 0 : Write '1' to enable interrupt for event CTS */ #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ #define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ @@ -14545,42 +15027,42 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: UART_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 17 : Write '1' to disable interrupt for RXTO event */ +/* Bit 17 : Write '1' to disable interrupt for event RXTO */ #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for ERROR event */ +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for TXDRDY event */ +/* Bit 7 : Write '1' to disable interrupt for event TXDRDY */ #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for RXDRDY event */ +/* Bit 2 : Write '1' to disable interrupt for event RXDRDY */ #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for NCTS event */ +/* Bit 1 : Write '1' to disable interrupt for event NCTS */ #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for CTS event */ +/* Bit 0 : Write '1' to disable interrupt for event CTS */ #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ @@ -14733,6 +15215,12 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: UART_CONFIG */ /* Description: Configuration of parity and hardware flow control */ +/* Bit 4 : Stop bits */ +#define UART_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */ +#define UART_CONFIG_STOP_Msk (0x1UL << UART_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */ +#define UART_CONFIG_STOP_One (0UL) /*!< One stop bit */ +#define UART_CONFIG_STOP_Two (1UL) /*!< Two stop bits */ + /* Bits 3..1 : Parity */ #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ @@ -14752,125 +15240,152 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: UARTE_TASKS_STARTRX */ /* Description: Start UART receiver */ -/* Bit 0 : */ +/* Bit 0 : Start UART receiver */ #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ /* Register: UARTE_TASKS_STOPRX */ /* Description: Stop UART receiver */ -/* Bit 0 : */ +/* Bit 0 : Stop UART receiver */ #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */ #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */ +#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */ /* Register: UARTE_TASKS_STARTTX */ /* Description: Start UART transmitter */ -/* Bit 0 : */ +/* Bit 0 : Start UART transmitter */ #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ /* Register: UARTE_TASKS_STOPTX */ /* Description: Stop UART transmitter */ -/* Bit 0 : */ +/* Bit 0 : Stop UART transmitter */ #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */ #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */ +#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */ /* Register: UARTE_TASKS_FLUSHRX */ /* Description: Flush RX FIFO into RX buffer */ -/* Bit 0 : */ +/* Bit 0 : Flush RX FIFO into RX buffer */ #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */ #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */ +#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL) /*!< Trigger task */ /* Register: UARTE_EVENTS_CTS */ /* Description: CTS is activated (set low). Clear To Send. */ -/* Bit 0 : */ +/* Bit 0 : CTS is activated (set low). Clear To Send. */ #define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ #define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_NCTS */ /* Description: CTS is deactivated (set high). Not Clear To Send. */ -/* Bit 0 : */ +/* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */ #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_RXDRDY */ /* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */ -/* Bit 0 : */ +/* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */ #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_ENDRX */ /* Description: Receive buffer is filled up */ -/* Bit 0 : */ +/* Bit 0 : Receive buffer is filled up */ #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_TXDRDY */ /* Description: Data sent from TXD */ -/* Bit 0 : */ +/* Bit 0 : Data sent from TXD */ #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_ENDTX */ /* Description: Last TX byte transmitted */ -/* Bit 0 : */ +/* Bit 0 : Last TX byte transmitted */ #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_ERROR */ /* Description: Error detected */ -/* Bit 0 : */ +/* Bit 0 : Error detected */ #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_RXTO */ /* Description: Receiver timeout */ -/* Bit 0 : */ +/* Bit 0 : Receiver timeout */ #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_RXSTARTED */ /* Description: UART receiver has started */ -/* Bit 0 : */ +/* Bit 0 : UART receiver has started */ #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_TXSTARTED */ /* Description: UART transmitter has started */ -/* Bit 0 : */ +/* Bit 0 : UART transmitter has started */ #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_TXSTOPPED */ /* Description: Transmitter stopped */ -/* Bit 0 : */ +/* Bit 0 : Transmitter stopped */ #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */ #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL) /*!< Event generated */ /* Register: UARTE_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 6 : Shortcut between ENDRX event and STOPRX task */ +/* Bit 6 : Shortcut between event ENDRX and task STOPRX */ #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */ #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */ #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */ #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 5 : Shortcut between ENDRX event and STARTRX task */ +/* Bit 5 : Shortcut between event ENDRX and task STARTRX */ #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */ #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */ #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ @@ -14879,67 +15394,67 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: UARTE_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 22 : Enable or disable interrupt for TXSTOPPED event */ +/* Bit 22 : Enable or disable interrupt for event TXSTOPPED */ #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */ -/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +/* Bit 20 : Enable or disable interrupt for event TXSTARTED */ #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +/* Bit 19 : Enable or disable interrupt for event RXSTARTED */ #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 17 : Enable or disable interrupt for RXTO event */ +/* Bit 17 : Enable or disable interrupt for event RXTO */ #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */ #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for ERROR event */ +/* Bit 9 : Enable or disable interrupt for event ERROR */ #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */ -/* Bit 8 : Enable or disable interrupt for ENDTX event */ +/* Bit 8 : Enable or disable interrupt for event ENDTX */ #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for TXDRDY event */ +/* Bit 7 : Enable or disable interrupt for event TXDRDY */ #define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ #define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for ENDRX event */ +/* Bit 4 : Enable or disable interrupt for event ENDRX */ #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for RXDRDY event */ +/* Bit 2 : Enable or disable interrupt for event RXDRDY */ #define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ #define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for NCTS event */ +/* Bit 1 : Enable or disable interrupt for event NCTS */ #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for CTS event */ +/* Bit 0 : Enable or disable interrupt for event CTS */ #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */ #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */ @@ -14948,77 +15463,77 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: UARTE_INTENSET */ /* Description: Enable interrupt */ -/* Bit 22 : Write '1' to enable interrupt for TXSTOPPED event */ +/* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */ #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for RXTO event */ +/* Bit 17 : Write '1' to enable interrupt for event RXTO */ #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for ERROR event */ +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for ENDTX event */ +/* Bit 8 : Write '1' to enable interrupt for event ENDTX */ #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for TXDRDY event */ +/* Bit 7 : Write '1' to enable interrupt for event TXDRDY */ #define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to enable interrupt for event ENDRX */ #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for RXDRDY event */ +/* Bit 2 : Write '1' to enable interrupt for event RXDRDY */ #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for NCTS event */ +/* Bit 1 : Write '1' to enable interrupt for event NCTS */ #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for CTS event */ +/* Bit 0 : Write '1' to enable interrupt for event CTS */ #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ @@ -15028,77 +15543,77 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: UARTE_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 22 : Write '1' to disable interrupt for TXSTOPPED event */ +/* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */ #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for RXTO event */ +/* Bit 17 : Write '1' to disable interrupt for event RXTO */ #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for ERROR event */ +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for ENDTX event */ +/* Bit 8 : Write '1' to disable interrupt for event ENDTX */ #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for TXDRDY event */ +/* Bit 7 : Write '1' to disable interrupt for event TXDRDY */ #define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to disable interrupt for event ENDRX */ #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for RXDRDY event */ +/* Bit 2 : Write '1' to disable interrupt for event RXDRDY */ #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for NCTS event */ +/* Bit 1 : Write '1' to disable interrupt for event NCTS */ #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for CTS event */ +/* Bit 0 : Write '1' to disable interrupt for event CTS */ #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ @@ -15106,7 +15621,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */ /* Register: UARTE_ERRORSRC */ -/* Description: Error source Note : this register is read / write one to clear. */ +/* Description: Error source This register is read/write one to clear. */ /* Bit 3 : Break condition */ #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ @@ -15232,7 +15747,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ -#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */ /* Register: UARTE_RXD_PTR */ /* Description: Data pointer */ @@ -15302,28 +15817,28 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Description: User information configuration registers */ /* Register: UICR_NRFFW */ -/* Description: Description collection[n]: Reserved for Nordic firmware design */ +/* Description: Description collection: Reserved for Nordic firmware design */ /* Bits 31..0 : Reserved for Nordic firmware design */ #define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */ #define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */ /* Register: UICR_NRFHW */ -/* Description: Description collection[n]: Reserved for Nordic hardware design */ +/* Description: Description collection: Reserved for Nordic hardware design */ /* Bits 31..0 : Reserved for Nordic hardware design */ #define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */ #define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */ /* Register: UICR_CUSTOMER */ -/* Description: Description collection[n]: Reserved for customer */ +/* Description: Description collection: Reserved for customer */ /* Bits 31..0 : Reserved for customer */ #define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */ #define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */ /* Register: UICR_PSELRESET */ -/* Description: Description collection[n]: Mapping of the nRESET function */ +/* Description: Description collection: Mapping of the nRESET function (see POWER chapter for details) */ /* Bit 31 : Connection */ #define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ @@ -15335,7 +15850,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define UICR_PSELRESET_PORT_Pos (5UL) /*!< Position of PORT field. */ #define UICR_PSELRESET_PORT_Msk (0x1UL << UICR_PSELRESET_PORT_Pos) /*!< Bit mask of PORT field. */ -/* Bits 4..0 : Pin number of PORT onto which nRESET is exposed */ +/* Bits 4..0 : GPIO pin number onto which nRESET is exposed */ #define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */ #define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ @@ -15346,7 +15861,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ -#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */ +#define UICR_APPROTECT_PALL_HwDisabled (0x5AUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware and software */ +#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware */ /* Register: UICR_NFCPINS */ /* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */ @@ -15354,8 +15870,8 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Setting of pins dedicated to NFC functionality */ #define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */ #define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */ -#define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */ -#define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */ +#define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins. */ +#define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation. */ /* Register: UICR_DEBUGCTRL */ /* Description: Processor debug control */ @@ -15373,9 +15889,9 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define UICR_DEBUGCTRL_CPUNIDEN_Enabled (0xFFUL) /*!< Enable CPU ITM and ETM functionality (default behavior) */ /* Register: UICR_REGOUT0 */ -/* Description: GPIO reference voltage / external output supply voltage in high voltage mode */ +/* Description: Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - V_VDDH-VDD. */ -/* Bits 2..0 : Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF. */ +/* Bits 2..0 : Output voltage from REG0 regulator stage. */ #define UICR_REGOUT0_VOUT_Pos (0UL) /*!< Position of VOUT field. */ #define UICR_REGOUT0_VOUT_Msk (0x7UL << UICR_REGOUT0_VOUT_Pos) /*!< Bit mask of VOUT field. */ #define UICR_REGOUT0_VOUT_1V8 (0UL) /*!< 1.8 V */ @@ -15391,173 +15907,204 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Description: Universal serial bus device */ /* Register: USBD_TASKS_STARTEPIN */ -/* Description: Description collection[n]: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */ +/* Description: Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */ -/* Bit 0 : */ +/* Bit 0 : Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */ #define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos (0UL) /*!< Position of TASKS_STARTEPIN field. */ #define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Msk (0x1UL << USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos) /*!< Bit mask of TASKS_STARTEPIN field. */ +#define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Trigger (1UL) /*!< Trigger task */ /* Register: USBD_TASKS_STARTISOIN */ /* Description: Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */ -/* Bit 0 : */ +/* Bit 0 : Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */ #define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos (0UL) /*!< Position of TASKS_STARTISOIN field. */ #define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Msk (0x1UL << USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos) /*!< Bit mask of TASKS_STARTISOIN field. */ +#define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Trigger (1UL) /*!< Trigger task */ /* Register: USBD_TASKS_STARTEPOUT */ -/* Description: Description collection[n]: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */ +/* Description: Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */ -/* Bit 0 : */ +/* Bit 0 : Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */ #define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos (0UL) /*!< Position of TASKS_STARTEPOUT field. */ #define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Msk (0x1UL << USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos) /*!< Bit mask of TASKS_STARTEPOUT field. */ +#define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Trigger (1UL) /*!< Trigger task */ /* Register: USBD_TASKS_STARTISOOUT */ /* Description: Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */ -/* Bit 0 : */ +/* Bit 0 : Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */ #define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos (0UL) /*!< Position of TASKS_STARTISOOUT field. */ #define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Msk (0x1UL << USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos) /*!< Bit mask of TASKS_STARTISOOUT field. */ +#define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Trigger (1UL) /*!< Trigger task */ /* Register: USBD_TASKS_EP0RCVOUT */ /* Description: Allows OUT data stage on control endpoint 0 */ -/* Bit 0 : */ +/* Bit 0 : Allows OUT data stage on control endpoint 0 */ #define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos (0UL) /*!< Position of TASKS_EP0RCVOUT field. */ #define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Msk (0x1UL << USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos) /*!< Bit mask of TASKS_EP0RCVOUT field. */ +#define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Trigger (1UL) /*!< Trigger task */ /* Register: USBD_TASKS_EP0STATUS */ /* Description: Allows status stage on control endpoint 0 */ -/* Bit 0 : */ +/* Bit 0 : Allows status stage on control endpoint 0 */ #define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos (0UL) /*!< Position of TASKS_EP0STATUS field. */ #define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Msk (0x1UL << USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos) /*!< Bit mask of TASKS_EP0STATUS field. */ +#define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Trigger (1UL) /*!< Trigger task */ /* Register: USBD_TASKS_EP0STALL */ /* Description: Stalls data and status stage on control endpoint 0 */ -/* Bit 0 : */ +/* Bit 0 : Stalls data and status stage on control endpoint 0 */ #define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos (0UL) /*!< Position of TASKS_EP0STALL field. */ #define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Msk (0x1UL << USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos) /*!< Bit mask of TASKS_EP0STALL field. */ +#define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Trigger (1UL) /*!< Trigger task */ /* Register: USBD_TASKS_DPDMDRIVE */ /* Description: Forces D+ and D- lines into the state defined in the DPDMVALUE register */ -/* Bit 0 : */ +/* Bit 0 : Forces D+ and D- lines into the state defined in the DPDMVALUE register */ #define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos (0UL) /*!< Position of TASKS_DPDMDRIVE field. */ #define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Msk (0x1UL << USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos) /*!< Bit mask of TASKS_DPDMDRIVE field. */ +#define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Trigger (1UL) /*!< Trigger task */ /* Register: USBD_TASKS_DPDMNODRIVE */ /* Description: Stops forcing D+ and D- lines into any state (USB engine takes control) */ -/* Bit 0 : */ +/* Bit 0 : Stops forcing D+ and D- lines into any state (USB engine takes control) */ #define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos (0UL) /*!< Position of TASKS_DPDMNODRIVE field. */ #define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Msk (0x1UL << USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos) /*!< Bit mask of TASKS_DPDMNODRIVE field. */ +#define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Trigger (1UL) /*!< Trigger task */ /* Register: USBD_EVENTS_USBRESET */ /* Description: Signals that a USB reset condition has been detected on USB lines */ -/* Bit 0 : */ +/* Bit 0 : Signals that a USB reset condition has been detected on USB lines */ #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos (0UL) /*!< Position of EVENTS_USBRESET field. */ #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Msk (0x1UL << USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos) /*!< Bit mask of EVENTS_USBRESET field. */ +#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_STARTED */ /* Description: Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */ -/* Bit 0 : */ +/* Bit 0 : Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */ #define USBD_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ #define USBD_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << USBD_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define USBD_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_ENDEPIN */ -/* Description: Description collection[n]: The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ +/* Description: Description collection: The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. */ -/* Bit 0 : */ +/* Bit 0 : The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. */ #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos (0UL) /*!< Position of EVENTS_ENDEPIN field. */ #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Msk (0x1UL << USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos) /*!< Bit mask of EVENTS_ENDEPIN field. */ +#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_EP0DATADONE */ /* Description: An acknowledged data transfer has taken place on the control endpoint */ -/* Bit 0 : */ +/* Bit 0 : An acknowledged data transfer has taken place on the control endpoint */ #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos (0UL) /*!< Position of EVENTS_EP0DATADONE field. */ #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Msk (0x1UL << USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos) /*!< Bit mask of EVENTS_EP0DATADONE field. */ +#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_ENDISOIN */ -/* Description: The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. */ +/* Description: The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. */ -/* Bit 0 : */ +/* Bit 0 : The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. */ #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos (0UL) /*!< Position of EVENTS_ENDISOIN field. */ #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Msk (0x1UL << USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos) /*!< Bit mask of EVENTS_ENDISOIN field. */ +#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_ENDEPOUT */ -/* Description: Description collection[n]: The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ +/* Description: Description collection: The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. */ -/* Bit 0 : */ +/* Bit 0 : The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. */ #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos (0UL) /*!< Position of EVENTS_ENDEPOUT field. */ #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Msk (0x1UL << USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos) /*!< Bit mask of EVENTS_ENDEPOUT field. */ +#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_ENDISOOUT */ -/* Description: The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. */ +/* Description: The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. */ -/* Bit 0 : */ +/* Bit 0 : The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. */ #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos (0UL) /*!< Position of EVENTS_ENDISOOUT field. */ #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Msk (0x1UL << USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos) /*!< Bit mask of EVENTS_ENDISOOUT field. */ +#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_SOF */ /* Description: Signals that a SOF (start of frame) condition has been detected on USB lines */ -/* Bit 0 : */ +/* Bit 0 : Signals that a SOF (start of frame) condition has been detected on USB lines */ #define USBD_EVENTS_SOF_EVENTS_SOF_Pos (0UL) /*!< Position of EVENTS_SOF field. */ #define USBD_EVENTS_SOF_EVENTS_SOF_Msk (0x1UL << USBD_EVENTS_SOF_EVENTS_SOF_Pos) /*!< Bit mask of EVENTS_SOF field. */ +#define USBD_EVENTS_SOF_EVENTS_SOF_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_SOF_EVENTS_SOF_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_USBEVENT */ /* Description: An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */ -/* Bit 0 : */ +/* Bit 0 : An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */ #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos (0UL) /*!< Position of EVENTS_USBEVENT field. */ #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Msk (0x1UL << USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos) /*!< Bit mask of EVENTS_USBEVENT field. */ +#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_EP0SETUP */ /* Description: A valid SETUP token has been received (and acknowledged) on the control endpoint */ -/* Bit 0 : */ +/* Bit 0 : A valid SETUP token has been received (and acknowledged) on the control endpoint */ #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos (0UL) /*!< Position of EVENTS_EP0SETUP field. */ #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Msk (0x1UL << USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos) /*!< Bit mask of EVENTS_EP0SETUP field. */ +#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_EPDATA */ /* Description: A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */ -/* Bit 0 : */ +/* Bit 0 : A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */ #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos (0UL) /*!< Position of EVENTS_EPDATA field. */ #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Msk (0x1UL << USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos) /*!< Bit mask of EVENTS_EPDATA field. */ +#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Generated (1UL) /*!< Event generated */ /* Register: USBD_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 4 : Shortcut between ENDEPOUT[0] event and EP0RCVOUT task */ +/* Bit 4 : Shortcut between event ENDEPOUT[0] and task EP0RCVOUT */ #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos (4UL) /*!< Position of ENDEPOUT0_EP0RCVOUT field. */ #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos) /*!< Bit mask of ENDEPOUT0_EP0RCVOUT field. */ #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Disabled (0UL) /*!< Disable shortcut */ #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between ENDEPOUT[0] event and EP0STATUS task */ +/* Bit 3 : Shortcut between event ENDEPOUT[0] and task EP0STATUS */ #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos (3UL) /*!< Position of ENDEPOUT0_EP0STATUS field. */ #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos) /*!< Bit mask of ENDEPOUT0_EP0STATUS field. */ #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */ #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between EP0DATADONE event and EP0STATUS task */ +/* Bit 2 : Shortcut between event EP0DATADONE and task EP0STATUS */ #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos (2UL) /*!< Position of EP0DATADONE_EP0STATUS field. */ #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos) /*!< Bit mask of EP0DATADONE_EP0STATUS field. */ #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */ #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between EP0DATADONE event and STARTEPOUT[0] task */ +/* Bit 1 : Shortcut between event EP0DATADONE and task STARTEPOUT[0] */ #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos (1UL) /*!< Position of EP0DATADONE_STARTEPOUT0 field. */ #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPOUT0 field. */ #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Disabled (0UL) /*!< Disable shortcut */ #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between EP0DATADONE event and STARTEPIN[0] task */ +/* Bit 0 : Shortcut between event EP0DATADONE and task STARTEPIN[0] */ #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos (0UL) /*!< Position of EP0DATADONE_STARTEPIN0 field. */ #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPIN0 field. */ #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Disabled (0UL) /*!< Disable shortcut */ @@ -15566,151 +16113,151 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 24 : Enable or disable interrupt for EPDATA event */ +/* Bit 24 : Enable or disable interrupt for event EPDATA */ #define USBD_INTEN_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */ #define USBD_INTEN_EPDATA_Msk (0x1UL << USBD_INTEN_EPDATA_Pos) /*!< Bit mask of EPDATA field. */ #define USBD_INTEN_EPDATA_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_EPDATA_Enabled (1UL) /*!< Enable */ -/* Bit 23 : Enable or disable interrupt for EP0SETUP event */ +/* Bit 23 : Enable or disable interrupt for event EP0SETUP */ #define USBD_INTEN_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */ #define USBD_INTEN_EP0SETUP_Msk (0x1UL << USBD_INTEN_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */ #define USBD_INTEN_EP0SETUP_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_EP0SETUP_Enabled (1UL) /*!< Enable */ -/* Bit 22 : Enable or disable interrupt for USBEVENT event */ +/* Bit 22 : Enable or disable interrupt for event USBEVENT */ #define USBD_INTEN_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */ #define USBD_INTEN_USBEVENT_Msk (0x1UL << USBD_INTEN_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */ #define USBD_INTEN_USBEVENT_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_USBEVENT_Enabled (1UL) /*!< Enable */ -/* Bit 21 : Enable or disable interrupt for SOF event */ +/* Bit 21 : Enable or disable interrupt for event SOF */ #define USBD_INTEN_SOF_Pos (21UL) /*!< Position of SOF field. */ #define USBD_INTEN_SOF_Msk (0x1UL << USBD_INTEN_SOF_Pos) /*!< Bit mask of SOF field. */ #define USBD_INTEN_SOF_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_SOF_Enabled (1UL) /*!< Enable */ -/* Bit 20 : Enable or disable interrupt for ENDISOOUT event */ +/* Bit 20 : Enable or disable interrupt for event ENDISOOUT */ #define USBD_INTEN_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */ #define USBD_INTEN_ENDISOOUT_Msk (0x1UL << USBD_INTEN_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */ #define USBD_INTEN_ENDISOOUT_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDISOOUT_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for ENDEPOUT[7] event */ +/* Bit 19 : Enable or disable interrupt for event ENDEPOUT[7] */ #define USBD_INTEN_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */ #define USBD_INTEN_ENDEPOUT7_Msk (0x1UL << USBD_INTEN_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */ #define USBD_INTEN_ENDEPOUT7_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT7_Enabled (1UL) /*!< Enable */ -/* Bit 18 : Enable or disable interrupt for ENDEPOUT[6] event */ +/* Bit 18 : Enable or disable interrupt for event ENDEPOUT[6] */ #define USBD_INTEN_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */ #define USBD_INTEN_ENDEPOUT6_Msk (0x1UL << USBD_INTEN_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */ #define USBD_INTEN_ENDEPOUT6_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT6_Enabled (1UL) /*!< Enable */ -/* Bit 17 : Enable or disable interrupt for ENDEPOUT[5] event */ +/* Bit 17 : Enable or disable interrupt for event ENDEPOUT[5] */ #define USBD_INTEN_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */ #define USBD_INTEN_ENDEPOUT5_Msk (0x1UL << USBD_INTEN_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */ #define USBD_INTEN_ENDEPOUT5_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT5_Enabled (1UL) /*!< Enable */ -/* Bit 16 : Enable or disable interrupt for ENDEPOUT[4] event */ +/* Bit 16 : Enable or disable interrupt for event ENDEPOUT[4] */ #define USBD_INTEN_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */ #define USBD_INTEN_ENDEPOUT4_Msk (0x1UL << USBD_INTEN_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */ #define USBD_INTEN_ENDEPOUT4_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT4_Enabled (1UL) /*!< Enable */ -/* Bit 15 : Enable or disable interrupt for ENDEPOUT[3] event */ +/* Bit 15 : Enable or disable interrupt for event ENDEPOUT[3] */ #define USBD_INTEN_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */ #define USBD_INTEN_ENDEPOUT3_Msk (0x1UL << USBD_INTEN_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */ #define USBD_INTEN_ENDEPOUT3_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT3_Enabled (1UL) /*!< Enable */ -/* Bit 14 : Enable or disable interrupt for ENDEPOUT[2] event */ +/* Bit 14 : Enable or disable interrupt for event ENDEPOUT[2] */ #define USBD_INTEN_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */ #define USBD_INTEN_ENDEPOUT2_Msk (0x1UL << USBD_INTEN_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */ #define USBD_INTEN_ENDEPOUT2_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT2_Enabled (1UL) /*!< Enable */ -/* Bit 13 : Enable or disable interrupt for ENDEPOUT[1] event */ +/* Bit 13 : Enable or disable interrupt for event ENDEPOUT[1] */ #define USBD_INTEN_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */ #define USBD_INTEN_ENDEPOUT1_Msk (0x1UL << USBD_INTEN_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */ #define USBD_INTEN_ENDEPOUT1_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT1_Enabled (1UL) /*!< Enable */ -/* Bit 12 : Enable or disable interrupt for ENDEPOUT[0] event */ +/* Bit 12 : Enable or disable interrupt for event ENDEPOUT[0] */ #define USBD_INTEN_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */ #define USBD_INTEN_ENDEPOUT0_Msk (0x1UL << USBD_INTEN_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */ #define USBD_INTEN_ENDEPOUT0_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT0_Enabled (1UL) /*!< Enable */ -/* Bit 11 : Enable or disable interrupt for ENDISOIN event */ +/* Bit 11 : Enable or disable interrupt for event ENDISOIN */ #define USBD_INTEN_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */ #define USBD_INTEN_ENDISOIN_Msk (0x1UL << USBD_INTEN_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */ #define USBD_INTEN_ENDISOIN_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDISOIN_Enabled (1UL) /*!< Enable */ -/* Bit 10 : Enable or disable interrupt for EP0DATADONE event */ +/* Bit 10 : Enable or disable interrupt for event EP0DATADONE */ #define USBD_INTEN_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */ #define USBD_INTEN_EP0DATADONE_Msk (0x1UL << USBD_INTEN_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */ #define USBD_INTEN_EP0DATADONE_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_EP0DATADONE_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for ENDEPIN[7] event */ +/* Bit 9 : Enable or disable interrupt for event ENDEPIN[7] */ #define USBD_INTEN_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */ #define USBD_INTEN_ENDEPIN7_Msk (0x1UL << USBD_INTEN_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */ #define USBD_INTEN_ENDEPIN7_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN7_Enabled (1UL) /*!< Enable */ -/* Bit 8 : Enable or disable interrupt for ENDEPIN[6] event */ +/* Bit 8 : Enable or disable interrupt for event ENDEPIN[6] */ #define USBD_INTEN_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */ #define USBD_INTEN_ENDEPIN6_Msk (0x1UL << USBD_INTEN_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */ #define USBD_INTEN_ENDEPIN6_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN6_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for ENDEPIN[5] event */ +/* Bit 7 : Enable or disable interrupt for event ENDEPIN[5] */ #define USBD_INTEN_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */ #define USBD_INTEN_ENDEPIN5_Msk (0x1UL << USBD_INTEN_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */ #define USBD_INTEN_ENDEPIN5_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN5_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for ENDEPIN[4] event */ +/* Bit 6 : Enable or disable interrupt for event ENDEPIN[4] */ #define USBD_INTEN_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */ #define USBD_INTEN_ENDEPIN4_Msk (0x1UL << USBD_INTEN_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */ #define USBD_INTEN_ENDEPIN4_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN4_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for ENDEPIN[3] event */ +/* Bit 5 : Enable or disable interrupt for event ENDEPIN[3] */ #define USBD_INTEN_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */ #define USBD_INTEN_ENDEPIN3_Msk (0x1UL << USBD_INTEN_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */ #define USBD_INTEN_ENDEPIN3_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN3_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for ENDEPIN[2] event */ +/* Bit 4 : Enable or disable interrupt for event ENDEPIN[2] */ #define USBD_INTEN_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */ #define USBD_INTEN_ENDEPIN2_Msk (0x1UL << USBD_INTEN_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */ #define USBD_INTEN_ENDEPIN2_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN2_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for ENDEPIN[1] event */ +/* Bit 3 : Enable or disable interrupt for event ENDEPIN[1] */ #define USBD_INTEN_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */ #define USBD_INTEN_ENDEPIN1_Msk (0x1UL << USBD_INTEN_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */ #define USBD_INTEN_ENDEPIN1_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN1_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for ENDEPIN[0] event */ +/* Bit 2 : Enable or disable interrupt for event ENDEPIN[0] */ #define USBD_INTEN_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */ #define USBD_INTEN_ENDEPIN0_Msk (0x1UL << USBD_INTEN_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */ #define USBD_INTEN_ENDEPIN0_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN0_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for STARTED event */ +/* Bit 1 : Enable or disable interrupt for event STARTED */ #define USBD_INTEN_STARTED_Pos (1UL) /*!< Position of STARTED field. */ #define USBD_INTEN_STARTED_Msk (0x1UL << USBD_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define USBD_INTEN_STARTED_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_STARTED_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for USBRESET event */ +/* Bit 0 : Enable or disable interrupt for event USBRESET */ #define USBD_INTEN_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */ #define USBD_INTEN_USBRESET_Msk (0x1UL << USBD_INTEN_USBRESET_Pos) /*!< Bit mask of USBRESET field. */ #define USBD_INTEN_USBRESET_Disabled (0UL) /*!< Disable */ @@ -15719,175 +16266,175 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_INTENSET */ /* Description: Enable interrupt */ -/* Bit 24 : Write '1' to enable interrupt for EPDATA event */ +/* Bit 24 : Write '1' to enable interrupt for event EPDATA */ #define USBD_INTENSET_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */ #define USBD_INTENSET_EPDATA_Msk (0x1UL << USBD_INTENSET_EPDATA_Pos) /*!< Bit mask of EPDATA field. */ #define USBD_INTENSET_EPDATA_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_EPDATA_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_EPDATA_Set (1UL) /*!< Enable */ -/* Bit 23 : Write '1' to enable interrupt for EP0SETUP event */ +/* Bit 23 : Write '1' to enable interrupt for event EP0SETUP */ #define USBD_INTENSET_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */ #define USBD_INTENSET_EP0SETUP_Msk (0x1UL << USBD_INTENSET_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */ #define USBD_INTENSET_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_EP0SETUP_Set (1UL) /*!< Enable */ -/* Bit 22 : Write '1' to enable interrupt for USBEVENT event */ +/* Bit 22 : Write '1' to enable interrupt for event USBEVENT */ #define USBD_INTENSET_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */ #define USBD_INTENSET_USBEVENT_Msk (0x1UL << USBD_INTENSET_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */ #define USBD_INTENSET_USBEVENT_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_USBEVENT_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_USBEVENT_Set (1UL) /*!< Enable */ -/* Bit 21 : Write '1' to enable interrupt for SOF event */ +/* Bit 21 : Write '1' to enable interrupt for event SOF */ #define USBD_INTENSET_SOF_Pos (21UL) /*!< Position of SOF field. */ #define USBD_INTENSET_SOF_Msk (0x1UL << USBD_INTENSET_SOF_Pos) /*!< Bit mask of SOF field. */ #define USBD_INTENSET_SOF_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_SOF_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_SOF_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for ENDISOOUT event */ +/* Bit 20 : Write '1' to enable interrupt for event ENDISOOUT */ #define USBD_INTENSET_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */ #define USBD_INTENSET_ENDISOOUT_Msk (0x1UL << USBD_INTENSET_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */ #define USBD_INTENSET_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDISOOUT_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for ENDEPOUT[7] event */ +/* Bit 19 : Write '1' to enable interrupt for event ENDEPOUT[7] */ #define USBD_INTENSET_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */ #define USBD_INTENSET_ENDEPOUT7_Msk (0x1UL << USBD_INTENSET_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */ #define USBD_INTENSET_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT7_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for ENDEPOUT[6] event */ +/* Bit 18 : Write '1' to enable interrupt for event ENDEPOUT[6] */ #define USBD_INTENSET_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */ #define USBD_INTENSET_ENDEPOUT6_Msk (0x1UL << USBD_INTENSET_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */ #define USBD_INTENSET_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT6_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for ENDEPOUT[5] event */ +/* Bit 17 : Write '1' to enable interrupt for event ENDEPOUT[5] */ #define USBD_INTENSET_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */ #define USBD_INTENSET_ENDEPOUT5_Msk (0x1UL << USBD_INTENSET_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */ #define USBD_INTENSET_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT5_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable interrupt for ENDEPOUT[4] event */ +/* Bit 16 : Write '1' to enable interrupt for event ENDEPOUT[4] */ #define USBD_INTENSET_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */ #define USBD_INTENSET_ENDEPOUT4_Msk (0x1UL << USBD_INTENSET_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */ #define USBD_INTENSET_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT4_Set (1UL) /*!< Enable */ -/* Bit 15 : Write '1' to enable interrupt for ENDEPOUT[3] event */ +/* Bit 15 : Write '1' to enable interrupt for event ENDEPOUT[3] */ #define USBD_INTENSET_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */ #define USBD_INTENSET_ENDEPOUT3_Msk (0x1UL << USBD_INTENSET_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */ #define USBD_INTENSET_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT3_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to enable interrupt for ENDEPOUT[2] event */ +/* Bit 14 : Write '1' to enable interrupt for event ENDEPOUT[2] */ #define USBD_INTENSET_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */ #define USBD_INTENSET_ENDEPOUT2_Msk (0x1UL << USBD_INTENSET_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */ #define USBD_INTENSET_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT2_Set (1UL) /*!< Enable */ -/* Bit 13 : Write '1' to enable interrupt for ENDEPOUT[1] event */ +/* Bit 13 : Write '1' to enable interrupt for event ENDEPOUT[1] */ #define USBD_INTENSET_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */ #define USBD_INTENSET_ENDEPOUT1_Msk (0x1UL << USBD_INTENSET_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */ #define USBD_INTENSET_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT1_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to enable interrupt for ENDEPOUT[0] event */ +/* Bit 12 : Write '1' to enable interrupt for event ENDEPOUT[0] */ #define USBD_INTENSET_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */ #define USBD_INTENSET_ENDEPOUT0_Msk (0x1UL << USBD_INTENSET_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */ #define USBD_INTENSET_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT0_Set (1UL) /*!< Enable */ -/* Bit 11 : Write '1' to enable interrupt for ENDISOIN event */ +/* Bit 11 : Write '1' to enable interrupt for event ENDISOIN */ #define USBD_INTENSET_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */ #define USBD_INTENSET_ENDISOIN_Msk (0x1UL << USBD_INTENSET_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */ #define USBD_INTENSET_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDISOIN_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to enable interrupt for EP0DATADONE event */ +/* Bit 10 : Write '1' to enable interrupt for event EP0DATADONE */ #define USBD_INTENSET_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */ #define USBD_INTENSET_EP0DATADONE_Msk (0x1UL << USBD_INTENSET_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */ #define USBD_INTENSET_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_EP0DATADONE_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for ENDEPIN[7] event */ +/* Bit 9 : Write '1' to enable interrupt for event ENDEPIN[7] */ #define USBD_INTENSET_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */ #define USBD_INTENSET_ENDEPIN7_Msk (0x1UL << USBD_INTENSET_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */ #define USBD_INTENSET_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN7_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for ENDEPIN[6] event */ +/* Bit 8 : Write '1' to enable interrupt for event ENDEPIN[6] */ #define USBD_INTENSET_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */ #define USBD_INTENSET_ENDEPIN6_Msk (0x1UL << USBD_INTENSET_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */ #define USBD_INTENSET_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN6_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for ENDEPIN[5] event */ +/* Bit 7 : Write '1' to enable interrupt for event ENDEPIN[5] */ #define USBD_INTENSET_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */ #define USBD_INTENSET_ENDEPIN5_Msk (0x1UL << USBD_INTENSET_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */ #define USBD_INTENSET_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN5_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for ENDEPIN[4] event */ +/* Bit 6 : Write '1' to enable interrupt for event ENDEPIN[4] */ #define USBD_INTENSET_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */ #define USBD_INTENSET_ENDEPIN4_Msk (0x1UL << USBD_INTENSET_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */ #define USBD_INTENSET_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN4_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for ENDEPIN[3] event */ +/* Bit 5 : Write '1' to enable interrupt for event ENDEPIN[3] */ #define USBD_INTENSET_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */ #define USBD_INTENSET_ENDEPIN3_Msk (0x1UL << USBD_INTENSET_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */ #define USBD_INTENSET_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN3_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for ENDEPIN[2] event */ +/* Bit 4 : Write '1' to enable interrupt for event ENDEPIN[2] */ #define USBD_INTENSET_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */ #define USBD_INTENSET_ENDEPIN2_Msk (0x1UL << USBD_INTENSET_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */ #define USBD_INTENSET_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN2_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for ENDEPIN[1] event */ +/* Bit 3 : Write '1' to enable interrupt for event ENDEPIN[1] */ #define USBD_INTENSET_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */ #define USBD_INTENSET_ENDEPIN1_Msk (0x1UL << USBD_INTENSET_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */ #define USBD_INTENSET_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN1_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for ENDEPIN[0] event */ +/* Bit 2 : Write '1' to enable interrupt for event ENDEPIN[0] */ #define USBD_INTENSET_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */ #define USBD_INTENSET_ENDEPIN0_Msk (0x1UL << USBD_INTENSET_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */ #define USBD_INTENSET_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN0_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for STARTED event */ +/* Bit 1 : Write '1' to enable interrupt for event STARTED */ #define USBD_INTENSET_STARTED_Pos (1UL) /*!< Position of STARTED field. */ #define USBD_INTENSET_STARTED_Msk (0x1UL << USBD_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define USBD_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_STARTED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for USBRESET event */ +/* Bit 0 : Write '1' to enable interrupt for event USBRESET */ #define USBD_INTENSET_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */ #define USBD_INTENSET_USBRESET_Msk (0x1UL << USBD_INTENSET_USBRESET_Pos) /*!< Bit mask of USBRESET field. */ #define USBD_INTENSET_USBRESET_Disabled (0UL) /*!< Read: Disabled */ @@ -15897,175 +16444,175 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 24 : Write '1' to disable interrupt for EPDATA event */ +/* Bit 24 : Write '1' to disable interrupt for event EPDATA */ #define USBD_INTENCLR_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */ #define USBD_INTENCLR_EPDATA_Msk (0x1UL << USBD_INTENCLR_EPDATA_Pos) /*!< Bit mask of EPDATA field. */ #define USBD_INTENCLR_EPDATA_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_EPDATA_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_EPDATA_Clear (1UL) /*!< Disable */ -/* Bit 23 : Write '1' to disable interrupt for EP0SETUP event */ +/* Bit 23 : Write '1' to disable interrupt for event EP0SETUP */ #define USBD_INTENCLR_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */ #define USBD_INTENCLR_EP0SETUP_Msk (0x1UL << USBD_INTENCLR_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */ #define USBD_INTENCLR_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_EP0SETUP_Clear (1UL) /*!< Disable */ -/* Bit 22 : Write '1' to disable interrupt for USBEVENT event */ +/* Bit 22 : Write '1' to disable interrupt for event USBEVENT */ #define USBD_INTENCLR_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */ #define USBD_INTENCLR_USBEVENT_Msk (0x1UL << USBD_INTENCLR_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */ #define USBD_INTENCLR_USBEVENT_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_USBEVENT_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_USBEVENT_Clear (1UL) /*!< Disable */ -/* Bit 21 : Write '1' to disable interrupt for SOF event */ +/* Bit 21 : Write '1' to disable interrupt for event SOF */ #define USBD_INTENCLR_SOF_Pos (21UL) /*!< Position of SOF field. */ #define USBD_INTENCLR_SOF_Msk (0x1UL << USBD_INTENCLR_SOF_Pos) /*!< Bit mask of SOF field. */ #define USBD_INTENCLR_SOF_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_SOF_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_SOF_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for ENDISOOUT event */ +/* Bit 20 : Write '1' to disable interrupt for event ENDISOOUT */ #define USBD_INTENCLR_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */ #define USBD_INTENCLR_ENDISOOUT_Msk (0x1UL << USBD_INTENCLR_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */ #define USBD_INTENCLR_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDISOOUT_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for ENDEPOUT[7] event */ +/* Bit 19 : Write '1' to disable interrupt for event ENDEPOUT[7] */ #define USBD_INTENCLR_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */ #define USBD_INTENCLR_ENDEPOUT7_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */ #define USBD_INTENCLR_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT7_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for ENDEPOUT[6] event */ +/* Bit 18 : Write '1' to disable interrupt for event ENDEPOUT[6] */ #define USBD_INTENCLR_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */ #define USBD_INTENCLR_ENDEPOUT6_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */ #define USBD_INTENCLR_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT6_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for ENDEPOUT[5] event */ +/* Bit 17 : Write '1' to disable interrupt for event ENDEPOUT[5] */ #define USBD_INTENCLR_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */ #define USBD_INTENCLR_ENDEPOUT5_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */ #define USBD_INTENCLR_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT5_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable interrupt for ENDEPOUT[4] event */ +/* Bit 16 : Write '1' to disable interrupt for event ENDEPOUT[4] */ #define USBD_INTENCLR_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */ #define USBD_INTENCLR_ENDEPOUT4_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */ #define USBD_INTENCLR_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT4_Clear (1UL) /*!< Disable */ -/* Bit 15 : Write '1' to disable interrupt for ENDEPOUT[3] event */ +/* Bit 15 : Write '1' to disable interrupt for event ENDEPOUT[3] */ #define USBD_INTENCLR_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */ #define USBD_INTENCLR_ENDEPOUT3_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */ #define USBD_INTENCLR_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT3_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to disable interrupt for ENDEPOUT[2] event */ +/* Bit 14 : Write '1' to disable interrupt for event ENDEPOUT[2] */ #define USBD_INTENCLR_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */ #define USBD_INTENCLR_ENDEPOUT2_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */ #define USBD_INTENCLR_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT2_Clear (1UL) /*!< Disable */ -/* Bit 13 : Write '1' to disable interrupt for ENDEPOUT[1] event */ +/* Bit 13 : Write '1' to disable interrupt for event ENDEPOUT[1] */ #define USBD_INTENCLR_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */ #define USBD_INTENCLR_ENDEPOUT1_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */ #define USBD_INTENCLR_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT1_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to disable interrupt for ENDEPOUT[0] event */ +/* Bit 12 : Write '1' to disable interrupt for event ENDEPOUT[0] */ #define USBD_INTENCLR_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */ #define USBD_INTENCLR_ENDEPOUT0_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */ #define USBD_INTENCLR_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT0_Clear (1UL) /*!< Disable */ -/* Bit 11 : Write '1' to disable interrupt for ENDISOIN event */ +/* Bit 11 : Write '1' to disable interrupt for event ENDISOIN */ #define USBD_INTENCLR_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */ #define USBD_INTENCLR_ENDISOIN_Msk (0x1UL << USBD_INTENCLR_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */ #define USBD_INTENCLR_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDISOIN_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to disable interrupt for EP0DATADONE event */ +/* Bit 10 : Write '1' to disable interrupt for event EP0DATADONE */ #define USBD_INTENCLR_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */ #define USBD_INTENCLR_EP0DATADONE_Msk (0x1UL << USBD_INTENCLR_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */ #define USBD_INTENCLR_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_EP0DATADONE_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for ENDEPIN[7] event */ +/* Bit 9 : Write '1' to disable interrupt for event ENDEPIN[7] */ #define USBD_INTENCLR_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */ #define USBD_INTENCLR_ENDEPIN7_Msk (0x1UL << USBD_INTENCLR_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */ #define USBD_INTENCLR_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN7_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for ENDEPIN[6] event */ +/* Bit 8 : Write '1' to disable interrupt for event ENDEPIN[6] */ #define USBD_INTENCLR_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */ #define USBD_INTENCLR_ENDEPIN6_Msk (0x1UL << USBD_INTENCLR_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */ #define USBD_INTENCLR_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN6_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for ENDEPIN[5] event */ +/* Bit 7 : Write '1' to disable interrupt for event ENDEPIN[5] */ #define USBD_INTENCLR_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */ #define USBD_INTENCLR_ENDEPIN5_Msk (0x1UL << USBD_INTENCLR_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */ #define USBD_INTENCLR_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN5_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for ENDEPIN[4] event */ +/* Bit 6 : Write '1' to disable interrupt for event ENDEPIN[4] */ #define USBD_INTENCLR_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */ #define USBD_INTENCLR_ENDEPIN4_Msk (0x1UL << USBD_INTENCLR_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */ #define USBD_INTENCLR_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN4_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for ENDEPIN[3] event */ +/* Bit 5 : Write '1' to disable interrupt for event ENDEPIN[3] */ #define USBD_INTENCLR_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */ #define USBD_INTENCLR_ENDEPIN3_Msk (0x1UL << USBD_INTENCLR_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */ #define USBD_INTENCLR_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN3_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for ENDEPIN[2] event */ +/* Bit 4 : Write '1' to disable interrupt for event ENDEPIN[2] */ #define USBD_INTENCLR_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */ #define USBD_INTENCLR_ENDEPIN2_Msk (0x1UL << USBD_INTENCLR_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */ #define USBD_INTENCLR_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN2_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for ENDEPIN[1] event */ +/* Bit 3 : Write '1' to disable interrupt for event ENDEPIN[1] */ #define USBD_INTENCLR_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */ #define USBD_INTENCLR_ENDEPIN1_Msk (0x1UL << USBD_INTENCLR_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */ #define USBD_INTENCLR_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN1_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for ENDEPIN[0] event */ +/* Bit 2 : Write '1' to disable interrupt for event ENDEPIN[0] */ #define USBD_INTENCLR_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */ #define USBD_INTENCLR_ENDEPIN0_Msk (0x1UL << USBD_INTENCLR_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */ #define USBD_INTENCLR_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN0_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for STARTED event */ +/* Bit 1 : Write '1' to disable interrupt for event STARTED */ #define USBD_INTENCLR_STARTED_Pos (1UL) /*!< Position of STARTED field. */ #define USBD_INTENCLR_STARTED_Msk (0x1UL << USBD_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define USBD_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for USBRESET event */ +/* Bit 0 : Write '1' to disable interrupt for event USBRESET */ #define USBD_INTENCLR_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */ #define USBD_INTENCLR_USBRESET_Msk (0x1UL << USBD_INTENCLR_USBRESET_Pos) /*!< Bit mask of USBRESET field. */ #define USBD_INTENCLR_USBRESET_Disabled (0UL) /*!< Read: Disabled */ @@ -16106,7 +16653,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define USBD_EVENTCAUSE_ISOOUTCRC_Detected (1UL) /*!< Error detected */ /* Register: USBD_HALTED_EPIN */ -/* Description: Description collection[n]: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ +/* Description: Description collection: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ /* Bits 15..0 : IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ #define USBD_HALTED_EPIN_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */ @@ -16115,7 +16662,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define USBD_HALTED_EPIN_GETSTATUS_Halted (1UL) /*!< Endpoint is halted */ /* Register: USBD_HALTED_EPOUT */ -/* Description: Description collection[n]: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ +/* Description: Description collection: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ /* Bits 15..0 : OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ #define USBD_HALTED_EPOUT_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */ @@ -16413,7 +16960,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define USBD_WLENGTHH_WLENGTHH_Msk (0xFFUL << USBD_WLENGTHH_WLENGTHH_Pos) /*!< Bit mask of WLENGTHH field. */ /* Register: USBD_SIZE_EPOUT */ -/* Description: Description collection[n]: Number of bytes received last in the data stage of this OUT endpoint */ +/* Description: Description collection: Number of bytes received last in the data stage of this OUT endpoint */ /* Bits 6..0 : Number of bytes received last in the data stage of this OUT endpoint */ #define USBD_SIZE_EPOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */ @@ -16619,7 +17166,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Bits 15..0 : Controls the split of ISO buffers */ #define USBD_ISOSPLIT_SPLIT_Pos (0UL) /*!< Position of SPLIT field. */ #define USBD_ISOSPLIT_SPLIT_Msk (0xFFFFUL << USBD_ISOSPLIT_SPLIT_Pos) /*!< Bit mask of SPLIT field. */ -#define USBD_ISOSPLIT_SPLIT_OneDir (0x0000UL) /*!< Full buffer dedicated to either iso IN or OUT */ +#define USBD_ISOSPLIT_SPLIT_OneDir (0x0000UL) /*!< Full buffer dedicated to either ISO IN or OUT */ #define USBD_ISOSPLIT_SPLIT_HalfIN (0x0080UL) /*!< Lower half for IN, upper half for OUT */ /* Register: USBD_FRAMECNTR */ @@ -16648,21 +17195,21 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define USBD_ISOINCONFIG_RESPONSE_ZeroData (1UL) /*!< Endpoint responds with a zero-length data packet in that case */ /* Register: USBD_EPIN_PTR */ -/* Description: Description cluster[n]: Data pointer */ +/* Description: Description cluster: Data pointer */ -/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ +/* Bits 31..0 : Data pointer */ #define USBD_EPIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define USBD_EPIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ /* Register: USBD_EPIN_MAXCNT */ -/* Description: Description cluster[n]: Maximum number of bytes to transfer */ +/* Description: Description cluster: Maximum number of bytes to transfer */ /* Bits 6..0 : Maximum number of bytes to transfer */ #define USBD_EPIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ #define USBD_EPIN_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ /* Register: USBD_EPIN_AMOUNT */ -/* Description: Description cluster[n]: Number of bytes transferred in the last transaction */ +/* Description: Description cluster: Number of bytes transferred in the last transaction */ /* Bits 6..0 : Number of bytes transferred in the last transaction */ #define USBD_EPIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ @@ -16671,7 +17218,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_ISOIN_PTR */ /* Description: Data pointer */ -/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ +/* Bits 31..0 : Data pointer */ #define USBD_ISOIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define USBD_ISOIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ @@ -16690,21 +17237,21 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define USBD_ISOIN_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ /* Register: USBD_EPOUT_PTR */ -/* Description: Description cluster[n]: Data pointer */ +/* Description: Description cluster: Data pointer */ -/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ +/* Bits 31..0 : Data pointer */ #define USBD_EPOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define USBD_EPOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ /* Register: USBD_EPOUT_MAXCNT */ -/* Description: Description cluster[n]: Maximum number of bytes to transfer */ +/* Description: Description cluster: Maximum number of bytes to transfer */ /* Bits 6..0 : Maximum number of bytes to transfer */ #define USBD_EPOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ #define USBD_EPOUT_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ /* Register: USBD_EPOUT_AMOUNT */ -/* Description: Description cluster[n]: Number of bytes transferred in the last transaction */ +/* Description: Description cluster: Number of bytes transferred in the last transaction */ /* Bits 6..0 : Number of bytes transferred in the last transaction */ #define USBD_EPOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ @@ -16713,7 +17260,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_ISOOUT_PTR */ /* Description: Data pointer */ -/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ +/* Bits 31..0 : Data pointer */ #define USBD_ISOOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define USBD_ISOOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ @@ -16738,21 +17285,24 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: WDT_TASKS_START */ /* Description: Start the watchdog */ -/* Bit 0 : */ +/* Bit 0 : Start the watchdog */ #define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: WDT_EVENTS_TIMEOUT */ /* Description: Watchdog timeout */ -/* Bit 0 : */ +/* Bit 0 : Watchdog timeout */ #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */ #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL) /*!< Event not generated */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL) /*!< Event generated */ /* Register: WDT_INTENSET */ /* Description: Enable interrupt */ -/* Bit 0 : Write '1' to enable interrupt for TIMEOUT event */ +/* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */ #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ @@ -16762,7 +17312,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* Register: WDT_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 0 : Write '1' to disable interrupt for TIMEOUT event */ +/* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */ #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ @@ -16903,7 +17453,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */ /* Register: WDT_RR */ -/* Description: Description collection[n]: Reload request n */ +/* Description: Description collection: Reload request n */ /* Bits 31..0 : Reload request register */ #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52840_peripherals.h b/bsp/boards/nrf52840_dk/sdk/nrf52840_peripherals.h similarity index 90% rename from bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52840_peripherals.h rename to bsp/boards/nrf52840_dk/sdk/nrf52840_peripherals.h index 0da6f332b4..00105f88b8 100644 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf52840_peripherals.h +++ b/bsp/boards/nrf52840_dk/sdk/nrf52840_peripherals.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. @@ -43,6 +43,10 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define _NRF52840_PERIPHERALS_H +/* Clock Peripheral */ +#define CLOCK_PRESENT +#define CLOCK_COUNT 1 + /* Power Peripheral */ #define POWER_PRESENT #define POWER_COUNT 1 @@ -51,6 +55,13 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define POWER_FEATURE_RAM_REGISTERS_COUNT 9 #define POWER_FEATURE_VDDH_PRESENT +#define POWER_FEATURE_VDDH_DCDC_PRESENT + +/* Non-Volatile Memory Controller */ +#define NVMC_PRESENT +#define NVMC_COUNT 1 + +#define NVMC_FEATURE_CACHE_PRESENT /* Floating Point Unit */ #define FPU_PRESENT @@ -75,6 +86,9 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define P0_PIN_NUM 32 #define P1_PIN_NUM 16 +#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL +#define P1_FEATURE_PINS_PRESENT 0x0000FFFFUL + /* ACL */ #define ACL_PRESENT @@ -85,6 +99,9 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define RADIO_COUNT 1 #define RADIO_EASYDMA_MAXCNT_SIZE 8 +#define RADIO_FEATURE_IEEE_802_15_4_PRESENT + +#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos8dBm /* Accelerated Address Resolver */ #define AAR_PRESENT diff --git a/bsp/boards/nrf52840_dk/sdk/nrf52_erratas.h b/bsp/boards/nrf52840_dk/sdk/nrf52_erratas.h new file mode 100644 index 0000000000..64846e773d --- /dev/null +++ b/bsp/boards/nrf52840_dk/sdk/nrf52_erratas.h @@ -0,0 +1,13035 @@ +#ifndef NRF52_ERRATAS_H +#define NRF52_ERRATAS_H + +/* + +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#include +#include +#include "compiler_abstraction.h" + +static bool nrf52_errata_1(void) __UNUSED; +static bool nrf52_errata_2(void) __UNUSED; +static bool nrf52_errata_3(void) __UNUSED; +static bool nrf52_errata_4(void) __UNUSED; +static bool nrf52_errata_7(void) __UNUSED; +static bool nrf52_errata_8(void) __UNUSED; +static bool nrf52_errata_9(void) __UNUSED; +static bool nrf52_errata_10(void) __UNUSED; +static bool nrf52_errata_11(void) __UNUSED; +static bool nrf52_errata_12(void) __UNUSED; +static bool nrf52_errata_15(void) __UNUSED; +static bool nrf52_errata_16(void) __UNUSED; +static bool nrf52_errata_17(void) __UNUSED; +static bool nrf52_errata_20(void) __UNUSED; +static bool nrf52_errata_23(void) __UNUSED; +static bool nrf52_errata_24(void) __UNUSED; +static bool nrf52_errata_25(void) __UNUSED; +static bool nrf52_errata_26(void) __UNUSED; +static bool nrf52_errata_27(void) __UNUSED; +static bool nrf52_errata_28(void) __UNUSED; +static bool nrf52_errata_29(void) __UNUSED; +static bool nrf52_errata_30(void) __UNUSED; +static bool nrf52_errata_31(void) __UNUSED; +static bool nrf52_errata_32(void) __UNUSED; +static bool nrf52_errata_33(void) __UNUSED; +static bool nrf52_errata_34(void) __UNUSED; +static bool nrf52_errata_35(void) __UNUSED; +static bool nrf52_errata_36(void) __UNUSED; +static bool nrf52_errata_37(void) __UNUSED; +static bool nrf52_errata_38(void) __UNUSED; +static bool nrf52_errata_39(void) __UNUSED; +static bool nrf52_errata_40(void) __UNUSED; +static bool nrf52_errata_41(void) __UNUSED; +static bool nrf52_errata_42(void) __UNUSED; +static bool nrf52_errata_43(void) __UNUSED; +static bool nrf52_errata_44(void) __UNUSED; +static bool nrf52_errata_46(void) __UNUSED; +static bool nrf52_errata_47(void) __UNUSED; +static bool nrf52_errata_48(void) __UNUSED; +static bool nrf52_errata_49(void) __UNUSED; +static bool nrf52_errata_51(void) __UNUSED; +static bool nrf52_errata_54(void) __UNUSED; +static bool nrf52_errata_55(void) __UNUSED; +static bool nrf52_errata_57(void) __UNUSED; +static bool nrf52_errata_58(void) __UNUSED; +static bool nrf52_errata_62(void) __UNUSED; +static bool nrf52_errata_63(void) __UNUSED; +static bool nrf52_errata_64(void) __UNUSED; +static bool nrf52_errata_65(void) __UNUSED; +static bool nrf52_errata_66(void) __UNUSED; +static bool nrf52_errata_67(void) __UNUSED; +static bool nrf52_errata_68(void) __UNUSED; +static bool nrf52_errata_70(void) __UNUSED; +static bool nrf52_errata_71(void) __UNUSED; +static bool nrf52_errata_72(void) __UNUSED; +static bool nrf52_errata_73(void) __UNUSED; +static bool nrf52_errata_74(void) __UNUSED; +static bool nrf52_errata_75(void) __UNUSED; +static bool nrf52_errata_76(void) __UNUSED; +static bool nrf52_errata_77(void) __UNUSED; +static bool nrf52_errata_78(void) __UNUSED; +static bool nrf52_errata_79(void) __UNUSED; +static bool nrf52_errata_81(void) __UNUSED; +static bool nrf52_errata_83(void) __UNUSED; +static bool nrf52_errata_84(void) __UNUSED; +static bool nrf52_errata_86(void) __UNUSED; +static bool nrf52_errata_87(void) __UNUSED; +static bool nrf52_errata_88(void) __UNUSED; +static bool nrf52_errata_89(void) __UNUSED; +static bool nrf52_errata_91(void) __UNUSED; +static bool nrf52_errata_94(void) __UNUSED; +static bool nrf52_errata_96(void) __UNUSED; +static bool nrf52_errata_97(void) __UNUSED; +static bool nrf52_errata_98(void) __UNUSED; +static bool nrf52_errata_101(void) __UNUSED; +static bool nrf52_errata_102(void) __UNUSED; +static bool nrf52_errata_103(void) __UNUSED; +static bool nrf52_errata_104(void) __UNUSED; +static bool nrf52_errata_106(void) __UNUSED; +static bool nrf52_errata_107(void) __UNUSED; +static bool nrf52_errata_108(void) __UNUSED; +static bool nrf52_errata_109(void) __UNUSED; +static bool nrf52_errata_110(void) __UNUSED; +static bool nrf52_errata_111(void) __UNUSED; +static bool nrf52_errata_112(void) __UNUSED; +static bool nrf52_errata_113(void) __UNUSED; +static bool nrf52_errata_115(void) __UNUSED; +static bool nrf52_errata_116(void) __UNUSED; +static bool nrf52_errata_117(void) __UNUSED; +static bool nrf52_errata_118(void) __UNUSED; +static bool nrf52_errata_119(void) __UNUSED; +static bool nrf52_errata_120(void) __UNUSED; +static bool nrf52_errata_121(void) __UNUSED; +static bool nrf52_errata_122(void) __UNUSED; +static bool nrf52_errata_127(void) __UNUSED; +static bool nrf52_errata_128(void) __UNUSED; +static bool nrf52_errata_131(void) __UNUSED; +static bool nrf52_errata_132(void) __UNUSED; +static bool nrf52_errata_133(void) __UNUSED; +static bool nrf52_errata_134(void) __UNUSED; +static bool nrf52_errata_135(void) __UNUSED; +static bool nrf52_errata_136(void) __UNUSED; +static bool nrf52_errata_138(void) __UNUSED; +static bool nrf52_errata_140(void) __UNUSED; +static bool nrf52_errata_141(void) __UNUSED; +static bool nrf52_errata_142(void) __UNUSED; +static bool nrf52_errata_143(void) __UNUSED; +static bool nrf52_errata_144(void) __UNUSED; +static bool nrf52_errata_145(void) __UNUSED; +static bool nrf52_errata_146(void) __UNUSED; +static bool nrf52_errata_147(void) __UNUSED; +static bool nrf52_errata_149(void) __UNUSED; +static bool nrf52_errata_150(void) __UNUSED; +static bool nrf52_errata_151(void) __UNUSED; +static bool nrf52_errata_153(void) __UNUSED; +static bool nrf52_errata_154(void) __UNUSED; +static bool nrf52_errata_155(void) __UNUSED; +static bool nrf52_errata_156(void) __UNUSED; +static bool nrf52_errata_158(void) __UNUSED; +static bool nrf52_errata_160(void) __UNUSED; +static bool nrf52_errata_162(void) __UNUSED; +static bool nrf52_errata_163(void) __UNUSED; +static bool nrf52_errata_164(void) __UNUSED; +static bool nrf52_errata_166(void) __UNUSED; +static bool nrf52_errata_170(void) __UNUSED; +static bool nrf52_errata_171(void) __UNUSED; +static bool nrf52_errata_172(void) __UNUSED; +static bool nrf52_errata_173(void) __UNUSED; +static bool nrf52_errata_174(void) __UNUSED; +static bool nrf52_errata_176(void) __UNUSED; +static bool nrf52_errata_178(void) __UNUSED; +static bool nrf52_errata_179(void) __UNUSED; +static bool nrf52_errata_180(void) __UNUSED; +static bool nrf52_errata_181(void) __UNUSED; +static bool nrf52_errata_182(void) __UNUSED; +static bool nrf52_errata_183(void) __UNUSED; +static bool nrf52_errata_184(void) __UNUSED; +static bool nrf52_errata_186(void) __UNUSED; +static bool nrf52_errata_187(void) __UNUSED; +static bool nrf52_errata_189(void) __UNUSED; +static bool nrf52_errata_190(void) __UNUSED; +static bool nrf52_errata_191(void) __UNUSED; +static bool nrf52_errata_192(void) __UNUSED; +static bool nrf52_errata_193(void) __UNUSED; +static bool nrf52_errata_194(void) __UNUSED; +static bool nrf52_errata_195(void) __UNUSED; +static bool nrf52_errata_196(void) __UNUSED; +static bool nrf52_errata_197(void) __UNUSED; +static bool nrf52_errata_198(void) __UNUSED; +static bool nrf52_errata_199(void) __UNUSED; +static bool nrf52_errata_200(void) __UNUSED; +static bool nrf52_errata_201(void) __UNUSED; +static bool nrf52_errata_202(void) __UNUSED; +static bool nrf52_errata_204(void) __UNUSED; +static bool nrf52_errata_208(void) __UNUSED; +static bool nrf52_errata_209(void) __UNUSED; +static bool nrf52_errata_210(void) __UNUSED; +static bool nrf52_errata_211(void) __UNUSED; +static bool nrf52_errata_212(void) __UNUSED; +static bool nrf52_errata_213(void) __UNUSED; +static bool nrf52_errata_214(void) __UNUSED; +static bool nrf52_errata_215(void) __UNUSED; +static bool nrf52_errata_216(void) __UNUSED; +static bool nrf52_errata_217(void) __UNUSED; +static bool nrf52_errata_218(void) __UNUSED; +static bool nrf52_errata_219(void) __UNUSED; +static bool nrf52_errata_220(void) __UNUSED; +static bool nrf52_errata_223(void) __UNUSED; +static bool nrf52_errata_225(void) __UNUSED; +static bool nrf52_errata_228(void) __UNUSED; +static bool nrf52_errata_230(void) __UNUSED; +static bool nrf52_errata_231(void) __UNUSED; +static bool nrf52_errata_232(void) __UNUSED; +static bool nrf52_errata_233(void) __UNUSED; +static bool nrf52_errata_236(void) __UNUSED; +static bool nrf52_errata_237(void) __UNUSED; +static bool nrf52_errata_242(void) __UNUSED; +static bool nrf52_errata_243(void) __UNUSED; +static bool nrf52_errata_244(void) __UNUSED; +static bool nrf52_errata_245(void) __UNUSED; +static bool nrf52_errata_246(void) __UNUSED; +static bool nrf52_errata_248(void) __UNUSED; +static bool nrf52_errata_249(void) __UNUSED; +static bool nrf52_errata_250(void) __UNUSED; +static bool nrf52_errata_254(void) __UNUSED; + +/* ========= Errata 1 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_1_PRESENT 1 +#else + #define NRF52_ERRATA_1_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_1_ENABLE_WORKAROUND + #define NRF52_ERRATA_1_ENABLE_WORKAROUND NRF52_ERRATA_1_PRESENT +#endif + +static bool nrf52_errata_1(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 2 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_2_PRESENT 1 +#else + #define NRF52_ERRATA_2_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_2_ENABLE_WORKAROUND + #define NRF52_ERRATA_2_ENABLE_WORKAROUND NRF52_ERRATA_2_PRESENT +#endif + +static bool nrf52_errata_2(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 3 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_3_PRESENT 1 +#else + #define NRF52_ERRATA_3_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_3_ENABLE_WORKAROUND + #define NRF52_ERRATA_3_ENABLE_WORKAROUND NRF52_ERRATA_3_PRESENT +#endif + +static bool nrf52_errata_3(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 4 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_4_PRESENT 1 +#else + #define NRF52_ERRATA_4_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_4_ENABLE_WORKAROUND + #define NRF52_ERRATA_4_ENABLE_WORKAROUND NRF52_ERRATA_4_PRESENT +#endif + +static bool nrf52_errata_4(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 7 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_7_PRESENT 1 +#else + #define NRF52_ERRATA_7_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_7_ENABLE_WORKAROUND + #define NRF52_ERRATA_7_ENABLE_WORKAROUND NRF52_ERRATA_7_PRESENT +#endif + +static bool nrf52_errata_7(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 8 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_8_PRESENT 1 +#else + #define NRF52_ERRATA_8_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_8_ENABLE_WORKAROUND + #define NRF52_ERRATA_8_ENABLE_WORKAROUND NRF52_ERRATA_8_PRESENT +#endif + +static bool nrf52_errata_8(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 9 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_9_PRESENT 1 +#else + #define NRF52_ERRATA_9_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_9_ENABLE_WORKAROUND + #define NRF52_ERRATA_9_ENABLE_WORKAROUND NRF52_ERRATA_9_PRESENT +#endif + +static bool nrf52_errata_9(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 10 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_10_PRESENT 1 +#else + #define NRF52_ERRATA_10_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_10_ENABLE_WORKAROUND + #define NRF52_ERRATA_10_ENABLE_WORKAROUND NRF52_ERRATA_10_PRESENT +#endif + +static bool nrf52_errata_10(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 11 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_11_PRESENT 1 +#else + #define NRF52_ERRATA_11_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_11_ENABLE_WORKAROUND + #define NRF52_ERRATA_11_ENABLE_WORKAROUND NRF52_ERRATA_11_PRESENT +#endif + +static bool nrf52_errata_11(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 12 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_12_PRESENT 1 +#else + #define NRF52_ERRATA_12_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_12_ENABLE_WORKAROUND + #define NRF52_ERRATA_12_ENABLE_WORKAROUND NRF52_ERRATA_12_PRESENT +#endif + +static bool nrf52_errata_12(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 15 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_15_PRESENT 1 +#else + #define NRF52_ERRATA_15_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_15_ENABLE_WORKAROUND + #define NRF52_ERRATA_15_ENABLE_WORKAROUND NRF52_ERRATA_15_PRESENT +#endif + +static bool nrf52_errata_15(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 16 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_16_PRESENT 1 +#else + #define NRF52_ERRATA_16_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_16_ENABLE_WORKAROUND + #define NRF52_ERRATA_16_ENABLE_WORKAROUND NRF52_ERRATA_16_PRESENT +#endif + +static bool nrf52_errata_16(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 17 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_17_PRESENT 1 +#else + #define NRF52_ERRATA_17_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_17_ENABLE_WORKAROUND + #define NRF52_ERRATA_17_ENABLE_WORKAROUND NRF52_ERRATA_17_PRESENT +#endif + +static bool nrf52_errata_17(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 20 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_20_PRESENT 1 +#else + #define NRF52_ERRATA_20_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_20_ENABLE_WORKAROUND + #define NRF52_ERRATA_20_ENABLE_WORKAROUND NRF52_ERRATA_20_PRESENT +#endif + +static bool nrf52_errata_20(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 23 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_23_PRESENT 1 +#else + #define NRF52_ERRATA_23_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_23_ENABLE_WORKAROUND + #define NRF52_ERRATA_23_ENABLE_WORKAROUND NRF52_ERRATA_23_PRESENT +#endif + +static bool nrf52_errata_23(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 24 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_24_PRESENT 1 +#else + #define NRF52_ERRATA_24_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_24_ENABLE_WORKAROUND + #define NRF52_ERRATA_24_ENABLE_WORKAROUND NRF52_ERRATA_24_PRESENT +#endif + +static bool nrf52_errata_24(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 25 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_25_PRESENT 1 +#else + #define NRF52_ERRATA_25_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_25_ENABLE_WORKAROUND + #define NRF52_ERRATA_25_ENABLE_WORKAROUND NRF52_ERRATA_25_PRESENT +#endif + +static bool nrf52_errata_25(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 26 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_26_PRESENT 1 +#else + #define NRF52_ERRATA_26_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_26_ENABLE_WORKAROUND + #define NRF52_ERRATA_26_ENABLE_WORKAROUND NRF52_ERRATA_26_PRESENT +#endif + +static bool nrf52_errata_26(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 27 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_27_PRESENT 1 +#else + #define NRF52_ERRATA_27_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_27_ENABLE_WORKAROUND + #define NRF52_ERRATA_27_ENABLE_WORKAROUND NRF52_ERRATA_27_PRESENT +#endif + +static bool nrf52_errata_27(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 28 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_28_PRESENT 1 +#else + #define NRF52_ERRATA_28_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_28_ENABLE_WORKAROUND + #define NRF52_ERRATA_28_ENABLE_WORKAROUND NRF52_ERRATA_28_PRESENT +#endif + +static bool nrf52_errata_28(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 29 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_29_PRESENT 1 +#else + #define NRF52_ERRATA_29_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_29_ENABLE_WORKAROUND + #define NRF52_ERRATA_29_ENABLE_WORKAROUND NRF52_ERRATA_29_PRESENT +#endif + +static bool nrf52_errata_29(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 30 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_30_PRESENT 1 +#else + #define NRF52_ERRATA_30_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_30_ENABLE_WORKAROUND + #define NRF52_ERRATA_30_ENABLE_WORKAROUND NRF52_ERRATA_30_PRESENT +#endif + +static bool nrf52_errata_30(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 31 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_31_PRESENT 1 +#else + #define NRF52_ERRATA_31_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_31_ENABLE_WORKAROUND + #define NRF52_ERRATA_31_ENABLE_WORKAROUND NRF52_ERRATA_31_PRESENT +#endif + +static bool nrf52_errata_31(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 32 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_32_PRESENT 1 +#else + #define NRF52_ERRATA_32_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_32_ENABLE_WORKAROUND + #define NRF52_ERRATA_32_ENABLE_WORKAROUND NRF52_ERRATA_32_PRESENT +#endif + +static bool nrf52_errata_32(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 33 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_33_PRESENT 1 +#else + #define NRF52_ERRATA_33_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_33_ENABLE_WORKAROUND + #define NRF52_ERRATA_33_ENABLE_WORKAROUND NRF52_ERRATA_33_PRESENT +#endif + +static bool nrf52_errata_33(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 34 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_34_PRESENT 1 +#else + #define NRF52_ERRATA_34_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_34_ENABLE_WORKAROUND + #define NRF52_ERRATA_34_ENABLE_WORKAROUND NRF52_ERRATA_34_PRESENT +#endif + +static bool nrf52_errata_34(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 35 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_35_PRESENT 1 +#else + #define NRF52_ERRATA_35_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_35_ENABLE_WORKAROUND + #define NRF52_ERRATA_35_ENABLE_WORKAROUND NRF52_ERRATA_35_PRESENT +#endif + +static bool nrf52_errata_35(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 36 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_36_PRESENT 1 +#else + #define NRF52_ERRATA_36_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_36_ENABLE_WORKAROUND + #define NRF52_ERRATA_36_ENABLE_WORKAROUND NRF52_ERRATA_36_PRESENT +#endif + +static bool nrf52_errata_36(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 37 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_37_PRESENT 1 +#else + #define NRF52_ERRATA_37_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_37_ENABLE_WORKAROUND + #define NRF52_ERRATA_37_ENABLE_WORKAROUND NRF52_ERRATA_37_PRESENT +#endif + +static bool nrf52_errata_37(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 38 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_38_PRESENT 1 +#else + #define NRF52_ERRATA_38_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_38_ENABLE_WORKAROUND + #define NRF52_ERRATA_38_ENABLE_WORKAROUND NRF52_ERRATA_38_PRESENT +#endif + +static bool nrf52_errata_38(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 39 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_39_PRESENT 1 +#else + #define NRF52_ERRATA_39_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_39_ENABLE_WORKAROUND + #define NRF52_ERRATA_39_ENABLE_WORKAROUND NRF52_ERRATA_39_PRESENT +#endif + +static bool nrf52_errata_39(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 40 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_40_PRESENT 1 +#else + #define NRF52_ERRATA_40_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_40_ENABLE_WORKAROUND + #define NRF52_ERRATA_40_ENABLE_WORKAROUND NRF52_ERRATA_40_PRESENT +#endif + +static bool nrf52_errata_40(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 41 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_41_PRESENT 1 +#else + #define NRF52_ERRATA_41_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_41_ENABLE_WORKAROUND + #define NRF52_ERRATA_41_ENABLE_WORKAROUND NRF52_ERRATA_41_PRESENT +#endif + +static bool nrf52_errata_41(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 42 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_42_PRESENT 1 +#else + #define NRF52_ERRATA_42_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_42_ENABLE_WORKAROUND + #define NRF52_ERRATA_42_ENABLE_WORKAROUND NRF52_ERRATA_42_PRESENT +#endif + +static bool nrf52_errata_42(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 43 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_43_PRESENT 1 +#else + #define NRF52_ERRATA_43_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_43_ENABLE_WORKAROUND + #define NRF52_ERRATA_43_ENABLE_WORKAROUND NRF52_ERRATA_43_PRESENT +#endif + +static bool nrf52_errata_43(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 44 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_44_PRESENT 1 +#else + #define NRF52_ERRATA_44_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_44_ENABLE_WORKAROUND + #define NRF52_ERRATA_44_ENABLE_WORKAROUND NRF52_ERRATA_44_PRESENT +#endif + +static bool nrf52_errata_44(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 46 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_46_PRESENT 1 +#else + #define NRF52_ERRATA_46_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_46_ENABLE_WORKAROUND + #define NRF52_ERRATA_46_ENABLE_WORKAROUND NRF52_ERRATA_46_PRESENT +#endif + +static bool nrf52_errata_46(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 47 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_47_PRESENT 1 +#else + #define NRF52_ERRATA_47_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_47_ENABLE_WORKAROUND + #define NRF52_ERRATA_47_ENABLE_WORKAROUND NRF52_ERRATA_47_PRESENT +#endif + +static bool nrf52_errata_47(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 48 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_48_PRESENT 1 +#else + #define NRF52_ERRATA_48_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_48_ENABLE_WORKAROUND + #define NRF52_ERRATA_48_ENABLE_WORKAROUND NRF52_ERRATA_48_PRESENT +#endif + +static bool nrf52_errata_48(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 49 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_49_PRESENT 1 +#else + #define NRF52_ERRATA_49_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_49_ENABLE_WORKAROUND + #define NRF52_ERRATA_49_ENABLE_WORKAROUND NRF52_ERRATA_49_PRESENT +#endif + +static bool nrf52_errata_49(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 51 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_51_PRESENT 1 +#else + #define NRF52_ERRATA_51_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_51_ENABLE_WORKAROUND + #define NRF52_ERRATA_51_ENABLE_WORKAROUND NRF52_ERRATA_51_PRESENT +#endif + +static bool nrf52_errata_51(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 54 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_54_PRESENT 1 +#else + #define NRF52_ERRATA_54_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_54_ENABLE_WORKAROUND + #define NRF52_ERRATA_54_ENABLE_WORKAROUND NRF52_ERRATA_54_PRESENT +#endif + +static bool nrf52_errata_54(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 55 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_55_PRESENT 1 +#else + #define NRF52_ERRATA_55_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_55_ENABLE_WORKAROUND + #define NRF52_ERRATA_55_ENABLE_WORKAROUND NRF52_ERRATA_55_PRESENT +#endif + +static bool nrf52_errata_55(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 57 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_57_PRESENT 1 +#else + #define NRF52_ERRATA_57_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_57_ENABLE_WORKAROUND + #define NRF52_ERRATA_57_ENABLE_WORKAROUND NRF52_ERRATA_57_PRESENT +#endif + +static bool nrf52_errata_57(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 58 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_58_PRESENT 1 +#else + #define NRF52_ERRATA_58_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_58_ENABLE_WORKAROUND + #define NRF52_ERRATA_58_ENABLE_WORKAROUND NRF52_ERRATA_58_PRESENT +#endif + +static bool nrf52_errata_58(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 62 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_62_PRESENT 1 +#else + #define NRF52_ERRATA_62_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_62_ENABLE_WORKAROUND + #define NRF52_ERRATA_62_ENABLE_WORKAROUND NRF52_ERRATA_62_PRESENT +#endif + +static bool nrf52_errata_62(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 63 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_63_PRESENT 1 +#else + #define NRF52_ERRATA_63_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_63_ENABLE_WORKAROUND + #define NRF52_ERRATA_63_ENABLE_WORKAROUND NRF52_ERRATA_63_PRESENT +#endif + +static bool nrf52_errata_63(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 64 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_64_PRESENT 1 +#else + #define NRF52_ERRATA_64_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_64_ENABLE_WORKAROUND + #define NRF52_ERRATA_64_ENABLE_WORKAROUND NRF52_ERRATA_64_PRESENT +#endif + +static bool nrf52_errata_64(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 65 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_65_PRESENT 1 +#else + #define NRF52_ERRATA_65_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_65_ENABLE_WORKAROUND + #define NRF52_ERRATA_65_ENABLE_WORKAROUND NRF52_ERRATA_65_PRESENT +#endif + +static bool nrf52_errata_65(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 66 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_66_PRESENT 1 +#else + #define NRF52_ERRATA_66_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_66_ENABLE_WORKAROUND + #define NRF52_ERRATA_66_ENABLE_WORKAROUND NRF52_ERRATA_66_PRESENT +#endif + +static bool nrf52_errata_66(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 67 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_67_PRESENT 1 +#else + #define NRF52_ERRATA_67_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_67_ENABLE_WORKAROUND + #define NRF52_ERRATA_67_ENABLE_WORKAROUND NRF52_ERRATA_67_PRESENT +#endif + +static bool nrf52_errata_67(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 68 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_68_PRESENT 1 +#else + #define NRF52_ERRATA_68_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_68_ENABLE_WORKAROUND + #define NRF52_ERRATA_68_ENABLE_WORKAROUND NRF52_ERRATA_68_PRESENT +#endif + +static bool nrf52_errata_68(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 70 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_70_PRESENT 1 +#else + #define NRF52_ERRATA_70_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_70_ENABLE_WORKAROUND + #define NRF52_ERRATA_70_ENABLE_WORKAROUND NRF52_ERRATA_70_PRESENT +#endif + +static bool nrf52_errata_70(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 71 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_71_PRESENT 1 +#else + #define NRF52_ERRATA_71_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_71_ENABLE_WORKAROUND + #define NRF52_ERRATA_71_ENABLE_WORKAROUND NRF52_ERRATA_71_PRESENT +#endif + +static bool nrf52_errata_71(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 72 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_72_PRESENT 1 +#else + #define NRF52_ERRATA_72_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_72_ENABLE_WORKAROUND + #define NRF52_ERRATA_72_ENABLE_WORKAROUND NRF52_ERRATA_72_PRESENT +#endif + +static bool nrf52_errata_72(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 73 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_73_PRESENT 1 +#else + #define NRF52_ERRATA_73_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_73_ENABLE_WORKAROUND + #define NRF52_ERRATA_73_ENABLE_WORKAROUND NRF52_ERRATA_73_PRESENT +#endif + +static bool nrf52_errata_73(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 74 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_74_PRESENT 1 +#else + #define NRF52_ERRATA_74_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_74_ENABLE_WORKAROUND + #define NRF52_ERRATA_74_ENABLE_WORKAROUND NRF52_ERRATA_74_PRESENT +#endif + +static bool nrf52_errata_74(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 75 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_75_PRESENT 1 +#else + #define NRF52_ERRATA_75_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_75_ENABLE_WORKAROUND + #define NRF52_ERRATA_75_ENABLE_WORKAROUND NRF52_ERRATA_75_PRESENT +#endif + +static bool nrf52_errata_75(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 76 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_76_PRESENT 1 +#else + #define NRF52_ERRATA_76_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_76_ENABLE_WORKAROUND + #define NRF52_ERRATA_76_ENABLE_WORKAROUND NRF52_ERRATA_76_PRESENT +#endif + +static bool nrf52_errata_76(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 77 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_77_PRESENT 1 +#else + #define NRF52_ERRATA_77_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_77_ENABLE_WORKAROUND + #define NRF52_ERRATA_77_ENABLE_WORKAROUND NRF52_ERRATA_77_PRESENT +#endif + +static bool nrf52_errata_77(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 78 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_78_PRESENT 1 +#else + #define NRF52_ERRATA_78_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_78_ENABLE_WORKAROUND + #define NRF52_ERRATA_78_ENABLE_WORKAROUND NRF52_ERRATA_78_PRESENT +#endif + +static bool nrf52_errata_78(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 79 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_79_PRESENT 1 +#else + #define NRF52_ERRATA_79_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_79_ENABLE_WORKAROUND + #define NRF52_ERRATA_79_ENABLE_WORKAROUND NRF52_ERRATA_79_PRESENT +#endif + +static bool nrf52_errata_79(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 81 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_81_PRESENT 1 +#else + #define NRF52_ERRATA_81_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_81_ENABLE_WORKAROUND + #define NRF52_ERRATA_81_ENABLE_WORKAROUND NRF52_ERRATA_81_PRESENT +#endif + +static bool nrf52_errata_81(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 83 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_83_PRESENT 1 +#else + #define NRF52_ERRATA_83_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_83_ENABLE_WORKAROUND + #define NRF52_ERRATA_83_ENABLE_WORKAROUND NRF52_ERRATA_83_PRESENT +#endif + +static bool nrf52_errata_83(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 84 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_84_PRESENT 1 +#else + #define NRF52_ERRATA_84_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_84_ENABLE_WORKAROUND + #define NRF52_ERRATA_84_ENABLE_WORKAROUND NRF52_ERRATA_84_PRESENT +#endif + +static bool nrf52_errata_84(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 86 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_86_PRESENT 1 +#else + #define NRF52_ERRATA_86_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_86_ENABLE_WORKAROUND + #define NRF52_ERRATA_86_ENABLE_WORKAROUND NRF52_ERRATA_86_PRESENT +#endif + +static bool nrf52_errata_86(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 87 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_87_PRESENT 1 +#else + #define NRF52_ERRATA_87_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_87_ENABLE_WORKAROUND + #define NRF52_ERRATA_87_ENABLE_WORKAROUND NRF52_ERRATA_87_PRESENT +#endif + +static bool nrf52_errata_87(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 88 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_88_PRESENT 1 +#else + #define NRF52_ERRATA_88_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_88_ENABLE_WORKAROUND + #define NRF52_ERRATA_88_ENABLE_WORKAROUND NRF52_ERRATA_88_PRESENT +#endif + +static bool nrf52_errata_88(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 89 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_89_PRESENT 1 +#else + #define NRF52_ERRATA_89_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_89_ENABLE_WORKAROUND + #define NRF52_ERRATA_89_ENABLE_WORKAROUND NRF52_ERRATA_89_PRESENT +#endif + +static bool nrf52_errata_89(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 91 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_91_PRESENT 1 +#else + #define NRF52_ERRATA_91_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_91_ENABLE_WORKAROUND + #define NRF52_ERRATA_91_ENABLE_WORKAROUND NRF52_ERRATA_91_PRESENT +#endif + +static bool nrf52_errata_91(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 94 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_94_PRESENT 1 +#else + #define NRF52_ERRATA_94_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_94_ENABLE_WORKAROUND + #define NRF52_ERRATA_94_ENABLE_WORKAROUND NRF52_ERRATA_94_PRESENT +#endif + +static bool nrf52_errata_94(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 96 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_96_PRESENT 1 +#else + #define NRF52_ERRATA_96_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_96_ENABLE_WORKAROUND + #define NRF52_ERRATA_96_ENABLE_WORKAROUND NRF52_ERRATA_96_PRESENT +#endif + +static bool nrf52_errata_96(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 97 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_97_PRESENT 1 +#else + #define NRF52_ERRATA_97_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_97_ENABLE_WORKAROUND + #define NRF52_ERRATA_97_ENABLE_WORKAROUND NRF52_ERRATA_97_PRESENT +#endif + +static bool nrf52_errata_97(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 98 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_98_PRESENT 1 +#else + #define NRF52_ERRATA_98_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_98_ENABLE_WORKAROUND + #define NRF52_ERRATA_98_ENABLE_WORKAROUND NRF52_ERRATA_98_PRESENT +#endif + +static bool nrf52_errata_98(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 101 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_101_PRESENT 1 +#else + #define NRF52_ERRATA_101_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_101_ENABLE_WORKAROUND + #define NRF52_ERRATA_101_ENABLE_WORKAROUND NRF52_ERRATA_101_PRESENT +#endif + +static bool nrf52_errata_101(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 102 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_102_PRESENT 1 +#else + #define NRF52_ERRATA_102_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_102_ENABLE_WORKAROUND + #define NRF52_ERRATA_102_ENABLE_WORKAROUND NRF52_ERRATA_102_PRESENT +#endif + +static bool nrf52_errata_102(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 103 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_103_PRESENT 1 +#else + #define NRF52_ERRATA_103_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_103_ENABLE_WORKAROUND + #define NRF52_ERRATA_103_ENABLE_WORKAROUND NRF52_ERRATA_103_PRESENT +#endif + +static bool nrf52_errata_103(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 104 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_104_PRESENT 1 +#else + #define NRF52_ERRATA_104_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_104_ENABLE_WORKAROUND + #define NRF52_ERRATA_104_ENABLE_WORKAROUND NRF52_ERRATA_104_PRESENT +#endif + +static bool nrf52_errata_104(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 106 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_106_PRESENT 1 +#else + #define NRF52_ERRATA_106_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_106_ENABLE_WORKAROUND + #define NRF52_ERRATA_106_ENABLE_WORKAROUND NRF52_ERRATA_106_PRESENT +#endif + +static bool nrf52_errata_106(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 107 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_107_PRESENT 1 +#else + #define NRF52_ERRATA_107_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_107_ENABLE_WORKAROUND + #define NRF52_ERRATA_107_ENABLE_WORKAROUND NRF52_ERRATA_107_PRESENT +#endif + +static bool nrf52_errata_107(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 108 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_108_PRESENT 1 +#else + #define NRF52_ERRATA_108_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_108_ENABLE_WORKAROUND + #define NRF52_ERRATA_108_ENABLE_WORKAROUND NRF52_ERRATA_108_PRESENT +#endif + +static bool nrf52_errata_108(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 109 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_109_PRESENT 1 +#else + #define NRF52_ERRATA_109_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_109_ENABLE_WORKAROUND + #define NRF52_ERRATA_109_ENABLE_WORKAROUND NRF52_ERRATA_109_PRESENT +#endif + +static bool nrf52_errata_109(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 110 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_110_PRESENT 1 +#else + #define NRF52_ERRATA_110_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_110_ENABLE_WORKAROUND + #define NRF52_ERRATA_110_ENABLE_WORKAROUND NRF52_ERRATA_110_PRESENT +#endif + +static bool nrf52_errata_110(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 111 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_111_PRESENT 1 +#else + #define NRF52_ERRATA_111_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_111_ENABLE_WORKAROUND + #define NRF52_ERRATA_111_ENABLE_WORKAROUND NRF52_ERRATA_111_PRESENT +#endif + +static bool nrf52_errata_111(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 112 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_112_PRESENT 1 +#else + #define NRF52_ERRATA_112_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_112_ENABLE_WORKAROUND + #define NRF52_ERRATA_112_ENABLE_WORKAROUND NRF52_ERRATA_112_PRESENT +#endif + +static bool nrf52_errata_112(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 113 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_113_PRESENT 1 +#else + #define NRF52_ERRATA_113_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_113_ENABLE_WORKAROUND + #define NRF52_ERRATA_113_ENABLE_WORKAROUND NRF52_ERRATA_113_PRESENT +#endif + +static bool nrf52_errata_113(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 115 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_115_PRESENT 1 +#else + #define NRF52_ERRATA_115_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_115_ENABLE_WORKAROUND + #define NRF52_ERRATA_115_ENABLE_WORKAROUND NRF52_ERRATA_115_PRESENT +#endif + +static bool nrf52_errata_115(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 116 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_116_PRESENT 1 +#else + #define NRF52_ERRATA_116_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_116_ENABLE_WORKAROUND + #define NRF52_ERRATA_116_ENABLE_WORKAROUND NRF52_ERRATA_116_PRESENT +#endif + +static bool nrf52_errata_116(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 117 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_117_PRESENT 1 +#else + #define NRF52_ERRATA_117_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_117_ENABLE_WORKAROUND + #define NRF52_ERRATA_117_ENABLE_WORKAROUND NRF52_ERRATA_117_PRESENT +#endif + +static bool nrf52_errata_117(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 118 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_118_PRESENT 1 +#else + #define NRF52_ERRATA_118_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_118_ENABLE_WORKAROUND + #define NRF52_ERRATA_118_ENABLE_WORKAROUND NRF52_ERRATA_118_PRESENT +#endif + +static bool nrf52_errata_118(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 119 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_119_PRESENT 1 +#else + #define NRF52_ERRATA_119_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_119_ENABLE_WORKAROUND + #define NRF52_ERRATA_119_ENABLE_WORKAROUND NRF52_ERRATA_119_PRESENT +#endif + +static bool nrf52_errata_119(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 120 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_120_PRESENT 1 +#else + #define NRF52_ERRATA_120_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_120_ENABLE_WORKAROUND + #define NRF52_ERRATA_120_ENABLE_WORKAROUND NRF52_ERRATA_120_PRESENT +#endif + +static bool nrf52_errata_120(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 121 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_121_PRESENT 1 +#else + #define NRF52_ERRATA_121_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_121_ENABLE_WORKAROUND + #define NRF52_ERRATA_121_ENABLE_WORKAROUND NRF52_ERRATA_121_PRESENT +#endif + +static bool nrf52_errata_121(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 122 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_122_PRESENT 1 +#else + #define NRF52_ERRATA_122_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_122_ENABLE_WORKAROUND + #define NRF52_ERRATA_122_ENABLE_WORKAROUND NRF52_ERRATA_122_PRESENT +#endif + +static bool nrf52_errata_122(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 127 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_127_PRESENT 1 +#else + #define NRF52_ERRATA_127_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_127_ENABLE_WORKAROUND + #define NRF52_ERRATA_127_ENABLE_WORKAROUND NRF52_ERRATA_127_PRESENT +#endif + +static bool nrf52_errata_127(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 128 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_128_PRESENT 1 +#else + #define NRF52_ERRATA_128_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_128_ENABLE_WORKAROUND + #define NRF52_ERRATA_128_ENABLE_WORKAROUND NRF52_ERRATA_128_PRESENT +#endif + +static bool nrf52_errata_128(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 131 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_131_PRESENT 1 +#else + #define NRF52_ERRATA_131_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_131_ENABLE_WORKAROUND + #define NRF52_ERRATA_131_ENABLE_WORKAROUND NRF52_ERRATA_131_PRESENT +#endif + +static bool nrf52_errata_131(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 132 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_132_PRESENT 1 +#else + #define NRF52_ERRATA_132_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_132_ENABLE_WORKAROUND + #define NRF52_ERRATA_132_ENABLE_WORKAROUND NRF52_ERRATA_132_PRESENT +#endif + +static bool nrf52_errata_132(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 133 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_133_PRESENT 1 +#else + #define NRF52_ERRATA_133_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_133_ENABLE_WORKAROUND + #define NRF52_ERRATA_133_ENABLE_WORKAROUND NRF52_ERRATA_133_PRESENT +#endif + +static bool nrf52_errata_133(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 134 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_134_PRESENT 1 +#else + #define NRF52_ERRATA_134_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_134_ENABLE_WORKAROUND + #define NRF52_ERRATA_134_ENABLE_WORKAROUND NRF52_ERRATA_134_PRESENT +#endif + +static bool nrf52_errata_134(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 135 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_135_PRESENT 1 +#else + #define NRF52_ERRATA_135_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_135_ENABLE_WORKAROUND + #define NRF52_ERRATA_135_ENABLE_WORKAROUND NRF52_ERRATA_135_PRESENT +#endif + +static bool nrf52_errata_135(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 136 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_136_PRESENT 1 +#else + #define NRF52_ERRATA_136_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_136_ENABLE_WORKAROUND + #define NRF52_ERRATA_136_ENABLE_WORKAROUND NRF52_ERRATA_136_PRESENT +#endif + +static bool nrf52_errata_136(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 138 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_138_PRESENT 1 +#else + #define NRF52_ERRATA_138_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_138_ENABLE_WORKAROUND + #define NRF52_ERRATA_138_ENABLE_WORKAROUND NRF52_ERRATA_138_PRESENT +#endif + +static bool nrf52_errata_138(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 140 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_140_PRESENT 1 +#else + #define NRF52_ERRATA_140_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_140_ENABLE_WORKAROUND + #define NRF52_ERRATA_140_ENABLE_WORKAROUND NRF52_ERRATA_140_PRESENT +#endif + +static bool nrf52_errata_140(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 141 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_141_PRESENT 1 +#else + #define NRF52_ERRATA_141_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_141_ENABLE_WORKAROUND + #define NRF52_ERRATA_141_ENABLE_WORKAROUND NRF52_ERRATA_141_PRESENT +#endif + +static bool nrf52_errata_141(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 142 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_142_PRESENT 1 +#else + #define NRF52_ERRATA_142_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_142_ENABLE_WORKAROUND + #define NRF52_ERRATA_142_ENABLE_WORKAROUND NRF52_ERRATA_142_PRESENT +#endif + +static bool nrf52_errata_142(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 143 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_143_PRESENT 1 +#else + #define NRF52_ERRATA_143_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_143_ENABLE_WORKAROUND + #define NRF52_ERRATA_143_ENABLE_WORKAROUND NRF52_ERRATA_143_PRESENT +#endif + +static bool nrf52_errata_143(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 144 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_144_PRESENT 1 +#else + #define NRF52_ERRATA_144_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_144_ENABLE_WORKAROUND + #define NRF52_ERRATA_144_ENABLE_WORKAROUND NRF52_ERRATA_144_PRESENT +#endif + +static bool nrf52_errata_144(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 145 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_145_PRESENT 1 +#else + #define NRF52_ERRATA_145_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_145_ENABLE_WORKAROUND + #define NRF52_ERRATA_145_ENABLE_WORKAROUND NRF52_ERRATA_145_PRESENT +#endif + +static bool nrf52_errata_145(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 146 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_146_PRESENT 1 +#else + #define NRF52_ERRATA_146_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_146_ENABLE_WORKAROUND + #define NRF52_ERRATA_146_ENABLE_WORKAROUND NRF52_ERRATA_146_PRESENT +#endif + +static bool nrf52_errata_146(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 147 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_147_PRESENT 1 +#else + #define NRF52_ERRATA_147_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_147_ENABLE_WORKAROUND + #define NRF52_ERRATA_147_ENABLE_WORKAROUND NRF52_ERRATA_147_PRESENT +#endif + +static bool nrf52_errata_147(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 149 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_149_PRESENT 1 +#else + #define NRF52_ERRATA_149_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_149_ENABLE_WORKAROUND + #define NRF52_ERRATA_149_ENABLE_WORKAROUND NRF52_ERRATA_149_PRESENT +#endif + +static bool nrf52_errata_149(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 150 ========= */ +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_150_PRESENT 1 +#else + #define NRF52_ERRATA_150_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_150_ENABLE_WORKAROUND + #define NRF52_ERRATA_150_ENABLE_WORKAROUND NRF52_ERRATA_150_PRESENT +#endif + +static bool nrf52_errata_150(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 151 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_151_PRESENT 1 +#else + #define NRF52_ERRATA_151_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_151_ENABLE_WORKAROUND + #define NRF52_ERRATA_151_ENABLE_WORKAROUND NRF52_ERRATA_151_PRESENT +#endif + +static bool nrf52_errata_151(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 153 ========= */ +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_153_PRESENT 1 +#else + #define NRF52_ERRATA_153_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_153_ENABLE_WORKAROUND + #define NRF52_ERRATA_153_ENABLE_WORKAROUND NRF52_ERRATA_153_PRESENT +#endif + +static bool nrf52_errata_153(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 154 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_154_PRESENT 1 +#else + #define NRF52_ERRATA_154_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_154_ENABLE_WORKAROUND + #define NRF52_ERRATA_154_ENABLE_WORKAROUND NRF52_ERRATA_154_PRESENT +#endif + +static bool nrf52_errata_154(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 155 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_155_PRESENT 1 +#else + #define NRF52_ERRATA_155_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_155_ENABLE_WORKAROUND + #define NRF52_ERRATA_155_ENABLE_WORKAROUND NRF52_ERRATA_155_PRESENT +#endif + +static bool nrf52_errata_155(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 156 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_156_PRESENT 1 +#else + #define NRF52_ERRATA_156_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_156_ENABLE_WORKAROUND + #define NRF52_ERRATA_156_ENABLE_WORKAROUND NRF52_ERRATA_156_PRESENT +#endif + +static bool nrf52_errata_156(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 158 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_158_PRESENT 1 +#else + #define NRF52_ERRATA_158_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_158_ENABLE_WORKAROUND + #define NRF52_ERRATA_158_ENABLE_WORKAROUND NRF52_ERRATA_158_PRESENT +#endif + +static bool nrf52_errata_158(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 160 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_160_PRESENT 1 +#else + #define NRF52_ERRATA_160_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_160_ENABLE_WORKAROUND + #define NRF52_ERRATA_160_ENABLE_WORKAROUND NRF52_ERRATA_160_PRESENT +#endif + +static bool nrf52_errata_160(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 162 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_162_PRESENT 1 +#else + #define NRF52_ERRATA_162_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_162_ENABLE_WORKAROUND + #define NRF52_ERRATA_162_ENABLE_WORKAROUND NRF52_ERRATA_162_PRESENT +#endif + +static bool nrf52_errata_162(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 163 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_163_PRESENT 1 +#else + #define NRF52_ERRATA_163_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_163_ENABLE_WORKAROUND + #define NRF52_ERRATA_163_ENABLE_WORKAROUND NRF52_ERRATA_163_PRESENT +#endif + +static bool nrf52_errata_163(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 164 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_164_PRESENT 1 +#else + #define NRF52_ERRATA_164_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_164_ENABLE_WORKAROUND + #define NRF52_ERRATA_164_ENABLE_WORKAROUND NRF52_ERRATA_164_PRESENT +#endif + +static bool nrf52_errata_164(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 166 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_166_PRESENT 1 +#else + #define NRF52_ERRATA_166_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_166_ENABLE_WORKAROUND + #define NRF52_ERRATA_166_ENABLE_WORKAROUND NRF52_ERRATA_166_PRESENT +#endif + +static bool nrf52_errata_166(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 170 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_170_PRESENT 1 +#else + #define NRF52_ERRATA_170_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_170_ENABLE_WORKAROUND + #define NRF52_ERRATA_170_ENABLE_WORKAROUND NRF52_ERRATA_170_PRESENT +#endif + +static bool nrf52_errata_170(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 171 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_171_PRESENT 1 +#else + #define NRF52_ERRATA_171_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_171_ENABLE_WORKAROUND + #define NRF52_ERRATA_171_ENABLE_WORKAROUND NRF52_ERRATA_171_PRESENT +#endif + +static bool nrf52_errata_171(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 172 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_172_PRESENT 1 +#else + #define NRF52_ERRATA_172_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_172_ENABLE_WORKAROUND + #define NRF52_ERRATA_172_ENABLE_WORKAROUND NRF52_ERRATA_172_PRESENT +#endif + +static bool nrf52_errata_172(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 173 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_173_PRESENT 1 +#else + #define NRF52_ERRATA_173_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_173_ENABLE_WORKAROUND + #define NRF52_ERRATA_173_ENABLE_WORKAROUND NRF52_ERRATA_173_PRESENT +#endif + +static bool nrf52_errata_173(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 174 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_174_PRESENT 1 +#else + #define NRF52_ERRATA_174_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_174_ENABLE_WORKAROUND + #define NRF52_ERRATA_174_ENABLE_WORKAROUND NRF52_ERRATA_174_PRESENT +#endif + +static bool nrf52_errata_174(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 176 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_176_PRESENT 1 +#else + #define NRF52_ERRATA_176_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_176_ENABLE_WORKAROUND + #define NRF52_ERRATA_176_ENABLE_WORKAROUND NRF52_ERRATA_176_PRESENT +#endif + +static bool nrf52_errata_176(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 178 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_178_PRESENT 1 +#else + #define NRF52_ERRATA_178_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_178_ENABLE_WORKAROUND + #define NRF52_ERRATA_178_ENABLE_WORKAROUND NRF52_ERRATA_178_PRESENT +#endif + +static bool nrf52_errata_178(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 179 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_179_PRESENT 1 +#else + #define NRF52_ERRATA_179_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_179_ENABLE_WORKAROUND + #define NRF52_ERRATA_179_ENABLE_WORKAROUND NRF52_ERRATA_179_PRESENT +#endif + +static bool nrf52_errata_179(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 180 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_180_PRESENT 1 +#else + #define NRF52_ERRATA_180_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_180_ENABLE_WORKAROUND + #define NRF52_ERRATA_180_ENABLE_WORKAROUND NRF52_ERRATA_180_PRESENT +#endif + +static bool nrf52_errata_180(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 181 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_181_PRESENT 1 +#else + #define NRF52_ERRATA_181_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_181_ENABLE_WORKAROUND + #define NRF52_ERRATA_181_ENABLE_WORKAROUND NRF52_ERRATA_181_PRESENT +#endif + +static bool nrf52_errata_181(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return false; + case 0x07ul: + return false; + default: + return false; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 182 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_182_PRESENT 1 +#else + #define NRF52_ERRATA_182_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_182_ENABLE_WORKAROUND + #define NRF52_ERRATA_182_ENABLE_WORKAROUND NRF52_ERRATA_182_PRESENT +#endif + +static bool nrf52_errata_182(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 183 ========= */ +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_183_PRESENT 1 +#else + #define NRF52_ERRATA_183_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_183_ENABLE_WORKAROUND + #define NRF52_ERRATA_183_ENABLE_WORKAROUND NRF52_ERRATA_183_PRESENT +#endif + +static bool nrf52_errata_183(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 184 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_184_PRESENT 1 +#else + #define NRF52_ERRATA_184_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_184_ENABLE_WORKAROUND + #define NRF52_ERRATA_184_ENABLE_WORKAROUND NRF52_ERRATA_184_PRESENT +#endif + +static bool nrf52_errata_184(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 186 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_186_PRESENT 1 +#else + #define NRF52_ERRATA_186_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_186_ENABLE_WORKAROUND + #define NRF52_ERRATA_186_ENABLE_WORKAROUND NRF52_ERRATA_186_PRESENT +#endif + +static bool nrf52_errata_186(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 187 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_187_PRESENT 1 +#else + #define NRF52_ERRATA_187_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_187_ENABLE_WORKAROUND + #define NRF52_ERRATA_187_ENABLE_WORKAROUND NRF52_ERRATA_187_PRESENT +#endif + +static bool nrf52_errata_187(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 189 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_189_PRESENT 1 +#else + #define NRF52_ERRATA_189_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_189_ENABLE_WORKAROUND + #define NRF52_ERRATA_189_ENABLE_WORKAROUND NRF52_ERRATA_189_PRESENT +#endif + +static bool nrf52_errata_189(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 190 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_190_PRESENT 1 +#else + #define NRF52_ERRATA_190_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_190_ENABLE_WORKAROUND + #define NRF52_ERRATA_190_ENABLE_WORKAROUND NRF52_ERRATA_190_PRESENT +#endif + +static bool nrf52_errata_190(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 191 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_191_PRESENT 1 +#else + #define NRF52_ERRATA_191_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_191_ENABLE_WORKAROUND + #define NRF52_ERRATA_191_ENABLE_WORKAROUND NRF52_ERRATA_191_PRESENT +#endif + +static bool nrf52_errata_191(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 192 ========= */ +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_192_PRESENT 1 +#else + #define NRF52_ERRATA_192_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_192_ENABLE_WORKAROUND + #define NRF52_ERRATA_192_ENABLE_WORKAROUND NRF52_ERRATA_192_PRESENT +#endif + +static bool nrf52_errata_192(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 193 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_193_PRESENT 1 +#else + #define NRF52_ERRATA_193_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_193_ENABLE_WORKAROUND + #define NRF52_ERRATA_193_ENABLE_WORKAROUND NRF52_ERRATA_193_PRESENT +#endif + +static bool nrf52_errata_193(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 194 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_194_PRESENT 1 +#else + #define NRF52_ERRATA_194_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_194_ENABLE_WORKAROUND + #define NRF52_ERRATA_194_ENABLE_WORKAROUND NRF52_ERRATA_194_PRESENT +#endif + +static bool nrf52_errata_194(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 195 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_195_PRESENT 1 +#else + #define NRF52_ERRATA_195_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_195_ENABLE_WORKAROUND + #define NRF52_ERRATA_195_ENABLE_WORKAROUND NRF52_ERRATA_195_PRESENT +#endif + +static bool nrf52_errata_195(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 196 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_196_PRESENT 1 +#else + #define NRF52_ERRATA_196_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_196_ENABLE_WORKAROUND + #define NRF52_ERRATA_196_ENABLE_WORKAROUND NRF52_ERRATA_196_PRESENT +#endif + +static bool nrf52_errata_196(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 197 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_197_PRESENT 1 +#else + #define NRF52_ERRATA_197_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_197_ENABLE_WORKAROUND + #define NRF52_ERRATA_197_ENABLE_WORKAROUND NRF52_ERRATA_197_PRESENT +#endif + +static bool nrf52_errata_197(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 198 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_198_PRESENT 1 +#else + #define NRF52_ERRATA_198_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_198_ENABLE_WORKAROUND + #define NRF52_ERRATA_198_ENABLE_WORKAROUND NRF52_ERRATA_198_PRESENT +#endif + +static bool nrf52_errata_198(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 199 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_199_PRESENT 1 +#else + #define NRF52_ERRATA_199_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_199_ENABLE_WORKAROUND + #define NRF52_ERRATA_199_ENABLE_WORKAROUND NRF52_ERRATA_199_PRESENT +#endif + +static bool nrf52_errata_199(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 200 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_200_PRESENT 1 +#else + #define NRF52_ERRATA_200_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_200_ENABLE_WORKAROUND + #define NRF52_ERRATA_200_ENABLE_WORKAROUND NRF52_ERRATA_200_PRESENT +#endif + +static bool nrf52_errata_200(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 201 ========= */ +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_201_PRESENT 1 +#else + #define NRF52_ERRATA_201_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_201_ENABLE_WORKAROUND + #define NRF52_ERRATA_201_ENABLE_WORKAROUND NRF52_ERRATA_201_PRESENT +#endif + +static bool nrf52_errata_201(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 202 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_202_PRESENT 1 +#else + #define NRF52_ERRATA_202_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_202_ENABLE_WORKAROUND + #define NRF52_ERRATA_202_ENABLE_WORKAROUND NRF52_ERRATA_202_PRESENT +#endif + +static bool nrf52_errata_202(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 204 ========= */ +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_204_PRESENT 1 +#else + #define NRF52_ERRATA_204_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_204_ENABLE_WORKAROUND + #define NRF52_ERRATA_204_ENABLE_WORKAROUND NRF52_ERRATA_204_PRESENT +#endif + +static bool nrf52_errata_204(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 208 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_208_PRESENT 1 +#else + #define NRF52_ERRATA_208_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_208_ENABLE_WORKAROUND + #define NRF52_ERRATA_208_ENABLE_WORKAROUND NRF52_ERRATA_208_PRESENT +#endif + +static bool nrf52_errata_208(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 209 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_209_PRESENT 1 +#else + #define NRF52_ERRATA_209_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_209_ENABLE_WORKAROUND + #define NRF52_ERRATA_209_ENABLE_WORKAROUND NRF52_ERRATA_209_PRESENT +#endif + +static bool nrf52_errata_209(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 210 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_210_PRESENT 1 +#else + #define NRF52_ERRATA_210_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_210_ENABLE_WORKAROUND + #define NRF52_ERRATA_210_ENABLE_WORKAROUND NRF52_ERRATA_210_PRESENT +#endif + +static bool nrf52_errata_210(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 211 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_211_PRESENT 1 +#else + #define NRF52_ERRATA_211_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_211_ENABLE_WORKAROUND + #define NRF52_ERRATA_211_ENABLE_WORKAROUND 0 +#endif + +static bool nrf52_errata_211(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 212 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_212_PRESENT 1 +#else + #define NRF52_ERRATA_212_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_212_ENABLE_WORKAROUND + #define NRF52_ERRATA_212_ENABLE_WORKAROUND NRF52_ERRATA_212_PRESENT +#endif + +static bool nrf52_errata_212(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 213 ========= */ +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_213_PRESENT 1 +#else + #define NRF52_ERRATA_213_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_213_ENABLE_WORKAROUND + #define NRF52_ERRATA_213_ENABLE_WORKAROUND NRF52_ERRATA_213_PRESENT +#endif + +static bool nrf52_errata_213(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 214 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_214_PRESENT 1 +#else + #define NRF52_ERRATA_214_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_214_ENABLE_WORKAROUND + #define NRF52_ERRATA_214_ENABLE_WORKAROUND NRF52_ERRATA_214_PRESENT +#endif + +static bool nrf52_errata_214(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 215 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_215_PRESENT 1 +#else + #define NRF52_ERRATA_215_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_215_ENABLE_WORKAROUND + #define NRF52_ERRATA_215_ENABLE_WORKAROUND NRF52_ERRATA_215_PRESENT +#endif + +static bool nrf52_errata_215(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 216 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_216_PRESENT 1 +#else + #define NRF52_ERRATA_216_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_216_ENABLE_WORKAROUND + #define NRF52_ERRATA_216_ENABLE_WORKAROUND NRF52_ERRATA_216_PRESENT +#endif + +static bool nrf52_errata_216(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 217 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + #define NRF52_ERRATA_217_PRESENT 1 +#else + #define NRF52_ERRATA_217_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_217_ENABLE_WORKAROUND + #define NRF52_ERRATA_217_ENABLE_WORKAROUND NRF52_ERRATA_217_PRESENT +#endif + +static bool nrf52_errata_217(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 218 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_218_PRESENT 1 +#else + #define NRF52_ERRATA_218_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_218_ENABLE_WORKAROUND + #define NRF52_ERRATA_218_ENABLE_WORKAROUND NRF52_ERRATA_218_PRESENT +#endif + +static bool nrf52_errata_218(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 219 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_219_PRESENT 1 +#else + #define NRF52_ERRATA_219_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_219_ENABLE_WORKAROUND + #define NRF52_ERRATA_219_ENABLE_WORKAROUND NRF52_ERRATA_219_PRESENT +#endif + +static bool nrf52_errata_219(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 220 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_220_PRESENT 1 +#else + #define NRF52_ERRATA_220_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_220_ENABLE_WORKAROUND + #define NRF52_ERRATA_220_ENABLE_WORKAROUND NRF52_ERRATA_220_PRESENT +#endif + +static bool nrf52_errata_220(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 223 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #define NRF52_ERRATA_223_PRESENT 1 +#else + #define NRF52_ERRATA_223_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_223_ENABLE_WORKAROUND + #define NRF52_ERRATA_223_ENABLE_WORKAROUND NRF52_ERRATA_223_PRESENT +#endif + +static bool nrf52_errata_223(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 225 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #define NRF52_ERRATA_225_PRESENT 1 +#else + #define NRF52_ERRATA_225_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_225_ENABLE_WORKAROUND + #define NRF52_ERRATA_225_ENABLE_WORKAROUND NRF52_ERRATA_225_PRESENT +#endif + +static bool nrf52_errata_225(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 228 ========= */ +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_228_PRESENT 1 +#else + #define NRF52_ERRATA_228_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_228_ENABLE_WORKAROUND + #define NRF52_ERRATA_228_ENABLE_WORKAROUND NRF52_ERRATA_228_PRESENT +#endif + +static bool nrf52_errata_228(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 230 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + #define NRF52_ERRATA_230_PRESENT 1 +#else + #define NRF52_ERRATA_230_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_230_ENABLE_WORKAROUND + #define NRF52_ERRATA_230_ENABLE_WORKAROUND NRF52_ERRATA_230_PRESENT +#endif + +static bool nrf52_errata_230(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 231 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + #define NRF52_ERRATA_231_PRESENT 1 +#else + #define NRF52_ERRATA_231_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_231_ENABLE_WORKAROUND + #define NRF52_ERRATA_231_ENABLE_WORKAROUND NRF52_ERRATA_231_PRESENT +#endif + +static bool nrf52_errata_231(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 232 ========= */ +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + #define NRF52_ERRATA_232_PRESENT 1 +#else + #define NRF52_ERRATA_232_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_232_ENABLE_WORKAROUND + #define NRF52_ERRATA_232_ENABLE_WORKAROUND NRF52_ERRATA_232_PRESENT +#endif + +static bool nrf52_errata_232(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 233 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_233_PRESENT 1 +#else + #define NRF52_ERRATA_233_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_233_ENABLE_WORKAROUND + #define NRF52_ERRATA_233_ENABLE_WORKAROUND NRF52_ERRATA_233_PRESENT +#endif + +static bool nrf52_errata_233(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 236 ========= */ +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_236_PRESENT 1 +#else + #define NRF52_ERRATA_236_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_236_ENABLE_WORKAROUND + #define NRF52_ERRATA_236_ENABLE_WORKAROUND NRF52_ERRATA_236_PRESENT +#endif + +static bool nrf52_errata_236(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 237 ========= */ +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_237_PRESENT 1 +#else + #define NRF52_ERRATA_237_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_237_ENABLE_WORKAROUND + #define NRF52_ERRATA_237_ENABLE_WORKAROUND NRF52_ERRATA_237_PRESENT +#endif + +static bool nrf52_errata_237(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 242 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_242_PRESENT 1 +#else + #define NRF52_ERRATA_242_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_242_ENABLE_WORKAROUND + #define NRF52_ERRATA_242_ENABLE_WORKAROUND NRF52_ERRATA_242_PRESENT +#endif + +static bool nrf52_errata_242(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 243 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_243_PRESENT 1 +#else + #define NRF52_ERRATA_243_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_243_ENABLE_WORKAROUND + #define NRF52_ERRATA_243_ENABLE_WORKAROUND NRF52_ERRATA_243_PRESENT +#endif + +static bool nrf52_errata_243(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 244 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_244_PRESENT 1 +#else + #define NRF52_ERRATA_244_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_244_ENABLE_WORKAROUND + #define NRF52_ERRATA_244_ENABLE_WORKAROUND NRF52_ERRATA_244_PRESENT +#endif + +static bool nrf52_errata_244(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 245 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_245_PRESENT 1 +#else + #define NRF52_ERRATA_245_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_245_ENABLE_WORKAROUND + #define NRF52_ERRATA_245_ENABLE_WORKAROUND 0 +#endif + +static bool nrf52_errata_245(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 246 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_246_PRESENT 1 +#else + #define NRF52_ERRATA_246_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_246_ENABLE_WORKAROUND + #define NRF52_ERRATA_246_ENABLE_WORKAROUND NRF52_ERRATA_246_PRESENT +#endif + +static bool nrf52_errata_246(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 248 ========= */ +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_248_PRESENT 1 +#else + #define NRF52_ERRATA_248_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_248_ENABLE_WORKAROUND + #define NRF52_ERRATA_248_ENABLE_WORKAROUND NRF52_ERRATA_248_PRESENT +#endif + +static bool nrf52_errata_248(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 249 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_249_PRESENT 1 +#else + #define NRF52_ERRATA_249_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_249_ENABLE_WORKAROUND + #define NRF52_ERRATA_249_ENABLE_WORKAROUND NRF52_ERRATA_249_PRESENT +#endif + +static bool nrf52_errata_249(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 250 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #define NRF52_ERRATA_250_PRESENT 1 +#else + #define NRF52_ERRATA_250_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_250_ENABLE_WORKAROUND + #define NRF52_ERRATA_250_ENABLE_WORKAROUND NRF52_ERRATA_250_PRESENT +#endif + +static bool nrf52_errata_250(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 254 ========= */ +#define NRF52_ERRATA_254_PRESENT 0 + +#ifndef NRF52_ERRATA_254_ENABLE_WORKAROUND + #define NRF52_ERRATA_254_ENABLE_WORKAROUND NRF52_ERRATA_254_PRESENT +#endif + +static bool nrf52_errata_254(void) +{ + #ifndef NRF52_SERIES + return false; + #else + return false; + #endif +} + +#endif /* NRF52_ERRATAS_H */ diff --git a/bsp/boards/nrf52840_dk/sdk/nrf52_to_nrf52840.h b/bsp/boards/nrf52840_dk/sdk/nrf52_to_nrf52840.h new file mode 100644 index 0000000000..e3b0727c4a --- /dev/null +++ b/bsp/boards/nrf52840_dk/sdk/nrf52_to_nrf52840.h @@ -0,0 +1,161 @@ +/* + +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF52_TO_NRF52840_H +#define NRF52_TO_NRF52840_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the name changes between nRF51 or nRF52832 and nRF52840 devices. + * It redefines the old nRF51 or nRF52832 names into the new ones as long as the functionality is still supported. If the + * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros + * from the nrf52_namechange.h file. */ + +/* Differences between latest nRF52 headers and nRF52840 headers. */ + +/* UART */ +/* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */ +#ifndef PSELRTS + #define PSELRTS PSEL.RTS +#endif +#ifndef PSELTXD + #define PSELTXD PSEL.TXD +#endif +#ifndef PSELCTS + #define PSELCTS PSEL.CTS +#endif +#ifndef PSELRXD + #define PSELRXD PSEL.RXD +#endif + +/* TWI */ +/* The registers PSELSCL, PSELSDA were restructured into a struct. */ +#ifndef PSELSCL + #define PSELSCL PSEL.SCL +#endif +#ifndef PSELSDA + #define PSELSDA PSEL.SDA +#endif + + +/* LPCOMP */ +/* The hysteresis control enumerated values has changed name for nRF52840 devices. */ +#ifndef LPCOMP_HYST_HYST_NoHyst + #define LPCOMP_HYST_HYST_NoHyst LPCOMP_HYST_HYST_Disabled +#endif +#ifndef LPCOMP_HYST_HYST_Hyst50mV + #define LPCOMP_HYST_HYST_Hyst50mV LPCOMP_HYST_HYST_Enabled +#endif + + +/* From nrf52_name_change.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */ + +/* I2S */ +/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */ +#ifndef I2S_ENABLE_ENABLE_DISABLE + #define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled +#endif +#ifndef I2S_ENABLE_ENABLE_ENABLE + #define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled +#endif +#ifndef I2S_CONFIG_MODE_MODE_MASTER + #define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master +#endif +#ifndef I2S_CONFIG_MODE_MODE_SLAVE + #define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave +#endif +#ifndef I2S_CONFIG_RXEN_RXEN_DISABLE + #define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled +#endif +#ifndef I2S_CONFIG_RXEN_RXEN_ENABLE + #define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled +#endif +#ifndef I2S_CONFIG_TXEN_TXEN_DISABLE + #define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled +#endif +#ifndef I2S_CONFIG_TXEN_TXEN_ENABLE + #define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled +#endif +#ifndef I2S_CONFIG_MCKEN_MCKEN_DISABLE + #define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled +#endif +#ifndef I2S_CONFIG_MCKEN_MCKEN_ENABLE + #define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled +#endif +#ifndef I2S_CONFIG_SWIDTH_SWIDTH_8BIT + #define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit +#endif +#ifndef I2S_CONFIG_SWIDTH_SWIDTH_16BIT + #define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit +#endif +#ifndef I2S_CONFIG_SWIDTH_SWIDTH_24BIT + #define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit +#endif +#ifndef I2S_CONFIG_ALIGN_ALIGN_LEFT + #define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left +#endif +#ifndef I2S_CONFIG_ALIGN_ALIGN_RIGHT + #define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right +#endif +#ifndef I2S_CONFIG_FORMAT_FORMAT_ALIGNED + #define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned +#endif +#ifndef I2S_CONFIG_CHANNELS_CHANNELS_STEREO + #define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo +#endif +#ifndef I2S_CONFIG_CHANNELS_CHANNELS_LEFT + #define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left +#endif +#ifndef I2S_CONFIG_CHANNELS_CHANNELS_RIGHT + #define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right +#endif + +/* LPCOMP */ +/* Corrected typo in RESULT register. */ +#ifndef LPCOMP_RESULT_RESULT_Bellow + #define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below +#endif + + +/*lint --flb "Leave library region" */ + +#endif /* NRF51_TO_NRF52840_H */ + diff --git a/bsp/boards/nrf52840_dk/sdk/nrf53_erratas.h b/bsp/boards/nrf52840_dk/sdk/nrf53_erratas.h new file mode 100644 index 0000000000..6930a0bf78 --- /dev/null +++ b/bsp/boards/nrf52840_dk/sdk/nrf53_erratas.h @@ -0,0 +1,4825 @@ +#ifndef NRF53_ERRATAS_H +#define NRF53_ERRATAS_H + +/* + +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#include +#include +#include "compiler_abstraction.h" + +static bool nrf53_errata_1(void) __UNUSED; +static bool nrf53_errata_2(void) __UNUSED; +static bool nrf53_errata_3(void) __UNUSED; +static bool nrf53_errata_4(void) __UNUSED; +static bool nrf53_errata_5(void) __UNUSED; +static bool nrf53_errata_6(void) __UNUSED; +static bool nrf53_errata_7(void) __UNUSED; +static bool nrf53_errata_8(void) __UNUSED; +static bool nrf53_errata_9(void) __UNUSED; +static bool nrf53_errata_10(void) __UNUSED; +static bool nrf53_errata_11(void) __UNUSED; +static bool nrf53_errata_12(void) __UNUSED; +static bool nrf53_errata_13(void) __UNUSED; +static bool nrf53_errata_14(void) __UNUSED; +static bool nrf53_errata_15(void) __UNUSED; +static bool nrf53_errata_16(void) __UNUSED; +static bool nrf53_errata_18(void) __UNUSED; +static bool nrf53_errata_19(void) __UNUSED; +static bool nrf53_errata_20(void) __UNUSED; +static bool nrf53_errata_21(void) __UNUSED; +static bool nrf53_errata_22(void) __UNUSED; +static bool nrf53_errata_23(void) __UNUSED; +static bool nrf53_errata_26(void) __UNUSED; +static bool nrf53_errata_27(void) __UNUSED; +static bool nrf53_errata_28(void) __UNUSED; +static bool nrf53_errata_29(void) __UNUSED; +static bool nrf53_errata_30(void) __UNUSED; +static bool nrf53_errata_31(void) __UNUSED; +static bool nrf53_errata_32(void) __UNUSED; +static bool nrf53_errata_33(void) __UNUSED; +static bool nrf53_errata_34(void) __UNUSED; +static bool nrf53_errata_36(void) __UNUSED; +static bool nrf53_errata_37(void) __UNUSED; +static bool nrf53_errata_42(void) __UNUSED; +static bool nrf53_errata_43(void) __UNUSED; +static bool nrf53_errata_44(void) __UNUSED; +static bool nrf53_errata_45(void) __UNUSED; +static bool nrf53_errata_46(void) __UNUSED; +static bool nrf53_errata_47(void) __UNUSED; +static bool nrf53_errata_49(void) __UNUSED; +static bool nrf53_errata_50(void) __UNUSED; +static bool nrf53_errata_51(void) __UNUSED; +static bool nrf53_errata_52(void) __UNUSED; +static bool nrf53_errata_53(void) __UNUSED; +static bool nrf53_errata_54(void) __UNUSED; +static bool nrf53_errata_55(void) __UNUSED; +static bool nrf53_errata_57(void) __UNUSED; +static bool nrf53_errata_58(void) __UNUSED; +static bool nrf53_errata_59(void) __UNUSED; +static bool nrf53_errata_62(void) __UNUSED; +static bool nrf53_errata_64(void) __UNUSED; +static bool nrf53_errata_65(void) __UNUSED; +static bool nrf53_errata_66(void) __UNUSED; +static bool nrf53_errata_67(void) __UNUSED; +static bool nrf53_errata_69(void) __UNUSED; +static bool nrf53_errata_70(void) __UNUSED; +static bool nrf53_errata_71(void) __UNUSED; +static bool nrf53_errata_72(void) __UNUSED; +static bool nrf53_errata_73(void) __UNUSED; +static bool nrf53_errata_74(void) __UNUSED; +static bool nrf53_errata_75(void) __UNUSED; +static bool nrf53_errata_76(void) __UNUSED; +static bool nrf53_errata_77(void) __UNUSED; +static bool nrf53_errata_79(void) __UNUSED; +static bool nrf53_errata_80(void) __UNUSED; +static bool nrf53_errata_81(void) __UNUSED; +static bool nrf53_errata_82(void) __UNUSED; +static bool nrf53_errata_83(void) __UNUSED; +static bool nrf53_errata_84(void) __UNUSED; +static bool nrf53_errata_85(void) __UNUSED; +static bool nrf53_errata_86(void) __UNUSED; +static bool nrf53_errata_87(void) __UNUSED; +static bool nrf53_errata_90(void) __UNUSED; +static bool nrf53_errata_91(void) __UNUSED; +static bool nrf53_errata_93(void) __UNUSED; +static bool nrf53_errata_95(void) __UNUSED; +static bool nrf53_errata_97(void) __UNUSED; +static bool nrf53_errata_99(void) __UNUSED; +static bool nrf53_errata_103(void) __UNUSED; +static bool nrf53_errata_105(void) __UNUSED; +static bool nrf53_errata_106(void) __UNUSED; +static bool nrf53_errata_107(void) __UNUSED; +static bool nrf53_errata_109(void) __UNUSED; +static bool nrf53_errata_110(void) __UNUSED; +static bool nrf53_errata_112(void) __UNUSED; +static bool nrf53_errata_113(void) __UNUSED; +static bool nrf53_errata_114(void) __UNUSED; +static bool nrf53_errata_115(void) __UNUSED; +static bool nrf53_errata_116(void) __UNUSED; +static bool nrf53_errata_117(void) __UNUSED; +static bool nrf53_errata_119(void) __UNUSED; +static bool nrf53_errata_121(void) __UNUSED; +static bool nrf53_errata_122(void) __UNUSED; + +/* ========= Errata 1 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_1_PRESENT 1 + #else + #define NRF53_ERRATA_1_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_1_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_1_ENABLE_WORKAROUND + #define NRF53_ERRATA_1_ENABLE_WORKAROUND NRF53_ERRATA_1_PRESENT +#endif + +static bool nrf53_errata_1(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 2 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_2_PRESENT 1 + #else + #define NRF53_ERRATA_2_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_2_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_2_ENABLE_WORKAROUND + #define NRF53_ERRATA_2_ENABLE_WORKAROUND NRF53_ERRATA_2_PRESENT +#endif + +static bool nrf53_errata_2(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 3 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_3_PRESENT 1 + #else + #define NRF53_ERRATA_3_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_3_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_3_ENABLE_WORKAROUND + #define NRF53_ERRATA_3_ENABLE_WORKAROUND NRF53_ERRATA_3_PRESENT +#endif + +static bool nrf53_errata_3(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 4 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_4_PRESENT 1 + #else + #define NRF53_ERRATA_4_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_4_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_4_ENABLE_WORKAROUND + #define NRF53_ERRATA_4_ENABLE_WORKAROUND NRF53_ERRATA_4_PRESENT +#endif + +static bool nrf53_errata_4(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 5 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_5_PRESENT 1 + #else + #define NRF53_ERRATA_5_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_5_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_5_ENABLE_WORKAROUND + #define NRF53_ERRATA_5_ENABLE_WORKAROUND NRF53_ERRATA_5_PRESENT +#endif + +static bool nrf53_errata_5(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 6 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_6_PRESENT 1 + #else + #define NRF53_ERRATA_6_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_6_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_6_ENABLE_WORKAROUND + #define NRF53_ERRATA_6_ENABLE_WORKAROUND NRF53_ERRATA_6_PRESENT +#endif + +static bool nrf53_errata_6(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 7 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_7_PRESENT 1 + #else + #define NRF53_ERRATA_7_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_7_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_7_ENABLE_WORKAROUND + #define NRF53_ERRATA_7_ENABLE_WORKAROUND NRF53_ERRATA_7_PRESENT +#endif + +static bool nrf53_errata_7(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 8 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_8_PRESENT 1 + #else + #define NRF53_ERRATA_8_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_8_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_8_ENABLE_WORKAROUND + #define NRF53_ERRATA_8_ENABLE_WORKAROUND NRF53_ERRATA_8_PRESENT +#endif + +static bool nrf53_errata_8(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 9 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_9_PRESENT 1 + #else + #define NRF53_ERRATA_9_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_9_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_9_ENABLE_WORKAROUND + #define NRF53_ERRATA_9_ENABLE_WORKAROUND NRF53_ERRATA_9_PRESENT +#endif + +static bool nrf53_errata_9(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 10 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_10_PRESENT 1 + #else + #define NRF53_ERRATA_10_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_10_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_10_ENABLE_WORKAROUND + #define NRF53_ERRATA_10_ENABLE_WORKAROUND NRF53_ERRATA_10_PRESENT +#endif + +static bool nrf53_errata_10(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 11 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_11_PRESENT 1 + #else + #define NRF53_ERRATA_11_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_11_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_11_ENABLE_WORKAROUND + #define NRF53_ERRATA_11_ENABLE_WORKAROUND NRF53_ERRATA_11_PRESENT +#endif + +static bool nrf53_errata_11(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 12 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_12_PRESENT 1 + #else + #define NRF53_ERRATA_12_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_12_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_12_ENABLE_WORKAROUND + #define NRF53_ERRATA_12_ENABLE_WORKAROUND NRF53_ERRATA_12_PRESENT +#endif + +static bool nrf53_errata_12(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 13 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_13_PRESENT 1 + #else + #define NRF53_ERRATA_13_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_13_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_13_ENABLE_WORKAROUND + #define NRF53_ERRATA_13_ENABLE_WORKAROUND NRF53_ERRATA_13_PRESENT +#endif + +static bool nrf53_errata_13(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 14 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_14_PRESENT 1 + #else + #define NRF53_ERRATA_14_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_14_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_14_ENABLE_WORKAROUND + #define NRF53_ERRATA_14_ENABLE_WORKAROUND NRF53_ERRATA_14_PRESENT +#endif + +static bool nrf53_errata_14(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 15 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_15_PRESENT 1 + #else + #define NRF53_ERRATA_15_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_15_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_15_ENABLE_WORKAROUND + #define NRF53_ERRATA_15_ENABLE_WORKAROUND NRF53_ERRATA_15_PRESENT +#endif + +static bool nrf53_errata_15(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 16 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_16_PRESENT 1 + #else + #define NRF53_ERRATA_16_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_16_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_16_ENABLE_WORKAROUND + #define NRF53_ERRATA_16_ENABLE_WORKAROUND NRF53_ERRATA_16_PRESENT +#endif + +static bool nrf53_errata_16(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 18 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_18_PRESENT 1 + #else + #define NRF53_ERRATA_18_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_18_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_18_ENABLE_WORKAROUND + #define NRF53_ERRATA_18_ENABLE_WORKAROUND NRF53_ERRATA_18_PRESENT +#endif + +static bool nrf53_errata_18(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 19 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_19_PRESENT 1 + #else + #define NRF53_ERRATA_19_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_19_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_19_ENABLE_WORKAROUND + #define NRF53_ERRATA_19_ENABLE_WORKAROUND NRF53_ERRATA_19_PRESENT +#endif + +static bool nrf53_errata_19(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 20 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_20_PRESENT 1 + #else + #define NRF53_ERRATA_20_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_20_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_20_ENABLE_WORKAROUND + #define NRF53_ERRATA_20_ENABLE_WORKAROUND NRF53_ERRATA_20_PRESENT +#endif + +static bool nrf53_errata_20(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 21 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_21_PRESENT 1 + #else + #define NRF53_ERRATA_21_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_21_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_21_ENABLE_WORKAROUND + #define NRF53_ERRATA_21_ENABLE_WORKAROUND NRF53_ERRATA_21_PRESENT +#endif + +static bool nrf53_errata_21(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 22 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_22_PRESENT 1 + #else + #define NRF53_ERRATA_22_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_22_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_22_ENABLE_WORKAROUND + #define NRF53_ERRATA_22_ENABLE_WORKAROUND NRF53_ERRATA_22_PRESENT +#endif + +static bool nrf53_errata_22(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 23 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_23_PRESENT 1 + #else + #define NRF53_ERRATA_23_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_23_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_23_ENABLE_WORKAROUND + #define NRF53_ERRATA_23_ENABLE_WORKAROUND NRF53_ERRATA_23_PRESENT +#endif + +static bool nrf53_errata_23(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 26 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_26_PRESENT 1 + #else + #define NRF53_ERRATA_26_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_26_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_26_ENABLE_WORKAROUND + #define NRF53_ERRATA_26_ENABLE_WORKAROUND NRF53_ERRATA_26_PRESENT +#endif + +static bool nrf53_errata_26(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 27 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_27_PRESENT 1 + #else + #define NRF53_ERRATA_27_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_27_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_27_ENABLE_WORKAROUND + #define NRF53_ERRATA_27_ENABLE_WORKAROUND NRF53_ERRATA_27_PRESENT +#endif + +static bool nrf53_errata_27(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 28 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_28_PRESENT 1 + #else + #define NRF53_ERRATA_28_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_28_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_28_ENABLE_WORKAROUND + #define NRF53_ERRATA_28_ENABLE_WORKAROUND NRF53_ERRATA_28_PRESENT +#endif + +static bool nrf53_errata_28(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 29 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_29_PRESENT 1 + #else + #define NRF53_ERRATA_29_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_29_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_29_ENABLE_WORKAROUND + #define NRF53_ERRATA_29_ENABLE_WORKAROUND NRF53_ERRATA_29_PRESENT +#endif + +static bool nrf53_errata_29(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 30 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_30_PRESENT 1 + #else + #define NRF53_ERRATA_30_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_30_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_30_ENABLE_WORKAROUND + #define NRF53_ERRATA_30_ENABLE_WORKAROUND NRF53_ERRATA_30_PRESENT +#endif + +static bool nrf53_errata_30(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 31 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_31_PRESENT 1 + #else + #define NRF53_ERRATA_31_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_31_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_31_ENABLE_WORKAROUND + #define NRF53_ERRATA_31_ENABLE_WORKAROUND NRF53_ERRATA_31_PRESENT +#endif + +static bool nrf53_errata_31(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 32 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_32_PRESENT 1 + #else + #define NRF53_ERRATA_32_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_32_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_32_ENABLE_WORKAROUND + #define NRF53_ERRATA_32_ENABLE_WORKAROUND NRF53_ERRATA_32_PRESENT +#endif + +static bool nrf53_errata_32(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 33 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_33_PRESENT 1 + #else + #define NRF53_ERRATA_33_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_33_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_33_ENABLE_WORKAROUND + #define NRF53_ERRATA_33_ENABLE_WORKAROUND NRF53_ERRATA_33_PRESENT +#endif + +static bool nrf53_errata_33(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 34 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_34_PRESENT 1 + #else + #define NRF53_ERRATA_34_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_34_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_34_ENABLE_WORKAROUND + #define NRF53_ERRATA_34_ENABLE_WORKAROUND NRF53_ERRATA_34_PRESENT +#endif + +static bool nrf53_errata_34(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 36 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_36_PRESENT 1 + #else + #define NRF53_ERRATA_36_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_36_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_36_ENABLE_WORKAROUND + #define NRF53_ERRATA_36_ENABLE_WORKAROUND NRF53_ERRATA_36_PRESENT +#endif + +static bool nrf53_errata_36(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 37 ========= */ +#define NRF53_ERRATA_37_PRESENT 0 + +#ifndef NRF53_ERRATA_37_ENABLE_WORKAROUND + #define NRF53_ERRATA_37_ENABLE_WORKAROUND NRF53_ERRATA_37_PRESENT +#endif + +static bool nrf53_errata_37(void) +{ + #ifndef NRF53_SERIES + return false; + #else + return false; + #endif +} + +/* ========= Errata 42 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_42_PRESENT 1 + #else + #define NRF53_ERRATA_42_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_42_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_42_ENABLE_WORKAROUND + #define NRF53_ERRATA_42_ENABLE_WORKAROUND NRF53_ERRATA_42_PRESENT +#endif + +static bool nrf53_errata_42(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 43 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_43_PRESENT 1 + #else + #define NRF53_ERRATA_43_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_43_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_43_ENABLE_WORKAROUND + #define NRF53_ERRATA_43_ENABLE_WORKAROUND NRF53_ERRATA_43_PRESENT +#endif + +static bool nrf53_errata_43(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 44 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_44_PRESENT 1 + #else + #define NRF53_ERRATA_44_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_44_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_44_ENABLE_WORKAROUND + #define NRF53_ERRATA_44_ENABLE_WORKAROUND NRF53_ERRATA_44_PRESENT +#endif + +static bool nrf53_errata_44(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 45 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_45_PRESENT 1 + #else + #define NRF53_ERRATA_45_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_45_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_45_ENABLE_WORKAROUND + #define NRF53_ERRATA_45_ENABLE_WORKAROUND NRF53_ERRATA_45_PRESENT +#endif + +static bool nrf53_errata_45(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 46 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_46_PRESENT 1 + #else + #define NRF53_ERRATA_46_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_46_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_46_ENABLE_WORKAROUND + #define NRF53_ERRATA_46_ENABLE_WORKAROUND NRF53_ERRATA_46_PRESENT +#endif + +static bool nrf53_errata_46(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 47 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_47_PRESENT 1 + #else + #define NRF53_ERRATA_47_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_47_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_47_ENABLE_WORKAROUND + #define NRF53_ERRATA_47_ENABLE_WORKAROUND NRF53_ERRATA_47_PRESENT +#endif + +static bool nrf53_errata_47(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 49 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_49_PRESENT 1 + #else + #define NRF53_ERRATA_49_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_49_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_49_ENABLE_WORKAROUND + #define NRF53_ERRATA_49_ENABLE_WORKAROUND NRF53_ERRATA_49_PRESENT +#endif + +static bool nrf53_errata_49(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 50 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_50_PRESENT 1 + #else + #define NRF53_ERRATA_50_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_50_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_50_ENABLE_WORKAROUND + #define NRF53_ERRATA_50_ENABLE_WORKAROUND NRF53_ERRATA_50_PRESENT +#endif + +static bool nrf53_errata_50(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 51 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_51_PRESENT 1 + #else + #define NRF53_ERRATA_51_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_51_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_51_ENABLE_WORKAROUND + #define NRF53_ERRATA_51_ENABLE_WORKAROUND NRF53_ERRATA_51_PRESENT +#endif + +static bool nrf53_errata_51(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 52 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_52_PRESENT 1 + #else + #define NRF53_ERRATA_52_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_52_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_52_ENABLE_WORKAROUND + #define NRF53_ERRATA_52_ENABLE_WORKAROUND NRF53_ERRATA_52_PRESENT +#endif + +static bool nrf53_errata_52(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 53 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_53_PRESENT 1 + #else + #define NRF53_ERRATA_53_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_53_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_53_ENABLE_WORKAROUND + #define NRF53_ERRATA_53_ENABLE_WORKAROUND NRF53_ERRATA_53_PRESENT +#endif + +static bool nrf53_errata_53(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 54 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_54_PRESENT 1 + #else + #define NRF53_ERRATA_54_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_54_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_54_ENABLE_WORKAROUND + #define NRF53_ERRATA_54_ENABLE_WORKAROUND NRF53_ERRATA_54_PRESENT +#endif + +static bool nrf53_errata_54(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 55 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_55_PRESENT 1 + #else + #define NRF53_ERRATA_55_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_55_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_55_ENABLE_WORKAROUND + #define NRF53_ERRATA_55_ENABLE_WORKAROUND NRF53_ERRATA_55_PRESENT +#endif + +static bool nrf53_errata_55(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 57 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_57_PRESENT 1 + #else + #define NRF53_ERRATA_57_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_57_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_57_ENABLE_WORKAROUND + #define NRF53_ERRATA_57_ENABLE_WORKAROUND NRF53_ERRATA_57_PRESENT +#endif + +static bool nrf53_errata_57(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 58 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_58_PRESENT 1 + #else + #define NRF53_ERRATA_58_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_58_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_58_ENABLE_WORKAROUND + #define NRF53_ERRATA_58_ENABLE_WORKAROUND NRF53_ERRATA_58_PRESENT +#endif + +static bool nrf53_errata_58(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 59 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_59_PRESENT 1 + #else + #define NRF53_ERRATA_59_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_59_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_59_ENABLE_WORKAROUND + #define NRF53_ERRATA_59_ENABLE_WORKAROUND NRF53_ERRATA_59_PRESENT +#endif + +static bool nrf53_errata_59(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 62 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_62_PRESENT 1 + #else + #define NRF53_ERRATA_62_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_62_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_62_ENABLE_WORKAROUND + #define NRF53_ERRATA_62_ENABLE_WORKAROUND NRF53_ERRATA_62_PRESENT +#endif + +static bool nrf53_errata_62(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 64 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_64_PRESENT 1 + #else + #define NRF53_ERRATA_64_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_64_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_64_ENABLE_WORKAROUND + #define NRF53_ERRATA_64_ENABLE_WORKAROUND NRF53_ERRATA_64_PRESENT +#endif + +static bool nrf53_errata_64(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 65 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_65_PRESENT 1 + #else + #define NRF53_ERRATA_65_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_65_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_65_ENABLE_WORKAROUND + #define NRF53_ERRATA_65_ENABLE_WORKAROUND NRF53_ERRATA_65_PRESENT +#endif + +static bool nrf53_errata_65(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 66 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_66_PRESENT 1 + #else + #define NRF53_ERRATA_66_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_66_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_66_ENABLE_WORKAROUND + #define NRF53_ERRATA_66_ENABLE_WORKAROUND NRF53_ERRATA_66_PRESENT +#endif + +static bool nrf53_errata_66(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 67 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_67_PRESENT 1 + #else + #define NRF53_ERRATA_67_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_67_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_67_ENABLE_WORKAROUND + #define NRF53_ERRATA_67_ENABLE_WORKAROUND NRF53_ERRATA_67_PRESENT +#endif + +static bool nrf53_errata_67(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 69 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_69_PRESENT 1 + #else + #define NRF53_ERRATA_69_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_69_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_69_ENABLE_WORKAROUND + #define NRF53_ERRATA_69_ENABLE_WORKAROUND NRF53_ERRATA_69_PRESENT +#endif + +static bool nrf53_errata_69(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 70 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_70_PRESENT 1 + #else + #define NRF53_ERRATA_70_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_70_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_70_ENABLE_WORKAROUND + #define NRF53_ERRATA_70_ENABLE_WORKAROUND NRF53_ERRATA_70_PRESENT +#endif + +static bool nrf53_errata_70(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 71 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_71_PRESENT 1 + #else + #define NRF53_ERRATA_71_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_71_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_71_ENABLE_WORKAROUND + #define NRF53_ERRATA_71_ENABLE_WORKAROUND NRF53_ERRATA_71_PRESENT +#endif + +static bool nrf53_errata_71(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 72 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_72_PRESENT 1 + #else + #define NRF53_ERRATA_72_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_72_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_72_ENABLE_WORKAROUND + #define NRF53_ERRATA_72_ENABLE_WORKAROUND NRF53_ERRATA_72_PRESENT +#endif + +static bool nrf53_errata_72(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 73 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_73_PRESENT 1 + #else + #define NRF53_ERRATA_73_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_73_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_73_ENABLE_WORKAROUND + #define NRF53_ERRATA_73_ENABLE_WORKAROUND NRF53_ERRATA_73_PRESENT +#endif + +static bool nrf53_errata_73(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 74 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_74_PRESENT 1 + #else + #define NRF53_ERRATA_74_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_74_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_74_ENABLE_WORKAROUND + #define NRF53_ERRATA_74_ENABLE_WORKAROUND NRF53_ERRATA_74_PRESENT +#endif + +static bool nrf53_errata_74(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 75 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_75_PRESENT 1 + #else + #define NRF53_ERRATA_75_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_75_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_75_ENABLE_WORKAROUND + #define NRF53_ERRATA_75_ENABLE_WORKAROUND NRF53_ERRATA_75_PRESENT +#endif + +static bool nrf53_errata_75(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 76 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_76_PRESENT 1 + #else + #define NRF53_ERRATA_76_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_76_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_76_ENABLE_WORKAROUND + #define NRF53_ERRATA_76_ENABLE_WORKAROUND NRF53_ERRATA_76_PRESENT +#endif + +static bool nrf53_errata_76(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 77 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_77_PRESENT 1 + #else + #define NRF53_ERRATA_77_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_77_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_77_ENABLE_WORKAROUND + #define NRF53_ERRATA_77_ENABLE_WORKAROUND NRF53_ERRATA_77_PRESENT +#endif + +static bool nrf53_errata_77(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 79 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_79_PRESENT 1 + #else + #define NRF53_ERRATA_79_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_79_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_79_ENABLE_WORKAROUND + #define NRF53_ERRATA_79_ENABLE_WORKAROUND NRF53_ERRATA_79_PRESENT +#endif + +static bool nrf53_errata_79(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 80 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_80_PRESENT 1 + #else + #define NRF53_ERRATA_80_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_80_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_80_ENABLE_WORKAROUND + #define NRF53_ERRATA_80_ENABLE_WORKAROUND NRF53_ERRATA_80_PRESENT +#endif + +static bool nrf53_errata_80(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 81 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_81_PRESENT 1 + #else + #define NRF53_ERRATA_81_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_81_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_81_ENABLE_WORKAROUND + #define NRF53_ERRATA_81_ENABLE_WORKAROUND NRF53_ERRATA_81_PRESENT +#endif + +static bool nrf53_errata_81(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 82 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_82_PRESENT 1 + #else + #define NRF53_ERRATA_82_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_82_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_82_ENABLE_WORKAROUND + #define NRF53_ERRATA_82_ENABLE_WORKAROUND NRF53_ERRATA_82_PRESENT +#endif + +static bool nrf53_errata_82(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 83 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_83_PRESENT 1 + #else + #define NRF53_ERRATA_83_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_83_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_83_ENABLE_WORKAROUND + #define NRF53_ERRATA_83_ENABLE_WORKAROUND NRF53_ERRATA_83_PRESENT +#endif + +static bool nrf53_errata_83(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 84 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_84_PRESENT 1 + #else + #define NRF53_ERRATA_84_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_84_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_84_ENABLE_WORKAROUND + #define NRF53_ERRATA_84_ENABLE_WORKAROUND NRF53_ERRATA_84_PRESENT +#endif + +static bool nrf53_errata_84(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 85 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_85_PRESENT 1 + #else + #define NRF53_ERRATA_85_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_85_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_85_ENABLE_WORKAROUND + #define NRF53_ERRATA_85_ENABLE_WORKAROUND NRF53_ERRATA_85_PRESENT +#endif + +static bool nrf53_errata_85(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 86 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_86_PRESENT 1 + #else + #define NRF53_ERRATA_86_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_86_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_86_ENABLE_WORKAROUND + #define NRF53_ERRATA_86_ENABLE_WORKAROUND NRF53_ERRATA_86_PRESENT +#endif + +static bool nrf53_errata_86(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 87 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_87_PRESENT 1 + #else + #define NRF53_ERRATA_87_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_87_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_87_ENABLE_WORKAROUND + #define NRF53_ERRATA_87_ENABLE_WORKAROUND NRF53_ERRATA_87_PRESENT +#endif + +static bool nrf53_errata_87(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 90 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_90_PRESENT 1 + #else + #define NRF53_ERRATA_90_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_90_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_90_ENABLE_WORKAROUND + #define NRF53_ERRATA_90_ENABLE_WORKAROUND NRF53_ERRATA_90_PRESENT +#endif + +static bool nrf53_errata_90(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 91 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_91_PRESENT 1 + #else + #define NRF53_ERRATA_91_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_91_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_91_ENABLE_WORKAROUND + #define NRF53_ERRATA_91_ENABLE_WORKAROUND NRF53_ERRATA_91_PRESENT +#endif + +static bool nrf53_errata_91(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 93 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_93_PRESENT 1 + #else + #define NRF53_ERRATA_93_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_93_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_93_ENABLE_WORKAROUND + #define NRF53_ERRATA_93_ENABLE_WORKAROUND NRF53_ERRATA_93_PRESENT +#endif + +static bool nrf53_errata_93(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 95 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_95_PRESENT 1 + #else + #define NRF53_ERRATA_95_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_95_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_95_ENABLE_WORKAROUND + #define NRF53_ERRATA_95_ENABLE_WORKAROUND NRF53_ERRATA_95_PRESENT +#endif + +static bool nrf53_errata_95(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 97 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_97_PRESENT 1 + #else + #define NRF53_ERRATA_97_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_97_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_97_ENABLE_WORKAROUND + #define NRF53_ERRATA_97_ENABLE_WORKAROUND NRF53_ERRATA_97_PRESENT +#endif + +static bool nrf53_errata_97(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 99 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_99_PRESENT 1 + #else + #define NRF53_ERRATA_99_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_99_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_99_ENABLE_WORKAROUND + #define NRF53_ERRATA_99_ENABLE_WORKAROUND NRF53_ERRATA_99_PRESENT +#endif + +static bool nrf53_errata_99(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 103 ========= */ +#define NRF53_ERRATA_103_PRESENT 0 + +#ifndef NRF53_ERRATA_103_ENABLE_WORKAROUND + #define NRF53_ERRATA_103_ENABLE_WORKAROUND NRF53_ERRATA_103_PRESENT +#endif + +static bool nrf53_errata_103(void) +{ + #ifndef NRF53_SERIES + return false; + #else + return false; + #endif +} + +/* ========= Errata 105 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_105_PRESENT 1 + #else + #define NRF53_ERRATA_105_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_105_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_105_ENABLE_WORKAROUND + #define NRF53_ERRATA_105_ENABLE_WORKAROUND NRF53_ERRATA_105_PRESENT +#endif + +static bool nrf53_errata_105(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 106 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_106_PRESENT 1 + #else + #define NRF53_ERRATA_106_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_106_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_106_ENABLE_WORKAROUND + #define NRF53_ERRATA_106_ENABLE_WORKAROUND NRF53_ERRATA_106_PRESENT +#endif + +static bool nrf53_errata_106(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 107 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_107_PRESENT 1 + #else + #define NRF53_ERRATA_107_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_107_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_107_ENABLE_WORKAROUND + #define NRF53_ERRATA_107_ENABLE_WORKAROUND NRF53_ERRATA_107_PRESENT +#endif + +static bool nrf53_errata_107(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 109 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_109_PRESENT 1 + #else + #define NRF53_ERRATA_109_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_109_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_109_ENABLE_WORKAROUND + #define NRF53_ERRATA_109_ENABLE_WORKAROUND NRF53_ERRATA_109_PRESENT +#endif + +static bool nrf53_errata_109(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 110 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_110_PRESENT 1 + #else + #define NRF53_ERRATA_110_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_110_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_110_ENABLE_WORKAROUND + #define NRF53_ERRATA_110_ENABLE_WORKAROUND NRF53_ERRATA_110_PRESENT +#endif + +static bool nrf53_errata_110(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 112 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_112_PRESENT 1 + #else + #define NRF53_ERRATA_112_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_112_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_112_ENABLE_WORKAROUND + #define NRF53_ERRATA_112_ENABLE_WORKAROUND NRF53_ERRATA_112_PRESENT +#endif + +static bool nrf53_errata_112(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 113 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_113_PRESENT 1 + #else + #define NRF53_ERRATA_113_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_113_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_113_ENABLE_WORKAROUND + #define NRF53_ERRATA_113_ENABLE_WORKAROUND NRF53_ERRATA_113_PRESENT +#endif + +static bool nrf53_errata_113(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 114 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_114_PRESENT 1 + #else + #define NRF53_ERRATA_114_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_114_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_114_ENABLE_WORKAROUND + #define NRF53_ERRATA_114_ENABLE_WORKAROUND NRF53_ERRATA_114_PRESENT +#endif + +static bool nrf53_errata_114(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 115 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_115_PRESENT 1 + #else + #define NRF53_ERRATA_115_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_115_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_115_ENABLE_WORKAROUND + #define NRF53_ERRATA_115_ENABLE_WORKAROUND NRF53_ERRATA_115_PRESENT +#endif + +static bool nrf53_errata_115(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 116 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_116_PRESENT 1 + #else + #define NRF53_ERRATA_116_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_116_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_116_ENABLE_WORKAROUND + #define NRF53_ERRATA_116_ENABLE_WORKAROUND NRF53_ERRATA_116_PRESENT +#endif + +static bool nrf53_errata_116(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 117 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_117_PRESENT 1 + #else + #define NRF53_ERRATA_117_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_117_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_117_ENABLE_WORKAROUND + #define NRF53_ERRATA_117_ENABLE_WORKAROUND NRF53_ERRATA_117_PRESENT +#endif + +static bool nrf53_errata_117(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 119 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_119_PRESENT 1 + #else + #define NRF53_ERRATA_119_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_119_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_119_ENABLE_WORKAROUND + #define NRF53_ERRATA_119_ENABLE_WORKAROUND NRF53_ERRATA_119_PRESENT +#endif + +static bool nrf53_errata_119(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 121 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_121_PRESENT 1 + #else + #define NRF53_ERRATA_121_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_121_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_121_ENABLE_WORKAROUND + #define NRF53_ERRATA_121_ENABLE_WORKAROUND NRF53_ERRATA_121_PRESENT +#endif + +static bool nrf53_errata_121(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 122 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_122_PRESENT 1 + #else + #define NRF53_ERRATA_122_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_122_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_122_ENABLE_WORKAROUND + #define NRF53_ERRATA_122_ENABLE_WORKAROUND NRF53_ERRATA_122_PRESENT +#endif + +static bool nrf53_errata_122(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +#endif /* NRF53_ERRATAS_H */ diff --git a/bsp/boards/nrf52840_dk/sdk/nrf91_erratas.h b/bsp/boards/nrf52840_dk/sdk/nrf91_erratas.h new file mode 100644 index 0000000000..7d318e23d4 --- /dev/null +++ b/bsp/boards/nrf52840_dk/sdk/nrf91_erratas.h @@ -0,0 +1,1025 @@ +#ifndef NRF91_ERRATAS_H +#define NRF91_ERRATAS_H + +/* + +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#include +#include +#include "compiler_abstraction.h" + +static bool nrf91_errata_1(void) __UNUSED; +static bool nrf91_errata_2(void) __UNUSED; +static bool nrf91_errata_4(void) __UNUSED; +static bool nrf91_errata_6(void) __UNUSED; +static bool nrf91_errata_7(void) __UNUSED; +static bool nrf91_errata_8(void) __UNUSED; +static bool nrf91_errata_9(void) __UNUSED; +static bool nrf91_errata_10(void) __UNUSED; +static bool nrf91_errata_12(void) __UNUSED; +static bool nrf91_errata_14(void) __UNUSED; +static bool nrf91_errata_15(void) __UNUSED; +static bool nrf91_errata_16(void) __UNUSED; +static bool nrf91_errata_17(void) __UNUSED; +static bool nrf91_errata_20(void) __UNUSED; +static bool nrf91_errata_21(void) __UNUSED; +static bool nrf91_errata_23(void) __UNUSED; +static bool nrf91_errata_24(void) __UNUSED; +static bool nrf91_errata_26(void) __UNUSED; +static bool nrf91_errata_27(void) __UNUSED; +static bool nrf91_errata_28(void) __UNUSED; +static bool nrf91_errata_29(void) __UNUSED; +static bool nrf91_errata_30(void) __UNUSED; +static bool nrf91_errata_31(void) __UNUSED; +static bool nrf91_errata_32(void) __UNUSED; +static bool nrf91_errata_33(void) __UNUSED; + +/* ========= Errata 1 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_1_PRESENT 1 +#else + #define NRF91_ERRATA_1_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_1_ENABLE_WORKAROUND + #define NRF91_ERRATA_1_ENABLE_WORKAROUND NRF91_ERRATA_1_PRESENT +#endif + +static bool nrf91_errata_1(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 2 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_2_PRESENT 1 +#else + #define NRF91_ERRATA_2_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_2_ENABLE_WORKAROUND + #define NRF91_ERRATA_2_ENABLE_WORKAROUND NRF91_ERRATA_2_PRESENT +#endif + +static bool nrf91_errata_2(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 4 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_4_PRESENT 1 +#else + #define NRF91_ERRATA_4_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_4_ENABLE_WORKAROUND + #define NRF91_ERRATA_4_ENABLE_WORKAROUND NRF91_ERRATA_4_PRESENT +#endif + +static bool nrf91_errata_4(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 6 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_6_PRESENT 1 +#else + #define NRF91_ERRATA_6_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_6_ENABLE_WORKAROUND + #define NRF91_ERRATA_6_ENABLE_WORKAROUND NRF91_ERRATA_6_PRESENT +#endif + +static bool nrf91_errata_6(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 7 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_7_PRESENT 1 +#else + #define NRF91_ERRATA_7_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_7_ENABLE_WORKAROUND + #define NRF91_ERRATA_7_ENABLE_WORKAROUND NRF91_ERRATA_7_PRESENT +#endif + +static bool nrf91_errata_7(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 8 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_8_PRESENT 1 +#else + #define NRF91_ERRATA_8_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_8_ENABLE_WORKAROUND + #define NRF91_ERRATA_8_ENABLE_WORKAROUND NRF91_ERRATA_8_PRESENT +#endif + +static bool nrf91_errata_8(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 9 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_9_PRESENT 1 +#else + #define NRF91_ERRATA_9_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_9_ENABLE_WORKAROUND + #define NRF91_ERRATA_9_ENABLE_WORKAROUND NRF91_ERRATA_9_PRESENT +#endif + +static bool nrf91_errata_9(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return false; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 10 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_10_PRESENT 1 +#else + #define NRF91_ERRATA_10_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_10_ENABLE_WORKAROUND + #define NRF91_ERRATA_10_ENABLE_WORKAROUND NRF91_ERRATA_10_PRESENT +#endif + +static bool nrf91_errata_10(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 12 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_12_PRESENT 1 +#else + #define NRF91_ERRATA_12_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_12_ENABLE_WORKAROUND + #define NRF91_ERRATA_12_ENABLE_WORKAROUND NRF91_ERRATA_12_PRESENT +#endif + +static bool nrf91_errata_12(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 14 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_14_PRESENT 1 +#else + #define NRF91_ERRATA_14_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_14_ENABLE_WORKAROUND + #define NRF91_ERRATA_14_ENABLE_WORKAROUND NRF91_ERRATA_14_PRESENT +#endif + +static bool nrf91_errata_14(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 15 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_15_PRESENT 1 +#else + #define NRF91_ERRATA_15_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_15_ENABLE_WORKAROUND + #define NRF91_ERRATA_15_ENABLE_WORKAROUND NRF91_ERRATA_15_PRESENT +#endif + +static bool nrf91_errata_15(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return false; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 16 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_16_PRESENT 1 +#else + #define NRF91_ERRATA_16_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_16_ENABLE_WORKAROUND + #define NRF91_ERRATA_16_ENABLE_WORKAROUND NRF91_ERRATA_16_PRESENT +#endif + +static bool nrf91_errata_16(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 17 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_17_PRESENT 1 +#else + #define NRF91_ERRATA_17_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_17_ENABLE_WORKAROUND + #define NRF91_ERRATA_17_ENABLE_WORKAROUND NRF91_ERRATA_17_PRESENT +#endif + +static bool nrf91_errata_17(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 20 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_20_PRESENT 1 +#else + #define NRF91_ERRATA_20_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_20_ENABLE_WORKAROUND + #define NRF91_ERRATA_20_ENABLE_WORKAROUND NRF91_ERRATA_20_PRESENT +#endif + +static bool nrf91_errata_20(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 21 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_21_PRESENT 1 +#else + #define NRF91_ERRATA_21_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_21_ENABLE_WORKAROUND + #define NRF91_ERRATA_21_ENABLE_WORKAROUND NRF91_ERRATA_21_PRESENT +#endif + +static bool nrf91_errata_21(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 23 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_23_PRESENT 1 +#else + #define NRF91_ERRATA_23_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_23_ENABLE_WORKAROUND + #define NRF91_ERRATA_23_ENABLE_WORKAROUND NRF91_ERRATA_23_PRESENT +#endif + +static bool nrf91_errata_23(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 24 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_24_PRESENT 1 +#else + #define NRF91_ERRATA_24_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_24_ENABLE_WORKAROUND + #define NRF91_ERRATA_24_ENABLE_WORKAROUND NRF91_ERRATA_24_PRESENT +#endif + +static bool nrf91_errata_24(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 26 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_26_PRESENT 1 +#else + #define NRF91_ERRATA_26_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_26_ENABLE_WORKAROUND + #define NRF91_ERRATA_26_ENABLE_WORKAROUND NRF91_ERRATA_26_PRESENT +#endif + +static bool nrf91_errata_26(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 27 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_27_PRESENT 1 +#else + #define NRF91_ERRATA_27_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_27_ENABLE_WORKAROUND + #define NRF91_ERRATA_27_ENABLE_WORKAROUND NRF91_ERRATA_27_PRESENT +#endif + +static bool nrf91_errata_27(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return false; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 28 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_28_PRESENT 1 +#else + #define NRF91_ERRATA_28_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_28_ENABLE_WORKAROUND + #define NRF91_ERRATA_28_ENABLE_WORKAROUND NRF91_ERRATA_28_PRESENT +#endif + +static bool nrf91_errata_28(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 29 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_29_PRESENT 1 +#else + #define NRF91_ERRATA_29_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_29_ENABLE_WORKAROUND + #define NRF91_ERRATA_29_ENABLE_WORKAROUND NRF91_ERRATA_29_PRESENT +#endif + +static bool nrf91_errata_29(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 30 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_30_PRESENT 1 +#else + #define NRF91_ERRATA_30_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_30_ENABLE_WORKAROUND + #define NRF91_ERRATA_30_ENABLE_WORKAROUND NRF91_ERRATA_30_PRESENT +#endif + +static bool nrf91_errata_30(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 31 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_31_PRESENT 1 +#else + #define NRF91_ERRATA_31_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_31_ENABLE_WORKAROUND + #define NRF91_ERRATA_31_ENABLE_WORKAROUND NRF91_ERRATA_31_PRESENT +#endif + +static bool nrf91_errata_31(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 32 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_32_PRESENT 1 +#else + #define NRF91_ERRATA_32_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_32_ENABLE_WORKAROUND + #define NRF91_ERRATA_32_ENABLE_WORKAROUND NRF91_ERRATA_32_PRESENT +#endif + +static bool nrf91_errata_32(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 33 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_33_PRESENT 1 +#else + #define NRF91_ERRATA_33_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_33_ENABLE_WORKAROUND + #define NRF91_ERRATA_33_ENABLE_WORKAROUND NRF91_ERRATA_33_PRESENT +#endif + +static bool nrf91_errata_33(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +#endif /* NRF91_ERRATAS_H */ diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf_peripherals.h b/bsp/boards/nrf52840_dk/sdk/nrf_erratas.h similarity index 68% rename from bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf_peripherals.h rename to bsp/boards/nrf52840_dk/sdk/nrf_erratas.h index 86e3d92fb5..2b2da3be2f 100644 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/nrf_peripherals.h +++ b/bsp/boards/nrf52840_dk/sdk/nrf_erratas.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. @@ -39,34 +39,21 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef NRF_PERIPHERALS_H__ -#define NRF_PERIPHERALS_H__ +#ifndef NRF_ERRATAS_H +#define NRF_ERRATAS_H + +#include "nrf.h" + +/* Check MDK version to make sure we have the required macros */ +NRF_MDK_VERSION_ASSERT_AT_LEAST(8,34,0); /*lint ++flb "Enter library region */ -#if defined(_WIN32) - /* Do not include nrf specific files when building for PC host */ -#elif defined(__unix) - /* Do not include nrf specific files when building for PC host */ -#elif defined(__APPLE__) - /* Do not include nrf specific files when building for PC host */ -#else - - #if defined(NRF51) - #include "nrf51_peripherals.h" - - #elif defined(NRF52810_XXAA) - #include "nrf52810_peripherals.h" - #elif defined(NRF52832_XXAA) || defined(NRF52832_XXAB) - #include "nrf52832_peripherals.h" - #elif defined(NRF52840_XXAA) - #include "nrf52840_peripherals.h" - - #else - #error "Device must be defined. See nrf.h." - #endif -#endif +#include "nrf51_erratas.h" +#include "nrf52_erratas.h" +#include "nrf53_erratas.h" +#include "nrf91_erratas.h" /*lint --flb "Leave library region" */ -#endif // NRF_PERIPHERALS_H__ +#endif // NRF_ERRATAS_H diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/startup_config.h b/bsp/boards/nrf52840_dk/sdk/nrf_peripherals.h similarity index 58% rename from bsp/boards/nrf52840/sdk/modules/nrfx/mdk/startup_config.h rename to bsp/boards/nrf52840_dk/sdk/nrf_peripherals.h index ca51149c5e..4ad9278c59 100644 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/startup_config.h +++ b/bsp/boards/nrf52840_dk/sdk/nrf_peripherals.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. @@ -39,22 +39,41 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* Configure stack size, stack alignement and heap size with a header file instead of project settings or modification of Nordic provided assembler files. Modify this file as needed. */ +#ifndef NRF_PERIPHERALS_H__ +#define NRF_PERIPHERALS_H__ -/* In order to make use this file, - 1. For Keil uVision IDE, in the Options for Target -> Asm tab, define symbol __STARTUP_CONFIG and use the additional assembler option --cpreproc in Misc Control text box. - 2. For GCC compiling, add extra assembly option -D__STARTUP_CONFIG. - 3. For IAR Embedded Workbench define symbol __STARTUP_CONFIG in the Assembler options and define symbol __STARTUP_CONFIG=1 in the linker options. -*/ +/*lint ++flb "Enter library region */ + +#if defined(NRF51) + #include "nrf51_peripherals.h" + +#elif defined (NRF52805_XXAA) + #include "nrf52805_peripherals.h" +#elif defined(NRF52810_XXAA) + #include "nrf52810_peripherals.h" +#elif defined(NRF52811_XXAA) + #include "nrf52811_peripherals.h" +#elif defined(NRF52820_XXAA) + #include "nrf52820_peripherals.h" +#elif defined(NRF52832_XXAA) || defined(NRF52832_XXAB) + #include "nrf52832_peripherals.h" +#elif defined (NRF52833_XXAA) + #include "nrf52833_peripherals.h" +#elif defined(NRF52840_XXAA) + #include "nrf52840_peripherals.h" -/* This file is a template and should be copied to the project directory. */ +#elif defined (NRF5340_XXAA_APPLICATION) + #include "nrf5340_application_peripherals.h" +#elif defined (NRF5340_XXAA_NETWORK) + #include "nrf5340_network_peripherals.h" -/* Define size of stack. Size must be multiple of 4. */ -#define __STARTUP_CONFIG_STACK_SIZE 0x1000 +#elif defined(NRF9160_XXAA) + #include "nrf9160_peripherals.h" -/* Define alignement of stack. Alignment will be 2 to the power of __STARTUP_CONFIG_STACK_ALIGNEMENT. Since calling convention requires that the stack is aligned to 8-bytes when a function is called, the minimum __STARTUP_CONFIG_STACK_ALIGNEMENT is therefore 3. */ -#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 +#else + #error "Device must be defined. See nrf.h." +#endif -/* Define size of heap. Size must be multiple of 4. */ -#define __STARTUP_CONFIG_HEAP_SIZE 0x1000 +/*lint --flb "Leave library region" */ +#endif // NRF_PERIPHERALS_H__ diff --git a/bsp/boards/nrf52840_dk/sdk/ses_startup_nrf52840.s b/bsp/boards/nrf52840_dk/sdk/ses_startup_nrf52840.s new file mode 100644 index 0000000000..0e26bd5265 --- /dev/null +++ b/bsp/boards/nrf52840_dk/sdk/ses_startup_nrf52840.s @@ -0,0 +1,409 @@ +/*********************************************************************************** + * SEGGER Microcontroller GmbH * + * The Embedded Experts * + *********************************************************************************** + * * + * (c) 2014 - 2018 SEGGER Microcontroller GmbH * + * * + * www.segger.com Support: support@segger.com * + * * + *********************************************************************************** + * * + * All rights reserved. * + * * + * Redistribution and use in source and binary forms, with or * + * without modification, are permitted provided that the following * + * conditions are met: * + * * + * - Redistributions of source code must retain the above copyright * + * notice, this list of conditions and the following disclaimer. * + * * + * - Neither the name of SEGGER Microcontroller GmbH * + * nor the names of its contributors may be used to endorse or * + * promote products derived from this software without specific * + * prior written permission. * + * * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * + * DISCLAIMED. * + * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * + * DAMAGE. * + * * + ***********************************************************************************/ + +/************************************************************************************ + * Preprocessor Definitions * + * ------------------------ * + * VECTORS_IN_RAM * + * * + * If defined, an area of RAM will large enough to store the vector table * + * will be reserved. * + * * + ************************************************************************************/ + + .syntax unified + .code 16 + + .section .init, "ax" + .align 0 + +/************************************************************************************ + * Default Exception Handlers * + ************************************************************************************/ + + + .thumb_func + .weak NMI_Handler +NMI_Handler: + b . + + .thumb_func + .weak HardFault_Handler +HardFault_Handler: + b . + + .thumb_func + .weak MemoryManagement_Handler +MemoryManagement_Handler: + b . + + .thumb_func + .weak BusFault_Handler +BusFault_Handler: + b . + + .thumb_func + .weak UsageFault_Handler +UsageFault_Handler: + b . + + .thumb_func + .weak SVC_Handler +SVC_Handler: + b . + + .thumb_func + .weak DebugMon_Handler +DebugMon_Handler: + b . + + .thumb_func + .weak PendSV_Handler +PendSV_Handler: + b . + + .thumb_func + .weak SysTick_Handler +SysTick_Handler: + b . + + .thumb_func + .weak Dummy_Handler +Dummy_Handler: + b . + +/************************************************************************************ + * Default Interrupt Handlers * + ************************************************************************************/ + +.weak POWER_CLOCK_IRQHandler +.thumb_set POWER_CLOCK_IRQHandler, Dummy_Handler + +.weak RADIO_IRQHandler +.thumb_set RADIO_IRQHandler, Dummy_Handler + +.weak UARTE0_UART0_IRQHandler +.thumb_set UARTE0_UART0_IRQHandler, Dummy_Handler + +.weak SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +.thumb_set SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler, Dummy_Handler + +.weak SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +.thumb_set SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler, Dummy_Handler + +.weak NFCT_IRQHandler +.thumb_set NFCT_IRQHandler, Dummy_Handler + +.weak GPIOTE_IRQHandler +.thumb_set GPIOTE_IRQHandler, Dummy_Handler + +.weak SAADC_IRQHandler +.thumb_set SAADC_IRQHandler, Dummy_Handler + +.weak TIMER0_IRQHandler +.thumb_set TIMER0_IRQHandler, Dummy_Handler + +.weak TIMER1_IRQHandler +.thumb_set TIMER1_IRQHandler, Dummy_Handler + +.weak TIMER2_IRQHandler +.thumb_set TIMER2_IRQHandler, Dummy_Handler + +.weak RTC0_IRQHandler +.thumb_set RTC0_IRQHandler, Dummy_Handler + +.weak TEMP_IRQHandler +.thumb_set TEMP_IRQHandler, Dummy_Handler + +.weak RNG_IRQHandler +.thumb_set RNG_IRQHandler, Dummy_Handler + +.weak ECB_IRQHandler +.thumb_set ECB_IRQHandler, Dummy_Handler + +.weak CCM_AAR_IRQHandler +.thumb_set CCM_AAR_IRQHandler, Dummy_Handler + +.weak WDT_IRQHandler +.thumb_set WDT_IRQHandler, Dummy_Handler + +.weak RTC1_IRQHandler +.thumb_set RTC1_IRQHandler, Dummy_Handler + +.weak QDEC_IRQHandler +.thumb_set QDEC_IRQHandler, Dummy_Handler + +.weak COMP_LPCOMP_IRQHandler +.thumb_set COMP_LPCOMP_IRQHandler, Dummy_Handler + +.weak SWI0_EGU0_IRQHandler +.thumb_set SWI0_EGU0_IRQHandler, Dummy_Handler + +.weak SWI1_EGU1_IRQHandler +.thumb_set SWI1_EGU1_IRQHandler, Dummy_Handler + +.weak SWI2_EGU2_IRQHandler +.thumb_set SWI2_EGU2_IRQHandler, Dummy_Handler + +.weak SWI3_EGU3_IRQHandler +.thumb_set SWI3_EGU3_IRQHandler, Dummy_Handler + +.weak SWI4_EGU4_IRQHandler +.thumb_set SWI4_EGU4_IRQHandler, Dummy_Handler + +.weak SWI5_EGU5_IRQHandler +.thumb_set SWI5_EGU5_IRQHandler, Dummy_Handler + +.weak TIMER3_IRQHandler +.thumb_set TIMER3_IRQHandler, Dummy_Handler + +.weak TIMER4_IRQHandler +.thumb_set TIMER4_IRQHandler, Dummy_Handler + +.weak PWM0_IRQHandler +.thumb_set PWM0_IRQHandler, Dummy_Handler + +.weak PDM_IRQHandler +.thumb_set PDM_IRQHandler, Dummy_Handler + +.weak MWU_IRQHandler +.thumb_set MWU_IRQHandler, Dummy_Handler + +.weak PWM1_IRQHandler +.thumb_set PWM1_IRQHandler, Dummy_Handler + +.weak PWM2_IRQHandler +.thumb_set PWM2_IRQHandler, Dummy_Handler + +.weak SPIM2_SPIS2_SPI2_IRQHandler +.thumb_set SPIM2_SPIS2_SPI2_IRQHandler, Dummy_Handler + +.weak RTC2_IRQHandler +.thumb_set RTC2_IRQHandler, Dummy_Handler + +.weak I2S_IRQHandler +.thumb_set I2S_IRQHandler, Dummy_Handler + +.weak FPU_IRQHandler +.thumb_set FPU_IRQHandler, Dummy_Handler + +.weak USBD_IRQHandler +.thumb_set USBD_IRQHandler, Dummy_Handler + +.weak UARTE1_IRQHandler +.thumb_set UARTE1_IRQHandler, Dummy_Handler + +.weak QSPI_IRQHandler +.thumb_set QSPI_IRQHandler, Dummy_Handler + +.weak CRYPTOCELL_IRQHandler +.thumb_set CRYPTOCELL_IRQHandler, Dummy_Handler + +.weak PWM3_IRQHandler +.thumb_set PWM3_IRQHandler, Dummy_Handler + +.weak SPIM3_IRQHandler +.thumb_set SPIM3_IRQHandler, Dummy_Handler + +/************************************************************************************ + * Reset Handler Extensions * + ************************************************************************************/ + + .extern Reset_Handler + .global nRFInitialize + .extern afterInitialize + + .thumb_func +nRFInitialize: + b afterInitialize + + +/************************************************************************************ + * Vector Table * + ************************************************************************************/ + + .section .vectors, "ax" + .align 0 + .global _vectors + .extern __stack_end__ + +_vectors: + .word __stack_end__ + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemoryManagement_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word SVC_Handler + .word DebugMon_Handler + .word 0 /*Reserved */ + .word PendSV_Handler + .word SysTick_Handler + +/* External Interrupts */ + .word POWER_CLOCK_IRQHandler + .word RADIO_IRQHandler + .word UARTE0_UART0_IRQHandler + .word SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler + .word SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler + .word NFCT_IRQHandler + .word GPIOTE_IRQHandler + .word SAADC_IRQHandler + .word TIMER0_IRQHandler + .word TIMER1_IRQHandler + .word TIMER2_IRQHandler + .word RTC0_IRQHandler + .word TEMP_IRQHandler + .word RNG_IRQHandler + .word ECB_IRQHandler + .word CCM_AAR_IRQHandler + .word WDT_IRQHandler + .word RTC1_IRQHandler + .word QDEC_IRQHandler + .word COMP_LPCOMP_IRQHandler + .word SWI0_EGU0_IRQHandler + .word SWI1_EGU1_IRQHandler + .word SWI2_EGU2_IRQHandler + .word SWI3_EGU3_IRQHandler + .word SWI4_EGU4_IRQHandler + .word SWI5_EGU5_IRQHandler + .word TIMER3_IRQHandler + .word TIMER4_IRQHandler + .word PWM0_IRQHandler + .word PDM_IRQHandler + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word MWU_IRQHandler + .word PWM1_IRQHandler + .word PWM2_IRQHandler + .word SPIM2_SPIS2_SPI2_IRQHandler + .word RTC2_IRQHandler + .word I2S_IRQHandler + .word FPU_IRQHandler + .word USBD_IRQHandler + .word UARTE1_IRQHandler + .word QSPI_IRQHandler + .word CRYPTOCELL_IRQHandler + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word PWM3_IRQHandler + .word 0 /*Reserved */ + .word SPIM3_IRQHandler + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ +_vectors_end: + +#ifdef VECTORS_IN_RAM + .section .vectors_ram, "ax" + .align 0 + .global _vectors_ram + +_vectors_ram: + .space _vectors_end - _vectors, 0 +#endif diff --git a/bsp/boards/nrf52840_dk/sdk/ses_startup_nrf_common.s b/bsp/boards/nrf52840_dk/sdk/ses_startup_nrf_common.s new file mode 100644 index 0000000000..2f0854e42e --- /dev/null +++ b/bsp/boards/nrf52840_dk/sdk/ses_startup_nrf_common.s @@ -0,0 +1,193 @@ +/*********************************************************************************** + * SEGGER Microcontroller GmbH * + * The Embedded Experts * + *********************************************************************************** + * * + * (c) 2014 - 2018 SEGGER Microcontroller GmbH * + * * + * www.segger.com Support: support@segger.com * + * * + *********************************************************************************** + * * + * All rights reserved. * + * * + * Redistribution and use in source and binary forms, with or * + * without modification, are permitted provided that the following * + * conditions are met: * + * * + * - Redistributions of source code must retain the above copyright * + * notice, this list of conditions and the following disclaimer. * + * * + * - Neither the name of SEGGER Microcontroller GmbH * + * nor the names of its contributors may be used to endorse or * + * promote products derived from this software without specific * + * prior written permission. * + * * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * + * DISCLAIMED. * + * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * + * DAMAGE. * + * * + *********************************************************************************** + * * + * This file has been modified by Nordic Semiconductor: * + * To separate out device-specific data * + * * + ***********************************************************************************/ + +/************************************************************************************ + * Preprocessor Definitions * + * ------------------------ * + * NO_FPU_ENABLE * + * * + * If defined, FPU will not be enabled. * + * * + * NO_STACK_INIT * + * * + * If defined, the stack pointer will not be initialised. * + * * + * NO_SYSTEM_INIT * + * * + * If defined, the SystemInit() function will not be called. By default * + * SystemInit() is called after reset to enable the clocks and memories to * + * be initialised prior to any C startup initialisation. * + * * + * NO_VTOR_CONFIG * + * * + * If defined, the vector table offset register will not be configured. * + * * + * MEMORY_INIT * + * * + * If defined, the MemoryInit() function will be called. By default * + * MemoryInit() is called after SystemInit() to enable an external memory * + * controller. * + * * + * STACK_INIT_VAL * + * * + * If defined, specifies the initial stack pointer value. If undefined, * + * the stack pointer will be initialised to point to the end of the * + * RAM segment. * + * * + * VECTORS_IN_RAM * + * * + * If defined, the exception vectors will be copied from Flash to RAM. * + * * + ************************************************************************************/ + + .syntax unified + + .global Reset_Handler +#ifdef INITIALIZE_USER_SECTIONS + .global InitializeUserMemorySections +#endif + .extern _vectors + .extern nRFInitialize + .global afterInitialize + + .section .init, "ax" + .thumb_func + + .equ VTOR_REG, 0xE000ED08 + .equ FPU_CPACR_REG, 0xE000ED88 + +#ifndef STACK_INIT_VAL +#define STACK_INIT_VAL __RAM1_segment_end__ +#endif + +Reset_Handler: + + /* Perform prestart tasks. */ + b nRFInitialize + +.thumb_func +afterInitialize: + +#ifndef NO_STACK_INIT + /* Initialise main stack */ + ldr r0, =STACK_INIT_VAL + ldr r1, =0x7 + bics r0, r1 + mov sp, r0 +#endif + +#ifndef NO_SYSTEM_INIT + /* Initialise system */ + ldr r0, =SystemInit + blx r0 +#endif + +#ifdef MEMORY_INIT + ldr r0, =MemoryInit + blx r0 +#endif + +#ifdef VECTORS_IN_RAM + /* Copy exception vectors into RAM */ + ldr r0, =__vectors_start__ + ldr r1, =__vectors_end__ + ldr r2, =__vectors_ram_start__ +1: + cmp r0, r1 + beq 2f + ldr r3, [r0] + str r3, [r2] + adds r0, r0, #4 + adds r2, r2, #4 + b 1b +2: +#endif + +#ifndef NO_VTOR_CONFIG + /* Configure vector table offset register */ + ldr r0, =VTOR_REG +#ifdef VECTORS_IN_RAM + ldr r1, =_vectors_ram +#else + ldr r1, =_vectors +#endif + str r1, [r0] +#endif + +#if (defined(__ARM_ARCH_FPV4_SP_D16__) || defined(__ARM_ARCH_FPV5_D16__)) && !defined(NO_FPU_ENABLE) + /* Enable FPU */ + ldr r0, =FPU_CPACR_REG + ldr r1, [r0] + orr r1, r1, #(0xF << 20) + str r1, [r0] + dsb + isb +#endif + + /* Jump to program start */ + b _start + +#ifdef INITIALIZE_USER_SECTIONS + .thumb_func +InitializeUserMemorySections: + ldr r0, =__start_nrf_sections + ldr r1, =__start_nrf_sections_run + ldr r2, =__end_nrf_sections_run + cmp r0, r1 + beq 2f + subs r2, r2, r1 + beq 2f +1: + ldrb r3, [r0] + adds r0, r0, #1 + strb r3, [r1] + adds r1, r1, #1 + subs r2, r2, #1 + bne 1b +2: + bx lr +#endif \ No newline at end of file diff --git a/bsp/boards/nrf52840_dk/sdk/system_nrf52.c b/bsp/boards/nrf52840_dk/sdk/system_nrf52.c new file mode 100644 index 0000000000..718654aed6 --- /dev/null +++ b/bsp/boards/nrf52840_dk/sdk/system_nrf52.c @@ -0,0 +1,317 @@ +/* + +Copyright (c) 2009-2021 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + +/* NOTE: Template files (including this one) are application specific and therefore expected to + be copied into the application project folder prior to its use! */ + +#include +#include +#include "nrf.h" +#include "nrf_peripherals.h" +#include "nrf_erratas.h" +#include "system_nrf52.h" +#include "system_nrf52_approtect.h" + +#define __SYSTEM_CLOCK_64M (64000000UL) + + +#if defined ( __CC_ARM ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; +#elif defined ( __ICCARM__ ) + __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M; +#elif defined ( __GNUC__ ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; +#endif + +/* Select correct reset pin */ +/* Handle DEVELOP_IN-targets first as they take precedence over the later macros */ +#if defined (DEVELOP_IN_NRF52805) \ + || defined (DEVELOP_IN_NRF52810) \ + || defined (DEVELOP_IN_NRF52811) \ + || defined (DEVELOP_IN_NRF52832) + #define RESET_PIN 21 +#elif defined (DEVELOP_IN_NRF52820) \ + || defined (DEVELOP_IN_NRF52833) \ + || defined (DEVELOP_IN_NRF52840) + #define RESET_PIN 18 +#elif defined (NRF52805_XXAA) \ + || defined (NRF52810_XXAA) \ + || defined (NRF52811_XXAA) \ + || defined (NRF52832_XXAA) \ + || defined (NRF52832_XXAB) + #define RESET_PIN 21 +#elif defined (NRF52820_XXAA) \ + || defined (NRF52833_XXAA) \ + || defined (NRF52840_XXAA) + #define RESET_PIN 18 +#else + #error "A supported device macro must be defined." +#endif + +/* -- NVMC utility functions -- */ +/* Waits until NVMC is done with the current pending action */ +void nvmc_wait(void) +{ + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} +} + +/* Configure the NVMC to "mode". + Mode must be an enumerator of field NVMC_CONFIG_WEN */ +void nvmc_config(uint32_t mode) +{ + NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos; + nvmc_wait(); +} + +void SystemCoreClockUpdate(void) +{ + SystemCoreClock = __SYSTEM_CLOCK_64M; +} + +void SystemInit(void) +{ + /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product + Specification to see which one). */ + #if defined (ENABLE_SWO) && defined(CLOCK_TRACECONFIG_TRACEMUX_Pos) + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos; + NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + #endif + + /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product + Specification to see which ones). */ + #if defined (ENABLE_TRACE) && defined(CLOCK_TRACECONFIG_TRACEMUX_Pos) + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos; + NRF_P0->PIN_CNF[14] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P0->PIN_CNF[15] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P0->PIN_CNF[16] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + #endif + + #if NRF52_ERRATA_12_ENABLE_WORKAROUND + /* Workaround for Errata 12 "COMP: Reference ladder not correctly calibrated" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_12()){ + *(volatile uint32_t *)0x40013540 = (*(uint32_t *)0x10000324 & 0x00001F00) >> 8; + } + #endif + + #if NRF52_ERRATA_16_ENABLE_WORKAROUND + /* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_16()){ + *(volatile uint32_t *)0x4007C074 = 3131961357ul; + } + #endif + + #if NRF52_ERRATA_31_ENABLE_WORKAROUND + /* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_31()){ + *(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13; + } + #endif + + #if NRF52_ERRATA_32_ENABLE_WORKAROUND + /* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_32()){ + CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; + } + #endif + + #if NRF52_ERRATA_36_ENABLE_WORKAROUND + /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_36()){ + NRF_CLOCK->EVENTS_DONE = 0; + NRF_CLOCK->EVENTS_CTTO = 0; + NRF_CLOCK->CTIV = 0; + } + #endif + + #if NRF52_ERRATA_37_ENABLE_WORKAROUND + /* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_37()){ + *(volatile uint32_t *)0x400005A0 = 0x3; + } + #endif + + #if NRF52_ERRATA_57_ENABLE_WORKAROUND + /* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_57()){ + *(volatile uint32_t *)0x40005610 = 0x00000005; + *(volatile uint32_t *)0x40005688 = 0x00000001; + *(volatile uint32_t *)0x40005618 = 0x00000000; + *(volatile uint32_t *)0x40005614 = 0x0000003F; + } + #endif + + #if NRF52_ERRATA_66_ENABLE_WORKAROUND + /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_66()){ + NRF_TEMP->A0 = NRF_FICR->TEMP.A0; + NRF_TEMP->A1 = NRF_FICR->TEMP.A1; + NRF_TEMP->A2 = NRF_FICR->TEMP.A2; + NRF_TEMP->A3 = NRF_FICR->TEMP.A3; + NRF_TEMP->A4 = NRF_FICR->TEMP.A4; + NRF_TEMP->A5 = NRF_FICR->TEMP.A5; + NRF_TEMP->B0 = NRF_FICR->TEMP.B0; + NRF_TEMP->B1 = NRF_FICR->TEMP.B1; + NRF_TEMP->B2 = NRF_FICR->TEMP.B2; + NRF_TEMP->B3 = NRF_FICR->TEMP.B3; + NRF_TEMP->B4 = NRF_FICR->TEMP.B4; + NRF_TEMP->B5 = NRF_FICR->TEMP.B5; + NRF_TEMP->T0 = NRF_FICR->TEMP.T0; + NRF_TEMP->T1 = NRF_FICR->TEMP.T1; + NRF_TEMP->T2 = NRF_FICR->TEMP.T2; + NRF_TEMP->T3 = NRF_FICR->TEMP.T3; + NRF_TEMP->T4 = NRF_FICR->TEMP.T4; + } + #endif + + #if NRF52_ERRATA_98_ENABLE_WORKAROUND + /* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_98()){ + *(volatile uint32_t *)0x4000568Cul = 0x00038148ul; + } + #endif + + #if NRF52_ERRATA_103_ENABLE_WORKAROUND && defined(CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) + /* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_103()){ + NRF_CCM->MAXPACKETSIZE = 0xFBul; + } + #endif + + #if NRF52_ERRATA_108_ENABLE_WORKAROUND + /* Workaround for Errata 108 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_108()){ + *(volatile uint32_t *)0x40000EE4ul = *(volatile uint32_t *)0x10000258ul & 0x0000004Ful; + } + #endif + + #if NRF52_ERRATA_115_ENABLE_WORKAROUND + /* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_115()){ + *(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F); + } + #endif + + #if NRF52_ERRATA_120_ENABLE_WORKAROUND + /* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_120()){ + *(volatile uint32_t *)0x40029640ul = 0x200ul; + } + #endif + + #if NRF52_ERRATA_136_ENABLE_WORKAROUND + /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_136()){ + if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){ + NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk; + } + } + #endif + + #if NRF52_ERRATA_182_ENABLE_WORKAROUND + /* Workaround for Errata 182 "RADIO: Fixes for anomalies #102, #106, and #107 do not take effect" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_182()){ + *(volatile uint32_t *) 0x4000173C |= (0x1 << 10); + } + #endif + + #if NRF52_ERRATA_217_ENABLE_WORKAROUND + /* Workaround for Errata 217 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_217()){ + *(volatile uint32_t *)0x40000EE4ul |= 0x0000000Ful; + } + #endif + + /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the + * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit + * operations are not used in your code. */ + #if (__FPU_USED == 1) + SCB->CPACR |= (3UL << 20) | (3UL << 22); + __DSB(); + __ISB(); + #endif + + nrf52_handle_approtect(); + + /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined, + two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as + normal GPIOs. */ + #if defined (CONFIG_NFCT_PINS_AS_GPIOS) && defined(NFCT_PRESENT) + if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){ + nvmc_config(NVMC_CONFIG_WEN_Wen); + NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk; + nvmc_wait(); + nvmc_config(NVMC_CONFIG_WEN_Ren); + NVIC_SystemReset(); + } + #endif + + /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not + defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be + reserved for PinReset and not available as normal GPIO. */ + #if defined (CONFIG_GPIO_AS_PINRESET) + if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) || + ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){ + nvmc_config(NVMC_CONFIG_WEN_Wen); + NRF_UICR->PSELRESET[0] = RESET_PIN; + nvmc_wait(); + NRF_UICR->PSELRESET[1] = RESET_PIN; + nvmc_wait(); + nvmc_config(NVMC_CONFIG_WEN_Ren); + NVIC_SystemReset(); + } + #endif + + /* When developing for nRF52810 on an nRF52832, or nRF52811 on an nRF52840, + make sure NFC pins are mapped as GPIO. */ + #if defined (DEVELOP_IN_NRF52832) && defined(NRF52810_XXAA) \ + || defined (DEVELOP_IN_NRF52840) && defined(NRF52811_XXAA) + if ((*((uint32_t *)0x1000120C) & (1 << 0)) != 0){ + nvmc_config(NVMC_CONFIG_WEN_Wen); + *((uint32_t *)0x1000120C) = 0; + nvmc_wait(); + nvmc_config(NVMC_CONFIG_WEN_Ren); + NVIC_SystemReset(); + } + #endif + + SystemCoreClockUpdate(); +} diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/system_nrf52.h b/bsp/boards/nrf52840_dk/sdk/system_nrf52.h similarity index 87% rename from bsp/boards/nrf52840/sdk/modules/nrfx/mdk/system_nrf52.h rename to bsp/boards/nrf52840_dk/sdk/system_nrf52.h index bad303c6a0..42d9028cad 100644 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/system_nrf52.h +++ b/bsp/boards/nrf52840_dk/sdk/system_nrf52.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2018 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -49,7 +49,7 @@ extern void SystemInit (void); * @param none * @return none * - * @brief Updates the SystemCoreClock with current core Clock + * @brief Updates the SystemCoreClock with current core Clock * retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); diff --git a/bsp/boards/nrf52840_dk/sdk/system_nrf52840.c b/bsp/boards/nrf52840_dk/sdk/system_nrf52840.c new file mode 100644 index 0000000000..29a5b48d27 --- /dev/null +++ b/bsp/boards/nrf52840_dk/sdk/system_nrf52840.c @@ -0,0 +1,42 @@ +/* + +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#include "system_nrf52.c" diff --git a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/system_nrf52840.h b/bsp/boards/nrf52840_dk/sdk/system_nrf52840.h similarity index 87% rename from bsp/boards/nrf52840/sdk/modules/nrfx/mdk/system_nrf52840.h rename to bsp/boards/nrf52840_dk/sdk/system_nrf52840.h index 9ce00cc6df..1abe23901b 100644 --- a/bsp/boards/nrf52840/sdk/modules/nrfx/mdk/system_nrf52840.h +++ b/bsp/boards/nrf52840_dk/sdk/system_nrf52840.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2018 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -49,7 +49,7 @@ extern void SystemInit (void); * @param none * @return none * - * @brief Updates the SystemCoreClock with current core Clock + * @brief Updates the SystemCoreClock with current core Clock * retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); diff --git a/bsp/boards/nrf52840_dk/sdk/system_nrf52_approtect.h b/bsp/boards/nrf52840_dk/sdk/system_nrf52_approtect.h new file mode 100644 index 0000000000..10b50ea785 --- /dev/null +++ b/bsp/boards/nrf52840_dk/sdk/system_nrf52_approtect.h @@ -0,0 +1,65 @@ +/* + +Copyright (c) 2009-2021 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + +#ifndef SYSTEM_NRF52_APPROTECT_H +#define SYSTEM_NRF52_APPROTECT_H + +#include "nrf.h" +#include "nrf_erratas.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Function that handles firmware-driven enabling or disabling of APPROTECT on devices where it is supported. + If ENABLE_APPROTECT is defined, the FW will lock the fw branch of the APPROTECT mechanism, + preventing it from being opened. + Otherwise, the fw branch state is loaded from UICR, emulating the legacy APPROTECT behavior. + + The same mechanism is implemented for SECURE APPROTECT, with the macros + ENABLE_SECURE_APPROTECT and ENABLE_SECURE_APPROTECT_USER_HANDLING. */ +static inline void nrf52_handle_approtect(void) +{ + #if NRF52_ERRATA_249_PRESENT + #if defined (ENABLE_APPROTECT) + if (nrf52_errata_249()) + { + /* Prevent processor from unlocking APPROTECT soft branch after this point. */ + NRF_APPROTECT->FORCEPROTECT = APPROTECT_FORCEPROTECT_FORCEPROTECT_Force; + } + #else + if (nrf52_errata_249()) + { + /* Load APPROTECT soft branch from UICR. + If UICR->APPROTECT is disabled, POWER->APPROTECT will be disabled. */ + NRF_APPROTECT->DISABLE = NRF_UICR->APPROTECT; + } + #endif + #endif +} + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_NRF52_APPROTECT_H */ diff --git a/bsp/boards/nrf52840_dk/sdk/thumb_crt0.s b/bsp/boards/nrf52840_dk/sdk/thumb_crt0.s new file mode 100644 index 0000000000..2fceb49eb3 --- /dev/null +++ b/bsp/boards/nrf52840_dk/sdk/thumb_crt0.s @@ -0,0 +1,395 @@ +// ********************************************************************** +// * SEGGER Microcontroller GmbH * +// * The Embedded Experts * +// ********************************************************************** +// * * +// * (c) 2014 - 2022 SEGGER Microcontroller GmbH * +// * (c) 2001 - 2022 Rowley Associates Limited * +// * * +// * www.segger.com Support: support@segger.com * +// * * +// ********************************************************************** +// * * +// * All rights reserved. * +// * * +// * Redistribution and use in source and binary forms, with or * +// * without modification, are permitted provided that the following * +// * condition is met: * +// * * +// * - Redistributions of source code must retain the above copyright * +// * notice, this condition and the following disclaimer. * +// * * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +// * DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +// * DAMAGE. * +// * * +// ********************************************************************** +// +// +// Preprocessor Definitions +// ------------------------ +// APP_ENTRY_POINT +// +// Defines the application entry point function, if undefined this setting +// defaults to "main". +// +// INITIALIZE_STACK +// +// If defined, the contents of the stack will be initialized to a the +// value 0xCC. +// +// INITIALIZE_SECONDARY_SECTIONS +// +// If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized. +// +// INITIALIZE_TCM_SECTIONS +// +// If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections +// will be initialized. +// +// INITIALIZE_USER_SECTIONS +// +// If defined, the function InitializeUserMemorySections will be called prior +// to entering main in order to allow the user to initialize any user defined +// memory sections. +// +// FULL_LIBRARY +// +// If defined then +// - argc, argv are setup by the SEGGER_SEMIHOST_GetArgs. +// - the exit symbol is defined and executes on return from main. +// - the exit symbol calls destructors, atexit functions and then SEGGER_SEMIHOST_Exit. +// +// If not defined then +// - argc and argv are zero. +// - the exit symbol is defined, executes on return from main and loops +// +// STACK_CHECK +// +// If defined will set the v8m msplim/psplim registers to the start of the stacks +// +// RETURN_FROM_CRT0 +// +// If defined, carry out a return to link register on application exit. +// + + +#ifndef APP_ENTRY_POINT +#define APP_ENTRY_POINT main +#endif + +#ifndef ARGSSPACE +#define ARGSSPACE 128 +#endif + .syntax unified + + .global _start + .extern APP_ENTRY_POINT + .weak exit + +#ifdef INITIALIZE_USER_SECTIONS + .extern InitializeUserMemorySections +#endif + + .section .init, "ax" + .code 16 + .balign 2 + .thumb_func + +_start: + /* Set up main stack if size > 0 */ + ldr r1, =__stack_end__ + ldr r0, =__stack_start__ + subs r2, r1, r0 + beq 1f +#ifdef __ARM_EABI__ + movs r2, #0x7 + bics r1, r2 +#endif + mov sp, r1 +#ifdef RETURN_FROM_CRT0 + push {lr} +#endif +#ifdef INITIALIZE_STACK + movs r2, #0xCC + ldr r0, =__stack_start__ + bl memory_set +#endif +#ifdef STACK_CHECK + ldr r0, =__stack_start__ + msr msplim, r0 +#endif +1: + /* Set up process stack if size > 0 */ + ldr r1, =__stack_process_end__ + ldr r0, =__stack_process_start__ + subs r2, r1, r0 + beq 1f +#ifdef __ARM_EABI__ + movs r2, #0x7 + bics r1, r2 +#endif + msr psp, r1 + movs r2, #2 + msr control, r2 +#ifdef INITIALIZE_STACK + movs r2, #0xCC + bl memory_set +#endif +#ifdef STACK_CHECK + ldr r0, =__stack_process_start__ + msr psplim, r0 +#endif +1: + + /* Copy initialized memory sections into RAM (if necessary). */ + ldr r0, =__data_load_start__ + ldr r1, =__data_start__ + ldr r2, =__data_end__ + bl memory_copy + ldr r0, =__text_load_start__ + ldr r1, =__text_start__ + ldr r2, =__text_end__ + bl memory_copy + ldr r0, =__fast_load_start__ + ldr r1, =__fast_start__ + ldr r2, =__fast_end__ + bl memory_copy + ldr r0, =__ctors_load_start__ + ldr r1, =__ctors_start__ + ldr r2, =__ctors_end__ + bl memory_copy + ldr r0, =__dtors_load_start__ + ldr r1, =__dtors_start__ + ldr r2, =__dtors_end__ + bl memory_copy + ldr r0, =__rodata_load_start__ + ldr r1, =__rodata_start__ + ldr r2, =__rodata_end__ + bl memory_copy + ldr r0, =__tdata_load_start__ + ldr r1, =__tdata_start__ + ldr r2, =__tdata_end__ + bl memory_copy +#ifdef INITIALIZE_SECONDARY_SECTIONS + ldr r0, =__data2_load_start__ + ldr r1, =__data2_start__ + ldr r2, =__data2_end__ + bl memory_copy + ldr r0, =__text2_load_start__ + ldr r1, =__text2_start__ + ldr r2, =__text2_end__ + bl memory_copy + ldr r0, =__rodata2_load_start__ + ldr r1, =__rodata2_start__ + ldr r2, =__rodata2_end__ + bl memory_copy +#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */ +#ifdef INITIALIZE_TCM_SECTIONS + ldr r0, =__data_tcm_load_start__ + ldr r1, =__data_tcm_start__ + ldr r2, =__data_tcm_end__ + bl memory_copy + ldr r0, =__text_tcm_load_start__ + ldr r1, =__text_tcm_start__ + ldr r2, =__text_tcm_end__ + bl memory_copy + ldr r0, =__rodata_tcm_load_start__ + ldr r1, =__rodata_tcm_start__ + ldr r2, =__rodata_tcm_end__ + bl memory_copy +#endif /* #ifdef INITIALIZE_TCM_SECTIONS */ + + /* Zero the bss. */ + ldr r0, =__bss_start__ + ldr r1, =__bss_end__ + movs r2, #0 + bl memory_set + ldr r0, =__tbss_start__ + ldr r1, =__tbss_end__ + movs r2, #0 + bl memory_set +#ifdef INITIALIZE_SECONDARY_SECTIONS + ldr r0, =__bss2_start__ + ldr r1, =__bss2_end__ + mov r2, #0 + bl memory_set +#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */ +#ifdef INITIALIZE_TCM_SECTIONS + ldr r0, =__bss_tcm_start__ + ldr r1, =__bss_tcm_end__ + mov r2, #0 + bl memory_set +#endif /* #ifdef INITIALIZE_TCM_SECTIONS */ + +#if !defined(__HEAP_SIZE__) || (__HEAP_SIZE__) + /* Initialize the heap */ + ldr r0, = __heap_start__ + ldr r1, = __heap_end__ + subs r1, r1, r0 +#if defined(__SES_ARM) + bl __SEGGER_RTL_init_heap +#else + cmp r1, #8 + blt 1f + movs r2, #0 + str r2, [r0] + str r1, [r0, #4] +1: +#endif +#endif + +#ifdef INITIALIZE_USER_SECTIONS + ldr r2, =InitializeUserMemorySections + blx r2 +#endif + + .type start, function +start: + + /* Call constructors */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ +ctor_loop: + cmp r0, r1 + beq ctor_end + ldr r2, [r0] + adds r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b ctor_loop +ctor_end: + + /* Setup initial call frame */ + movs r0, #0 + mov lr, r0 + mov r12, sp + + .type __startup_complete, function +__startup_complete: + + /* Jump to application entry point */ +#ifdef FULL_LIBRARY + movs r0, #ARGSSPACE + ldr r1, =args + ldr r2, =SEGGER_SEMIHOST_GetArgs + blx r2 + ldr r1, =args +#else + movs r0, #0 + movs r1, #0 +#endif + ldr r2, =APP_ENTRY_POINT + blx r2 + + .thumb_func +exit: +#ifdef FULL_LIBRARY + mov r5, r0 // save the exit parameter/return result + + /* Call destructors */ + ldr r0, =__dtors_start__ + ldr r1, =__dtors_end__ +dtor_loop: + cmp r0, r1 + beq dtor_end + ldr r2, [r0] + adds r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b dtor_loop +dtor_end: + + /* Call atexit functions */ + ldr r2, =__SEGGER_RTL_execute_at_exit_fns + blx r2 + + /* Call SEGGER_SEMIHOST_Exit with return result/exit parameter */ + mov r0, r5 + ldr r2, =SEGGER_SEMIHOST_Exit + blx r2 +#endif + + /* Returned from application entry point */ +#ifdef RETURN_FROM_CRT0 + pop {r2} + bx r2 +#else + /* Loop forever */ +exit_loop: + b exit_loop +#endif + + .thumb_func +memory_copy: + cmp r0, r1 + beq 2f + subs r2, r2, r1 + beq 2f +1: + ldrb r3, [r0] + adds r0, r0, #1 + strb r3, [r1] + adds r1, r1, #1 + subs r2, r2, #1 + bne 1b +2: + bx lr + + .thumb_func +memory_set: + cmp r0, r1 + beq 1f + strb r2, [r0] + adds r0, r0, #1 + b memory_set +1: + bx lr + + // default C/C++ library helpers + +.macro HELPER helper_name + .section .text.\helper_name, "ax", %progbits + .balign 2 + .weak \helper_name + .thumb_func +\helper_name: +.endm + +HELPER __aeabi_read_tp + ldr r0, =__tbss_start__-8 + bx lr +HELPER abort + b . +HELPER __assert + b . +HELPER __assert_func + b . +HELPER __aeabi_assert + b . +HELPER __sync_synchronize + bx lr + +#ifdef FULL_LIBRARY + .bss +args: + .space ARGSSPACE +#endif + + /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */ + .section .stack, "wa", %nobits + .section .stack_process, "wa", %nobits + .section .heap, "wa", %nobits + diff --git a/bsp/boards/nrf52840/sensors.c b/bsp/boards/nrf52840_dk/sensors.c similarity index 100% rename from bsp/boards/nrf52840/sensors.c rename to bsp/boards/nrf52840_dk/sensors.c diff --git a/bsp/boards/nrf52840_dk/spi.c b/bsp/boards/nrf52840_dk/spi.c new file mode 100644 index 0000000000..61c30e90c3 --- /dev/null +++ b/bsp/boards/nrf52840_dk/spi.c @@ -0,0 +1,40 @@ +/** + * Author: Adam Sedmak (adam.sedmak@gmail.com) + * Company: Faculty of Electronics and Computing, Zagreb, Croatia + * Date: Apr 2018 + * Description: nRF52840-specific definition of the "spi" bsp module. + */ + +#include "board_info.h" +#include "spi.h" + +//=========================== defines ========================================= + + +#define SPI_SS_PIN NRF_GPIO_PIN_MAP(1,1) ///< P1.01 +#define SPI_MISO_PIN NRF_GPIO_PIN_MAP(1,2) ///< P1.02 +#define SPI_MOSI_PIN NRF_GPIO_PIN_MAP(1,3) ///< P1.03 +#define SPI_SCK_PIN NRF_GPIO_PIN_MAP(1,4) ///< P1.04 + +//=========================== variables ======================================= + +//=========================== prototypes ====================================== + +//=========================== public ========================================== + +void spi_init(void) { +} + + +void spi_txrx(uint8_t* bufTx, + uint16_t lenbufTx, + spi_return_t returnType, + uint8_t* bufRx, + uint16_t maxLenBufRx, + spi_first_t isFirst, + spi_last_t isLast) +{ + +} + +//=========================== private ========================================= \ No newline at end of file diff --git a/bsp/boards/nrf52840_dk/uart.c b/bsp/boards/nrf52840_dk/uart.c new file mode 100644 index 0000000000..a80a3f209b --- /dev/null +++ b/bsp/boards/nrf52840_dk/uart.c @@ -0,0 +1,180 @@ + /** + * Author: Tamas Harczos (tamas.harczos@imms.de) + * Date: Apr 2018 + * Description: nRF52840-specific definition of the "uart" bsp module. + */ + + +#include "nrf52840.h" +#include "nrf52840_bitfields.h" +#include "board_info.h" + +#include "leds.h" +#include "debugpins.h" +#include "uart.h" + +//=========================== defines ========================================= + +#define UART_RX_PIN NRF_GPIO_PIN_MAP(0,8) // p0.08 +#define UART_TX_PIN NRF_GPIO_PIN_MAP(0,6) // p0.06 +#define UART_CTS_PIN NRF_GPIO_PIN_MAP(0,7) // p0.07 +#define UART_RTS_PIN NRF_GPIO_PIN_MAP(0,5) // p0.05 + +#define UART_BAUDRATE_115200 0x01D7E000 // Baud 115200 +#define UART_BAUDRATE_1M 0x10000000 // Baud 1M + +#define UART_INTEN_RXDRDY_POS 2 +#define UART_INTEN_TXDRDY_POS 7 + +#define UART_CONFIG_PARITY 0 // excluded +#define UART_CONFIG_PARITY_POS 1 +#define UART_CONFIG_HWFC 0 +#define UART_CONFIG_HWFC_POS 0 + +//=========================== variables ======================================= + +typedef struct +{ + uart_tx_cbt txCb; + uart_rx_cbt rxCb; + bool fXonXoffEscaping; + uint8_t xonXoffEscapedByte; +} uart_vars_t; + +uart_vars_t uart_vars; + +//=========================== prototypes ====================================== + +//=========================== public ========================================== + +void uart_init(void) { + // reset local variables + memset(&uart_vars,0,sizeof(uart_vars_t)); + + NRF_P0->PIN_CNF[UART_TX_PIN] = ((uint32_t)GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos) + | ((uint32_t)GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) + | ((uint32_t)GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) + | ((uint32_t)GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | ((uint32_t)GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos); + NRF_P0->PIN_CNF[UART_RX_PIN] = ((uint32_t)GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) + | ((uint32_t)GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) + | ((uint32_t)GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) + | ((uint32_t)GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | ((uint32_t)GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos); + + NRF_UART0->PSEL.TXD = UART_TX_PIN; + NRF_UART0->PSEL.RXD = UART_RX_PIN; + + // default: stop 1 bit, no parity, no HWFC + NRF_UART0->CONFIG = 0 ; + NRF_UART0->BAUDRATE = UART_BAUDRATE_115200; + + NRF_UART0->EVENTS_TXDRDY = 0; + NRF_UART0->EVENTS_RXDRDY = 0; + NRF_UART0->INTENSET = (1 << UART_INTEN_RXDRDY_POS) |\ + (1 << UART_INTEN_TXDRDY_POS); + + NVIC->IP[UARTE0_UART0_IRQn] = (uint8_t)((UART_PRIORITY << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFF); + NVIC->ISER[UARTE0_UART0_IRQn>>5] = (uint32_t)(0x1 << (UARTE0_UART0_IRQn & 0x1f)); + + NRF_UART0->ENABLE = 4; // set to 4 to enable + + NRF_UART0->TASKS_STARTTX = 1; + NRF_UART0->TASKS_STARTRX = 1; +} + +void uart_setCallbacks(uart_tx_cbt txCb, uart_rx_cbt rxCb) { + uart_vars.txCb = txCb; + uart_vars.rxCb = rxCb; +} + +void uart_enableInterrupts(void) { + + NRF_UART0->INTENSET = + (uint32_t)(1<EVENTS_RXDRDY = (uint32_t)0; +} + +void uart_clearTxInterrupts(void) { + + NRF_UART0->EVENTS_TXDRDY = (uint32_t)0; +} + +void uart_setCTS(bool state) { + + if (state==0x01) { + NRF_UART0->TXD = XON; + } else { + NRF_UART0->TXD = XOFF; + } +} + +void uart_writeByte(uint8_t byteToWrite){ + + if (byteToWrite==XON || byteToWrite==XOFF || byteToWrite==XONXOFF_ESCAPE) { + uart_vars.fXonXoffEscaping = 0x01; + uart_vars.xonXoffEscapedByte = byteToWrite; + NRF_UART0->TXD = XONXOFF_ESCAPE; + } else { + NRF_UART0->TXD = byteToWrite; + } +} + +uint8_t uart_readByte(void) { + + return NRF_UART0->RXD; +} + +//=========================== private ========================================= + +void UARTE0_UART0_IRQHandler(void) { + + debugpins_isr_set(); + + if (NRF_UART0->EVENTS_RXDRDY) { + + NRF_UART0->EVENTS_RXDRDY = (uint32_t)0; + uart_rx_isr(); + } + + + if (NRF_UART0->EVENTS_TXDRDY) { + + NRF_UART0->EVENTS_TXDRDY = (uint32_t)0; + uart_tx_isr(); + } + + debugpins_isr_clr(); +} + +//=========================== interrupt handlers ============================== + +kick_scheduler_t uart_tx_isr(void) { + + if (uart_vars.fXonXoffEscaping==0x01) { + uart_vars.fXonXoffEscaping = 0x00; + NRF_UART0->TXD = uart_vars.xonXoffEscapedByte^XONXOFF_MASK; + } else { + if (uart_vars.txCb != NULL){ + uart_vars.txCb(); + return KICK_SCHEDULER; + } + } + + return DO_NOT_KICK_SCHEDULER; +} + +kick_scheduler_t uart_rx_isr(void) { + + if (uart_vars.rxCb != NULL){ + uart_vars.rxCb(); + return KICK_SCHEDULER; + } + + return DO_NOT_KICK_SCHEDULER; +} \ No newline at end of file diff --git a/bsp/boards/openmote-b-24ghz/board_info.h b/bsp/boards/openmote-b-24ghz/board_info.h index fa44269846..38373defbf 100644 --- a/bsp/boards/openmote-b-24ghz/board_info.h +++ b/bsp/boards/openmote-b-24ghz/board_info.h @@ -34,6 +34,7 @@ #define PORT_SIGNED_INT_WIDTH int32_t #define PORT_TICS_PER_MS 33 #define PORT_US_PER_TICK 30 // number of us per 32kHz clock tick +#define PORT_MAX_TICKS_IN_SINGLE_CLOCK (uint32_t)(0xffffffff>>1) // on GINA, we use the comparatorA interrupt for the OS #define SCHEDULER_WAKEUP() diff --git a/bsp/boards/openmote-b-subghz/board_info.h b/bsp/boards/openmote-b-subghz/board_info.h index a09cc1e7a5..c8c29efeae 100644 --- a/bsp/boards/openmote-b-subghz/board_info.h +++ b/bsp/boards/openmote-b-subghz/board_info.h @@ -34,6 +34,8 @@ #define PORT_SIGNED_INT_WIDTH int32_t #define PORT_TICS_PER_MS 33 #define PORT_US_PER_TICK 30 // number of us per 32kHz clock tick +#define PORT_MAX_TICKS_IN_SINGLE_CLOCK (uint32_t)(0xffffffff>>1) + // on GINA, we use the comparatorA interrupt for the OS #define SCHEDULER_WAKEUP() #define SCHEDULER_ENABLE_INTERRUPT() diff --git a/bsp/boards/openmote-cc2538/board_info.h b/bsp/boards/openmote-cc2538/board_info.h index 47f74b3065..1da030805c 100644 --- a/bsp/boards/openmote-cc2538/board_info.h +++ b/bsp/boards/openmote-cc2538/board_info.h @@ -34,6 +34,7 @@ #define PORT_SIGNED_INT_WIDTH int32_t #define PORT_TICS_PER_MS 33 #define PORT_US_PER_TICK 30 // number of us per 32kHz clock tick +#define PORT_MAX_TICKS_IN_SINGLE_CLOCK (uint32_t)(0xffffffff>>1) // on GINA, we use the comparatorA interrupt for the OS #define SCHEDULER_WAKEUP() diff --git a/bsp/chips/bmx160/bmx160.c b/bsp/chips/bmx160/bmx160.c new file mode 100644 index 0000000000..1ceb1d89be --- /dev/null +++ b/bsp/chips/bmx160/bmx160.c @@ -0,0 +1,181 @@ +/** +\brief bmx160 driver. + +\author Tengfei Chang , Nov 2021. +*/ + +#include "i2c.h" +#include "bmx160.h" + +//=========================== define ========================================== + +typedef struct{ + + int16_t mag_x; + int16_t mag_y; + int16_t mag_z; + + int16_t rhall; + + int16_t gyr_x; + int16_t gyr_y; + int16_t gyr_z; + + int16_t acc_x; + int16_t acc_y; + int16_t acc_z; + +}bmx160x_data_t; + +typedef struct { + + bmx160x_data_t bmx160x_data; + +}bmx160x_var_t; + +//=========================== variables ======================================= + +bmx160x_var_t bmx160x_var; + +//=========================== prototypes ====================================== + +//=========================== public ========================================== + +// admin +uint8_t bmx160_who_am_i(void) { + + uint8_t chipid; + i2c_read_bytes(BMX160_REG_ADDR_CHIPID, &chipid, 1); + return chipid; +} + +void bmx160_config_wakeup(void) { + +} + +uint8_t bmx160_power_down(void) { + +} + +uint8_t bmx160_get_pmu_status(void) { + + uint8_t pmu_status; + i2c_read_bytes(BMX160_REG_ADDR_PMU_STATUS, &pmu_status, 1); + return pmu_status; +} + + +void bmx160_set_cmd(uint8_t cmd) { + i2c_write_bytes(BMX160_REG_ADDR_CMD, &cmd, 1); +} + +// configuration + +void bmx160_acc_config(uint8_t config) { + i2c_write_bytes(BMX160_REG_ADDR_ACC_CONF, &config, 1); +} + +void bmx160_gyr_config(uint8_t config) { + i2c_write_bytes(BMX160_REG_ADDR_GYR_CONF, &config, 1); +} + +void bmx160_mag_config(uint8_t config) { + i2c_write_bytes(BMX160_REG_ADDR_MAG_CONF, &config, 1); +} + +// range & interface + +void bmx160_acc_range(uint8_t range) { + i2c_write_bytes(BMX160_REG_ADDR_ACC_RANGE, &range, 1); +} + +void bmx160_gyr_range(uint8_t range) { + i2c_write_bytes(BMX160_REG_ADDR_GYR_RANGE, &range, 1); +} + +void bmx160_mag_if(uint8_t interface) { + i2c_write_bytes(BMX160_REG_ADDR_MAG_IF, &interface, 1); +} + + +// read +void bmx160_read_9dof_data(void) { + + uint8_t pmu_status; + + // enable accelarometer + do { + bmx160_set_cmd(BMX160_CMD_PMU_ACC_NORMAL); + i2c_read_bytes(BMX160_REG_ADDR_PMU_STATUS, &pmu_status, 1); + } while ((pmu_status & 0x10) != 0x10); + + // enable gyroscope + do { + bmx160_set_cmd(BMX160_CMD_PMU_GYR_NORMAL); + i2c_read_bytes(BMX160_REG_ADDR_PMU_STATUS, &pmu_status, 1); + } while ((pmu_status & 0x04) != 0x04); + + // enabel mag + do { + bmx160_set_cmd(BMX160_CMD_PMU_MAG_IF_NORMAL); + i2c_read_bytes(BMX160_REG_ADDR_PMU_STATUS, &pmu_status, 1); + } while ((pmu_status & 0x01) != 0x01); + + // wait until pmu status are correct + // acc_normal gyr_normal mag_if_normal + // 0xb10 01 01 01 = 0x95 + + i2c_read_bytes(BMX160_REG_ADDR_DATA, (uint8_t*)(&bmx160x_var.bmx160x_data), sizeof(bmx160x_data_t)); +} + + +int16_t bmx160_read_acc_x(void) { + + return bmx160x_var.bmx160x_data.acc_x; +} +int16_t bmx160_read_acc_y(void) { + + return bmx160x_var.bmx160x_data.acc_y; +} +int16_t bmx160_read_acc_z(void) { + + return bmx160x_var.bmx160x_data.acc_z; +} + +int16_t bmx160_read_mag_x(void) { + + return bmx160x_var.bmx160x_data.mag_x; +} +int16_t bmx160_read_mag_y(void) { + + return bmx160x_var.bmx160x_data.mag_y; +} +int16_t bmx160_read_mag_z(void) { + + return bmx160x_var.bmx160x_data.mag_z; +} + +int16_t bmx160_read_gyr_x(void) { + + return bmx160x_var.bmx160x_data.gyr_x; +} +int16_t bmx160_read_gyr_y(void) { + + return bmx160x_var.bmx160x_data.gyr_y; +} +int16_t bmx160_read_gyr_z(void) { + + return bmx160x_var.bmx160x_data.gyr_z; +} + +//=========================== helper ========================================== + +float bmx160_from_lsb_to_celsius(int16_t lsb) { + +} + +float bmx160_from_fs8_lp1_to_mg(int16_t lsb) { + +} + +//=========================== private ========================================= \ No newline at end of file diff --git a/bsp/chips/bmx160/bmx160.h b/bsp/chips/bmx160/bmx160.h new file mode 100644 index 0000000000..2c4b538f2f --- /dev/null +++ b/bsp/chips/bmx160/bmx160.h @@ -0,0 +1,112 @@ +/** +\brief registers address mapping of bmx160 sensor. + +\author Tengfei Chang , Nov 2021. +*/ + +#include "stdint.h" + +//=========================== define ========================================== + +#define BMX160_ADDR 0x68 + +//---- register addresses + +#define BMX160_REG_ADDR_CHIPID 0x00 +#define BMX160_REG_ADDR_ERR_REG 0x02 +#define BMX160_REG_ADDR_PMU_STATUS 0x03 + +// sensor data + +#define BMX160_REG_ADDR_DATA 0x04 + +#define BMX160_REG_ADDR_MAG_X_L 0x04 +#define BMX160_REG_ADDR_MAG_X_H 0x05 +#define BMX160_REG_ADDR_MAG_Y_L 0x06 +#define BMX160_REG_ADDR_MAG_Y_H 0x07 +#define BMX160_REG_ADDR_MAG_Z_L 0x08 +#define BMX160_REG_ADDR_MAG_Z_H 0x09 +#define BMX160_REG_ADDR_RHALL_L 0x0a +#define BMX160_REG_ADDR_RHALL_H 0x0b +#define BMX160_REG_ADDR_GYR_X_L 0x0c +#define BMX160_REG_ADDR_GYR_X_H 0x0d +#define BMX160_REG_ADDR_GYR_Y_L 0x0e +#define BMX160_REG_ADDR_GYR_Y_H 0x0f +#define BMX160_REG_ADDR_GYR_Z_L 0x10 +#define BMX160_REG_ADDR_GYR_Z_H 0x11 +#define BMX160_REG_ADDR_ACC_X_L 0x12 +#define BMX160_REG_ADDR_ACC_X_H 0x13 +#define BMX160_REG_ADDR_ACC_Y_L 0x14 +#define BMX160_REG_ADDR_ACC_Y_H 0x15 +#define BMX160_REG_ADDR_ACC_Z_L 0x16 +#define BMX160_REG_ADDR_ACC_Z_H 0x17 + +#define BMX160_REG_ADDR_SENSORTIME 0x18 +#define BMX160_REG_ADDR_STATUS 0x1B +#define BMX160_REG_ADDR_INT_STATUS 0x1C +#define BMX160_REG_ADDR_TEMPERATURE 0x20 +#define BMX160_REG_ADDR_FIFO_LENGTH 0x22 +#define BMX160_REG_ADDR_FIFO_DATA 0x24 +#define BMX160_REG_ADDR_ACC_CONF 0x40 +#define BMX160_REG_ADDR_ACC_RANGE 0x41 +#define BMX160_REG_ADDR_GYR_CONF 0x42 +#define BMX160_REG_ADDR_GYR_RANGE 0x43 +#define BMX160_REG_ADDR_MAG_CONF 0x44 +#define BMX160_REG_ADDR_FIFO_DOWNS 0x45 +#define BMX160_REG_ADDR_FIFO_CONFIG 0x46 +#define BMX160_REG_ADDR_MAG_IF 0x4C +#define BMX160_REG_ADDR_INT_EN 0x50 +#define BMX160_REG_ADDR_CMD 0x7E + +//---- register values + +#define BMX160_CMD_PMU_ACC_SUSPEND 0x10 +#define BMX160_CMD_PMU_ACC_NORMAL 0x11 +#define BMX160_CMD_PMU_ACC_LOW_POWER 0x12 + +#define BMX160_CMD_PMU_GYR_SUSPEND 0x14 +#define BMX160_CMD_PMU_GYR_NORMAL 0x15 +#define BMX160_CMD_PMU_GYR_FSU 0x17 + +#define BMX160_CMD_PMU_MAG_IF_SUSPEND 0x18 +#define BMX160_CMD_PMU_MAG_IF_NORMAL 0x19 +#define BMX160_CMD_PMU_MAG_IF_LOW_POWER 0x1A + +//=========================== variables ======================================= + +//=========================== prototypes ====================================== + +//=========================== public ========================================== + +// admin +uint8_t bmx160_who_am_i(void); +uint8_t bmx160_power_down(void); +uint8_t bmx160_get_pmu_status(void); + +void bmx160_set_cmd(uint8_t cmd); +void bmx160_acc_config(uint8_t config); +void bmx160_gyr_config(uint8_t config); +void bmx160_mag_config(uint8_t config); + +void bmx160_acc_range(uint8_t range); +void bmx160_gyr_range(uint8_t range); +void bmx160_mag_if(uint8_t interface); + +// read +int16_t bmx160_read_temperature(void); + +int16_t bmx160_read_acc_x(void); +int16_t bmx160_read_acc_y(void); +int16_t bmx160_read_acc_z(void); + +int16_t bmx160_read_mag_x(void); +int16_t bmx160_read_mag_y(void); +int16_t bmx160_read_mag_z(void); + +int16_t bmx160_read_gyr_x(void); +int16_t bmx160_read_gyr_y(void); +int16_t bmx160_read_gyr_z(void); + +void bmx160_read_9dof_data(void); + +//=========================== private ========================================= \ No newline at end of file diff --git a/drivers/common/opentimers.c b/drivers/common/opentimers.c index 0c7c6683ce..7c3ea9a8a4 100644 --- a/drivers/common/opentimers.c +++ b/drivers/common/opentimers.c @@ -133,9 +133,9 @@ void opentimers_scheduleIn(opentimers_id_t id, } if (opentimers_vars.timersBuf[id].wraps_remaining==0){ - opentimers_vars.timersBuf[id].currentCompareValue = opentimers_vars.timersBuf[id].duration+sctimer_readCounter(); + opentimers_vars.timersBuf[id].currentCompareValue = (opentimers_vars.timersBuf[id].duration+sctimer_readCounter()) & MAX_TICKS_IN_SINGLE_CLOCK; } else { - opentimers_vars.timersBuf[id].currentCompareValue = MAX_TICKS_IN_SINGLE_CLOCK+sctimer_readCounter(); + opentimers_vars.timersBuf[id].currentCompareValue = (MAX_TICKS_IN_SINGLE_CLOCK+sctimer_readCounter()) & MAX_TICKS_IN_SINGLE_CLOCK; } opentimers_vars.timersBuf[id].isrunning = TRUE; @@ -149,11 +149,11 @@ void opentimers_scheduleIn(opentimers_id_t id, while (opentimers_vars.timersBuf[i].isrunning==FALSE){ i++; } - timerGap = opentimers_vars.timersBuf[i].currentCompareValue-opentimers_vars.lastCompareValue; + timerGap = (opentimers_vars.timersBuf[i].currentCompareValue-opentimers_vars.lastCompareValue) & MAX_TICKS_IN_SINGLE_CLOCK; idToSchedule = i; for (i=idToSchedule+1;i>1) +#define MAX_TICKS_IN_SINGLE_CLOCK PORT_MAX_TICKS_IN_SINGLE_CLOCK #define ERROR_NO_AVAILABLE_ENTRIES 255 #define MAX_DURATION_ISR 33 // 33@32768Hz = 1ms #define opentimers_id_t uint8_t diff --git a/inc/check_config.h b/inc/check_config.h index d2f4c96724..775eafb453 100644 --- a/inc/check_config.h +++ b/inc/check_config.h @@ -16,7 +16,7 @@ !defined(IOTLAB_M3) && \ !defined(IOTLAB_A8_M3) && \ !defined(SAMR21_XPRO) && \ - !defined(NRF52840) + !defined(NRF52840_DK) #error 'Board name must be specified to check for configuration errors' #endif @@ -29,7 +29,7 @@ defined(WSN430V14) || \ defined(OPENMOTESTM) || \ defined(GINA) || \ - defined(NRF52840) || \ + defined(NRF52840_DK) || \ defined(AGILEFOX) || \ defined(IOTLAB_M3) || \ defined(IOTLAB_A8_M3) || \ @@ -45,7 +45,7 @@ defined(WSN430V14) || \ defined(AGILEFOX) || \ defined(GINA) || \ - defined(NRF52840) || \ + defined(NRF52840_DK) || \ defined(SAMR21_XPRO) || \ defined(Z1) || \ defined(OPENMOTESTM)) diff --git a/openapps/uinject/uinject.c b/openapps/uinject/uinject.c index b57d3fa481..2f869c2859 100644 --- a/openapps/uinject/uinject.c +++ b/openapps/uinject/uinject.c @@ -19,7 +19,7 @@ //=========================== defines ========================================= -#define UINJECT_TRAFFIC_RATE 2 ///> the value X indicates 1 packet/X minutes +#define UINJECT_TRAFFIC_RATE 1 ///> the value X indicates 1 packet/X minutes //=========================== variables ======================================= diff --git a/projects/common/01bsp_i2c/01bsp_i2c.c b/projects/common/01bsp_i2c/01bsp_i2c.c new file mode 100644 index 0000000000..e2cbf1da89 --- /dev/null +++ b/projects/common/01bsp_i2c/01bsp_i2c.c @@ -0,0 +1,60 @@ +/** +\brief This is a program shows how to read data from i2c slave device. + +\note: Since the bsp modules for different platforms have the same declaration, + you can use this project with any platform. + +This project reads the chipid through i2c interface with the device. + +\author Tengfei Chang , July 2023. +*/ + +#include "stdint.h" +#include "stdio.h" +// bsp modules required +#include "board.h" +#include "i2c.h" + +//=========================== defines ========================================= + +#define I2C_DEV_ADDR 0x68 +#define I2C_DEV_REG_ADDR_CHIPID 0x00 + +//=========================== variables ======================================= + +typedef struct { + uint8_t who_am_i; +} app_vars_t; + +app_vars_t app_vars; + +//=========================== prototypes ====================================== + +//=========================== main ============================================ + +/** +\brief The program starts executing here. +*/ +int mote_main(void) { + + uint32_t tmp; + uint32_t i; + + memset(&app_vars,0,sizeof(app_vars)); + + // initialize + + board_init(); + + // alway set address first + i2c_set_addr(I2C_DEV_ADDR); + + // retrieve radio manufacturer ID over SPI + while(1) { + + tmp = i2c_read_bytes(I2C_DEV_REG_ADDR_CHIPID, &app_vars.who_am_i, 1); + for (i=0;i<0xfffff;i++); + } +} + +//=========================== callbacks ======================================= \ No newline at end of file diff --git a/projects/common/01bsp_radio/01bsp_radio.c b/projects/common/01bsp_radio/01bsp_radio.c index 756f907e75..554d7aa075 100644 --- a/projects/common/01bsp_radio/01bsp_radio.c +++ b/projects/common/01bsp_radio/01bsp_radio.c @@ -50,6 +50,9 @@ typedef struct { uint8_t num_startFrame; uint8_t num_endFrame; uint8_t num_timer; + + uint8_t num_rx_startFrame; + uint8_t num_rx_endFrame; } app_dbg_t; app_dbg_t app_dbg; @@ -299,6 +302,10 @@ void cb_startFrame(PORT_TIMER_WIDTH timestamp) { // update debug stats app_dbg.num_startFrame++; + + if (app_vars.state == APP_STATE_RX) { + app_dbg.num_rx_startFrame++; + } } void cb_endFrame(PORT_TIMER_WIDTH timestamp) { @@ -307,6 +314,10 @@ void cb_endFrame(PORT_TIMER_WIDTH timestamp) { // update debug stats app_dbg.num_endFrame++; + + if (app_vars.state == APP_STATE_RX) { + app_dbg.num_rx_endFrame++; + } } void cb_timer(void) { diff --git a/projects/common/03oos_macpong/03oos_macpong.c b/projects/common/03oos_macpong/03oos_macpong.c index 91af2bfa6d..2391ed1e52 100644 --- a/projects/common/03oos_macpong/03oos_macpong.c +++ b/projects/common/03oos_macpong/03oos_macpong.c @@ -213,4 +213,5 @@ void coap_init(void) { return; } //===== L7 void openapps_init(void) { return; } +void openweb_init(void) { return; } diff --git a/projects/nrf52840/01bsp_debugpins/01bsp_debugpins.emProject b/projects/nrf52840/01bsp_debugpins/01bsp_debugpins.emProject deleted file mode 100644 index 79839528e1..0000000000 --- a/projects/nrf52840/01bsp_debugpins/01bsp_debugpins.emProject +++ /dev/null @@ -1,119 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/nrf52840/01bsp_debugpins/flash_placement.xml b/projects/nrf52840/01bsp_debugpins/flash_placement.xml deleted file mode 100644 index ec73e42550..0000000000 --- a/projects/nrf52840/01bsp_debugpins/flash_placement.xml +++ /dev/null @@ -1,36 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/nrf52840/01bsp_leds/01bsp_leds.emProject b/projects/nrf52840/01bsp_leds/01bsp_leds.emProject deleted file mode 100644 index 155b7747c7..0000000000 --- a/projects/nrf52840/01bsp_leds/01bsp_leds.emProject +++ /dev/null @@ -1,119 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/nrf52840/01bsp_leds/flash_placement.xml b/projects/nrf52840/01bsp_leds/flash_placement.xml deleted file mode 100644 index ec73e42550..0000000000 --- a/projects/nrf52840/01bsp_leds/flash_placement.xml +++ /dev/null @@ -1,36 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/nrf52840/01bsp_radio/01bsp_radio.emProject b/projects/nrf52840/01bsp_radio/01bsp_radio.emProject deleted file mode 100644 index 6b0dfd2e8b..0000000000 --- a/projects/nrf52840/01bsp_radio/01bsp_radio.emProject +++ /dev/null @@ -1,119 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/nrf52840/01bsp_radio/flash_placement.xml b/projects/nrf52840/01bsp_radio/flash_placement.xml deleted file mode 100644 index ec73e42550..0000000000 --- a/projects/nrf52840/01bsp_radio/flash_placement.xml +++ /dev/null @@ -1,36 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/nrf52840/01bsp_radio_ble/01bsp_radio_ble.c b/projects/nrf52840/01bsp_radio_ble/01bsp_radio_ble.c deleted file mode 100644 index 1ce475679e..0000000000 --- a/projects/nrf52840/01bsp_radio_ble/01bsp_radio_ble.c +++ /dev/null @@ -1,298 +0,0 @@ -/** -\brief This program shows the use of the "radio" bsp module. - -Since the bsp modules for different platforms have the same declaration, you -can use this project with any platform. - -After loading this program, your board will switch on its radio on frequency -CHANNEL. - -While receiving a packet (i.e. from the start of frame event to the end of -frame event), it will turn on its sync LED. - -Every TIMER_PERIOD, it will also send a packet containing LENGTH_PACKET bytes -set to ID. While sending a packet (i.e. from the start of frame event to the -end of frame event), it will turn on its error LED. - -\author Tengfei Chang , August 2020. -*/ - -#include "board.h" -#include "radio.h" -#include "leds.h" -#include "sctimer.h" -#include "radio_ble.h" - -//=========================== defines ========================================= - -#define LENGTH_PACKET 125+LENGTH_CRC ///< maximum length is 127 bytes -#define CHANNEL 38 ///< 0~39 -#define TIMER_PERIOD (0xffff>>2) ///< 0xffff = 2s@32kHz -#define TXPOWER 0xD5 ///< 2's complement format, 0xD8 = -40dbm - -const static uint8_t ble_device_addr[6] = { - 0xaa, 0xbb, 0xcc, 0xcc, 0xbb, 0xaa -}; - -// get from https://openuuid.net/signin/: a24e7112-a03f-4623-bb56-ae67bd653c73 -const static uint8_t ble_uuid[16] = { - - 0xa2, 0x4e, 0x71, 0x12, 0xa0, 0x3f, - 0x46, 0x23, 0xbb, 0x56, 0xae, 0x67, - 0xbd, 0x65, 0x3c, 0x73 -}; - -//=========================== variables ======================================= - -enum { - APP_FLAG_START_FRAME = 0x01, - APP_FLAG_END_FRAME = 0x02, - APP_FLAG_TIMER = 0x04, -}; - -typedef enum { - APP_STATE_TX = 0x01, - APP_STATE_RX = 0x02, -} app_state_t; - -typedef struct { - uint8_t num_startFrame; - uint8_t num_endFrame; - uint8_t num_timer; -} app_dbg_t; - -app_dbg_t app_dbg; - -typedef struct { - uint8_t flags; - app_state_t state; - uint8_t packet[LENGTH_PACKET]; - uint8_t packet_len; - int8_t rxpk_rssi; - uint8_t rxpk_lqi; - bool rxpk_crc; -} app_vars_t; - -app_vars_t app_vars; - -//=========================== prototypes ====================================== - -void cb_startFrame(PORT_TIMER_WIDTH timestamp); -void cb_endFrame(PORT_TIMER_WIDTH timestamp); -void cb_timer(void); - -void assemble_ibeacon_packet(void); - -//=========================== main ============================================ - -/** -\brief The program starts executing here. -*/ -int mote_main(void) { - uint8_t i; - - uint8_t freq_offset; - uint8_t sign; - uint8_t read; - - // clear local variables - memset(&app_vars,0,sizeof(app_vars_t)); - - // initialize board - board_init(); - radio_ble_init(); - - // add callback functions radio - radio_setStartFrameCb(cb_startFrame); - radio_setEndFrameCb(cb_endFrame); - - // prepare packet - app_vars.packet_len = sizeof(app_vars.packet); - - // start bsp timer - sctimer_set_callback(cb_timer); - sctimer_setCompare(sctimer_readCounter()+TIMER_PERIOD); - sctimer_enable(); - - // prepare radio - radio_rfOn(); - // freq type only effects on scum port - radio_ble_setFrequency(CHANNEL); - - // switch in RX by default - radio_rxEnable(); - app_vars.state = APP_STATE_RX; - - // start by a transmit - app_vars.flags |= APP_FLAG_TIMER; - - while (1) { - - // sleep while waiting for at least one of the flags to be set - while (app_vars.flags==0x00) { - board_sleep(); - } - - // handle and clear every flag - while (app_vars.flags) { - - - //==== APP_FLAG_START_FRAME (TX or RX) - - if (app_vars.flags & APP_FLAG_START_FRAME) { - // start of frame - - switch (app_vars.state) { - case APP_STATE_RX: - // started receiving a packet - - // led - leds_error_on(); - break; - case APP_STATE_TX: - // started sending a packet - - // led - leds_sync_on(); - break; - } - - // clear flag - app_vars.flags &= ~APP_FLAG_START_FRAME; - } - - //==== APP_FLAG_END_FRAME (TX or RX) - - if (app_vars.flags & APP_FLAG_END_FRAME) { - // end of frame - - switch (app_vars.state) { - - case APP_STATE_RX: - - // done receiving a packet - app_vars.packet_len = sizeof(app_vars.packet); - - // get packet from radio - radio_ble_getReceivedFrame( - app_vars.packet, - &app_vars.packet_len, - sizeof(app_vars.packet), - &app_vars.rxpk_rssi, - &app_vars.rxpk_lqi, - &app_vars.rxpk_crc - ); - - // led - leds_error_off(); - - // continue to listen - radio_rxNow(); - break; - case APP_STATE_TX: - // done sending a packet - - memset( app_vars.packet, 0x00, sizeof(app_vars.packet) ); - - // switch to RX mode - radio_rxEnable(); - radio_rxNow(); - app_vars.state = APP_STATE_RX; - - // led - leds_sync_off(); - break; - } - // clear flag - app_vars.flags &= ~APP_FLAG_END_FRAME; - } - - //==== APP_FLAG_TIMER - - if (app_vars.flags & APP_FLAG_TIMER) { - // timer fired - - if (app_vars.state==APP_STATE_RX) { - // stop listening - radio_rfOff(); - - // prepare packet - app_vars.packet_len = sizeof(app_vars.packet); - - assemble_ibeacon_packet(); - - // start transmitting packet - radio_ble_loadPacket(app_vars.packet,LENGTH_PACKET); - radio_txEnable(); - radio_txNow(); - - app_vars.state = APP_STATE_TX; - } - - // clear flag - app_vars.flags &= ~APP_FLAG_TIMER; - } - } - } -} -//=========================== private ========================================= - -void assemble_ibeacon_packet(void) { - - uint8_t i; - i=0; - - memset( app_vars.packet, 0x00, sizeof(app_vars.packet) ); - - app_vars.packet[i++] = 0x42; // BLE ADV_NONCONN_IND (this is a must) - app_vars.packet[i++] = 0x21; // Payload length - app_vars.packet[i++] = ble_device_addr[0]; // BLE adv address byte 0 - app_vars.packet[i++] = ble_device_addr[1]; // BLE adv address byte 1 - app_vars.packet[i++] = ble_device_addr[2]; // BLE adv address byte 2 - app_vars.packet[i++] = ble_device_addr[3]; // BLE adv address byte 3 - app_vars.packet[i++] = ble_device_addr[4]; // BLE adv address byte 4 - app_vars.packet[i++] = ble_device_addr[5]; // BLE adv address byte 5 - - app_vars.packet[i++] = 0x1a; - app_vars.packet[i++] = 0xff; - app_vars.packet[i++] = 0x4c; - app_vars.packet[i++] = 0x00; - - app_vars.packet[i++] = 0x02; - app_vars.packet[i++] = 0x15; - memcpy(&app_vars.packet[i], &ble_uuid[0], 16); - i += 16; - app_vars.packet[i++] = 0x00; // major - app_vars.packet[i++] = 0xff; - app_vars.packet[i++] = 0x00; // minor - app_vars.packet[i++] = 0x0f; - app_vars.packet[i++] = TXPOWER; // power level -} - -//=========================== callbacks ======================================= - -void cb_startFrame(PORT_TIMER_WIDTH timestamp) { - // set flag - app_vars.flags |= APP_FLAG_START_FRAME; - - // update debug stats - app_dbg.num_startFrame++; -} - -void cb_endFrame(PORT_TIMER_WIDTH timestamp) { - // set flag - app_vars.flags |= APP_FLAG_END_FRAME; - - // update debug stats - app_dbg.num_endFrame++; -} - -void cb_timer(void) { - // set flag - app_vars.flags |= APP_FLAG_TIMER; - - // update debug stats - app_dbg.num_timer++; - - sctimer_setCompare(sctimer_readCounter()+TIMER_PERIOD); -} \ No newline at end of file diff --git a/projects/nrf52840/01bsp_radio_ble/01bsp_radio_ble.emProject b/projects/nrf52840/01bsp_radio_ble/01bsp_radio_ble.emProject deleted file mode 100644 index 02e31f30a7..0000000000 --- a/projects/nrf52840/01bsp_radio_ble/01bsp_radio_ble.emProject +++ /dev/null @@ -1,123 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/nrf52840/01bsp_sctimer/01bsp_sctimer.emProject b/projects/nrf52840/01bsp_sctimer/01bsp_sctimer.emProject deleted file mode 100644 index 850547ca2f..0000000000 --- a/projects/nrf52840/01bsp_sctimer/01bsp_sctimer.emProject +++ /dev/null @@ -1,119 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/nrf52840/01bsp_sctimer/flash_placement.xml b/projects/nrf52840/01bsp_sctimer/flash_placement.xml deleted file mode 100644 index ec73e42550..0000000000 --- a/projects/nrf52840/01bsp_sctimer/flash_placement.xml +++ /dev/null @@ -1,36 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/nrf52840/01bsp_uart/01bsp_uart.emProject b/projects/nrf52840/01bsp_uart/01bsp_uart.emProject deleted file mode 100644 index d30ff9b673..0000000000 --- a/projects/nrf52840/01bsp_uart/01bsp_uart.emProject +++ /dev/null @@ -1,196 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/nrf52840/01bsp_uart/flash_placement.xml b/projects/nrf52840/01bsp_uart/flash_placement.xml deleted file mode 100644 index ec73e42550..0000000000 --- a/projects/nrf52840/01bsp_uart/flash_placement.xml +++ /dev/null @@ -1,36 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/nrf52840/02drv_openserial/02drv_openserial.emProject b/projects/nrf52840/02drv_openserial/02drv_openserial.emProject deleted file mode 100644 index 78de1f20a6..0000000000 --- a/projects/nrf52840/02drv_openserial/02drv_openserial.emProject +++ /dev/null @@ -1,126 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/nrf52840/02drv_openserial/flash_placement.xml b/projects/nrf52840/02drv_openserial/flash_placement.xml deleted file mode 100644 index ec73e42550..0000000000 --- a/projects/nrf52840/02drv_openserial/flash_placement.xml +++ /dev/null @@ -1,36 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/nrf52840/02drv_opentimers/02drv_opentimers.emProject b/projects/nrf52840/02drv_opentimers/02drv_opentimers.emProject deleted file mode 100644 index a3dfd016b4..0000000000 --- a/projects/nrf52840/02drv_opentimers/02drv_opentimers.emProject +++ /dev/null @@ -1,126 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/nrf52840/02drv_opentimers/flash_placement.xml b/projects/nrf52840/02drv_opentimers/flash_placement.xml deleted file mode 100644 index 3ebfc8b247..0000000000 --- a/projects/nrf52840/02drv_opentimers/flash_placement.xml +++ /dev/null @@ -1,36 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/nrf52840/03oos_macpong/03oos_macpong.emProject b/projects/nrf52840/03oos_macpong/03oos_macpong.emProject deleted file mode 100644 index dc222c320d..0000000000 --- a/projects/nrf52840/03oos_macpong/03oos_macpong.emProject +++ /dev/null @@ -1,143 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/nrf52840/03oos_macpong/flash_placement.xml b/projects/nrf52840/03oos_macpong/flash_placement.xml deleted file mode 100644 index ec73e42550..0000000000 --- a/projects/nrf52840/03oos_macpong/flash_placement.xml +++ /dev/null @@ -1,36 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/nrf52840/03oos_openwsn/03oos_openwsn_DK.emProject b/projects/nrf52840/03oos_openwsn/03oos_openwsn_DK.emProject deleted file mode 100644 index cfd1c42f26..0000000000 --- a/projects/nrf52840/03oos_openwsn/03oos_openwsn_DK.emProject +++ /dev/null @@ -1,215 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/nrf52840/03oos_openwsn/03oos_openwsn_DONGLE.emProject b/projects/nrf52840/03oos_openwsn/03oos_openwsn_DONGLE.emProject deleted file mode 100644 index e9ace3e08d..0000000000 --- a/projects/nrf52840/03oos_openwsn/03oos_openwsn_DONGLE.emProject +++ /dev/null @@ -1,198 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/nrf52840/03oos_openwsn/flash_placement.xml b/projects/nrf52840/03oos_openwsn/flash_placement.xml deleted file mode 100644 index 3ebfc8b247..0000000000 --- a/projects/nrf52840/03oos_openwsn/flash_placement.xml +++ /dev/null @@ -1,36 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/nrf52840_dk/01bsp_bmx160/01bsp_bmx160.c b/projects/nrf52840_dk/01bsp_bmx160/01bsp_bmx160.c new file mode 100644 index 0000000000..19b514f876 --- /dev/null +++ b/projects/nrf52840_dk/01bsp_bmx160/01bsp_bmx160.c @@ -0,0 +1,177 @@ +/** +\brief This program shows the use of the "bmx160" bsp module. + +Since the bsp modules for different platforms have the same declaration, you +can use this project with any platform. + +This project configure bmx160 and read the gyroscope values in 3 axises. +Then it sends out the gyro data through uart at interval of SAMPLE_PERIOD. + +\author Tengfei Chang , Nov 2021. +*/ + +#include "stdio.h" +#include "stdint.h" +#include "string.h" +#include "board.h" +#include "leds.h" +#include "sctimer.h" +#include "i2c.h" +#include "uart.h" +#include "bmx160.h" + +//=========================== defines ========================================= + +#define SAMPLE_PERIOD (32768>>4) // @32kHz = 1s +#define BUFFER_SIZE 0x08 //2B*3 axises value + 2B ending with '\r\n' + +//=========================== variables ======================================= + +typedef struct { + uint16_t num_compare; + bool sampling_now; + uint8_t axes[6]; + float axis_x; + float axis_y; + float axis_z; + + uint8_t who_am_i; + int16_t temp; + float temp_f; + + // uart specific + uint8_t uart_lastTxByteIndex; + volatile uint8_t uartDone; + volatile uint8_t uartSendNow; + volatile uint8_t uartToSend[BUFFER_SIZE]; +} app_vars_t; + +app_vars_t app_vars; + +//=========================== prototypes ====================================== + +void cb_compare(void); +void cb_uartTxDone(void); +uint8_t cb_uartRxCb(void); + +//=========================== main ============================================ + +/** +\brief The program starts executing here. +*/ +int mote_main(void) { + + int16_t tmp; + uint8_t i; + + // initialize board. + board_init(); + + // setup UART + uart_setCallbacks(cb_uartTxDone,cb_uartRxCb); + uart_enableInterrupts(); + + sctimer_set_callback(cb_compare); + sctimer_setCompare(sctimer_readCounter()+SAMPLE_PERIOD); + + // alway set address first + i2c_set_addr(BMX160_ADDR); + + // should be 0xd8 for bmx160 + app_vars.who_am_i = bmx160_who_am_i(); + + // configure bmx160 + + // 0x8: 100Hz + // 0xb: 800Hz + // 0xc: 1600Hz + bmx160_acc_config(0x0c); + // 0x8: 100Hz + // 0xc: 1600Hz + // 0xd: 3200Hz + bmx160_gyr_config(0x0d); + // 0x8: 100Hz + // 0xb: 800Hz + bmx160_mag_config(0x0b); + + // 0x3: +/-2g + // 0x5: +/-4g + // 0x8: +/-8g + // 0xc: +/-16g + bmx160_acc_range(0x8); + // 0x0: +/-2000°/s = 16.4LSB/°/s + // 0x1: +/-1000°/s = 32.8LSB/°/s + // 0x2: +/-500°/s = 131.2LSB/°/s + // 0x3: +/-250°/s = 262.4LSB/°/s + bmx160_gyr_range(0x1); + // ToDo + //bmx160_mag_if(); + + while (1) { + + // wait for timer to elapse + while (app_vars.uartSendNow==0); + app_vars.uartSendNow = 0; + + bmx160_read_9dof_data(); + + i=0; + tmp = bmx160_read_gyr_x(); + app_vars.uartToSend[i++] = (uint8_t)((tmp>>8) & 0x00ff); + app_vars.uartToSend[i++] = (uint8_t)((tmp>>0) & 0x00ff); + + tmp = bmx160_read_gyr_y(); + app_vars.uartToSend[i++] = (uint8_t)((tmp>>8) & 0x00ff); + app_vars.uartToSend[i++] = (uint8_t)((tmp>>0) & 0x00ff); + + tmp = bmx160_read_gyr_z(); + app_vars.uartToSend[i++] = (uint8_t)((tmp>>8) & 0x00ff); + app_vars.uartToSend[i++] = (uint8_t)((tmp>>0) & 0x00ff); + + app_vars.uartToSend[i++] = '\r'; + app_vars.uartToSend[i++] = '\n'; + + // send string over UART + app_vars.uartDone = 0; + app_vars.uart_lastTxByteIndex = 0; + uart_writeByte(app_vars.uartToSend[app_vars.uart_lastTxByteIndex]); + while(app_vars.uartDone==0); + } +} + +//=========================== callbacks ======================================= + +void cb_compare(void) { + + // have main "task" send over UART + app_vars.uartSendNow = 1; + + // schedule again + sctimer_setCompare(sctimer_readCounter()+SAMPLE_PERIOD); +} + +void cb_uartTxDone(void) { + + app_vars.uart_lastTxByteIndex++; + if (app_vars.uart_lastTxByteIndexhhh', bytes(rawFrame[:-2])) + + # debug info + output = 'gyr_x={0:<6} gyr_y={1:<6} gyr_z={2:<6}'.format( + x_gyro, + y_gyro, + z_gyro + ) + + rawFrame = [] + + # GYRO_RESOLUATION_0 = 16.4 + GYRO_RESOLUATION_1 = 32.8 + # GYRO_RESOLUATION_2 = 65.6 + # GYRO_RESOLUATION_3 = 131.2 + + # GYRO_RESOLUATION_4 = 264.4 + gyro_reso = GYRO_RESOLUATION_1 + DATA_INTERVAL = 0.0625 + + x_gyro = DATA_INTERVAL*float(x_gyro)/float(gyro_reso) + y_gyro = DATA_INTERVAL*float(y_gyro)/float(gyro_reso) + z_gyro = DATA_INTERVAL*float(z_gyro)/float(gyro_reso) + + # Rotate the cube based on gyroscope measurements + glRotatef(x_gyro, 1, 0, 0) + glRotatef(y_gyro, 0, 1, 0) + glRotatef(z_gyro, 0, 0, 1) + + glClear(GL_COLOR_BUFFER_BIT | GL_DEPTH_BUFFER_BIT) + draw_cube() + pygame.display.flip() + pygame.time.wait(10) + + # Close the serial port when finished + ser.close() + +if __name__ == '__main__': + main() diff --git a/projects/nrf52840/README.md b/projects/nrf52840_dk/README.md similarity index 100% rename from projects/nrf52840/README.md rename to projects/nrf52840_dk/README.md diff --git a/projects/nrf52840/SConscript b/projects/nrf52840_dk/SConscript similarity index 100% rename from projects/nrf52840/SConscript rename to projects/nrf52840_dk/SConscript diff --git a/projects/nrf52840/SConscript.env b/projects/nrf52840_dk/SConscript.env similarity index 100% rename from projects/nrf52840/SConscript.env rename to projects/nrf52840_dk/SConscript.env diff --git a/projects/nrf52840/01bsp_radio_ble/flash_placement.xml b/projects/nrf52840_dk/flash_placement.xml similarity index 76% rename from projects/nrf52840/01bsp_radio_ble/flash_placement.xml rename to projects/nrf52840_dk/flash_placement.xml index ec73e42550..b2d0b3a96c 100644 --- a/projects/nrf52840/01bsp_radio_ble/flash_placement.xml +++ b/projects/nrf52840_dk/flash_placement.xml @@ -1,36 +1,38 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/nrf52840_dk/nrf52840_dk.emProject b/projects/nrf52840_dk/nrf52840_dk.emProject new file mode 100644 index 0000000000..e19faf7477 --- /dev/null +++ b/projects/nrf52840_dk/nrf52840_dk.emProject @@ -0,0 +1,719 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +