From fd111b8efaec47008fdc9cb865545fe01be751f3 Mon Sep 17 00:00:00 2001
From: alaindargelas <alain.dargelas@gmail.com>
Date: Sat, 29 Jun 2024 11:21:30 -0700
Subject: [PATCH 1/2] VHDL buf writer, non determ techmap

---
 yosys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/yosys b/yosys
index 5b242fb54..44af79f65 160000
--- a/yosys
+++ b/yosys
@@ -1 +1 @@
-Subproject commit 5b242fb54ec78451b40a2608b9fec5aada73e588
+Subproject commit 44af79f6570f812d9fa4c94eceacf560dea704ac

From 8bf7c967a8db1994d73c4768239ad462804c43b1 Mon Sep 17 00:00:00 2001
From: alaindargelas <alaindargelas@users.noreply.github.com>
Date: Sat, 29 Jun 2024 18:22:25 +0000
Subject: [PATCH 2/2] Incremented patch version

---
 CMakeLists.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index f2afe0709..fbeb74b21 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -16,7 +16,7 @@ set(VERSION_MAJOR 0)
 set(VERSION_MINOR 0)
 
 
-set(VERSION_PATCH 338)
+set(VERSION_PATCH 339)
 
 
 project(yosys_verific_rs)