gimlet release

Remove unconnected QSPI reset line (#1812)

This is a legacy pin from the original Gemini Bringup Board, and isn't
actually connected on Sidecar (PF5 is `V1P8_PG_A2`, which we're
presumably fighting against)

sidecar release

Add a long timeout for setting boot component

Setting the stage0 boot component involves writing to flash which
requires a longer timeout

psc release

Add a long timeout for setting boot component

Setting the stage0 boot component involves writing to flash which
requires a longer timeout

gimlet release

Add a long timeout for setting boot component

Setting the stage0 boot component involves writing to flash which
requires a longer timeout

sidecar release

Allow SP to set active slot

It's useful for the SP to be able to change the active slot.
Pull this through. The final finish step no longer implicitly
swaps the bank.

psc release

Allow SP to set active slot

It's useful for the SP to be able to change the active slot.
Pull this through. The final finish step no longer implicitly
swaps the bank.

gimlet release

Allow SP to set active slot

It's useful for the SP to be able to change the active slot.
Pull this through. The final finish step no longer implicitly
swaps the bank.

psc release

What's Changed

• Refresh FPGAs after toolchain bump by @Aaron-Hartwig in #1782
• transceivers: convert to counted_ringbufs by @Aaron-Hartwig in #1780
• transceivers: fix I2C read bug by @Aaron-Hartwig in #1787
• psc-seq: don't repeat StickyFault every time. by @cbiffle in #1799
• psc: turn PSU back on even if it says !OK by @cbiffle in #1801
• psc: allow PSUs a grace period before requiring OK after enable. by @cbiffle in #1802

Full Changelog: psc-v1.0.17...psc-v1.0.18

sidecar release

transceivers: fix I2C read bug (#1787)

#1768 did not properly account for the FIFO behavior of the FPGA's data
buffers. The "check the status byte" portion of the loop happened
outside the part where we read the buffer, and since the buffer was just
memory-mapped registers it could be repeatedly without consequence.
Since the data was now in a FIFO, I was inadvertently draining the FIFO
before the transaction was done. This PR consolidates the "is I2C done
yet" logic into the `get_i2c_status_and_read_buffer` so calling code can
just deal with the status register and the data buffer.

Fixes #1786

sidecar release

Refresh FPGAs after toolchain bump (#1782)

We updated the FPGA toolchain in
https://github.com/oxidecomputer/quartz/pull/150. This refreshes the
images we have as part of our applications with fresh ones from CI.

cc: @nathanaelhuffman @arjenroodselaar