This repository presents a 10-bit Potentiometric Digital to Analog Converter.
The target is to design a 10-bit potentiometric DAC with 3.3v analog voltage and 1 off-chip external reference using the osu180nm technology node. Here are the specifications from VSD Corporation Pvt. Ltd.
A DAC is a building block required to convert digital data into analog.
- 1. Introduction to Potentiometric Digital to Analog Converter
- 2. Potentiometric DAC Architecture Design
- 3. Specification List
- 4. EDA Tools Used
- 5. Pre-layout and Simulations
- A. Switch
- B. 2-Bit DAC subcircuit
- C. 3-Bit DAC subcircuit
- D. 4-Bit DAC subcircuit
- E. 5-Bit DAC subcircuit
- F. 6-Bit DAC subcircuit
- G. 7-Bit DAC subcircuit
- H. 8-Bit DAC subcircuit
- I. 9-Bit DAC subcircuit
- J. 10-Bit-DAC
- Vout v/s Digital Code Graph for 10-Bit DAC
- INL(LSB) v/s Digital Code Graph for 10-Bit DAC
- DNL(LSB) v/s Digital Code Graph for 10-Bit DAC
- 6. Layout and Simulations
- A. Switch Layout
- B. Resistor Layout
- C. Capacitor Layout
- D. 2-Bit DAC Subcircuit Layout
- E. 3-Bit DAC Subcircuit Layout
- F. 4-Bit DAC Subcircuit Layout
- G. 5-Bit DAC Subcircuit Layout
- H. 6-Bit DAC Subcircuit Layout
- I. 7-Bit DAC Subcircuit Layout
- J. 8-Bit DAC Subcircuit Layout
- K. 9-Bit DAC Subcircuit Layout
- L. 10-Bit-DAC Layout
- Vout v/s Digital Code Graph for 10-Bit DAC
- INL(LSB) v/s Digital Code Graph for 10-Bit DAC
- DNL(LSB) v/s Digital Code Graph for 10-Bit DAC
- 7. Instructions to get started with the design
- 8. Author
- 9. Acknowledgments
- 10. Contact Information -
The basic idea is to divide the voltage into N different voltage values in the range of Vref+ and Vref- for an N-Bit DAC. The design used here to achieve this is the simple resistor string DAC which consists of resistors in series. These resistors are then connected to various switches in such a fashion that it routes the exact voltage to the output.
The problem of the largeness of the circuit is reduced by building hierarchical subcircuits of switch, 2 Bit, 3 Bit, 4 Bit,....., 9 Bit DAC, and then two 9 Bit DAC is used to build the 10-Bit potentiometric DAC.
Have a look at the simplified architecture for potentiometric-DAC given below
Given below is the block diagram of the DAC -
| Parameter | Description | Min | Type | Max | Unit | Condition |
|---|---|---|---|---|---|---|
| RL | Load resistance | 50 | Mohm | T=-40 to 85C | ||
| CL | Load capacitance | 1 | pF | T=-40 to 85C | ||
| VDDA | Analog supply | 3.3 | V | T=-40 to 85C | ||
| VDD | Digital supply voltage | 1.8 | V | T=-40 to 85C | ||
| VREFH | Reference voltage high | 3.3 | V | T=-40 to 85C | ||
| VREFL | Reference voltage low | 0 | V | T=-40 to 85C | ||
| RES | Resolution | 10 | bit | T=27C | ||
| VFS | Full Scale Voltage | 0 | 3.291627 | V | T=27C |
| Parameter | Pre-layout (LSB) | Post-Layout (LSB) |
|---|---|---|
| DNL | -0.999893345 LSB to 2.03065020 LSB | -1.182952606 LSB to 2.380283181 LSB |
| INL | -1.953038429 LSB to 0.527216491 LSB | -3.698306813 LSB to 0.181125461 LSB |
The design has been built using open-source EDA tools. The library used is osu180nm.
I have used eSim to build schematic, ngSpice to run simulations and verify the circuit. Magic has been used to lay-out the circuit.
The complete circuit of 10-Bit potentiometric DAC is built hierarchically using the following subcircuits.
The source details at Vref+ = 3.3V and Vref- = 0V are given here.
.png)
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For pre-layout simulation please follow this.
value = 253 Ω
value = 3.12nF
add
device capacitor None glass poly,pc 9000 73000
in the #devices section inside the osu180nm.tech node.
As the capacitor layer, or poly2 none are present in osu180nm, the capacitor can not be built in a straight forward way using the osu PDK.The above given modifications in the technology node were done to simulate the characteristics of the circuit. Here, defining the capacitor in a certain manner gives the required characteristics in the circuit.
size = 635.1 x 684.8 microns
The source details are here.
-postLayout.png)
-postLayout.png)
For post-layout simulation please follow this.
- Download eSim from the given website.
- Download this folder.
- Keep the contents of subcircuits folder inside the eSim subcircuits folder (C:\FOSSEE\eSim\library\SubcircuitLibrary).
- Store the libary files in the eSim User Library section (C:\FOSSEE\eSim\library\deviceModelLibrary\User Libraries).
- Open the 10_bit_dac project in eSim kept in Pre-Layout Simulation folder .
- Run the schematic, extract spice netlist, and simulate the design using ngSpice to view the output. You should get the output as shown above in the figure.
The simulation may take more than an hour to complete. Kindly keep patience.
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Download Magic from the given website for Linux and Mac. For windows, you will have to install Cygwin Terminal and then Magic can run on the Windows platform also. Kindly look here for Windows operating system.
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Download this folder or complete repository.
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Go to the specific directory to run the Magic file.
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To open the 10BitDac.mag with osu180nm.tech using terminal type - magic -T osu180nm.tech 10BitDac
-
To extract the spice netlist type in tkcon window -
extract all ext2spice 10BitDac.ext -
After you get the extracted netlist, to add the contents of this file at the beginning of the spice file, and also add the contents of this file at the end of the spice file to append the pmos,nmos libraries, and simulation parameters.
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Now, to simulate the layout, run ngspice in another terminal using -
ngspice 10BitDac.spice -
You should get the output as shown above in the figure.
- Ashutosh Sharma, B.Tech, Electronics & Communication Engineering, IIITD&M Kurnool
- Kunal Ghosh, Co-founder VSD Corp. Pvt. Ltd.
- Philipp Gühring, Software Architect, LibreSilicon Association.
I would also like to thank research fellows for extending their help and guidance during the research internship program. Many Thanks to
- Ankur Sah, M.tech Embedded Systems, NIT Jamshedpur, [email protected]
- Nikhil Shinde, B.E., KJSIEIT Mumbai, [email protected]
- Shubham Negi, B.Tech. Computer Engineering, IIITD&M Kurnool, [email protected]
- Sheryl Serrao, Undergraduate Student, Mumbai University, [email protected]
- Ashutosh Sharma, B.Tech, Electronics, and Communication Engineering, IIITD&M Kurnool, [email protected]
- Kunal Ghosh, Co-founder, VSD Corp. Pvt. Ltd. - [email protected]
- Philipp Gühring, Software Architect, LibreSilicon Association - [email protected]