From 99a43283be621d72dd81ccb7bfa22c672cd0a95a Mon Sep 17 00:00:00 2001
From: Mikhail Nitenko <mnitenko@gmail.com>
Date: Thu, 6 Jun 2024 21:40:13 +0000
Subject: [PATCH] unittests/bextr: add SrcSize tests

dougallj mentioned that adding these tests might expose
a bug in bextr. Since bextr implementation was changed
apparently it now works correctly, that's good.
---
 unittests/ASM/VEX/bextr.asm | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/unittests/ASM/VEX/bextr.asm b/unittests/ASM/VEX/bextr.asm
index cab0b6b5af..d9f4be2f75 100644
--- a/unittests/ASM/VEX/bextr.asm
+++ b/unittests/ASM/VEX/bextr.asm
@@ -4,6 +4,8 @@
       "RBX": "0",
       "RDX": "0xFF",
       "RSI": "0",
+      "R8" : "0xDEADBEEFDEADBEEF",
+      "R9" : "0xDEADBEEF",
       "R14": "0x7F",
       "R15": "0x838"
   },
@@ -21,6 +23,11 @@ mov rbx, -1
 mov rcx, 0
 bextr rbx, rbx, rcx
 
+; Extraction with 'SrcSize' bits should get the unchanged register
+mov r8, 0xDEADBEEFDEADBEEF
+mov r9, 16384              ; Start at 0 extract 64 bits
+bextr r8, r8, r9           ; r8 should stay the same
+
 ; Same tests as above but with 32-bit registers
 
 ; General extraction
@@ -33,4 +40,9 @@ mov rsi, -1
 mov rdi, 0
 bextr esi, esi, edi
 
+; Extraction with 'SrcSize' bits should get the unchanged register
+mov r9, 0xDEADBEEFDEADBEEF
+mov r10, 8192               ; Start at 0 extract 32 bits
+bextr r9d, r9d, r10d        ; r9 should become 0xDEADBEEF (and r9d stays the same)
+
 hlt