diff --git a/FEXCore/Source/Interface/Core/Frontend.cpp b/FEXCore/Source/Interface/Core/Frontend.cpp
index 1e286f0f18..70e4d5f699 100644
--- a/FEXCore/Source/Interface/Core/Frontend.cpp
+++ b/FEXCore/Source/Interface/Core/Frontend.cpp
@@ -632,7 +632,6 @@ bool Decoder::NormalOpHeader(const FEXCore::X86Tables::X86InstInfo* Info, uint16
     uint16_t X87Op = ((Op - 0xD8) << 8) | ModRMByte;
     return NormalOp(&X87Ops[X87Op], X87Op);
   } else if (Info->Type == FEXCore::X86Tables::TYPE_VEX_TABLE_PREFIX) {
-    FEXCORE_TELEMETRY_SET(VEXOpTelem, 1);
     uint16_t map_select = 1;
     uint16_t pp = 0;
     const uint8_t Byte1 = ReadByte();
@@ -678,7 +677,6 @@ bool Decoder::NormalOpHeader(const FEXCore::X86Tables::X86InstInfo* Info, uint16
     FEXCore::X86Tables::X86InstInfo* LocalInfo = &VEXTableOps[Op];
 
     if (LocalInfo->Type >= FEXCore::X86Tables::TYPE_VEX_GROUP_12 && LocalInfo->Type <= FEXCore::X86Tables::TYPE_VEX_GROUP_17) {
-      FEXCORE_TELEMETRY_SET(VEXOpTelem, 1);
       // We have ModRM
       uint8_t ModRMByte = ReadByte();
       DecodeInst->ModRM = ModRMByte;
diff --git a/FEXCore/Source/Interface/Core/Frontend.h b/FEXCore/Source/Interface/Core/Frontend.h
index 6a54142a02..6b08f522e5 100644
--- a/FEXCore/Source/Interface/Core/Frontend.h
+++ b/FEXCore/Source/Interface/Core/Frontend.h
@@ -120,7 +120,6 @@ class Decoder final {
 
   const uint8_t* AdjustAddrForSpecialRegion(const uint8_t* _InstStream, uint64_t EntryPoint, uint64_t RIP);
 
-  FEXCORE_TELEMETRY_INIT(VEXOpTelem, TYPE_USES_VEX_OPS);
   FEXCORE_TELEMETRY_INIT(EVEXOpTelem, TYPE_USES_EVEX_OPS);
 };
 } // namespace FEXCore::Frontend
diff --git a/FEXCore/Source/Utils/Telemetry.cpp b/FEXCore/Source/Utils/Telemetry.cpp
index 78bb7b8bd3..62d173005c 100644
--- a/FEXCore/Source/Utils/Telemetry.cpp
+++ b/FEXCore/Source/Utils/Telemetry.cpp
@@ -20,7 +20,6 @@ std::array<Value, FEXCore::Telemetry::TelemetryType::TYPE_LAST> TelemetryValues
 const std::array<std::string_view, FEXCore::Telemetry::TelemetryType::TYPE_LAST> TelemetryNames {
   "64byte Split Locks",
   "16byte Split atomics",
-  "VEX instructions (AVX)",
   "EVEX instructions (AVX512)",
   "16bit CAS Tear",
   "32bit CAS Tear",
diff --git a/FEXCore/include/FEXCore/Utils/Telemetry.h b/FEXCore/include/FEXCore/Utils/Telemetry.h
index 081dd8afc6..2474389650 100644
--- a/FEXCore/include/FEXCore/Utils/Telemetry.h
+++ b/FEXCore/include/FEXCore/Utils/Telemetry.h
@@ -12,7 +12,6 @@ namespace FEXCore::Telemetry {
 enum TelemetryType {
   TYPE_HAS_SPLIT_LOCKS,
   TYPE_16BYTE_SPLIT,
-  TYPE_USES_VEX_OPS,
   TYPE_USES_EVEX_OPS,
   TYPE_CAS_16BIT_TEAR,
   TYPE_CAS_32BIT_TEAR,
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1.json b/unittests/InstructionCountCI/AVX128/VEX_map1.json
index 16ce2fae8d..5087bf69a0 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map1.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map1.json
@@ -516,7 +516,7 @@
       ],
       "ExpectedArm64ASM": [
         "ushr v2.4s, v16.4s, #31",
-        "ldr q3, [x28, #2464]",
+        "ldr q3, [x28, #2448]",
         "ushl v2.4s, v2.4s, v3.4s",
         "addv s2, v2.4s",
         "mov w4, v2.s[0]"
@@ -530,7 +530,7 @@
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #16]",
         "ushr v3.4s, v16.4s, #31",
-        "ldr q4, [x28, #2464]",
+        "ldr q4, [x28, #2448]",
         "ushl v3.4s, v3.4s, v4.4s",
         "addv s3, v3.4s",
         "mov w20, v3.s[0]",
@@ -4054,7 +4054,7 @@
         "Map 1 0b01 0xd0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2368]",
+        "ldr q2, [x28, #2352]",
         "eor v2.16b, v18.16b, v2.16b",
         "fadd v16.2d, v17.2d, v2.2d",
         "movi v2.2d, #0x0",
@@ -4069,7 +4069,7 @@
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #32]",
         "ldr q3, [x28, #48]",
-        "ldr q4, [x28, #2368]",
+        "ldr q4, [x28, #2352]",
         "eor v5.16b, v18.16b, v4.16b",
         "fadd v16.2d, v17.2d, v5.2d",
         "eor v3.16b, v3.16b, v4.16b",
@@ -4083,7 +4083,7 @@
         "Map 1 0b11 0xd0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2336]",
+        "ldr q2, [x28, #2320]",
         "eor v2.16b, v18.16b, v2.16b",
         "fadd v16.4s, v17.4s, v2.4s",
         "movi v2.2d, #0x0",
@@ -4098,7 +4098,7 @@
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #32]",
         "ldr q3, [x28, #48]",
-        "ldr q4, [x28, #2336]",
+        "ldr q4, [x28, #2320]",
         "eor v5.16b, v18.16b, v4.16b",
         "fadd v16.4s, v17.4s, v5.4s",
         "eor v3.16b, v3.16b, v4.16b",
@@ -4274,7 +4274,7 @@
         "Map 1 0b01 0xd7 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2592]",
+        "ldr q2, [x28, #2576]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",
@@ -4290,7 +4290,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #16]",
-        "ldr q3, [x28, #2592]",
+        "ldr q3, [x28, #2576]",
         "cmlt v4.16b, v16.16b, #0",
         "and v4.16b, v4.16b, v3.16b",
         "addp v4.16b, v4.16b, v4.16b",
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2.json b/unittests/InstructionCountCI/AVX128/VEX_map2.json
index 7ab36cf83b..7ca7244e89 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map2.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map2.json
@@ -1964,7 +1964,7 @@
         "Map 2 0b01 0x41 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2304]",
+        "ldr q2, [x28, #2288]",
         "zip1 v3.8h, v2.8h, v17.8h",
         "zip2 v2.8h, v2.8h, v17.8h",
         "umin v2.4s, v3.4s, v2.4s",
@@ -4548,7 +4548,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2336]",
+        "ldr q2, [x28, #2320]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -4566,7 +4566,7 @@
         "ldr q2, [x28, #16]",
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
-        "ldr q5, [x28, #2336]",
+        "ldr q5, [x28, #2320]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -4582,7 +4582,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2368]",
+        "ldr q2, [x28, #2352]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -4600,7 +4600,7 @@
         "ldr q2, [x28, #16]",
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
-        "ldr q5, [x28, #2368]",
+        "ldr q5, [x28, #2352]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -4616,7 +4616,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2400]",
+        "ldr q2, [x28, #2384]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -4634,7 +4634,7 @@
         "ldr q2, [x28, #16]",
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
-        "ldr q5, [x28, #2400]",
+        "ldr q5, [x28, #2384]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -4650,7 +4650,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2432]",
+        "ldr q2, [x28, #2416]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -4668,7 +4668,7 @@
         "ldr q2, [x28, #16]",
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
-        "ldr q5, [x28, #2432]",
+        "ldr q5, [x28, #2416]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -5656,7 +5656,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2336]",
+        "ldr q2, [x28, #2320]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -5674,7 +5674,7 @@
         "ldr q2, [x28, #16]",
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
-        "ldr q5, [x28, #2336]",
+        "ldr q5, [x28, #2320]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -5690,7 +5690,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2368]",
+        "ldr q2, [x28, #2352]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -5708,7 +5708,7 @@
         "ldr q2, [x28, #16]",
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
-        "ldr q5, [x28, #2368]",
+        "ldr q5, [x28, #2352]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -5724,7 +5724,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2400]",
+        "ldr q2, [x28, #2384]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -5742,7 +5742,7 @@
         "ldr q2, [x28, #16]",
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
-        "ldr q5, [x28, #2400]",
+        "ldr q5, [x28, #2384]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -5758,7 +5758,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2432]",
+        "ldr q2, [x28, #2416]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -5776,7 +5776,7 @@
         "ldr q2, [x28, #16]",
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
-        "ldr q5, [x28, #2432]",
+        "ldr q5, [x28, #2416]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -5792,7 +5792,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2336]",
+        "ldr q2, [x28, #2320]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -5809,7 +5809,7 @@
         "ldr q2, [x28, #16]",
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
-        "ldr q5, [x28, #2336]",
+        "ldr q5, [x28, #2320]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -5824,7 +5824,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2368]",
+        "ldr q2, [x28, #2352]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -5841,7 +5841,7 @@
         "ldr q2, [x28, #16]",
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
-        "ldr q5, [x28, #2368]",
+        "ldr q5, [x28, #2352]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -5856,7 +5856,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2400]",
+        "ldr q2, [x28, #2384]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -5873,7 +5873,7 @@
         "ldr q2, [x28, #16]",
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
-        "ldr q5, [x28, #2400]",
+        "ldr q5, [x28, #2384]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -5888,7 +5888,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2432]",
+        "ldr q2, [x28, #2416]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -5905,7 +5905,7 @@
         "ldr q2, [x28, #16]",
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
-        "ldr q5, [x28, #2432]",
+        "ldr q5, [x28, #2416]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.2d, v17.2d, v18.2d",
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json b/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json
index 69fdce981b..ab8137ee49 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json
@@ -2850,7 +2850,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2336]",
+        "ldr q2, [x28, #2320]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -2868,7 +2868,7 @@
         "ldr q2, [x28, #16]",
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
-        "ldr q5, [x28, #2336]",
+        "ldr q5, [x28, #2320]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -2884,7 +2884,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2368]",
+        "ldr q2, [x28, #2352]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -2902,7 +2902,7 @@
         "ldr q2, [x28, #16]",
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
-        "ldr q5, [x28, #2368]",
+        "ldr q5, [x28, #2352]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -2918,7 +2918,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2400]",
+        "ldr q2, [x28, #2384]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -2936,7 +2936,7 @@
         "ldr q2, [x28, #16]",
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
-        "ldr q5, [x28, #2400]",
+        "ldr q5, [x28, #2384]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -2952,7 +2952,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2432]",
+        "ldr q2, [x28, #2416]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -2970,7 +2970,7 @@
         "ldr q2, [x28, #16]",
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
-        "ldr q5, [x28, #2432]",
+        "ldr q5, [x28, #2416]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -3938,7 +3938,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2336]",
+        "ldr q2, [x28, #2320]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -3956,7 +3956,7 @@
         "ldr q2, [x28, #16]",
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
-        "ldr q5, [x28, #2336]",
+        "ldr q5, [x28, #2320]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -3972,7 +3972,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2368]",
+        "ldr q2, [x28, #2352]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -3990,7 +3990,7 @@
         "ldr q2, [x28, #16]",
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
-        "ldr q5, [x28, #2368]",
+        "ldr q5, [x28, #2352]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -4006,7 +4006,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2400]",
+        "ldr q2, [x28, #2384]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -4024,7 +4024,7 @@
         "ldr q2, [x28, #16]",
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
-        "ldr q5, [x28, #2400]",
+        "ldr q5, [x28, #2384]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -4040,7 +4040,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2432]",
+        "ldr q2, [x28, #2416]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -4058,7 +4058,7 @@
         "ldr q2, [x28, #16]",
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
-        "ldr q5, [x28, #2432]",
+        "ldr q5, [x28, #2416]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -4074,7 +4074,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2336]",
+        "ldr q2, [x28, #2320]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -4091,7 +4091,7 @@
         "ldr q2, [x28, #16]",
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
-        "ldr q5, [x28, #2336]",
+        "ldr q5, [x28, #2320]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -4106,7 +4106,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2368]",
+        "ldr q2, [x28, #2352]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -4123,7 +4123,7 @@
         "ldr q2, [x28, #16]",
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
-        "ldr q5, [x28, #2368]",
+        "ldr q5, [x28, #2352]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -4138,7 +4138,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2400]",
+        "ldr q2, [x28, #2384]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -4155,7 +4155,7 @@
         "ldr q2, [x28, #16]",
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
-        "ldr q5, [x28, #2400]",
+        "ldr q5, [x28, #2384]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -4170,7 +4170,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2432]",
+        "ldr q2, [x28, #2416]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -4187,7 +4187,7 @@
         "ldr q2, [x28, #16]",
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
-        "ldr q5, [x28, #2432]",
+        "ldr q5, [x28, #2416]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.2d, v17.2d, v18.2d",
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map3.json b/unittests/InstructionCountCI/AVX128/VEX_map3.json
index 2fabf540ec..237572f5af 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map3.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map3.json
@@ -3715,7 +3715,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -3730,7 +3730,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -3745,7 +3745,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -3760,7 +3760,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -3775,7 +3775,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -3790,7 +3790,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -3805,7 +3805,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -3820,7 +3820,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -3835,7 +3835,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -3850,7 +3850,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -3865,7 +3865,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -3880,7 +3880,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -3895,7 +3895,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -3910,7 +3910,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -3925,7 +3925,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -3940,7 +3940,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -3955,7 +3955,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -3970,7 +3970,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -3985,7 +3985,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -4000,7 +4000,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -4015,7 +4015,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -4030,7 +4030,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -4045,7 +4045,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -4060,7 +4060,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -4075,7 +4075,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -4090,7 +4090,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -4105,7 +4105,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -4120,7 +4120,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -4135,7 +4135,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -4150,7 +4150,7 @@
         "str x20, [x28, #272]",
         "mov w1, #0x401",
         "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2240]",
+        "ldr x0, [x28, #2232]",
         "br x0"
       ]
     },
@@ -4161,7 +4161,7 @@
       ],
       "ExpectedArm64ASM": [
         "movi v2.2d, #0x0",
-        "ldr q3, [x28, #2480]",
+        "ldr q3, [x28, #2464]",
         "mov v16.16b, v17.16b",
         "unimplemented (Unimplemented)",
         "tbl v16.16b, {v16.16b}, v3.16b",
@@ -4175,7 +4175,7 @@
       ],
       "ExpectedArm64ASM": [
         "movi v2.2d, #0x0",
-        "ldr q3, [x28, #2480]",
+        "ldr q3, [x28, #2464]",
         "mov v16.16b, v17.16b",
         "unimplemented (Unimplemented)",
         "tbl v16.16b, {v16.16b}, v3.16b",
diff --git a/unittests/InstructionCountCI/Crypto/H0F3A.json b/unittests/InstructionCountCI/Crypto/H0F3A.json
index 23af16e4dc..ff742c7dc2 100644
--- a/unittests/InstructionCountCI/Crypto/H0F3A.json
+++ b/unittests/InstructionCountCI/Crypto/H0F3A.json
@@ -55,7 +55,7 @@
         "0x66 0x0f 0x3a 0xdf"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2480]",
+        "ldr q2, [x28, #2464]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
         "unimplemented (Unimplemented)",
@@ -68,7 +68,7 @@
         "0x66 0x0f 0x3a 0xdf"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2480]",
+        "ldr q2, [x28, #2464]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
         "unimplemented (Unimplemented)",
diff --git a/unittests/InstructionCountCI/FlagM/Secondary.json b/unittests/InstructionCountCI/FlagM/Secondary.json
index 25525e296d..6311629e1e 100644
--- a/unittests/InstructionCountCI/FlagM/Secondary.json
+++ b/unittests/InstructionCountCI/FlagM/Secondary.json
@@ -1610,7 +1610,7 @@
       "Comment": "0x0f 0xd7",
       "ExpectedArm64ASM": [
         "ldr d2, [x28, #1040]",
-        "ldr d3, [x28, #2592]",
+        "ldr d3, [x28, #2576]",
         "cmlt v2.16b, v2.16b, #0",
         "and v2.16b, v2.16b, v3.16b",
         "addp v2.16b, v2.16b, v2.16b",
diff --git a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json
index 5d817d7c2a..401d7b4bb3 100644
--- a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json
+++ b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json
@@ -39,7 +39,7 @@
       "ExpectedInstructionCount": 7,
       "Comment": "0x66 0x0f 0xd7",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2592]",
+        "ldr q2, [x28, #2576]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",
diff --git a/unittests/InstructionCountCI/FlagM/VEX_map1.json b/unittests/InstructionCountCI/FlagM/VEX_map1.json
index 9856994449..b3b689998b 100644
--- a/unittests/InstructionCountCI/FlagM/VEX_map1.json
+++ b/unittests/InstructionCountCI/FlagM/VEX_map1.json
@@ -72,7 +72,7 @@
         "Map 1 0b01 0xd7 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2592]",
+        "ldr q2, [x28, #2576]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",
diff --git a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json
index 4f52eecd85..87fbb713f3 100644
--- a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json
+++ b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json
@@ -4470,7 +4470,7 @@
         "add w22, w20, w22",
         "str w20, [x8, #-4]!",
         "strb w21, [x28, #1298]",
-        "ldr x0, [x28, #2280]",
+        "ldr x0, [x28, #2272]",
         "and x3, x22, #0xfffff",
         "add x0, x0, x3, lsl #4",
         "ldp x1, x0, [x0]"
@@ -5725,7 +5725,7 @@
         "add w22, w20, w22",
         "str w20, [x8, #-4]!",
         "strb w21, [x28, #1298]",
-        "ldr x0, [x28, #2280]",
+        "ldr x0, [x28, #2272]",
         "and x3, x22, #0xfffff",
         "add x0, x0, x3, lsl #4",
         "ldp x1, x0, [x0]"
@@ -8273,7 +8273,7 @@
         "add w22, w20, w22",
         "str w20, [x8, #-4]!",
         "strb w21, [x28, #1298]",
-        "ldr x0, [x28, #2280]",
+        "ldr x0, [x28, #2272]",
         "and x3, x22, #0xfffff",
         "add x0, x0, x3, lsl #4",
         "ldp x1, x0, [x0]"
@@ -8563,7 +8563,7 @@
         "add w22, w20, w22",
         "str w20, [x8, #-4]!",
         "strb w21, [x28, #1298]",
-        "ldr x0, [x28, #2280]",
+        "ldr x0, [x28, #2272]",
         "and x3, x22, #0xfffff",
         "add x0, x0, x3, lsl #4",
         "ldp x1, x0, [x0]"
@@ -8721,7 +8721,7 @@
         "movk w21, #0x1, lsl #16",
         "add w21, w20, w21",
         "str w20, [x8, #-4]!",
-        "ldr x0, [x28, #2280]",
+        "ldr x0, [x28, #2272]",
         "and x3, x21, #0xfffff",
         "add x0, x0, x3, lsl #4",
         "ldp x1, x0, [x0]"
diff --git a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json
index 6d463d0f92..d2bd0a5a4e 100644
--- a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json
+++ b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json
@@ -79289,7 +79289,7 @@
         "add w22, w20, w22",
         "str w20, [x8, #-4]!",
         "strb w21, [x28, #1298]",
-        "ldr x0, [x28, #2280]",
+        "ldr x0, [x28, #2272]",
         "and x3, x22, #0xfffff",
         "add x0, x0, x3, lsl #4",
         "ldp x1, x0, [x0]"
@@ -81422,7 +81422,7 @@
         "movk w21, #0x41, lsl #16",
         "add w21, w20, w21",
         "str w20, [x8, #-4]!",
-        "ldr x0, [x28, #2280]",
+        "ldr x0, [x28, #2272]",
         "and x3, x21, #0xfffff",
         "add x0, x0, x3, lsl #4",
         "ldp x1, x0, [x0]"
@@ -81887,7 +81887,7 @@
         "lsl w23, w21, w20",
         "orr w22, w22, w23",
         "strb w20, [x28, #1019]",
-        "ldr q2, [x28, #2624]",
+        "ldr q2, [x28, #2608]",
         "add x0, x28, x20, lsl #4",
         "str q2, [x0, #1040]",
         "str w5, [x8, #56]",
@@ -82383,7 +82383,7 @@
         "add w22, w20, w22",
         "str w20, [x8, #-4]!",
         "strb w21, [x28, #1298]",
-        "ldr x0, [x28, #2280]",
+        "ldr x0, [x28, #2272]",
         "and x3, x22, #0xfffff",
         "add x0, x0, x3, lsl #4",
         "ldp x1, x0, [x0]"
@@ -82776,7 +82776,7 @@
         "add w22, w20, w22",
         "str w20, [x8, #-4]!",
         "strb w21, [x28, #1298]",
-        "ldr x0, [x28, #2280]",
+        "ldr x0, [x28, #2272]",
         "and x3, x22, #0xfffff",
         "add x0, x0, x3, lsl #4",
         "ldp x1, x0, [x0]"
@@ -99732,7 +99732,7 @@
         "add w22, w20, w22",
         "str w20, [x8, #-4]!",
         "strb w21, [x28, #1298]",
-        "ldr x0, [x28, #2280]",
+        "ldr x0, [x28, #2272]",
         "and x3, x22, #0xfffff",
         "add x0, x0, x3, lsl #4",
         "ldp x1, x0, [x0]"
@@ -101213,7 +101213,7 @@
         "add w22, w20, w22",
         "str w20, [x8, #-4]!",
         "strb w21, [x28, #1298]",
-        "ldr x0, [x28, #2280]",
+        "ldr x0, [x28, #2272]",
         "and x3, x22, #0xfffff",
         "add x0, x0, x3, lsl #4",
         "ldp x1, x0, [x0]"
diff --git a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json
index 1a75160fdc..d6d43341d3 100644
--- a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json
+++ b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json
@@ -39729,7 +39729,7 @@
         "movk w21, #0x819, lsl #16",
         "add w21, w20, w21",
         "str w20, [x8, #-4]!",
-        "ldr x0, [x28, #2280]",
+        "ldr x0, [x28, #2272]",
         "and x3, x21, #0xfffff",
         "add x0, x0, x3, lsl #4",
         "ldp x1, x0, [x0]"
@@ -76408,7 +76408,7 @@
         "add w22, w20, w22",
         "str w20, [x8, #-4]!",
         "strb w21, [x28, #1298]",
-        "ldr x0, [x28, #2280]",
+        "ldr x0, [x28, #2272]",
         "and x3, x22, #0xfffff",
         "add x0, x0, x3, lsl #4",
         "ldp x1, x0, [x0]"
@@ -87836,7 +87836,7 @@
         "add w22, w20, w22",
         "str w20, [x8, #-4]!",
         "strb w21, [x28, #1298]",
-        "ldr x0, [x28, #2280]",
+        "ldr x0, [x28, #2272]",
         "and x3, x22, #0xfffff",
         "add x0, x0, x3, lsl #4",
         "ldp x1, x0, [x0]"
@@ -114213,7 +114213,7 @@
         "add w22, w20, w22",
         "str w20, [x8, #-4]!",
         "strb w21, [x28, #1298]",
-        "ldr x0, [x28, #2280]",
+        "ldr x0, [x28, #2272]",
         "and x3, x22, #0xfffff",
         "add x0, x0, x3, lsl #4",
         "ldp x1, x0, [x0]"
diff --git a/unittests/InstructionCountCI/FlagM/x87.json b/unittests/InstructionCountCI/FlagM/x87.json
index 8e4eb185ab..fdb6f43e7e 100644
--- a/unittests/InstructionCountCI/FlagM/x87.json
+++ b/unittests/InstructionCountCI/FlagM/x87.json
@@ -4529,7 +4529,7 @@
         "lsl w21, w21, w20",
         "orr w21, w22, w21",
         "strb w20, [x28, #1019]",
-        "ldr q2, [x28, #2624]",
+        "ldr q2, [x28, #2608]",
         "add x0, x28, x20, lsl #4",
         "str q2, [x0, #1040]",
         "strb w21, [x28, #1298]"
@@ -4549,7 +4549,7 @@
         "lsl w21, w21, w20",
         "orr w21, w22, w21",
         "strb w20, [x28, #1019]",
-        "ldr q2, [x28, #2640]",
+        "ldr q2, [x28, #2624]",
         "add x0, x28, x20, lsl #4",
         "str q2, [x0, #1040]",
         "strb w21, [x28, #1298]"
@@ -4569,7 +4569,7 @@
         "lsl w21, w21, w20",
         "orr w21, w22, w21",
         "strb w20, [x28, #1019]",
-        "ldr q2, [x28, #2656]",
+        "ldr q2, [x28, #2640]",
         "add x0, x28, x20, lsl #4",
         "str q2, [x0, #1040]",
         "strb w21, [x28, #1298]"
@@ -4589,7 +4589,7 @@
         "lsl w21, w21, w20",
         "orr w21, w22, w21",
         "strb w20, [x28, #1019]",
-        "ldr q2, [x28, #2672]",
+        "ldr q2, [x28, #2656]",
         "add x0, x28, x20, lsl #4",
         "str q2, [x0, #1040]",
         "strb w21, [x28, #1298]"
@@ -4609,7 +4609,7 @@
         "lsl w21, w21, w20",
         "orr w21, w22, w21",
         "strb w20, [x28, #1019]",
-        "ldr q2, [x28, #2688]",
+        "ldr q2, [x28, #2672]",
         "add x0, x28, x20, lsl #4",
         "str q2, [x0, #1040]",
         "strb w21, [x28, #1298]"
@@ -4629,7 +4629,7 @@
         "lsl w21, w21, w20",
         "orr w21, w22, w21",
         "strb w20, [x28, #1019]",
-        "ldr q2, [x28, #2704]",
+        "ldr q2, [x28, #2688]",
         "add x0, x28, x20, lsl #4",
         "str q2, [x0, #1040]",
         "strb w21, [x28, #1298]"
@@ -4793,7 +4793,7 @@
         "eor v2.16b, v2.16b, v2.16b",
         "mov v2.d[0], x0",
         "mov v2.h[4], w1",
-        "ldr q3, [x28, #2624]",
+        "ldr q3, [x28, #2608]",
         "mov w23, #0x0",
         "strb w23, [x28, #1018]",
         "add x0, x28, x20, lsl #4",
@@ -5075,7 +5075,7 @@
         "ldr q2, [x0, #1040]",
         "add x0, x28, x22, lsl #4",
         "ldr q3, [x0, #1040]",
-        "ldr q4, [x28, #2624]",
+        "ldr q4, [x28, #2608]",
         "mrs x0, nzcv",
         "str w0, [x28, #1000]",
         "stp x4, x5, [x28, #280]",
diff --git a/unittests/InstructionCountCI/H0F38.json b/unittests/InstructionCountCI/H0F38.json
index ac23473bac..87bd690faa 100644
--- a/unittests/InstructionCountCI/H0F38.json
+++ b/unittests/InstructionCountCI/H0F38.json
@@ -625,7 +625,7 @@
         "0x66 0x0f 0x38 0x41"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2304]",
+        "ldr q2, [x28, #2288]",
         "zip1 v3.8h, v2.8h, v17.8h",
         "zip2 v2.8h, v2.8h, v17.8h",
         "umin v2.4s, v3.4s, v2.4s",
diff --git a/unittests/InstructionCountCI/H0F3A.json b/unittests/InstructionCountCI/H0F3A.json
index 174dee5149..c938b4d59e 100644
--- a/unittests/InstructionCountCI/H0F3A.json
+++ b/unittests/InstructionCountCI/H0F3A.json
@@ -315,7 +315,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2496]",
+        "ldr q2, [x28, #2480]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -325,7 +325,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2512]",
+        "ldr q2, [x28, #2496]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -344,7 +344,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2528]",
+        "ldr q2, [x28, #2512]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -364,7 +364,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2544]",
+        "ldr q2, [x28, #2528]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -383,7 +383,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2560]",
+        "ldr q2, [x28, #2544]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -393,7 +393,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2576]",
+        "ldr q2, [x28, #2560]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json
index a788757f8b..adc7dea312 100644
--- a/unittests/InstructionCountCI/PrimaryGroup.json
+++ b/unittests/InstructionCountCI/PrimaryGroup.json
@@ -2742,7 +2742,7 @@
         "mov x0, x6",
         "mov x1, x4",
         "mov x2, x7",
-        "ldr x3, [x28, #2752]",
+        "ldr x3, [x28, #2736]",
         "str x30, [sp, #-16]!",
         "blr x3",
         "ldr x30, [sp], #16",
@@ -2753,7 +2753,7 @@
         "mov x0, x6",
         "mov x1, x4",
         "mov x2, x7",
-        "ldr x3, [x28, #2768]",
+        "ldr x3, [x28, #2752]",
         "str x30, [sp, #-16]!",
         "blr x3",
         "ldr x30, [sp], #16",
@@ -2814,7 +2814,7 @@
         "mov x0, x6",
         "mov x1, x4",
         "mov x2, x7",
-        "ldr x3, [x28, #2760]",
+        "ldr x3, [x28, #2744]",
         "str x30, [sp, #-16]!",
         "blr x3",
         "ldr x30, [sp], #16",
@@ -2827,7 +2827,7 @@
         "mov x0, x6",
         "mov x1, x4",
         "mov x2, x7",
-        "ldr x3, [x28, #2776]",
+        "ldr x3, [x28, #2760]",
         "str x30, [sp, #-16]!",
         "blr x3",
         "ldr x30, [sp], #16",
diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json
index 5e8193946d..3b5460d2fa 100644
--- a/unittests/InstructionCountCI/Secondary.json
+++ b/unittests/InstructionCountCI/Secondary.json
@@ -646,7 +646,7 @@
       "Comment": "0x0f 0x50",
       "ExpectedArm64ASM": [
         "ushr v2.4s, v16.4s, #31",
-        "ldr q3, [x28, #2464]",
+        "ldr q3, [x28, #2448]",
         "ushl v2.4s, v2.4s, v3.4s",
         "addv s2, v2.4s",
         "mov w4, v2.s[0]"
@@ -657,7 +657,7 @@
       "Comment": "0x0f 0x50",
       "ExpectedArm64ASM": [
         "ushr v2.4s, v16.4s, #31",
-        "ldr q3, [x28, #2464]",
+        "ldr q3, [x28, #2448]",
         "ushl v2.4s, v2.4s, v3.4s",
         "addv s2, v2.4s",
         "mov w4, v2.s[0]"
@@ -3402,7 +3402,7 @@
       "Comment": "0x0f 0xd7",
       "ExpectedArm64ASM": [
         "ldr d2, [x28, #1040]",
-        "ldr d3, [x28, #2592]",
+        "ldr d3, [x28, #2576]",
         "cmlt v2.16b, v2.16b, #0",
         "and v2.16b, v2.16b, v3.16b",
         "addp v2.16b, v2.16b, v2.16b",
diff --git a/unittests/InstructionCountCI/Secondary_OpSize.json b/unittests/InstructionCountCI/Secondary_OpSize.json
index 849cf00c3e..611c624b94 100644
--- a/unittests/InstructionCountCI/Secondary_OpSize.json
+++ b/unittests/InstructionCountCI/Secondary_OpSize.json
@@ -1192,7 +1192,7 @@
       "ExpectedInstructionCount": 3,
       "Comment": "0x66 0x0f 0xd0",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2368]",
+        "ldr q2, [x28, #2352]",
         "eor v2.16b, v17.16b, v2.16b",
         "fadd v16.2d, v16.2d, v2.2d"
       ]
@@ -1248,7 +1248,7 @@
       "ExpectedInstructionCount": 7,
       "Comment": "0x66 0x0f 0xd7",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2592]",
+        "ldr q2, [x28, #2576]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",
diff --git a/unittests/InstructionCountCI/Secondary_REPNE.json b/unittests/InstructionCountCI/Secondary_REPNE.json
index f6f329babd..5b4e720e1e 100644
--- a/unittests/InstructionCountCI/Secondary_REPNE.json
+++ b/unittests/InstructionCountCI/Secondary_REPNE.json
@@ -453,7 +453,7 @@
       "ExpectedInstructionCount": 3,
       "Comment": "0xf2 0x0f 0xd0",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2336]",
+        "ldr q2, [x28, #2320]",
         "eor v2.16b, v17.16b, v2.16b",
         "fadd v16.4s, v16.4s, v2.4s"
       ]
diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json
index 6cc078f7ad..504802124c 100644
--- a/unittests/InstructionCountCI/VEX_map1.json
+++ b/unittests/InstructionCountCI/VEX_map1.json
@@ -4384,7 +4384,7 @@
         "Map 1 0b01 0xd0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2368]",
+        "ldr q2, [x28, #2352]",
         "eor v2.16b, v18.16b, v2.16b",
         "fadd v16.2d, v17.2d, v2.2d"
       ]
@@ -4407,7 +4407,7 @@
         "Map 1 0b11 0xd0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2336]",
+        "ldr q2, [x28, #2320]",
         "eor v2.16b, v18.16b, v2.16b",
         "fadd v16.4s, v17.4s, v2.4s"
       ]
@@ -4544,7 +4544,7 @@
         "Map 1 0b01 0xd7 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2592]",
+        "ldr q2, [x28, #2576]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",
diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json
index 35da83ddf9..2564150c55 100644
--- a/unittests/InstructionCountCI/VEX_map2.json
+++ b/unittests/InstructionCountCI/VEX_map2.json
@@ -1603,7 +1603,7 @@
         "Map 2 0b01 0x41 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2304]",
+        "ldr q2, [x28, #2288]",
         "zip1 v3.8h, v2.8h, v17.8h",
         "zip2 v2.8h, v2.8h, v17.8h",
         "umin v2.4s, v3.4s, v2.4s",
@@ -3657,7 +3657,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2336]",
+        "ldr q2, [x28, #2320]",
         "eor v2.16b, v17.16b, v2.16b",
         "fmla v2.4s, v16.4s, v18.4s",
         "mov v16.16b, v2.16b"
@@ -3683,7 +3683,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2368]",
+        "ldr q2, [x28, #2352]",
         "eor v2.16b, v17.16b, v2.16b",
         "fmla v2.2d, v16.2d, v18.2d",
         "mov v16.16b, v2.16b"
@@ -3709,7 +3709,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2400]",
+        "ldr q2, [x28, #2384]",
         "eor v2.16b, v17.16b, v2.16b",
         "fmla v2.4s, v16.4s, v18.4s",
         "mov v16.16b, v2.16b"
@@ -3735,7 +3735,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2432]",
+        "ldr q2, [x28, #2416]",
         "eor v2.16b, v17.16b, v2.16b",
         "fmla v2.2d, v16.2d, v18.2d",
         "mov v16.16b, v2.16b"
@@ -4609,7 +4609,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2336]",
+        "ldr q2, [x28, #2320]",
         "eor v2.16b, v18.16b, v2.16b",
         "fmla v2.4s, v17.4s, v16.4s",
         "mov v16.16b, v2.16b"
@@ -4635,7 +4635,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2368]",
+        "ldr q2, [x28, #2352]",
         "eor v2.16b, v18.16b, v2.16b",
         "fmla v2.2d, v17.2d, v16.2d",
         "mov v16.16b, v2.16b"
@@ -4661,7 +4661,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2400]",
+        "ldr q2, [x28, #2384]",
         "eor v2.16b, v18.16b, v2.16b",
         "fmla v2.4s, v17.4s, v16.4s",
         "mov v16.16b, v2.16b"
@@ -4687,7 +4687,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2432]",
+        "ldr q2, [x28, #2416]",
         "eor v2.16b, v18.16b, v2.16b",
         "fmla v2.2d, v17.2d, v16.2d",
         "mov v16.16b, v2.16b"
@@ -4713,7 +4713,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2336]",
+        "ldr q2, [x28, #2320]",
         "eor v2.16b, v16.16b, v2.16b",
         "fmla v2.4s, v17.4s, v18.4s",
         "mov v16.16b, v2.16b"
@@ -4738,7 +4738,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2368]",
+        "ldr q2, [x28, #2352]",
         "eor v2.16b, v16.16b, v2.16b",
         "fmla v2.2d, v17.2d, v18.2d",
         "mov v16.16b, v2.16b"
@@ -4763,7 +4763,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2400]",
+        "ldr q2, [x28, #2384]",
         "eor v2.16b, v16.16b, v2.16b",
         "fmla v2.4s, v17.4s, v18.4s",
         "mov v16.16b, v2.16b"
@@ -4788,7 +4788,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2432]",
+        "ldr q2, [x28, #2416]",
         "eor v2.16b, v16.16b, v2.16b",
         "fmla v2.2d, v17.2d, v18.2d",
         "mov v16.16b, v2.16b"
diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json
index e44df745af..f209785eb9 100644
--- a/unittests/InstructionCountCI/VEX_map3.json
+++ b/unittests/InstructionCountCI/VEX_map3.json
@@ -4862,7 +4862,7 @@
         "Map 3 0b01 0xdf 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2480]",
+        "ldr q2, [x28, #2464]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
         "unimplemented (Unimplemented)",
@@ -4875,7 +4875,7 @@
         "Map 3 0b01 0xdf 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2480]",
+        "ldr q2, [x28, #2464]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
         "unimplemented (Unimplemented)",
diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json
index 0cd7d6fe11..a1b63996b2 100644
--- a/unittests/InstructionCountCI/x87.json
+++ b/unittests/InstructionCountCI/x87.json
@@ -4528,7 +4528,7 @@
         "lsl w21, w21, w20",
         "orr w21, w22, w21",
         "strb w20, [x28, #1019]",
-        "ldr q2, [x28, #2624]",
+        "ldr q2, [x28, #2608]",
         "add x0, x28, x20, lsl #4",
         "str q2, [x0, #1040]",
         "strb w21, [x28, #1298]"
@@ -4548,7 +4548,7 @@
         "lsl w21, w21, w20",
         "orr w21, w22, w21",
         "strb w20, [x28, #1019]",
-        "ldr q2, [x28, #2640]",
+        "ldr q2, [x28, #2624]",
         "add x0, x28, x20, lsl #4",
         "str q2, [x0, #1040]",
         "strb w21, [x28, #1298]"
@@ -4568,7 +4568,7 @@
         "lsl w21, w21, w20",
         "orr w21, w22, w21",
         "strb w20, [x28, #1019]",
-        "ldr q2, [x28, #2656]",
+        "ldr q2, [x28, #2640]",
         "add x0, x28, x20, lsl #4",
         "str q2, [x0, #1040]",
         "strb w21, [x28, #1298]"
@@ -4588,7 +4588,7 @@
         "lsl w21, w21, w20",
         "orr w21, w22, w21",
         "strb w20, [x28, #1019]",
-        "ldr q2, [x28, #2672]",
+        "ldr q2, [x28, #2656]",
         "add x0, x28, x20, lsl #4",
         "str q2, [x0, #1040]",
         "strb w21, [x28, #1298]"
@@ -4608,7 +4608,7 @@
         "lsl w21, w21, w20",
         "orr w21, w22, w21",
         "strb w20, [x28, #1019]",
-        "ldr q2, [x28, #2688]",
+        "ldr q2, [x28, #2672]",
         "add x0, x28, x20, lsl #4",
         "str q2, [x0, #1040]",
         "strb w21, [x28, #1298]"
@@ -4628,7 +4628,7 @@
         "lsl w21, w21, w20",
         "orr w21, w22, w21",
         "strb w20, [x28, #1019]",
-        "ldr q2, [x28, #2704]",
+        "ldr q2, [x28, #2688]",
         "add x0, x28, x20, lsl #4",
         "str q2, [x0, #1040]",
         "strb w21, [x28, #1298]"
@@ -4792,7 +4792,7 @@
         "eor v2.16b, v2.16b, v2.16b",
         "mov v2.d[0], x0",
         "mov v2.h[4], w1",
-        "ldr q3, [x28, #2624]",
+        "ldr q3, [x28, #2608]",
         "mov w23, #0x0",
         "strb w23, [x28, #1018]",
         "add x0, x28, x20, lsl #4",
@@ -5074,7 +5074,7 @@
         "ldr q2, [x0, #1040]",
         "add x0, x28, x22, lsl #4",
         "ldr q3, [x0, #1040]",
-        "ldr q4, [x28, #2624]",
+        "ldr q4, [x28, #2608]",
         "mrs x0, nzcv",
         "str w0, [x28, #1000]",
         "stp x4, x5, [x28, #280]",