diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp
index 5b73640663..fd67883cae 100644
--- a/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp
+++ b/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp
@@ -194,7 +194,7 @@ DEF_UNOP(VNeg, neg, false)
 DEF_UNOP(VFNeg, fneg, false)
 
 DEF_BITOP(VAnd, and_)
-DEF_BITOP(VBic, bic)
+DEF_BITOP(VAndn, bic)
 DEF_BITOP(VOr, orr)
 DEF_BITOP(VXor, eor)
 
diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
index 0d439d07fd..0063325907 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -5656,7 +5656,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) {
     {0x52, 1, &OpDispatchBuilder::VectorUnaryOp<IR::OP_VFRSQRT, 4>},
     {0x53, 1, &OpDispatchBuilder::VectorUnaryOp<IR::OP_VFRECP, 4>},
     {0x54, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VAND, 16>},
-    {0x55, 1, &OpDispatchBuilder::VectorALUROp<IR::OP_VBIC, 8>},
+    {0x55, 1, &OpDispatchBuilder::VectorALUROp<IR::OP_VANDN, 8>},
     {0x56, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VOR, 16>},
     {0x57, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VXOR, 16>},
     {0x58, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VFADD, 4>},
@@ -5702,7 +5702,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) {
     {0xDC, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VUQADD, 1>},
     {0xDD, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VUQADD, 2>},
     {0xDE, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VUMAX, 1>},
-    {0xDF, 1, &OpDispatchBuilder::VectorALUROp<IR::OP_VBIC, 8>},
+    {0xDF, 1, &OpDispatchBuilder::VectorALUROp<IR::OP_VANDN, 8>},
     {0xE0, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VURAVG, 1>},
     {0xE1, 1, &OpDispatchBuilder::PSRAOp<2>},
     {0xE2, 1, &OpDispatchBuilder::PSRAOp<4>},
@@ -5945,7 +5945,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) {
     {0x50, 1, &OpDispatchBuilder::MOVMSKOp<8>},
     {0x51, 1, &OpDispatchBuilder::VectorUnaryOp<IR::OP_VFSQRT, 8>},
     {0x54, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VAND, 16>},
-    {0x55, 1, &OpDispatchBuilder::VectorALUROp<IR::OP_VBIC, 8>},
+    {0x55, 1, &OpDispatchBuilder::VectorALUROp<IR::OP_VANDN, 8>},
     {0x56, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VOR, 16>},
     {0x57, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VXOR, 16>},
     {0x58, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VFADD, 8>},
@@ -6002,7 +6002,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) {
     {0xDC, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VUQADD, 1>},
     {0xDD, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VUQADD, 2>},
     {0xDE, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VUMAX, 1>},
-    {0xDF, 1, &OpDispatchBuilder::VectorALUROp<IR::OP_VBIC, 8>},
+    {0xDF, 1, &OpDispatchBuilder::VectorALUROp<IR::OP_VANDN, 8>},
     {0xE0, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VURAVG, 1>},
     {0xE1, 1, &OpDispatchBuilder::PSRAOp<2>},
     {0xE2, 1, &OpDispatchBuilder::PSRAOp<4>},
diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
index e918618d09..929d858bf8 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
@@ -386,7 +386,7 @@ void OpDispatchBuilder::VectorALUROp(OpcodeArgs) {
   VectorALUROpImpl(Op, IROp, ElementSize);
 }
 
-template void OpDispatchBuilder::VectorALUROp<IR::OP_VBIC, 8>(OpcodeArgs);
+template void OpDispatchBuilder::VectorALUROp<IR::OP_VANDN, 8>(OpcodeArgs);
 template void OpDispatchBuilder::VectorALUROp<IR::OP_VFSUB, 4>(OpcodeArgs);
 template void OpDispatchBuilder::VectorALUROp<IR::OP_VFSUB, 8>(OpcodeArgs);
 
@@ -1482,7 +1482,7 @@ void OpDispatchBuilder::VANDNOp(OpcodeArgs) {
 
   Ref Src1 = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
   Ref Src2 = LoadSource(FPRClass, Op, Op->Src[1], Op->Flags);
-  Ref Dest = _VBic(SrcSize, SrcSize, Src2, Src1);
+  Ref Dest = _VAndn(SrcSize, SrcSize, Src2, Src1);
 
   StoreResult(FPRClass, Op, Dest, -1);
 }
@@ -1724,7 +1724,7 @@ Ref OpDispatchBuilder::PSIGNImpl(OpcodeArgs, size_t ElementSize, Ref Src1, Ref S
     Ref CmpLT = _VCMPLTZ(Size, ElementSize, Src2);
     Ref CmpEQ = _VCMPEQZ(Size, ElementSize, Src2);
     auto BSLResult = _VBSL(Size, CmpLT, NegVec, Src1);
-    return _VBic(Size, Size, BSLResult, CmpEQ);
+    return _VAndn(Size, Size, BSLResult, CmpEQ);
   }
 }
 
@@ -4087,7 +4087,7 @@ void OpDispatchBuilder::PTestOp(OpcodeArgs) {
   Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
 
   Ref Test1 = _VAnd(Size, 1, Dest, Src);
-  Ref Test2 = _VBic(Size, 1, Src, Dest);
+  Ref Test2 = _VAndn(Size, 1, Src, Dest);
 
   // Element size must be less than 32-bit for the sign bit tricks.
   Test1 = _VUMaxV(Size, 2, Test1);
@@ -4124,7 +4124,7 @@ void OpDispatchBuilder::VTESTOpImpl(OpcodeArgs, size_t ElementSize) {
   Ref Mask = _VDupFromGPR(SrcSize, ElementSize, _Constant(MaskConstant));
 
   Ref AndTest = _VAnd(SrcSize, 1, Src2, Src1);
-  Ref AndNotTest = _VBic(SrcSize, 1, Src2, Src1);
+  Ref AndNotTest = _VAndn(SrcSize, 1, Src2, Src1);
 
   Ref MaskedAnd = _VAnd(SrcSize, 1, AndTest, Mask);
   Ref MaskedAndNot = _VAnd(SrcSize, 1, AndNotTest, Mask);
diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json
index 93f289e956..03904018e6 100644
--- a/FEXCore/Source/Interface/IR/IR.json
+++ b/FEXCore/Source/Interface/IR/IR.json
@@ -1917,7 +1917,7 @@
         "NumElements": "RegisterSize / ElementSize"
       },
 
-      "FPR = VBic u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
+      "FPR = VAndn u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
         "DestSize": "RegisterSize",
         "NumElements": "RegisterSize / ElementSize"
       },