From 4094aa1b9a86ee82505e9110803486b26156fbde Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Sun, 21 Jul 2024 10:12:26 -0400 Subject: [PATCH 1/4] DeadStoreElimination: drop flag handling now that we do everything via NZCV, this is mostly vestigial. DF/x87 flags are sufficiently rare to be "don't care"s here, and we don't even have multiblock enabled yet! Signed-off-by: Alyssa Rosenzweig --- .../IR/Passes/DeadStoreElimination.cpp | 46 ++++--------------- 1 file changed, 9 insertions(+), 37 deletions(-) diff --git a/FEXCore/Source/Interface/IR/Passes/DeadStoreElimination.cpp b/FEXCore/Source/Interface/IR/Passes/DeadStoreElimination.cpp index d203f6c747..dfe980d138 100644 --- a/FEXCore/Source/Interface/IR/Passes/DeadStoreElimination.cpp +++ b/FEXCore/Source/Interface/IR/Passes/DeadStoreElimination.cpp @@ -42,17 +42,16 @@ struct ReadWriteKill { }; struct Info { - ReadWriteKill flag; ReadWriteKill reg; }; /** - * @brief This is a temporary pass to detect simple multiblock dead flag/reg stores + * @brief This is a temporary pass to detect simple multiblock dead reg stores * - * First pass computes which flags/regs are read and written per block + * First pass computes which regs are read and written per block * - * Second pass computes which flags/regs are stored, but overwritten by the next block(s). - * It also propagates this information a few times to catch dead flags/regs across multiple blocks. + * Second pass computes which regs are stored, but overwritten by the next block(s). + * It also propagates this information a few times to catch dead regs across multiple blocks. * * Third pass removes the dead stores. * @@ -64,28 +63,14 @@ void DeadStoreElimination::Run(IREmitter* IREmit) { fextl::vector InfoMap(CurrentIR.GetSSACount()); // Pass 1 - // Compute flags/regs read/writes per block + // Compute regs read/writes per block // This is conservative and doesn't try to be smart about loads after writes { for (auto [BlockNode, BlockIROp] : CurrentIR.GetBlocks()) { auto& BlockInfo = InfoMap[CurrentIR.GetID(BlockNode).Value]; for (auto [CodeNode, IROp] : CurrentIR.GetCode(BlockNode)) { - if (IROp->Op == OP_STOREFLAG) { - auto Op = IROp->C(); - - BlockInfo.flag.writes |= 1UL << Op->Flag; - } else if (IROp->Op == OP_INVALIDATEFLAGS) { - auto Op = IROp->C(); - - BlockInfo.flag.writes |= Op->Flags; - } else if (IROp->Op == OP_LOADFLAG) { - auto Op = IROp->C(); - - BlockInfo.flag.reads |= 1UL << Op->Flag; - } else if (IROp->Op == OP_LOADDF) { - BlockInfo.flag.reads |= 1UL << X86State::RFLAG_DF_RAW_LOC; - } else if (IROp->Op == OP_STOREREGISTER) { + if (IROp->Op == OP_STOREREGISTER) { auto Op = IROp->C(); BlockInfo.reg.writes |= RegBit(Op->Class, Op->Reg); } else if (IROp->Op == OP_LOADREGISTER) { @@ -111,11 +96,9 @@ void DeadStoreElimination::Run(IREmitter* IREmit) { auto& TargetInfo = InfoMap[Op->Header.Args[0].ID().Value]; // stores to remove are written by the next block but not read - BlockInfo.flag.kill = TargetInfo.flag.writes & ~(TargetInfo.flag.reads) & ~BlockInfo.flag.reads; BlockInfo.reg.kill = TargetInfo.reg.writes & ~(TargetInfo.reg.reads) & ~BlockInfo.reg.reads; - // Flags that are written by the next block can be considered as written by this block, if not read - BlockInfo.flag.writes |= BlockInfo.flag.kill & ~BlockInfo.flag.reads; + // If written by the next block can be considered as written by this block, if not read BlockInfo.reg.writes |= BlockInfo.reg.kill & ~BlockInfo.reg.reads; } else if (IROp->Op == OP_CONDJUMP) { auto Op = IROp->C(); @@ -125,14 +108,10 @@ void DeadStoreElimination::Run(IREmitter* IREmit) { auto& FalseTargetInfo = InfoMap[Op->FalseBlock.ID().Value]; // stores to remove are written by the next blocks but not read - BlockInfo.flag.kill = TrueTargetInfo.flag.writes & ~(TrueTargetInfo.flag.reads) & ~BlockInfo.flag.reads; BlockInfo.reg.kill = TrueTargetInfo.reg.writes & ~(TrueTargetInfo.reg.reads) & ~BlockInfo.reg.reads; - - BlockInfo.flag.kill &= FalseTargetInfo.flag.writes & ~(FalseTargetInfo.flag.reads) & ~BlockInfo.flag.reads; BlockInfo.reg.kill &= FalseTargetInfo.reg.writes & ~(FalseTargetInfo.reg.reads) & ~BlockInfo.reg.reads; - // Flags that are written by the next blocks can be considered as written by this block, if not read - BlockInfo.flag.writes |= BlockInfo.flag.kill & ~BlockInfo.flag.reads; + // if written by the next blocks can be considered as written by this block, if not read BlockInfo.reg.writes |= BlockInfo.reg.kill & ~BlockInfo.reg.reads; } } @@ -145,14 +124,7 @@ void DeadStoreElimination::Run(IREmitter* IREmit) { auto& BlockInfo = InfoMap[CurrentIR.GetID(BlockNode).Value]; for (auto [CodeNode, IROp] : CurrentIR.GetCode(BlockNode)) { - if (IROp->Op == OP_STOREFLAG) { - auto Op = IROp->C(); - - // If this StoreFlag is never read, remove it - if (BlockInfo.flag.kill & (1UL << Op->Flag)) { - IREmit->Remove(CodeNode); - } - } else if (IROp->Op == OP_STOREREGISTER) { + if (IROp->Op == OP_STOREREGISTER) { auto Op = IROp->C(); // If this OP_STOREREGISTER is never read, remove it From d20b46e46f3ab402219812297fe963725d75fd96 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Sun, 21 Jul 2024 10:18:49 -0400 Subject: [PATCH 2/4] IR: drop LoadFlag/StoreFlag ops pointless, we can just load/store the context now. Signed-off-by: Alyssa Rosenzweig --- .../Interface/Core/JIT/Arm64/MemoryOps.cpp | 19 ------------------- .../Source/Interface/Core/OpcodeDispatcher.h | 6 +++--- FEXCore/Source/Interface/IR/IR.json | 15 --------------- 3 files changed, 3 insertions(+), 37 deletions(-) diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp index e28b33a8c5..c8aedee82f 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp @@ -529,25 +529,6 @@ DEF_OP(LoadDF) { ldrsb(Dst.X(), STATE, offsetof(FEXCore::Core::CPUState, flags[Flag])); } -DEF_OP(LoadFlag) { - auto Op = IROp->C(); - auto Dst = GetReg(Node); - - LOGMAN_THROW_A_FMT(Op->Flag != X86State::RFLAG_PF_RAW_LOC && Op->Flag != X86State::RFLAG_AF_RAW_LOC, "PF/AF must be accessed as " - "registers"); - - ldrb(Dst, STATE, offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag); -} - -DEF_OP(StoreFlag) { - auto Op = IROp->C(); - - LOGMAN_THROW_A_FMT(Op->Flag != X86State::RFLAG_PF_RAW_LOC && Op->Flag != X86State::RFLAG_AF_RAW_LOC, "PF/AF must be accessed as " - "registers"); - - strb(GetReg(Op->Value.ID()), STATE, offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag); -} - ARMEmitter::ExtendedMemOperand Arm64JITCore::GenerateMemOperand( uint8_t AccessSize, ARMEmitter::Register Base, IR::OrderedNodeWrapper Offset, IR::MemOffsetType OffsetType, uint8_t OffsetScale) { if (Offset.IsInvalid()) { diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index 1572c926bb..248d7c577a 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -1260,7 +1260,7 @@ class OpDispatchBuilder final : public IREmitter { } else if (Index >= FPR0Index && Index <= FPR15Index) { _StoreRegister(Value, Index - FPR0Index, FPRClass, VectorSize); } else if (Index == DFIndex) { - _StoreFlag(Value, X86State::RFLAG_DF_RAW_LOC); + _StoreContext(1, GPRClass, Value, offsetof(Core::CPUState, flags[X86State::RFLAG_DF_RAW_LOC])); } else { bool Partial = RegCache.Partial & (1ull << Index); unsigned Size = Partial ? 8 : CacheIndexToSize(Index); @@ -1729,7 +1729,7 @@ class OpDispatchBuilder final : public IREmitter { if (BitOffset == FEXCore::X86State::RFLAG_DF_RAW_LOC) { StoreDF(_SubShift(OpSize::i64Bit, _Constant(1), Value, ShiftType::LSL, 1)); } else { - _StoreFlag(Value, BitOffset); + _StoreContext(1, GPRClass, Value, offsetof(FEXCore::Core::CPUState, flags[BitOffset])); } } } @@ -1934,7 +1934,7 @@ class OpDispatchBuilder final : public IREmitter { // Recover the sign bit, it is the logical DF value return _Lshr(OpSize::i64Bit, LoadDF(), _Constant(63)); } else { - return _LoadFlag(BitOffset); + return _LoadContext(1, GPRClass, offsetof(Core::CPUState, flags[BitOffset])); } } diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json index b06078d089..9dedf0af37 100644 --- a/FEXCore/Source/Interface/IR/IR.json +++ b/FEXCore/Source/Interface/IR/IR.json @@ -489,21 +489,6 @@ "DestSize": "8" }, - "GPR = LoadFlag u32:$Flag": { - "Desc": ["Loads an x86-64 flag from the context object", - "Specialized to allow flexible implementation of flag handling" - ], - "DestSize": "1" - }, - - "StoreFlag GPR:$Value, u32:$Flag": { - "HasSideEffects": true, - "Desc": ["Stores 1-bit of the flag in to the specified x86-64 flag", - "Specialized to allow flexible implementation of flag handling" - ], - "DestSize": "1" - }, - "SSA = LoadMem RegisterClass:$Class, u8:#Size, GPR:$Addr, GPR:$Offset, u8:$Align, MemOffsetType:$OffsetType, u8:$OffsetScale": { "DestSize": "Size" }, From 610caf85299fefb35e349e5e1aa05fcaebb68cc3 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Sun, 21 Jul 2024 09:58:13 -0400 Subject: [PATCH 3/4] ConstProp: treat StoreContext as zeroable todo: FPR equivalent. Signed-off-by: Alyssa Rosenzweig --- FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp | 2 +- FEXCore/Source/Interface/IR/Passes/ConstProp.cpp | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp index c8aedee82f..afc9c68cf4 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp @@ -52,7 +52,7 @@ DEF_OP(StoreContext) { const auto OpSize = IROp->Size; if (Op->Class == FEXCore::IR::GPRClass) { - auto Src = GetReg(Op->Value.ID()); + auto Src = GetZeroableReg(Op->Value); switch (OpSize) { case 1: strb(Src, STATE, Op->Offset); break; diff --git a/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp b/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp index 1a31a53a38..b34e2ce483 100644 --- a/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp +++ b/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp @@ -629,7 +629,8 @@ void ConstProp::ConstantInlining(IREmitter* IREmit, const IRListView& CurrentIR) break; } case OP_ADC: - case OP_ADCWITHFLAGS: { + case OP_ADCWITHFLAGS: + case OP_STORECONTEXT: { uint64_t Constant1 {}; if (IREmit->IsValueConstant(IROp->Args[0], &Constant1)) { if (Constant1 == 0) { From 592d6cc43f8e860f2757fbcbe694be410e10da98 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Sun, 21 Jul 2024 15:50:10 -0400 Subject: [PATCH 4/4] InstCountCI: Update Signed-off-by: Alyssa Rosenzweig --- .../FlagM/SecondaryGroup.json | 21 +- .../FlagM/x87-HalfLife.json | 498 ++- .../FlagM/x87-Oblivion.json | 2421 ++++++------ .../FlagM/x87-Psychonauts.json | 3352 ++++++++--------- unittests/InstructionCountCI/FlagM/x87.json | 419 +-- .../InstructionCountCI/FlagM/x87_f64.json | 862 ++--- unittests/InstructionCountCI/Secondary.json | 10 +- .../InstructionCountCI/SecondaryGroup.json | 21 +- unittests/InstructionCountCI/x87.json | 419 +-- unittests/InstructionCountCI/x87_f64.json | 1030 +++-- 10 files changed, 4405 insertions(+), 4648 deletions(-) diff --git a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json index bbd153daf8..5bd17fea90 100644 --- a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json @@ -1503,7 +1503,7 @@ ] }, "xrstor [rax]": { - "ExpectedInstructionCount": 167, + "ExpectedInstructionCount": 166, "Comment": "GROUP15 0x0F 0xAE /5", "ExpectedArm64ASM": [ "sub sp, sp, #0x40 (64)", @@ -1542,17 +1542,16 @@ "str q4, [x28, #1072]", "str q3, [x28, #1056]", "str q2, [x28, #1040]", - "b #+0x4c", - "mov w20, #0x0", - "mov w21, #0x37f", - "strh w21, [x28, #1296]", - "strb w20, [x28, #1019]", - "strb w20, [x28, #1016]", - "strb w20, [x28, #1017]", - "strb w20, [x28, #1018]", - "strb w20, [x28, #1022]", + "b #+0x48", + "mov w20, #0x37f", + "strh w20, [x28, #1296]", + "strb wzr, [x28, #1019]", + "strb wzr, [x28, #1016]", + "strb wzr, [x28, #1017]", + "strb wzr, [x28, #1018]", + "strb wzr, [x28, #1022]", "movi v2.2d, #0x0", - "strb w20, [x28, #1298]", + "strb wzr, [x28, #1298]", "str q2, [x28, #1152]", "str q2, [x28, #1136]", "str q2, [x28, #1120]", diff --git a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json index 87fbb713f3..0071184b4d 100644 --- a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json +++ b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json @@ -13,7 +13,7 @@ }, "Instructions": { "Block1": { - "ExpectedInstructionCount": 2035, + "ExpectedInstructionCount": 2034, "x86Insts": [ "sub esp,0x2c", "mov ecx,dword [esp + 0x34]", @@ -616,8 +616,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "mov w24, #0x0", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -739,7 +738,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -861,7 +860,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -903,8 +902,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -917,7 +916,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -959,8 +958,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -973,7 +972,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -1015,8 +1014,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -1029,7 +1028,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -1119,8 +1118,8 @@ "eor v3.16b, v3.16b, v3.16b", "mov v3.d[0], x0", "mov v3.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -1211,8 +1210,8 @@ "eor v3.16b, v3.16b, v3.16b", "mov v3.d[0], x0", "mov v3.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -1255,8 +1254,8 @@ "eor v3.16b, v3.16b, v3.16b", "mov v3.d[0], x0", "mov v3.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -1347,8 +1346,8 @@ "eor v3.16b, v3.16b, v3.16b", "mov v3.d[0], x0", "mov v3.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -1391,8 +1390,8 @@ "eor v3.16b, v3.16b, v3.16b", "mov v3.d[0], x0", "mov v3.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -1483,8 +1482,8 @@ "eor v3.16b, v3.16b, v3.16b", "mov v3.d[0], x0", "mov v3.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -1535,8 +1534,8 @@ "eor v3.16b, v3.16b, v3.16b", "mov v3.d[0], x0", "mov v3.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -1627,8 +1626,8 @@ "eor v3.16b, v3.16b, v3.16b", "mov v3.d[0], x0", "mov v3.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -1671,8 +1670,8 @@ "eor v3.16b, v3.16b, v3.16b", "mov v3.d[0], x0", "mov v3.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -1685,7 +1684,7 @@ "ldr q3, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q4, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q4, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -1766,8 +1765,8 @@ "eor v3.16b, v3.16b, v3.16b", "mov v3.d[0], x0", "mov v3.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -1780,7 +1779,7 @@ "ldr q3, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q4, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q4, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -1869,8 +1868,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -1883,7 +1882,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -1964,8 +1963,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -1978,7 +1977,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -2073,7 +2072,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x22, lsl #4", @@ -2125,7 +2124,7 @@ ] }, "Block2": { - "ExpectedInstructionCount": 839, + "ExpectedInstructionCount": 838, "x86Insts": [ "sub esp,0x1c", "mov edx,dword [esp + 0x20]", @@ -2269,8 +2268,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x25, lsl #4", "ldr q3, [x0, #1040]", - "mov w12, #0x0", - "strb w12, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x25, lsl #4", @@ -2311,10 +2309,10 @@ "ldp x17, x30, [sp], #16", "mov x20, x0", "ubfx x25, x20, #1, #1", - "ubfx x13, x20, #0, #1", + "ubfx x12, x20, #0, #1", "ubfx x20, x20, #2, #1", "orr w25, w25, w20", - "orr w20, w13, w20", + "orr w20, w12, w20", "rmif x25, #63, #nzCv", "rmif x20, #62, #nZcv", "csetm x20, hs", @@ -2439,7 +2437,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x25, lsl #4", "ldr q3, [x0, #1040]", - "strb w12, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x25, lsl #4", @@ -2480,10 +2478,10 @@ "ldp x17, x30, [sp], #16", "mov x20, x0", "ubfx x25, x20, #1, #1", - "ubfx x13, x20, #0, #1", + "ubfx x12, x20, #0, #1", "ubfx x20, x20, #2, #1", "orr w25, w25, w20", - "orr w20, w13, w20", + "orr w20, w12, w20", "rmif x25, #63, #nzCv", "rmif x20, #62, #nZcv", "csetm x20, hs", @@ -2608,7 +2606,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w12, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -2745,7 +2743,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w12, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -3008,7 +3006,7 @@ ] }, "Block3": { - "ExpectedInstructionCount": 1132, + "ExpectedInstructionCount": 1131, "x86Insts": [ "fld dword [ecx]", "fld dword [edx + 0x4]", @@ -3513,8 +3511,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "mov w24, #0x0", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -3589,7 +3586,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -3670,8 +3667,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -3750,8 +3747,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -3764,7 +3761,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -3806,8 +3803,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -3820,7 +3817,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -3862,8 +3859,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -3876,7 +3873,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -4477,7 +4474,7 @@ ] }, "Block5": { - "ExpectedInstructionCount": 1199, + "ExpectedInstructionCount": 1198, "x86Insts": [ "fld dword [esp + 0x80]", "fsub dword [esp + 0x7c]", @@ -4702,22 +4699,21 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "mov w23, #0x0", - "add w24, w20, #0x0 (0)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x0 (0)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -4751,24 +4747,24 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", "ldr s2, [x8, #124]", @@ -4863,8 +4859,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #44]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -4899,8 +4895,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -4969,9 +4965,9 @@ "str q2, [x0, #1040]", "ldr s16, [x8, #44]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -5100,8 +5096,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #68]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -5136,8 +5132,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -5205,9 +5201,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -5336,8 +5332,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #72]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -5372,8 +5368,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -5441,9 +5437,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -5477,12 +5473,12 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", "ldr s2, [x9, #8]", @@ -5583,16 +5579,16 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #76]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "movi v2.2d, #0x0", "add x0, x28, x20, lsl #4", @@ -5628,22 +5624,22 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", "add w23, w20, #0x1 (1)", @@ -5732,7 +5728,7 @@ ] }, "Block6": { - "ExpectedInstructionCount": 1135, + "ExpectedInstructionCount": 1134, "x86Insts": [ "push ebp", "push edi", @@ -6846,8 +6842,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "mov w24, #0x0", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -6913,7 +6908,7 @@ ] }, "Block7": { - "ExpectedInstructionCount": 1045, + "ExpectedInstructionCount": 1044, "x86Insts": [ "fld dword [ebx + 0x4]", "fld dword [ebx]", @@ -7316,8 +7311,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "mov w24, #0x0", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -7497,8 +7491,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -7604,8 +7598,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -7681,7 +7675,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -7786,8 +7780,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -7800,7 +7794,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -7990,7 +7984,7 @@ ] }, "Block8": { - "ExpectedInstructionCount": 258, + "ExpectedInstructionCount": 257, "x86Insts": [ "fstp st0", "fstp st3", @@ -8020,87 +8014,86 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1298]", - "mov w24, #0x1", - "lsl w22, w24, w22", - "orr w22, w23, w22", - "lsl w23, w24, w20", - "bic w22, w22, w23", + "ldrb w22, [x28, #1298]", + "mov w23, #0x1", + "lsl w21, w23, w21", + "orr w21, w22, w21", + "lsl w22, w23, w20", + "bic w21, w21, w22", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w23, w20, #0x3 (3)", - "and w23, w23, #0x7", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x23, lsl #4", + "add x0, x28, x22, lsl #4", "str q2, [x0, #1040]", - "lsl w23, w24, w23", - "orr w22, w22, w23", - "lsl w23, w24, w20", - "bic w22, w22, w23", + "lsl w22, w23, w22", + "orr w21, w21, w22", + "lsl w22, w23, w20", + "bic w21, w21, w22", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w23, w20, #0x0 (0)", - "and w23, w23, #0x7", + "add w22, w20, #0x0 (0)", + "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x23, lsl #4", + "add x0, x28, x22, lsl #4", "str q2, [x0, #1040]", - "lsl w23, w24, w23", - "orr w22, w22, w23", - "lsl w23, w24, w20", - "bic w22, w22, w23", + "lsl w22, w23, w22", + "orr w21, w21, w22", + "lsl w22, w23, w20", + "bic w21, w21, w22", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w23, w20, #0x3 (3)", - "and w23, w23, #0x7", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x23, lsl #4", + "add x0, x28, x22, lsl #4", "str q2, [x0, #1040]", - "lsl w23, w24, w23", - "orr w22, w22, w23", - "lsl w23, w24, w20", - "bic w22, w22, w23", + "lsl w22, w23, w22", + "orr w21, w21, w22", + "lsl w22, w23, w20", + "bic w21, w21, w22", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w23, w20, #0x1 (1)", - "and w23, w23, #0x7", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x23, lsl #4", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x23, lsl #4", + "add x0, x28, x22, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w23, w20, #0x2 (2)", - "and w23, w23, #0x7", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x23, lsl #4", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x23, lsl #4", + "add x0, x28, x22, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -8132,22 +8125,22 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #56]", - "lsl w23, w24, w20", - "bic w22, w22, w23", + "lsl w22, w23, w20", + "bic w21, w21, w22", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w23, w20, #0x1 (1)", - "and w23, w23, #0x7", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x23, lsl #4", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x23, lsl #4", + "add x0, x28, x22, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -8179,22 +8172,22 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #44]", - "lsl w23, w24, w20", - "bic w22, w22, w23", + "lsl w22, w23, w20", + "bic w21, w21, w22", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w23, w20, #0x1 (1)", - "and w23, w23, #0x7", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x23, lsl #4", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x23, lsl #4", + "add x0, x28, x22, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -8226,8 +8219,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #40]", - "lsl w21, w24, w20", - "bic w21, w22, w21", + "lsl w22, w23, w20", + "bic w21, w21, w22", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -8261,7 +8254,7 @@ "ldp x17, x30, [sp], #16", "mov v2.8b, v0.8b", "str d2, [x8]", - "lsl w22, w24, w20", + "lsl w22, w23, w20", "bic w21, w21, w22", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8280,7 +8273,7 @@ ] }, "Block9": { - "ExpectedInstructionCount": 258, + "ExpectedInstructionCount": 257, "x86Insts": [ "fstp st0", "fstp st3", @@ -8310,87 +8303,86 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1298]", - "mov w24, #0x1", - "lsl w22, w24, w22", - "orr w22, w23, w22", - "lsl w23, w24, w20", - "bic w22, w22, w23", + "ldrb w22, [x28, #1298]", + "mov w23, #0x1", + "lsl w21, w23, w21", + "orr w21, w22, w21", + "lsl w22, w23, w20", + "bic w21, w21, w22", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w23, w20, #0x3 (3)", - "and w23, w23, #0x7", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x23, lsl #4", + "add x0, x28, x22, lsl #4", "str q2, [x0, #1040]", - "lsl w23, w24, w23", - "orr w22, w22, w23", - "lsl w23, w24, w20", - "bic w22, w22, w23", + "lsl w22, w23, w22", + "orr w21, w21, w22", + "lsl w22, w23, w20", + "bic w21, w21, w22", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w23, w20, #0x0 (0)", - "and w23, w23, #0x7", + "add w22, w20, #0x0 (0)", + "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x23, lsl #4", + "add x0, x28, x22, lsl #4", "str q2, [x0, #1040]", - "lsl w23, w24, w23", - "orr w22, w22, w23", - "lsl w23, w24, w20", - "bic w22, w22, w23", + "lsl w22, w23, w22", + "orr w21, w21, w22", + "lsl w22, w23, w20", + "bic w21, w21, w22", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w23, w20, #0x3 (3)", - "and w23, w23, #0x7", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x23, lsl #4", + "add x0, x28, x22, lsl #4", "str q2, [x0, #1040]", - "lsl w23, w24, w23", - "orr w22, w22, w23", - "lsl w23, w24, w20", - "bic w22, w22, w23", + "lsl w22, w23, w22", + "orr w21, w21, w22", + "lsl w22, w23, w20", + "bic w21, w21, w22", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w23, w20, #0x1 (1)", - "and w23, w23, #0x7", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x23, lsl #4", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x23, lsl #4", + "add x0, x28, x22, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w23, w20, #0x2 (2)", - "and w23, w23, #0x7", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x23, lsl #4", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x23, lsl #4", + "add x0, x28, x22, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -8422,22 +8414,22 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #56]", - "lsl w23, w24, w20", - "bic w22, w22, w23", + "lsl w22, w23, w20", + "bic w21, w21, w22", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w23, w20, #0x1 (1)", - "and w23, w23, #0x7", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x23, lsl #4", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x23, lsl #4", + "add x0, x28, x22, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -8469,22 +8461,22 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #44]", - "lsl w23, w24, w20", - "bic w22, w22, w23", + "lsl w22, w23, w20", + "bic w21, w21, w22", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w23, w20, #0x1 (1)", - "and w23, w23, #0x7", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x23, lsl #4", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x23, lsl #4", + "add x0, x28, x22, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -8516,8 +8508,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #40]", - "lsl w21, w24, w20", - "bic w21, w22, w21", + "lsl w22, w23, w20", + "bic w21, w21, w22", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -8551,7 +8543,7 @@ "ldp x17, x30, [sp], #16", "mov v2.8b, v0.8b", "str d2, [x8]", - "lsl w22, w24, w20", + "lsl w22, w23, w20", "bic w21, w21, w22", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", diff --git a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json index d2bd0a5a4e..0310137a80 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json +++ b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json @@ -3223,7 +3223,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -3410,7 +3410,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -3597,7 +3597,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -4314,7 +4314,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -4452,7 +4452,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x25, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x25, lsl #4", @@ -5922,7 +5922,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x29, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x29, lsl #4", @@ -6109,7 +6109,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x29, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x29, lsl #4", @@ -6296,7 +6296,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x29, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x29, lsl #4", @@ -6477,7 +6477,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x29, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x29, lsl #4", @@ -6627,7 +6627,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x29, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x29, lsl #4", @@ -6674,7 +6674,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x29, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x29, lsl #4", @@ -6824,7 +6824,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x29, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x29, lsl #4", @@ -7009,7 +7009,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x29, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x29, lsl #4", @@ -7249,7 +7249,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x30, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x30, lsl #4", @@ -7436,7 +7436,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x30, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x30, lsl #4", @@ -8667,7 +8667,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x30, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x30, lsl #4", @@ -8860,7 +8860,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x30, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x30, lsl #4", @@ -9010,7 +9010,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x30, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x30, lsl #4", @@ -9214,7 +9214,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x30, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x30, lsl #4", @@ -11334,7 +11334,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x30, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x30, lsl #4", @@ -23669,7 +23669,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -23859,7 +23859,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -24049,7 +24049,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -24433,7 +24433,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -24626,7 +24626,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -24738,7 +24738,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -25062,7 +25062,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -25255,7 +25255,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -25367,7 +25367,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -25691,7 +25691,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -25884,7 +25884,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -25996,7 +25996,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -26320,7 +26320,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -26513,7 +26513,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -26569,7 +26569,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -26625,7 +26625,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -26971,7 +26971,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -27276,7 +27276,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -27581,7 +27581,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -27886,7 +27886,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -28191,7 +28191,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -28496,7 +28496,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -28801,7 +28801,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -29106,7 +29106,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -29416,7 +29416,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -29603,7 +29603,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -29841,7 +29841,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -30637,7 +30637,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -31309,7 +31309,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -31837,7 +31837,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -32294,7 +32294,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -32434,7 +32434,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -32569,7 +32569,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -32889,7 +32889,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -33834,7 +33834,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -33947,7 +33947,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -34155,7 +34155,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -34368,7 +34368,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -34502,7 +34502,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -34557,7 +34557,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -34612,7 +34612,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -35879,7 +35879,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -36018,7 +36018,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -36157,7 +36157,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -36296,7 +36296,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -36435,7 +36435,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -36574,7 +36574,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -36713,7 +36713,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -36852,7 +36852,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -36991,7 +36991,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -37130,7 +37130,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -37269,7 +37269,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -37408,7 +37408,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -37547,7 +37547,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -37686,7 +37686,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -37825,7 +37825,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -37994,7 +37994,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -38345,7 +38345,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -38484,7 +38484,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -38623,7 +38623,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -38762,7 +38762,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -38901,7 +38901,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -39040,7 +39040,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -39785,7 +39785,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -39930,7 +39930,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -40075,7 +40075,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -41231,7 +41231,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -41287,7 +41287,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -41918,7 +41918,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x25, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x25, lsl #4", @@ -42051,7 +42051,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x25, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x25, lsl #4", @@ -42184,7 +42184,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x25, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x25, lsl #4", @@ -42386,7 +42386,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x25, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x25, lsl #4", @@ -42697,7 +42697,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x25, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x25, lsl #4", @@ -45404,7 +45404,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x25, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x25, lsl #4", @@ -45552,7 +45552,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x25, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x25, lsl #4", @@ -45608,7 +45608,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x25, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x25, lsl #4", @@ -45735,7 +45735,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x25, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x25, lsl #4", @@ -45917,7 +45917,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x25, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x25, lsl #4", @@ -47271,7 +47271,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -52389,7 +52389,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -52445,7 +52445,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -53172,7 +53172,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x25, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x25, lsl #4", @@ -53355,7 +53355,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x25, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x25, lsl #4", @@ -53538,7 +53538,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x25, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x25, lsl #4", @@ -53721,7 +53721,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x25, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x25, lsl #4", @@ -53904,7 +53904,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x25, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x25, lsl #4", @@ -61505,7 +61505,7 @@ "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", "mov w24, #0x0", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -63083,7 +63083,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -63126,7 +63126,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -63168,7 +63168,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -64988,7 +64988,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -65031,7 +65031,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -65073,7 +65073,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -66893,7 +66893,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -66941,7 +66941,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -66988,7 +66988,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -67541,7 +67541,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -67668,7 +67668,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -71954,7 +71954,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -73532,7 +73532,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -73575,7 +73575,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -73617,7 +73617,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -75437,7 +75437,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -75480,7 +75480,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -75522,7 +75522,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -77343,7 +77343,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -77393,7 +77393,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -77440,7 +77440,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -77979,8 +77979,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -77993,7 +77993,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -78106,8 +78106,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -78120,7 +78120,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -82087,7 +82087,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -83232,7 +83232,7 @@ "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", "mov w24, #0x0", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -83372,7 +83372,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x25, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x25, lsl #4", @@ -83512,7 +83512,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x12, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x12, lsl #4", @@ -83652,7 +83652,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x12, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x12, lsl #4", @@ -84437,7 +84437,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x12, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x12, lsl #4", @@ -84721,7 +84721,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x12, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x12, lsl #4", @@ -85904,7 +85904,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x12, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x12, lsl #4", @@ -86190,7 +86190,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x12, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x12, lsl #4", @@ -86476,7 +86476,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x12, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x12, lsl #4", @@ -87645,7 +87645,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x13, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x13, lsl #4", @@ -87825,7 +87825,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x13, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x13, lsl #4", @@ -87872,7 +87872,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x13, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x13, lsl #4", @@ -88549,7 +88549,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x13, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x13, lsl #4", @@ -88596,7 +88596,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x13, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x13, lsl #4", @@ -88696,7 +88696,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x13, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x13, lsl #4", @@ -90657,7 +90657,7 @@ ] }, "Block8": { - "ExpectedInstructionCount": 8284, + "ExpectedInstructionCount": 8283, "x86Insts": [ "movzx eax,word [esi + edx*0x8]", "fld dword [esi + edx*0x8 + 0x4]", @@ -91008,17 +91008,16 @@ "mov x5, x4", "ldr w20, [x8, #484]", "mul w5, w5, w20", - "mov w20, #0x0", "add w4, w4, w4, lsl #1", "add w4, w4, w4", "add w4, w4, w4", - "add w23, w4, #0x8 (8)", - "add w11, w23, w10", + "add w20, w4, #0x8 (8)", + "add w11, w20, w10", "str w11, [x8, #16]", - "ldrb w23, [x28, #1019]", - "add w24, w4, #0x4 (4)", - "add w24, w24, w10", - "ldr s2, [x24]", + "ldrb w20, [x28, #1019]", + "add w23, w4, #0x4 (4)", + "add w23, w23, w10", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -91046,7 +91045,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -91078,9 +91077,9 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #152]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -91109,16 +91108,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w4, w10", - "ldr s2, [x24]", + "ldrb w20, [x28, #1019]", + "add w23, w4, w10", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -91146,7 +91145,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -91178,14 +91177,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -91217,14 +91216,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #160]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -91253,14 +91252,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x11]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -91289,7 +91288,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -91321,14 +91320,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -91360,14 +91359,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #136]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -91396,7 +91395,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -91428,10 +91427,10 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -91460,12 +91459,12 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #208]", - "lsl w24, w21, w23", - "bic w22, w22, w24", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "ldrb w23, [x28, #1019]", + "lsl w23, w21, w20", + "bic w22, w22, w23", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #168]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -91494,17 +91493,17 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w4, #0x4 (4)", - "add w24, w24, w10", - "ldr s2, [x24]", + "ldrb w20, [x28, #1019]", + "add w23, w4, #0x4 (4)", + "add w23, w23, w10", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -91532,7 +91531,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -91564,9 +91563,9 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #164]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -91595,16 +91594,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w4, w10", - "ldr s2, [x24]", + "ldrb w20, [x28, #1019]", + "add w23, w4, w10", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -91632,7 +91631,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -91664,14 +91663,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -91703,14 +91702,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #172]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -91739,14 +91738,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x11]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -91775,7 +91774,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -91807,14 +91806,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -91846,14 +91845,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #140]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -91882,7 +91881,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -91914,10 +91913,10 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -91946,12 +91945,12 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #212]", - "lsl w24, w21, w23", - "bic w22, w22, w24", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "ldrb w23, [x28, #1019]", + "lsl w23, w21, w20", + "bic w22, w22, w23", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #180]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -91980,17 +91979,17 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w4, #0x4 (4)", - "add w24, w24, w10", - "ldr s2, [x24]", + "ldrb w20, [x28, #1019]", + "add w23, w4, #0x4 (4)", + "add w23, w23, w10", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -92018,7 +92017,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -92050,9 +92049,9 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #176]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -92081,16 +92080,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w4, w10", - "ldr s2, [x24]", + "ldrb w20, [x28, #1019]", + "add w23, w4, w10", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -92118,7 +92117,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -92150,15 +92149,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "mov x10, x11", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -92190,14 +92189,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #184]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -92226,14 +92225,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x10]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -92262,7 +92261,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -92294,18 +92293,18 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldr w10, [x8, #56]", - "add w23, w10, #0x8 (8)", - "add w11, w23, w4", + "add w20, w10, #0x8 (8)", + "add w11, w20, w4", "str w11, [x8, #16]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -92337,14 +92336,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #144]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -92373,7 +92372,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -92405,10 +92404,10 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -92437,12 +92436,12 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #216]", - "lsl w24, w21, w23", - "bic w22, w22, w24", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "ldrb w23, [x28, #1019]", + "lsl w23, w21, w20", + "bic w22, w22, w23", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #100]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -92471,28 +92470,28 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x0 (0)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", - "sub w23, w23, #0x1 (1)", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x0 (0)", "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w4, w7", - "ldr s2, [x24]", + "ldrb w20, [x28, #1019]", + "add w23, w4, w7", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -92520,7 +92519,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -92552,9 +92551,9 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #104]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -92583,29 +92582,29 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x0 (0)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", - "sub w23, w23, #0x1 (1)", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x0 (0)", "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w4, #0x4 (4)", - "add w24, w24, w7", - "ldr s2, [x24]", + "ldrb w20, [x28, #1019]", + "add w23, w4, #0x4 (4)", + "add w23, w23, w7", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -92633,7 +92632,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -92665,14 +92664,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -92704,14 +92703,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #108]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -92740,29 +92739,29 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x0 (0)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", - "sub w23, w23, #0x1 (1)", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x0 (0)", "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w4, #0x8 (8)", - "add w24, w24, w7", - "ldr s2, [x24]", + "ldrb w20, [x28, #1019]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w7", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -92790,7 +92789,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -92822,14 +92821,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x3 (3)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -92861,27 +92860,27 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", - "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x2 (2)", - "and w24, w24, #0x7", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", - "ldr q3, [x0, #1040]", - "strb w20, [x28, #1017]", "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "strb wzr, [x28, #1017]", + "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", - "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -92910,12 +92909,12 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #232]", - "lsl w24, w21, w23", - "bic w22, w22, w24", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "ldrb w23, [x28, #1019]", + "lsl w23, w21, w20", + "bic w22, w22, w23", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #112]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -92944,28 +92943,28 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x0 (0)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", - "sub w23, w23, #0x1 (1)", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x0 (0)", "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w4, w7", - "ldr s2, [x24]", + "ldrb w20, [x28, #1019]", + "add w23, w4, w7", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -92993,7 +92992,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -93025,9 +93024,9 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #116]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -93056,29 +93055,29 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x0 (0)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", - "sub w23, w23, #0x1 (1)", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x0 (0)", "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w4, #0x4 (4)", - "add w24, w24, w7", - "ldr s2, [x24]", + "ldrb w20, [x28, #1019]", + "add w23, w4, #0x4 (4)", + "add w23, w23, w7", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -93106,7 +93105,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -93138,14 +93137,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -93177,14 +93176,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #120]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -93213,17 +93212,17 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w4, #0x8 (8)", - "add w24, w24, w7", - "ldr s2, [x24]", + "ldrb w20, [x28, #1019]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w7", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -93251,7 +93250,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -93283,14 +93282,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -93322,27 +93321,27 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", - "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x1 (1)", - "and w24, w24, #0x7", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", - "ldr q3, [x0, #1040]", - "strb w20, [x28, #1017]", "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "strb wzr, [x28, #1017]", + "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", - "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -93371,12 +93370,12 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #236]", - "lsl w24, w21, w23", - "bic w22, w22, w24", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "ldrb w23, [x28, #1019]", + "lsl w23, w21, w20", + "bic w22, w22, w23", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #124]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -93405,16 +93404,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w4, w7", - "ldr s2, [x24]", + "ldrb w20, [x28, #1019]", + "add w23, w4, w7", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -93442,7 +93441,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -93474,9 +93473,9 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #128]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -93505,17 +93504,17 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w4, #0x4 (4)", - "add w24, w24, w7", - "ldr s2, [x24]", + "ldrb w20, [x28, #1019]", + "add w23, w4, #0x4 (4)", + "add w23, w23, w7", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -93543,7 +93542,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -93575,14 +93574,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -93614,14 +93613,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #132]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -93650,17 +93649,17 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w4, #0x8 (8)", - "add w24, w24, w7", - "ldr s2, [x24]", + "ldrb w20, [x28, #1019]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w7", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -93688,7 +93687,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -93720,14 +93719,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -93759,15 +93758,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", - "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -93796,27 +93795,27 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #240]", - "lsl w24, w21, w23", - "bic w22, w22, w24", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", - "sub w23, w23, #0x1 (1)", + "lsl w23, w21, w20", + "bic w22, w22, w23", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x2 (2)", "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w10, #0x4 (4)", - "add w24, w24, w4", - "ldr s2, [x24]", + "ldrb w20, [x28, #1019]", + "add w23, w10, #0x4 (4)", + "add w23, w23, w4", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -93844,7 +93843,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -93876,23 +93875,23 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x5 (5)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", - "sub w23, w23, #0x1 (1)", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x5 (5)", "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w10, w4", - "ldr s2, [x24]", + "ldrb w20, [x28, #1019]", + "add w23, w10, w4", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -93920,7 +93919,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -93952,14 +93951,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -93991,26 +93990,26 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x4 (4)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", - "sub w23, w23, #0x1 (1)", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x4 (4)", "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x11]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -94039,7 +94038,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -94071,14 +94070,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -94110,15 +94109,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", - "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -94147,27 +94146,27 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #88]", - "lsl w24, w21, w23", - "bic w22, w22, w24", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x0 (0)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", - "sub w23, w23, #0x1 (1)", + "lsl w23, w21, w20", + "bic w22, w22, w23", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x0 (0)", "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w10, #0x4 (4)", - "add w24, w24, w4", - "ldr s2, [x24]", + "ldrb w20, [x28, #1019]", + "add w23, w10, #0x4 (4)", + "add w23, w23, w4", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -94195,7 +94194,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -94227,23 +94226,23 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", - "sub w23, w23, #0x1 (1)", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x2 (2)", "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w10, w4", - "ldr s2, [x24]", + "ldrb w20, [x28, #1019]", + "add w23, w10, w4", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -94271,7 +94270,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -94303,14 +94302,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -94342,14 +94341,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #120]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -94378,14 +94377,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x11]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -94414,7 +94413,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -94446,14 +94445,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -94485,15 +94484,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", - "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -94522,12 +94521,12 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #92]", - "lsl w24, w21, w23", - "bic w22, w22, w24", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "ldrb w23, [x28, #1019]", + "lsl w23, w21, w20", + "bic w22, w22, w23", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #128]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -94556,17 +94555,17 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w10, #0x4 (4)", - "add w24, w24, w4", - "ldr s2, [x24]", + "ldrb w20, [x28, #1019]", + "add w23, w10, #0x4 (4)", + "add w23, w23, w4", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -94594,7 +94593,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -94626,9 +94625,9 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #124]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -94657,16 +94656,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w10, w4", - "ldr s2, [x24]", + "ldrb w20, [x28, #1019]", + "add w23, w10, w4", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -94694,7 +94693,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -94726,162 +94725,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "mov x10, x11", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x23, lsl #4", - "ldr q3, [x0, #1040]", - "mrs x0, nzcv", - "str w0, [x28, #1000]", - "stp x4, x5, [x28, #280]", - "stp x6, x7, [x28, #296]", - "str x8, [x28, #312]", - "sub sp, sp, #0x80 (128)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "str x16, [x0], #16", - "stp x17, x30, [x0], #16", - "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1608]", - "blr x5", - "ldr w4, [x28, #1000]", - "msr nzcv, x4", - "ldp x4, x5, [x28, #280]", - "ldp x6, x7, [x28, #296]", - "ldr x8, [x28, #312]", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ldr x16, [sp], #16", - "ldp x17, x30, [sp], #16", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", - "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "ldr s2, [x8, #132]", - "mrs x0, nzcv", - "str w0, [x28, #1000]", - "stp x4, x5, [x28, #280]", - "stp x6, x7, [x28, #296]", - "str x8, [x28, #312]", - "sub sp, sp, #0x80 (128)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "str x16, [x0], #16", - "stp x17, x30, [x0], #16", - "fmov s0, s2", - "ldrh w0, [x28, #1296]", - "ldr x1, [x28, #1424]", - "blr x1", - "ldr w4, [x28, #1000]", - "msr nzcv, x4", - "ldp x4, x5, [x28, #280]", - "ldp x6, x7, [x28, #296]", - "ldr x8, [x28, #312]", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ldr x16, [sp], #16", - "ldp x17, x30, [sp], #16", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x1 (1)", "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", "add x0, x28, x23, lsl #4", - "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "ldr s2, [x10]", - "mrs x0, nzcv", - "str w0, [x28, #1000]", - "stp x4, x5, [x28, #280]", - "stp x6, x7, [x28, #296]", - "str x8, [x28, #312]", - "sub sp, sp, #0x80 (128)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "str x16, [x0], #16", - "stp x17, x30, [x0], #16", - "fmov s0, s2", - "ldrh w0, [x28, #1296]", - "ldr x1, [x28, #1424]", - "blr x1", - "ldr w4, [x28, #1000]", - "msr nzcv, x4", - "ldp x4, x5, [x28, #280]", - "ldp x6, x7, [x28, #296]", - "ldr x8, [x28, #312]", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ldr x16, [sp], #16", - "ldp x17, x30, [sp], #16", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", - "ldr q3, [x0, #1040]", - "mrs x0, nzcv", - "str w0, [x28, #1000]", - "stp x4, x5, [x28, #280]", - "stp x6, x7, [x28, #296]", - "str x8, [x28, #312]", - "sub sp, sp, #0x80 (128)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "str x16, [x0], #16", - "stp x17, x30, [x0], #16", - "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1624]", - "blr x5", - "ldr w4, [x28, #1000]", - "msr nzcv, x4", - "ldp x4, x5, [x28, #280]", - "ldp x6, x7, [x28, #296]", - "ldr x8, [x28, #312]", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ldr x16, [sp], #16", - "ldp x17, x30, [sp], #16", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", - "str q2, [x0, #1040]", - "ldr w10, [x8, #32]", - "add w23, w10, #0x4 (4)", - "add w11, w23, w4", - "str w11, [x8, #16]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -94913,19 +94765,166 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "ldr s2, [x8, #132]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "ldr s2, [x10]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1624]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr w10, [x8, #32]", + "add w20, w10, #0x4 (4)", + "add w11, w20, w4", + "str w11, [x8, #16]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x1 (1)", "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1608]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "add w23, w10, #0x8 (8)", - "add w11, w23, w4", + "add w20, w10, #0x8 (8)", + "add w11, w20, w4", "str w11, [x8, #188]", "ldr w11, [x8, #16]", - "ldrb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -94954,14 +94953,14 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #96]", - "lsl w24, w21, w23", - "bic w22, w22, w24", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "ldrb w23, [x28, #1019]", - "add w24, w10, w4", - "ldr s2, [x24]", + "lsl w23, w21, w20", + "bic w22, w22, w23", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldrb w20, [x28, #1019]", + "add w23, w10, w4", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -94989,19 +94988,19 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x5 (5)", "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", "add x0, x28, x23, lsl #4", - "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x5 (5)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -95033,14 +95032,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x11]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -95069,20 +95068,20 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldr w11, [x8, #188]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x3 (3)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -95114,31 +95113,31 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", - "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x4 (4)", - "and w24, w24, #0x7", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x4 (4)", + "and w23, w23, #0x7", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", - "ldr q3, [x0, #1040]", - "strb w20, [x28, #1017]", "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "strb wzr, [x28, #1017]", + "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -95170,14 +95169,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x11]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -95206,20 +95205,20 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldr w11, [x8, #16]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x3 (3)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -95251,31 +95250,31 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", - "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x1 (1)", - "and w24, w24, #0x7", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", - "ldr q3, [x0, #1040]", - "strb w20, [x28, #1017]", "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "strb wzr, [x28, #1017]", + "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -95307,27 +95306,27 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", - "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x1 (1)", - "and w24, w24, #0x7", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", - "ldr q3, [x0, #1040]", - "strb w20, [x28, #1017]", "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "strb wzr, [x28, #1017]", + "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", - "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -95356,14 +95355,14 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #76]", - "lsl w24, w21, w23", - "bic w22, w22, w24", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "ldrb w23, [x28, #1019]", - "add w24, w10, w4", - "ldr s2, [x24]", + "lsl w23, w21, w20", + "bic w22, w22, w23", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldrb w20, [x28, #1019]", + "add w23, w10, w4", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -95391,7 +95390,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -95423,9 +95422,9 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x11]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -95454,20 +95453,20 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldr w11, [x8, #188]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -95499,19 +95498,19 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -95543,14 +95542,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #120]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -95579,14 +95578,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x11]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -95615,7 +95614,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -95647,14 +95646,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -95686,15 +95685,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", - "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -95723,12 +95722,12 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #80]", - "lsl w24, w21, w23", - "bic w22, w22, w24", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "ldrb w23, [x28, #1019]", + "lsl w23, w21, w20", + "bic w22, w22, w23", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #124]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -95757,16 +95756,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w10, w4", - "ldr s2, [x24]", + "ldrb w20, [x28, #1019]", + "add w23, w10, w4", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -95794,7 +95793,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -95826,10 +95825,10 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldr w4, [x8, #16]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #128]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -95858,14 +95857,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -95894,7 +95893,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -95926,15 +95925,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldr w4, [x8, #468]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -95966,14 +95965,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #132]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -96002,14 +96001,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x11]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -96038,7 +96037,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -96070,14 +96069,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -96109,15 +96108,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", - "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -96146,12 +96145,12 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #84]", - "lsl w24, w21, w23", - "bic w22, w22, w24", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "ldrb w23, [x28, #1019]", + "lsl w23, w21, w20", + "bic w22, w22, w23", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #208]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -96180,14 +96179,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", - "add x0, x28, x23, lsl #4", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", + "ldrb w20, [x28, #1019]", "ldr s2, [x8, #36]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -96216,31 +96215,31 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w23, w23, #0x1 (1)", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x0 (0)", "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", "add x0, x28, x23, lsl #4", - "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x0 (0)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", "ldr q2, [x0, #1040]", - "sub w23, w23, #0x1 (1)", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w23, w21, w20", + "orr w22, w22, w23", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x2 (2)", "and w23, w23, #0x7", - "lsl w24, w21, w23", - "orr w22, w22, w24", - "strb w23, [x28, #1019]", "add x0, x28, x23, lsl #4", - "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x23, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -96272,24 +96271,24 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w23", - "bic w22, w22, w25", - "add w23, w23, #0x1 (1)", - "and w23, w23, #0x7", - "strb w23, [x28, #1019]", - "add x0, x28, x24, lsl #4", - "str q2, [x0, #1040]", - "ldrb w23, [x28, #1019]", - "add w24, w23, #0x1 (1)", - "and w24, w24, #0x7", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", - "ldr q3, [x0, #1040]", - "strb w20, [x28, #1017]", "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "strb wzr, [x28, #1017]", + "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", diff --git a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json index d6d43341d3..7e6065ad57 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json +++ b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json @@ -13,7 +13,7 @@ }, "Instructions": { "Block1": { - "ExpectedInstructionCount": 20546, + "ExpectedInstructionCount": 20545, "x86Insts": [ "sub esp,0x88", "fld dword [ecx + 0x4]", @@ -1763,8 +1763,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "mov w24, #0x0", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -3615,8 +3614,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -3808,8 +3807,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -4294,8 +4293,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -4442,7 +4441,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -4547,8 +4546,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -5569,8 +5568,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -5810,8 +5809,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -6207,8 +6206,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -6331,7 +6330,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -6412,8 +6411,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -7386,8 +7385,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -7579,8 +7578,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -8017,8 +8016,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -8141,7 +8140,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -8222,8 +8221,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -9196,8 +9195,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -9320,7 +9319,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -9401,8 +9400,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -9839,8 +9838,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -10032,8 +10031,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -11023,8 +11022,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -11072,7 +11071,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -11147,7 +11146,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -11252,8 +11251,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -11596,8 +11595,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -11684,7 +11683,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -11765,8 +11764,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -12620,8 +12619,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -12708,7 +12707,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -12789,8 +12788,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -13209,8 +13208,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -13321,7 +13320,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -13426,8 +13425,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -13824,8 +13823,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -14465,7 +14464,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -15305,7 +15304,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -15970,8 +15969,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -16219,7 +16218,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -16968,8 +16967,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -18030,7 +18029,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -18870,7 +18869,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -19511,8 +19510,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -19760,7 +19759,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -21086,7 +21085,7 @@ ] }, "Block2": { - "ExpectedInstructionCount": 17382, + "ExpectedInstructionCount": 17381, "x86Insts": [ "sub esp,0x90", "fld dword [ecx + 0x4]", @@ -21564,15 +21563,14 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "mov w23, #0x0", - "add w24, w20, #0x0 (0)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x0 (0)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -21640,14 +21638,14 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x0 (0)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x0 (0)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -21745,8 +21743,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -21844,8 +21842,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -21943,8 +21941,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -22041,8 +22039,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #8]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -22077,8 +22075,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -22175,8 +22173,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #4]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -22211,8 +22209,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -22310,8 +22308,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -22408,8 +22406,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #16]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -22444,8 +22442,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -22542,8 +22540,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -22578,8 +22576,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -22676,27 +22674,27 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #12]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x0 (0)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x0 (0)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x3 (3)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -22762,8 +22760,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #84]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -22798,15 +22796,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -22872,27 +22870,27 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #100]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -22958,22 +22956,22 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #60]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "lsl w24, w21, w24", - "orr w22, w22, w24", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w23", + "orr w22, w22, w23", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -23070,8 +23068,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #68]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -23106,8 +23104,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -23204,8 +23202,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #96]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -23240,8 +23238,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -23338,8 +23336,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #120]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -23374,8 +23372,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -23472,8 +23470,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #80]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -23508,8 +23506,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -23606,8 +23604,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #40]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -23642,8 +23640,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -23741,8 +23739,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -23840,8 +23838,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -23938,8 +23936,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #8]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -23974,8 +23972,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -24072,8 +24070,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #4]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -24108,8 +24106,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -24207,8 +24205,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -24305,8 +24303,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #16]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -24341,8 +24339,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -24439,8 +24437,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -24475,8 +24473,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -24573,27 +24571,27 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #12]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x0 (0)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x0 (0)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x3 (3)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -24659,8 +24657,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #116]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -24695,15 +24693,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -24769,27 +24767,27 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #132]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -24855,22 +24853,22 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #32]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "lsl w24, w21, w24", - "orr w22, w22, w24", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w23", + "orr w22, w22, w23", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -24967,8 +24965,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #36]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -25003,8 +25001,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -25102,8 +25100,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -25171,21 +25169,21 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x3 (3)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -25222,21 +25220,21 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x5 (5)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x5 (5)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -25273,9 +25271,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -25309,12 +25307,12 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -25346,66 +25344,15 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #104]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", - "mrs x0, nzcv", - "str w0, [x28, #1000]", - "stp x4, x5, [x28, #280]", - "stp x6, x7, [x28, #296]", - "str x8, [x28, #312]", - "sub sp, sp, #0x80 (128)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "str x16, [x0], #16", - "stp x17, x30, [x0], #16", - "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1624]", - "blr x5", - "ldr w4, [x28, #1000]", - "msr nzcv, x4", - "ldp x4, x5, [x28, #280]", - "ldp x6, x7, [x28, #296]", - "ldr x8, [x28, #312]", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ldr x16, [sp], #16", - "ldp x17, x30, [sp], #16", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", - "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", - "add x0, x28, x20, lsl #4", - "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add w24, w20, #0x3 (3)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -25442,9 +25389,60 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "strb wzr, [x28, #1017]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1624]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w20, [x28, #1019]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -25478,12 +25476,12 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -25515,8 +25513,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #136]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -25551,8 +25549,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -25650,8 +25648,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -25719,21 +25717,21 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x4 (4)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x4 (4)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -25770,21 +25768,21 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x4 (4)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x4 (4)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -25821,9 +25819,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -25857,12 +25855,12 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -25894,27 +25892,27 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #128]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -25951,21 +25949,21 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x3 (3)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -26002,9 +26000,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -26038,12 +26036,12 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -26075,8 +26073,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #48]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -26111,8 +26109,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -26210,8 +26208,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -26309,8 +26307,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -26407,8 +26405,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #8]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -26443,8 +26441,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -26541,8 +26539,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #4]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -26577,8 +26575,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -26676,8 +26674,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -26774,8 +26772,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #16]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -26810,8 +26808,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -26908,8 +26906,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -26944,8 +26942,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -27042,27 +27040,27 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #12]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x0 (0)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x0 (0)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x3 (3)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -27128,8 +27126,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #92]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -27164,15 +27162,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -27238,27 +27236,27 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #108]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -27324,22 +27322,22 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #76]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "lsl w24, w21, w24", - "orr w22, w22, w24", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w23", + "orr w22, w22, w23", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -27436,8 +27434,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #52]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -27472,8 +27470,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -27571,8 +27569,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -27640,21 +27638,21 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -27691,9 +27689,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x5 (5)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x5 (5)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -27759,15 +27757,15 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #56]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -27804,9 +27802,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x4 (4)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x4 (4)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -27872,22 +27870,22 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #64]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x0 (0)", - "and w24, w24, #0x7", + "add w23, w20, #0x0 (0)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "lsl w24, w21, w24", - "orr w22, w22, w24", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w23", + "orr w22, w22, w23", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -27922,8 +27920,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -28021,8 +28019,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -28090,21 +28088,21 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x0 (0)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x0 (0)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -28141,9 +28139,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x5 (5)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x5 (5)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -28209,15 +28207,15 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #72]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -28254,9 +28252,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x4 (4)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x4 (4)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -28322,22 +28320,22 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #88]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x0 (0)", - "and w24, w24, #0x7", + "add w23, w20, #0x0 (0)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "lsl w24, w21, w24", - "orr w22, w22, w24", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w23", + "orr w22, w22, w23", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -28372,8 +28370,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -28471,8 +28469,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -28570,8 +28568,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -28668,8 +28666,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #8]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -28704,8 +28702,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -28802,8 +28800,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #4]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -28838,8 +28836,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -28937,8 +28935,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -29035,8 +29033,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #16]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -29071,8 +29069,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -29169,8 +29167,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -29205,8 +29203,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -29303,27 +29301,27 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #12]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x0 (0)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x0 (0)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x3 (3)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -29389,8 +29387,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #124]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -29425,15 +29423,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -29499,27 +29497,27 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #140]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -29585,22 +29583,22 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #44]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "lsl w24, w21, w24", - "orr w22, w22, w24", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w23", + "orr w22, w22, w23", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -29697,8 +29695,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #112]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -29733,8 +29731,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -29832,8 +29830,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -29901,21 +29899,21 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x4 (4)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x4 (4)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -29952,21 +29950,21 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x4 (4)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x4 (4)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -30003,9 +30001,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -30039,12 +30037,12 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -30076,27 +30074,27 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #28]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -30133,21 +30131,21 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x3 (3)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -30184,9 +30182,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -30220,12 +30218,12 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -30257,8 +30255,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #20]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -30293,8 +30291,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -30392,8 +30390,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -30461,21 +30459,21 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x3 (3)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -30512,21 +30510,21 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x5 (5)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x5 (5)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -30563,9 +30561,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -30599,12 +30597,12 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -30636,15 +30634,15 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -30681,21 +30679,21 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x3 (3)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -30732,9 +30730,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -30768,38 +30766,38 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "lsl w24, w21, w24", - "orr w22, w22, w24", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w23", + "orr w22, w22, w23", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x0 (0)", - "and w24, w24, #0x7", + "add w23, w20, #0x0 (0)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "lsl w24, w21, w24", - "orr w22, w22, w24", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w23", + "orr w22, w22, w23", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -30834,8 +30832,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -30933,8 +30931,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -31031,8 +31029,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #24]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -31067,8 +31065,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -31165,8 +31163,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #8]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -31201,8 +31199,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -31299,8 +31297,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #4]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -31335,8 +31333,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -31434,15 +31432,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x3 (3)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -31508,8 +31506,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #16]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -31544,8 +31542,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -31642,22 +31640,22 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", "ldr s2, [x8, #48]", @@ -31752,39 +31750,39 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #12]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x0 (0)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x0 (0)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -31850,8 +31848,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #96]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -31886,8 +31884,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -31984,27 +31982,27 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #100]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -32070,22 +32068,22 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #104]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x0 (0)", - "and w24, w24, #0x7", + "add w23, w20, #0x0 (0)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "lsl w24, w21, w24", - "orr w22, w22, w24", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w23", + "orr w22, w22, w23", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -32120,8 +32118,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -32218,8 +32216,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #108]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -32254,8 +32252,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -32352,8 +32350,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #112]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -32388,8 +32386,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -32486,8 +32484,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #116]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -32522,8 +32520,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -32620,8 +32618,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #120]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -32656,8 +32654,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -32754,8 +32752,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #124]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -32790,8 +32788,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -32889,8 +32887,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -32988,8 +32986,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -33086,8 +33084,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #8]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -33122,8 +33120,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -33220,8 +33218,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #4]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -33256,8 +33254,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -33355,8 +33353,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -33453,8 +33451,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #16]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -33489,8 +33487,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -33587,8 +33585,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -33623,8 +33621,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -33721,27 +33719,27 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #12]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x0 (0)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x0 (0)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x3 (3)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -33807,8 +33805,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #64]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -33843,15 +33841,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -33917,27 +33915,27 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #68]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -34003,22 +34001,22 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #72]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "lsl w24, w21, w24", - "orr w22, w22, w24", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w23", + "orr w22, w22, w23", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -34115,8 +34113,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #76]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -34151,8 +34149,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -34249,8 +34247,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #80]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -34285,8 +34283,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -34383,8 +34381,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #84]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -34419,8 +34417,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -34517,8 +34515,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #88]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -34553,8 +34551,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -34651,8 +34649,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #92]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -34687,8 +34685,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -34786,8 +34784,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -34855,21 +34853,21 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -34906,9 +34904,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x3 (3)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -34974,15 +34972,15 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #20]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -35016,17 +35014,17 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -35093,8 +35091,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -35192,8 +35190,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -35261,21 +35259,21 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -35312,9 +35310,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x4 (4)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x4 (4)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -35380,15 +35378,15 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -35425,9 +35423,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x3 (3)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -35493,22 +35491,22 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #12]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x0 (0)", - "and w24, w24, #0x7", + "add w23, w20, #0x0 (0)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "lsl w24, w21, w24", - "orr w22, w22, w24", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w23", + "orr w22, w22, w23", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -35543,8 +35541,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -35642,8 +35640,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -35740,8 +35738,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #24]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -35776,8 +35774,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -35874,8 +35872,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #8]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -35910,8 +35908,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -36008,8 +36006,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #4]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -36044,15 +36042,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -36118,20 +36116,20 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #32]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -36228,8 +36226,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #36]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -36326,8 +36324,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #40]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -36362,15 +36360,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -36436,36 +36434,36 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #44]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x0 (0)", - "and w24, w24, #0x7", + "add w23, w20, #0x0 (0)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "lsl w24, w21, w24", - "orr w22, w22, w24", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w23", + "orr w22, w22, w23", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x0 (0)", - "and w24, w24, #0x7", + "add w23, w20, #0x0 (0)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "lsl w24, w21, w24", - "orr w22, w22, w24", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w23", + "orr w22, w22, w23", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -36500,8 +36498,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -36598,8 +36596,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #48]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -36634,8 +36632,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -36732,8 +36730,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #52]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -36768,8 +36766,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -36866,8 +36864,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #56]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -36902,8 +36900,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -37000,8 +36998,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #60]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -37036,8 +37034,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -37135,8 +37133,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -37234,8 +37232,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -37332,8 +37330,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #8]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -37368,8 +37366,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -37466,8 +37464,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #4]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -37502,8 +37500,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -37601,8 +37599,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -37699,8 +37697,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #16]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -37735,8 +37733,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -37833,8 +37831,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -37869,8 +37867,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -37967,27 +37965,27 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #12]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x0 (0)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x0 (0)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x3 (3)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -38053,8 +38051,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -38089,15 +38087,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -38163,22 +38161,22 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #4]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", "add w23, w20, #0x2 (2)", @@ -43499,7 +43497,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x13, lsl #4", "ldr q3, [x0, #1040]", - "strb w25, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x13, lsl #4", @@ -49214,7 +49212,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w25, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -53640,8 +53638,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #60]", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -53676,8 +53674,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -53775,8 +53773,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -53874,8 +53872,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -53972,8 +53970,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #24]", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -54008,8 +54006,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -54106,8 +54104,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #28]", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -54142,8 +54140,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -54240,8 +54238,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #68]", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -54276,8 +54274,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -54374,8 +54372,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #76]", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -54410,8 +54408,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -54508,8 +54506,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #88]", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -54544,8 +54542,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -54642,8 +54640,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #92]", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -54678,8 +54676,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -54777,8 +54775,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -54875,8 +54873,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #16]", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -54911,8 +54909,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -55009,8 +55007,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #32]", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -55045,8 +55043,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -55143,8 +55141,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #20]", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -55179,8 +55177,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -55277,8 +55275,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #72]", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -55313,8 +55311,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -55411,8 +55409,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #80]", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -55447,8 +55445,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -55545,8 +55543,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #96]", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -55581,8 +55579,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -55679,27 +55677,27 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #84]", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w12, w20, #0x0 (0)", - "and w12, w12, #0x7", - "add x0, x28, x12, lsl #4", + "add w25, w20, #0x0 (0)", + "and w25, w25, #0x7", + "add x0, x28, x25, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w12, w20, #0x3 (3)", - "and w12, w12, #0x7", - "add x0, x28, x12, lsl #4", + "add w25, w20, #0x3 (3)", + "and w25, w25, #0x7", + "add x0, x28, x25, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -55765,8 +55763,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x11, w24, sxtw]", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -55801,15 +55799,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w12, w20, #0x2 (2)", - "and w12, w12, #0x7", - "add x0, x28, x12, lsl #4", + "add w25, w20, #0x2 (2)", + "and w25, w25, #0x7", + "add x0, x28, x25, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -55875,8 +55873,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x11, w23, sxtw]", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -55911,8 +55909,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -56009,8 +56007,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x11]", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -56045,8 +56043,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -56143,27 +56141,27 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x11, #4]", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w12, w20, #0x2 (2)", - "and w12, w12, #0x7", + "add w25, w20, #0x2 (2)", + "and w25, w25, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x12, lsl #4", + "add x0, x28, x25, lsl #4", "ldr q3, [x0, #1040]", - "strb w25, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x12, lsl #4", + "add x0, x28, x25, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w12, w20, #0x2 (2)", - "and w12, w12, #0x7", - "add x0, x28, x12, lsl #4", + "add w25, w20, #0x2 (2)", + "and w25, w25, #0x7", + "add x0, x28, x25, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -56229,22 +56227,22 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x10, w24, sxtw]", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w12, w20, #0x1 (1)", - "and w12, w12, #0x7", + "add w25, w20, #0x1 (1)", + "and w25, w25, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x12, lsl #4", + "add x0, x28, x25, lsl #4", "str q2, [x0, #1040]", - "lsl w12, w22, w12", - "orr w21, w21, w12", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w25", + "orr w21, w21, w25", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -56341,8 +56339,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x10, w23, sxtw]", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -56377,8 +56375,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -56475,8 +56473,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x10]", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -56511,8 +56509,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -56609,8 +56607,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x10, #4]", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -56645,8 +56643,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -56744,8 +56742,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -56843,15 +56841,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w12, w20, #0x2 (2)", - "and w12, w12, #0x7", - "add x0, x28, x12, lsl #4", + "add w25, w20, #0x2 (2)", + "and w25, w25, #0x7", + "add x0, x28, x25, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -56918,15 +56916,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w12, w20, #0x2 (2)", - "and w12, w12, #0x7", - "add x0, x28, x12, lsl #4", + "add w25, w20, #0x2 (2)", + "and w25, w25, #0x7", + "add x0, x28, x25, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -56963,9 +56961,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w12, w20, #0x1 (1)", - "and w12, w12, #0x7", - "add x0, x28, x12, lsl #4", + "add w25, w20, #0x1 (1)", + "and w25, w25, #0x7", + "add x0, x28, x25, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -56999,12 +56997,12 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w13, w22, w20", - "bic w21, w21, w13", + "lsl w12, w22, w20", + "bic w21, w21, w12", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add x0, x28, x12, lsl #4", + "add x0, x28, x25, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -57036,8 +57034,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x6, w24, sxtw]", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -57072,15 +57070,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w12, w20, #0x1 (1)", - "and w12, w12, #0x7", - "add x0, x28, x12, lsl #4", + "add w25, w20, #0x1 (1)", + "and w25, w25, #0x7", + "add x0, x28, x25, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -57147,15 +57145,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w12, w20, #0x3 (3)", - "and w12, w12, #0x7", - "add x0, x28, x12, lsl #4", + "add w25, w20, #0x3 (3)", + "and w25, w25, #0x7", + "add x0, x28, x25, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -57192,9 +57190,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w12, w20, #0x1 (1)", - "and w12, w12, #0x7", - "add x0, x28, x12, lsl #4", + "add w25, w20, #0x1 (1)", + "and w25, w25, #0x7", + "add x0, x28, x25, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -57228,12 +57226,12 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w13, w22, w20", - "bic w21, w21, w13", + "lsl w12, w22, w20", + "bic w21, w21, w12", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add x0, x28, x12, lsl #4", + "add x0, x28, x25, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -57265,36 +57263,36 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x6, w23, sxtw]", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w12, w20, #0x0 (0)", - "and w12, w12, #0x7", + "add w25, w20, #0x0 (0)", + "and w25, w25, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x12, lsl #4", + "add x0, x28, x25, lsl #4", "str q2, [x0, #1040]", - "lsl w12, w22, w12", - "orr w21, w21, w12", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w25", + "orr w21, w21, w25", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w12, w20, #0x0 (0)", - "and w12, w12, #0x7", + "add w25, w20, #0x0 (0)", + "and w25, w25, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x12, lsl #4", + "add x0, x28, x25, lsl #4", "str q2, [x0, #1040]", - "lsl w12, w22, w12", - "orr w21, w21, w12", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w25", + "orr w21, w21, w25", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -57329,8 +57327,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -57428,8 +57426,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -57497,21 +57495,21 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w12, w20, #0x2 (2)", - "and w12, w12, #0x7", - "add x0, x28, x12, lsl #4", + "add w25, w20, #0x2 (2)", + "and w25, w25, #0x7", + "add x0, x28, x25, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w12, w20, #0x2 (2)", - "and w12, w12, #0x7", - "add x0, x28, x12, lsl #4", + "add w25, w20, #0x2 (2)", + "and w25, w25, #0x7", + "add x0, x28, x25, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -57578,15 +57576,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w12, w20, #0x2 (2)", - "and w12, w12, #0x7", - "add x0, x28, x12, lsl #4", + "add w25, w20, #0x2 (2)", + "and w25, w25, #0x7", + "add x0, x28, x25, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -57623,9 +57621,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w12, w20, #0x1 (1)", - "and w12, w12, #0x7", - "add x0, x28, x12, lsl #4", + "add w25, w20, #0x1 (1)", + "and w25, w25, #0x7", + "add x0, x28, x25, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -57659,12 +57657,12 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w13, w22, w20", - "bic w21, w21, w13", + "lsl w12, w22, w20", + "bic w21, w21, w12", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add x0, x28, x12, lsl #4", + "add x0, x28, x25, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -57696,27 +57694,27 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x6]", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w12, w20, #0x2 (2)", - "and w12, w12, #0x7", - "add x0, x28, x12, lsl #4", + "add w25, w20, #0x2 (2)", + "and w25, w25, #0x7", + "add x0, x28, x25, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w12, w20, #0x1 (1)", - "and w12, w12, #0x7", - "add x0, x28, x12, lsl #4", + "add w25, w20, #0x1 (1)", + "and w25, w25, #0x7", + "add x0, x28, x25, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -57783,15 +57781,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w12, w20, #0x3 (3)", - "and w12, w12, #0x7", - "add x0, x28, x12, lsl #4", + "add w25, w20, #0x3 (3)", + "and w25, w25, #0x7", + "add x0, x28, x25, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -57828,9 +57826,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w12, w20, #0x1 (1)", - "and w12, w12, #0x7", - "add x0, x28, x12, lsl #4", + "add w25, w20, #0x1 (1)", + "and w25, w25, #0x7", + "add x0, x28, x25, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -57864,12 +57862,12 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w13, w22, w20", - "bic w21, w21, w13", + "lsl w12, w22, w20", + "bic w21, w21, w12", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add x0, x28, x12, lsl #4", + "add x0, x28, x25, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -57901,36 +57899,36 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x6, #4]", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w12, w20, #0x0 (0)", - "and w12, w12, #0x7", + "add w25, w20, #0x0 (0)", + "and w25, w25, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x12, lsl #4", + "add x0, x28, x25, lsl #4", "str q2, [x0, #1040]", - "lsl w12, w22, w12", - "orr w21, w21, w12", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w25", + "orr w21, w21, w25", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w12, w20, #0x0 (0)", - "and w12, w12, #0x7", + "add w25, w20, #0x0 (0)", + "and w25, w25, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x12, lsl #4", + "add x0, x28, x25, lsl #4", "str q2, [x0, #1040]", - "lsl w12, w22, w12", - "orr w21, w21, w12", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w25", + "orr w21, w21, w25", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -57965,8 +57963,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -58064,8 +58062,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -58163,15 +58161,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w12, w20, #0x1 (1)", - "and w12, w12, #0x7", - "add x0, x28, x12, lsl #4", + "add w25, w20, #0x1 (1)", + "and w25, w25, #0x7", + "add x0, x28, x25, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -58238,15 +58236,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w21, w21, w12", + "lsl w25, w22, w20", + "orr w21, w21, w25", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w12, w20, #0x3 (3)", - "and w12, w12, #0x7", - "add x0, x28, x12, lsl #4", + "add w25, w20, #0x3 (3)", + "and w25, w25, #0x7", + "add x0, x28, x25, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -58283,9 +58281,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w12, w20, #0x1 (1)", - "and w12, w12, #0x7", - "add x0, x28, x12, lsl #4", + "add w25, w20, #0x1 (1)", + "and w25, w25, #0x7", + "add x0, x28, x25, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -58319,12 +58317,12 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w13, w22, w20", - "bic w21, w21, w13", + "lsl w12, w22, w20", + "bic w21, w21, w12", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add x0, x28, x12, lsl #4", + "add x0, x28, x25, lsl #4", "str q2, [x0, #1040]", "ldr w9, [x8, #36]", "ldrb w20, [x28, #1019]", @@ -58549,8 +58547,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w12, w22, w20", - "bic w21, w21, w12", + "lsl w25, w22, w20", + "bic w21, w21, w25", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -61831,7 +61829,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w25, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -65004,7 +65002,7 @@ ] }, "Block6": { - "ExpectedInstructionCount": 10995, + "ExpectedInstructionCount": 10994, "x86Insts": [ "mov eax,dword [ebp + 0x10]", "fld dword [eax + 0x30]", @@ -76160,8 +76158,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "mov w24, #0x0", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -76208,7 +76205,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -76255,7 +76252,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -76415,7 +76412,7 @@ ] }, "Block7": { - "ExpectedInstructionCount": 11003, + "ExpectedInstructionCount": 11002, "x86Insts": [ "push ebp", "mov ebp,esp", @@ -87588,8 +87585,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "mov w24, #0x0", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -87636,7 +87632,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -87683,7 +87679,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w24, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x23, lsl #4", @@ -89979,7 +89975,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x25, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x25, lsl #4", @@ -92685,7 +92681,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x25, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x25, lsl #4", @@ -93781,7 +93777,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x25, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x25, lsl #4", @@ -94079,9 +94075,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0xc (12)", - "add w24, w24, w10, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0xc (12)", + "add w23, w23, w10, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -94144,9 +94140,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0x8 (8)", - "add w24, w24, w5, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w5, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -94176,15 +94172,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0x8 (8)", - "add w24, w24, w10, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w10, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -94276,15 +94272,15 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #20]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0xc (12)", - "add w24, w24, w10, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0xc (12)", + "add w23, w23, w10, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -94314,15 +94310,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0xc (12)", - "add w24, w24, w5, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0xc (12)", + "add w23, w23, w5, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -94414,15 +94410,15 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #28]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0x8 (8)", - "add w24, w24, w11, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w11, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -94452,15 +94448,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0x8 (8)", - "add w24, w24, w6, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w6, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -94523,9 +94519,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0xc (12)", - "add w24, w24, w6, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0xc (12)", + "add w23, w23, w6, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -94555,15 +94551,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0xc (12)", - "add w24, w24, w11, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0xc (12)", + "add w23, w23, w11, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -94655,15 +94651,15 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #16]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0x8 (8)", - "add w24, w24, w6, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w6, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -94693,15 +94689,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0x8 (8)", - "add w24, w24, w11, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w11, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -94793,15 +94789,15 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #32]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0xc (12)", - "add w24, w24, w6, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0xc (12)", + "add w23, w23, w6, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -94831,15 +94827,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0xc (12)", - "add w24, w24, w11, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0xc (12)", + "add w23, w23, w11, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -94931,27 +94927,27 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #24]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x0 (0)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x0 (0)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x3 (3)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -95016,23 +95012,23 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "add w24, w4, #0x8 (8)", - "add w24, w24, w5, lsl #2", - "str s2, [x24]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "add w23, w4, #0x8 (8)", + "add w23, w23, w5, lsl #2", + "str s2, [x23]", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -95128,30 +95124,30 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "add w24, w4, #0xc (12)", - "add w24, w24, w5, lsl #2", - "str s2, [x24]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "add w23, w4, #0xc (12)", + "add w23, w23, w5, lsl #2", + "str s2, [x23]", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -95216,25 +95212,25 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "add w24, w4, #0x8 (8)", - "add w24, w24, w6, lsl #2", - "str s2, [x24]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "add w23, w4, #0x8 (8)", + "add w23, w23, w6, lsl #2", + "str s2, [x23]", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "lsl w24, w21, w24", - "orr w22, w22, w24", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w23", + "orr w22, w22, w23", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -95269,15 +95265,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -95342,25 +95338,25 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "add w24, w4, #0xc (12)", - "add w24, w24, w6, lsl #2", - "str s2, [x24]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "add w23, w4, #0xc (12)", + "add w23, w23, w6, lsl #2", + "str s2, [x23]", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x0 (0)", - "and w24, w24, #0x7", + "add w23, w20, #0x0 (0)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "lsl w24, w21, w24", - "orr w22, w22, w24", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w23", + "orr w22, w22, w23", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -95395,8 +95391,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -95494,8 +95490,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -95563,21 +95559,21 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -95614,21 +95610,21 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x4 (4)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x4 (4)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -95665,9 +95661,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -95701,12 +95697,12 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -95737,30 +95733,30 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "add w24, w4, #0x8 (8)", - "add w24, w24, w10, lsl #2", - "str s2, [x24]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "add w23, w4, #0x8 (8)", + "add w23, w23, w10, lsl #2", + "str s2, [x23]", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -95797,21 +95793,21 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x3 (3)", - "and w24, w24, #0x7", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -95848,9 +95844,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x3 (3)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -95884,24 +95880,24 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -98789,7 +98785,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -101461,7 +101457,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x24, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x24, lsl #4", @@ -102400,21 +102396,21 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x3 (3)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -102451,9 +102447,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -102518,29 +102514,29 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "add w24, w4, w11, lsl #2", - "str s2, [x24]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "add w23, w4, w11, lsl #2", + "str s2, [x23]", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -102577,9 +102573,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -102644,46 +102640,46 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "add w24, w4, #0x4 (4)", - "add w24, w24, w11, lsl #2", - "str s2, [x24]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "add w23, w4, #0x4 (4)", + "add w23, w23, w11, lsl #2", + "str s2, [x23]", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x0 (0)", - "and w24, w24, #0x7", + "add w23, w20, #0x0 (0)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "lsl w24, w21, w24", - "orr w22, w22, w24", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w23", + "orr w22, w22, w23", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x0 (0)", - "and w24, w24, #0x7", + "add w23, w20, #0x0 (0)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "lsl w24, w21, w24", - "orr w22, w22, w24", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w23", + "orr w22, w22, w23", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0x8 (8)", - "add w24, w24, w5, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w5, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -102713,15 +102709,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0x8 (8)", - "add w24, w24, w10, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w10, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -102784,9 +102780,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0xc (12)", - "add w24, w24, w5, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0xc (12)", + "add w23, w23, w5, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -102816,15 +102812,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0xc (12)", - "add w24, w24, w10, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0xc (12)", + "add w23, w23, w10, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -102887,9 +102883,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0x8 (8)", - "add w24, w24, w5, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w5, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -102919,15 +102915,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0x8 (8)", - "add w24, w24, w10, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w10, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -103019,15 +103015,15 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #24]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0xc (12)", - "add w24, w24, w5, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0xc (12)", + "add w23, w23, w5, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -103057,15 +103053,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0xc (12)", - "add w24, w24, w10, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0xc (12)", + "add w23, w23, w10, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -103157,15 +103153,15 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #28]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0x8 (8)", - "add w24, w24, w11, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w11, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -103195,15 +103191,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0x8 (8)", - "add w24, w24, w6, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w6, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -103266,9 +103262,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0xc (12)", - "add w24, w24, w11, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0xc (12)", + "add w23, w23, w11, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -103298,15 +103294,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0xc (12)", - "add w24, w24, w6, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0xc (12)", + "add w23, w23, w6, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -103398,15 +103394,15 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #16]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0x8 (8)", - "add w24, w24, w6, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w6, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -103436,15 +103432,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0x8 (8)", - "add w24, w24, w11, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w11, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -103536,15 +103532,15 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #32]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0xc (12)", - "add w24, w24, w6, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0xc (12)", + "add w23, w23, w6, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -103574,15 +103570,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w4, #0xc (12)", - "add w24, w24, w11, lsl #2", - "ldr s2, [x24]", + "add w23, w4, #0xc (12)", + "add w23, w23, w11, lsl #2", + "ldr s2, [x23]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -103674,27 +103670,27 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #20]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x0 (0)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x0 (0)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x3 (3)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -103759,11 +103755,11 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "add w24, w4, #0x8 (8)", - "add w24, w24, w5, lsl #2", - "str s2, [x24]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "add w23, w4, #0x8 (8)", + "add w23, w23, w5, lsl #2", + "str s2, [x23]", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -103798,15 +103794,15 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -103871,30 +103867,30 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "add w24, w4, #0xc (12)", - "add w24, w24, w5, lsl #2", - "str s2, [x24]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "add w23, w4, #0xc (12)", + "add w23, w23, w5, lsl #2", + "str s2, [x23]", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -103959,25 +103955,25 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "add w24, w4, #0x8 (8)", - "add w24, w24, w6, lsl #2", - "str s2, [x24]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "add w23, w4, #0x8 (8)", + "add w23, w23, w6, lsl #2", + "str s2, [x23]", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", - "lsl w24, w21, w24", - "orr w22, w22, w24", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "lsl w23, w21, w23", + "orr w22, w22, w23", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -104073,11 +104069,11 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "add w24, w4, #0xc (12)", - "add w24, w24, w6, lsl #2", - "str s2, [x24]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "add w23, w4, #0xc (12)", + "add w23, w23, w6, lsl #2", + "str s2, [x23]", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -104112,8 +104108,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -104211,8 +104207,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -104280,21 +104276,21 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -104331,21 +104327,21 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x4 (4)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x4 (4)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w24, w21, w20", - "orr w22, w22, w24", + "lsl w23, w21, w20", + "orr w22, w22, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -104382,9 +104378,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -104418,12 +104414,12 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -104454,30 +104450,30 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "add w24, w4, #0x8 (8)", - "add w24, w24, w10, lsl #2", - "str s2, [x24]", - "lsl w24, w21, w20", - "bic w22, w22, w24", + "add w23, w4, #0x8 (8)", + "add w23, w23, w10, lsl #2", + "str s2, [x23]", + "lsl w23, w21, w20", + "bic w22, w22, w23", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -104514,21 +104510,21 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x3 (3)", - "and w24, w24, #0x7", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x1 (1)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -104565,9 +104561,9 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x3 (3)", - "and w24, w24, #0x7", - "add x0, x28, x24, lsl #4", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -104601,24 +104597,24 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "lsl w25, w21, w20", - "bic w22, w22, w25", + "lsl w24, w21, w20", + "bic w22, w22, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", - "add w24, w20, #0x2 (2)", - "and w24, w24, #0x7", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x24, lsl #4", + "add x0, x28, x23, lsl #4", "str q2, [x0, #1040]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", diff --git a/unittests/InstructionCountCI/FlagM/x87.json b/unittests/InstructionCountCI/FlagM/x87.json index fdb6f43e7e..542c943de1 100644 --- a/unittests/InstructionCountCI/FlagM/x87.json +++ b/unittests/InstructionCountCI/FlagM/x87.json @@ -156,7 +156,7 @@ ] }, "fcom dword [rax]": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 68, "Comment": [ "0xd8 !11b /2" ], @@ -226,14 +226,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fcomp dword [rax]": { - "ExpectedInstructionCount": 77, + "ExpectedInstructionCount": 76, "Comment": [ "0xd8 !11b /3" ], @@ -303,8 +302,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -1354,16 +1352,15 @@ ] }, "fcom st0, st0": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xd8 11b 0xd0 /2" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -1395,19 +1392,19 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x22, x20, #1, #1", - "ubfx x23, x20, #0, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", "orr w22, w22, w20", - "orr w23, w23, w20", - "strb w22, [x28, #1016]", - "strb w21, [x28, #1017]", + "strb w21, [x28, #1016]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w23, [x28, #1022]" + "strb w22, [x28, #1022]" ] }, "fcom st0, st1": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xd8 11b 0xd1 /2" ], @@ -1453,14 +1450,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fcom st0, st2": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xd8 11b 0xd2 /2" ], @@ -1506,14 +1502,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fcom st0, st3": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xd8 11b 0xd3 /2" ], @@ -1559,14 +1554,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fcom st0, st4": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xd8 11b 0xd4 /2" ], @@ -1612,14 +1606,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fcom st0, st5": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xd8 11b 0xd5 /2" ], @@ -1665,14 +1658,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fcom st0, st6": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xd8 11b 0xd6 /2" ], @@ -1718,14 +1710,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fcom st0, st7": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xd8 11b 0xd7 /2" ], @@ -1771,23 +1762,21 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fcomp st0, st0": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xd8 11b 0xd8 /3" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -1818,16 +1807,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x22, x0", - "ubfx x23, x22, #1, #1", - "ubfx x24, x22, #0, #1", - "ubfx x22, x22, #2, #1", - "orr w23, w23, w22", - "orr w24, w24, w22", - "strb w23, [x28, #1016]", - "strb w21, [x28, #1017]", - "strb w22, [x28, #1018]", - "strb w24, [x28, #1022]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #1016]", + "strb wzr, [x28, #1017]", + "strb w21, [x28, #1018]", + "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -1839,7 +1828,7 @@ ] }, "fcomp st0, st1": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xd8 11b 0xd9 /3" ], @@ -1886,8 +1875,7 @@ "orr w23, w23, w22", "orr w24, w24, w22", "strb w23, [x28, #1016]", - "mov w23, #0x0", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w22, [x28, #1018]", "strb w24, [x28, #1022]", "ldrb w22, [x28, #1298]", @@ -1900,7 +1888,7 @@ ] }, "fcomp st0, st2": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xd8 11b 0xda /3" ], @@ -1946,8 +1934,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -1961,7 +1948,7 @@ ] }, "fcomp st0, st3": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xd8 11b 0xdb /3" ], @@ -2007,8 +1994,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -2022,7 +2008,7 @@ ] }, "fcomp st0, st4": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xd8 11b 0xdc /3" ], @@ -2068,8 +2054,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -2083,7 +2068,7 @@ ] }, "fcomp st0, st5": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xd8 11b 0xdd /3" ], @@ -2129,8 +2114,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -2144,7 +2128,7 @@ ] }, "fcomp st0, st6": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xd8 11b 0xde /3" ], @@ -2190,8 +2174,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -2205,7 +2188,7 @@ ] }, "fcomp st0, st7": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xd8 11b 0xdf /3" ], @@ -2251,8 +2234,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -4231,28 +4213,27 @@ ] }, "fxch st0, st0": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xc8 /1" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]" ] }, "fxch st0, st1": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xc9 /1" ], @@ -4264,8 +4245,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -4273,7 +4253,7 @@ ] }, "fxch st0, st2": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xca /1" ], @@ -4285,8 +4265,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -4294,7 +4273,7 @@ ] }, "fxch st0, st3": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xcb /1" ], @@ -4306,8 +4285,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -4315,7 +4293,7 @@ ] }, "fxch st0, st4": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xcc /1" ], @@ -4327,8 +4305,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -4336,7 +4313,7 @@ ] }, "fxch st0, st5": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xcd /1" ], @@ -4348,8 +4325,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -4357,7 +4333,7 @@ ] }, "fxch st0, st6": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xce /1" ], @@ -4369,8 +4345,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -4378,7 +4353,7 @@ ] }, "fxch st0, st7": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xcf /1" ], @@ -4390,8 +4365,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -4479,16 +4453,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]" + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #1016]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]", + "strb w22, [x28, #1022]" ] }, "fxam": { @@ -4750,7 +4724,7 @@ ] }, "fptan": { - "ExpectedInstructionCount": 46, + "ExpectedInstructionCount": 45, "Comment": [ "0xd9 11b 0xf2 /6" ], @@ -4794,8 +4768,7 @@ "mov v2.d[0], x0", "mov v2.h[4], w1", "ldr q3, [x28, #2608]", - "mov w23, #0x0", - "strb w23, [x28, #1018]", + "strb wzr, [x28, #1018]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "add x0, x28, x22, lsl #4", @@ -4936,7 +4909,7 @@ ] }, "fprem1": { - "ExpectedInstructionCount": 41, + "ExpectedInstructionCount": 40, "Comment": [ "0xd9 11b 0xf5 /6" ], @@ -4978,8 +4951,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "strb wzr, [x28, #1018]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -5009,7 +4981,7 @@ ] }, "fprem": { - "ExpectedInstructionCount": 41, + "ExpectedInstructionCount": 40, "Comment": [ "0xd9 11b 0xf8 /7" ], @@ -5051,8 +5023,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "strb wzr, [x28, #1018]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -5183,7 +5154,7 @@ ] }, "fsincos": { - "ExpectedInstructionCount": 73, + "ExpectedInstructionCount": 72, "Comment": [ "0xd9 11b 0xfb /7" ], @@ -5254,8 +5225,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "mov w23, #0x0", - "strb w23, [x28, #1018]", + "strb wzr, [x28, #1018]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x22, lsl #4", @@ -5352,7 +5322,7 @@ ] }, "fsin": { - "ExpectedInstructionCount": 35, + "ExpectedInstructionCount": 34, "Comment": [ "0xd9 11b 0xfe /7" ], @@ -5388,14 +5358,13 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "strb wzr, [x28, #1018]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, "fcos": { - "ExpectedInstructionCount": 35, + "ExpectedInstructionCount": 34, "Comment": [ "0xd9 11b 0xff /7" ], @@ -5431,8 +5400,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "strb wzr, [x28, #1018]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -5580,7 +5548,7 @@ ] }, "ficom dword [rax]": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 68, "Comment": [ "0xda !11b /2" ], @@ -5650,14 +5618,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "ficomp dword [rax]": { - "ExpectedInstructionCount": 77, + "ExpectedInstructionCount": 76, "Comment": [ "0xda !11b /3" ], @@ -5727,8 +5694,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -6730,7 +6696,7 @@ ] }, "fucompp": { - "ExpectedInstructionCount": 57, + "ExpectedInstructionCount": 56, "Comment": [ "0xda 11b 0xe9 /5" ], @@ -6777,8 +6743,7 @@ "orr w23, w23, w22", "orr w24, w24, w22", "strb w23, [x28, #1016]", - "mov w23, #0x0", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w22, [x28, #1018]", "strb w24, [x28, #1022]", "ldrb w22, [x28, #1298]", @@ -7713,20 +7678,19 @@ "ExpectedArm64ASM": [] }, "fninit": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": [ "0xdb 11b 0xe3 /4" ], "ExpectedArm64ASM": [ - "mov w20, #0x0", - "mov w21, #0x37f", - "strh w21, [x28, #1296]", - "strb w20, [x28, #1019]", - "strb w20, [x28, #1016]", - "strb w20, [x28, #1017]", - "strb w20, [x28, #1018]", - "strb w20, [x28, #1022]", - "strb w20, [x28, #1298]" + "mov w20, #0x37f", + "strh w20, [x28, #1296]", + "strb wzr, [x28, #1019]", + "strb wzr, [x28, #1016]", + "strb wzr, [x28, #1017]", + "strb wzr, [x28, #1018]", + "strb wzr, [x28, #1022]", + "strb wzr, [x28, #1298]" ] }, "fucomi st0, st0": { @@ -8688,7 +8652,7 @@ ] }, "fcom qword [rax]": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 68, "Comment": [ "0xdc !11b /2" ], @@ -8758,14 +8722,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fcomp qword [rax]": { - "ExpectedInstructionCount": 77, + "ExpectedInstructionCount": 76, "Comment": [ "0xdc !11b /3" ], @@ -8835,8 +8798,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -11795,13 +11757,13 @@ "str h2, [x4, #106]", "mov w20, #0x37f", "strh w20, [x28, #1296]", - "strb w21, [x28, #1019]", - "strb w21, [x28, #1016]", - "strb w21, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w21, [x28, #1022]", + "strb wzr, [x28, #1019]", + "strb wzr, [x28, #1016]", + "strb wzr, [x28, #1017]", + "strb wzr, [x28, #1018]", + "strb wzr, [x28, #1022]", "msr nzcv, x25", - "strb w21, [x28, #1298]" + "strb wzr, [x28, #1298]" ] }, "fnstsw [rax]": { @@ -12312,16 +12274,15 @@ ] }, "fucom st0": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xdd 11b 0xe0 /4" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -12353,19 +12314,19 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x22, x20, #1, #1", - "ubfx x23, x20, #0, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", "orr w22, w22, w20", - "orr w23, w23, w20", - "strb w22, [x28, #1016]", - "strb w21, [x28, #1017]", + "strb w21, [x28, #1016]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w23, [x28, #1022]" + "strb w22, [x28, #1022]" ] }, "fucom st1": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xdd 11b 0xe1 /4" ], @@ -12411,14 +12372,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fucom st2": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xdd 11b 0xe2 /4" ], @@ -12464,14 +12424,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fucom st3": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xdd 11b 0xe3 /4" ], @@ -12517,14 +12476,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fucom st4": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xdd 11b 0xe4 /4" ], @@ -12570,14 +12528,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fucom st5": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xdd 11b 0xe5 /4" ], @@ -12623,14 +12580,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fucom st6": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xdd 11b 0xe6 /4" ], @@ -12676,14 +12632,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fucom st7": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xdd 11b 0xe7 /4" ], @@ -12729,23 +12684,21 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fucomp st0": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xdd 11b 0xe8 /5" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -12776,16 +12729,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x22, x0", - "ubfx x23, x22, #1, #1", - "ubfx x24, x22, #0, #1", - "ubfx x22, x22, #2, #1", - "orr w23, w23, w22", - "orr w24, w24, w22", - "strb w23, [x28, #1016]", - "strb w21, [x28, #1017]", - "strb w22, [x28, #1018]", - "strb w24, [x28, #1022]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #1016]", + "strb wzr, [x28, #1017]", + "strb w21, [x28, #1018]", + "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -12797,7 +12750,7 @@ ] }, "fucomp st1": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xdd 11b 0xe9 /5" ], @@ -12844,8 +12797,7 @@ "orr w23, w23, w22", "orr w24, w24, w22", "strb w23, [x28, #1016]", - "mov w23, #0x0", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w22, [x28, #1018]", "strb w24, [x28, #1022]", "ldrb w22, [x28, #1298]", @@ -12858,7 +12810,7 @@ ] }, "fucomp st2": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xdd 11b 0xea /5" ], @@ -12904,8 +12856,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -12919,7 +12870,7 @@ ] }, "fucomp st3": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xdd 11b 0xeb /5" ], @@ -12965,8 +12916,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -12980,7 +12930,7 @@ ] }, "fucomp st4": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xdd 11b 0xec /5" ], @@ -13026,8 +12976,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -13041,7 +12990,7 @@ ] }, "fucomp st5": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xdd 11b 0xed /5" ], @@ -13087,8 +13036,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -13102,7 +13050,7 @@ ] }, "fucomp st6": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xdd 11b 0xee /5" ], @@ -13148,8 +13096,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -13163,7 +13110,7 @@ ] }, "fucomp st7": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xdd 11b 0xef /5" ], @@ -13209,8 +13156,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -13366,7 +13312,7 @@ ] }, "ficom word [rax]": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 68, "Comment": [ "0xde !11b /2" ], @@ -13436,14 +13382,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "ficomp word [rax]": { - "ExpectedInstructionCount": 77, + "ExpectedInstructionCount": 76, "Comment": [ "0xde !11b /3" ], @@ -13513,8 +13458,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -14692,7 +14636,7 @@ ] }, "fcompp": { - "ExpectedInstructionCount": 57, + "ExpectedInstructionCount": 56, "Comment": [ "0xde 11b 0xd9 /3" ], @@ -14739,8 +14683,7 @@ "orr w23, w23, w22", "orr w24, w24, w22", "strb w23, [x28, #1016]", - "mov w23, #0x0", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w22, [x28, #1018]", "strb w24, [x28, #1022]", "ldrb w22, [x28, #1298]", diff --git a/unittests/InstructionCountCI/FlagM/x87_f64.json b/unittests/InstructionCountCI/FlagM/x87_f64.json index 19f2332ff8..6008934077 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64.json @@ -48,7 +48,7 @@ ] }, "fcom dword [rax]": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Comment": [ "0xd8 !11b /2" ], @@ -59,19 +59,18 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", - "cset w22, lo", - "strb w22, [x28, #1016]", - "cset w22, eq", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w21, lo", + "strb w21, [x28, #1016]", + "cset w21, eq", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcomp dword [rax]": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 22, "Comment": [ "0xd8 !11b /3" ], @@ -83,15 +82,14 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", + "cset w22, vs", "axflag", - "cset w24, lo", - "strb w24, [x28, #1016]", - "cset w24, eq", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w23, lo", + "strb w23, [x28, #1016]", + "cset w23, eq", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -454,32 +452,31 @@ ] }, "fcom st0, st0": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": [ "0xd8 11b 0xd0 /2" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", "cset w20, vs", "axflag", - "cset w22, lo", - "strb w22, [x28, #1016]", - "cset w22, eq", - "strb w22, [x28, #1022]", - "strb w21, [x28, #1017]", + "cset w21, lo", + "strb w21, [x28, #1016]", + "cset w21, eq", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]" ] }, "fcom st0, st1": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": [ "0xd8 11b 0xd1 /2" ], @@ -492,19 +489,18 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", - "cset w22, lo", - "strb w22, [x28, #1016]", - "cset w22, eq", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w21, lo", + "strb w21, [x28, #1016]", + "cset w21, eq", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcom st0, st2": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": [ "0xd8 11b 0xd2 /2" ], @@ -517,19 +513,18 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", - "cset w22, lo", - "strb w22, [x28, #1016]", - "cset w22, eq", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w21, lo", + "strb w21, [x28, #1016]", + "cset w21, eq", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcom st0, st3": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": [ "0xd8 11b 0xd3 /2" ], @@ -542,19 +537,18 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", - "cset w22, lo", - "strb w22, [x28, #1016]", - "cset w22, eq", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w21, lo", + "strb w21, [x28, #1016]", + "cset w21, eq", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcom st0, st4": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": [ "0xd8 11b 0xd4 /2" ], @@ -567,19 +561,18 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", - "cset w22, lo", - "strb w22, [x28, #1016]", - "cset w22, eq", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w21, lo", + "strb w21, [x28, #1016]", + "cset w21, eq", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcom st0, st5": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": [ "0xd8 11b 0xd5 /2" ], @@ -592,19 +585,18 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", - "cset w22, lo", - "strb w22, [x28, #1016]", - "cset w22, eq", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w21, lo", + "strb w21, [x28, #1016]", + "cset w21, eq", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcom st0, st6": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": [ "0xd8 11b 0xd6 /2" ], @@ -617,19 +609,18 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", - "cset w22, lo", - "strb w22, [x28, #1016]", - "cset w22, eq", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w21, lo", + "strb w21, [x28, #1016]", + "cset w21, eq", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcom st0, st7": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": [ "0xd8 11b 0xd7 /2" ], @@ -642,44 +633,42 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", - "cset w22, lo", - "strb w22, [x28, #1016]", - "cset w22, eq", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w21, lo", + "strb w21, [x28, #1016]", + "cset w21, eq", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcomp st0, st0": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 24, "Comment": [ "0xd8 11b 0xd8 /3" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w22, #0x1", - "cset w23, vs", + "mov w21, #0x1", + "cset w22, vs", "axflag", - "cset w24, lo", - "strb w24, [x28, #1016]", - "cset w24, eq", - "strb w24, [x28, #1022]", - "strb w21, [x28, #1017]", - "strb w23, [x28, #1018]", - "ldrb w21, [x28, #1298]", - "lsl w22, w22, w20", - "bic w21, w21, w22", + "cset w23, lo", + "strb w23, [x28, #1016]", + "cset w23, eq", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", + "ldrb w22, [x28, #1298]", + "lsl w21, w21, w20", + "bic w21, w22, w21", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -687,7 +676,7 @@ ] }, "fcomp st0, st1": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 24, "Comment": [ "0xd8 11b 0xd9 /3" ], @@ -701,15 +690,14 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w22, #0x0", - "cset w23, vs", + "cset w22, vs", "axflag", - "cset w24, lo", - "strb w24, [x28, #1016]", - "cset w24, eq", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w23, lo", + "strb w23, [x28, #1016]", + "cset w23, eq", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -720,7 +708,7 @@ ] }, "fcomp st0, st2": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 24, "Comment": [ "0xd8 11b 0xda /3" ], @@ -734,15 +722,14 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", + "cset w22, vs", "axflag", - "cset w24, lo", - "strb w24, [x28, #1016]", - "cset w24, eq", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w23, lo", + "strb w23, [x28, #1016]", + "cset w23, eq", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -753,7 +740,7 @@ ] }, "fcomp st0, st3": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 24, "Comment": [ "0xd8 11b 0xdb /3" ], @@ -767,15 +754,14 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", + "cset w22, vs", "axflag", - "cset w24, lo", - "strb w24, [x28, #1016]", - "cset w24, eq", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w23, lo", + "strb w23, [x28, #1016]", + "cset w23, eq", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -786,7 +772,7 @@ ] }, "fcomp st0, st4": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 24, "Comment": [ "0xd8 11b 0xdc /3" ], @@ -800,15 +786,14 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", + "cset w22, vs", "axflag", - "cset w24, lo", - "strb w24, [x28, #1016]", - "cset w24, eq", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w23, lo", + "strb w23, [x28, #1016]", + "cset w23, eq", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -819,7 +804,7 @@ ] }, "fcomp st0, st5": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 24, "Comment": [ "0xd8 11b 0xdd /3" ], @@ -833,15 +818,14 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", + "cset w22, vs", "axflag", - "cset w24, lo", - "strb w24, [x28, #1016]", - "cset w24, eq", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w23, lo", + "strb w23, [x28, #1016]", + "cset w23, eq", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -852,7 +836,7 @@ ] }, "fcomp st0, st6": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 24, "Comment": [ "0xd8 11b 0xde /3" ], @@ -866,15 +850,14 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", + "cset w22, vs", "axflag", - "cset w24, lo", - "strb w24, [x28, #1016]", - "cset w24, eq", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w23, lo", + "strb w23, [x28, #1016]", + "cset w23, eq", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -885,7 +868,7 @@ ] }, "fcomp st0, st7": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 24, "Comment": [ "0xd8 11b 0xdf /3" ], @@ -899,15 +882,14 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", + "cset w22, vs", "axflag", - "cset w24, lo", - "strb w24, [x28, #1016]", - "cset w24, eq", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w23, lo", + "strb w23, [x28, #1016]", + "cset w23, eq", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -1895,28 +1877,27 @@ ] }, "fxch st0, st0": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xc8 /1" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]" ] }, "fxch st0, st1": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xc9 /1" ], @@ -1928,8 +1909,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -1937,7 +1917,7 @@ ] }, "fxch st0, st2": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xca /1" ], @@ -1949,8 +1929,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -1958,7 +1937,7 @@ ] }, "fxch st0, st3": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xcb /1" ], @@ -1970,8 +1949,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -1979,7 +1957,7 @@ ] }, "fxch st0, st4": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xcc /1" ], @@ -1991,8 +1969,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -2000,7 +1977,7 @@ ] }, "fxch st0, st5": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xcd /1" ], @@ -2012,8 +1989,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -2021,7 +1997,7 @@ ] }, "fxch st0, st6": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xce /1" ], @@ -2033,8 +2009,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -2042,7 +2017,7 @@ ] }, "fxch st0, st7": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xcf /1" ], @@ -2054,8 +2029,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -2109,14 +2083,14 @@ "mov w20, #0x0", "fmov d3, x20", "fcmp d2, d3", - "cset w21, vs", + "cset w20, vs", "axflag", - "cset w22, lo", - "strb w22, [x28, #1016]", - "cset w22, eq", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w21, lo", + "strb w21, [x28, #1016]", + "cset w21, eq", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fxam": { @@ -2447,7 +2421,7 @@ ] }, "fptan": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 69, "Comment": [ "0xd9 11b 0xf2 /6" ], @@ -2515,8 +2489,7 @@ "mov v2.8b, v0.8b", "mov x23, #0x3ff0000000000000", "fmov d3, x23", - "mov w23, #0x0", - "strb w23, [x28, #1018]", + "strb wzr, [x28, #1018]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", "add x0, x28, x22, lsl #4", @@ -2631,7 +2604,7 @@ ] }, "fprem1": { - "ExpectedInstructionCount": 63, + "ExpectedInstructionCount": 62, "Comment": [ "0xd9 11b 0xf5 /6" ], @@ -2695,8 +2668,7 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "strb wzr, [x28, #1018]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -2726,7 +2698,7 @@ ] }, "fprem": { - "ExpectedInstructionCount": 63, + "ExpectedInstructionCount": 62, "Comment": [ "0xd9 11b 0xf8 /7" ], @@ -2790,8 +2762,7 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "strb wzr, [x28, #1018]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -2889,7 +2860,7 @@ ] }, "fsincos": { - "ExpectedInstructionCount": 119, + "ExpectedInstructionCount": 118, "Comment": [ "0xd9 11b 0xfb /7" ], @@ -3006,8 +2977,7 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "mov w23, #0x0", - "strb w23, [x28, #1018]", + "strb wzr, [x28, #1018]", "add x0, x28, x20, lsl #4", "str d3, [x0, #1040]", "add x0, x28, x22, lsl #4", @@ -3099,7 +3069,7 @@ ] }, "fsin": { - "ExpectedInstructionCount": 58, + "ExpectedInstructionCount": 57, "Comment": [ "0xd9 11b 0xfe /7" ], @@ -3158,14 +3128,13 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "strb wzr, [x28, #1018]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, "fcos": { - "ExpectedInstructionCount": 58, + "ExpectedInstructionCount": 57, "Comment": [ "0xd9 11b 0xff /7" ], @@ -3224,8 +3193,7 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "strb wzr, [x28, #1018]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -3263,7 +3231,7 @@ ] }, "ficom dword [rax]": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Comment": [ "0xda !11b /2" ], @@ -3274,19 +3242,18 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", - "cset w22, lo", - "strb w22, [x28, #1016]", - "cset w22, eq", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w21, lo", + "strb w21, [x28, #1016]", + "cset w21, eq", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "ficomp dword [rax]": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 22, "Comment": [ "0xda !11b /3" ], @@ -3298,15 +3265,14 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", + "cset w22, vs", "axflag", - "cset w24, lo", - "strb w24, [x28, #1016]", - "cset w24, eq", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w23, lo", + "strb w23, [x28, #1016]", + "cset w23, eq", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -4085,7 +4051,7 @@ ] }, "fucompp": { - "ExpectedInstructionCount": 29, + "ExpectedInstructionCount": 28, "Comment": [ "0xda 11b 0xe9 /5" ], @@ -4099,15 +4065,14 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w22, #0x0", - "cset w23, vs", + "cset w22, vs", "axflag", - "cset w24, lo", - "strb w24, [x28, #1016]", - "cset w24, eq", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w23, lo", + "strb w23, [x28, #1016]", + "cset w23, eq", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w23, w21, w20", "bic w22, w22, w23", @@ -5013,12 +4978,12 @@ "bfi x0, x1, #24, #1", "msr fpcr, x0", "strh w20, [x28, #1296]", - "strb w21, [x28, #1019]", - "strb w21, [x28, #1016]", - "strb w21, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w21, [x28, #1022]", - "strb w21, [x28, #1298]" + "strb wzr, [x28, #1019]", + "strb wzr, [x28, #1016]", + "strb wzr, [x28, #1017]", + "strb wzr, [x28, #1018]", + "strb wzr, [x28, #1022]", + "strb wzr, [x28, #1298]" ] }, "fucomi st0, st0": { @@ -5356,7 +5321,7 @@ ] }, "fcom qword [rax]": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 13, "Comment": [ "0xdc !11b /2" ], @@ -5366,19 +5331,18 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", - "cset w22, lo", - "strb w22, [x28, #1016]", - "cset w22, eq", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w21, lo", + "strb w21, [x28, #1016]", + "cset w21, eq", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcomp qword [rax]": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 21, "Comment": [ "0xdc !11b /3" ], @@ -5389,15 +5353,14 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", + "cset w22, vs", "axflag", - "cset w24, lo", - "strb w24, [x28, #1016]", - "cset w24, eq", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w23, lo", + "strb w23, [x28, #1016]", + "cset w23, eq", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -7067,13 +7030,13 @@ "str h2, [x4, #106]", "mov w20, #0x37f", "strh w20, [x28, #1296]", - "strb w21, [x28, #1019]", - "strb w21, [x28, #1016]", - "strb w21, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w21, [x28, #1022]", + "strb wzr, [x28, #1019]", + "strb wzr, [x28, #1016]", + "strb wzr, [x28, #1017]", + "strb wzr, [x28, #1018]", + "strb wzr, [x28, #1022]", "msr nzcv, x25", - "strb w21, [x28, #1298]" + "strb wzr, [x28, #1298]" ] }, "fnstsw [rax]": { @@ -7584,32 +7547,31 @@ ] }, "fucom st0": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": [ "0xdd 11b 0xe0 /4" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", "cset w20, vs", "axflag", - "cset w22, lo", - "strb w22, [x28, #1016]", - "cset w22, eq", - "strb w22, [x28, #1022]", - "strb w21, [x28, #1017]", + "cset w21, lo", + "strb w21, [x28, #1016]", + "cset w21, eq", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]" ] }, "fucom st1": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": [ "0xdd 11b 0xe1 /4" ], @@ -7622,19 +7584,18 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", - "cset w22, lo", - "strb w22, [x28, #1016]", - "cset w22, eq", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w21, lo", + "strb w21, [x28, #1016]", + "cset w21, eq", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucom st2": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": [ "0xdd 11b 0xe2 /4" ], @@ -7647,19 +7608,18 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", - "cset w22, lo", - "strb w22, [x28, #1016]", - "cset w22, eq", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w21, lo", + "strb w21, [x28, #1016]", + "cset w21, eq", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucom st3": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": [ "0xdd 11b 0xe3 /4" ], @@ -7672,19 +7632,18 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", - "cset w22, lo", - "strb w22, [x28, #1016]", - "cset w22, eq", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w21, lo", + "strb w21, [x28, #1016]", + "cset w21, eq", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucom st4": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": [ "0xdd 11b 0xe4 /4" ], @@ -7697,19 +7656,18 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", - "cset w22, lo", - "strb w22, [x28, #1016]", - "cset w22, eq", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w21, lo", + "strb w21, [x28, #1016]", + "cset w21, eq", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucom st5": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": [ "0xdd 11b 0xe5 /4" ], @@ -7722,19 +7680,18 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", - "cset w22, lo", - "strb w22, [x28, #1016]", - "cset w22, eq", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w21, lo", + "strb w21, [x28, #1016]", + "cset w21, eq", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucom st6": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": [ "0xdd 11b 0xe6 /4" ], @@ -7747,19 +7704,18 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", - "cset w22, lo", - "strb w22, [x28, #1016]", - "cset w22, eq", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w21, lo", + "strb w21, [x28, #1016]", + "cset w21, eq", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucom st7": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": [ "0xdd 11b 0xe7 /4" ], @@ -7772,44 +7728,42 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", - "cset w22, lo", - "strb w22, [x28, #1016]", - "cset w22, eq", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w21, lo", + "strb w21, [x28, #1016]", + "cset w21, eq", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucomp st0": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 24, "Comment": [ "0xdd 11b 0xe8 /5" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w22, #0x1", - "cset w23, vs", + "mov w21, #0x1", + "cset w22, vs", "axflag", - "cset w24, lo", - "strb w24, [x28, #1016]", - "cset w24, eq", - "strb w24, [x28, #1022]", - "strb w21, [x28, #1017]", - "strb w23, [x28, #1018]", - "ldrb w21, [x28, #1298]", - "lsl w22, w22, w20", - "bic w21, w21, w22", + "cset w23, lo", + "strb w23, [x28, #1016]", + "cset w23, eq", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", + "ldrb w22, [x28, #1298]", + "lsl w21, w21, w20", + "bic w21, w22, w21", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -7817,7 +7771,7 @@ ] }, "fucomp st1": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 24, "Comment": [ "0xdd 11b 0xe9 /5" ], @@ -7831,15 +7785,14 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w22, #0x0", - "cset w23, vs", + "cset w22, vs", "axflag", - "cset w24, lo", - "strb w24, [x28, #1016]", - "cset w24, eq", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w23, lo", + "strb w23, [x28, #1016]", + "cset w23, eq", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -7850,7 +7803,7 @@ ] }, "fucomp st2": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 24, "Comment": [ "0xdd 11b 0xea /5" ], @@ -7864,15 +7817,14 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", + "cset w22, vs", "axflag", - "cset w24, lo", - "strb w24, [x28, #1016]", - "cset w24, eq", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w23, lo", + "strb w23, [x28, #1016]", + "cset w23, eq", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -7883,7 +7835,7 @@ ] }, "fucomp st3": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 24, "Comment": [ "0xdd 11b 0xeb /5" ], @@ -7897,15 +7849,14 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", + "cset w22, vs", "axflag", - "cset w24, lo", - "strb w24, [x28, #1016]", - "cset w24, eq", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w23, lo", + "strb w23, [x28, #1016]", + "cset w23, eq", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -7916,7 +7867,7 @@ ] }, "fucomp st4": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 24, "Comment": [ "0xdd 11b 0xec /5" ], @@ -7930,15 +7881,14 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", + "cset w22, vs", "axflag", - "cset w24, lo", - "strb w24, [x28, #1016]", - "cset w24, eq", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w23, lo", + "strb w23, [x28, #1016]", + "cset w23, eq", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -7949,7 +7899,7 @@ ] }, "fucomp st5": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 24, "Comment": [ "0xdd 11b 0xed /5" ], @@ -7963,15 +7913,14 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", + "cset w22, vs", "axflag", - "cset w24, lo", - "strb w24, [x28, #1016]", - "cset w24, eq", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w23, lo", + "strb w23, [x28, #1016]", + "cset w23, eq", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -7982,7 +7931,7 @@ ] }, "fucomp st6": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 24, "Comment": [ "0xdd 11b 0xee /5" ], @@ -7996,15 +7945,14 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", + "cset w22, vs", "axflag", - "cset w24, lo", - "strb w24, [x28, #1016]", - "cset w24, eq", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w23, lo", + "strb w23, [x28, #1016]", + "cset w23, eq", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -8015,7 +7963,7 @@ ] }, "fucomp st7": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 24, "Comment": [ "0xdd 11b 0xef /5" ], @@ -8029,15 +7977,14 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", + "cset w22, vs", "axflag", - "cset w24, lo", - "strb w24, [x28, #1016]", - "cset w24, eq", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w23, lo", + "strb w23, [x28, #1016]", + "cset w23, eq", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -8082,7 +8029,7 @@ ] }, "ficom word [rax]": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 15, "Comment": [ "0xde !11b /2" ], @@ -8094,19 +8041,18 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", - "cset w22, lo", - "strb w22, [x28, #1016]", - "cset w22, eq", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w21, lo", + "strb w21, [x28, #1016]", + "cset w21, eq", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "ficomp word [rax]": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xde !11b /3" ], @@ -8119,15 +8065,14 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", + "cset w22, vs", "axflag", - "cset w24, lo", - "strb w24, [x28, #1016]", - "cset w24, eq", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w23, lo", + "strb w23, [x28, #1016]", + "cset w23, eq", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -8622,7 +8567,7 @@ ] }, "fcompp": { - "ExpectedInstructionCount": 29, + "ExpectedInstructionCount": 28, "Comment": [ "0xde 11b 0xd9 /3" ], @@ -8636,15 +8581,14 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w22, #0x0", - "cset w23, vs", + "cset w22, vs", "axflag", - "cset w24, lo", - "strb w24, [x28, #1016]", - "cset w24, eq", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w23, lo", + "strb w23, [x28, #1016]", + "cset w23, eq", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w23, w21, w20", "bic w22, w22, w23", diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json index 3b5460d2fa..b034901472 100644 --- a/unittests/InstructionCountCI/Secondary.json +++ b/unittests/InstructionCountCI/Secondary.json @@ -19,11 +19,10 @@ ], "Instructions": { "femms": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 1, "Comment": "0x0f 0x0b", "ExpectedArm64ASM": [ - "mov w20, #0x0", - "strb w20, [x28, #1298]" + "strb wzr, [x28, #1298]" ] }, "movups xmm0, xmm0": { @@ -1114,11 +1113,10 @@ ] }, "emms": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 1, "Comment": "0x0f 0x77", "ExpectedArm64ASM": [ - "mov w20, #0x0", - "strb w20, [x28, #1298]" + "strb wzr, [x28, #1298]" ] }, "movd eax, mm0": { diff --git a/unittests/InstructionCountCI/SecondaryGroup.json b/unittests/InstructionCountCI/SecondaryGroup.json index 68a2479b21..14d0a1fb1b 100644 --- a/unittests/InstructionCountCI/SecondaryGroup.json +++ b/unittests/InstructionCountCI/SecondaryGroup.json @@ -1687,7 +1687,7 @@ ] }, "xrstor [rax]": { - "ExpectedInstructionCount": 167, + "ExpectedInstructionCount": 166, "Comment": "GROUP15 0x0F 0xAE /5", "ExpectedArm64ASM": [ "sub sp, sp, #0x40 (64)", @@ -1726,17 +1726,16 @@ "str q4, [x28, #1072]", "str q3, [x28, #1056]", "str q2, [x28, #1040]", - "b #+0x4c", - "mov w20, #0x0", - "mov w21, #0x37f", - "strh w21, [x28, #1296]", - "strb w20, [x28, #1019]", - "strb w20, [x28, #1016]", - "strb w20, [x28, #1017]", - "strb w20, [x28, #1018]", - "strb w20, [x28, #1022]", + "b #+0x48", + "mov w20, #0x37f", + "strh w20, [x28, #1296]", + "strb wzr, [x28, #1019]", + "strb wzr, [x28, #1016]", + "strb wzr, [x28, #1017]", + "strb wzr, [x28, #1018]", + "strb wzr, [x28, #1022]", "movi v2.2d, #0x0", - "strb w20, [x28, #1298]", + "strb wzr, [x28, #1298]", "str q2, [x28, #1152]", "str q2, [x28, #1136]", "str q2, [x28, #1120]", diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json index a1b63996b2..0f133c7449 100644 --- a/unittests/InstructionCountCI/x87.json +++ b/unittests/InstructionCountCI/x87.json @@ -155,7 +155,7 @@ ] }, "fcom dword [rax]": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 68, "Comment": [ "0xd8 !11b /2" ], @@ -225,14 +225,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fcomp dword [rax]": { - "ExpectedInstructionCount": 77, + "ExpectedInstructionCount": 76, "Comment": [ "0xd8 !11b /3" ], @@ -302,8 +301,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -1353,16 +1351,15 @@ ] }, "fcom st0, st0": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xd8 11b 0xd0 /2" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -1394,19 +1391,19 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x22, x20, #1, #1", - "ubfx x23, x20, #0, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", "orr w22, w22, w20", - "orr w23, w23, w20", - "strb w22, [x28, #1016]", - "strb w21, [x28, #1017]", + "strb w21, [x28, #1016]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w23, [x28, #1022]" + "strb w22, [x28, #1022]" ] }, "fcom st0, st1": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xd8 11b 0xd1 /2" ], @@ -1452,14 +1449,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fcom st0, st2": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xd8 11b 0xd2 /2" ], @@ -1505,14 +1501,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fcom st0, st3": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xd8 11b 0xd3 /2" ], @@ -1558,14 +1553,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fcom st0, st4": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xd8 11b 0xd4 /2" ], @@ -1611,14 +1605,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fcom st0, st5": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xd8 11b 0xd5 /2" ], @@ -1664,14 +1657,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fcom st0, st6": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xd8 11b 0xd6 /2" ], @@ -1717,14 +1709,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fcom st0, st7": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xd8 11b 0xd7 /2" ], @@ -1770,23 +1761,21 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fcomp st0, st0": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xd8 11b 0xd8 /3" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -1817,16 +1806,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x22, x0", - "ubfx x23, x22, #1, #1", - "ubfx x24, x22, #0, #1", - "ubfx x22, x22, #2, #1", - "orr w23, w23, w22", - "orr w24, w24, w22", - "strb w23, [x28, #1016]", - "strb w21, [x28, #1017]", - "strb w22, [x28, #1018]", - "strb w24, [x28, #1022]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #1016]", + "strb wzr, [x28, #1017]", + "strb w21, [x28, #1018]", + "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -1838,7 +1827,7 @@ ] }, "fcomp st0, st1": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xd8 11b 0xd9 /3" ], @@ -1885,8 +1874,7 @@ "orr w23, w23, w22", "orr w24, w24, w22", "strb w23, [x28, #1016]", - "mov w23, #0x0", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w22, [x28, #1018]", "strb w24, [x28, #1022]", "ldrb w22, [x28, #1298]", @@ -1899,7 +1887,7 @@ ] }, "fcomp st0, st2": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xd8 11b 0xda /3" ], @@ -1945,8 +1933,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -1960,7 +1947,7 @@ ] }, "fcomp st0, st3": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xd8 11b 0xdb /3" ], @@ -2006,8 +1993,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -2021,7 +2007,7 @@ ] }, "fcomp st0, st4": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xd8 11b 0xdc /3" ], @@ -2067,8 +2053,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -2082,7 +2067,7 @@ ] }, "fcomp st0, st5": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xd8 11b 0xdd /3" ], @@ -2128,8 +2113,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -2143,7 +2127,7 @@ ] }, "fcomp st0, st6": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xd8 11b 0xde /3" ], @@ -2189,8 +2173,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -2204,7 +2187,7 @@ ] }, "fcomp st0, st7": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xd8 11b 0xdf /3" ], @@ -2250,8 +2233,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -4230,28 +4212,27 @@ ] }, "fxch st0, st0": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xc8 /1" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]" ] }, "fxch st0, st1": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xc9 /1" ], @@ -4263,8 +4244,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -4272,7 +4252,7 @@ ] }, "fxch st0, st2": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xca /1" ], @@ -4284,8 +4264,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -4293,7 +4272,7 @@ ] }, "fxch st0, st3": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xcb /1" ], @@ -4305,8 +4284,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -4314,7 +4292,7 @@ ] }, "fxch st0, st4": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xcc /1" ], @@ -4326,8 +4304,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -4335,7 +4312,7 @@ ] }, "fxch st0, st5": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xcd /1" ], @@ -4347,8 +4324,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -4356,7 +4332,7 @@ ] }, "fxch st0, st6": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xce /1" ], @@ -4368,8 +4344,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -4377,7 +4352,7 @@ ] }, "fxch st0, st7": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xcf /1" ], @@ -4389,8 +4364,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -4478,16 +4452,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]" + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #1016]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]", + "strb w22, [x28, #1022]" ] }, "fxam": { @@ -4749,7 +4723,7 @@ ] }, "fptan": { - "ExpectedInstructionCount": 46, + "ExpectedInstructionCount": 45, "Comment": [ "0xd9 11b 0xf2 /6" ], @@ -4793,8 +4767,7 @@ "mov v2.d[0], x0", "mov v2.h[4], w1", "ldr q3, [x28, #2608]", - "mov w23, #0x0", - "strb w23, [x28, #1018]", + "strb wzr, [x28, #1018]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "add x0, x28, x22, lsl #4", @@ -4935,7 +4908,7 @@ ] }, "fprem1": { - "ExpectedInstructionCount": 41, + "ExpectedInstructionCount": 40, "Comment": [ "0xd9 11b 0xf5 /6" ], @@ -4977,8 +4950,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "strb wzr, [x28, #1018]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -5008,7 +4980,7 @@ ] }, "fprem": { - "ExpectedInstructionCount": 41, + "ExpectedInstructionCount": 40, "Comment": [ "0xd9 11b 0xf8 /7" ], @@ -5050,8 +5022,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "strb wzr, [x28, #1018]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -5182,7 +5153,7 @@ ] }, "fsincos": { - "ExpectedInstructionCount": 73, + "ExpectedInstructionCount": 72, "Comment": [ "0xd9 11b 0xfb /7" ], @@ -5253,8 +5224,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "mov w23, #0x0", - "strb w23, [x28, #1018]", + "strb wzr, [x28, #1018]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x22, lsl #4", @@ -5351,7 +5321,7 @@ ] }, "fsin": { - "ExpectedInstructionCount": 35, + "ExpectedInstructionCount": 34, "Comment": [ "0xd9 11b 0xfe /7" ], @@ -5387,14 +5357,13 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "strb wzr, [x28, #1018]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, "fcos": { - "ExpectedInstructionCount": 35, + "ExpectedInstructionCount": 34, "Comment": [ "0xd9 11b 0xff /7" ], @@ -5430,8 +5399,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "strb wzr, [x28, #1018]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -5579,7 +5547,7 @@ ] }, "ficom dword [rax]": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 68, "Comment": [ "0xda !11b /2" ], @@ -5649,14 +5617,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "ficomp dword [rax]": { - "ExpectedInstructionCount": 77, + "ExpectedInstructionCount": 76, "Comment": [ "0xda !11b /3" ], @@ -5726,8 +5693,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -6729,7 +6695,7 @@ ] }, "fucompp": { - "ExpectedInstructionCount": 57, + "ExpectedInstructionCount": 56, "Comment": [ "0xda 11b 0xe9 /5" ], @@ -6776,8 +6742,7 @@ "orr w23, w23, w22", "orr w24, w24, w22", "strb w23, [x28, #1016]", - "mov w23, #0x0", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w22, [x28, #1018]", "strb w24, [x28, #1022]", "ldrb w22, [x28, #1298]", @@ -7712,20 +7677,19 @@ "ExpectedArm64ASM": [] }, "fninit": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": [ "0xdb 11b 0xe3 /4" ], "ExpectedArm64ASM": [ - "mov w20, #0x0", - "mov w21, #0x37f", - "strh w21, [x28, #1296]", - "strb w20, [x28, #1019]", - "strb w20, [x28, #1016]", - "strb w20, [x28, #1017]", - "strb w20, [x28, #1018]", - "strb w20, [x28, #1022]", - "strb w20, [x28, #1298]" + "mov w20, #0x37f", + "strh w20, [x28, #1296]", + "strb wzr, [x28, #1019]", + "strb wzr, [x28, #1016]", + "strb wzr, [x28, #1017]", + "strb wzr, [x28, #1018]", + "strb wzr, [x28, #1022]", + "strb wzr, [x28, #1298]" ] }, "fucomi st0, st0": { @@ -8703,7 +8667,7 @@ ] }, "fcom qword [rax]": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 68, "Comment": [ "0xdc !11b /2" ], @@ -8773,14 +8737,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fcomp qword [rax]": { - "ExpectedInstructionCount": 77, + "ExpectedInstructionCount": 76, "Comment": [ "0xdc !11b /3" ], @@ -8850,8 +8813,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -11810,13 +11772,13 @@ "str h2, [x4, #106]", "mov w20, #0x37f", "strh w20, [x28, #1296]", - "strb w21, [x28, #1019]", - "strb w21, [x28, #1016]", - "strb w21, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w21, [x28, #1022]", + "strb wzr, [x28, #1019]", + "strb wzr, [x28, #1016]", + "strb wzr, [x28, #1017]", + "strb wzr, [x28, #1018]", + "strb wzr, [x28, #1022]", "msr nzcv, x25", - "strb w21, [x28, #1298]" + "strb wzr, [x28, #1298]" ] }, "fnstsw [rax]": { @@ -12327,16 +12289,15 @@ ] }, "fucom st0": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xdd 11b 0xe0 /4" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -12368,19 +12329,19 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x22, x20, #1, #1", - "ubfx x23, x20, #0, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", "orr w22, w22, w20", - "orr w23, w23, w20", - "strb w22, [x28, #1016]", - "strb w21, [x28, #1017]", + "strb w21, [x28, #1016]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w23, [x28, #1022]" + "strb w22, [x28, #1022]" ] }, "fucom st1": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xdd 11b 0xe1 /4" ], @@ -12426,14 +12387,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fucom st2": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xdd 11b 0xe2 /4" ], @@ -12479,14 +12439,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fucom st3": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xdd 11b 0xe3 /4" ], @@ -12532,14 +12491,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fucom st4": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xdd 11b 0xe4 /4" ], @@ -12585,14 +12543,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fucom st5": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xdd 11b 0xe5 /4" ], @@ -12638,14 +12595,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fucom st6": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xdd 11b 0xe6 /4" ], @@ -12691,14 +12647,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fucom st7": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 44, "Comment": [ "0xdd 11b 0xe7 /4" ], @@ -12744,23 +12699,21 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "fucomp st0": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xdd 11b 0xe8 /5" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -12791,16 +12744,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x22, x0", - "ubfx x23, x22, #1, #1", - "ubfx x24, x22, #0, #1", - "ubfx x22, x22, #2, #1", - "orr w23, w23, w22", - "orr w24, w24, w22", - "strb w23, [x28, #1016]", - "strb w21, [x28, #1017]", - "strb w22, [x28, #1018]", - "strb w24, [x28, #1022]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #1016]", + "strb wzr, [x28, #1017]", + "strb w21, [x28, #1018]", + "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -12812,7 +12765,7 @@ ] }, "fucomp st1": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xdd 11b 0xe9 /5" ], @@ -12859,8 +12812,7 @@ "orr w23, w23, w22", "orr w24, w24, w22", "strb w23, [x28, #1016]", - "mov w23, #0x0", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w22, [x28, #1018]", "strb w24, [x28, #1022]", "ldrb w22, [x28, #1298]", @@ -12873,7 +12825,7 @@ ] }, "fucomp st2": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xdd 11b 0xea /5" ], @@ -12919,8 +12871,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -12934,7 +12885,7 @@ ] }, "fucomp st3": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xdd 11b 0xeb /5" ], @@ -12980,8 +12931,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -12995,7 +12945,7 @@ ] }, "fucomp st4": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xdd 11b 0xec /5" ], @@ -13041,8 +12991,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -13056,7 +13005,7 @@ ] }, "fucomp st5": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xdd 11b 0xed /5" ], @@ -13102,8 +13051,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -13117,7 +13065,7 @@ ] }, "fucomp st6": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xdd 11b 0xee /5" ], @@ -13163,8 +13111,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -13178,7 +13125,7 @@ ] }, "fucomp st7": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 52, "Comment": [ "0xdd 11b 0xef /5" ], @@ -13224,8 +13171,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -13381,7 +13327,7 @@ ] }, "ficom word [rax]": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 68, "Comment": [ "0xde !11b /2" ], @@ -13451,14 +13397,13 @@ "orr w21, w21, w20", "orr w22, w22, w20", "strb w21, [x28, #1016]", - "mov w21, #0x0", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", "strb w22, [x28, #1022]" ] }, "ficomp word [rax]": { - "ExpectedInstructionCount": 77, + "ExpectedInstructionCount": 76, "Comment": [ "0xde !11b /3" ], @@ -13528,8 +13473,7 @@ "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", "strb w23, [x28, #1022]", "ldrb w21, [x28, #1298]", @@ -14707,7 +14651,7 @@ ] }, "fcompp": { - "ExpectedInstructionCount": 57, + "ExpectedInstructionCount": 56, "Comment": [ "0xde 11b 0xd9 /3" ], @@ -14754,8 +14698,7 @@ "orr w23, w23, w22", "orr w24, w24, w22", "strb w23, [x28, #1016]", - "mov w23, #0x0", - "strb w23, [x28, #1017]", + "strb wzr, [x28, #1017]", "strb w22, [x28, #1018]", "strb w24, [x28, #1022]", "ldrb w22, [x28, #1298]", diff --git a/unittests/InstructionCountCI/x87_f64.json b/unittests/InstructionCountCI/x87_f64.json index a3f48d5586..485ee0cc25 100644 --- a/unittests/InstructionCountCI/x87_f64.json +++ b/unittests/InstructionCountCI/x87_f64.json @@ -47,7 +47,7 @@ ] }, "fcom dword [rax]": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 15, "Comment": [ "0xd8 !11b /2" ], @@ -58,20 +58,19 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", - "cset w22, eq", - "cset w23, mi", - "orr w23, w23, w21", - "strb w23, [x28, #1016]", - "orr w22, w22, w21", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w20, vs", + "cset w21, eq", + "cset w22, mi", + "orr w22, w22, w20", + "strb w22, [x28, #1016]", + "orr w21, w21, w20", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcomp dword [rax]": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xd8 !11b /3" ], @@ -83,16 +82,15 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", - "cset w24, eq", - "cset w25, mi", - "orr w25, w25, w23", - "strb w25, [x28, #1016]", - "orr w24, w24, w23", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w22, vs", + "cset w23, eq", + "cset w24, mi", + "orr w24, w24, w22", + "strb w24, [x28, #1016]", + "orr w23, w23, w22", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -455,33 +453,32 @@ ] }, "fcom st0, st0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xd8 11b 0xd0 /2" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", "cset w20, vs", - "cset w22, eq", - "cset w23, mi", - "orr w23, w23, w20", - "strb w23, [x28, #1016]", + "cset w21, eq", + "cset w22, mi", "orr w22, w22, w20", - "strb w22, [x28, #1022]", - "strb w21, [x28, #1017]", + "strb w22, [x28, #1016]", + "orr w21, w21, w20", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]" ] }, "fcom st0, st1": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xd8 11b 0xd1 /2" ], @@ -494,20 +491,19 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", - "cset w22, eq", - "cset w23, mi", - "orr w23, w23, w21", - "strb w23, [x28, #1016]", - "orr w22, w22, w21", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w20, vs", + "cset w21, eq", + "cset w22, mi", + "orr w22, w22, w20", + "strb w22, [x28, #1016]", + "orr w21, w21, w20", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcom st0, st2": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xd8 11b 0xd2 /2" ], @@ -520,20 +516,19 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", - "cset w22, eq", - "cset w23, mi", - "orr w23, w23, w21", - "strb w23, [x28, #1016]", - "orr w22, w22, w21", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w20, vs", + "cset w21, eq", + "cset w22, mi", + "orr w22, w22, w20", + "strb w22, [x28, #1016]", + "orr w21, w21, w20", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcom st0, st3": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xd8 11b 0xd3 /2" ], @@ -546,20 +541,19 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", - "cset w22, eq", - "cset w23, mi", - "orr w23, w23, w21", - "strb w23, [x28, #1016]", - "orr w22, w22, w21", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w20, vs", + "cset w21, eq", + "cset w22, mi", + "orr w22, w22, w20", + "strb w22, [x28, #1016]", + "orr w21, w21, w20", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcom st0, st4": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xd8 11b 0xd4 /2" ], @@ -572,20 +566,19 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", - "cset w22, eq", - "cset w23, mi", - "orr w23, w23, w21", - "strb w23, [x28, #1016]", - "orr w22, w22, w21", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w20, vs", + "cset w21, eq", + "cset w22, mi", + "orr w22, w22, w20", + "strb w22, [x28, #1016]", + "orr w21, w21, w20", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcom st0, st5": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xd8 11b 0xd5 /2" ], @@ -598,20 +591,19 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", - "cset w22, eq", - "cset w23, mi", - "orr w23, w23, w21", - "strb w23, [x28, #1016]", - "orr w22, w22, w21", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w20, vs", + "cset w21, eq", + "cset w22, mi", + "orr w22, w22, w20", + "strb w22, [x28, #1016]", + "orr w21, w21, w20", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcom st0, st6": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xd8 11b 0xd6 /2" ], @@ -624,20 +616,19 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", - "cset w22, eq", - "cset w23, mi", - "orr w23, w23, w21", - "strb w23, [x28, #1016]", - "orr w22, w22, w21", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w20, vs", + "cset w21, eq", + "cset w22, mi", + "orr w22, w22, w20", + "strb w22, [x28, #1016]", + "orr w21, w21, w20", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcom st0, st7": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xd8 11b 0xd7 /2" ], @@ -650,46 +641,44 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", - "cset w22, eq", - "cset w23, mi", - "orr w23, w23, w21", - "strb w23, [x28, #1016]", - "orr w22, w22, w21", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w20, vs", + "cset w21, eq", + "cset w22, mi", + "orr w22, w22, w20", + "strb w22, [x28, #1016]", + "orr w21, w21, w20", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcomp st0, st0": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 25, "Comment": [ "0xd8 11b 0xd8 /3" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w22, #0x1", - "cset w23, vs", - "cset w24, eq", - "cset w25, mi", - "orr w25, w25, w23", - "strb w25, [x28, #1016]", - "orr w24, w24, w23", - "strb w24, [x28, #1022]", - "strb w21, [x28, #1017]", - "strb w23, [x28, #1018]", - "ldrb w21, [x28, #1298]", - "lsl w22, w22, w20", - "bic w21, w21, w22", + "mov w21, #0x1", + "cset w22, vs", + "cset w23, eq", + "cset w24, mi", + "orr w24, w24, w22", + "strb w24, [x28, #1016]", + "orr w23, w23, w22", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", + "ldrb w22, [x28, #1298]", + "lsl w21, w21, w20", + "bic w21, w22, w21", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -697,7 +686,7 @@ ] }, "fcomp st0, st1": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 25, "Comment": [ "0xd8 11b 0xd9 /3" ], @@ -711,16 +700,15 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w22, #0x0", - "cset w23, vs", - "cset w24, eq", - "cset w25, mi", - "orr w25, w25, w23", - "strb w25, [x28, #1016]", - "orr w24, w24, w23", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w22, vs", + "cset w23, eq", + "cset w24, mi", + "orr w24, w24, w22", + "strb w24, [x28, #1016]", + "orr w23, w23, w22", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -731,7 +719,7 @@ ] }, "fcomp st0, st2": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 25, "Comment": [ "0xd8 11b 0xda /3" ], @@ -745,16 +733,15 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", - "cset w24, eq", - "cset w25, mi", - "orr w25, w25, w23", - "strb w25, [x28, #1016]", - "orr w24, w24, w23", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w22, vs", + "cset w23, eq", + "cset w24, mi", + "orr w24, w24, w22", + "strb w24, [x28, #1016]", + "orr w23, w23, w22", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -765,7 +752,7 @@ ] }, "fcomp st0, st3": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 25, "Comment": [ "0xd8 11b 0xdb /3" ], @@ -779,16 +766,15 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", - "cset w24, eq", - "cset w25, mi", - "orr w25, w25, w23", - "strb w25, [x28, #1016]", - "orr w24, w24, w23", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w22, vs", + "cset w23, eq", + "cset w24, mi", + "orr w24, w24, w22", + "strb w24, [x28, #1016]", + "orr w23, w23, w22", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -799,7 +785,7 @@ ] }, "fcomp st0, st4": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 25, "Comment": [ "0xd8 11b 0xdc /3" ], @@ -813,16 +799,15 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", - "cset w24, eq", - "cset w25, mi", - "orr w25, w25, w23", - "strb w25, [x28, #1016]", - "orr w24, w24, w23", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w22, vs", + "cset w23, eq", + "cset w24, mi", + "orr w24, w24, w22", + "strb w24, [x28, #1016]", + "orr w23, w23, w22", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -833,7 +818,7 @@ ] }, "fcomp st0, st5": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 25, "Comment": [ "0xd8 11b 0xdd /3" ], @@ -847,16 +832,15 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", - "cset w24, eq", - "cset w25, mi", - "orr w25, w25, w23", - "strb w25, [x28, #1016]", - "orr w24, w24, w23", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w22, vs", + "cset w23, eq", + "cset w24, mi", + "orr w24, w24, w22", + "strb w24, [x28, #1016]", + "orr w23, w23, w22", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -867,7 +851,7 @@ ] }, "fcomp st0, st6": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 25, "Comment": [ "0xd8 11b 0xde /3" ], @@ -881,16 +865,15 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", - "cset w24, eq", - "cset w25, mi", - "orr w25, w25, w23", - "strb w25, [x28, #1016]", - "orr w24, w24, w23", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w22, vs", + "cset w23, eq", + "cset w24, mi", + "orr w24, w24, w22", + "strb w24, [x28, #1016]", + "orr w23, w23, w22", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -901,7 +884,7 @@ ] }, "fcomp st0, st7": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 25, "Comment": [ "0xd8 11b 0xdf /3" ], @@ -915,16 +898,15 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", - "cset w24, eq", - "cset w25, mi", - "orr w25, w25, w23", - "strb w25, [x28, #1016]", - "orr w24, w24, w23", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w22, vs", + "cset w23, eq", + "cset w24, mi", + "orr w24, w24, w22", + "strb w24, [x28, #1016]", + "orr w23, w23, w22", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -1912,28 +1894,27 @@ ] }, "fxch st0, st0": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xc8 /1" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "strb w21, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]" ] }, "fxch st0, st1": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xc9 /1" ], @@ -1945,8 +1926,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -1954,7 +1934,7 @@ ] }, "fxch st0, st2": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xca /1" ], @@ -1966,8 +1946,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -1975,7 +1954,7 @@ ] }, "fxch st0, st3": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xcb /1" ], @@ -1987,8 +1966,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -1996,7 +1974,7 @@ ] }, "fxch st0, st4": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xcc /1" ], @@ -2008,8 +1986,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -2017,7 +1994,7 @@ ] }, "fxch st0, st5": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xcd /1" ], @@ -2029,8 +2006,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -2038,7 +2014,7 @@ ] }, "fxch st0, st6": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xce /1" ], @@ -2050,8 +2026,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -2059,7 +2034,7 @@ ] }, "fxch st0, st7": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xd9 11b 0xcf /1" ], @@ -2071,8 +2046,7 @@ "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x21, lsl #4", @@ -2126,15 +2100,15 @@ "mov w20, #0x0", "fmov d3, x20", "fcmp d2, d3", - "cset w21, vs", - "cset w22, eq", - "cset w23, mi", - "orr w23, w23, w21", - "strb w23, [x28, #1016]", - "orr w22, w22, w21", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w20, vs", + "cset w21, eq", + "cset w22, mi", + "orr w22, w22, w20", + "strb w22, [x28, #1016]", + "orr w21, w21, w20", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fxam": { @@ -2465,7 +2439,7 @@ ] }, "fptan": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 69, "Comment": [ "0xd9 11b 0xf2 /6" ], @@ -2533,8 +2507,7 @@ "mov v2.8b, v0.8b", "mov x23, #0x3ff0000000000000", "fmov d3, x23", - "mov w23, #0x0", - "strb w23, [x28, #1018]", + "strb wzr, [x28, #1018]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", "add x0, x28, x22, lsl #4", @@ -2649,7 +2622,7 @@ ] }, "fprem1": { - "ExpectedInstructionCount": 63, + "ExpectedInstructionCount": 62, "Comment": [ "0xd9 11b 0xf5 /6" ], @@ -2713,8 +2686,7 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "strb wzr, [x28, #1018]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -2744,7 +2716,7 @@ ] }, "fprem": { - "ExpectedInstructionCount": 63, + "ExpectedInstructionCount": 62, "Comment": [ "0xd9 11b 0xf8 /7" ], @@ -2808,8 +2780,7 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "strb wzr, [x28, #1018]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -2907,7 +2878,7 @@ ] }, "fsincos": { - "ExpectedInstructionCount": 119, + "ExpectedInstructionCount": 118, "Comment": [ "0xd9 11b 0xfb /7" ], @@ -3024,8 +2995,7 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "mov w23, #0x0", - "strb w23, [x28, #1018]", + "strb wzr, [x28, #1018]", "add x0, x28, x20, lsl #4", "str d3, [x0, #1040]", "add x0, x28, x22, lsl #4", @@ -3117,7 +3087,7 @@ ] }, "fsin": { - "ExpectedInstructionCount": 58, + "ExpectedInstructionCount": 57, "Comment": [ "0xd9 11b 0xfe /7" ], @@ -3176,14 +3146,13 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "strb wzr, [x28, #1018]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, "fcos": { - "ExpectedInstructionCount": 58, + "ExpectedInstructionCount": 57, "Comment": [ "0xd9 11b 0xff /7" ], @@ -3242,8 +3211,7 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "strb wzr, [x28, #1018]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -3281,7 +3249,7 @@ ] }, "ficom dword [rax]": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 15, "Comment": [ "0xda !11b /2" ], @@ -3292,20 +3260,19 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", - "cset w22, eq", - "cset w23, mi", - "orr w23, w23, w21", - "strb w23, [x28, #1016]", - "orr w22, w22, w21", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w20, vs", + "cset w21, eq", + "cset w22, mi", + "orr w22, w22, w20", + "strb w22, [x28, #1016]", + "orr w21, w21, w20", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "ficomp dword [rax]": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xda !11b /3" ], @@ -3317,16 +3284,15 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", - "cset w24, eq", - "cset w25, mi", - "orr w25, w25, w23", - "strb w25, [x28, #1016]", - "orr w24, w24, w23", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w22, vs", + "cset w23, eq", + "cset w24, mi", + "orr w24, w24, w22", + "strb w24, [x28, #1016]", + "orr w23, w23, w22", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -4105,7 +4071,7 @@ ] }, "fucompp": { - "ExpectedInstructionCount": 30, + "ExpectedInstructionCount": 29, "Comment": [ "0xda 11b 0xe9 /5" ], @@ -4119,16 +4085,15 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w22, #0x0", - "cset w23, vs", - "cset w24, eq", - "cset w25, mi", - "orr w25, w25, w23", - "strb w25, [x28, #1016]", - "orr w24, w24, w23", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w22, vs", + "cset w23, eq", + "cset w24, mi", + "orr w24, w24, w22", + "strb w24, [x28, #1016]", + "orr w23, w23, w22", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w23, w21, w20", "bic w22, w22, w23", @@ -5034,12 +4999,12 @@ "bfi x0, x1, #24, #1", "msr fpcr, x0", "strh w20, [x28, #1296]", - "strb w21, [x28, #1019]", - "strb w21, [x28, #1016]", - "strb w21, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w21, [x28, #1022]", - "strb w21, [x28, #1298]" + "strb wzr, [x28, #1019]", + "strb wzr, [x28, #1016]", + "strb wzr, [x28, #1017]", + "strb wzr, [x28, #1018]", + "strb wzr, [x28, #1022]", + "strb wzr, [x28, #1298]" ] }, "fucomi st0, st0": { @@ -5473,7 +5438,7 @@ ] }, "fcom qword [rax]": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Comment": [ "0xdc !11b /2" ], @@ -5483,20 +5448,19 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", - "cset w22, eq", - "cset w23, mi", - "orr w23, w23, w21", - "strb w23, [x28, #1016]", - "orr w22, w22, w21", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w20, vs", + "cset w21, eq", + "cset w22, mi", + "orr w22, w22, w20", + "strb w22, [x28, #1016]", + "orr w21, w21, w20", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcomp qword [rax]": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 22, "Comment": [ "0xdc !11b /3" ], @@ -5507,16 +5471,15 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", - "cset w24, eq", - "cset w25, mi", - "orr w25, w25, w23", - "strb w25, [x28, #1016]", - "orr w24, w24, w23", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w22, vs", + "cset w23, eq", + "cset w24, mi", + "orr w24, w24, w22", + "strb w24, [x28, #1016]", + "orr w23, w23, w22", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -7186,13 +7149,13 @@ "str h2, [x4, #106]", "mov w20, #0x37f", "strh w20, [x28, #1296]", - "strb w21, [x28, #1019]", - "strb w21, [x28, #1016]", - "strb w21, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w21, [x28, #1022]", + "strb wzr, [x28, #1019]", + "strb wzr, [x28, #1016]", + "strb wzr, [x28, #1017]", + "strb wzr, [x28, #1018]", + "strb wzr, [x28, #1022]", "msr nzcv, x25", - "strb w21, [x28, #1298]" + "strb wzr, [x28, #1298]" ] }, "fnstsw [rax]": { @@ -7703,33 +7666,32 @@ ] }, "fucom st0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xe0 /4" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", "cset w20, vs", - "cset w22, eq", - "cset w23, mi", - "orr w23, w23, w20", - "strb w23, [x28, #1016]", + "cset w21, eq", + "cset w22, mi", "orr w22, w22, w20", - "strb w22, [x28, #1022]", - "strb w21, [x28, #1017]", + "strb w22, [x28, #1016]", + "orr w21, w21, w20", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]" ] }, "fucom st1": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xe1 /4" ], @@ -7742,20 +7704,19 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", - "cset w22, eq", - "cset w23, mi", - "orr w23, w23, w21", - "strb w23, [x28, #1016]", - "orr w22, w22, w21", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w20, vs", + "cset w21, eq", + "cset w22, mi", + "orr w22, w22, w20", + "strb w22, [x28, #1016]", + "orr w21, w21, w20", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucom st2": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xe2 /4" ], @@ -7768,20 +7729,19 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", - "cset w22, eq", - "cset w23, mi", - "orr w23, w23, w21", - "strb w23, [x28, #1016]", - "orr w22, w22, w21", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w20, vs", + "cset w21, eq", + "cset w22, mi", + "orr w22, w22, w20", + "strb w22, [x28, #1016]", + "orr w21, w21, w20", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucom st3": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xe3 /4" ], @@ -7794,20 +7754,19 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", - "cset w22, eq", - "cset w23, mi", - "orr w23, w23, w21", - "strb w23, [x28, #1016]", - "orr w22, w22, w21", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w20, vs", + "cset w21, eq", + "cset w22, mi", + "orr w22, w22, w20", + "strb w22, [x28, #1016]", + "orr w21, w21, w20", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucom st4": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xe4 /4" ], @@ -7820,20 +7779,19 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", - "cset w22, eq", - "cset w23, mi", - "orr w23, w23, w21", - "strb w23, [x28, #1016]", - "orr w22, w22, w21", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w20, vs", + "cset w21, eq", + "cset w22, mi", + "orr w22, w22, w20", + "strb w22, [x28, #1016]", + "orr w21, w21, w20", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucom st5": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xe5 /4" ], @@ -7846,20 +7804,19 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", - "cset w22, eq", - "cset w23, mi", - "orr w23, w23, w21", - "strb w23, [x28, #1016]", - "orr w22, w22, w21", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w20, vs", + "cset w21, eq", + "cset w22, mi", + "orr w22, w22, w20", + "strb w22, [x28, #1016]", + "orr w21, w21, w20", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucom st6": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xe6 /4" ], @@ -7872,20 +7829,19 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", - "cset w22, eq", - "cset w23, mi", - "orr w23, w23, w21", - "strb w23, [x28, #1016]", - "orr w22, w22, w21", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w20, vs", + "cset w21, eq", + "cset w22, mi", + "orr w22, w22, w20", + "strb w22, [x28, #1016]", + "orr w21, w21, w20", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucom st7": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xe7 /4" ], @@ -7898,46 +7854,44 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", - "cset w22, eq", - "cset w23, mi", - "orr w23, w23, w21", - "strb w23, [x28, #1016]", - "orr w22, w22, w21", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w20, vs", + "cset w21, eq", + "cset w22, mi", + "orr w22, w22, w20", + "strb w22, [x28, #1016]", + "orr w21, w21, w20", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucomp st0": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 25, "Comment": [ "0xdd 11b 0xe8 /5" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w22, #0x1", - "cset w23, vs", - "cset w24, eq", - "cset w25, mi", - "orr w25, w25, w23", - "strb w25, [x28, #1016]", - "orr w24, w24, w23", - "strb w24, [x28, #1022]", - "strb w21, [x28, #1017]", - "strb w23, [x28, #1018]", - "ldrb w21, [x28, #1298]", - "lsl w22, w22, w20", - "bic w21, w21, w22", + "mov w21, #0x1", + "cset w22, vs", + "cset w23, eq", + "cset w24, mi", + "orr w24, w24, w22", + "strb w24, [x28, #1016]", + "orr w23, w23, w22", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", + "ldrb w22, [x28, #1298]", + "lsl w21, w21, w20", + "bic w21, w22, w21", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -7945,7 +7899,7 @@ ] }, "fucomp st1": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 25, "Comment": [ "0xdd 11b 0xe9 /5" ], @@ -7959,16 +7913,15 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w22, #0x0", - "cset w23, vs", - "cset w24, eq", - "cset w25, mi", - "orr w25, w25, w23", - "strb w25, [x28, #1016]", - "orr w24, w24, w23", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w22, vs", + "cset w23, eq", + "cset w24, mi", + "orr w24, w24, w22", + "strb w24, [x28, #1016]", + "orr w23, w23, w22", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -7979,7 +7932,7 @@ ] }, "fucomp st2": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 25, "Comment": [ "0xdd 11b 0xea /5" ], @@ -7993,16 +7946,15 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", - "cset w24, eq", - "cset w25, mi", - "orr w25, w25, w23", - "strb w25, [x28, #1016]", - "orr w24, w24, w23", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w22, vs", + "cset w23, eq", + "cset w24, mi", + "orr w24, w24, w22", + "strb w24, [x28, #1016]", + "orr w23, w23, w22", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -8013,7 +7965,7 @@ ] }, "fucomp st3": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 25, "Comment": [ "0xdd 11b 0xeb /5" ], @@ -8027,16 +7979,15 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", - "cset w24, eq", - "cset w25, mi", - "orr w25, w25, w23", - "strb w25, [x28, #1016]", - "orr w24, w24, w23", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w22, vs", + "cset w23, eq", + "cset w24, mi", + "orr w24, w24, w22", + "strb w24, [x28, #1016]", + "orr w23, w23, w22", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -8047,7 +7998,7 @@ ] }, "fucomp st4": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 25, "Comment": [ "0xdd 11b 0xec /5" ], @@ -8061,16 +8012,15 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", - "cset w24, eq", - "cset w25, mi", - "orr w25, w25, w23", - "strb w25, [x28, #1016]", - "orr w24, w24, w23", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w22, vs", + "cset w23, eq", + "cset w24, mi", + "orr w24, w24, w22", + "strb w24, [x28, #1016]", + "orr w23, w23, w22", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -8081,7 +8031,7 @@ ] }, "fucomp st5": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 25, "Comment": [ "0xdd 11b 0xed /5" ], @@ -8095,16 +8045,15 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", - "cset w24, eq", - "cset w25, mi", - "orr w25, w25, w23", - "strb w25, [x28, #1016]", - "orr w24, w24, w23", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w22, vs", + "cset w23, eq", + "cset w24, mi", + "orr w24, w24, w22", + "strb w24, [x28, #1016]", + "orr w23, w23, w22", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -8115,7 +8064,7 @@ ] }, "fucomp st6": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 25, "Comment": [ "0xdd 11b 0xee /5" ], @@ -8129,16 +8078,15 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", - "cset w24, eq", - "cset w25, mi", - "orr w25, w25, w23", - "strb w25, [x28, #1016]", - "orr w24, w24, w23", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w22, vs", + "cset w23, eq", + "cset w24, mi", + "orr w24, w24, w22", + "strb w24, [x28, #1016]", + "orr w23, w23, w22", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -8149,7 +8097,7 @@ ] }, "fucomp st7": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 25, "Comment": [ "0xdd 11b 0xef /5" ], @@ -8163,16 +8111,15 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", - "cset w24, eq", - "cset w25, mi", - "orr w25, w25, w23", - "strb w25, [x28, #1016]", - "orr w24, w24, w23", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w22, vs", + "cset w23, eq", + "cset w24, mi", + "orr w24, w24, w22", + "strb w24, [x28, #1016]", + "orr w23, w23, w22", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -8217,7 +8164,7 @@ ] }, "ficom word [rax]": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": [ "0xde !11b /2" ], @@ -8229,20 +8176,19 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", - "cset w22, eq", - "cset w23, mi", - "orr w23, w23, w21", - "strb w23, [x28, #1016]", - "orr w22, w22, w21", - "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "cset w20, vs", + "cset w21, eq", + "cset w22, mi", + "orr w22, w22, w20", + "strb w22, [x28, #1016]", + "orr w21, w21, w20", + "strb w21, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "ficomp word [rax]": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 24, "Comment": [ "0xde !11b /3" ], @@ -8255,16 +8201,15 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "mov w21, #0x1", - "mov w22, #0x0", - "cset w23, vs", - "cset w24, eq", - "cset w25, mi", - "orr w25, w25, w23", - "strb w25, [x28, #1016]", - "orr w24, w24, w23", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w22, vs", + "cset w23, eq", + "cset w24, mi", + "orr w24, w24, w22", + "strb w24, [x28, #1016]", + "orr w23, w23, w22", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -8759,7 +8704,7 @@ ] }, "fcompp": { - "ExpectedInstructionCount": 30, + "ExpectedInstructionCount": 29, "Comment": [ "0xde 11b 0xd9 /3" ], @@ -8773,16 +8718,15 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w22, #0x0", - "cset w23, vs", - "cset w24, eq", - "cset w25, mi", - "orr w25, w25, w23", - "strb w25, [x28, #1016]", - "orr w24, w24, w23", - "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", - "strb w23, [x28, #1018]", + "cset w22, vs", + "cset w23, eq", + "cset w24, mi", + "orr w24, w24, w22", + "strb w24, [x28, #1016]", + "orr w23, w23, w22", + "strb w23, [x28, #1022]", + "strb wzr, [x28, #1017]", + "strb w22, [x28, #1018]", "ldrb w22, [x28, #1298]", "lsl w23, w21, w20", "bic w22, w22, w23",