From cbda688e296880fae92e075cea043c2c8bdb1a23 Mon Sep 17 00:00:00 2001 From: Paulo Matos Date: Fri, 10 Jan 2025 12:51:14 +0100 Subject: [PATCH] Revert "Cache predicate register generation from pattern" This reverts commit 72a40636515aaa8986f500ce7f4c5cb546d6127f. Caused #4264 --- FEXCore/Scripts/json_ir_generator.py | 2 +- .../Interface/Core/OpcodeDispatcher.cpp | 4 +-- .../Source/Interface/Core/OpcodeDispatcher.h | 3 -- FEXCore/Source/Interface/IR/IREmitter.cpp | 1 - FEXCore/Source/Interface/IR/IREmitter.h | 34 +------------------ .../IR/Passes/x87StackOptimizationPass.cpp | 2 +- 6 files changed, 5 insertions(+), 41 deletions(-) diff --git a/FEXCore/Scripts/json_ir_generator.py b/FEXCore/Scripts/json_ir_generator.py index 8ef4842249..cda8d9c509 100755 --- a/FEXCore/Scripts/json_ir_generator.py +++ b/FEXCore/Scripts/json_ir_generator.py @@ -223,7 +223,7 @@ def parse_ops(ops): (OpArg.Type == "GPR" or OpArg.Type == "GPRPair" or OpArg.Type == "FPR" or - OpArg.Type == "PRED")): + OpArg.Type == "PR")): OpDef.EmitValidation.append(f"GetOpRegClass({ArgName}) == InvalidClass || WalkFindRegClass({ArgName}) == {OpArg.Type}Class") OpArg.Name = ArgName diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index f729823364..6dd2d8b108 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -4314,7 +4314,7 @@ Ref OpDispatchBuilder::LoadSource_WithOpSize(RegisterClassType Class, const X86T Ref MemSrc = LoadEffectiveAddress(A, true); if (CTX->HostFeatures.SupportsSVE128 || CTX->HostFeatures.SupportsSVE256) { // Using SVE we can load this with a single instruction. - auto PReg = InitPredicateCached(OpSize::i16Bit, ARMEmitter::PredicatePattern::SVE_VL5); + auto PReg = _InitPredicate(OpSize::i16Bit, FEXCore::ToUnderlying(ARMEmitter::PredicatePattern::SVE_VL5)); return _LoadMemPredicate(OpSize::i128Bit, OpSize::i16Bit, PReg, MemSrc); } else { // For X87 extended doubles, Split the load. @@ -4448,7 +4448,7 @@ void OpDispatchBuilder::StoreResult_WithOpSize(FEXCore::IR::RegisterClassType Cl if (OpSize == OpSize::f80Bit) { Ref MemStoreDst = LoadEffectiveAddress(A, true); if (CTX->HostFeatures.SupportsSVE128 || CTX->HostFeatures.SupportsSVE256) { - auto PReg = InitPredicateCached(OpSize::i16Bit, ARMEmitter::PredicatePattern::SVE_VL5); + auto PReg = _InitPredicate(OpSize::i16Bit, FEXCore::ToUnderlying(ARMEmitter::PredicatePattern::SVE_VL5)); _StoreMemPredicate(OpSize::i128Bit, OpSize::i16Bit, Src, PReg, MemStoreDst); } else { // For X87 extended doubles, split before storing diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index 46a4019a4a..9545e87612 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -125,9 +125,6 @@ class OpDispatchBuilder final : public IREmitter { // Need to clear any named constants that were cached. ClearCachedNamedConstants(); - - // Clear predicate cache for x87 ldst - ResetInitPredicateCache(); } IRPair Jump() { diff --git a/FEXCore/Source/Interface/IR/IREmitter.cpp b/FEXCore/Source/Interface/IR/IREmitter.cpp index 95cb2e73dd..0850187b1c 100644 --- a/FEXCore/Source/Interface/IR/IREmitter.cpp +++ b/FEXCore/Source/Interface/IR/IREmitter.cpp @@ -41,7 +41,6 @@ FEXCore::IR::RegisterClassType IREmitter::WalkFindRegClass(Ref Node) { case FPRClass: case GPRFixedClass: case FPRFixedClass: - case PREDClass: case InvalidClass: return Class; default: break; } diff --git a/FEXCore/Source/Interface/IR/IREmitter.h b/FEXCore/Source/Interface/IR/IREmitter.h index c5af4efdd3..0cfc4027be 100644 --- a/FEXCore/Source/Interface/IR/IREmitter.h +++ b/FEXCore/Source/Interface/IR/IREmitter.h @@ -1,7 +1,6 @@ // SPDX-License-Identifier: MIT #pragma once -#include "CodeEmitter/Emitter.h" #include "Interface/IR/IR.h" #include "Interface/IR/IntrusiveIRList.h" @@ -10,9 +9,9 @@ #include #include -#include #include +#include #include #include @@ -46,37 +45,6 @@ class IREmitter { } void ResetWorkingList(); - // Predicate Cache Implementation - // This lives here rather than OpcodeDispatcher because x87StackOptimization Pass - // also needs it. - struct PredicateKey { - ARMEmitter::PredicatePattern Pattern; - OpSize Size; - bool operator==(const PredicateKey& rhs) const = default; - }; - - struct PredicateKeyHash { - size_t operator()(const PredicateKey& key) const { - return FEXCore::ToUnderlying(key.Pattern) + (FEXCore::ToUnderlying(key.Size) * FEXCore::ToUnderlying(OpSize::iInvalid)); - } - }; - fextl::unordered_map InitPredicateCache; - - Ref InitPredicateCached(OpSize Size, ARMEmitter::PredicatePattern Pattern) { - PredicateKey Key {Pattern, Size}; - auto ValIt = InitPredicateCache.find(Key); - if (ValIt == InitPredicateCache.end()) { - auto Predicate = _InitPredicate(Size, static_cast(FEXCore::ToUnderlying(Pattern))); - InitPredicateCache[Key] = Predicate; - return Predicate; - } - return ValIt->second; - } - - void ResetInitPredicateCache() { - InitPredicateCache.clear(); - } - /** * @name IR allocation routines * diff --git a/FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp b/FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp index 1dd1f58823..247b54633e 100644 --- a/FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp +++ b/FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp @@ -824,7 +824,7 @@ void X87StackOptimization::Run(IREmitter* Emit) { } if (Op->StoreSize == OpSize::f80Bit) { // Part of code from StoreResult_WithOpSize() if (Features.SupportsSVE128 || Features.SupportsSVE256) { - auto PReg = IREmit->InitPredicateCached(OpSize::i16Bit, ARMEmitter::PredicatePattern::SVE_VL5); + auto PReg = IREmit->_InitPredicate(OpSize::i16Bit, FEXCore::ToUnderlying(ARMEmitter::PredicatePattern::SVE_VL5)); IREmit->_StoreMemPredicate(OpSize::i128Bit, OpSize::i16Bit, StackNode, PReg, AddrNode); } else { // For X87 extended doubles, split before storing