hive/daughterboard/ESP32_SIFIVE_00 at new-design · probe-rs/hive · GitHub

Name		Name	Last commit message	Last commit date
parent directory ..
component_library		component_library
.gitignore		.gitignore
ESP32_SIFIVE_00-cache.lib		ESP32_SIFIVE_00-cache.lib
ESP32_SIFIVE_00.kicad_pcb		ESP32_SIFIVE_00.kicad_pcb
ESP32_SIFIVE_00.pro		ESP32_SIFIVE_00.pro
ESP32_SIFIVE_00.sch		ESP32_SIFIVE_00.sch
README.md		README.md
fp-info-cache		fp-info-cache
fp-lib-table		fp-lib-table
sym-lib-table		sym-lib-table
target0.sch		target0.sch
target1.sch		target1.sch
target2.sch		target2.sch
target3.sch		target3.sch

README.md

Daughterboard ESP32_SIFIVE_00

This board features RISC-V and Xtensa cores.

Targets

The following targets are implemented on this Daughterboard:

Designation	MCU
target0	ESP32-S3-WROOM-1-N8R8
target1	ESP32-S2
target2	LOFIVE-R1 (FE310-G002)
target3	ESP32-C3

Partlist

The partlist for this Daughterboard is available here.

Other

The target3 and target1 devices have separate flash memory, as the currently available cores do not have any embedded flash.