diff --git a/Bender.yml b/Bender.yml index 1227d06b..75a7e25f 100644 --- a/Bender.yml +++ b/Bender.yml @@ -10,7 +10,11 @@ package: dependencies: tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.1.1 } +export_include_dirs: + - include + sources: + - src/shift_reg.sv - src/fifo_v1.sv - src/fifo_v2.sv - src/fifo_v3.sv @@ -20,6 +24,7 @@ sources: - src/stream_register.sv - src/stream_mux.sv - src/stream_demux.sv + - src/popcount.sv - src/cdc_2phase.sv - src/cdc_fifo_2phase.sv - src/cdc_fifo_gray.sv @@ -31,6 +36,7 @@ sources: - src/edge_propagator.sv - src/lzc.sv - src/rrarbiter.sv + - src/stream_arbiter_flushable.sv - src/stream_arbiter.sv - src/sync_wedge.sv - src/sync.sv @@ -39,6 +45,7 @@ sources: - src/edge_detect.sv - src/serial_deglitch.sv - src/counter.sv + - src/stream_delay.sv - src/mv_filter.sv - target: simulation diff --git a/CHANGELOG.md b/CHANGELOG.md index a785852a..3885d46a 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -4,15 +4,24 @@ All notable changes to this project will be documented in this file. The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/) and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html). -## Unreleased +## 1.10.0 - 2018-12-18 +### Added - Add `fifo_v3` with generic fill count - Add 16 bit LFSR -- Add ready/valid handshake delayer +- Add stream delayer - Add stream arbiter +- Add register macros for RTL +- Add shift register + +### Changed +- Make number of registers of `rstgen_bypass` a parameter. ### Fixed - Fix `valid_i` and `grant_i` guarantees in `generic_fifo` for backward compatibility. +- LZC: Synthesis of streaming operators in ternary operators +- Add missing entry for `popcount` to `Bender.yml`. +- Add default values for parameters to improve compatibility with Synopsys DC and Vivado. ## 1.9.0 - 2018-11-02 diff --git a/README.md b/README.md index 2b195483..5a8764bc 100644 --- a/README.md +++ b/README.md @@ -55,7 +55,7 @@ Please note that cells with status *deprecated* are not to be used for new desig | `gray_to_binary` | Gray code to binary converter | active | | `lzc` | Leading/trailing-zero counter | active | | `onehot_to_bin` | One-hot to binary converter | active | -| `pipe_reg_simple` | Pipeline register for arbitrary types | active | +| `shift_reg` | Shift register for arbitrary types | active | | `rrarbiter` | Round-robin arbiter for req/ack interface with look-ahead | active | | `spill_register` | Register with ready/valid interface to cut all combinational interface paths | active | | `stream_arbiter` | Round-robin arbiter for ready/valid stream interface | active | @@ -63,7 +63,7 @@ Please note that cells with status *deprecated* are not to be used for new desig | `stream_demux` | Ready/valid interface demultiplexer | active | | `stream_mux` | Ready/valid interface multiplexer | active | | `stream_register` | Register with ready/valid interface | active | -| `ready_valid_delay` | Randomize or delay ready/valid interface | active | +| `stream_delay` | Randomize or delay ready/valid interface | active | | `popcount` | Combinatorial popcount (hamming weight) | active | ### Data Structures @@ -83,9 +83,9 @@ Please note that cells with status *deprecated* are not to be used for new desig This repository currently contains the following header files. -### Register Header +### RTL Register Macros -The register header file `register_defines.svh` contains macros that expand to descriptions of registers. +The header file `registers.svh` contains macros that expand to descriptions of registers. To avoid misuse of `always_ff` blocks, only the following macros shall be used to describe sequential behavior. The use of linter rules that flag explicit uses of `always_ff` in source code is encouraged. diff --git a/header/register_defines.svh b/include/common_cells/registers.svh similarity index 91% rename from header/register_defines.svh rename to include/common_cells/registers.svh index bd027b5d..5be1ff40 100644 --- a/header/register_defines.svh +++ b/include/common_cells/registers.svh @@ -1,6 +1,17 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + // Common register defines for RTL designs -`ifndef REGISTER_DEFINES_H_ -`define REGISTER_DEFINES_H_ +`ifndef COMMON_CELLS_REGISTERS_SVH_ +`define COMMON_CELLS_REGISTERS_SVH_ // Abridged Summary of available FF macros: // `FF: asynchronous active-low reset (implicit clock and reset) diff --git a/src/deprecated/find_first_one.sv b/src/deprecated/find_first_one.sv index c4100566..ee3ba20f 100644 --- a/src/deprecated/find_first_one.sv +++ b/src/deprecated/find_first_one.sv @@ -1,16 +1,13 @@ -// Copyright (c) 2018 ETH Zurich, University of Bologna -// All rights reserved. +// Copyright 2018 ETH Zurich and University of Bologna. // -// This code is under development and not yet released to the public. -// Until it is released, the code is under the copyright of ETH Zurich and -// the University of Bologna, and may contain confidential and/or unpublished -// work. Any reuse/redistribution is strictly forbidden without written -// permission from ETH Zurich. -// -// Bug fixes and contributions will eventually be released under the -// SolderPad open hardware license in the context of the PULP platform -// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the -// University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. // Deprecated, use lzc unit instead. diff --git a/src/lzc.sv b/src/lzc.sv index e195a367..5f65f892 100644 --- a/src/lzc.sv +++ b/src/lzc.sv @@ -41,7 +41,11 @@ module lzc #( logic [WIDTH-1:0] in_tmp; // reverse vector if required - assign in_tmp = MODE ? {<<{in_i}} : in_i; + always_comb begin : flip_vector + in_tmp = in_i; + if (MODE) + in_tmp = {<< {in_i}}; + end for (genvar j = 0; j < WIDTH; j++) begin : g_index_lut assign index_lut[j] = j; diff --git a/src/popcount.sv b/src/popcount.sv index a4e5a9b9..0e164531 100644 --- a/src/popcount.sv +++ b/src/popcount.sv @@ -1,16 +1,3 @@ -//----------------------------------------------------------------------------- -// Title : Popcount -//----------------------------------------------------------------------------- -// File : popcount.sv -// Author : Manuel Eggimann -// Created : 01.11.2018 -//----------------------------------------------------------------------------- -// Description : -// This module calculates the hamming weight (number of ones) in its input vector using a -// balanced binary adder tree. Recursive instantiation is used to build the tree. -// Any unsigned INPUT_WIDTH larger or equal 2 is legal. The module pads the signal internally -// to the next power of two. The output result width is ceil(log2(INPUT_WIDTH))+1. -//----------------------------------------------------------------------------- // Copyright (C) 2013-2018 ETH Zurich, University of Bologna // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the "License"); you may not use this file except in @@ -20,7 +7,14 @@ // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. -//----------------------------------------------------------------------------- + +// Author: Manuel Eggimann + +// Description: This module calculates the hamming weight (number of ones) in +// its input vector using a balanced binary adder tree. Recursive instantiation +// is used to build the tree. Any unsigned INPUT_WIDTH larger or equal 2 is +// legal. The module pads the signal internally to the next power of two. The +// output result width is ceil(log2(INPUT_WIDTH))+1. module popcount #( parameter int unsigned INPUT_WIDTH = 256, diff --git a/src/pipe_reg_simple.sv b/src/shift_reg.sv similarity index 98% rename from src/pipe_reg_simple.sv rename to src/shift_reg.sv index 15a8eb04..cbfab0e7 100644 --- a/src/pipe_reg_simple.sv +++ b/src/shift_reg.sv @@ -13,7 +13,7 @@ // // Description: Simple shift register for arbitrary depth and types -module pipe_reg_simple #( +module shift_reg #( parameter type dtype = logic, parameter int unsigned Depth = 1 )( diff --git a/src/spill_register.sv b/src/spill_register.sv index 7c12c915..6a99c89e 100644 --- a/src/spill_register.sv +++ b/src/spill_register.sv @@ -1,16 +1,13 @@ -// Copyright (c) 2018 ETH Zurich, University of Bologna -// All rights reserved. +// Copyright 2018 ETH Zurich and University of Bologna. // -// This code is under development and not yet released to the public. -// Until it is released, the code is under the copyright of ETH Zurich and -// the University of Bologna, and may contain confidential and/or unpublished -// work. Any reuse/redistribution is strictly forbidden without written -// permission from ETH Zurich. -// -// Bug fixes and contributions will eventually be released under the -// SolderPad open hardware license in the context of the PULP platform -// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the -// University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. // // Fabian Schuiki diff --git a/src/stream_arbiter.sv b/src/stream_arbiter.sv index 773ffb3d..8f9e4053 100644 --- a/src/stream_arbiter.sv +++ b/src/stream_arbiter.sv @@ -14,8 +14,8 @@ // arbitration scheme is round-robin with "look ahead", see the `rrarbiter` for details. module stream_arbiter #( - parameter type DATA_T = logic, // Vivado requires a default value for type parameters. - parameter integer N_INP + parameter type DATA_T = logic, // Vivado requires a default value for type parameters. + parameter integer N_INP = -1 // Synopsys DC requires a default value for parameters. ) ( input logic clk_i, input logic rst_ni, @@ -29,27 +29,19 @@ module stream_arbiter #( input logic oup_ready_i ); - logic [$clog2(N_INP)-1:0] idx; - - rrarbiter #( - .NUM_REQ (N_INP), - // Lock arbitration decision once the output is valid and until the handshake happens. - .LOCK_IN (1) - ) i_arbiter ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .flush_i (1'b0), - .en_i (oup_ready_i), - .req_i (inp_valid_i), - .ack_o (inp_ready_o), - // The `vld_o` port of `rrarbiter` combinatorially depends on `en_i`. In the stream protocol, - // a valid may not depend on a ready, so we drive `oup_valid_o` from the `inp_valid_i`s in (1) - // and leave `vld_o` unconnected. - .vld_o (), - .idx_o (idx) + stream_arbiter_flushable #( + .DATA_T (DATA_T), + .N_INP (N_INP) + ) i_arb ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (1'b0), + .inp_data_i (inp_data_i), + .inp_valid_i (inp_valid_i), + .inp_ready_o (inp_ready_o), + .oup_data_o (oup_data_o), + .oup_valid_o (oup_valid_o), + .oup_ready_i (oup_ready_i) ); - assign oup_valid_o = (|inp_valid_i); // (1), see reference above. - assign oup_data_o = inp_data_i[idx]; - endmodule diff --git a/src/stream_arbiter_flushable.sv b/src/stream_arbiter_flushable.sv index 9caa87da..4b1457ad 100644 --- a/src/stream_arbiter_flushable.sv +++ b/src/stream_arbiter_flushable.sv @@ -14,8 +14,8 @@ // arbitration scheme is round-robin with "look ahead", see the `rrarbiter` for details. module stream_arbiter_flushable #( - parameter type DATA_T = logic, // Vivado requires a default value for type parameters. - parameter integer N_INP + parameter type DATA_T = logic, // Vivado requires a default value for type parameters. + parameter integer N_INP = -1 // Synopsys DC requires a default value for parameters. ) ( input logic clk_i, input logic rst_ni, diff --git a/src/ready_valid_delay.sv b/src/stream_delay.sv similarity index 99% rename from src/ready_valid_delay.sv rename to src/stream_delay.sv index f0d70858..e0b6b01f 100644 --- a/src/ready_valid_delay.sv +++ b/src/stream_delay.sv @@ -11,7 +11,7 @@ // Author: Florian Zaruba, zarubaf@iis.ee.ethz.ch // Description: Delay (or randomize) AXI-like handshaking -module ready_valid_delay #( +module stream_delay #( parameter bit StallRandom = 0, parameter int FixedDelay = 1, parameter type payload_t = logic diff --git a/src/stream_mux.sv b/src/stream_mux.sv index 30364c9f..fe276075 100644 --- a/src/stream_mux.sv +++ b/src/stream_mux.sv @@ -13,7 +13,7 @@ module stream_mux #( parameter type DATA_T = logic, // Vivado requires a default value for type parameters. - parameter integer N_INP, + parameter integer N_INP = 0, // Synopsys DC requires a default value for value parameters. /// Dependent parameters, DO NOT OVERRIDE! localparam integer LOG_N_INP = $clog2(N_INP) ) ( @@ -35,4 +35,12 @@ module stream_mux #( assign oup_data_o = inp_data_i[inp_sel_i]; assign oup_valid_o = inp_valid_i[inp_sel_i]; +// pragma translate_off +`ifndef VERILATOR + initial begin: p_assertions + assert (N_INP >= 1) else $fatal ("The number of inputs must be at least 1!"); + end +`endif +// pragma translate_on + endmodule diff --git a/src/stream_register.sv b/src/stream_register.sv index 3457bcae..35829b04 100644 --- a/src/stream_register.sv +++ b/src/stream_register.sv @@ -12,7 +12,7 @@ /// This register does not cut combinatorial paths on all control signals; if you need a complete /// cut, use the `spill_register`. module stream_register #( - parameter type T + parameter type T = logic // Vivado requires a default value for type parameters. ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous active-low reset diff --git a/src_files.yml b/src_files.yml index b6094125..5c8cd04c 100644 --- a/src_files.yml +++ b/src_files.yml @@ -1,5 +1,6 @@ common_cells_all: files: + - src/shift_reg.sv - src/fifo_v1.sv - src/fifo_v2.sv - src/fifo_v3.sv @@ -25,6 +26,7 @@ common_cells_all: - src/edge_detect.sv - src/serial_deglitch.sv - src/counter.sv + - src/stream_delay.sv - src/mv_filter.sv - src/popcount.sv