From a0525f7564cf28f1d4a3f54d075ff97f16f6a95c Mon Sep 17 00:00:00 2001
From: Michael Platzer <michael.platzer@axelera.ai>
Date: Tue, 3 Sep 2024 09:41:16 +0000
Subject: [PATCH] Avoid wide signals in sensitivity lists of immediate
assertions
Verilator has decent support for various types of assertions by now but
dislikes wide signals (e.g., wider than 64 bits) in sensitivity lists.
---
src/addr_decode_dync.sv | 2 +-
src/multiaddr_decode.sv | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/addr_decode_dync.sv b/src/addr_decode_dync.sv
index 03d19808..4dadc5e2 100644
--- a/src/addr_decode_dync.sv
+++ b/src/addr_decode_dync.sv
@@ -146,7 +146,7 @@ module addr_decode_dync #(
// check_start: Enforces a smaller start than end address.
// check_idx: Enforces a valid index in the rule.
// check_overlap: Warns if there are overlapping address regions.
- always @(addr_map_i or config_ongoing_i) #0 begin : proc_check_addr_map
+ always @* begin : proc_check_addr_map
if (!$isunknown(addr_map_i) && ~config_ongoing_i) begin
for (int unsigned i = 0; i < NoRules; i++) begin
check_start : assume (Napot || addr_map_i[i].start_addr < addr_map_i[i].end_addr ||
diff --git a/src/multiaddr_decode.sv b/src/multiaddr_decode.sv
index a6589b76..3c3de9dd 100644
--- a/src/multiaddr_decode.sv
+++ b/src/multiaddr_decode.sv
@@ -133,7 +133,7 @@ module multiaddr_decode #(
// These following assumptions check the validity of the address map.
// check_idx: Enforces a valid index in the rule.
- always @(addr_map_i) #0 begin : proc_check_addr_map
+ always @* begin : proc_check_addr_map
if (!$isunknown(addr_map_i)) begin
for (int unsigned i = 0; i < NoRules; i++) begin
// check the SLV ids