diff --git a/src/lfsr.sv b/src/lfsr.sv index 433b3f54..0b730d62 100644 --- a/src/lfsr.sv +++ b/src/lfsr.sv @@ -20,13 +20,13 @@ // of 64bit, since the block cipher has been designed for that block length. module lfsr #( - parameter int unsigned LfsrWidth = 64, // [4,64] - parameter int unsigned OutWidth = 8, // [1,LfsrWidth] - parameter logic [LfsrWidth-1:0] RstVal = '1, // [1,2^LfsrWidth-1] + parameter int unsigned LfsrWidth = 64, // [4,64] + parameter int unsigned OutWidth = 8, // [1,LfsrWidth] + parameter logic [LfsrWidth-1:0] RstVal = '1, // [1,2^LfsrWidth-1] // 0: disabled, the present cipher uses 31, but just a few layers (1-3) are enough // to break linear shifting patterns parameter int unsigned CipherLayers = 0, - parameter bit CipherReg = 1'b1 // additional output reg after cipher + parameter bit CipherReg = 1'b1 // additional output reg after cipher ) ( input logic clk_i, input logic rst_ni, @@ -121,7 +121,7 @@ localparam logic[63:0][5:0] perm = {6'd63, 6'd47, 6'd31, 6'd15, 6'd62, 6'd46, 6' 6'd51, 6'd35, 6'd19, 6'd03, 6'd50, 6'd34, 6'd18, 6'd02, 6'd49, 6'd33, 6'd17, 6'd01, 6'd48, 6'd32, 6'd16, 6'd00}; -function logic [63:0] sbox4_layer(logic [63:0] in); +function automatic logic [63:0] sbox4_layer(logic [63:0] in); logic [63:0] out; //for (logic [4:0] j = '0; j<16; j++) out[j*4 +: 4] = sbox4[in[j*4 +: 4]]; // this simulates much faster than the loop @@ -147,7 +147,7 @@ function logic [63:0] sbox4_layer(logic [63:0] in); return out; endfunction : sbox4_layer -function logic [63:0] perm_layer(logic [63:0] in); +function automatic logic [63:0] perm_layer(logic [63:0] in); logic [63:0] out; // for (logic [7:0] j = '0; j<64; j++) out[perm[j]] = in[j]; // this simulates much faster than the loop @@ -244,14 +244,14 @@ end // block cipher layers //////////////////////////////////////////////////////////////////////// -if (CipherLayers > 0) begin : g_cipher_layers +if (CipherLayers > unsigned'(0)) begin : g_cipher_layers logic [63:0] ciph_layer; localparam int unsigned NumRepl = ((64+LfsrWidth)/LfsrWidth); always_comb begin : p_ciph_layer automatic logic [63:0] tmp; tmp = 64'({NumRepl{lfsr_q}}); - for(int k = 0; k < CipherLayers; k++) begin + for(int unsigned k = 0; k < CipherLayers; k++) begin tmp = perm_layer(sbox4_layer(tmp)); end ciph_layer = tmp; @@ -264,7 +264,7 @@ if (CipherLayers > 0) begin : g_cipher_layers assign out_d = (en_i) ? ciph_layer[OutWidth-1:0] : out_q; assign out_o = out_q[OutWidth-1:0]; - always_ff @(posedge clk_i or negedge rst_ni) begin : p_p + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs if (!rst_ni) begin out_q <= '0; end else begin @@ -290,7 +290,7 @@ initial begin // these are the LUT limits assert(OutWidth <= LfsrWidth) else $fatal(1,"OutWidth must be smaller equal the LfsrWidth."); - assert(RstVal > 0) else + assert(RstVal > unsigned'(0)) else $fatal(1,"RstVal must be nonzero."); assert((LfsrWidth >= $low(masks)) && (LfsrWidth <= $high(masks))) else $fatal(1,"Unsupported LfsrWidth."); diff --git a/src/lzc.sv b/src/lzc.sv index 02313ac2..4ebbb5f5 100644 --- a/src/lzc.sv +++ b/src/lzc.sv @@ -55,7 +55,7 @@ module lzc #( end for (genvar j = 0; unsigned'(j) < WIDTH; j++) begin : g_index_lut - assign index_lut[j] = NUM_LEVELS'(j); + assign index_lut[j] = NUM_LEVELS'(unsigned'(j)); end for (genvar level = 0; unsigned'(level) < NUM_LEVELS; level++) begin : g_levels @@ -87,7 +87,7 @@ module lzc #( end end - assign cnt_o = NUM_LEVELS > 0 ? index_nodes[0] : '0; - assign empty_o = NUM_LEVELS > 0 ? ~sel_nodes[0] : ~(|in_i); + assign cnt_o = NUM_LEVELS > unsigned'(0) ? index_nodes[0] : $clog2(WIDTH)'(0); + assign empty_o = NUM_LEVELS > unsigned'(0) ? ~sel_nodes[0] : ~(|in_i); endmodule : lzc diff --git a/src/rr_arb_tree.sv b/src/rr_arb_tree.sv index 6252efec..dee50249 100644 --- a/src/rr_arb_tree.sv +++ b/src/rr_arb_tree.sv @@ -56,7 +56,7 @@ module rr_arb_tree #( output logic [$clog2(NumIn)-1:0] idx_o ); // just pass through in this corner case - if (NumIn == 1) begin + if (NumIn == unsigned'(1)) begin assign req_o = req_i[0]; assign gnt_o[0] = gnt_i; assign data_o = data_i[0]; @@ -71,11 +71,8 @@ module rr_arb_tree #( logic [2**NumLevels-2:0] gnt_nodes; // used to propagate the grant to masters logic [2**NumLevels-2:0] req_nodes; // used to propagate the requests to slave /* lint_off */ - logic [NumLevels-1:0] rr_d, rr_q; - - // only used in case of enabled lock feature - logic [NumIn-1:0] req_d, req_q; - logic lock_d, lock_q; + logic [NumLevels-1:0] rr_q; + logic [NumIn-1:0] req_d; // the final arbitration decision can be taken from the root of the tree assign req_o = req_nodes[0]; @@ -86,8 +83,13 @@ module rr_arb_tree #( assign rr_q = rr_i; assign req_d = req_i; end else begin : gen_int_rr + logic [NumLevels-1:0] rr_d; + // lock arbiter decision in case we got at least one req and no acknowledge if (LockIn) begin : gen_lock + logic lock_d, lock_q; + logic [NumIn-1:0] req_q; + assign lock_d = req_o & ~gnt_i; assign req_d = (lock_q) ? req_q : req_i; @@ -102,23 +104,46 @@ module rr_arb_tree #( end end end + + // pragma translate_off + `ifndef VERILATOR + lock: assert property( + @(posedge clk_i) disable iff (!rst_ni) LockIn |-> req_o && !gnt_i |=> idx_o == $past(idx_o)) + else $fatal (1, "Lock implies same arbiter decision in next cycle if output is not ready."); + + logic [NumIn-1:0] req_tmp; + assign req_tmp = req_q & req_i; + lock_req: assert property( + @(posedge clk_i) disable iff (!rst_ni) LockIn |-> lock_d |=> req_tmp == req_q) + else $fatal (1, "It is disallowed to deassert unserved request signals when LockIn is enabled."); + `endif + // pragma translate_on + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_req_regs + if (!rst_ni) begin + req_q <= '0; + end else begin + if (flush_i) begin + req_q <= '0; + end else begin + req_q <= req_d; + end + end + end end else begin : gen_no_lock assign req_d = req_i; end assign rr_d = (gnt_i && req_o) ? ((rr_q == NumLevels'(NumIn-1)) ? '0 : rr_q + 1'b1) : rr_q; - always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + always_ff @(posedge clk_i or negedge rst_ni) begin : p_rr_regs if (!rst_ni) begin rr_q <= '0; - req_q <= '0; end else begin if (flush_i) begin rr_q <= '0; - req_q <= '0; end else begin rr_q <= rr_d; - req_q <= req_d; end end end @@ -170,8 +195,8 @@ module rr_arb_tree #( // arbitration: round robin assign sel = ~req_nodes[idx1] | req_nodes[idx1+1] & rr_q[NumLevels-1-level]; - assign index_nodes[idx0] = (sel) ? NumLevels'({1'b1, index_nodes[idx1+1][NumLevels-level-2:0]}) : - NumLevels'({1'b0, index_nodes[idx1][NumLevels-level-2:0]}); + assign index_nodes[idx0] = (sel) ? NumLevels'({1'b1, index_nodes[idx1+1][NumLevels-unsigned'(level)-2:0]}) : + NumLevels'({1'b0, index_nodes[idx1][NumLevels-unsigned'(level)-2:0]}); assign data_nodes[idx0] = (sel) ? data_nodes[idx1+1] : data_nodes[idx1]; assign gnt_nodes[idx1] = gnt_nodes[idx0] & ~sel; assign gnt_nodes[idx1+1] = gnt_nodes[idx0] & sel; @@ -212,16 +237,6 @@ module rr_arb_tree #( req1 : assert property( @(posedge clk_i) disable iff (!rst_ni) |req_o |-> req_i) else $fatal (1, "Req out implies req in."); - - lock: assert property( - @(posedge clk_i) disable iff (!rst_ni) LockIn |-> req_o && !gnt_i |=> idx_o == $past(idx_o)) - else $fatal (1, "Lock implies same arbiter decision in next cycle if output is not ready."); - - logic [NumIn-1:0] req_tmp; - assign req_tmp = req_q & req_i; - lock_req: assert property( - @(posedge clk_i) disable iff (!rst_ni) LockIn |-> lock_d |=> req_tmp == req_q) - else $fatal (1, "It is disallowed to deassert unserved request signals when LockIn is enabled."); `endif // pragma translate_on end