PiDP-10: Clock bit in APR is not set when repeating CONT.

[larsbrinkhoff]

Posting here because https://github.com/rcornwell/pidp10 doesn't allow issues.

Steps to reproduce:

1. Enter test program:

   d 100 ADDI 1,1
   d 101 DATAO PI,1
   d 102 CONSO APR,1000
   d 103 JRST 102
   d 104 CONO APR,1000
   d 105 JRST 100
   

2. Push SING INST SING CYCLE and REPT.
3. Push START.
4. Hold down CONT.

Expected outcome:

Program ADDI executed frequently, counting up on the MI lights. This is because the APR 1000 bit should be set 60 times a second, so the CONSO, JRST loop should exit immediately in single stepping (repeated or not).

Actual outcome:

I'm not sure if SING CYCLE has been implemented yet, but if it is.
Program stuck in CONSO, JRST loop. Seems like APR bit 1000 isn't set 60 times a second.

[larsbrinkhoff]

@aap remarked that SING INST disables the clock flag. So the current behavior is kind of correct, albeit not by design. (I assume.)

However, the issue can (and will) be rewritten to use SING CYCLE instead.

[rcornwell]

SING CYCLE is not implemented under the emulator. I have fixed SING CYCLE to operate same as SING INST.

[larsbrinkhoff]

Can you fix SING CYCLE so it doesn't inhibit the clock flag?

[rcornwell]

No, SING CYCLE sets the SING INST SWITCH.

Also since single Cycle and single Instruction, bring you back to simH prompt, there can not be any timer events generated.

[larsbrinkhoff]

On a real KA10, only SING INST should inhibit the clock flag. SING CYCLE should not inhibit the clock flag.

[rcornwell]

They are implemented identically, so single cycle will inhibit the clock. Also single Cycle has no meaning on pdp10-ka.

[larsbrinkhoff]

I understand they are identical now. What I propose is to make them not identical. Is that up for discussion?

Also, any chance single cycle could be implemented in the future?

[rcornwell]

On a different emulator possibly. Now single Cycle on the KA10 was single memory cycle, not single execution cycle. But interrupting the simulation at every memory access and then restarting the instruction where it left off will add a huge performance hit to simulation. I am not sure that is justified for the few cases the feature would be used. Also making single cycle not disable clock is a bit of work that offers very little gain in functionality.

[larsbrinkhoff]

For the record, I disagree this is resolved. I would like to see this fixed in the future. Are you saying you will not accept updates to fix this in your simulator?

[rcornwell]

I will always accept updates. However I think trying to emulate single cycle will greatly increase the complexity of the code, and have a negative effect on performance with little gain of functionality. If you want to propose a fix I will gladly look over it.