performance counters are stopped(mcycle and mintret)

[123swk123]

CSR_MCOUNTINHIBIT is reset back to 0x05 after executing function libc_init_array

GD32VF103_Firmware_Library/Firmware/RISCV/env_Eclipse/start.S

Line 237 in 12b61d1

call __libc_init_array

even though it was cleared at

GD32VF103_Firmware_Library/Firmware/RISCV/env_Eclipse/start.S

Line 233 in 12b61d1

csrci CSR_MCOUNTINHIBIT, 0x5

clear these bits just before calling main.

[fanghuaqi]

Hi @123swk123,

We have improved the startup and exception handling for Nuclei RISC-V processor using NMSIS, and adjust the gd32vf103 firmware in our Nuclei SDK, which will of course fix the issue.

Thanks
Huaqi

[123swk123]

Has it been fixed already?

If so please share the commit details let me try to use it for my current work and feedback if I find something.

[fanghuaqi]

It is not fixed in this repo, it is fixed in a seperated repo mentioned above maintained by Nuclei RISC-V Processor software team.

Thanks
Huaqi

[fanghuaqi]

If you are using this repo, you can simply change this csrci CSR_MCOUNTINHIBIT, 0x5 to csrsi CSR_MCOUNTINHIBIT, 0x5 to enable the cycle/instret counter.

Thanks
Huaqi