From 9cddf2076b5c9824d860b75a7fca6ff3cc07e5a9 Mon Sep 17 00:00:00 2001 From: Nicolas Brunie Date: Fri, 29 Sep 2023 15:54:24 -0700 Subject: [PATCH 1/6] [vector-crypto] Fixing Zvkb/Zvbb distinction --- disasm/isa_parser.cc | 2 ++ riscv/insns/vandn_vv.h | 2 +- riscv/insns/vandn_vx.h | 2 +- riscv/insns/vbrev8_v.h | 2 +- riscv/insns/vrev8_v.h | 2 +- riscv/insns/vrol_vv.h | 2 +- riscv/insns/vrol_vx.h | 2 +- riscv/insns/vror_vi.h | 2 +- riscv/insns/vror_vv.h | 2 +- riscv/insns/vror_vx.h | 2 +- riscv/isa_parser.h | 1 + riscv/riscv.mk.in | 13 ++++++++----- riscv/zvk_ext_macros.h | 10 +++++++++- 13 files changed, 29 insertions(+), 15 deletions(-) diff --git a/disasm/isa_parser.cc b/disasm/isa_parser.cc index 79203dfbe2..5ab25f5cc3 100644 --- a/disasm/isa_parser.cc +++ b/disasm/isa_parser.cc @@ -257,6 +257,8 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv) extension_table[EXT_ZVFBFMIN] = true; } else if (ext_str == "zvfbfwma") { extension_table[EXT_ZVFBFWMA] = true; + } else if (ext_str == "zvkb") { + extension_table[EXT_ZVKB] = true; } else if (ext_str == "zvkg") { extension_table[EXT_ZVKG] = true; } else if (ext_str == "zvkn") { diff --git a/riscv/insns/vandn_vv.h b/riscv/insns/vandn_vv.h index d85e47d7fe..411c97d5b9 100644 --- a/riscv/insns/vandn_vv.h +++ b/riscv/insns/vandn_vv.h @@ -2,7 +2,7 @@ #include "zvk_ext_macros.h" -require_zvbb; +require_zvkb; VI_VV_LOOP ({ diff --git a/riscv/insns/vandn_vx.h b/riscv/insns/vandn_vx.h index 1c66a40970..417b8d2eac 100644 --- a/riscv/insns/vandn_vx.h +++ b/riscv/insns/vandn_vx.h @@ -2,7 +2,7 @@ #include "zvk_ext_macros.h" -require_zvbb; +require_zvkb; VI_VX_LOOP ({ diff --git a/riscv/insns/vbrev8_v.h b/riscv/insns/vbrev8_v.h index a6d3cda744..19fa7235e4 100644 --- a/riscv/insns/vbrev8_v.h +++ b/riscv/insns/vbrev8_v.h @@ -2,7 +2,7 @@ #include "zvk_ext_macros.h" -require_zvbb; +require_zvkb; VI_V_ULOOP ({ diff --git a/riscv/insns/vrev8_v.h b/riscv/insns/vrev8_v.h index f26c5a0502..e39c5c07fe 100644 --- a/riscv/insns/vrev8_v.h +++ b/riscv/insns/vrev8_v.h @@ -2,7 +2,7 @@ #include "zvk_ext_macros.h" -require_zvbb; +require_zvkb; VI_V_ULOOP ({ diff --git a/riscv/insns/vrol_vv.h b/riscv/insns/vrol_vv.h index fb2e483320..a2ac832451 100644 --- a/riscv/insns/vrol_vv.h +++ b/riscv/insns/vrol_vv.h @@ -2,7 +2,7 @@ #include "zvk_ext_macros.h" -require_zvbb; +require_zvkb; // 'mask' selects the low log2(vsew) bits of the shift amount, // to limit the maximum shift to "vsew - 1" bits. diff --git a/riscv/insns/vrol_vx.h b/riscv/insns/vrol_vx.h index b0c89a27b7..8e4b41b6c7 100644 --- a/riscv/insns/vrol_vx.h +++ b/riscv/insns/vrol_vx.h @@ -2,7 +2,7 @@ #include "zvk_ext_macros.h" -require_zvbb; +require_zvkb; // 'mask' selects the low log2(vsew) bits of the shift amount, // to limit the maximum shift to "vsew - 1" bits. diff --git a/riscv/insns/vror_vi.h b/riscv/insns/vror_vi.h index 1269c3d477..6ae9fcdbe1 100644 --- a/riscv/insns/vror_vi.h +++ b/riscv/insns/vror_vi.h @@ -2,7 +2,7 @@ #include "zvk_ext_macros.h" -require_zvbb; +require_zvkb; // 'mask' selects the low log2(vsew) bits of the shift amount, // to limit the maximum shift to "vsew - 1" bits. diff --git a/riscv/insns/vror_vv.h b/riscv/insns/vror_vv.h index c649c6d97f..276d7ec29a 100644 --- a/riscv/insns/vror_vv.h +++ b/riscv/insns/vror_vv.h @@ -2,7 +2,7 @@ #include "zvk_ext_macros.h" -require_zvbb; +require_zvkb; // 'mask' selects the low log2(vsew) bits of the shift amount, // to limit the maximum shift to "vsew - 1" bits. diff --git a/riscv/insns/vror_vx.h b/riscv/insns/vror_vx.h index 50c8e5c94a..98e1248336 100644 --- a/riscv/insns/vror_vx.h +++ b/riscv/insns/vror_vx.h @@ -2,7 +2,7 @@ #include "zvk_ext_macros.h" -require_zvbb; +require_zvkb; // 'mask' selects the low log2(vsew) bits of the shift amount, // to limit the maximum shift to "vsew - 1" bits. diff --git a/riscv/isa_parser.h b/riscv/isa_parser.h index 45f637c640..f87b190158 100644 --- a/riscv/isa_parser.h +++ b/riscv/isa_parser.h @@ -59,6 +59,7 @@ typedef enum { EXT_ZVBC, EXT_ZVFBFMIN, EXT_ZVFBFWMA, + EXT_ZVKB, EXT_ZVKG, EXT_ZVKNED, EXT_ZVKNHA, diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 60723b58e6..57dd935b59 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -1005,20 +1005,23 @@ riscv_insn_ext_zalasr = \ sw_rl \ sd_rl \ -riscv_insn_ext_zvbb = \ +riscv_insn_ext_zvkb = \ vandn_vv \ vandn_vx \ vbrev8_v \ - vbrev_v \ - vclz_v \ - vcpop_v \ - vctz_v \ vrev8_v \ vrol_vv \ vrol_vx \ vror_vi \ vror_vv \ vror_vx \ + +riscv_insn_ext_zvbb = \ + $(riscv_insn_ext_zvkb) \ + vbrev_v \ + vclz_v \ + vcpop_v \ + vctz_v \ vwsll_vi \ vwsll_vv \ vwsll_vx \ diff --git a/riscv/zvk_ext_macros.h b/riscv/zvk_ext_macros.h index f094629835..9d5571cea2 100644 --- a/riscv/zvk_ext_macros.h +++ b/riscv/zvk_ext_macros.h @@ -13,7 +13,7 @@ // Predicate Macros // -// Ensures that the ZVBB extension (vector crypto bitmanip) is present, +// Ensures that the ZVBB extension (vector basic bitmanip) is present, // and the vector unit is enabled and in a valid state. #define require_zvbb \ do { \ @@ -29,6 +29,14 @@ require_extension(EXT_ZVBC); \ } while (0) +// Ensures that the ZVKB extension (vector crypto bitmanip) is present, +// and the vector unit is enabled and in a valid state. +#define require_zvkb \ + do { \ + require_vector(true); \ + require_extension(EXT_ZVKB); \ + } while (0) + // Ensures that the ZVKG extension (vector Galois Field Multiplication) // is present, and the vector unit is enabled and in a valid state. #define require_zvkg \ From f94914f426a6f2ecdc021e25cdb2bee6ab8cb758 Mon Sep 17 00:00:00 2001 From: Nicolas Brunie <82109999+nibrunieAtSi5@users.noreply.github.com> Date: Fri, 29 Sep 2023 17:25:40 -0700 Subject: [PATCH 2/6] Fixing space -> tab in riscv.mk.in Signed-off-by: Nicolas Brunie <82109999+nibrunieAtSi5@users.noreply.github.com> --- riscv/riscv.mk.in | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 57dd935b59..100cea6ae0 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -1017,7 +1017,7 @@ riscv_insn_ext_zvkb = \ vror_vx \ riscv_insn_ext_zvbb = \ - $(riscv_insn_ext_zvkb) \ + $(riscv_insn_ext_zvkb) \ vbrev_v \ vclz_v \ vcpop_v \ From 71a5ef4a58e421cf324f5c878d966714458a6553 Mon Sep 17 00:00:00 2001 From: Nicolas Brunie Date: Sat, 30 Sep 2023 21:21:56 -0700 Subject: [PATCH 3/6] fixing ZVBB -> ZVKB in isa_parser aliases --- disasm/isa_parser.cc | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/disasm/isa_parser.cc b/disasm/isa_parser.cc index 5ab25f5cc3..85a573f16a 100644 --- a/disasm/isa_parser.cc +++ b/disasm/isa_parser.cc @@ -250,7 +250,7 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv) } else if (ext_str == "zcmlsd") { extension_table[EXT_ZCMLSD] = true; } else if (ext_str == "zvbb") { - extension_table[EXT_ZVBB] = true; + extension_table[EXT_ZVKB] = true; } else if (ext_str == "zvbc") { extension_table[EXT_ZVBC] = true; } else if (ext_str == "zvfbfmin") { @@ -262,16 +262,16 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv) } else if (ext_str == "zvkg") { extension_table[EXT_ZVKG] = true; } else if (ext_str == "zvkn") { - extension_table[EXT_ZVBB] = true; + extension_table[EXT_ZVKB] = true; extension_table[EXT_ZVKNED] = true; extension_table[EXT_ZVKNHB] = true; } else if (ext_str == "zvknc") { - extension_table[EXT_ZVBB] = true; + extension_table[EXT_ZVKB] = true; extension_table[EXT_ZVBC] = true; extension_table[EXT_ZVKNED] = true; extension_table[EXT_ZVKNHB] = true; } else if (ext_str == "zvkng") { - extension_table[EXT_ZVBB] = true; + extension_table[EXT_ZVKB] = true; extension_table[EXT_ZVKG] = true; extension_table[EXT_ZVKNED] = true; extension_table[EXT_ZVKNHB] = true; @@ -282,16 +282,16 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv) } else if (ext_str == "zvknhb") { extension_table[EXT_ZVKNHB] = true; } else if (ext_str == "zvks") { - extension_table[EXT_ZVBB] = true; + extension_table[EXT_ZVKB] = true; extension_table[EXT_ZVKSED] = true; extension_table[EXT_ZVKSH] = true; } else if (ext_str == "zvksc") { - extension_table[EXT_ZVBB] = true; + extension_table[EXT_ZVKB] = true; extension_table[EXT_ZVBC] = true; extension_table[EXT_ZVKSED] = true; extension_table[EXT_ZVKSH] = true; } else if (ext_str == "zvksg") { - extension_table[EXT_ZVBB] = true; + extension_table[EXT_ZVKB] = true; extension_table[EXT_ZVKG] = true; extension_table[EXT_ZVKSED] = true; extension_table[EXT_ZVKSH] = true; From d851b902c5b71721826ac12c118ea8cb093e8c6f Mon Sep 17 00:00:00 2001 From: Nicolas Brunie Date: Sat, 30 Sep 2023 21:41:57 -0700 Subject: [PATCH 4/6] fixing enabling EXT_ZVBB+EXT_ZVKB when zvbb enabled --- disasm/isa_parser.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/disasm/isa_parser.cc b/disasm/isa_parser.cc index 85a573f16a..667532ebfc 100644 --- a/disasm/isa_parser.cc +++ b/disasm/isa_parser.cc @@ -250,6 +250,7 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv) } else if (ext_str == "zcmlsd") { extension_table[EXT_ZCMLSD] = true; } else if (ext_str == "zvbb") { + extension_table[EXT_ZVBB] = true; extension_table[EXT_ZVKB] = true; } else if (ext_str == "zvbc") { extension_table[EXT_ZVBC] = true; From 3180eddf017b5fdf55b6390d2cff24d493004b3d Mon Sep 17 00:00:00 2001 From: Nicolas Brunie Date: Sat, 30 Sep 2023 22:00:36 -0700 Subject: [PATCH 5/6] fixing disasm split ZVKB/ZVBB --- disasm/disasm.cc | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/disasm/disasm.cc b/disasm/disasm.cc index c3ba62a690..73a34ce7cb 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -2125,38 +2125,43 @@ void disassembler_t::add_instructions(const isa_parser_t* isa) DEFINE_R1TYPE(sm3p1); } - if (isa->extension_enabled(EXT_ZVBB)) { + if (isa->extension_enabled(EXT_ZVKB) || isa->extension_enabled(EXT_ZVBB)) { #define DEFINE_VECTOR_VIU_ZIMM6(code) \ add_vector_viu_z6_insn(this, #code, match_##code, mask_##code) #define DISASM_VECTOR_VV_VX(name) \ DEFINE_VECTOR_VV(name##_vv); \ DEFINE_VECTOR_VX(name##_vx) -#define DISASM_VECTOR_VV_VX_VIU(name) \ - DEFINE_VECTOR_VV(name##_vv); \ - DEFINE_VECTOR_VX(name##_vx); \ - DEFINE_VECTOR_VIU(name##_vi) #define DISASM_VECTOR_VV_VX_VIU_ZIMM6(name) \ DEFINE_VECTOR_VV(name##_vv); \ DEFINE_VECTOR_VX(name##_vx); \ DEFINE_VECTOR_VIU_ZIMM6(name##_vi) DISASM_VECTOR_VV_VX(vandn); - DEFINE_VECTOR_V(vbrev_v); DEFINE_VECTOR_V(vbrev8_v); DEFINE_VECTOR_V(vrev8_v); - DEFINE_VECTOR_V(vclz_v); - DEFINE_VECTOR_V(vctz_v); - DEFINE_VECTOR_V(vcpop_v); DISASM_VECTOR_VV_VX(vrol); DISASM_VECTOR_VV_VX_VIU_ZIMM6(vror); - DISASM_VECTOR_VV_VX_VIU(vwsll); #undef DEFINE_VECTOR_VIU_ZIMM6 #undef DISASM_VECTOR_VV_VX -#undef DISASM_VECTOR_VV_VX_VIU #undef DISASM_VECTOR_VV_VX_VIU_ZIMM6 } + if (isa->extension_enabled(EXT_ZVBB)) { +#define DISASM_VECTOR_VV_VX_VIU(name) \ + DEFINE_VECTOR_VV(name##_vv); \ + DEFINE_VECTOR_VX(name##_vx); \ + DEFINE_VECTOR_VIU(name##_vi) + + DEFINE_VECTOR_V(vbrev_v); + DEFINE_VECTOR_V(vclz_v); + DEFINE_VECTOR_V(vctz_v); + DEFINE_VECTOR_V(vcpop_v); + DISASM_VECTOR_VV_VX_VIU(vwsll); + +#undef DISASM_VECTOR_VV_VX_VIU + } + if (isa->extension_enabled(EXT_ZVBC)) { #define DISASM_VECTOR_VV_VX(name) \ DEFINE_VECTOR_VV(name##_vv); \ From 6a31dc2410c9b057904571e15270bf50e01d298a Mon Sep 17 00:00:00 2001 From: Nicolas Brunie <82109999+nibrunieAtSi5@users.noreply.github.com> Date: Mon, 2 Oct 2023 14:21:09 -0700 Subject: [PATCH 6/6] Update disasm/disasm.cc Signed-off-by: Nicolas Brunie <82109999+nibrunieAtSi5@users.noreply.github.com> --- disasm/disasm.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/disasm/disasm.cc b/disasm/disasm.cc index 73a34ce7cb..123f578ce5 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -2125,7 +2125,7 @@ void disassembler_t::add_instructions(const isa_parser_t* isa) DEFINE_R1TYPE(sm3p1); } - if (isa->extension_enabled(EXT_ZVKB) || isa->extension_enabled(EXT_ZVBB)) { + if (isa->extension_enabled(EXT_ZVKB)) { #define DEFINE_VECTOR_VIU_ZIMM6(code) \ add_vector_viu_z6_insn(this, #code, match_##code, mask_##code) #define DISASM_VECTOR_VV_VX(name) \