From 8062e5e943a0244e0d093e46c3052e95bced72d9 Mon Sep 17 00:00:00 2001 From: Dmitriy Ryabtsev Date: Thu, 26 Sep 2024 12:16:37 +0300 Subject: [PATCH] Address github comments Signed-off-by: Dmitriy Ryabtsev --- adoc_event_tables/cache_retired.adoc | 8 ++- adoc_event_tables/cache_retired_metrics.adoc | 20 +++--- adoc_event_tables/cache_spec_metrics.adoc | 44 +++++++------- adoc_event_tables/prediction_metrics.adoc | 40 ++++++------ adoc_event_tables/prediction_retired.adoc | 2 +- adoc_event_tables/retired.adoc | 14 ++--- adoc_event_tables/rvv_retired.adoc | 6 +- adoc_event_tables/rvv_spec.adoc | 6 +- adoc_event_tables/spec.adoc | 12 ++-- adoc_event_tables/tlb_retired_metrics.adoc | 16 ++--- adoc_event_tables/tlb_spec_metrics.adoc | 24 ++++---- adoc_event_tables/topdown_metrics.adoc | 4 +- event_files/cache_retired.json | 18 +++++- event_files/cache_retired_metrics.json | 32 +++++----- event_files/cache_spec_metrics.json | 64 ++++++++++---------- event_files/prediction_metrics.json | 40 ++++++------ event_files/prediction_retired.json | 2 +- event_files/retired.json | 14 ++--- event_files/rvv_retired.json | 6 +- event_files/rvv_spec.json | 6 +- event_files/spec.json | 12 ++-- event_files/tlb_retired_metrics.json | 24 ++++---- event_files/tlb_spec_metrics.json | 36 +++++------ event_files/topdown_metrics.json | 6 +- intro.adoc | 4 +- 25 files changed, 237 insertions(+), 223 deletions(-) diff --git a/adoc_event_tables/cache_retired.adoc b/adoc_event_tables/cache_retired.adoc index e081526..0158272 100644 --- a/adoc_event_tables/cache_retired.adoc +++ b/adoc_event_tables/cache_retired.adoc @@ -14,11 +14,13 @@ |CACHE.L2.LOAD.ACCESS.RET |Retired load instruction which got data from L2 or from some next level in memory hierarchy - L3 cache, local mmemory, remote cache, remote memory, etc. |CACHE.L2.LOAD.MISS.RET |Retired load instruction which got data from some next level (relative to L2) in memory hierarchy - L3 cache, local mmemory, remote cache, remote memory, etc. |CACHE.L2.LOAD.HIT.RET |Retired load instruction which got data from L2 cache +|CACHE.L2.LOAD.MERGE.RET |Retired load instruction which hit L2 cache with data not yet in cache but was already requested by preceding miss |CACHE.L3.LOAD.ACCESS.RET |Retired load instruction which got data from L3 cache or from some next level in memory hierarchy - local mmemory, remote cache, remote memory, etc. |CACHE.L3.LOAD.MISS.RET |Retired load instruction which got data from some next level (relative to L3) in memory hierarchy - local mmemory, remote cache, remote memory, etc. |CACHE.L3.LOAD.HIT.RET |Retired load instruction which got data from L3 cache -|CACHE.L3.LOAD.MISS.LOCAL_MEMORY.RET |Retired load instruction which got data from local memory. -|CACHE.L3.LOAD.MISS.REMOTE_MEMORY.RET |Retired load instruction which got data from remote memory (memory attached to remote socket). -|CACHE.L3.LOAD.MISS.REMOTE_CACHE.RET |Retired load instruction which got data from remote cache (cache on remote socket). +|CACHE.L3.LOAD.MERGE.RET |Retired load instruction which hit L3 cache with data not yet in cache but was already requested by preceding miss +|CACHE.LOAD.LOCAL_MEMORY.RET |Retired load instruction which got data from local memory. +|CACHE.LOAD.REMOTE_MEMORY.RET |Retired load instruction which got data from remote memory (memory attached to remote socket). +|CACHE.LOAD.REMOTE_CACHE.RET |Retired load instruction which got data from remote cache (cache on remote socket). |=== diff --git a/adoc_event_tables/cache_retired_metrics.adoc b/adoc_event_tables/cache_retired_metrics.adoc index e2e6141..0237074 100644 --- a/adoc_event_tables/cache_retired_metrics.adoc +++ b/adoc_event_tables/cache_retired_metrics.adoc @@ -2,15 +2,15 @@ [width="100%",cols="25%,40%,35%",options="header",] |=== |Name |Description |Formula -|CACHE.L1D.LOAD.MPKI.RET |The rate of retired L1 data load cache misses per kilo instructions retired |CACHE.L1D.LOAD.MISS.RET / RETIRED.INST * 1000 -|CACHE.L1D.LOAD.MISS.RATE.RET |The ratio of retired L1D cache load misses to the total number of retired L1D load accesses |CACHE.L1D.LOAD.MISS.RET / CACHE.L1D.LOAD.ACCESS.RET -|CACHE.L1D.LOAD.MERGE.PKI.RET |The rate of retired L1 data load cache misses which merged with previous cache miss per kilo instructions retired |CACHE.L1D.LOAD.MERGE.RET / RETIRED.INST * 1000 -|CACHE.L1I.MPKI.RET |The rate of retired instructions with L1 instruction cache misses per kilo instructions retired |CACHE.L1I.MISS.RET / RETIRED.INST * 1000 -|CACHE.L1D.STORE.MPKI.RET |The rate of retired L1 data store cache misses per kilo instructions retired |CACHE.L1D.STORE.MISS.RET / RETIRED.INST * 1000 -|CACHE.L1D.STORE.MISS.RATE.RET |The ratio of retired L1D cache store misses to the total number of retired L1D store accesses |CACHE.L1D.STORE.MISS.RET / CACHE.L1D.STORE.ACCESS.RET -|CACHE.L2.LOAD.MPKI.RET |The rate of retired L2 data load cache misses per kilo instructions retired |CACHE.L2.LOAD.MISS.RET / RETIRED.INST * 1000 -|CACHE.L2.LOAD.MISS.RATE.RET |The ratio of retired L2 cache load misses to the total number of retired L2 load accesses |CACHE.L2.LOAD.MISS.RET / CACHE.L2.LOAD.ACCESS.RET -|CACHE.L3.LOAD.MPKI.RET |The rate of retired L3 data load cache misses per kilo instructions retired |CACHE.L3.LOAD.MISS.RET / RETIRED.INST * 1000 -|CACHE.L3.LOAD.MISS.RATE.RET |The ratio of retired L3 cache load misses to the total number of retired L3 load accesses |CACHE.L3.LOAD.MISS.RET / CACHE.L3.LOAD.ACCESS.RET +|CACHE.L1D.LOAD.RET.MPKI |The rate of retired L1 data load cache misses per kilo instructions retired |CACHE.L1D.LOAD.MISS.RET / INST.RET * 1000 +|CACHE.L1D.LOAD.MISS.RET.RATE |The ratio of retired L1D cache load misses to the total number of retired L1D load accesses |CACHE.L1D.LOAD.MISS.RET / CACHE.L1D.LOAD.ACCESS.RET +|CACHE.L1D.LOAD.MERGE.RET.PKI |The rate of retired L1 data load cache misses which merged with previous cache miss per kilo instructions retired |CACHE.L1D.LOAD.MERGE.RET / INST.RET * 1000 +|CACHE.L1I.RET.MPKI |The rate of retired instructions with L1 instruction cache misses per kilo instructions retired |CACHE.L1I.MISS.RET / INST.RET * 1000 +|CACHE.L1D.STORE.RET.MPKI |The rate of retired L1 data store cache misses per kilo instructions retired |CACHE.L1D.STORE.MISS.RET / INST.RET * 1000 +|CACHE.L1D.STORE.MISS.RET.RATE |The ratio of retired L1D cache store misses to the total number of retired L1D store accesses |CACHE.L1D.STORE.MISS.RET / CACHE.L1D.STORE.ACCESS.RET +|CACHE.L2.LOAD.RET.MPKI |The rate of retired L2 data load cache misses per kilo instructions retired |CACHE.L2.LOAD.MISS.RET / INST.RET * 1000 +|CACHE.L2.LOAD.MISS.RET.RATE |The ratio of retired L2 cache load misses to the total number of retired L2 load accesses |CACHE.L2.LOAD.MISS.RET / CACHE.L2.LOAD.ACCESS.RET +|CACHE.L3.LOAD.RET.MPKI |The rate of retired L3 data load cache misses per kilo instructions retired |CACHE.L3.LOAD.MISS.RET / INST.RET * 1000 +|CACHE.L3.LOAD.MISS.RET.RATE |The ratio of retired L3 cache load misses to the total number of retired L3 load accesses |CACHE.L3.LOAD.MISS.RET / CACHE.L3.LOAD.ACCESS.RET |=== diff --git a/adoc_event_tables/cache_spec_metrics.adoc b/adoc_event_tables/cache_spec_metrics.adoc index 86f13e8..bd1aee0 100644 --- a/adoc_event_tables/cache_spec_metrics.adoc +++ b/adoc_event_tables/cache_spec_metrics.adoc @@ -2,31 +2,31 @@ [width="100%",cols="25%,40%,35%",options="header",] |=== |Name |Description |Formula -|CACHE.L1D.LOAD.MPKI.SPEC |The rate of speculative L1 data cache misses caused by data loads per kilo instructions retired |CACHE.L1D.LOAD.MISS.SPEC / RETIRED.INST * 1000 -|CACHE.L1D.LOAD.MISS.RATE.SPEC |The ratio of speculative L1D cache misses to the total number of L1D accesses caused by data loads |CACHE.L1D.LOAD.MISS.SPEC / CACHE.L1D.LOAD.ACCESS.SPEC -|CACHE.L1D.LOAD.MERGE.PKI.SPEC |The rate of speculative L1 data cache accesses which merged with previous cache miss per kilo instructions retired |CACHE.L1D.LOAD.MERGE.SPEC / RETIRED.INST * 1000 -|CACHE.L1D.STORE.MPKI.SPEC |The rate of speculative L1 data cache misses caused by data stores per kilo instructions retired |CACHE.L1D.STORE.MISS.SPEC / RETIRED.INST * 1000 -|CACHE.L1D.STORE.MISS.RATE.SPEC |The ratio of speculative L1D cache misses to the total number of L1D accesses caused by data stores |CACHE.L1D.STORE.MISS.SPEC / CACHE.L1D.STORE.ACCESS.SPEC -|CACHE.L1D.PREF.ISSUED.PKI |The rate of prefetcher requests issued by L1D to next level cache per kilo instructions retired |CACHE.L1D.PREF.ISSUED / RETIRED.INST * 1000 +|CACHE.L1D.LOAD.SPEC.MPKI |The rate of speculative L1 data cache misses caused by data loads per kilo instructions retired |CACHE.L1D.LOAD.MISS.SPEC / INST.RET * 1000 +|CACHE.L1D.LOAD.MISS.SPEC.RATE |The ratio of speculative L1D cache misses to the total number of L1D accesses caused by data loads |CACHE.L1D.LOAD.MISS.SPEC / CACHE.L1D.LOAD.ACCESS.SPEC +|CACHE.L1D.LOAD.MERGE.SPEC.PKI |The rate of speculative L1 data cache accesses which merged with previous cache miss per kilo instructions retired |CACHE.L1D.LOAD.MERGE.SPEC / INST.RET * 1000 +|CACHE.L1D.STORE.SPEC.MPKI |The rate of speculative L1 data cache misses caused by data stores per kilo instructions retired |CACHE.L1D.STORE.MISS.SPEC / INST.RET * 1000 +|CACHE.L1D.STORE.MISS.SPEC.RATE |The ratio of speculative L1D cache misses to the total number of L1D accesses caused by data stores |CACHE.L1D.STORE.MISS.SPEC / CACHE.L1D.STORE.ACCESS.SPEC +|CACHE.L1D.PREF.ISSUED.PKI |The rate of prefetcher requests issued by L1D to next level cache per kilo instructions retired |CACHE.L1D.PREF.ISSUED / INST.RET * 1000 |CACHE.L1D.PREF.UNUSED.RATE |The ratio of unused cachelines brought into L1D by prefetcher to the total number of prefetcher requests issued by L1D |CACHE.L1D.PREF.UNUSED / CACHE.L1D.PREF.ISSUED -|CACHE.L1I.MPKI.SPEC |The rate of L1 instruction cache misses per kilo instructions retired |CACHE.L1I.MISS.SPEC / RETIRED.INST * 1000 -|CACHE.L1I.MISS.RATE.SPEC |The ratio of L1 instruction cache misses to the total number of L1I accesses |CACHE.L1I.MISS.SPEC / CACHE.L1I.ACCESS.SPEC -|CACHE.L1I.MERGE.PKI.SPEC |The rate of L1 instruction cache accesses which merged with previous cache miss per kilo instructions retired |CACHE.L1I.MERGE.SPEC / RETIRED.INST * 1000 +|CACHE.L1I.SPEC.MPKI |The rate of L1 instruction cache misses per kilo instructions retired |CACHE.L1I.MISS.SPEC / INST.RET * 1000 +|CACHE.L1I.MISS.SPEC.RATE |The ratio of L1 instruction cache misses to the total number of L1I accesses |CACHE.L1I.MISS.SPEC / CACHE.L1I.ACCESS.SPEC +|CACHE.L1I.MERGE.SPEC.PKI |The rate of L1 instruction cache accesses which merged with previous cache miss per kilo instructions retired |CACHE.L1I.MERGE.SPEC / INST.RET * 1000 |CACHE.L1I.MISS.IMPACT |The approximate ratio of cycles lost due to L1I misses |CACHE.L1I.MISS_OUTSTANDING.CYCLES / CYCLES.HART -|CACHE.L2.LOAD.MPKI.SPEC |The rate of speculative L2 cache misses caused by data loads per kilo instructions retired |CACHE.L2.LOAD.MISS.SPEC / RETIRED.INST * 1000 -|CACHE.L2.LOAD.MISS.RATE.SPEC |The ratio of speculative L2 cache misses to the total number of L2 accesses caused by data loads |CACHE.L2.LOAD.MISS.SPEC / CACHE.L2.LOAD.ACCESS.SPEC -|CACHE.L2.STORE.MPKI.SPEC |The rate of speculative L2 cache misses caused by data stores per kilo instructions retired |CACHE.L2.STORE.MISS.SPEC / RETIRED.INST * 1000 -|CACHE.L2.STORE.MISS.RATE.SPEC |The ratio of speculative L2 cache misses to the total number of L2 accesses caused by data stores |CACHE.L2.STORE.MISS.SPEC / CACHE.L2.STORE.ACCESS.SPEC -|CACHE.L2.STORE.HIT.RFO.PKI.SPEC |The rate of L2 cache hits for store instructions with the purpose to get exclusive ownership per kilo instructions retired |CACHE.L2.STORE.HIT.RFO.SPEC / RETIRED.INST * 1000 -|CACHE.L2.PREF.ISSUED.PKI |The rate of prefetcher requests issued by L2 to next level cache per kilo instructions retired |CACHE.L2.PREF.ISSUED / RETIRED.INST * 1000 -|CACHE.L2.PREF.MPKI |The rate of L2 cache misses caused by prefetcher per kilo instructions retired |CACHE.L2.PREF.MISS / RETIRED.INST * 1000 +|CACHE.L2.LOAD.SPEC.MPKI |The rate of speculative L2 cache misses caused by data loads per kilo instructions retired |CACHE.L2.LOAD.MISS.SPEC / INST.RET * 1000 +|CACHE.L2.LOAD.MISS.SPEC.RATE |The ratio of speculative L2 cache misses to the total number of L2 accesses caused by data loads |CACHE.L2.LOAD.MISS.SPEC / CACHE.L2.LOAD.ACCESS.SPEC +|CACHE.L2.STORE.SPEC.MPKI |The rate of speculative L2 cache misses caused by data stores per kilo instructions retired |CACHE.L2.STORE.MISS.SPEC / INST.RET * 1000 +|CACHE.L2.STORE.MISS.SPEC.RATE |The ratio of speculative L2 cache misses to the total number of L2 accesses caused by data stores |CACHE.L2.STORE.MISS.SPEC / CACHE.L2.STORE.ACCESS.SPEC +|CACHE.L2.STORE.HIT.RFO.SPEC.PKI |The rate of L2 cache hits for store instructions with the purpose to get exclusive ownership per kilo instructions retired |CACHE.L2.STORE.HIT.RFO.SPEC / INST.RET * 1000 +|CACHE.L2.PREF.ISSUED.PKI |The rate of prefetcher requests issued by L2 to next level cache per kilo instructions retired |CACHE.L2.PREF.ISSUED / INST.RET * 1000 +|CACHE.L2.PREF.MPKI |The rate of L2 cache misses caused by prefetcher per kilo instructions retired |CACHE.L2.PREF.MISS / INST.RET * 1000 |CACHE.L2.PREF.UNUSED.RATE |The ratio of unused cachelines brought into L2 by prefetcher to the total number of prefetcher requests issued by L2 |CACHE.L2.PREF.UNUSED / CACHE.L2.PF.ISSUED -|CACHE.L3.LOAD.MPKI.SPEC |The rate of speculative L3 cache misses caused by data loads per kilo instructions retired |CACHE.L3.LOAD.MISS.SPEC / RETIRED.INST * 1000 -|CACHE.L3.LOAD.MISS.RATE.SPEC |The ratio of speculative L3 cache misses to the total number of L3 accesses caused by data loads |CACHE.L3.LOAD.MISS.SPEC / CACHE.L3.LOAD.ACCESS.SPEC -|CACHE.L3.STORE.MPKI.SPEC |The rate of speculative L3 cache misses caused by data stores per kilo instructions retired |CACHE.L3.STORE.MISS.SPEC / RETIRED.INST * 1000 -|CACHE.L3.STORE.MISS.RATE.SPEC |The ratio of speculative L3 cache misses to the total number of L3 accesses caused by data stores |CACHE.L3.STORE.MISS.SPEC / CACHE.L3.STORE.ACCESS.SPEC -|CACHE.L3.PREF.ISSUED.PKI |The rate of prefetcher requests issued by L3 to next level cache per kilo instructions retired |CACHE.L3.PREF.ISSUED / RETIRED.INST * 1000 -|CACHE.L3.PREF.MPKI |The rate of L3 cache misses caused by prefetcher per kilo instructions retired |CACHE.L3.PREF.MISS / RETIRED.INST * 1000 +|CACHE.L3.LOAD.SPEC.MPKI |The rate of speculative L3 cache misses caused by data loads per kilo instructions retired |CACHE.L3.LOAD.MISS.SPEC / INST.RET * 1000 +|CACHE.L3.LOAD.MISS.SPEC.RATE |The ratio of speculative L3 cache misses to the total number of L3 accesses caused by data loads |CACHE.L3.LOAD.MISS.SPEC / CACHE.L3.LOAD.ACCESS.SPEC +|CACHE.L3.STORE.SPEC.MPKI |The rate of speculative L3 cache misses caused by data stores per kilo instructions retired |CACHE.L3.STORE.MISS.SPEC / INST.RET * 1000 +|CACHE.L3.STORE.MISS.SPEC.RATE |The ratio of speculative L3 cache misses to the total number of L3 accesses caused by data stores |CACHE.L3.STORE.MISS.SPEC / CACHE.L3.STORE.ACCESS.SPEC +|CACHE.L3.PREF.ISSUED.PKI |The rate of prefetcher requests issued by L3 to next level cache per kilo instructions retired |CACHE.L3.PREF.ISSUED / INST.RET * 1000 +|CACHE.L3.PREF.MPKI |The rate of L3 cache misses caused by prefetcher per kilo instructions retired |CACHE.L3.PREF.MISS / INST.RET * 1000 |CACHE.L3.PREF.UNUSED.RATE |The ratio of unused cachelines brought into L3 by prefetcher to the total number of prefetcher requests issued by L3 |CACHE.L3.PREF.UNUSED / CACHE.L3.PREF.ISSUED |=== diff --git a/adoc_event_tables/prediction_metrics.adoc b/adoc_event_tables/prediction_metrics.adoc index 393199f..ffa687e 100644 --- a/adoc_event_tables/prediction_metrics.adoc +++ b/adoc_event_tables/prediction_metrics.adoc @@ -2,35 +2,35 @@ [width="100%",cols="25%,40%,35%",options="header",] |=== |Name |Description |Formula -|CTRL_FLOW.PKI |The rate of control flow instructions retired per kilo instructions |CTRL_FLOW.RET / RETIRED.INST * 1000 -|CTRL_FLOW.MPKI |The rate of control flow instructions mis-predicted per kilo instructions |CTRL_FLOW.MISPRED.RET / RETIRED.INST * 1000 +|CTRL_FLOW.PKI |The rate of control flow instructions retired per kilo instructions |CTRL_FLOW.RET / INST.RET * 1000 +|CTRL_FLOW.MPKI |The rate of control flow instructions mis-predicted per kilo instructions |CTRL_FLOW.MISPRED.RET / INST.RET * 1000 |CTRL_FLOW.MISPRED.RATE |The rate of control flow instructions mis-predicted to the overall predicted control flow instructions |CTRL_FLOW.MISPRED.RET / (CTRL_FLOW.RET - CTRL_FLOW.DIR_CALL.RET - CTRL_FLOW.DIR_JUMP.RET - CTRL_FLOW.DIR_JUMP_LINKAGE.RET) -|CTRL_FLOW.BRANCH.PKI |The rate of conditional branches retired per kilo instructions |CTRL_FLOW.BRANCH.RET / RETIRED.INST * 1000 -|CTRL_FLOW.BRANCH.MPKI |The rate of conditional branches mis-predicted per kilo instructions |CTRL_FLOW.BRANCH.MISPRED.RET / RETIRED.INST * 1000 +|CTRL_FLOW.BRANCH.PKI |The rate of conditional branches retired per kilo instructions |CTRL_FLOW.BRANCH.RET / INST.RET * 1000 +|CTRL_FLOW.BRANCH.MPKI |The rate of conditional branches mis-predicted per kilo instructions |CTRL_FLOW.BRANCH.MISPRED.RET / INST.RET * 1000 |CTRL_FLOW.BRANCH.MISPRED.RATE |The rate of conditional branches mis-predicted to the overall conditional branches |CTRL_FLOW.BRANCH.MISPRED.RET / CTRL_FLOW.BRANCH.RET -|CTRL_FLOW.IND_CALL.PKI |The rate of indirect calls retired per kilo instructions |CTRL_FLOW.IND_CALL.RET / RETIRED.INST * 1000 -|CTRL_FLOW.IND_CALL.MPKI |The rate of indirect calls mis-predicted per kilo instructions |CTRL_FLOW.IND_CALL.MISPRED.RET / RETIRED.INST * 1000 +|CTRL_FLOW.IND_CALL.PKI |The rate of indirect calls retired per kilo instructions |CTRL_FLOW.IND_CALL.RET / INST.RET * 1000 +|CTRL_FLOW.IND_CALL.MPKI |The rate of indirect calls mis-predicted per kilo instructions |CTRL_FLOW.IND_CALL.MISPRED.RET / INST.RET * 1000 |CTRL_FLOW.IND_CALL.MISPRED_RATE |The rate of indirect calls mis-predicted to the overall indirect calls |CTRL_FLOW.IND_CALL.MISPRED.RET / CTRL_FLOW.IND_CALL.RET -|CTRL_FLOW.DIR_CALL.PKI |The rate of direct calls retired per kilo instructions |CTRL_FLOW.DIR_CALL.RET / RETIRED.INST * 1000 -|CTRL_FLOW.DIR_CALL.MPKI |The rate of direct calls mis-predicted per kilo instructions |CTRL_FLOW.DIR_CALL.MISPRED.RET / RETIRED.INST * 1000 +|CTRL_FLOW.DIR_CALL.PKI |The rate of direct calls retired per kilo instructions |CTRL_FLOW.DIR_CALL.RET / INST.RET * 1000 +|CTRL_FLOW.DIR_CALL.MPKI |The rate of direct calls mis-predicted per kilo instructions |CTRL_FLOW.DIR_CALL.MISPRED.RET / INST.RET * 1000 |CTRL_FLOW.DIR_CALL.MISPRED.RATE |The rate of direct calls mis-predicted to the overall direct calls |CTRL_FLOW.DIR_CALL.MISPRED.RET / CTRL_FLOW.DIR_CALL.RET -|CTRL_FLOW.IND_JUMP.PKI |The rate of indirect jumps retired per kilo instructions |CTRL_FLOW.IND_JUMP.RET / RETIRED.INST * 1000 -|CTRL_FLOW.IND_JUMP.MPKI |The rate of indirect jumps mis-predicted per kilo instructions |CTRL_FLOW.IND_JUMP.MISPRED.RET / RETIRED.INST * 1000 +|CTRL_FLOW.IND_JUMP.PKI |The rate of indirect jumps retired per kilo instructions |CTRL_FLOW.IND_JUMP.RET / INST.RET * 1000 +|CTRL_FLOW.IND_JUMP.MPKI |The rate of indirect jumps mis-predicted per kilo instructions |CTRL_FLOW.IND_JUMP.MISPRED.RET / INST.RET * 1000 |CTRL_FLOW.IND_JUMP.MISPRED.RATE |The rate of indirect jumps mis-predicted to the overall indirect jumps |CTRL_FLOW.IND_JUMP.MISPRED.RET / CTRL_FLOW.IND_JUMP.RET -|CTRL_FLOW.DIR_JUMP.PKI |The rate of direct jumps retired per kilo instructions |CTRL_FLOW.DIR_JUMP.RET / RETIRED.INST * 1000 -|CTRL_FLOW.DIR_JUMP.MPKI |The rate of direct jumps mis-predicted per kilo instructions |CTRL_FLOW.DIR_JUMP.MISPRED.RET / RETIRED.INST * 1000 +|CTRL_FLOW.DIR_JUMP.PKI |The rate of direct jumps retired per kilo instructions |CTRL_FLOW.DIR_JUMP.RET / INST.RET * 1000 +|CTRL_FLOW.DIR_JUMP.MPKI |The rate of direct jumps mis-predicted per kilo instructions |CTRL_FLOW.DIR_JUMP.MISPRED.RET / INST.RET * 1000 |CTRL_FLOW.DIR_JUMP.MISPRED.RATE |The rate of direct jumps mis-predicted to the overall indirect jumps |CTRL_FLOW.DIR_JUMP.MISPRED.RET / CTRL_FLOW.DIR_JUMP.RET -|CTRL_FLOW.CORE_SWAP.PKI |The rate of co-routine swaps retired per kilo instructions |CTRL_FLOW.COR_SWAP.RET / RETIRED.INST * 1000 -|CTRL_FLOW.COR_SWAP.MPKI |The rate of co-routine swaps mis-predicted per kilo instructions |CTRL_FLOW.COR_SWAP.MISPRED.RET / RETIRED.INST * 1000 +|CTRL_FLOW.CORE_SWAP.PKI |The rate of co-routine swaps retired per kilo instructions |CTRL_FLOW.COR_SWAP.RET / INST.RET * 1000 +|CTRL_FLOW.COR_SWAP.MPKI |The rate of co-routine swaps mis-predicted per kilo instructions |CTRL_FLOW.COR_SWAP.MISPRED.RET / INST.RET * 1000 |CTRL_FLOW.COR_SWAP.MISPRED.RATE |The rate of co-routine swaps mis-predicted to the overall indirect jumps |CTRL_FLOW.COR_SWAP.MISPRED.RET / CTRL_FLOW.COR_SWAP.RET -|CTRL_FLOW.RETURN.PKI |The rate of function returns retired per kilo instructions |CTRL_FLOW.RETURN.RET / RETIRED.INST * 1000 -|CTRL_FLOW.RETURN.MPKI |The rate of function returns mis-predicted per kilo instructions |CTRL_FLOW.RETURN.MISPRED.RET / RETIRED.INST * 1000 +|CTRL_FLOW.RETURN.PKI |The rate of function returns retired per kilo instructions |CTRL_FLOW.RETURN.RET / INST.RET * 1000 +|CTRL_FLOW.RETURN.MPKI |The rate of function returns mis-predicted per kilo instructions |CTRL_FLOW.RETURN.MISPRED.RET / INST.RET * 1000 |CTRL_FLOW.RETURN.MISPRED.RATE |The rate of function returns mis-predicted to the overall function returns |CTRL_FLOW.RETURN.MISPRED.RET / CTRL_FLOW.RETURN.RET -|CTRL_FLOW.IND_JUMP_LINKAGE.PKI |The rate of indirect jumps (with linkage) retired per kilo instructions |CTRL_FLOW.IND_JUMP_LINKAGE.RET / RETIRED.INST * 1000 -|CTRL_FLOW.IND_JUMP_LINKAGE.MPKI |The rate of indirect jumps (with linkage) mis-predicted per kilo instructions |CTRL_FLOW.IND_JUMP_LINKAGE.MISPRED.RET / RETIRED.INST * 1000 +|CTRL_FLOW.IND_JUMP_LINKAGE.PKI |The rate of indirect jumps (with linkage) retired per kilo instructions |CTRL_FLOW.IND_JUMP_LINKAGE.RET / INST.RET * 1000 +|CTRL_FLOW.IND_JUMP_LINKAGE.MPKI |The rate of indirect jumps (with linkage) mis-predicted per kilo instructions |CTRL_FLOW.IND_JUMP_LINKAGE.MISPRED.RET / INST.RET * 1000 |CTRL_FLOW.IND_JUMP_LINKAGE.MISPRED.RATE |The rate of indirect jumps (with linkage) mis-predicted to the overall indirect jumps (with linkage) |CTRL_FLOW.IND_JUMP_LINKAGE.MISPRED.RET / CTRL_FLOW.IND_JUMP_LINKAGE.RET -|CTRL_FLOW.DIR_JUMP_LINKAGE.PKI |The rate of direct jumps (with linkage) retired per kilo instructions |CTRL_FLOW.DIR_JUMP_LINKAGE.RET / RETIRED.INST * 1000 -|CTRL_FLOW.DIR_JUMP_LINKAGE.MPKI |The rate of direct jumps (with linkage) mis-predicted per kilo instructions |CTRL_FLOW.DIR_JUMP_LINKAGE.MISPRED.RET / RETIRED.INST * 1000 +|CTRL_FLOW.DIR_JUMP_LINKAGE.PKI |The rate of direct jumps (with linkage) retired per kilo instructions |CTRL_FLOW.DIR_JUMP_LINKAGE.RET / INST.RET * 1000 +|CTRL_FLOW.DIR_JUMP_LINKAGE.MPKI |The rate of direct jumps (with linkage) mis-predicted per kilo instructions |CTRL_FLOW.DIR_JUMP_LINKAGE.MISPRED.RET / INST.RET * 1000 |CTRL_FLOW.DIR_JUMP_LINKAGE.MISPRED.RATE |The rate of direct jumps (with linkage) mis-predicted to the overall direct jumps (with linkage) |CTRL_FLOW.DIR_JUMP_LINKAGE.MISPRED.RET / CTRL_FLOW.DIR_JUMP_LINKAGE.RET |=== diff --git a/adoc_event_tables/prediction_retired.adoc b/adoc_event_tables/prediction_retired.adoc index d777f16..5bccd44 100644 --- a/adoc_event_tables/prediction_retired.adoc +++ b/adoc_event_tables/prediction_retired.adoc @@ -15,7 +15,7 @@ |CTRL_FLOW.DIR_JUMP.RET |Direct jumps (without linkage) retired. Direct jumps (without linkage) are defined using following encodings: 'JAL x0'; 'C.J' |CTRL_FLOW.DIR_JUMP.MISPRED.RET |Direct jumps (without linkage) mis-predicted. Direct jumps (without linkage) are defined using following encodings: 'JAL x0'; 'C.J' |CTRL_FLOW.COR_SWAP.RET |Co-routine swaps retired. Co-routine swaps are defined using following encodings: 'JALR x1, x5'; 'JALR x5, x1'; 'C.JALR x5' -|CTRL_FLOW.CORE_SWAP.MISPRED.RET |Co-routine swaps mis-predicted. Co-routine swaps are defined using following encodings: 'JALR x1, x5'; 'JALR x5, x1'; 'C.JALR x5' +|CTRL_FLOW.COR_SWAP.MISPRED.RET |Co-routine swaps mis-predicted. Co-routine swaps are defined using following encodings: 'JALR x1, x5'; 'JALR x5, x1'; 'C.JALR x5' |CTRL_FLOW.RETURN.RET |Function returns retired. Function returns are defined using following encodings: 'JALR rd, rs where rs == (x1 or x5) and rd != (x1 or x5)'; 'C.JR rs1 where rs1 == (x1 or x5)' |CTRL_FLOW.RETURN.MISPRED.RET |Function returns mis-predicted. Function returns are defined using following encodings: 'JALR rd, rs where rs == (x1 or x5) and rd != (x1 or x5)'; 'C.JR rs1 where rs1 == (x1 or x5)' |CTRL_FLOW.IND_JUMP_LINKAGE.RET |Other indirect jumps (with linkage) retired. Other indirect jump (with linkage) are defined using following encodings: 'JALR rd, rs where rs != (x1 or x5) and rd != (x0, x1, or x5)' diff --git a/adoc_event_tables/retired.adoc b/adoc_event_tables/retired.adoc index 2e54b09..6e0f0f3 100644 --- a/adoc_event_tables/retired.adoc +++ b/adoc_event_tables/retired.adoc @@ -2,12 +2,12 @@ [width="100%",cols="30%,70%",options="header",] |=== |Name |Description -|RETIRED.INST |Number of instructions retired -|RETIRED.MEM_LOAD |Number of memory load instructions retired -|RETIRED.MEM_LOAD.UC |Number of memory load instructions retired which accessed uncacheble memory -|RETIRED.MEM_STORE |Number of memory store instructions retired -|RETIRED.INT |Number of integer instructions retired -|RETIRED.FPU |Number of FPU instructions retired -|RETIRED.UOP |Number of micro-operations retired +|INST.RET |Number of instructions retired +|INST.LOAD.RET |Number of memory load instructions retired +|INST.LOAD.UC.RET |Number of memory load instructions retired which accessed uncacheble memory +|INST.STORE.RET |Number of memory store instructions retired +|INST.INT.RET |Number of integer instructions retired +|INST.FPU.RET |Number of FPU instructions retired +|UOP.RET |Number of micro-operations retired |=== diff --git a/adoc_event_tables/rvv_retired.adoc b/adoc_event_tables/rvv_retired.adoc index 5720815..7a3cd9e 100644 --- a/adoc_event_tables/rvv_retired.adoc +++ b/adoc_event_tables/rvv_retired.adoc @@ -2,9 +2,9 @@ [width="100%",cols="30%,70%",options="header",] |=== |Name |Description -|RVV.ALL.RET |Number of RVV instructions retired -|RVV.INT.RET |Number of integer RVV instructions retired -|RVV.FP.RET |Number of floating point RVV instructions retired +|INST.RVV.RET |Number of RVV instructions retired +|INST.RVV.INT.RET |Number of integer RVV instructions retired +|INST.RVV.FP.RET |Number of floating point RVV instructions retired |RVV.ELEMENT.UNMASKED.INT8.RET |Number of 8-bit integer element operation retired. For example, if we have SEW=8, LMUL=1, VLEN=128 and doing vector integer arith instruction - it should increment the RVV.ELEMENT.UNMASKED.INT8 counter by 16. Masked-out elements should not increment the counter - so in the previous example if half of the lanes are masked the RVV.ELEMENT.UNMASKED.INT8 will be incremented by 8. For multiply-add instructions each element operation should increment counter by 2 to account for both multiplication and addition. |RVV.ELEMENT.INT8.RET |Number of 8-bit integer element operation retired not taking into account masking. For example, if we have SEW=8, LMUL=1, VLEN=128 and doing vector integer arith instruction - it should increment the RVV.ELEMENT.INT8 counter by 16. Mask should not be taken into account - so in the previous example if half of the lanes are masked the RVV.ELEMENT.INT8 will still be incremented by 16. For multiply-add instructions each element operation should increment counter by 2 to account for both multiplication and addition. |RVV.ELEMENT.UNMASKED.INT16.RET |Number of 16-bit integer element operation retired. For example, if we have SEW=16, LMUL=1, VLEN=128 and doing vector integer arith instruction - it should increment the RVV.ELEMENT.UNMASKED.INT16 counter by 8. Masked-out elements should not increment the counter - so in the previous example half of the lanes are masked the RVV.ELEMENT.UNMASKED.INT16 counter will be incremented by 4. For multiply-add instructions each element operation should increment counter by 2 to account for both multiplication and addition. diff --git a/adoc_event_tables/rvv_spec.adoc b/adoc_event_tables/rvv_spec.adoc index 958804b..67c3688 100644 --- a/adoc_event_tables/rvv_spec.adoc +++ b/adoc_event_tables/rvv_spec.adoc @@ -2,9 +2,9 @@ [width="100%",cols="30%,70%",options="header",] |=== |Name |Description -|RVV.ALL.SPEC |Number of RVV instructions executed -|RVV.INT.SPEC |Number of integer RVV instructions executed -|RVV.FP.SPEC |Number of floating point RVV instructions executed +|INST.RVV.SPEC |Number of RVV instructions executed +|INST.RVV.INT.SPEC |Number of integer RVV instructions executed +|INST.RVV.FP.SPEC |Number of floating point RVV instructions executed |RVV.ELEMENT.UNMASKED.INT8.SPEC |Number of 8-bit integer element operation executed. For example, if we have SEW=8, LMUL=1, VLEN=128 and doing vector integer arith instruction - it should increment the RVV.ELEMENT.UNMASKED.INT8 counter by 16. Masked-out elements should not increment the counter - so in the previous example if half of the lanes are masked the RVV.ELEMENT.UNMASKED.INT8 will be incremented by 8. For multiply-add instructions each element operation should increment counter by 2 to account for both multiplication and addition. |RVV.ELEMENT.INT8.SPEC |Number of 8-bit integer element operation executed. For example, if we have SEW=8, LMUL=1, VLEN=128 and doing vector integer arith instruction - it should increment the RVV.ELEMENT.INT8 counter by 16. Mask should not be taken into account - so in the previous example if half of the lanes are masked the RVV.ELEMENT.INT8 will still be incremented by 16. For multiply-add instructions each element operation should increment counter by 2 to account for both multiplication and addition. |RVV.ELEMENT.UNMASKED.INT16.SPEC |Number of 16-bit integer element operation executed. For example, if we have SEW=16, LMUL=1, VLEN=128 and doing vector integer arith instruction - it should increment the RVV.ELEMENT.UNMASKED.INT16 counter by 8. Masked-out elements should not increment the counter - so in the previous example half of the lanes are masked the RVV.ELEMENT.UNMASKED.INT16 counter will be incremented by 4. For multiply-add instructions each element operation should increment counter by 2 to account for both multiplication and addition. diff --git a/adoc_event_tables/spec.adoc b/adoc_event_tables/spec.adoc index c6941bd..b95538b 100644 --- a/adoc_event_tables/spec.adoc +++ b/adoc_event_tables/spec.adoc @@ -2,11 +2,11 @@ [width="100%",cols="30%,70%",options="header",] |=== |Name |Description -|SPEC.INST_ISSUED |Number of instructions issued -|SPEC.MEM_LOAD_ISSUED |Number of memory load instructions issued -|SPEC.MEM_STORE_ISSUED |Number of memory store instructions issued -|SPEC.INT_ISSUED |Number of integer instructions issued -|SPEC.FPU_ISSUED |Number of FPU instructions issued -|SPEC.UOP_ISSUED |Number of micro-operations issued +|INST.ISSUED |Number of instructions issued +|INST.LOAD.ISSUED |Number of memory load instructions issued +|INST.STORE.ISSUED |Number of memory store instructions issued +|INST.INT.ISSUED |Number of integer instructions issued +|INST.FPU.ISSUED |Number of FPU instructions issued +|UOP.ISSUED |Number of micro-operations issued |=== diff --git a/adoc_event_tables/tlb_retired_metrics.adoc b/adoc_event_tables/tlb_retired_metrics.adoc index b036675..688e3c2 100644 --- a/adoc_event_tables/tlb_retired_metrics.adoc +++ b/adoc_event_tables/tlb_retired_metrics.adoc @@ -2,13 +2,13 @@ [width="100%",cols="25%,40%,35%",options="header",] |=== |Name |Description |Formula -|TLB.L1.LOAD.MPKI.RET |The rate of L1 TLB misses caused by data loads per kilo instructions retired |TLB.L1.LOAD.MISS.RET / RETIRED.INST * 1000 -|TLB.L1.LOAD.MISS.RATE |The ratio of L1 TLB load misses to the total number of L1 TLB load accesses retired |TLB.L1.LOAD.MISS.RET / TLB.L1.LOAD.ACCESS.RET -|TLB.L1.STORE.MPKI.RET |The rate of L1 TLB misses caused by data stores per kilo instructions retired |TLB.L1.STORE.MISS.RET / RETIRED.INST * 1000 -|TLB.L1.STORE.MISS.RATE |The ratio of L1 TLB store misses to the total number of L1 TLB store accesses retired |TLB.L1.STORE.MISS.RET / TLB.L1.STORE.ACCESS.RET -|TLB.L2.LOAD.MPKI.RET |The rate of L2 TLB misses caused by data loads per kilo instructions retired |TLB.L2.LOAD.MISS.RET / RETIRED.INST * 1000 -|TLB.L2.LOAD.MISS.RATE |The ratio of L2 TLB load misses to the total number of L2 TLB load accesses retired |TLB.L2.LOAD.MISS.RET / TLB.L2.LOAD.ACCESS.RET -|TLB.L2.STORE.MPKI.RET |The rate of L2 TLB misses caused by data stores per kilo instructions retired |TLB.L2.STORE.MISS.RET / RETIRED.INST * 1000 -|TLB.L2.STORE.MISS.RATE |The ratio of L2 TLB store misses to the total number of L2 TLB store accesses retired |TLB.L2.STORE.MISS.RET / TLB.L2.STORE.ACCESS.RET +|TLB.L1.LOAD.RET.MPKI |The rate of L1 TLB misses caused by data loads per kilo instructions retired |TLB.L1.LOAD.MISS.RET / INST.RET * 1000 +|TLB.L1.LOAD.RET.MISS.RATE |The ratio of L1 TLB load misses to the total number of L1 TLB load accesses retired |TLB.L1.LOAD.MISS.RET / TLB.L1.LOAD.ACCESS.RET +|TLB.L1.STORE.RET.MPKI |The rate of L1 TLB misses caused by data stores per kilo instructions retired |TLB.L1.STORE.MISS.RET / INST.RET * 1000 +|TLB.L1.STORE.MISS.RET.RATE |The ratio of L1 TLB store misses to the total number of L1 TLB store accesses retired |TLB.L1.STORE.MISS.RET / TLB.L1.STORE.ACCESS.RET +|TLB.L2.LOAD.RET.MPKI |The rate of L2 TLB misses caused by data loads per kilo instructions retired |TLB.L2.LOAD.MISS.RET / INST.RET * 1000 +|TLB.L2.LOAD.MISS.RET.RATE |The ratio of L2 TLB load misses to the total number of L2 TLB load accesses retired |TLB.L2.LOAD.MISS.RET / TLB.L2.LOAD.ACCESS.RET +|TLB.L2.STORE.RET.MPKI |The rate of L2 TLB misses caused by data stores per kilo instructions retired |TLB.L2.STORE.MISS.RET / INST.RET * 1000 +|TLB.L2.STORE.MISS.RET.RATE |The ratio of L2 TLB store misses to the total number of L2 TLB store accesses retired |TLB.L2.STORE.MISS.RET / TLB.L2.STORE.ACCESS.RET |=== diff --git a/adoc_event_tables/tlb_spec_metrics.adoc b/adoc_event_tables/tlb_spec_metrics.adoc index ac29b97..e81cd7e 100644 --- a/adoc_event_tables/tlb_spec_metrics.adoc +++ b/adoc_event_tables/tlb_spec_metrics.adoc @@ -2,18 +2,18 @@ [width="100%",cols="25%,40%,35%",options="header",] |=== |Name |Description |Formula -|TLB.L1.LOAD.MPKI.SPEC |The rate of L1 TLB misses caused by data loads per kilo instructions retired |TLB.L1.LOAD.MISS.SPEC / RETIRED.INST * 1000 -|TLB.L1.LOAD.MISS.RATE.SPEC |The ratio of L1 TLB load misses to the total number of L1 TLB load accesses |TLB.L1.LOAD.MISS.SPEC / TLB.L1.LOAD.ACCESS.SPEC -|TLB.L1.STORE.MPKI.SPEC |The rate of L1 TLB misses caused by data stores per kilo instructions retired |TLB.L1.STORE.MISS.SPEC / RETIRED.INST * 1000 -|TLB.L1.STORE.MISS.RATE.SPEC |The ratio of L1 TLB store misses to the total number of L1 TLB store accesses |TLB.L1.STORE.MISS.SPEC / TLB.L1.STORE.ACCESS.SPEC -|TLB.L1.CODE.MPKI.SPEC |The rate of L1 TLB misses caused by instruction fetches per kilo instructions retired |TLB.L1.CODE.MISS.SPEC / RETIRED.INST * 1000 -|TLB.L1.CODE.MISS.RATE.SPEC |The ratio of L1 TLB instruction fetch misses to the total number of L1 TLB instruction fetch accesses |TLB.L1.CODE.MISS.SPEC / TLB.L1.CODE.ACCESS -|TLB.L2.LOAD.MPKI.SPEC |The rate of L2 TLB misses caused by data loads per kilo instructions retired |TLB.L2.LOAD.MISS.SPEC / RETIRED.INST * 1000 -|TLB.L2.LOAD.MISS.RATE.SPEC |The ratio of L2 TLB load misses to the total number of L2 TLB load accesses |TLB.L2.LOAD.MISS.SPEC / TLB.L2.LOAD.ACCESS.SPEC -|TLB.L2.STORE.MPKI.SPEC |The rate of L2 TLB misses caused by data stores per kilo instructions retired |TLB.L2.STORE.MISS.SPEC / RETIRED.INST * 1000 -|TLB.L2.STORE.MISS.RATE.SPEC |The ratio of L2 TLB store misses to the total number of L2 TLB store accesses |TLB.L2.STORE.MISS.SPEC / TLB.L2.STORE.ACCESS -|TLB.L2.CODE.MPKI.SPEC |The rate of L2 TLB misses caused by instruction fetches per kilo instructions retired |TLB.L2.CODE.MISS.SPEC / RETIRED.INST * 1000 -|TLB.L2.CODE.MISS.RATE.SPEC |The ratio of L2 TLB instruction fetch misses to the total number of L2 TLB instruction fetch accesses |TLB.L2.CODE.MISS.SPEC / TLB.L2.CODE.ACCESS.SPEC +|TLB.L1.LOAD.SPEC.MPKI |The rate of L1 TLB misses caused by data loads per kilo instructions retired |TLB.L1.LOAD.MISS.SPEC / INST.RET * 1000 +|TLB.L1.LOAD.MISS.SPEC.RATE |The ratio of L1 TLB load misses to the total number of L1 TLB load accesses |TLB.L1.LOAD.MISS.SPEC / TLB.L1.LOAD.ACCESS.SPEC +|TLB.L1.STORE.SPEC.MPKI |The rate of L1 TLB misses caused by data stores per kilo instructions retired |TLB.L1.STORE.MISS.SPEC / INST.RET * 1000 +|TLB.L1.STORE.MISS.SPEC.RATE |The ratio of L1 TLB store misses to the total number of L1 TLB store accesses |TLB.L1.STORE.MISS.SPEC / TLB.L1.STORE.ACCESS.SPEC +|TLB.L1.CODE.SPEC.MPKI |The rate of L1 TLB misses caused by instruction fetches per kilo instructions retired |TLB.L1.CODE.MISS.SPEC / INST.RET * 1000 +|TLB.L1.CODE.MISS.SPEC.RATE |The ratio of L1 TLB instruction fetch misses to the total number of L1 TLB instruction fetch accesses |TLB.L1.CODE.MISS.SPEC / TLB.L1.CODE.ACCESS +|TLB.L2.LOAD.SPEC.MPKI |The rate of L2 TLB misses caused by data loads per kilo instructions retired |TLB.L2.LOAD.MISS.SPEC / INST.RET * 1000 +|TLB.L2.LOAD.MISS.SPEC.RATE |The ratio of L2 TLB load misses to the total number of L2 TLB load accesses |TLB.L2.LOAD.MISS.SPEC / TLB.L2.LOAD.ACCESS.SPEC +|TLB.L2.STORE.SPEC.MPKI |The rate of L2 TLB misses caused by data stores per kilo instructions retired |TLB.L2.STORE.MISS.SPEC / INST.RET * 1000 +|TLB.L2.STORE.MISS.SPEC.RATE |The ratio of L2 TLB store misses to the total number of L2 TLB store accesses |TLB.L2.STORE.MISS.SPEC / TLB.L2.STORE.ACCESS +|TLB.L2.CODE.SPEC.MPKI |The rate of L2 TLB misses caused by instruction fetches per kilo instructions retired |TLB.L2.CODE.MISS.SPEC / INST.RET * 1000 +|TLB.L2.CODE.MISS.SPEC.RATE |The ratio of L2 TLB instruction fetch misses to the total number of L2 TLB instruction fetch accesses |TLB.L2.CODE.MISS.SPEC / TLB.L2.CODE.ACCESS.SPEC |TLB.L1.MISS.IMPACT |The approximate ratio of cycles lost due to TLB (all levels) missed by load instructions |TLB.L1.LOAD.MISS_OUTSTANDING.CYCLES / CYCLES.HART |TLB.L2.MISS.IMPACT |The approximate ratio of cycles lost due to L2 TLB missed by load instructions |TLB.L2.LOAD.MISS_OUTSTANDING.CYCLES / CYCLES.HART |TLB.L2.HIT.IMPACT |The approximate ratio of cycles lost due to L1 TLB missed and L2 TLB hit by load instructions |(TLB.L1.LOAD.MISS_OUTSTANDING.CYCLES - TLB.L2.LOAD.MISS_OUTSTANDING.CYCLES) / CYCLES.HART diff --git a/adoc_event_tables/topdown_metrics.adoc b/adoc_event_tables/topdown_metrics.adoc index 8d50bca..3495058 100644 --- a/adoc_event_tables/topdown_metrics.adoc +++ b/adoc_event_tables/topdown_metrics.adoc @@ -3,14 +3,14 @@ |=== |Name |Description |Formula |TOPDOWN.SLOTS |For implementations which do not provide TOPDOWN.SLOTS as explicit event it is possible to calculate it as metric using CYCLES.HART event. |pipeline_width * CYCLES.HART -|TOPDOWN.BAD_SPECULATION.SLOTS |For implementations which do not provide TOPDOWN.BAD_SPECULATION.SLOTS as explicit event it is possible to calculate it as metric. It consiste of two part - the number of cancelled operations (SPEC.UOP_ISSUED - RETIRED.UOP) and the number of slots wasted on recovery from pipeline flush (pipeline_width * PRD.PIPELINE_FLUSH.RECOVERY_CYCLES) |SPEC.UOP_ISSUED - RETIRED.UOP + pipeline_width * PRD.PIPELINE_FLUSH.RECOVERY_CYCLES +|TOPDOWN.BAD_SPECULATION.SLOTS |For implementations which do not provide TOPDOWN.BAD_SPECULATION.SLOTS as explicit event it is possible to calculate it as metric. It consiste of two part - the number of cancelled operations (UOP.ISSUED - UOP.RET) and the number of slots wasted on recovery from pipeline flush (pipeline_width * PRD.PIPELINE_FLUSH.RECOVERY_CYCLES) |UOP.ISSUED - UOP.RET + pipeline_width * PRD.PIPELINE_FLUSH.RECOVERY_CYCLES |TOPDOWN.BACKEND_BOUND.CORE.SLOTS |For implementations which do not provide TOPDOWN.BACKEND_BOUND.CORE.SLOTS as explicit event it is possible to calculate it as metric by subtracting memory bound slots from all backend bound slots |TOPDOWN.BACKEND_BOUND.SLOTS - TOPDOWN.BACKEND_BOUND.MEMORY.SLOTS |TOPDOWN.BAD_SPECULATION |Fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. |TOPDOWN.BAD_SPECULATION.SLOTS / TOPDOWN.SLOTS |TOPDOWN.BAD_SPECULATION.MISPRED.RATE |Fraction of slots wasted due to incorrect control flow speculations |TOPDOWN.BAD_SPECULATION.MISPRED.SLOTS / TOPDOWN.SLOTS |TOPDOWN.BAD_SPECULATION.MEM_ORDERING.RATE |Fraction of slots wasted due to memory ordering violations |TOPDOWN.BAD_SPECULATION.MEM_ORDERING.SLOTS / TOPDOWN.SLOTS |TOPDOWN.BAD_SPECULATION.OTHER.RATE |Fraction of slots wasted due to reasons other than control flow mis-speculations or memory ordering violations |TOPDOWN.BAD_SPECULATION.MEM_ORDERING.SLOTS / TOPDOWN.SLOTS |TOPDOWN.FRONTEND_BOUND.RATE |Fraction of slots unused due to the frontend did not supply enough operations. Frontend Bound denotes unutilized slots when there is no Backend stall - i.e. when Frontend delivered no uops while Backend could have accepted them. For example, stalls due to instruction cache misses would be categorized under Frontend Bound. |TOPDOWN.FRONTEND_BOUND.SLOTS / TOPDOWN.SLOTS -|TOPDOWN.RETIRING.RATE |Fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (IPC). |RETIRED.UOP / TOPDOWN.SLOTS +|TOPDOWN.RETIRING.RATE |Fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (IPC). |UOP.RET / TOPDOWN.SLOTS |TOPDOWN.BACKEND_BOUND.RATE |Fraction of slots unused due to the due to lack of backend resources. Backend Bound denotes unutilized slots due to a lack of required resources for accepting new uops in the Backend. |TOPDOWN.BACKEND_BOUND.SLOTS / TOPDOWN.SLOTS |TOPDOWN.BACKEND_BOUND.MEMORY_BOUND.RATE |Fraction of slots unused due to the memory subsystem stalls inside the backend. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two). |TOPDOWN.BACKEND_BOUND.MEMORY.SLOTS / TOPDOWN.SLOTS |TOPDOWN.BACKEND_BOUND.CORE_BOUND.RATE |Fraction of slots unused due to the non-memory stalls inside the backend. Shortage in hardware compute resources or dependencies in software instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. chained long-latency arithmetic operations). |TOPDOWN.BACKEND_BOUND.CORE.SLOTS / TOPDOWN.SLOTS diff --git a/event_files/cache_retired.json b/event_files/cache_retired.json index 0e4ee11..1a88b6b 100644 --- a/event_files/cache_retired.json +++ b/event_files/cache_retired.json @@ -71,6 +71,12 @@ "BriefDescription": "Retired load instruction which got data from L2 cache", "PublicDescription": "Retired load instruction which got data from L2 cache" }, + { + "EventName": "CACHE.L2.LOAD.MERGE.RET", + "EventCode": "0x0", + "BriefDescription": "Retired load instruction which hit L2 cache with data not yet in cache but was already requested by preceding miss", + "PublicDescription": "Retired load instruction which hit L2 cache with data not yet in cache but was already requested by preceding miss" + }, { "EventName": "CACHE.L3.LOAD.ACCESS.RET", "EventCode": "0x0", @@ -90,19 +96,25 @@ "PublicDescription": "Retired load instruction which got data from L3 cache" }, { - "EventName": "CACHE.L3.LOAD.MISS.LOCAL_MEMORY.RET", + "EventName": "CACHE.L3.LOAD.MERGE.RET", + "EventCode": "0x0", + "BriefDescription": "Retired load instruction which hit L3 cache with data not yet in cache but was already requested by preceding miss", + "PublicDescription": "Retired load instruction which hit L3 cache with data not yet in cache but was already requested by preceding miss" + }, + { + "EventName": "CACHE.LOAD.LOCAL_MEMORY.RET", "EventCode": "0x0", "BriefDescription": "Retired load instruction which got data from local memory.", "PublicDescription": "Retired load instruction which got data from local memory." }, { - "EventName": "CACHE.L3.LOAD.MISS.REMOTE_MEMORY.RET", + "EventName": "CACHE.LOAD.REMOTE_MEMORY.RET", "EventCode": "0x0", "BriefDescription": "Retired load instruction which got data from remote memory (memory attached to remote socket).", "PublicDescription": "Retired load instruction which got data from remote memory (memory attached to remote socket)." }, { - "EventName": "CACHE.L3.LOAD.MISS.REMOTE_CACHE.RET", + "EventName": "CACHE.LOAD.REMOTE_CACHE.RET", "EventCode": "0x0", "BriefDescription": "Retired load instruction which got data from remote cache (cache on remote socket).", "PublicDescription": "Retired load instruction which got data from remote cache (cache on remote socket)." diff --git a/event_files/cache_retired_metrics.json b/event_files/cache_retired_metrics.json index fe97e9c..8b94df6 100644 --- a/event_files/cache_retired_metrics.json +++ b/event_files/cache_retired_metrics.json @@ -1,69 +1,69 @@ [ { - "MetricName": "CACHE.L1D.LOAD.MPKI.RET", + "MetricName": "CACHE.L1D.LOAD.RET.MPKI", "BriefDescription": "The rate of retired L1 data load cache misses per kilo instructions retired", - "MetricExpr": "CACHE.L1D.LOAD.MISS.RET / RETIRED.INST * 1000", + "MetricExpr": "CACHE.L1D.LOAD.MISS.RET / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, { - "MetricName": "CACHE.L1D.LOAD.MISS.RATE.RET", + "MetricName": "CACHE.L1D.LOAD.MISS.RET.RATE", "BriefDescription": "The ratio of retired L1D cache load misses to the total number of retired L1D load accesses", "MetricExpr": "CACHE.L1D.LOAD.MISS.RET / CACHE.L1D.LOAD.ACCESS.RET", "MetricGroup": "Cache", "ScaleUnit": "100%" }, { - "MetricName": "CACHE.L1D.LOAD.MERGE.PKI.RET", + "MetricName": "CACHE.L1D.LOAD.MERGE.RET.PKI", "BriefDescription": "The rate of retired L1 data load cache misses which merged with previous cache miss per kilo instructions retired", - "MetricExpr": "CACHE.L1D.LOAD.MERGE.RET / RETIRED.INST * 1000", + "MetricExpr": "CACHE.L1D.LOAD.MERGE.RET / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, { - "MetricName": "CACHE.L1I.MPKI.RET", + "MetricName": "CACHE.L1I.RET.MPKI", "BriefDescription": "The rate of retired instructions with L1 instruction cache misses per kilo instructions retired", - "MetricExpr": "CACHE.L1I.MISS.RET / RETIRED.INST * 1000", + "MetricExpr": "CACHE.L1I.MISS.RET / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, { - "MetricName": "CACHE.L1D.STORE.MPKI.RET", + "MetricName": "CACHE.L1D.STORE.RET.MPKI", "BriefDescription": "The rate of retired L1 data store cache misses per kilo instructions retired", - "MetricExpr": "CACHE.L1D.STORE.MISS.RET / RETIRED.INST * 1000", + "MetricExpr": "CACHE.L1D.STORE.MISS.RET / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, { - "MetricName": "CACHE.L1D.STORE.MISS.RATE.RET", + "MetricName": "CACHE.L1D.STORE.MISS.RET.RATE", "BriefDescription": "The ratio of retired L1D cache store misses to the total number of retired L1D store accesses", "MetricExpr": "CACHE.L1D.STORE.MISS.RET / CACHE.L1D.STORE.ACCESS.RET", "MetricGroup": "Cache", "ScaleUnit": "100%" }, { - "MetricName": "CACHE.L2.LOAD.MPKI.RET", + "MetricName": "CACHE.L2.LOAD.RET.MPKI", "BriefDescription": "The rate of retired L2 data load cache misses per kilo instructions retired", - "MetricExpr": "CACHE.L2.LOAD.MISS.RET / RETIRED.INST * 1000", + "MetricExpr": "CACHE.L2.LOAD.MISS.RET / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, { - "MetricName": "CACHE.L2.LOAD.MISS.RATE.RET", + "MetricName": "CACHE.L2.LOAD.MISS.RET.RATE", "BriefDescription": "The ratio of retired L2 cache load misses to the total number of retired L2 load accesses", "MetricExpr": "CACHE.L2.LOAD.MISS.RET / CACHE.L2.LOAD.ACCESS.RET", "MetricGroup": "Cache", "ScaleUnit": "100%" }, { - "MetricName": "CACHE.L3.LOAD.MPKI.RET", + "MetricName": "CACHE.L3.LOAD.RET.MPKI", "BriefDescription": "The rate of retired L3 data load cache misses per kilo instructions retired", - "MetricExpr": "CACHE.L3.LOAD.MISS.RET / RETIRED.INST * 1000", + "MetricExpr": "CACHE.L3.LOAD.MISS.RET / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, { - "MetricName": "CACHE.L3.LOAD.MISS.RATE.RET", + "MetricName": "CACHE.L3.LOAD.MISS.RET.RATE", "BriefDescription": "The ratio of retired L3 cache load misses to the total number of retired L3 load accesses", "MetricExpr": "CACHE.L3.LOAD.MISS.RET / CACHE.L3.LOAD.ACCESS.RET", "MetricGroup": "Cache", diff --git a/event_files/cache_spec_metrics.json b/event_files/cache_spec_metrics.json index fbb44b7..915b1bc 100644 --- a/event_files/cache_spec_metrics.json +++ b/event_files/cache_spec_metrics.json @@ -1,34 +1,34 @@ [ { - "MetricName": "CACHE.L1D.LOAD.MPKI.SPEC", + "MetricName": "CACHE.L1D.LOAD.SPEC.MPKI", "BriefDescription": "The rate of speculative L1 data cache misses caused by data loads per kilo instructions retired", - "MetricExpr": "CACHE.L1D.LOAD.MISS.SPEC / RETIRED.INST * 1000", + "MetricExpr": "CACHE.L1D.LOAD.MISS.SPEC / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, { - "MetricName": "CACHE.L1D.LOAD.MISS.RATE.SPEC", + "MetricName": "CACHE.L1D.LOAD.MISS.SPEC.RATE", "BriefDescription": "The ratio of speculative L1D cache misses to the total number of L1D accesses caused by data loads", "MetricExpr": "CACHE.L1D.LOAD.MISS.SPEC / CACHE.L1D.LOAD.ACCESS.SPEC", "MetricGroup": "Cache", "ScaleUnit": "100%" }, { - "MetricName": "CACHE.L1D.LOAD.MERGE.PKI.SPEC", + "MetricName": "CACHE.L1D.LOAD.MERGE.SPEC.PKI", "BriefDescription": "The rate of speculative L1 data cache accesses which merged with previous cache miss per kilo instructions retired", - "MetricExpr": "CACHE.L1D.LOAD.MERGE.SPEC / RETIRED.INST * 1000", + "MetricExpr": "CACHE.L1D.LOAD.MERGE.SPEC / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, { - "MetricName": "CACHE.L1D.STORE.MPKI.SPEC", + "MetricName": "CACHE.L1D.STORE.SPEC.MPKI", "BriefDescription": "The rate of speculative L1 data cache misses caused by data stores per kilo instructions retired", - "MetricExpr": "CACHE.L1D.STORE.MISS.SPEC / RETIRED.INST * 1000", + "MetricExpr": "CACHE.L1D.STORE.MISS.SPEC / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, { - "MetricName": "CACHE.L1D.STORE.MISS.RATE.SPEC", + "MetricName": "CACHE.L1D.STORE.MISS.SPEC.RATE", "BriefDescription": "The ratio of speculative L1D cache misses to the total number of L1D accesses caused by data stores", "MetricExpr": "CACHE.L1D.STORE.MISS.SPEC / CACHE.L1D.STORE.ACCESS.SPEC", "MetricGroup": "Cache", @@ -37,7 +37,7 @@ { "MetricName": "CACHE.L1D.PREF.ISSUED.PKI", "BriefDescription": "The rate of prefetcher requests issued by L1D to next level cache per kilo instructions retired", - "MetricExpr": "CACHE.L1D.PREF.ISSUED / RETIRED.INST * 1000", + "MetricExpr": "CACHE.L1D.PREF.ISSUED / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, @@ -49,23 +49,23 @@ "ScaleUnit": "100%" }, { - "MetricName": "CACHE.L1I.MPKI.SPEC", + "MetricName": "CACHE.L1I.SPEC.MPKI", "BriefDescription": "The rate of L1 instruction cache misses per kilo instructions retired", - "MetricExpr": "CACHE.L1I.MISS.SPEC / RETIRED.INST * 1000", + "MetricExpr": "CACHE.L1I.MISS.SPEC / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, { - "MetricName": "CACHE.L1I.MISS.RATE.SPEC", + "MetricName": "CACHE.L1I.MISS.SPEC.RATE", "BriefDescription": "The ratio of L1 instruction cache misses to the total number of L1I accesses", "MetricExpr": "CACHE.L1I.MISS.SPEC / CACHE.L1I.ACCESS.SPEC", "MetricGroup": "Cache", "ScaleUnit": "100%" }, { - "MetricName": "CACHE.L1I.MERGE.PKI.SPEC", + "MetricName": "CACHE.L1I.MERGE.SPEC.PKI", "BriefDescription": "The rate of L1 instruction cache accesses which merged with previous cache miss per kilo instructions retired", - "MetricExpr": "CACHE.L1I.MERGE.SPEC / RETIRED.INST * 1000", + "MetricExpr": "CACHE.L1I.MERGE.SPEC / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, @@ -77,51 +77,51 @@ "ScaleUnit": "100%" }, { - "MetricName": "CACHE.L2.LOAD.MPKI.SPEC", + "MetricName": "CACHE.L2.LOAD.SPEC.MPKI", "BriefDescription": "The rate of speculative L2 cache misses caused by data loads per kilo instructions retired", - "MetricExpr": "CACHE.L2.LOAD.MISS.SPEC / RETIRED.INST * 1000", + "MetricExpr": "CACHE.L2.LOAD.MISS.SPEC / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, { - "MetricName": "CACHE.L2.LOAD.MISS.RATE.SPEC", + "MetricName": "CACHE.L2.LOAD.MISS.SPEC.RATE", "BriefDescription": "The ratio of speculative L2 cache misses to the total number of L2 accesses caused by data loads", "MetricExpr": "CACHE.L2.LOAD.MISS.SPEC / CACHE.L2.LOAD.ACCESS.SPEC", "MetricGroup": "Cache", "ScaleUnit": "100%" }, { - "MetricName": "CACHE.L2.STORE.MPKI.SPEC", + "MetricName": "CACHE.L2.STORE.SPEC.MPKI", "BriefDescription": "The rate of speculative L2 cache misses caused by data stores per kilo instructions retired", - "MetricExpr": "CACHE.L2.STORE.MISS.SPEC / RETIRED.INST * 1000", + "MetricExpr": "CACHE.L2.STORE.MISS.SPEC / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, { - "MetricName": "CACHE.L2.STORE.MISS.RATE.SPEC", + "MetricName": "CACHE.L2.STORE.MISS.SPEC.RATE", "BriefDescription": "The ratio of speculative L2 cache misses to the total number of L2 accesses caused by data stores", "MetricExpr": "CACHE.L2.STORE.MISS.SPEC / CACHE.L2.STORE.ACCESS.SPEC", "MetricGroup": "Cache", "ScaleUnit": "100%" }, { - "MetricName": "CACHE.L2.STORE.HIT.RFO.PKI.SPEC", + "MetricName": "CACHE.L2.STORE.HIT.RFO.SPEC.PKI", "BriefDescription": "The rate of L2 cache hits for store instructions with the purpose to get exclusive ownership per kilo instructions retired", - "MetricExpr": "CACHE.L2.STORE.HIT.RFO.SPEC / RETIRED.INST * 1000", + "MetricExpr": "CACHE.L2.STORE.HIT.RFO.SPEC / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, { "MetricName": "CACHE.L2.PREF.ISSUED.PKI", "BriefDescription": "The rate of prefetcher requests issued by L2 to next level cache per kilo instructions retired", - "MetricExpr": "CACHE.L2.PREF.ISSUED / RETIRED.INST * 1000", + "MetricExpr": "CACHE.L2.PREF.ISSUED / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, { "MetricName": "CACHE.L2.PREF.MPKI", "BriefDescription": "The rate of L2 cache misses caused by prefetcher per kilo instructions retired", - "MetricExpr": "CACHE.L2.PREF.MISS / RETIRED.INST * 1000", + "MetricExpr": "CACHE.L2.PREF.MISS / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, @@ -133,28 +133,28 @@ "ScaleUnit": "100%" }, { - "MetricName": "CACHE.L3.LOAD.MPKI.SPEC", + "MetricName": "CACHE.L3.LOAD.SPEC.MPKI", "BriefDescription": "The rate of speculative L3 cache misses caused by data loads per kilo instructions retired", - "MetricExpr": "CACHE.L3.LOAD.MISS.SPEC / RETIRED.INST * 1000", + "MetricExpr": "CACHE.L3.LOAD.MISS.SPEC / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, { - "MetricName": "CACHE.L3.LOAD.MISS.RATE.SPEC", + "MetricName": "CACHE.L3.LOAD.MISS.SPEC.RATE", "BriefDescription": "The ratio of speculative L3 cache misses to the total number of L3 accesses caused by data loads", "MetricExpr": "CACHE.L3.LOAD.MISS.SPEC / CACHE.L3.LOAD.ACCESS.SPEC", "MetricGroup": "Cache", "ScaleUnit": "100%" }, { - "MetricName": "CACHE.L3.STORE.MPKI.SPEC", + "MetricName": "CACHE.L3.STORE.SPEC.MPKI", "BriefDescription": "The rate of speculative L3 cache misses caused by data stores per kilo instructions retired", - "MetricExpr": "CACHE.L3.STORE.MISS.SPEC / RETIRED.INST * 1000", + "MetricExpr": "CACHE.L3.STORE.MISS.SPEC / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, { - "MetricName": "CACHE.L3.STORE.MISS.RATE.SPEC", + "MetricName": "CACHE.L3.STORE.MISS.SPEC.RATE", "BriefDescription": "The ratio of speculative L3 cache misses to the total number of L3 accesses caused by data stores", "MetricExpr": "CACHE.L3.STORE.MISS.SPEC / CACHE.L3.STORE.ACCESS.SPEC", "MetricGroup": "Cache", @@ -163,14 +163,14 @@ { "MetricName": "CACHE.L3.PREF.ISSUED.PKI", "BriefDescription": "The rate of prefetcher requests issued by L3 to next level cache per kilo instructions retired", - "MetricExpr": "CACHE.L3.PREF.ISSUED / RETIRED.INST * 1000", + "MetricExpr": "CACHE.L3.PREF.ISSUED / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, { "MetricName": "CACHE.L3.PREF.MPKI", "BriefDescription": "The rate of L3 cache misses caused by prefetcher per kilo instructions retired", - "MetricExpr": "CACHE.L3.PREF.MISS / RETIRED.INST * 1000", + "MetricExpr": "CACHE.L3.PREF.MISS / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, diff --git a/event_files/prediction_metrics.json b/event_files/prediction_metrics.json index de02fee..af7fc6b 100644 --- a/event_files/prediction_metrics.json +++ b/event_files/prediction_metrics.json @@ -2,14 +2,14 @@ { "MetricName": "CTRL_FLOW.PKI", "BriefDescription": "The rate of control flow instructions retired per kilo instructions", - "MetricExpr": "CTRL_FLOW.RET / RETIRED.INST * 1000", + "MetricExpr": "CTRL_FLOW.RET / INST.RET * 1000", "MetricGroup": "Prediction", "ScaleUnit": "1PKI" }, { "MetricName": "CTRL_FLOW.MPKI", "BriefDescription": "The rate of control flow instructions mis-predicted per kilo instructions", - "MetricExpr": "CTRL_FLOW.MISPRED.RET / RETIRED.INST * 1000", + "MetricExpr": "CTRL_FLOW.MISPRED.RET / INST.RET * 1000", "MetricGroup": "Prediction", "ScaleUnit": "1MPKI" }, @@ -23,14 +23,14 @@ { "MetricName": "CTRL_FLOW.BRANCH.PKI", "BriefDescription": "The rate of conditional branches retired per kilo instructions", - "MetricExpr": "CTRL_FLOW.BRANCH.RET / RETIRED.INST * 1000", + "MetricExpr": "CTRL_FLOW.BRANCH.RET / INST.RET * 1000", "MetricGroup": "Prediction", "ScaleUnit": "1PKI" }, { "MetricName": "CTRL_FLOW.BRANCH.MPKI", "BriefDescription": "The rate of conditional branches mis-predicted per kilo instructions", - "MetricExpr": "CTRL_FLOW.BRANCH.MISPRED.RET / RETIRED.INST * 1000", + "MetricExpr": "CTRL_FLOW.BRANCH.MISPRED.RET / INST.RET * 1000", "MetricGroup": "Prediction", "ScaleUnit": "1MPKI" }, @@ -44,14 +44,14 @@ { "MetricName": "CTRL_FLOW.IND_CALL.PKI", "BriefDescription": "The rate of indirect calls retired per kilo instructions", - "MetricExpr": "CTRL_FLOW.IND_CALL.RET / RETIRED.INST * 1000", + "MetricExpr": "CTRL_FLOW.IND_CALL.RET / INST.RET * 1000", "MetricGroup": "Prediction", "ScaleUnit": "1PKI" }, { "MetricName": "CTRL_FLOW.IND_CALL.MPKI", "BriefDescription": "The rate of indirect calls mis-predicted per kilo instructions", - "MetricExpr": "CTRL_FLOW.IND_CALL.MISPRED.RET / RETIRED.INST * 1000", + "MetricExpr": "CTRL_FLOW.IND_CALL.MISPRED.RET / INST.RET * 1000", "MetricGroup": "Prediction", "ScaleUnit": "1MPKI" }, @@ -65,14 +65,14 @@ { "MetricName": "CTRL_FLOW.DIR_CALL.PKI", "BriefDescription": "The rate of direct calls retired per kilo instructions", - "MetricExpr": "CTRL_FLOW.DIR_CALL.RET / RETIRED.INST * 1000", + "MetricExpr": "CTRL_FLOW.DIR_CALL.RET / INST.RET * 1000", "MetricGroup": "Prediction", "ScaleUnit": "1PKI" }, { "MetricName": "CTRL_FLOW.DIR_CALL.MPKI", "BriefDescription": "The rate of direct calls mis-predicted per kilo instructions", - "MetricExpr": "CTRL_FLOW.DIR_CALL.MISPRED.RET / RETIRED.INST * 1000", + "MetricExpr": "CTRL_FLOW.DIR_CALL.MISPRED.RET / INST.RET * 1000", "MetricGroup": "Prediction", "ScaleUnit": "1MPKI" }, @@ -86,14 +86,14 @@ { "MetricName": "CTRL_FLOW.IND_JUMP.PKI", "BriefDescription": "The rate of indirect jumps retired per kilo instructions", - "MetricExpr": "CTRL_FLOW.IND_JUMP.RET / RETIRED.INST * 1000", + "MetricExpr": "CTRL_FLOW.IND_JUMP.RET / INST.RET * 1000", "MetricGroup": "Prediction", "ScaleUnit": "1PKI" }, { "MetricName": "CTRL_FLOW.IND_JUMP.MPKI", "BriefDescription": "The rate of indirect jumps mis-predicted per kilo instructions", - "MetricExpr": "CTRL_FLOW.IND_JUMP.MISPRED.RET / RETIRED.INST * 1000", + "MetricExpr": "CTRL_FLOW.IND_JUMP.MISPRED.RET / INST.RET * 1000", "MetricGroup": "Prediction", "ScaleUnit": "1MPKI" }, @@ -107,14 +107,14 @@ { "MetricName": "CTRL_FLOW.DIR_JUMP.PKI", "BriefDescription": "The rate of direct jumps retired per kilo instructions", - "MetricExpr": "CTRL_FLOW.DIR_JUMP.RET / RETIRED.INST * 1000", + "MetricExpr": "CTRL_FLOW.DIR_JUMP.RET / INST.RET * 1000", "MetricGroup": "Prediction", "ScaleUnit": "1PKI" }, { "MetricName": "CTRL_FLOW.DIR_JUMP.MPKI", "BriefDescription": "The rate of direct jumps mis-predicted per kilo instructions", - "MetricExpr": "CTRL_FLOW.DIR_JUMP.MISPRED.RET / RETIRED.INST * 1000", + "MetricExpr": "CTRL_FLOW.DIR_JUMP.MISPRED.RET / INST.RET * 1000", "MetricGroup": "Prediction", "ScaleUnit": "1MPKI" }, @@ -128,14 +128,14 @@ { "MetricName": "CTRL_FLOW.CORE_SWAP.PKI", "BriefDescription": "The rate of co-routine swaps retired per kilo instructions", - "MetricExpr": "CTRL_FLOW.COR_SWAP.RET / RETIRED.INST * 1000", + "MetricExpr": "CTRL_FLOW.COR_SWAP.RET / INST.RET * 1000", "MetricGroup": "Prediction", "ScaleUnit": "1PKI" }, { "MetricName": "CTRL_FLOW.COR_SWAP.MPKI", "BriefDescription": "The rate of co-routine swaps mis-predicted per kilo instructions", - "MetricExpr": "CTRL_FLOW.COR_SWAP.MISPRED.RET / RETIRED.INST * 1000", + "MetricExpr": "CTRL_FLOW.COR_SWAP.MISPRED.RET / INST.RET * 1000", "MetricGroup": "Prediction", "ScaleUnit": "1MPKI" }, @@ -149,14 +149,14 @@ { "MetricName": "CTRL_FLOW.RETURN.PKI", "BriefDescription": "The rate of function returns retired per kilo instructions", - "MetricExpr": "CTRL_FLOW.RETURN.RET / RETIRED.INST * 1000", + "MetricExpr": "CTRL_FLOW.RETURN.RET / INST.RET * 1000", "MetricGroup": "Prediction", "ScaleUnit": "1PKI" }, { "MetricName": "CTRL_FLOW.RETURN.MPKI", "BriefDescription": "The rate of function returns mis-predicted per kilo instructions", - "MetricExpr": "CTRL_FLOW.RETURN.MISPRED.RET / RETIRED.INST * 1000", + "MetricExpr": "CTRL_FLOW.RETURN.MISPRED.RET / INST.RET * 1000", "MetricGroup": "Prediction", "ScaleUnit": "1MPKI" }, @@ -170,14 +170,14 @@ { "MetricName": "CTRL_FLOW.IND_JUMP_LINKAGE.PKI", "BriefDescription": "The rate of indirect jumps (with linkage) retired per kilo instructions", - "MetricExpr": "CTRL_FLOW.IND_JUMP_LINKAGE.RET / RETIRED.INST * 1000", + "MetricExpr": "CTRL_FLOW.IND_JUMP_LINKAGE.RET / INST.RET * 1000", "MetricGroup": "Prediction", "ScaleUnit": "1PKI" }, { "MetricName": "CTRL_FLOW.IND_JUMP_LINKAGE.MPKI", "BriefDescription": "The rate of indirect jumps (with linkage) mis-predicted per kilo instructions", - "MetricExpr": "CTRL_FLOW.IND_JUMP_LINKAGE.MISPRED.RET / RETIRED.INST * 1000", + "MetricExpr": "CTRL_FLOW.IND_JUMP_LINKAGE.MISPRED.RET / INST.RET * 1000", "MetricGroup": "Prediction", "ScaleUnit": "1MPKI" }, @@ -191,14 +191,14 @@ { "MetricName": "CTRL_FLOW.DIR_JUMP_LINKAGE.PKI", "BriefDescription": "The rate of direct jumps (with linkage) retired per kilo instructions", - "MetricExpr": "CTRL_FLOW.DIR_JUMP_LINKAGE.RET / RETIRED.INST * 1000", + "MetricExpr": "CTRL_FLOW.DIR_JUMP_LINKAGE.RET / INST.RET * 1000", "MetricGroup": "Prediction", "ScaleUnit": "1PKI" }, { "MetricName": "CTRL_FLOW.DIR_JUMP_LINKAGE.MPKI", "BriefDescription": "The rate of direct jumps (with linkage) mis-predicted per kilo instructions", - "MetricExpr": "CTRL_FLOW.DIR_JUMP_LINKAGE.MISPRED.RET / RETIRED.INST * 1000", + "MetricExpr": "CTRL_FLOW.DIR_JUMP_LINKAGE.MISPRED.RET / INST.RET * 1000", "MetricGroup": "Prediction", "ScaleUnit": "1MPKI" }, diff --git a/event_files/prediction_retired.json b/event_files/prediction_retired.json index acdc3f4..d73c44e 100644 --- a/event_files/prediction_retired.json +++ b/event_files/prediction_retired.json @@ -78,7 +78,7 @@ "PublicDescription": "Co-routine swaps retired. Co-routine swaps are defined using following encodings: 'JALR x1, x5'; 'JALR x5, x1'; 'C.JALR x5'" }, { - "EventName": "CTRL_FLOW.CORE_SWAP.MISPRED.RET", + "EventName": "CTRL_FLOW.COR_SWAP.MISPRED.RET", "EventCode": "0x0", "BriefDescription": "Co-routine swaps mis-predicted", "PublicDescription": "Co-routine swaps mis-predicted. Co-routine swaps are defined using following encodings: 'JALR x1, x5'; 'JALR x5, x1'; 'C.JALR x5'" diff --git a/event_files/retired.json b/event_files/retired.json index afcd25c..4520c91 100644 --- a/event_files/retired.json +++ b/event_files/retired.json @@ -1,42 +1,42 @@ [ { - "EventName": "RETIRED.INST", + "EventName": "INST.RET", "EventCode": "0x0", "BriefDescription": "Number of instructions retired", "PublicDescription": "Number of instructions retired" }, { - "EventName": "RETIRED.MEM_LOAD", + "EventName": "INST.LOAD.RET", "EventCode": "0x0", "BriefDescription": "Number of memory load instructions retired", "PublicDescription": "Number of memory load instructions retired" }, { - "EventName": "RETIRED.MEM_LOAD.UC", + "EventName": "INST.LOAD.UC.RET", "EventCode": "0x0", "BriefDescription": "Number of memory load instructions retired which accessed uncacheble memory", "PublicDescription": "Number of memory load instructions retired which accessed uncacheble memory" }, { - "EventName": "RETIRED.MEM_STORE", + "EventName": "INST.STORE.RET", "EventCode": "0x0", "BriefDescription": "Number of memory store instructions retired", "PublicDescription": "Number of memory store instructions retired" }, { - "EventName": "RETIRED.INT", + "EventName": "INST.INT.RET", "EventCode": "0x0", "BriefDescription": "Number of integer instructions retired", "PublicDescription": "Number of integer instructions retired" }, { - "EventName": "RETIRED.FPU", + "EventName": "INST.FPU.RET", "EventCode": "0x0", "BriefDescription": "Number of FPU instructions retired", "PublicDescription": "Number of FPU instructions retired" }, { - "EventName": "RETIRED.UOP", + "EventName": "UOP.RET", "EventCode": "0x0", "BriefDescription": "Number of micro-operations retired", "PublicDescription": "Number of micro-operations retired" diff --git a/event_files/rvv_retired.json b/event_files/rvv_retired.json index cc90e47..09dfdb0 100644 --- a/event_files/rvv_retired.json +++ b/event_files/rvv_retired.json @@ -1,18 +1,18 @@ [ { - "EventName": "RVV.ALL.RET", + "EventName": "INST.RVV.RET", "EventCode": "0x0", "BriefDescription": "Number of RVV instructions retired", "PublicDescription": "Number of RVV instructions retired" }, { - "EventName": "RVV.INT.RET", + "EventName": "INST.RVV.INT.RET", "EventCode": "0x0", "BriefDescription": "Number of integer RVV instructions retired", "PublicDescription": "Number of integer RVV instructions retired" }, { - "EventName": "RVV.FP.RET", + "EventName": "INST.RVV.FP.RET", "EventCode": "0x0", "BriefDescription": "Number of floating point RVV instructions retired", "PublicDescription": "Number of floating point RVV instructions retired" diff --git a/event_files/rvv_spec.json b/event_files/rvv_spec.json index 5d8adec..66a65b8 100644 --- a/event_files/rvv_spec.json +++ b/event_files/rvv_spec.json @@ -1,18 +1,18 @@ [ { - "EventName": "RVV.ALL.SPEC", + "EventName": "INST.RVV.SPEC", "EventCode": "0x0", "BriefDescription": "Number of RVV instructions executed", "PublicDescription": "Number of RVV instructions executed" }, { - "EventName": "RVV.INT.SPEC", + "EventName": "INST.RVV.INT.SPEC", "EventCode": "0x0", "BriefDescription": "Number of integer RVV instructions executed", "PublicDescription": "Number of integer RVV instructions executed" }, { - "EventName": "RVV.FP.SPEC", + "EventName": "INST.RVV.FP.SPEC", "EventCode": "0x0", "BriefDescription": "Number of floating point RVV instructions executed", "PublicDescription": "Number of floating point RVV instructions executed" diff --git a/event_files/spec.json b/event_files/spec.json index bdad06b..ca3d835 100644 --- a/event_files/spec.json +++ b/event_files/spec.json @@ -1,36 +1,36 @@ [ { - "EventName": "SPEC.INST_ISSUED", + "EventName": "INST.ISSUED", "EventCode": "0x0", "BriefDescription": "Number of instructions issued", "PublicDescription": "Number of instructions issued" }, { - "EventName": "SPEC.MEM_LOAD_ISSUED", + "EventName": "INST.LOAD.ISSUED", "EventCode": "0x0", "BriefDescription": "Number of memory load instructions issued", "PublicDescription": "Number of memory load instructions issued" }, { - "EventName": "SPEC.MEM_STORE_ISSUED", + "EventName": "INST.STORE.ISSUED", "EventCode": "0x0", "BriefDescription": "Number of memory store instructions issued", "PublicDescription": "Number of memory store instructions issued" }, { - "EventName": "SPEC.INT_ISSUED", + "EventName": "INST.INT.ISSUED", "EventCode": "0x0", "BriefDescription": "Number of integer instructions issued", "PublicDescription": "Number of integer instructions issued" }, { - "EventName": "SPEC.FPU_ISSUED", + "EventName": "INST.FPU.ISSUED", "EventCode": "0x0", "BriefDescription": "Number of FPU instructions issued", "PublicDescription": "Number of FPU instructions issued" }, { - "EventName": "SPEC.UOP_ISSUED", + "EventName": "UOP.ISSUED", "EventCode": "0x0", "BriefDescription": "Number of micro-operations issued", "PublicDescription": "Number of micro-operations issued" diff --git a/event_files/tlb_retired_metrics.json b/event_files/tlb_retired_metrics.json index 1646a90..0b3029c 100644 --- a/event_files/tlb_retired_metrics.json +++ b/event_files/tlb_retired_metrics.json @@ -1,55 +1,55 @@ [ { - "MetricName": "TLB.L1.LOAD.MPKI.RET", + "MetricName": "TLB.L1.LOAD.RET.MPKI", "BriefDescription": "The rate of L1 TLB misses caused by data loads per kilo instructions retired", - "MetricExpr": "TLB.L1.LOAD.MISS.RET / RETIRED.INST * 1000", + "MetricExpr": "TLB.L1.LOAD.MISS.RET / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, { - "MetricName": "TLB.L1.LOAD.MISS.RATE", + "MetricName": "TLB.L1.LOAD.RET.MISS.RATE", "BriefDescription": "The ratio of L1 TLB load misses to the total number of L1 TLB load accesses retired", "MetricExpr": "TLB.L1.LOAD.MISS.RET / TLB.L1.LOAD.ACCESS.RET", "MetricGroup": "Cache", "ScaleUnit": "100%" }, { - "MetricName": "TLB.L1.STORE.MPKI.RET", + "MetricName": "TLB.L1.STORE.RET.MPKI", "BriefDescription": "The rate of L1 TLB misses caused by data stores per kilo instructions retired", - "MetricExpr": "TLB.L1.STORE.MISS.RET / RETIRED.INST * 1000", + "MetricExpr": "TLB.L1.STORE.MISS.RET / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, { - "MetricName": "TLB.L1.STORE.MISS.RATE", + "MetricName": "TLB.L1.STORE.MISS.RET.RATE", "BriefDescription": "The ratio of L1 TLB store misses to the total number of L1 TLB store accesses retired", "MetricExpr": "TLB.L1.STORE.MISS.RET / TLB.L1.STORE.ACCESS.RET", "MetricGroup": "Cache", "ScaleUnit": "100%" }, { - "MetricName": "TLB.L2.LOAD.MPKI.RET", + "MetricName": "TLB.L2.LOAD.RET.MPKI", "BriefDescription": "The rate of L2 TLB misses caused by data loads per kilo instructions retired", - "MetricExpr": "TLB.L2.LOAD.MISS.RET / RETIRED.INST * 1000", + "MetricExpr": "TLB.L2.LOAD.MISS.RET / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, { - "MetricName": "TLB.L2.LOAD.MISS.RATE", + "MetricName": "TLB.L2.LOAD.MISS.RET.RATE", "BriefDescription": "The ratio of L2 TLB load misses to the total number of L2 TLB load accesses retired", "MetricExpr": "TLB.L2.LOAD.MISS.RET / TLB.L2.LOAD.ACCESS.RET", "MetricGroup": "Cache", "ScaleUnit": "100%" }, { - "MetricName": "TLB.L2.STORE.MPKI.RET", + "MetricName": "TLB.L2.STORE.RET.MPKI", "BriefDescription": "The rate of L2 TLB misses caused by data stores per kilo instructions retired", - "MetricExpr": "TLB.L2.STORE.MISS.RET / RETIRED.INST * 1000", + "MetricExpr": "TLB.L2.STORE.MISS.RET / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, { - "MetricName": "TLB.L2.STORE.MISS.RATE", + "MetricName": "TLB.L2.STORE.MISS.RET.RATE", "BriefDescription": "The ratio of L2 TLB store misses to the total number of L2 TLB store accesses retired", "MetricExpr": "TLB.L2.STORE.MISS.RET / TLB.L2.STORE.ACCESS.RET", "MetricGroup": "Cache", diff --git a/event_files/tlb_spec_metrics.json b/event_files/tlb_spec_metrics.json index 1ede436..8d56019 100644 --- a/event_files/tlb_spec_metrics.json +++ b/event_files/tlb_spec_metrics.json @@ -1,83 +1,83 @@ [ { - "MetricName": "TLB.L1.LOAD.MPKI.SPEC", + "MetricName": "TLB.L1.LOAD.SPEC.MPKI", "BriefDescription": "The rate of L1 TLB misses caused by data loads per kilo instructions retired", - "MetricExpr": "TLB.L1.LOAD.MISS.SPEC / RETIRED.INST * 1000", + "MetricExpr": "TLB.L1.LOAD.MISS.SPEC / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, { - "MetricName": "TLB.L1.LOAD.MISS.RATE.SPEC", + "MetricName": "TLB.L1.LOAD.MISS.SPEC.RATE", "BriefDescription": "The ratio of L1 TLB load misses to the total number of L1 TLB load accesses", "MetricExpr": "TLB.L1.LOAD.MISS.SPEC / TLB.L1.LOAD.ACCESS.SPEC", "MetricGroup": "Cache", "ScaleUnit": "100%" }, { - "MetricName": "TLB.L1.STORE.MPKI.SPEC", + "MetricName": "TLB.L1.STORE.SPEC.MPKI", "BriefDescription": "The rate of L1 TLB misses caused by data stores per kilo instructions retired", - "MetricExpr": "TLB.L1.STORE.MISS.SPEC / RETIRED.INST * 1000", + "MetricExpr": "TLB.L1.STORE.MISS.SPEC / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, { - "MetricName": "TLB.L1.STORE.MISS.RATE.SPEC", + "MetricName": "TLB.L1.STORE.MISS.SPEC.RATE", "BriefDescription": "The ratio of L1 TLB store misses to the total number of L1 TLB store accesses", "MetricExpr": "TLB.L1.STORE.MISS.SPEC / TLB.L1.STORE.ACCESS.SPEC", "MetricGroup": "Cache", "ScaleUnit": "100%" }, { - "MetricName": "TLB.L1.CODE.MPKI.SPEC", + "MetricName": "TLB.L1.CODE.SPEC.MPKI", "BriefDescription": "The rate of L1 TLB misses caused by instruction fetches per kilo instructions retired", - "MetricExpr": "TLB.L1.CODE.MISS.SPEC / RETIRED.INST * 1000", + "MetricExpr": "TLB.L1.CODE.MISS.SPEC / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, { - "MetricName": "TLB.L1.CODE.MISS.RATE.SPEC", + "MetricName": "TLB.L1.CODE.MISS.SPEC.RATE", "BriefDescription": "The ratio of L1 TLB instruction fetch misses to the total number of L1 TLB instruction fetch accesses", "MetricExpr": "TLB.L1.CODE.MISS.SPEC / TLB.L1.CODE.ACCESS", "MetricGroup": "Cache", "ScaleUnit": "100%" }, { - "MetricName": "TLB.L2.LOAD.MPKI.SPEC", + "MetricName": "TLB.L2.LOAD.SPEC.MPKI", "BriefDescription": "The rate of L2 TLB misses caused by data loads per kilo instructions retired", - "MetricExpr": "TLB.L2.LOAD.MISS.SPEC / RETIRED.INST * 1000", + "MetricExpr": "TLB.L2.LOAD.MISS.SPEC / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, { - "MetricName": "TLB.L2.LOAD.MISS.RATE.SPEC", + "MetricName": "TLB.L2.LOAD.MISS.SPEC.RATE", "BriefDescription": "The ratio of L2 TLB load misses to the total number of L2 TLB load accesses", "MetricExpr": "TLB.L2.LOAD.MISS.SPEC / TLB.L2.LOAD.ACCESS.SPEC", "MetricGroup": "Cache", "ScaleUnit": "100%" }, { - "MetricName": "TLB.L2.STORE.MPKI.SPEC", + "MetricName": "TLB.L2.STORE.SPEC.MPKI", "BriefDescription": "The rate of L2 TLB misses caused by data stores per kilo instructions retired", - "MetricExpr": "TLB.L2.STORE.MISS.SPEC / RETIRED.INST * 1000", + "MetricExpr": "TLB.L2.STORE.MISS.SPEC / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, { - "MetricName": "TLB.L2.STORE.MISS.RATE.SPEC", + "MetricName": "TLB.L2.STORE.MISS.SPEC.RATE", "BriefDescription": "The ratio of L2 TLB store misses to the total number of L2 TLB store accesses", "MetricExpr": "TLB.L2.STORE.MISS.SPEC / TLB.L2.STORE.ACCESS", "MetricGroup": "Cache", "ScaleUnit": "100%" }, { - "MetricName": "TLB.L2.CODE.MPKI.SPEC", + "MetricName": "TLB.L2.CODE.SPEC.MPKI", "BriefDescription": "The rate of L2 TLB misses caused by instruction fetches per kilo instructions retired", - "MetricExpr": "TLB.L2.CODE.MISS.SPEC / RETIRED.INST * 1000", + "MetricExpr": "TLB.L2.CODE.MISS.SPEC / INST.RET * 1000", "MetricGroup": "Cache", "ScaleUnit": "1PKI" }, { - "MetricName": "TLB.L2.CODE.MISS.RATE.SPEC", + "MetricName": "TLB.L2.CODE.MISS.SPEC.RATE", "BriefDescription": "The ratio of L2 TLB instruction fetch misses to the total number of L2 TLB instruction fetch accesses", "MetricExpr": "TLB.L2.CODE.MISS.SPEC / TLB.L2.CODE.ACCESS.SPEC", "MetricGroup": "Cache", diff --git a/event_files/topdown_metrics.json b/event_files/topdown_metrics.json index fad4f23..0b83fc5 100644 --- a/event_files/topdown_metrics.json +++ b/event_files/topdown_metrics.json @@ -7,8 +7,8 @@ }, { "MetricName": "TOPDOWN.BAD_SPECULATION.SLOTS", - "BriefDescription": "For implementations which do not provide TOPDOWN.BAD_SPECULATION.SLOTS as explicit event it is possible to calculate it as metric. It consiste of two part - the number of cancelled operations (SPEC.UOP_ISSUED - RETIRED.UOP) and the number of slots wasted on recovery from pipeline flush (pipeline_width * PRD.PIPELINE_FLUSH.RECOVERY_CYCLES)", - "MetricExpr": "SPEC.UOP_ISSUED - RETIRED.UOP + pipeline_width * PRD.PIPELINE_FLUSH.RECOVERY_CYCLES" + "BriefDescription": "For implementations which do not provide TOPDOWN.BAD_SPECULATION.SLOTS as explicit event it is possible to calculate it as metric. It consiste of two part - the number of cancelled operations (UOP.ISSUED - UOP.RET) and the number of slots wasted on recovery from pipeline flush (pipeline_width * PRD.PIPELINE_FLUSH.RECOVERY_CYCLES)", + "MetricExpr": "UOP.ISSUED - UOP.RET + pipeline_width * PRD.PIPELINE_FLUSH.RECOVERY_CYCLES" }, { "MetricName": "TOPDOWN.BACKEND_BOUND.CORE.SLOTS", @@ -58,7 +58,7 @@ { "MetricName": "TOPDOWN.RETIRING.RATE", "BriefDescription": "Fraction of slots utilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "RETIRED.UOP / TOPDOWN.SLOTS", + "MetricExpr": "UOP.RET / TOPDOWN.SLOTS", "MetricThreshold": "TOPDOWN.RETIRING.RATE > 0.75", "PublicDescription": "Fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (IPC).", "ScaleUnit": "100%" diff --git a/intro.adoc b/intro.adoc index 0da337f..13c962c 100644 --- a/intro.adoc +++ b/intro.adoc @@ -3,10 +3,10 @@ The RISC-V hardware performance monitoring counters (Zihpm) provide support for counting programmable performance events. Such events can provide insights into software execution behavior, insights that are critical when tuning a profiled workload. However, no performance events are standardized, which means profiling tools must comprehend a custom set of events specific to each hardware implementation. This prevents profiling tools from offering general-purpose, event-based analysis capabilities that can be employed regardless of the underlying hardware implementation. -The Performance Events non-ISA extension provides a set of standard performance events and metrics (or formulas of events). For each standard event, the name and the precise hardware behavior associated with it will be specified. For each standard metric, the name, precise description, and event formula, including the names of the constituent events, will be defined. +The Performance Events non-ISA extension provides a set of standard performance events and metrics (or formulas of events). For each standard event, the name and the precise hardware behavior associated with it is specified. For each standard metric, the name, precise description, and event formula, including the names of the constituent events, is defined. [NOTE] [%unbreakable] ==== -This extension does not standardize event selector values - these will be left up to implementations. +This extension does not standardize event selector values - these are left up to implementations. ==== \ No newline at end of file