From 8b7fb2464ae2969d555c82c751878d3b07a89bad Mon Sep 17 00:00:00 2001 From: beeman Date: Wed, 9 Oct 2024 13:05:04 -0700 Subject: [PATCH 01/13] minor text improvements, plus rewrite of TMA chapter --- body.adoc | 33 +++++++++++++++++++++++++-------- 1 file changed, 25 insertions(+), 8 deletions(-) diff --git a/body.adoc b/body.adoc index bbfd09f..81509e0 100644 --- a/body.adoc +++ b/body.adoc @@ -4,10 +4,10 @@ All the events and metrics are split between several groups which are described in details sub-sections below. In addition most of the groups are further split into 2 variants: -* RETIRED - for events counted at retirement. For example, CACHE_RETIRED.L2.LOAD.MISS event will count L2 misses caused by retired load instructions -* SPEC - for speculative events. For example, CACHE_SPEC.L2.LOAD.MISS event will count L2 misses caused by load instructions regardless of whether they were retired or not. +* RET - for non-speculative events counted at retirement. For example, INST.RET counts retired instructions. +* SPEC - for speculative events. For example, INST.SPEC counts instructions that are issued to the backend pipeline, regardless of whether they retire. -In general RETIRED events look more useful for performance analysis. In addition in the future it may be possible to provide more context for them - e.g. precise sample IP. But on the other hand they it may be significantly more expensive to implement. It is up to implementations to decide if they want to provide RETIRED, SPEC or both variants of a group. +NOTE: _In general, RET events are more useful for performance analysis, since they are consistent with software's view of the instruction flow. But they can be significantly more expensive to implement, as they require event data to be staged along with the associated instruction to retirement. It is up to implementations to decide whether to support the RET, SPEC, or both variants of an event._ === GEN @@ -29,7 +29,7 @@ include::adoc_event_tables/spec.adoc[] === CTRL_FLOW (retirement) -Retirement control flow group which contains events and metrics for measuring things branch mispredictions, data mis-speculations etc. +Retirement control flow group which contains events and metrics for counting all control transfer instructions, or just those that were mispredicted, including breakdowns by transfer type. include::adoc_event_tables/prediction_retired.adoc[] @@ -77,12 +77,29 @@ include::adoc_event_tables/tlb_spec_metrics.adoc[] This group contains events and metrics related for Topdown Microarchitecture Analysis (TMA) methodology. -The TMA methodology categorizes CPU execution time at a high level first. This step flags (reports high fraction value) some domain(s) for possible investigation. Next, the user can drill down into those flagged domains, and can safely ignore all non-flagged domains. The process is repeated in a hierarchical manner until a specific performance issue is determined or at least a small subset of candidate issues is identified for potential investigation. +TMA allows even developers with minimal microarchitecture knowledge to understand, for a given workload, where bottlenecks reside. It does so by accounting for the utilization of each pipeline "slot" in the microarchitecture. When the hardware is utilized with optimal efficiency, each slot is occupied by an instruction or micro-operation (a.k.a., uop) that will go on to execute and retire. When bottlenecks occur, due perhaps to a cache miss, branch misprediction, or any number of other microarchitectural conditions, some slots may be either unused or thrown away, which results in inefficiency and ultimately reduced performance. TMA is able to identify these wasted slots, and the stalls, clears, misses, or other events which caused them. This enables developers to make informed decisions when tuning their code. -Given the highly sophisticated microarchitecture, the first interesting question is how and where to do the first level breakdown? TMA chooses the issue point as it is the natural border that splits the frontend and backend portions of machine. +TMA accomplishes this by defining a set of hierarchical states into which each slot falls, based on the boundary between the frontend (instruction fetch and decode) and the backend (instruction execution and retire) of the processor. Each cycle, the frontend can issue some implementation-defined number _N_ instructions/uops to the backend, hence there are _N_ issue slots to be categorized per cycle. At the top level, issue slots fall into one of states depicted in the figure below. -At issue point it classifies each pipeline-slot into one of four base categories: Frontend Bound, Backend Bound, Bad Speculation and Retiring. -If a uop is issued in a given cycle, it would eventually either get retired or cancelled. Thus it can be attributed to either Retiring or Bad Speculation respectively. Otherwise it can be split into whether there was a backend-stall or not. A backend-stall is a backpressure mechanism the Backend asserts upon resource unavailability (e.g. lack of load buffer entries). In such a case TMA attributes the stall to the Backend, since even if the Frontend was ready with more uops it would not be able to pass them down the pipeline. If there was no backend-stall, it means the Frontend should have delivered some uops while the Backend was ready to accept them; hence it is tagged with Frontend Bound. +.Topdown Level 1 +image::images/tma-l1.png[TMA Level 1] + +* Frontend Bound - The frontend did not issue a uop to the backend for execution. Example causes include stalls that result from cache or TLB misses during instruction fetch. +* Backend Bound - The backend could not consume an uop from the frontend. Example causes include backpressure that results from cache or TLB misses on data (load/store) accesses, or from oversubscribed execution units. +* Bad Speculation - The uop was dropped, as a result of a pipeline clear. Example clears include branch/jump mispredictions, or memory ordering clears. This category also includes pipeline clear recovery cycles, during which issue slots go unfilled. +* Retiring - The uop retired. Ideally the majority of slots fall into this state. + +Many of the top-level states listed above include further breakdown at the 2nd and 3rd levels of the TMA hierarchy. See details in the figure below. + +.Topdown Hierarchy +image::images/tma-full.png[TMA Hierarchy] + +[NOTE] +==== +_Some imprecision within the event hierarchy is allowed and even expected. The standard L2 and L3 events are unlikely to sum precisely to the parent L1 or L2 events, respectively, as it is expected that there are additional sources of bottlenecks beyond those represented by the standard events. The exception is the Backend Bound L2 events (Core Bound and Memory Bound), which ideally should sum to the Backend Bound event total._ + +_Implementations may opt to add custom L2 or L3 events, to identify additional bottlenecks specific to the microarchitecture._ +==== include::adoc_event_tables/topdown.adoc[] From 47d655a676f638b01d1d4b0ab2ae119cf3c54a89 Mon Sep 17 00:00:00 2001 From: beeman Date: Wed, 9 Oct 2024 13:05:38 -0700 Subject: [PATCH 02/13] add non-normative section, comment on replacing events with formulas --- intro.adoc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/intro.adoc b/intro.adoc index 13c962c..c6ec555 100644 --- a/intro.adoc +++ b/intro.adoc @@ -9,4 +9,6 @@ The Performance Events non-ISA extension provides a set of standard performance [%unbreakable] ==== This extension does not standardize event selector values - these are left up to implementations. + +An implementation may opt to support any of the standard events described below as an event formula rather than a hardware event. As an example, for a typical implementation, the TOPDOWN.SLOTS event count could be derived from CYCLES.HART * ConstantIssueWidth. It is strongly advised that any such formulas require counting no more events than the number of programmable counters implemented can support simultaneously. Requiring the workload to be run multiple times to satisfy a single formula risks run-to-run noise reducing the fidelity of the profile results. Also, implementing an event as a formula means that the user cannot use Sscofpmf to sample on that event. Thus care should be taken when choosing which (if any) events to support in this manner. ==== \ No newline at end of file From 7ebf616b80fb78d4e60401f387666920e7076def Mon Sep 17 00:00:00 2001 From: beeman Date: Wed, 9 Oct 2024 13:06:09 -0700 Subject: [PATCH 03/13] update TG and extension name --- header.adoc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/header.adoc b/header.adoc index d564306..4772fa9 100644 --- a/header.adoc +++ b/header.adoc @@ -1,7 +1,7 @@ = RISC-V Performance Events Authors: Author 1, Author 2 -:docgroup: RISC-V Task Group -:description: RISC-V Performance Events +:docgroup: RISC-V Performance Events TG +:description: RISC-V Hart Performance Events :company: RISC-V.org :revdate: 09/2024 :revnumber: 1.0 From 98f103d78d14242cc9528e0c1525abc8bcea2eaa Mon Sep 17 00:00:00 2001 From: beeman Date: Wed, 9 Oct 2024 13:06:46 -0700 Subject: [PATCH 04/13] update extension name again --- header.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/header.adoc b/header.adoc index 4772fa9..164de2a 100644 --- a/header.adoc +++ b/header.adoc @@ -1,4 +1,4 @@ -= RISC-V Performance Events += RISC-V Hart Performance Events Authors: Author 1, Author 2 :docgroup: RISC-V Performance Events TG :description: RISC-V Hart Performance Events From 6f32bed53c28019e3403c2edfa401ffb465785e5 Mon Sep 17 00:00:00 2001 From: beeman Date: Wed, 9 Oct 2024 13:07:12 -0700 Subject: [PATCH 05/13] add non-normative section, comment on replacing events with formulas --- intro.adoc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/intro.adoc b/intro.adoc index c6ec555..40589ee 100644 --- a/intro.adoc +++ b/intro.adoc @@ -8,7 +8,7 @@ The Performance Events non-ISA extension provides a set of standard performance [NOTE] [%unbreakable] ==== -This extension does not standardize event selector values - these are left up to implementations. +_This extension does not standardize event selector values - these are left up to implementations._ -An implementation may opt to support any of the standard events described below as an event formula rather than a hardware event. As an example, for a typical implementation, the TOPDOWN.SLOTS event count could be derived from CYCLES.HART * ConstantIssueWidth. It is strongly advised that any such formulas require counting no more events than the number of programmable counters implemented can support simultaneously. Requiring the workload to be run multiple times to satisfy a single formula risks run-to-run noise reducing the fidelity of the profile results. Also, implementing an event as a formula means that the user cannot use Sscofpmf to sample on that event. Thus care should be taken when choosing which (if any) events to support in this manner. +_An implementation may opt to support any of the standard events described below as an event formula rather than a hardware event. As an example, for a typical implementation, the TOPDOWN.SLOTS event count could be derived from CYCLES.HART * ConstantIssueWidth. It is strongly advised that any such formulas require counting no more events than the number of programmable counters implemented can support simultaneously. Requiring the workload to be run multiple times to satisfy a single formula risks run-to-run noise reducing the fidelity of the profile results. Also, implementing an event as a formula means that the user cannot use Sscofpmf to sample on that event. Thus care should be taken when choosing which (if any) events to support in this manner._ ==== \ No newline at end of file From 66cc400b8657200d9af1387a08803c47edace879 Mon Sep 17 00:00:00 2001 From: beeman Date: Wed, 9 Oct 2024 13:07:34 -0700 Subject: [PATCH 06/13] add Dmitriy and Beeman as contributors --- contributors.adoc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/contributors.adoc b/contributors.adoc index 13fd776..a55e6ea 100644 --- a/contributors.adoc +++ b/contributors.adoc @@ -3,5 +3,5 @@ This RISC-V specification has been contributed to directly or indirectly by: [%hardbreaks] -* Author1 -* Author2 +* Dmitry Ryabtsev +* Beeman Strong From 6357647697260aed86526ff0cbdc77831d8d3913 Mon Sep 17 00:00:00 2001 From: beeman Date: Wed, 9 Oct 2024 13:08:09 -0700 Subject: [PATCH 07/13] add TMA flowchart and diagram images --- images/tma-full.png | Bin 0 -> 27122 bytes images/tma-l1.png | Bin 0 -> 24014 bytes 2 files changed, 0 insertions(+), 0 deletions(-) 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zr-Scb^W=-jA1}M-@=gJJi&RM$h;W*1DW}j~QXw3(NfuSHAWHO^GS=wX_&~>l?Q}5z zDz7H#&RQvBg{ARjgSWynKC3Uzap*t2>cO#TgB#cwj2%_GQo~wQI_oW~i*@qpAc+;5 z3JuTKv#_abCZ5N9%8MZ1y2cQ5->P%_>jC8bo*YRd)ul8D_)k&pifoCranSz<1DD!} literal 0 HcmV?d00001 From e4d79edc555350cbbdb4efac2a11fa6df35db165 Mon Sep 17 00:00:00 2001 From: beeman Date: Wed, 9 Oct 2024 14:37:21 -0700 Subject: [PATCH 08/13] fix image paths, author --- header.adoc | 6 +++--- images/tma-full.png | Bin 27122 -> 0 bytes images/tma-full.svg | 4 ++++ images/tma-l1.png | Bin 24014 -> 0 bytes images/tma-l1.svg | 4 ++++ 5 files changed, 11 insertions(+), 3 deletions(-) delete mode 100644 images/tma-full.png create mode 100644 images/tma-full.svg delete mode 100644 images/tma-l1.png create mode 100644 images/tma-l1.svg diff --git a/header.adoc b/header.adoc index 164de2a..ecc2a23 100644 --- a/header.adoc +++ b/header.adoc @@ -1,5 +1,5 @@ = RISC-V Hart Performance Events -Authors: Author 1, Author 2 +Authors: RISC-V Performance Events TG :docgroup: RISC-V Performance Events TG :description: RISC-V Hart Performance Events :company: RISC-V.org @@ -12,8 +12,8 @@ Authors: Author 1, Author 2 :preface-title: Preamble :colophon: :appendix-caption: Appendix -:imagesdir: docs-resources/images -:title-logo-image: image:risc-v_logo.png[pdfwidth=3.25in,align=center] +:imagesdir: +:title-logo-image: image:docs-resources/images/risc-v_logo.png[pdfwidth=3.25in,align=center] // Settings: :experimental: :reproducible: diff --git a/images/tma-full.png b/images/tma-full.png deleted file mode 100644 index b4e634de44695292d2157cc2a7ad94c6fa089593..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 27122 zcmdqJ2RL0@w>ORm5)qvQK?o`8))T$=NQmCsW@|f$-btbd(TNZtO$!^*OM(!4>m>-H z2SM}_<(msR?|IKT_rCZ0-~adA^WNu?*w&hJtvTlybBy2kjWKuVt()>hr)f@OVPO#| zD#)l~Vd0>#u&{{<@W7SZ_$ndb7q+vyycAY`8{I4x)&=W(vO4$d-Qfs3ODq;%>7!39 zJlxhu=X)%?GAukivUZl{_neRp;3K$hYGvtgd_xuKiLkRXW#N(I=i~;ru4p41ERb%_ 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Retiring
Bad Speculation
Backend Bound
Frontend Bound
Core Bound
Memory Bound
Serialization
Address
Data
TLB L1
TLB L2
DL1
L2
L3
Misprediction
Memory Ordering
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Yes
Yes
Yes
Yes
Uop Retired?
Uop Retired?
Retiring
Retiring
Yes
Yes
No
No
Backend Stall?
Backend Stall?
Backend Bound
Backend Bound
Frontend Bound
Frontend Bound
No
No
Uop Issued?
Uop Issued?
No
No
Bad Speculation
Bad Speculation \ No newline at end of file From a74dc1735c4a0ad0b4700438ad9c22df934e0660 Mon Sep 17 00:00:00 2001 From: beeman Date: Wed, 9 Oct 2024 14:37:56 -0700 Subject: [PATCH 09/13] switch from png to svg for line drawings, tweak text --- body.adoc | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/body.adoc b/body.adoc index 81509e0..f194ed0 100644 --- a/body.adoc +++ b/body.adoc @@ -79,10 +79,11 @@ This group contains events and metrics related for Topdown Microarchitecture Ana TMA allows even developers with minimal microarchitecture knowledge to understand, for a given workload, where bottlenecks reside. It does so by accounting for the utilization of each pipeline "slot" in the microarchitecture. When the hardware is utilized with optimal efficiency, each slot is occupied by an instruction or micro-operation (a.k.a., uop) that will go on to execute and retire. When bottlenecks occur, due perhaps to a cache miss, branch misprediction, or any number of other microarchitectural conditions, some slots may be either unused or thrown away, which results in inefficiency and ultimately reduced performance. TMA is able to identify these wasted slots, and the stalls, clears, misses, or other events which caused them. This enables developers to make informed decisions when tuning their code. -TMA accomplishes this by defining a set of hierarchical states into which each slot falls, based on the boundary between the frontend (instruction fetch and decode) and the backend (instruction execution and retire) of the processor. Each cycle, the frontend can issue some implementation-defined number _N_ instructions/uops to the backend, hence there are _N_ issue slots to be categorized per cycle. At the top level, issue slots fall into one of states depicted in the figure below. +TMA accomplishes this by defining a set of hierarchical states into which each slot falls, based on the boundary between the frontend (instruction fetch and decode) and the backend (instruction execution and retire) of the processor. Each cycle, the frontend can issue some implementation-defined number (_N_) of instructions/uops to the backend, hence there are _N_ issue slots to be categorized per cycle. At the top level of the TMA hierarchy, issue slots fall into one of states depicted in the figure below. +[align="center"] .Topdown Level 1 -image::images/tma-l1.png[TMA Level 1] +image::images/tma-l1.svg[TMA Level 1] * Frontend Bound - The frontend did not issue a uop to the backend for execution. Example causes include stalls that result from cache or TLB misses during instruction fetch. * Backend Bound - The backend could not consume an uop from the frontend. Example causes include backpressure that results from cache or TLB misses on data (load/store) accesses, or from oversubscribed execution units. @@ -91,8 +92,9 @@ image::images/tma-l1.png[TMA Level 1] Many of the top-level states listed above include further breakdown at the 2nd and 3rd levels of the TMA hierarchy. See details in the figure below. +[align="center"] .Topdown Hierarchy -image::images/tma-full.png[TMA Hierarchy] +image::images/tma-full.svg[TMA Hierarchy] [NOTE] ==== From e8e1ebff205385b6bb6434a8c39be3103dceac33 Mon Sep 17 00:00:00 2001 From: beeman Date: Thu, 10 Oct 2024 10:48:14 -0700 Subject: [PATCH 10/13] minor text improvements --- body.adoc | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/body.adoc b/body.adoc index f194ed0..387d66b 100644 --- a/body.adoc +++ b/body.adoc @@ -77,20 +77,20 @@ include::adoc_event_tables/tlb_spec_metrics.adoc[] This group contains events and metrics related for Topdown Microarchitecture Analysis (TMA) methodology. -TMA allows even developers with minimal microarchitecture knowledge to understand, for a given workload, where bottlenecks reside. It does so by accounting for the utilization of each pipeline "slot" in the microarchitecture. When the hardware is utilized with optimal efficiency, each slot is occupied by an instruction or micro-operation (a.k.a., uop) that will go on to execute and retire. When bottlenecks occur, due perhaps to a cache miss, branch misprediction, or any number of other microarchitectural conditions, some slots may be either unused or thrown away, which results in inefficiency and ultimately reduced performance. TMA is able to identify these wasted slots, and the stalls, clears, misses, or other events which caused them. This enables developers to make informed decisions when tuning their code. +TMA allows even developers with minimal microarchitecture knowledge to understand, for a given workload, where bottlenecks reside. It does so by accounting for the utilization of each pipeline "slot" in the microarchitecture. When the hardware is utilized with optimal efficiency, each slot is occupied by an instruction or micro-operation (uop) that will go on to execute and retire. When bottlenecks occur, due perhaps to a cache miss, branch misprediction, or any number of other microarchitectural conditions, some slots may be either unused or thrown away, which results in inefficiency and reduced performance. TMA is able to identify these wasted slots, and the stalls, clears, misses, or other events that cause them. This enables developers to make informed decisions when tuning their code. -TMA accomplishes this by defining a set of hierarchical states into which each slot falls, based on the boundary between the frontend (instruction fetch and decode) and the backend (instruction execution and retire) of the processor. Each cycle, the frontend can issue some implementation-defined number (_N_) of instructions/uops to the backend, hence there are _N_ issue slots to be categorized per cycle. At the top level of the TMA hierarchy, issue slots fall into one of states depicted in the figure below. +TMA accomplishes this by defining a set of hierarchical states into which each slot is categorized. Each cycle, the frontend of the processor (responsible for instruction fetch and decode) can issue some implementation-defined number (_N_) of instructions/uops to the backend (instruction execution and retire). Hence there are _N_ issue slots to be categorized per cycle. At the top level of the TMA hierarchy, issue slots are categorized as described below. [align="center"] .Topdown Level 1 image::images/tma-l1.svg[TMA Level 1] * Frontend Bound - The frontend did not issue a uop to the backend for execution. Example causes include stalls that result from cache or TLB misses during instruction fetch. -* Backend Bound - The backend could not consume an uop from the frontend. Example causes include backpressure that results from cache or TLB misses on data (load/store) accesses, or from oversubscribed execution units. +* Backend Bound - The backend could not consume a uop from the frontend. Example causes include backpressure that results from cache or TLB misses on data (load/store) accesses, or from oversubscribed execution units. * Bad Speculation - The uop was dropped, as a result of a pipeline clear. Example clears include branch/jump mispredictions, or memory ordering clears. This category also includes pipeline clear recovery cycles, during which issue slots go unfilled. * Retiring - The uop retired. Ideally the majority of slots fall into this state. -Many of the top-level states listed above include further breakdown at the 2nd and 3rd levels of the TMA hierarchy. See details in the figure below. +Many of the top-level states listed above include further breakdown at the 2nd and 3rd levels of the TMA hierarchy, as illustrated below. [align="center"] .Topdown Hierarchy @@ -98,11 +98,13 @@ image::images/tma-full.svg[TMA Hierarchy] [NOTE] ==== -_Some imprecision within the event hierarchy is allowed and even expected. The standard L2 and L3 events are unlikely to sum precisely to the parent L1 or L2 events, respectively, as it is expected that there are additional sources of bottlenecks beyond those represented by the standard events. The exception is the Backend Bound L2 events (Core Bound and Memory Bound), which ideally should sum to the Backend Bound event total._ +_Some imprecision within the event hierarchy is allowed and even expected. The standard L2 and L3 events may not sum precisely to the parent L1 or L2 events, respectively, as it is expected that there will be some additional sources of bottlenecks beyond those represented by the standard events. The exception is the Backend Bound L2 events (Core Bound and Memory Bound), which ideally should sum to the Backend Bound event total._ _Implementations may opt to add custom L2 or L3 events, to identify additional bottlenecks specific to the microarchitecture._ ==== +The events which follow count slots for each of the states listed above, while the metrics express the slots per state value as a percentage of total slots. + include::adoc_event_tables/topdown.adoc[] include::adoc_event_tables/topdown_metrics.adoc[] From f4a0d03e0a486bd121dcc6016f0b0c0be8777626 Mon Sep 17 00:00:00 2001 From: beeman Date: Thu, 10 Oct 2024 10:49:11 -0700 Subject: [PATCH 11/13] revise TMA diagrams to better match RV events --- images/tma-full.svg | 2 +- images/tma-l1.svg | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/images/tma-full.svg b/images/tma-full.svg index 9124a5a..343d3ba 100644 --- a/images/tma-full.svg +++ b/images/tma-full.svg @@ -1,4 +1,4 @@ -
Retiring
Bad Speculation
Backend Bound
Frontend Bound
Core Bound
Memory Bound
Serialization
Address
Data
TLB L1
TLB L2
DL1
L2
L3
Misprediction
Memory Ordering
 \ No newline at end of file +
Retiring
Bad Speculation
Backend Bound
Frontend Bound
Core Bound
Memory Bound
Serialization
Address
Data
TLB L1
TLB L2
L1
L2
L3
Misprediction
Memory Ordering
EXTMEM
PGWALK
 \ No newline at end of file diff --git a/images/tma-l1.svg b/images/tma-l1.svg index 767f6e3..d7d682a 100644 --- a/images/tma-l1.svg +++ b/images/tma-l1.svg @@ -1,4 +1,4 @@ -
Yes
Yes
Yes
Yes
Uop Retired?
Uop Retired?
Retiring
Retiring
Yes
Yes
No
No
Backend Stall?
Backend Stall?
Backend Bound
Backend Bound
Frontend Bound
Frontend Bound
No
No
Uop Issued?
Uop Issued?
No
No
Bad Speculation
Bad Speculation \ No newline at end of file +
Yes
Yes
Uop Retired?
Retiring
Yes
No
Backend Stall?
Backend Bound
Frontend Bound
No
Uop Issued?
No
Bad Speculation
 \ No newline at end of file From 3a51b41461b1be06d261245dd24bb9a74cc83969 Mon Sep 17 00:00:00 2001 From: beeman Date: Thu, 10 Oct 2024 10:49:37 -0700 Subject: [PATCH 12/13] uprev docs-resources, which improves pdf appearance --- docs-resources | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs-resources b/docs-resources index 8abc934..07b9904 160000 --- a/docs-resources +++ b/docs-resources @@ -1 +1 @@ -Subproject commit 8abc93401a61e52c460888ff658518a56e37ee9c +Subproject commit 07b9904bd4de7aca03257200a0f88cb2683d9790 From 9852a3e70086b91ef8391e766e7ac8902092488b Mon Sep 17 00:00:00 2001 From: beeman Date: Tue, 15 Oct 2024 11:17:12 -0700 Subject: [PATCH 13/13] add some clarifications to top-down event section header, including links to papers with background and usage --- body.adoc | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/body.adoc b/body.adoc index 387d66b..0ff7bf9 100644 --- a/body.adoc +++ b/body.adoc @@ -73,11 +73,13 @@ include::adoc_event_tables/tlb_spec.adoc[] include::adoc_event_tables/tlb_spec_metrics.adoc[] -=== TOPDOWN +=== TOP-DOWN -This group contains events and metrics related for Topdown Microarchitecture Analysis (TMA) methodology. +This group contains events and metrics related for Top-down Microarchitecture Analysis (TMA) methodology. -TMA allows even developers with minimal microarchitecture knowledge to understand, for a given workload, where bottlenecks reside. It does so by accounting for the utilization of each pipeline "slot" in the microarchitecture. When the hardware is utilized with optimal efficiency, each slot is occupied by an instruction or micro-operation (uop) that will go on to execute and retire. When bottlenecks occur, due perhaps to a cache miss, branch misprediction, or any number of other microarchitectural conditions, some slots may be either unused or thrown away, which results in inefficiency and reduced performance. TMA is able to identify these wasted slots, and the stalls, clears, misses, or other events that cause them. This enables developers to make informed decisions when tuning their code. +TMA is an industry-standard methodology https://ieeexplore.ieee.org/document/6844459[introduced by Intel] in characterizing the performance of SPEC CPU2006 on Intel CPUs, and since used to characterize https://www.mdpi.com/2078-2489/14/10/554[HPC workloads], https://ieeexplore.ieee.org/abstract/document/9820717[GPU workloads], https://dl.acm.org/doi/10.1145/3369383[microarchitecture changes], https://ieeexplore.ieee.org/abstract/document/9579960[pre-silicon performance validation failures], and more. + +TMA allows even developers with minimal microarchitecture knowledge to understand, for a given workload, where bottlenecks reside. It does so by accounting for the utilization of each pipeline "slot" in the microarchitecture. As an example, for a 4-wide implementation, there are 4 slots to account for each cycle. When the hardware is utilized with optimal efficiency, each slot is occupied by an instruction or micro-operation (uop) that will go on to execute and retire. When bottlenecks occur, due perhaps to a cache miss, branch misprediction, or any number of other microarchitectural conditions, some slots may be either unused or thrown away, which results in inefficiency and reduced performance. TMA is able to identify these wasted slots, and the stalls, clears, misses, or other events that cause them. This enables developers to make informed decisions when tuning their code. TMA accomplishes this by defining a set of hierarchical states into which each slot is categorized. Each cycle, the frontend of the processor (responsible for instruction fetch and decode) can issue some implementation-defined number (_N_) of instructions/uops to the backend (instruction execution and retire). Hence there are _N_ issue slots to be categorized per cycle. At the top level of the TMA hierarchy, issue slots are categorized as described below. @@ -87,10 +89,10 @@ image::images/tma-l1.svg[TMA Level 1] * Frontend Bound - The frontend did not issue a uop to the backend for execution. Example causes include stalls that result from cache or TLB misses during instruction fetch. * Backend Bound - The backend could not consume a uop from the frontend. Example causes include backpressure that results from cache or TLB misses on data (load/store) accesses, or from oversubscribed execution units. -* Bad Speculation - The uop was dropped, as a result of a pipeline clear. Example clears include branch/jump mispredictions, or memory ordering clears. This category also includes pipeline clear recovery cycles, during which issue slots go unfilled. +* Bad Speculation - The uop was dropped, as a result of a pipeline clear. Example clears include branch/jump mispredictions, or memory ordering clears. This category also includes any pipeline clear recovery cycles during which issue slots go unfilled. * Retiring - The uop retired. Ideally the majority of slots fall into this state. -Many of the top-level states listed above include further breakdown at the 2nd and 3rd levels of the TMA hierarchy, as illustrated below. +Many of the top-level states listed above include further breakdown at the 2nd and 3rd levels of the TMA hierarchy, as illustrated below. [align="center"] .Topdown Hierarchy @@ -100,6 +102,8 @@ image::images/tma-full.svg[TMA Hierarchy] ==== _Some imprecision within the event hierarchy is allowed and even expected. The standard L2 and L3 events may not sum precisely to the parent L1 or L2 events, respectively, as it is expected that there will be some additional sources of bottlenecks beyond those represented by the standard events. The exception is the Backend Bound L2 events (Core Bound and Memory Bound), which ideally should sum to the Backend Bound event total._ +_Because of this possible imprecision, it is recommended that lower level TMA events are examined only when the parent event count or rate is higher than expected. This avoids spending time on misleading L2 or L3 events that may be implemented by imprecise event formulas rather than precise hardware events._ + _Implementations may opt to add custom L2 or L3 events, to identify additional bottlenecks specific to the microarchitecture._ ====