Fix MIPS IL for addi, move and negu ops (#4916)

rizinorg · Feb 20, 2025 · e742a10 · e742a10
1 parent e0a69df
commit e742a10
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Showing 3 changed files with 33 additions and 11 deletions.
diff --git a/librz/arch/isa/mips/il/common.c b/librz/arch/isa/mips/il/common.c
@@ -102,6 +102,10 @@ static RzILOpEffect *mips_il_addiu(const csh *handle, const cs_insn *insn, const
 
 static RzILOpEffect *mips_il_addu(const csh *handle, const cs_insn *insn, const ut32 gprlen) {
 	MIPS_CHECK_IF_TARGET_IS_ZERO_REG_AND_NOP();
+	if (OPCOUNT() < 3) {
+		// move
+		return mips_il_move(handle, insn, gprlen);
+	}
 
 	const char *rd = REG(0);
 	RzILOpPure *rs = MIPS_REG(1);
@@ -969,9 +973,24 @@ static RzILOpEffect *mips_il_sub(const csh *handle, const cs_insn *insn, const u
 	return SETG(rd, SUB(rs, rt));
 }
 
+static RzILOpEffect *mips_il_negu(const csh *handle, const cs_insn *insn, const ut32 gprlen) {
+	MIPS_CHECK_IF_TARGET_IS_ZERO_REG_AND_NOP();
+
+	const char *rd = REG(0);
+	RzILOpPure *zero = MIPS_ZERO();
+	RzILOpPure *rt = MIPS_REG(1);
+
+	return SETG(rd, SUB(zero, rt));
+}
+
 static RzILOpEffect *mips_il_subu(const csh *handle, const cs_insn *insn, const ut32 gprlen) {
 	MIPS_CHECK_IF_TARGET_IS_ZERO_REG_AND_NOP();
 
+	if (OPCOUNT() < 3) {
+		// negu
+		return mips_il_negu(handle, insn, gprlen);
+	}
+
 	// TODO: handle unsigness.
 	const char *rd = REG(0);
 	RzILOpPure *rs = MIPS_REG(1);

diff --git a/librz/arch/isa/mips/il/hw.c b/librz/arch/isa/mips/il/hw.c
@@ -7,16 +7,16 @@
  **/
 
 #define REG_CAUSE_EXCEPTION             "CAUSE_EXC"
-#define IL_REG_CAUSE_EXCEPTION()        VARG(REG_CAUSE_EXCEPTION)
-#define IL_CAUSE_CLEAR()                SETG(REG_CAUSE_EXCEPTION, U8(0));
-#define IL_CAUSE_INTERRUPT()            SETG(REG_CAUSE_EXCEPTION, U8(0x00))
-#define IL_CAUSE_ADDRESS_LOAD_ERROR()   SETG(REG_CAUSE_EXCEPTION, U8(0x04))
-#define IL_CAUSE_ADDRESS_STORE_ERROR()  SETG(REG_CAUSE_EXCEPTION, U8(0x05))
-#define IL_CAUSE_SYSCALL()              SETG(REG_CAUSE_EXCEPTION, U8(0x08))
-#define IL_CAUSE_BREAKPOINT()           SETG(REG_CAUSE_EXCEPTION, U8(0x09))
-#define IL_CAUSE_OVERFLOW()             SETG(REG_CAUSE_EXCEPTION, U8(0x0C))
-#define IL_CAUSE_RESERVED_INSTRUCTION() SETG(REG_CAUSE_EXCEPTION, U8(0x0A))
-#define IL_CAUSE_TRAP()                 SETG(REG_CAUSE_EXCEPTION, U8(0x0D))
+#define IL_REG_CAUSE_EXCEPTION()        NOP() // VARG(REG_CAUSE_EXCEPTION)
+#define IL_CAUSE_CLEAR()                NOP() // SETG(REG_CAUSE_EXCEPTION, U8(0));
+#define IL_CAUSE_INTERRUPT()            NOP() // SETG(REG_CAUSE_EXCEPTION, U8(0x00))
+#define IL_CAUSE_ADDRESS_LOAD_ERROR()   NOP() // SETG(REG_CAUSE_EXCEPTION, U8(0x04))
+#define IL_CAUSE_ADDRESS_STORE_ERROR()  NOP() // SETG(REG_CAUSE_EXCEPTION, U8(0x05))
+#define IL_CAUSE_SYSCALL()              NOP() // SETG(REG_CAUSE_EXCEPTION, U8(0x08))
+#define IL_CAUSE_BREAKPOINT()           NOP() // SETG(REG_CAUSE_EXCEPTION, U8(0x09))
+#define IL_CAUSE_OVERFLOW()             NOP() // SETG(REG_CAUSE_EXCEPTION, U8(0x0C))
+#define IL_CAUSE_RESERVED_INSTRUCTION() NOP() // SETG(REG_CAUSE_EXCEPTION, U8(0x0A))
+#define IL_CAUSE_TRAP()                 NOP() // SETG(REG_CAUSE_EXCEPTION, U8(0x0D))
 
 static RzILOpEffect *mips_il_break(const csh *handle, const cs_insn *insn, const ut32 gprlen) {
 	// HW breakpoint

diff --git a/test/db/asm/mips_mips2_32 b/test/db/asm/mips_mips2_32
@@ -1,2 +1,5 @@
 d "lwc3 0, 0(zero)" 000000cc
-d "swc3 0, 0(zero)" 000000ec
+d "swc3 0, 0(zero)" 000000ec
+d "addi t8, t8, 0x700" 00071823 4 (branch (== (>> (& (cast 32 (msb (+ (var t8) (bv 32 0x700))) (+ (var t8) (bv 32 0x700))) (bv 32 0x80000000)) (bv 32 0x1f) false) (>> (& (cast 32 (msb (+ (var t8) (bv 32 0x700))) (+ (var t8) (bv 32 0x700))) (bv 32 0x40000000)) (bv 32 0x1e) false)) nop (set t8 (cast 32 (msb (+ (var t8) (bv 32 0x700))) (+ (var t8) (bv 32 0x700)))))
+d "move ra, zero" 21f80000 4 (set ra (bv 32 0x0))
+d "negu v1, a3" 23180700 4 (set v1 (- (bv 32 0x0) (var a3)))