-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathmp3.qsf
144 lines (141 loc) · 9.42 KB
/
mp3.qsf
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition
# Date created = 18:29:08 October 22, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# mp3_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Stratix IV"
set_global_assignment -name DEVICE AUTO
set_global_assignment -name TOP_LEVEL_ENTITY mp3
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:29:08 OCTOBER 22, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH mp3_tb -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME mp3_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id mp3_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME mp3_tb -section_id mp3_tb
set_global_assignment -name EDA_TEST_BENCH_NAME random_icache_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id random_icache_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME random_icache_tb -section_id random_icache_tb
set_global_assignment -name EDA_TEST_BENCH_NAME random_dcache_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id random_dcache_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME random_dcache_tb -section_id random_dcache_tb
set_global_assignment -name EDA_TEST_BENCH_NAME mult_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id mult_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME mult_tb -section_id mult_tb
set_global_assignment -name EDA_TEST_BENCH_NAME div_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id div_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME div_tb -section_id div_tb
set_global_assignment -name SYSTEMVERILOG_FILE div_types.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/predictor_table.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/global_history_reg.sv
set_global_assignment -name EDA_TEST_BENCH_NAME pseudo_lru_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id pseudo_lru_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME pseudo_lru_tb -section_id pseudo_lru_tb
set_global_assignment -name SDC_FILE mp3.out.sdc
set_global_assignment -name SYSTEMVERILOG_FILE hdl/arbiter_dp.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/arbiter_control.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/arbiter.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/cache/dcache.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/cache/dcache_dp.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/cache/dcache_control.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/cache/line_adapter.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/cache/data_reg.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/cache/data_array.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/cache/cache_mux_types.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/cache/cache_cw_reg.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/cache/array.sv
set_global_assignment -name SYSTEMVERILOG_FILE rv32i_types.sv
set_global_assignment -name SYSTEMVERILOG_FILE rv32i_mux_types.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/register.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/regfile.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/pc_reg.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/mp3.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/mem_data_out.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/datapath.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/cw_register.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/control.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/cmp.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/alu.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/cache/icache_dp.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/cache/icache_control.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/cache/icache.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/forward.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/cache/l2_cache.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/cache/l2_cache_datapath.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/cache/l2_cache_control.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/cache/l2_ret_reg.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/cache/l2_go_reg.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/btb.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/btb_array.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/selector.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/multiplier.sv
set_global_assignment -name SYSTEMVERILOG_FILE mult_types.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/divider.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdl/divider_control.sv
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name EDA_TEST_BENCH_FILE hvl/mp3/magic_dual_port.sv -section_id mp3_tb
set_global_assignment -name EDA_TEST_BENCH_FILE hvl/mp3/mp3_tb.sv -section_id mp3_tb
set_global_assignment -name EDA_TEST_BENCH_FILE hvl/mp3/tb_itf.sv -section_id mp3_tb
set_global_assignment -name EDA_TEST_BENCH_FILE hvl/mp3/physical_memory.sv -section_id mp3_tb
set_global_assignment -name EDA_TEST_BENCH_FILE hvl/mp3/pmem_random_cache_tb.sv -section_id random_icache_tb
set_global_assignment -name EDA_TEST_BENCH_FILE hvl/mp3/tb_itf.sv -section_id random_icache_tb
set_global_assignment -name EDA_TEST_BENCH_FILE hvl/mp3/random_icache_tb.sv -section_id random_icache_tb
set_global_assignment -name EDA_TEST_BENCH_FILE hdl/cache/icache.sv -section_id random_icache_tb
set_global_assignment -name EDA_TEST_BENCH_FILE hvl/mp3/pmem_random_cache_tb.sv -section_id random_dcache_tb
set_global_assignment -name EDA_TEST_BENCH_FILE hvl/mp3/random_dcache_tb.sv -section_id random_dcache_tb
set_global_assignment -name EDA_TEST_BENCH_FILE hvl/mp3/tb_itf.sv -section_id random_dcache_tb
set_global_assignment -name EDA_TEST_BENCH_FILE hdl/cache/dcache.sv -section_id random_dcache_tb
set_global_assignment -name EDA_TEST_BENCH_FILE hvl/mp3/tb_itf.sv -section_id mult_tb
set_global_assignment -name EDA_TEST_BENCH_FILE hvl/mp3/mult_tb.sv -section_id mult_tb
set_global_assignment -name EDA_TEST_BENCH_FILE hvl/mp3/div_tb.sv -section_id div_tb
set_global_assignment -name EDA_TEST_BENCH_FILE hvl/mp3/tb_itf.sv -section_id div_tb
set_global_assignment -name EDA_TEST_BENCH_FILE hvl/mp3/pseudo_lru_tb.sv -section_id pseudo_lru_tb
set_global_assignment -name POWER_USE_INPUT_FILES ON
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY ON
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION ON
set_global_assignment -name POWER_INPUT_FILE_NAME simulation/modelsim/comp3power.vcd -section_id comp3power.vcd
set_instance_assignment -name POWER_READ_INPUT_FILE comp3power.vcd -to mp3
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top