DE0_NANO_SOC_LT24_NIOS.map.smsg

Info (10281): Verilog HDL Declaration information at lt24_qsys_mm_interconnect_0_router_005.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at lt24_qsys_mm_interconnect_0_router_005.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at lt24_qsys_mm_interconnect_0_router_002.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at lt24_qsys_mm_interconnect_0_router_002.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at lt24_qsys_mm_interconnect_0_router_001.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at lt24_qsys_mm_interconnect_0_router_001.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at lt24_qsys_mm_interconnect_0_router.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at lt24_qsys_mm_interconnect_0_router.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope