Only one last-level cache allowed

[apoorvaaaa5]

Hey, I had this doubt about why last level cache is required, can i not simulate the cores with private l1-d and l1-i cache itself?? what is the reason behind l3 cache requirement all the time in init.cpp at around lines 508??
is there a way and could you suggest what i can change in init.cpp so that it accepts only l1 cache not necessary to have last level cache to simulate??