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Nitrogen6_SoloX board serial output doesn't work when sel4test -DRELEASE=ON is used #55

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kent-mcleod opened this issue Oct 25, 2021 · 4 comments

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@kent-mcleod
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When running sel4test on the Nitrogen6_SoloX board with release settings configured, seL4_DebugPutchar() is disabled and the platform serial driver from libplatsupport will be used instead. The error occurs when re-configuring the divider settings for the serial baud (if the baud reconfiguration is disabled such that the device is assumed to be initialized already then the serial works).

U-Boot 2018.07-36618-g616d48151d (Oct 08 2020 - 10:15:22 -0700), Build: jenkins-uboot_v2018.07-240

CPU:   Freescale i.MX6SX rev1.3 at 792 MHz
Reset cause: POR
Board: nitrogen6sx
I2C:   ready
DRAM:  1 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from SPI Flash...
SF: Detected gd25q16c with page size 256 Bytes, erase size 4 KiB, total 2 MiB
*** Warning - bad CRC, using default environment

Failed (-5)
Display: lcd:1280x720M@60 (1280x720)
In:    serial
Out:   serial
Err:   serial
Net:   AR8035 at 4
AR8035 at 5
FEC0 [PRIME], FEC1, usb_ether
Hit any key to stop autoboot:  0 
=> dhcp
BOOTP broadcast 1
DHCP client bound to address 10.0.121.29 (4 ms)
*** Warning: no boot file name; using '0A00791D.img'
Using FEC0 device
TFTP from server 0.0.0.0; our IP address is 10.0.121.29; sending through gateway 10.0.121.100
Filename '0A00791D.img'.
Load address: 0x82000000
Loading: *
TFTP error: 'File not found' (1)
Not retrying...
=> setenv serverip 10.0.121.19
=> tftp sel4test-driver-image-arm-imx6
Using FEC0 device
TFTP from server 10.0.121.19; our IP address is 10.0.121.29
Filename 'sel4test-driver-image-arm-imx6'.
Load address: 0x82000000
Loading: #################################################################
	 ########################################################
	 7 MiB/s
done
Bytes transferred = 1763056 (1ae6f0 hex)
=> bootm
## Booting kernel from Legacy Image at 82000000 ...
   Image Name:   
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    1762992 Bytes = 1.7 MiB
   Load Address: 80657000
   Entry Point:  80657000
   Verifying Checksum ... OK
   Loading Kernel Image ... OK

Starting kernel ...


ELF-loader started on CPU: ARM Ltd. Cortex-A9 r2p10
  paddr=[80657000..808056af]
No DTB passed in from boot loader.
Looking for DTB in CPIO archive...found at 8069d410.
Loaded DTB from 8069d410.
   paddr=[80030000..80033fff]
ELF-loading image 'kernel' to 80000000
  paddr=[80000000..8002ffff]
  vaddr=[e0000000..e002ffff]
  virt_entry=e0000000
ELF-loading image 'sel4test-driver' to 80034000
  paddr=[80034000..8025afff]
  vaddr=[10000..236fff]
  virt_entry=17ad4
Enabling MMU and paging
Jumping to kernel-image entry point...

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@kent-mcleod
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Running this currently requires the following patch to seL4_tools:

project tools/seL4/
diff --git a/cmake-tool/helpers/application_settings.cmake b/cmake-tool/helpers/application>
index 4997687..8786105 100644
--- a/cmake-tool/helpers/application_settings.cmake
+++ b/cmake-tool/helpers/application_settings.cmake
@@ -11,7 +11,7 @@ include_guard(GLOBAL)
 function(ApplyData61ElfLoaderSettings kernel_platform kernel_sel4_arch)
     set(binary_list "tx1;hikey;odroidc2;odroidc4;imx8mq-evk;zynqmp;imx8mm-evk;hifive;tqma8>
     set(efi_list "tk1;rockpro64")
-    set(uimage_list "tx2;am335x")
+    set(uimage_list "tx2;am335x;imx6")
     if(
         ${kernel_platform} IN_LIST efi_list
         OR (${kernel_platform} STREQUAL "hikey" AND ${kernel_sel4_arch} STREQUAL "aarch64")

@kent-mcleod
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The baud rate calculation is done based off of the value of UART_REF_CLK which for imx6 is defined as 40089600. This seems to be in relation to half the uart clock rate on the sabre (half because the UARTx_UFCR(RFDIV) field is set to divide the input clock by 2 first):

ERTOS MX6Q SABRELITE U-Boot > clk
cpu clock: 792MHz
mx6q pll1: 792MHz
mx6q pll2: 528MHz
mx6q pll3: 480MHz
mx6q pll8: 50MHz
ipg clock     : 66000000Hz
ipg per clock : 66000000Hz
uart clock    : 80000000Hz
cspi clock    : 60000000Hz
ahb clock     : 132000000Hz
axi clock   : 264000000Hz
emi_slow clock: 132000000Hz
ddr clock     : 528000000Hz
usdhc1 clock  : 198000000Hz
usdhc2 clock  : 198000000Hz
usdhc3 clock  : 198000000Hz
usdhc4 clock  : 198000000Hz
nfc clock     : 24000000Hz

The clocks for the nitrogen6sx:

=> clocks 
PLL_SYS         792 MHz
PLL_BUS         528 MHz
PLL_OTG         480 MHz
PLL_NET         125 MHz

ARM          792000 kHz
IPG           66000 kHz
UART          24000 kHz
CSPI          60000 kHz
AHB          132000 kHz
AXI          198000 kHz
DDR          396000 kHz
USDHC1       198000 kHz
USDHC2       198000 kHz
USDHC3       198000 kHz
USDHC4       198000 kHz
EMI SLOW      99000 kHz
IPG PERCLK    66000 kHz

Because the UART rate is only 24MHz on the Nitrogen6_SoloX, changing the constant to 12000000 (it needs to be half of the input clk frequency) makes the serial work.
(The difference between the rates because they use a different clock source, the sabre uses the pll3 divided by 6 and the solox uses the external oscillator.)

@kent-mcleod
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Fix: seL4/util_libs#108

@axel-h
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axel-h commented Mar 8, 2022

@kent-mcleod : Can we close this since the fix is merged?

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