From b3eefd78c293644f3ad038954c083cffdfd44c18 Mon Sep 17 00:00:00 2001 From: sibradzic <5964548+sibradzic@users.noreply.github.com> Date: Sun, 15 Aug 2021 19:09:32 +0900 Subject: [PATCH] v0.1.2 Regenerate all atom_gen structures against latest kernel sources (36a21d517 5.14-rc5 Sun Aug 8 13:49:31 2021 -0700) Add support for RX6600XT & RX6600M. Note that the decoded values in the last ~10% of the PP table (Mostly just I2C & GPIO stuff) might be incorrect, so use with caution. --- setup.py | 2 +- src/upp/atom_gen/README.md | 21 +++++--- src/upp/atom_gen/atom.py | 8 ++- src/upp/atom_gen/atombios.py | 48 ++++++++--------- src/upp/atom_gen/smu_v11_0_7_navi20.py | 58 ++++++++++----------- src/upp/atom_gen/smu_v11_0_navi10.py | 20 +++---- src/upp/atom_gen/vega20_pptable.py | 66 ++++++++++++------------ src/upp/decode.py | 25 +++++---- test/AMD.RX6900.16384.201104.rom.rawdump | 2 +- 9 files changed, 132 insertions(+), 118 deletions(-) diff --git a/setup.py b/setup.py index 2ced175..fc40878 100644 --- a/setup.py +++ b/setup.py @@ -5,7 +5,7 @@ setuptools.setup( name='upp', - version='0.1.1', + version='0.1.2', author='Samir Ibradžić', description='Uplift Power Play', long_description=long_description, diff --git a/src/upp/atom_gen/README.md b/src/upp/atom_gen/README.md index ff44a55..5648f61 100644 --- a/src/upp/atom_gen/README.md +++ b/src/upp/atom_gen/README.md @@ -10,7 +10,7 @@ git clone --depth=1 git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git -Generated against 324c92e5e (Wed Jun 2 08:53:37 2021 -1000) +Generated against 36a21d517 (5.14-rc5) (Sun Aug 8 13:49:31 2021 -0700) ## atom.py @@ -30,12 +30,6 @@ Generated against 324c92e5e (Wed Jun 2 08:53:37 2021 -1000) " \ linux/drivers/gpu/drm/amd/include/atombios.h > atombios.py - clang2py -k 's' --clang-args="\ - --include stdint.h \ - --include linux/drivers/gpu/drm/amd/include/atom-types.h \ - " \ - linux/drivers/gpu/drm/amd/include/atombios.h > atombios.py - ## pptable_v1_0.py (Polaris/Tonga) @@ -80,7 +74,16 @@ Generated against 324c92e5e (Wed Jun 2 08:53:37 2021 -1000) linux/drivers/gpu/drm/amd/pm/inc/smu_v11_0_pptable.h > smu_v11_0_navi10.py -## smu_v11_0_navi20.py (Navi21/22) +## smu_v11_0_navi20.py (Navi21/22/23) + +### An ugly workadound for Navi 23 + +Something is totally weird with Navi 23 (RX6600) PP table, data at the end of +the table seems to be totally messed up. Since VBIOSes of various RX6600 card +manufacturers contains very similar "garbage" there, it might be possible that +PP table definition at smu11_driver_if_sienna_cichlid.h is wrong? + + sed -i 's| int8_t Mem1Offset;| uint8_t Mem1Offset;|' linux/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h clang2py -k 'mst' \ --clang-args="--include stdint.h \ @@ -89,3 +92,5 @@ Generated against 324c92e5e (Wed Jun 2 08:53:37 2021 -1000) --include linux/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h " \ linux/drivers/gpu/drm/amd/pm/inc/smu_v11_0_7_pptable.h > smu_v11_0_7_navi20.py + pushd linux && git checkout drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h && popd + diff --git a/src/upp/atom_gen/atom.py b/src/upp/atom_gen/atom.py index be8ef1a..ac54215 100644 --- a/src/upp/atom_gen/atom.py +++ b/src/upp/atom_gen/atom.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# TARGET arch is: ['-Ilinux/include', '-Ilinux/drivers/gpu/drm/amd/include'] +# TARGET arch is: ['', '-Ilinux/include', '-Ilinux/drivers/gpu/drm/amd/include'] # WORD_SIZE is: 8 # POINTER_SIZE is: 8 # LONGDOUBLE_SIZE is: 16 @@ -80,6 +80,9 @@ ATOM_IO_PCI = 1 # macro ATOM_IO_SYSIO = 2 # macro ATOM_IO_IIO = 0x80 # macro +STRLEN_NORMAL = 32 # macro +STRLEN_LONG = 64 # macro +STRLEN_VERYLONG = 254 # macro __all__ = \ ['ATOM_ARG_FB', 'ATOM_ARG_ID', 'ATOM_ARG_IMM', 'ATOM_ARG_MC', 'ATOM_ARG_PLL', 'ATOM_ARG_PS', 'ATOM_ARG_REG', 'ATOM_ARG_WS', @@ -103,4 +106,5 @@ 'ATOM_SRC_WORD16', 'ATOM_SRC_WORD8', 'ATOM_WS_AND_MASK', 'ATOM_WS_ATTRIBUTES', 'ATOM_WS_DATAPTR', 'ATOM_WS_FB_WINDOW', 'ATOM_WS_OR_MASK', 'ATOM_WS_QUOTIENT', 'ATOM_WS_REGPTR', - 'ATOM_WS_REMAINDER', 'ATOM_WS_SHIFT'] + 'ATOM_WS_REMAINDER', 'ATOM_WS_SHIFT', 'STRLEN_LONG', + 'STRLEN_NORMAL', 'STRLEN_VERYLONG'] diff --git a/src/upp/atom_gen/atombios.py b/src/upp/atom_gen/atombios.py index 0ec01b1..66e7ed5 100644 --- a/src/upp/atom_gen/atombios.py +++ b/src/upp/atom_gen/atombios.py @@ -353,8 +353,8 @@ class struct__COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3(Structure): class union__COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3_0(Union): pass -ATOM_S_MPLL_FB_DIVIDER = struct__ATOM_S_MPLL_FB_DIVIDER ATOM_COMPUTE_CLOCK_FREQ = struct__ATOM_COMPUTE_CLOCK_FREQ +ATOM_S_MPLL_FB_DIVIDER = struct__ATOM_S_MPLL_FB_DIVIDER union__COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3_0._pack_ = 1 # source:False union__COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3_0._fields_ = [ ('ulClock', ATOM_COMPUTE_CLOCK_FREQ), @@ -383,6 +383,15 @@ class struct__COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4(Structure): class struct__COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5(Structure): pass +class union__COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5_1(Union): + pass + +union__COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5_1._pack_ = 1 # source:False +union__COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5_1._fields_ = [ + ('ucCntlFlag', ctypes.c_ubyte), + ('ucInputFlag', ctypes.c_ubyte), +] + class union__COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5_0(Union): pass @@ -393,15 +402,6 @@ class union__COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5_0(Union): ('ulFbDiv', ATOM_S_MPLL_FB_DIVIDER), ] -class union__COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5_1(Union): - pass - -union__COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5_1._pack_ = 1 # source:False -union__COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5_1._fields_ = [ - ('ucCntlFlag', ctypes.c_ubyte), - ('ucInputFlag', ctypes.c_ubyte), -] - struct__COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5._pack_ = 1 # source:False struct__COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5._fields_ = [ ('_COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5_0', union__COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5_0), @@ -1672,8 +1672,8 @@ class struct__ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3(Structure): class struct__SET_PIXEL_CLOCK_PS_ALLOCATION(Structure): pass -ENABLE_SPREAD_SPECTRUM_ON_PPLL = struct__ENABLE_SPREAD_SPECTRUM_ON_PPLL PIXEL_CLOCK_PARAMETERS = struct__PIXEL_CLOCK_PARAMETERS +ENABLE_SPREAD_SPECTRUM_ON_PPLL = struct__ENABLE_SPREAD_SPECTRUM_ON_PPLL struct__SET_PIXEL_CLOCK_PS_ALLOCATION._pack_ = 1 # source:False struct__SET_PIXEL_CLOCK_PS_ALLOCATION._fields_ = [ ('sPCLKInput', PIXEL_CLOCK_PARAMETERS), @@ -3029,8 +3029,8 @@ class struct__EXT_DISPLAY_PATH(Structure): class union__EXT_DISPLAY_PATH_0(Union): pass -ATOM_DP_CONN_CHANNEL_MAPPING = struct__ATOM_DP_CONN_CHANNEL_MAPPING ATOM_DVI_CONN_CHANNEL_MAPPING = struct__ATOM_DVI_CONN_CHANNEL_MAPPING +ATOM_DP_CONN_CHANNEL_MAPPING = struct__ATOM_DP_CONN_CHANNEL_MAPPING union__EXT_DISPLAY_PATH_0._pack_ = 1 # source:False union__EXT_DISPLAY_PATH_0._fields_ = [ ('ucChannelMapping', ctypes.c_ubyte), @@ -3635,8 +3635,8 @@ class union__ATOM_VOLTAGE_OBJECT_V3(Union): ATOM_I2C_VOLTAGE_OBJECT_V3 = struct__ATOM_I2C_VOLTAGE_OBJECT_V3 ATOM_EVV_VOLTAGE_OBJECT_V3 = struct__ATOM_EVV_VOLTAGE_OBJECT_V3 ATOM_SVID2_VOLTAGE_OBJECT_V3 = struct__ATOM_SVID2_VOLTAGE_OBJECT_V3 -ATOM_GPIO_VOLTAGE_OBJECT_V3 = struct__ATOM_GPIO_VOLTAGE_OBJECT_V3 ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 = struct__ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 +ATOM_GPIO_VOLTAGE_OBJECT_V3 = struct__ATOM_GPIO_VOLTAGE_OBJECT_V3 union__ATOM_VOLTAGE_OBJECT_V3._pack_ = 1 # source:False union__ATOM_VOLTAGE_OBJECT_V3._fields_ = [ ('asGpioVoltageObj', ATOM_GPIO_VOLTAGE_OBJECT_V3), @@ -4845,8 +4845,8 @@ class struct__ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4(Structure): class struct__ENABLE_GRAPH_SURFACE_PS_ALLOCATION(Structure): pass -ENABLE_GRAPH_SURFACE_PARAMETERS = struct__ENABLE_GRAPH_SURFACE_PARAMETERS ENABLE_YUV_PARAMETERS = struct__ENABLE_YUV_PARAMETERS +ENABLE_GRAPH_SURFACE_PARAMETERS = struct__ENABLE_GRAPH_SURFACE_PARAMETERS struct__ENABLE_GRAPH_SURFACE_PS_ALLOCATION._pack_ = 1 # source:False struct__ENABLE_GRAPH_SURFACE_PS_ALLOCATION._fields_ = [ ('sSetSurface', ENABLE_GRAPH_SURFACE_PARAMETERS), @@ -5178,6 +5178,15 @@ class struct__ATOM_VRAM_MODULE_V2(Structure): class struct__ATOM_MEMORY_TIMING_FORMAT(Structure): pass +class union__ATOM_MEMORY_TIMING_FORMAT_0(Union): + pass + +union__ATOM_MEMORY_TIMING_FORMAT_0._pack_ = 1 # source:False +union__ATOM_MEMORY_TIMING_FORMAT_0._fields_ = [ + ('usMRS', ctypes.c_uint16), + ('usDDR3_MR0', ctypes.c_uint16), +] + class union__ATOM_MEMORY_TIMING_FORMAT_2(Union): pass @@ -5205,15 +5214,6 @@ class union__ATOM_MEMORY_TIMING_FORMAT_1(Union): ('usDDR3_MR1', ctypes.c_uint16), ] -class union__ATOM_MEMORY_TIMING_FORMAT_0(Union): - pass - -union__ATOM_MEMORY_TIMING_FORMAT_0._pack_ = 1 # source:False -union__ATOM_MEMORY_TIMING_FORMAT_0._fields_ = [ - ('usMRS', ctypes.c_uint16), - ('usDDR3_MR0', ctypes.c_uint16), -] - struct__ATOM_MEMORY_TIMING_FORMAT._pack_ = 1 # source:False struct__ATOM_MEMORY_TIMING_FORMAT._fields_ = [ ('ulClkRange', ctypes.c_uint32), @@ -6419,8 +6419,8 @@ class struct__DVO_ENCODER_CONTROL_PARAMETERS(Structure): class union__ATOM_ENCODER_ATTRIBUTE(Union): pass -ATOM_ENCODER_DIGITAL_ATTRIBUTE = struct__ATOM_ENCODER_DIGITAL_ATTRIBUTE ATOM_ENCODER_ANALOG_ATTRIBUTE = struct__ATOM_ENCODER_ANALOG_ATTRIBUTE +ATOM_ENCODER_DIGITAL_ATTRIBUTE = struct__ATOM_ENCODER_DIGITAL_ATTRIBUTE union__ATOM_ENCODER_ATTRIBUTE._pack_ = 1 # source:False union__ATOM_ENCODER_ATTRIBUTE._fields_ = [ ('sAlgAttrib', ATOM_ENCODER_ANALOG_ATTRIBUTE), diff --git a/src/upp/atom_gen/smu_v11_0_7_navi20.py b/src/upp/atom_gen/smu_v11_0_7_navi20.py index ad1b04e..afece93 100644 --- a/src/upp/atom_gen/smu_v11_0_7_navi20.py +++ b/src/upp/atom_gen/smu_v11_0_7_navi20.py @@ -164,16 +164,6 @@ class struct_smu_11_0_7_power_saving_clock_table(Structure): class struct_smu_11_0_7_powerplay_table(Structure): pass -class struct_atom_common_table_header(Structure): - pass - -struct_atom_common_table_header._pack_ = 1 # source:False -struct_atom_common_table_header._fields_ = [ - ('structuresize', ctypes.c_uint16), - ('format_revision', ctypes.c_ubyte), - ('content_revision', ctypes.c_ubyte), -] - class struct_c__SA_PPTable_t(Structure): pass @@ -195,23 +185,23 @@ class struct_c__SA_I2cControllerConfig_t(Structure): class struct_c__SA_DpmDescriptor_t(Structure): pass -class struct_c__SA_QuadraticInt_t(Structure): +class struct_c__SA_LinearInt_t(Structure): pass -struct_c__SA_QuadraticInt_t._pack_ = 1 # source:False -struct_c__SA_QuadraticInt_t._fields_ = [ - ('a', ctypes.c_uint32), +struct_c__SA_LinearInt_t._pack_ = 1 # source:False +struct_c__SA_LinearInt_t._fields_ = [ + ('m', ctypes.c_uint32), ('b', ctypes.c_uint32), - ('c', ctypes.c_uint32), ] -class struct_c__SA_LinearInt_t(Structure): +class struct_c__SA_QuadraticInt_t(Structure): pass -struct_c__SA_LinearInt_t._pack_ = 1 # source:False -struct_c__SA_LinearInt_t._fields_ = [ - ('m', ctypes.c_uint32), +struct_c__SA_QuadraticInt_t._pack_ = 1 # source:False +struct_c__SA_QuadraticInt_t._fields_ = [ + ('a', ctypes.c_uint32), ('b', ctypes.c_uint32), + ('c', ctypes.c_uint32), ] struct_c__SA_DpmDescriptor_t._pack_ = 1 # source:False @@ -235,15 +225,6 @@ class struct_c__SA_PiecewiseLinearDroopInt_t(Structure): ('Vdroop', ctypes.c_uint32 * 5), ] -class struct_c__SA_UclkDpmChangeRange_t(Structure): - pass - -struct_c__SA_UclkDpmChangeRange_t._pack_ = 1 # source:False -struct_c__SA_UclkDpmChangeRange_t._fields_ = [ - ('Fmin', ctypes.c_uint16), - ('Fmax', ctypes.c_uint16), -] - class struct_c__SA_DroopInt_t(Structure): pass @@ -254,6 +235,15 @@ class struct_c__SA_DroopInt_t(Structure): ('c', ctypes.c_uint32), ] +class struct_c__SA_UclkDpmChangeRange_t(Structure): + pass + +struct_c__SA_UclkDpmChangeRange_t._pack_ = 1 # source:False +struct_c__SA_UclkDpmChangeRange_t._fields_ = [ + ('Fmin', ctypes.c_uint16), + ('Fmax', ctypes.c_uint16), +] + struct_c__SA_PPTable_t._pack_ = 1 # source:False struct_c__SA_PPTable_t._fields_ = [ ('Version', ctypes.c_uint32), @@ -430,7 +420,7 @@ class struct_c__SA_DroopInt_t(Structure): ('Mem0Offset', ctypes.c_byte), ('Padding_TelemetryMem0', ctypes.c_ubyte), ('Mem1MaxCurrent', ctypes.c_uint16), - ('Mem1Offset', ctypes.c_byte), + ('Mem1Offset', ctypes.c_ubyte), ('Padding_TelemetryMem1', ctypes.c_ubyte), ('MvddRatio', ctypes.c_uint32), ('AcDcGpio', ctypes.c_ubyte), @@ -476,6 +466,16 @@ class struct_c__SA_DroopInt_t(Structure): ('MmHubPadding', ctypes.c_uint32 * 8), ] +class struct_atom_common_table_header(Structure): + pass + +struct_atom_common_table_header._pack_ = 1 # source:False +struct_atom_common_table_header._fields_ = [ + ('structuresize', ctypes.c_uint16), + ('format_revision', ctypes.c_ubyte), + ('content_revision', ctypes.c_ubyte), +] + struct_smu_11_0_7_powerplay_table._pack_ = 1 # source:True struct_smu_11_0_7_powerplay_table._fields_ = [ ('header', struct_atom_common_table_header), diff --git a/src/upp/atom_gen/smu_v11_0_navi10.py b/src/upp/atom_gen/smu_v11_0_navi10.py index daacae8..c97c7b3 100644 --- a/src/upp/atom_gen/smu_v11_0_navi10.py +++ b/src/upp/atom_gen/smu_v11_0_navi10.py @@ -161,6 +161,16 @@ class struct_smu_11_0_power_saving_clock_table(Structure): class struct_smu_11_0_powerplay_table(Structure): pass +class struct_atom_common_table_header(Structure): + pass + +struct_atom_common_table_header._pack_ = 1 # source:False +struct_atom_common_table_header._fields_ = [ + ('structuresize', ctypes.c_uint16), + ('format_revision', ctypes.c_ubyte), + ('content_revision', ctypes.c_ubyte), +] + class struct_c__SA_PPTable_t(Structure): pass @@ -424,16 +434,6 @@ class struct_c__SA_I2cControllerConfig_t(Structure): ('MmHubPadding', ctypes.c_uint32 * 8), ] -class struct_atom_common_table_header(Structure): - pass - -struct_atom_common_table_header._pack_ = 1 # source:False -struct_atom_common_table_header._fields_ = [ - ('structuresize', ctypes.c_uint16), - ('format_revision', ctypes.c_ubyte), - ('content_revision', ctypes.c_ubyte), -] - struct_smu_11_0_powerplay_table._pack_ = 1 # source:True struct_smu_11_0_powerplay_table._fields_ = [ ('header', struct_atom_common_table_header), diff --git a/src/upp/atom_gen/vega20_pptable.py b/src/upp/atom_gen/vega20_pptable.py index 98e1081..9b79970 100644 --- a/src/upp/atom_gen/vega20_pptable.py +++ b/src/upp/atom_gen/vega20_pptable.py @@ -160,33 +160,22 @@ class struct__ATOM_VEGA20_POWER_SAVING_CLOCK_RECORD(Structure): class struct__ATOM_VEGA20_POWERPLAYTABLE(Structure): pass -class struct_atom_common_table_header(Structure): - pass - -struct_atom_common_table_header._pack_ = 1 # source:False -struct_atom_common_table_header._fields_ = [ - ('structuresize', ctypes.c_uint16), - ('format_revision', ctypes.c_ubyte), - ('content_revision', ctypes.c_ubyte), -] - class struct_c__SA_PPTable_t(Structure): pass -class struct_c__SA_I2cControllerConfig_t(Structure): +class struct_c__SA_DroopInt_t(Structure): pass -struct_c__SA_I2cControllerConfig_t._pack_ = 1 # source:False -struct_c__SA_I2cControllerConfig_t._fields_ = [ - ('Enabled', ctypes.c_uint32), - ('SlaveAddress', ctypes.c_uint32), - ('ControllerPort', ctypes.c_uint32), - ('ControllerName', ctypes.c_uint32), - ('ThermalThrottler', ctypes.c_uint32), - ('I2cProtocol', ctypes.c_uint32), - ('I2cSpeed', ctypes.c_uint32), +struct_c__SA_DroopInt_t._pack_ = 1 # source:False +struct_c__SA_DroopInt_t._fields_ = [ + ('a', ctypes.c_uint32), + ('b', ctypes.c_uint32), + ('c', ctypes.c_uint32), ] +class struct_c__SA_DpmDescriptor_t(Structure): + pass + class struct_c__SA_LinearInt_t(Structure): pass @@ -206,19 +195,6 @@ class struct_c__SA_QuadraticInt_t(Structure): ('c', ctypes.c_uint32), ] -class struct_c__SA_DroopInt_t(Structure): - pass - -struct_c__SA_DroopInt_t._pack_ = 1 # source:False -struct_c__SA_DroopInt_t._fields_ = [ - ('a', ctypes.c_uint32), - ('b', ctypes.c_uint32), - ('c', ctypes.c_uint32), -] - -class struct_c__SA_DpmDescriptor_t(Structure): - pass - struct_c__SA_DpmDescriptor_t._pack_ = 1 # source:False struct_c__SA_DpmDescriptor_t._fields_ = [ ('VoltageMode', ctypes.c_ubyte), @@ -229,6 +205,20 @@ class struct_c__SA_DpmDescriptor_t(Structure): ('SsCurve', struct_c__SA_QuadraticInt_t), ] +class struct_c__SA_I2cControllerConfig_t(Structure): + pass + +struct_c__SA_I2cControllerConfig_t._pack_ = 1 # source:False +struct_c__SA_I2cControllerConfig_t._fields_ = [ + ('Enabled', ctypes.c_uint32), + ('SlaveAddress', ctypes.c_uint32), + ('ControllerPort', ctypes.c_uint32), + ('ControllerName', ctypes.c_uint32), + ('ThermalThrottler', ctypes.c_uint32), + ('I2cProtocol', ctypes.c_uint32), + ('I2cSpeed', ctypes.c_uint32), +] + struct_c__SA_PPTable_t._pack_ = 1 # source:False struct_c__SA_PPTable_t._fields_ = [ ('Version', ctypes.c_uint32), @@ -413,6 +403,16 @@ class struct_c__SA_DpmDescriptor_t(Structure): ('MmHubPadding', ctypes.c_uint32 * 8), ] +class struct_atom_common_table_header(Structure): + pass + +struct_atom_common_table_header._pack_ = 1 # source:False +struct_atom_common_table_header._fields_ = [ + ('structuresize', ctypes.c_uint16), + ('format_revision', ctypes.c_ubyte), + ('content_revision', ctypes.c_ubyte), +] + struct__ATOM_VEGA20_POWERPLAYTABLE._pack_ = 1 # source:False struct__ATOM_VEGA20_POWERPLAYTABLE._fields_ = [ ('sHeader', struct_atom_common_table_header), diff --git a/src/upp/decode.py b/src/upp/decode.py index 0b9b174..02ae7b8 100644 --- a/src/upp/decode.py +++ b/src/upp/decode.py @@ -605,30 +605,35 @@ def select_pp_struct(rawbytes, rawdump=False, debug=False): pp_header = common_hdr.from_buffer(rawbytes[:4]) pp_ver = validate_pp(pp_header, len(rawbytes), rawdump) - if pp_ver == (7, 1): # Polaris + # Polaris aka RX470/RX480/RX570/RX580/RX590 + if pp_ver == (7, 1): gpugen = 'Polaris' from upp.atom_gen import pptable_v1_0 as pp_struct ctypes_strct = pp_struct.struct__ATOM_Tonga_POWERPLAYTABLE - elif pp_ver == (8, 1): # Vega 10 + # Vega 10 aka Vega 56/64 + elif pp_ver == (8, 1): gpugen = 'Vega 10' from upp.atom_gen import vega10_pptable as pp_struct ctypes_strct = pp_struct.struct__ATOM_Vega10_POWERPLAYTABLE - elif pp_ver == (11, 0): # Vega 20 aka Radeon 7 + # Vega 20 aka Radeon VII + elif pp_ver == (11, 0): gpugen = 'Vega 20' from upp.atom_gen import vega20_pptable as pp_struct ctypes_strct = pp_struct.struct__ATOM_VEGA20_POWERPLAYTABLE - elif pp_ver == (12, 0): # Navi 10, 14 + # Navi 10 aka RX5700/RX5600(XT,M), Navi 14 aka RX5500/RX5300(XT,M) + elif pp_ver == (12, 0): gpugen = 'Navi 10 or 14' from upp.atom_gen import smu_v11_0_navi10 as pp_struct ctypes_strct = pp_struct.struct_smu_11_0_powerplay_table - elif pp_ver == (15, 0): # Navi 21 - gpugen = 'Navi 21' - from upp.atom_gen import smu_v11_0_7_navi20 as pp_struct - ctypes_strct = pp_struct.struct_smu_11_0_7_powerplay_table - elif pp_ver == (16, 0): # Navi 22 - gpugen = 'Navi 22' + # Navi 21 (Sienna Cichlid) aka RX6900XT/RX6800(XT) + # Navi 22 (Navy Flounder) aka RX6700(XT)/RX6800M + # Navi 23 (Dimgrey Cavefish) aka RX6600(XT)/RX6600M + elif ((pp_ver[0] == 15 or pp_ver[0] == 16 or pp_ver[0] == 18) and + pp_ver[1] == 0): + gpugen = 'Navi 21 or 22 or 23' from upp.atom_gen import smu_v11_0_7_navi20 as pp_struct ctypes_strct = pp_struct.struct_smu_11_0_7_powerplay_table + # Navi 24? (Beige Goby?) aka RX6300(XT)? elif pp_ver is not None: msg = 'Can not decode PowerPlay table version {}.{}' print(msg.format(pp_ver[0], pp_ver[1])) diff --git a/test/AMD.RX6900.16384.201104.rom.rawdump b/test/AMD.RX6900.16384.201104.rom.rawdump index d1e605d..637f641 100644 --- a/test/AMD.RX6900.16384.201104.rom.rawdump +++ b/test/AMD.RX6900.16384.201104.rom.rawdump @@ -951,7 +951,7 @@ PowerPlay table rev 15.0 size 2470 bytes 0x08f8 (2296) b 00 Mem0Offset : 0 0x08f9 (2297) B 00 Padding_TelemetryMem0 : 0 0x08fa (2298) H 0000 Mem1MaxCurrent : 0 - 0x08fc (2300) b 00 Mem1Offset : 0 + 0x08fc (2300) B 00 Mem1Offset : 0 0x08fd (2301) B 00 Padding_TelemetryMem1 : 0 0x08fe (2302) I 00000000 MvddRatio : 0 0x0902 (2306) B 00 AcDcGpio : 0