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game_control.vhd.bak
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game_control.vhd.bak
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library ieee;
use ieee.std_logic_1164.all;
entity game_control is
port (
CLOCK_50 : in std_logic;
PS2_DAT : inout STD_LOGIC;
PS2_CLK : inout STD_LOGIC;
HEX5 : out std_logic_vector(6 downto 0);
HEX4 : out std_logic_vector(6 downto 0);
HEX3 : out std_logic_vector(6 downto 0);
HEX2 : out std_logic_vector(6 downto 0);
HEX1 : out std_logic_vector(6 downto 0);
HEX0 : out std_logic_vector(6 downto 0)
);
end game_control ;
architecture of game_control is
component kbd_alphanum is
port (
clk : in std_logic;
key_on : in std_logic_vector(2 downto 0);
key_code : in std_logic_vector(47 downto 0);
HEX1 : out std_logic_vector(6 downto 0); -- GFEDCBA
HEX0 : out std_logic_vector(6 downto 0) -- GFEDCBA
);
end component;
component kbdex_ctrl is
generic(
clkfreq : integer
);
port(
ps2_data : inout std_logic;
ps2_clk : inout std_logic;
clk : in std_logic;
en : in std_logic;
resetn : in std_logic;
lights : in std_logic_vector(2 downto 0);
key_on : out std_logic_vector(2 downto 0);
key_code : out std_logic_vector(47 downto 0)
);
end component;
component ram is
port (
Clock : in std_logic;
Address : in std_logic_vector(9 downto 0);
DataIn : in std_logic_vector(31 downto 0);
DataOut : out std_logic_vector(31 downto 0);
WrEn : in std_logic
);
end component;
component ascii_2_num is
port (key_pressed: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
numeric : OUT std_logic_vector (31 downto 0)
);
end component;
component bin2dec is
port (
);
signal key_on : std_logic_vector(2 downto 0);
signal key_code : std_logic_vector(47 downto 0);
signal key_pressed : std_logic_vector(7 downto 0);
signal key_number : std_logic_vector (31 downto 0);
signal p1, p2, p3, p4 :
begin
kbdex_ctrl_inst : kbdex_ctrl
generic map (
clkfreq => 50000
)
port map (
ps2_data => PS2_DAT,
ps2_clk => PS2_CLK,
clk => CLOCK_50,
en => '1',
resetn => '1',
lights => "000",
key_on => key_on,
key_code => key_code
);
kbd_alphanum_inst : kbd_alphanum
port map (
clk => CLOCK_50,
key_on => key_on,
key_code => key_code,
HEX1 => key_pressed(7 downto 4),
HEX0 => key_pressed(3 downto 0)
);
translate : ascii_2_num
port map (
key_pressed,
key_number
);
print : bin2dec
port map (
) ;
-- process
-- begin
-- wait until clock'event and clock = '1';
-- if reset = '1' then
-- next_state <= "000";
-- else
-- case state is
-- when "000" =>
-- addr <= "000000000";
-- save <= '1';
--
--
-- d_in <= key_number;
-- if key_on /= 0 then next_state <="001";
-- end if;
-- when "001" =>
-- addr <= "000000001";
-- save <= '1';
-- d_in <= key_number;
-- next_state <="001";
-- if key_on /= 0 then next_state <="010";
-- end if;
-- when "010" =>
-- addr <= "000000010";
-- save <= '1';
-- d_in <= key_number;
-- next_state <="001";
-- if key_on /= 0 then next_state <="011";
-- end if;
-- when "011" =>
-- if w = '1' then next_state <= "100";
-- else next_state <= "001";
-- end if;
-- when "100" =>
-- if w = '1' then next_state <= "000";
-- else next_state <= "011";
-- end if;
-- when others =>
-- if w = '1' then next_state <= "000";
-- else next_state <= "001";
-- end if;
-- end case;
-- end if;
-- end process;
--
end rtl;