diff --git a/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd b/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd
index 824672b..7491a42 100644
--- a/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd
+++ b/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd
@@ -33,6 +33,7 @@ entity TimingGtCoreWrapper is
       TPD_G             : time             := 1 ns;
       DISABLE_TIME_GT_G : boolean          := false;
       EXTREF_G          : boolean          := false;
+      AXI_CLK_FREQ_G    : real             := 156.25e6;
       AXIL_BASE_ADDR_G  : slv(31 downto 0);
       ADDR_BITS_G       : positive         := 22;
       GTY_DRP_OFFSET_G  : slv(31 downto 0) := x"00400000");
@@ -300,15 +301,17 @@ begin
          mAxiReadMasters     => axilReadMasters,
          mAxiReadSlaves      => axilReadSlaves);
 
-   U_AlignCheck : entity lcls_timing_core.GthRxAlignCheck
+   U_AlignCheck : entity surf.GtRxAlignCheck
       generic map (
-         TPD_G      => TPD_G,
-         GT_TYPE_G  => "GTYE4",
-         DRP_ADDR_G => AXI_CROSSBAR_MASTERS_CONFIG_C(1).baseAddr)
+         TPD_G          => TPD_G,
+         GT_TYPE_G      => "GTYE4",
+         AXI_CLK_FREQ_G => AXI_CLK_FREQ_G,
+         DRP_ADDR_G     => AXI_CROSSBAR_MASTERS_CONFIG_C(1).baseAddr)
       port map (
          -- Clock Monitoring
          txClk            => txoutclkb,
-         rxClk            => rxUsrClk,  -- Should maybe be rxUsrClk
+         rxClk            => rxUsrClk,
+         refClk           => axilClk,   -- Could probably also be stableClk
          -- GTH Status/Control Interface
          resetIn          => rxControl.reset,
          resetDone        => bypassdone,