diff --git a/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd b/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd
index 7491a42..070fcb4 100644
--- a/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd
+++ b/LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd
@@ -31,6 +31,7 @@ use unisim.vcomponents.all;
 entity TimingGtCoreWrapper is
    generic (
       TPD_G             : time             := 1 ns;
+      SIMULATION_G      : boolean          := false;
       DISABLE_TIME_GT_G : boolean          := false;
       EXTREF_G          : boolean          := false;
       AXI_CLK_FREQ_G    : real             := 156.25e6;
@@ -304,6 +305,7 @@ begin
    U_AlignCheck : entity surf.GtRxAlignCheck
       generic map (
          TPD_G          => TPD_G,
+         SIMULATION_G   => SIMULATION_G,
          GT_TYPE_G      => "GTYE4",
          AXI_CLK_FREQ_G => AXI_CLK_FREQ_G,
          DRP_ADDR_G     => AXI_CROSSBAR_MASTERS_CONFIG_C(1).baseAddr)