From 3b83ea2587df9ebd5501e02774debe2069104990 Mon Sep 17 00:00:00 2001
From: Larry Ruckman <ruckman@slac.stanford.edu>
Date: Thu, 8 Feb 2024 21:04:36 -0800
Subject: [PATCH] whitespace clean up

---
 LCLS-II/core/rtl/TimingDeserializer.vhd             | 4 ++--
 LCLS-II/core/rtl/TimingFrameRx.vhd                  | 2 +-
 LCLS-II/core/rtl/TimingRx.vhd                       | 2 +-
 LCLS-II/gthUltraScale+/rtl/TimingGthCoreWrapper.vhd | 2 +-
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/LCLS-II/core/rtl/TimingDeserializer.vhd b/LCLS-II/core/rtl/TimingDeserializer.vhd
index d6f4f9e1..babaf5dc 100644
--- a/LCLS-II/core/rtl/TimingDeserializer.vhd
+++ b/LCLS-II/core/rtl/TimingDeserializer.vhd
@@ -79,9 +79,9 @@ architecture TimingDeserializer of TimingDeserializer is
   signal r   : RegType := REG_INIT_C;
   signal rin : RegType;
   signal crc : slv(31 downto 0);
-   
+
 begin
-  
+
   fiducial <= r.fiducial;
   streams  <= r.streams;
   advance  <= r.advance;
diff --git a/LCLS-II/core/rtl/TimingFrameRx.vhd b/LCLS-II/core/rtl/TimingFrameRx.vhd
index 316ff73b..55df77f6 100644
--- a/LCLS-II/core/rtl/TimingFrameRx.vhd
+++ b/LCLS-II/core/rtl/TimingFrameRx.vhd
@@ -83,7 +83,7 @@ architecture rtl of TimingFrameRx is
    signal dframe  : DataArray;
    signal dstrobe : slv(15 downto 1);
    signal dvalid  : slv(15 downto 1);
-   
+
 begin
 
    delayRst <= rxRst or messageDelayRst or doverflow0;
diff --git a/LCLS-II/core/rtl/TimingRx.vhd b/LCLS-II/core/rtl/TimingRx.vhd
index 5756027c..2fed60e0 100644
--- a/LCLS-II/core/rtl/TimingRx.vhd
+++ b/LCLS-II/core/rtl/TimingRx.vhd
@@ -193,7 +193,7 @@ begin
             rxVersion           => rxVersion(1),
             staData             => staData (1));
    end generate;
-    
+
    axilComb : process (axilR, axilRst, axilReadMaster, axilRxLinkUp, axilStatusCounters12,
                        axilStatusCounters3, axilVersion, axilVsnErr, axilWriteMaster, rxStatusCount,
                        timingTSEvCntGray_o, txClkCntS) is
diff --git a/LCLS-II/gthUltraScale+/rtl/TimingGthCoreWrapper.vhd b/LCLS-II/gthUltraScale+/rtl/TimingGthCoreWrapper.vhd
index 436aecdd..8ba961aa 100644
--- a/LCLS-II/gthUltraScale+/rtl/TimingGthCoreWrapper.vhd
+++ b/LCLS-II/gthUltraScale+/rtl/TimingGthCoreWrapper.vhd
@@ -81,7 +81,7 @@ entity TimingGthCoreWrapper is
       txOutClk       : out sl;
 
       loopback : in slv(2 downto 0));
-   
+
 end entity TimingGthCoreWrapper;
 
 architecture rtl of TimingGthCoreWrapper is