Intro to verilog and staq.

[akataba]

I am new to verilog and staq. I am trying to synthesize and oracle that could add and multiply but writing a verilog file for example adding two different numbers does not seem

module top ( a, b, c );
  input a,b;
  output c;
  assign c = a + b;
endmodule

does not return an error but simply returns an empty gate on the other hand what I understand to be the right verilog file

module top ( a, b, c );
  input [3:0] a;
  inpit  [3:0 ] b;
  output [4:0] c;
  assign c = a + b;
endmodule

this returns an error
Get quantum circuits for adding and multiplying intergers should be possible right ?

[vsoftco]

@meamy any suggestions?

[meamy]

So the problem here is just that staq doesn't currently support integer arithmetic in verilog files. The subset of verilog which staq supports is fairly limited, corresponding to combinational logic using Boolean operators. Part of this is due to the fact that high-level, modular logic synthesis has a larger design space which makes it harder to reach the performance of human-designed logic, so it hasn't been a high priority and we just haven't gotten around to it yet.

For the time being, to compile an adder, what you would have to do is explicitly program or otherwise compile a (classical/irreversible) adder in verilog. Unfortunately a bit of a pain, but I believe there are some tools out there for compiling higher-level logic to combinational verilog code --- though such tools seem to be escaping me at the moment...